diff options
Diffstat (limited to 'src')
38 files changed, 2979 insertions, 1469 deletions
diff --git a/src/include/usr/hwpf/plat/fapiPlatAttributeService.H b/src/include/usr/hwpf/plat/fapiPlatAttributeService.H index b2d3a9b9d..e08b79629 100644 --- a/src/include/usr/hwpf/plat/fapiPlatAttributeService.H +++ b/src/include/usr/hwpf/plat/fapiPlatAttributeService.H @@ -398,7 +398,7 @@ fapi::ReturnCode fapiPlatGetProcNxMmioBarSize ( */ fapi::ReturnCode fapiPlatGetProcPcieBarEnable ( const fapi::Target * i_pTarget, - uint8_t (&o_pcieBarEnable) [3][3] ); + uint8_t (&o_pcieBarEnable) [4][3] ); /** * @brief This function is called by the FAPI_ATTR_GET macro when getting * ATTR_PROC_PCIE_BAR_BASE_ADDR_ @@ -412,7 +412,7 @@ fapi::ReturnCode fapiPlatGetProcPcieBarEnable ( */ fapi::ReturnCode fapiPlatGetProcPcieBarBaseAddr ( const fapi::Target * i_pTarget, - uint64_t (&o_pcieBarBase) [3][3] ); + uint64_t (&o_pcieBarBase) [4][3] ); /** * @brief This function is called by the FAPI_ATTR_GET macro when getting * ATTR_PROC_PCIE_BAR_SIZE @@ -426,7 +426,7 @@ fapi::ReturnCode fapiPlatGetProcPcieBarBaseAddr ( */ fapi::ReturnCode fapiPlatGetProcPcieBarSize ( const fapi::Target * i_pTarget, - uint64_t (&o_pcieBarSize) [3][3] ); + uint64_t (&o_pcieBarSize) [4][3] ); /** * @brief This function is called by the FAPI_ATTR_GET macro when getting diff --git a/src/usr/hwpf/fapi/fapiCreateL3DeltaVals.pl b/src/usr/hwpf/fapi/fapiCreateL3DeltaVals.pl index 91fca0986..3ec91df6d 100755 --- a/src/usr/hwpf/fapi/fapiCreateL3DeltaVals.pl +++ b/src/usr/hwpf/fapi/fapiCreateL3DeltaVals.pl @@ -6,7 +6,9 @@ # # OpenPOWER HostBoot Project # -# COPYRIGHT International Business Machines Corp. 2013,2014 +# Contributors Listed Below - COPYRIGHT 2013,2015 +# [+] International Business Machines Corp. +# # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -21,7 +23,7 @@ # permissions and limitations under the License. # # IBM_PROLOG_END_TAG -# $Id: fapiCreateL3DeltaVals.pl,v 1.3 2014/03/20 16:25:04 whs Exp $ +# $Id: fapiCreateL3DeltaVals.pl,v 1.4 2014/12/17 23:43:11 thi Exp $ # # Purpose: This perl script will parse HWP Attribute XML files # and add attribute information to a file called fapiL3DeltaDataAttr.H @@ -36,6 +38,8 @@ # Flag Track# Userid Date Description # ---- -------- -------- -------- ----------- # 873826 dpeterso 09/16/13 Based on fapiCreatePllRingAttrVals.pl +# 920311 whs 03/23/14 PROC_EX_FUNC_L3_LENGTH from +# mrw to hwp accessor # # # End Change Log ****************************************************** @@ -144,7 +148,7 @@ foreach $ringAttrFile (@fileList) print OUTFILE "*/\n"; while (<FILE>) - { + { # Each section we are interested in begins with ===BEGIN and ends with ===END if (/\===BEGIN/../\===END/) { # Keep track of how many instances we have in the file and reset some sub-counters. @@ -152,7 +156,7 @@ foreach $ringAttrFile (@fileList) { $count++; $dataCount = 0; - } + } # Store select value in array if ($_ =~ m"^#SELECT=(\d)") @@ -162,7 +166,7 @@ foreach $ringAttrFile (@fileList) if ($_ =~ m"^ATTR_PROC_EX_FUNC_L3_LENGTH u32\s+(\d+)\s+") { $lengthVal = $1; - + if ($selectVal != ($count-1)) { die "$ProgName ERROR: Select value in file $ringAttrFile does not appear to be sequential. There may be a script problem or a corrupted ring attribute file.\n"; @@ -205,7 +209,7 @@ foreach $ringAttrFile (@fileList) $dataArrayString = $dataArrayString . $2 . ", "; # If this is the last entry in the array (delta data size = 64 if ($dataCount eq 64) - { + { print OUTFILE " $dataArrayString\n"; print OUTFILE " }, // ATTR_PROC_EX_FUNC_L3_DELTA_DATA\n"; print OUTFILE "},\n"; diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C index faee55b8e..00c98bf70 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp.C,v 1.17 2014/08/05 15:13:27 kahnevan Exp $ +// $Id: proc_build_smp.C,v 1.19 2014/11/18 17:41:03 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp.C,v $ //------------------------------------------------------------------------------ // *| @@ -658,6 +658,8 @@ fapi::ReturnCode proc_build_smp_process_chip( { // return code fapi::ReturnCode rc; + uint8_t nv_present; + uint8_t dual_capp_present; uint8_t pcie_enabled; uint8_t nx_enabled; uint8_t x_enabled; @@ -675,6 +677,41 @@ fapi::ReturnCode proc_build_smp_process_chip( FAPI_DBG("proc_build_smp_process_chip: Target: %s", io_smp_chip.chip->this_chip.toEcmdString()); + // get NV link presence attribute + FAPI_DBG("proc_build_smp_process_chip: Querying NV chiplet/link feature attribute"); + rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_NV_PRESENT, + &(io_smp_chip.chip->this_chip), + nv_present); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_process_chip: Error querying ATTR_CHIP_EC_FEATURE_NV_PRESENT"); + break; + } + io_smp_chip.nv_present = (nv_present != 0); + + // get dual CAPP presence attribute + FAPI_DBG("proc_build_smp_process_chip: Querying dual CAPP feature attribute"); + rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_DUAL_CAPP_PRESENT, + &(io_smp_chip.chip->this_chip), + dual_capp_present); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_process_chip: Error querying ATTR_CHIP_EC_FEATURE_DUAL_CAPP_PRESENT"); + break; + } + io_smp_chip.dual_capp_present = (dual_capp_present != 0); + + // get PCIe PHB configuration + FAPI_DBG("proc_build_smp_process_chip: Querying PCIe PHB configuration"); + rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_NUM_PHB, + &(io_smp_chip.chip->this_chip), + io_smp_chip.num_phb); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_process_chip: Error querying ATTR_PROC_PCIE_NUM_PHB"); + break; + } + // get PCIe/DSMP mux attributes FAPI_DBG("proc_build_smp_process_chip: Querying PCIe/DSMP mux attribute"); rc = proc_fab_smp_get_pcie_dsmp_mux_attrs(&(io_smp_chip.chip->this_chip), @@ -751,11 +788,14 @@ fapi::ReturnCode proc_build_smp_process_chip( io_smp_chip.x_enabled = (x_enabled == fapi::ENUM_ATTR_PROC_X_ENABLE_ENABLE); + // NV link replaces A & F link support io_smp_chip.a_enabled = - (a_enabled == fapi::ENUM_ATTR_PROC_A_ENABLE_ENABLE); + ((a_enabled == fapi::ENUM_ATTR_PROC_A_ENABLE_ENABLE) && + !nv_present); io_smp_chip.pcie_enabled = - (pcie_enabled == fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE); + ((pcie_enabled == fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE) && + !nv_present); } while(0); diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H index b0fe10d1d..c06efa782 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp.H,v 1.14 2014/02/23 21:41:06 jmcgill Exp $ +// $Id: proc_build_smp.H,v 1.16 2014/11/18 17:41:03 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp.H,v $ //------------------------------------------------------------------------------ // *| @@ -129,6 +129,9 @@ struct proc_build_smp_chip proc_build_smp_proc_chip* chip; // chip properties/attributes: + bool nv_present; + bool dual_capp_present; + uint8_t num_phb; // fabric chip/node ID proc_fab_smp_chip_id chip_id; proc_fab_smp_node_id node_id; diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C index fa8b1d15c..4a46449d2 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_adu.C,v 1.9 2014/02/23 21:41:06 jmcgill Exp $ +// $Id: proc_build_smp_adu.C,v 1.11 2014/11/18 17:41:03 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_adu.C,v $ //------------------------------------------------------------------------------ // *| @@ -425,6 +425,7 @@ fapi::ReturnCode proc_build_smp_adu_check_status( std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator n_iter; std::map<proc_fab_smp_chip_id, proc_build_smp_chip>::iterator p_iter; std::vector<fapi::Target*> targets_to_collect; + std::vector<bool> nv_present; ecmdDataBufferBase scom_data(64); ecmdDataBufferBase chip_ids; ecmdDataBufferBase ffdc_reg_data[PROC_BUILD_SMP_FFDC_NUM_REGS]; @@ -442,6 +443,7 @@ fapi::ReturnCode proc_build_smp_adu_check_status( if (i_dump_all_targets || (p_iter->second.chip->this_chip == i_target)) { + nv_present.push_back(p_iter->second.nv_present); targets_to_collect.push_back(&(p_iter->second.chip->this_chip)); } } @@ -455,9 +457,10 @@ fapi::ReturnCode proc_build_smp_adu_check_status( } // extract FFDC data + std::vector<bool>::iterator n = nv_present.begin(); for (std::vector<fapi::Target*>::iterator t = targets_to_collect.begin(); t != targets_to_collect.end(); - t++) + t++, n++) { // log node/chip ID for (n_iter = i_smp.nodes.begin(); @@ -481,11 +484,23 @@ fapi::ReturnCode proc_build_smp_adu_check_status( // collect SCOM data for (uint8_t i = 0; i < PROC_BUILD_SMP_FFDC_NUM_REGS; i++) { - rc = fapiGetScom(*(*t), PROC_BUILD_SMP_FFDC_REGS[i], scom_data); - if (!rc.ok()) + // skip A / F link registers if NV link logic is present + if ((*n) && + ((i == static_cast<uint8_t>(A_GP0_DATA_INDEX)) || + (i == static_cast<uint8_t>(ADU_IOS_LINK_EN_DATA_INDEX)) || + (i == static_cast<uint8_t>(PB_A_MODE_DATA_INDEX)))) + { + rc_ecmd |= scom_data.flushTo1(); + } + else { - ffdc_scom_error = true; + rc = fapiGetScom(*(*t), PROC_BUILD_SMP_FFDC_REGS[i], scom_data); + if (!rc.ok()) + { + ffdc_scom_error = true; + } } + rc_ecmd |= scom_data.extractPreserve( ffdc_reg_data[i], 0, 64, diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C index 0e2714465..99a0aa5d7 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_epsilon.C,v 1.11 2014/03/06 17:42:24 jmcgill Exp $ +// $Id: proc_build_smp_epsilon.C,v 1.12 2014/11/18 17:41:03 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_epsilon.C,v $ //------------------------------------------------------------------------------ // *| @@ -1001,8 +1001,9 @@ fapi::ReturnCode proc_build_smp_set_epsilons_hca( //------------------------------------------------------------------------------ // function: set CAPP unit epsilon registers -// parameters: i_target => chip target -// i_eps_cfg => system epsilon configuration structure +// parameters: i_target => chip target +// i_dual_capp_present => indicate presence of 2nd CAPP unit +// i_eps_cfg => system epsilon configuration structure // returns: ECMD_SUCCESS if all settings are programmed correctly, // RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR if any target value is out of // range given underlying HW storage, @@ -1010,6 +1011,7 @@ fapi::ReturnCode proc_build_smp_set_epsilons_hca( //------------------------------------------------------------------------------ fapi::ReturnCode proc_build_smp_set_epsilons_capp( fapi::Target & i_target, + const bool i_dual_capp_present, const proc_build_smp_eps_cfg & i_eps_cfg) { fapi::ReturnCode rc; @@ -1114,6 +1116,21 @@ fapi::ReturnCode proc_build_smp_set_epsilons_capp( break; } + if (i_dual_capp_present) + { + rc = fapiPutScomUnderMask(i_target, + CAPP1_APC_MASTER_PB_CTL_0x02013198, + data, + mask); + + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_set_epsilons_capp: fapiPutScomUnderMask error (CAPP1_APC_MASTER_PB_CTL_0x02013198)"); + break; + } + } + + // program read epsilon register based on unit implementation rc_ecmd = data.flushTo0(); rc_ecmd |= mask.flushTo0(); @@ -1184,6 +1201,20 @@ fapi::ReturnCode proc_build_smp_set_epsilons_capp( break; } + if (i_dual_capp_present) + { + rc = fapiPutScomUnderMask(i_target, + CAPP1_CXA_SNOOP_CTL_0x0201319B, + data, + mask); + + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_set_epsilons_capp: fapiPutScomUnderMask error (CAPP1_CXA_SNOOP_CTL_0x0201319B)"); + break; + } + } + } while(0); // mark function exit @@ -1547,7 +1578,7 @@ fapi::ReturnCode proc_build_smp_set_epsilons( } // CAPP - rc = proc_build_smp_set_epsilons_capp(target, i_smp.eps_cfg); + rc = proc_build_smp_set_epsilons_capp(target, p_iter->second.dual_capp_present, i_smp.eps_cfg); if (!rc.ok()) { FAPI_ERR("proc_build_smp_set_epsilons: Error from proc_build_smp_set_epsilons_capp"); diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C index 1e8678de1..96f41b88f 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_fbc_ab.C,v 1.11 2014/02/26 18:12:57 jmcgill Exp $ +// $Id: proc_build_smp_fbc_ab.C,v 1.13 2014/11/18 17:41:03 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_ab.C,v $ //------------------------------------------------------------------------------ // *| @@ -75,7 +75,9 @@ const uint32_t PB_HP_MODE_A_CMD_RATE_MAX_VALUE = 0x7F; const uint32_t PB_HP_MODE_A_GATHER_ENABLE_BIT = 32; const uint32_t PB_HP_MODE_A_GATHER_DLY_CNT_START_BIT = 33; const uint32_t PB_HP_MODE_A_GATHER_DLY_CNT_END_BIT = 37; -const uint32_t PB_HP_MODE_GATHER_ENABLE_BIT = 40; +const uint32_t PB_HP_MODE_PCIE3_NOT_DSMP_BIT = 40; +const uint32_t PB_HP_MODE_GATHER_ENABLE_BIT_PCIE3_PRESENT = 41; +const uint32_t PB_HP_MODE_GATHER_ENABLE_BIT_PCIE3_NOT_PRESENT = 40; const uint32_t PB_HP_MODE_F_AGGREGATE_BIT = 55; const uint32_t PB_HP_MODE_F_CMD_RATE_START_BIT = 56; const uint32_t PB_HP_MODE_F_CMD_RATE_END_BIT = 63; @@ -112,6 +114,7 @@ const uint32_t PB_HPX_MODE_X_GATHER_ENABLE_BIT = 32; const uint32_t PB_HPX_MODE_X_GATHER_DLY_CNT_START_BIT = 33; const uint32_t PB_HPX_MODE_X_GATHER_DLY_CNT_END_BIT = 37; const uint32_t PB_HPX_MODE_X_ONNODE_12QUEUES_BIT = 38; +const uint32_t PB_HPX_MODE_GROUP_EQ_CHIP_BIT = 39; const uint32_t PB_HPX_MODE_X_CMD_RATE_START_BIT = 56; const uint32_t PB_HPX_MODE_X_CMD_RATE_END_BIT = 63; const uint32_t PB_HPX_MODE_X_CMD_RATE_MIN_VALUE = 1; @@ -1466,9 +1469,21 @@ fapi::ReturnCode proc_build_smp_set_pb_hp_mode( (PB_HP_MODE_A_GATHER_DLY_CNT_END_BIT- PB_HP_MODE_A_GATHER_DLY_CNT_START_BIT+1)); - // pb_cfg_gather_enable - rc_ecmd |= data.writeBit(PB_HP_MODE_GATHER_ENABLE_BIT, - PB_HP_MODE_GATHER_ENABLE?1:0); + if (i_smp_chip.num_phb > 3) + { + // pb_cfg_p3_x8tok + rc_ecmd |= data.setBit(PB_HP_MODE_PCIE3_NOT_DSMP_BIT); + + // pb_cfg_gather_enable + rc_ecmd |= data.writeBit(PB_HP_MODE_GATHER_ENABLE_BIT_PCIE3_PRESENT, + PB_HP_MODE_GATHER_ENABLE?1:0); + } + else + { + // pb_cfg_gather_enable + rc_ecmd |= data.writeBit(PB_HP_MODE_GATHER_ENABLE_BIT_PCIE3_NOT_PRESENT, + PB_HP_MODE_GATHER_ENABLE?1:0); + } // pb_cfg_f_aggregate rc_ecmd |= data.writeBit(PB_HP_MODE_F_AGGREGATE_BIT, @@ -1675,6 +1690,10 @@ fapi::ReturnCode proc_build_smp_set_pb_hpx_mode( rc_ecmd |= data.writeBit(PB_HPX_MODE_X_ONNODE_12QUEUES_BIT, PB_HPX_MODE_X_ONNODE_12QUEUES?1:0); + // pb_cfg_group_eq_chip + rc_ecmd |= data.writeBit(PB_HPX_MODE_GROUP_EQ_CHIP_BIT, + i_smp_chip.nv_present?1:0); + // pb_cfg_x_cmd_rate rc_ecmd |= data.insertFromRight( x_cmd_rate, diff --git a/src/usr/hwpf/hwp/build_winkle_images/proc_mailbox_utils/p8_mailbox_utils.C b/src/usr/hwpf/hwp/build_winkle_images/proc_mailbox_utils/p8_mailbox_utils.C index f5ee1ba8f..b43674a48 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/proc_mailbox_utils/p8_mailbox_utils.C +++ b/src/usr/hwpf/hwp/build_winkle_images/proc_mailbox_utils/p8_mailbox_utils.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2013,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -23,7 +23,7 @@ /* */ /* IBM_PROLOG_END_TAG */ // -*- mode: C++; c-file-style: "linux"; -*- -// $Id: p8_mailbox_utils.C,v 1.5 2014/08/05 15:14:03 kahnevan Exp $ +// $Id: p8_mailbox_utils.C,v 1.7 2014/11/18 17:35:56 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_mailbox_utils.C,v $ //------------------------------------------------------------------------------ // *| @@ -769,19 +769,18 @@ fapi::ReturnCode p8_mailbox_utils_get_mbox4( const fapi::Target &i_target, uint3 } FAPI_INF( "ATTR_MNFG_FLAGS => %016llX", l_mnfg_flags); - // get chip type - // TODO RTC 102992 - fapi::ATTR_NAME_Type l_chip_type; - l_fapirc = FAPI_ATTR_GET_PRIVILEGED(ATTR_NAME, &i_target, l_chip_type); + // set legacy node ID valid bit + uint8_t set_legacy_node_id_valid = 0; + l_fapirc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_SET_LEGACY_NODE_ID_VALID_MBOX_BIT, &i_target, set_legacy_node_id_valid); if (l_fapirc) { - FAPI_ERR("fapiGetAttribute (Privildged) of ATTR_NAME failed"); + FAPI_ERR("fapiGetAttribute of ATTR_CHIP_EC_FEATURE_SET_LEGACY_NODE_ID_VALID_MBOX_BIT failed"); break; - } + } if (((l_mnfg_flags & fapi::ENUM_ATTR_MNFG_FLAGS_MNFG_BRAZOS_WRAP_CONFIG) == fapi::ENUM_ATTR_MNFG_FLAGS_MNFG_BRAZOS_WRAP_CONFIG) || - (l_chip_type == fapi::ENUM_ATTR_NAME_MURANO)) + (set_legacy_node_id_valid != 0)) { o_set_data |= 1 << (sizeof(o_set_data)*8 - WRAP_TEST_BIT - 1); } diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C index dd560543d..fd008021b 100644 --- a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C +++ b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_pcie_config.C,v 1.9 2014/08/27 14:53:48 jmcgill Exp $ +// $Id: proc_pcie_config.C,v 1.10 2014/11/18 17:41:59 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_config.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -97,12 +97,14 @@ fapi::ReturnCode proc_pcie_config_pbcq( // clear FIR/WOF // initialize FIR action settings // reset FIR masks -// parameters: i_target => processor chip target +// parameters: i_target => processor chip target +// i_num_phb => number of PHB units // returns: FAPI_RC_SUCCESS if all actions are successful, // else error //------------------------------------------------------------------------------ fapi::ReturnCode proc_pcie_config_pbcq_fir( - const fapi::Target & i_target) + const fapi::Target & i_target, + uint8_t i_num_phb) { fapi::ReturnCode rc; uint32_t rc_ecmd = 0; @@ -113,7 +115,7 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir( FAPI_INF("proc_pcie_config_pbcq_fir: Start"); // loop over all PHBs - for (size_t i = 0; i < PROC_PCIE_CONFIG_NUM_PHB; i++) + for (size_t i = 0; i < i_num_phb; i++) { // clear FIR rc_ecmd |= data.flushTo0(); @@ -133,7 +135,7 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir( i, PROC_PCIE_CONFIG_PCIE_NEST_FIR[i]); break; } - + // clear FIR WOF rc = fapiPutScom(i_target, PROC_PCIE_CONFIG_PCIE_NEST_FIR_WOF[i], @@ -144,7 +146,7 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir( i, PROC_PCIE_CONFIG_PCIE_NEST_FIR_WOF[i]); break; } - + // set action0 rc_ecmd |= data.setDoubleWord(0, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0_VAL); if (rc_ecmd) @@ -154,7 +156,7 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir( rc.setEcmdError(rc_ecmd); break; } - + rc = fapiPutScom(i_target, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0[i], data); @@ -164,7 +166,7 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir( i, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0[i]); break; } - + // set action1 rc_ecmd |= data.setDoubleWord(0, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1_VAL); if (rc_ecmd) @@ -174,7 +176,7 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir( rc.setEcmdError(rc_ecmd); break; } - + rc = fapiPutScom(i_target, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1[i], data); @@ -184,7 +186,7 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir( i, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1[i]); break; } - + // set mask rc_ecmd |= data.setDoubleWord(0, PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK_VAL); if (rc_ecmd) @@ -194,7 +196,7 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir( rc.setEcmdError(rc_ecmd); break; } - + rc = fapiPutScom(i_target, PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK[i], data); @@ -218,6 +220,7 @@ fapi::ReturnCode proc_pcie_config( { fapi::ReturnCode rc; uint8_t pcie_enabled; + uint8_t num_phb; // mark HWP entry FAPI_INF("proc_pcie_config: Start"); @@ -247,6 +250,16 @@ fapi::ReturnCode proc_pcie_config( // atttribute is set) if (pcie_enabled == fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE) { + // determine PHB configuration + rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_NUM_PHB, + &i_target, + num_phb); + if (!rc.ok()) + { + FAPI_ERR("proc_pcie_config: Error from FAPI_ATTR_GET (ATTR_PROC_PCIE_NUM_PHB)"); + break; + } + rc = proc_pcie_config_pbcq(i_target); if (!rc.ok()) { @@ -254,7 +267,7 @@ fapi::ReturnCode proc_pcie_config( break; } - rc = proc_pcie_config_pbcq_fir(i_target); + rc = proc_pcie_config_pbcq_fir(i_target, num_phb); if (!rc.ok()) { FAPI_ERR("proc_pcie_config: Error from proc_pcie_config_pbcq_fir"); diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H index 1ab683f2f..564471d99 100644 --- a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H +++ b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_pcie_config.H,v 1.4 2014/02/03 15:58:53 jmcgill Exp $ +// $Id: proc_pcie_config.H,v 1.5 2014/11/18 17:41:59 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_config.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -57,41 +57,46 @@ const char * const PROC_PCIE_CONFIG_PHASE2_IF = "p8.pe.phase2.scom.if"; // PCIe physical constants -const uint8_t PROC_PCIE_CONFIG_NUM_PHB = 3; +const uint8_t PROC_PCIE_CONFIG_NUM_PHB = 4; const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR[PROC_PCIE_CONFIG_NUM_PHB] = { PCIE0_FIR_0x02012000, PCIE1_FIR_0x02012400, - PCIE2_FIR_0x02012800 + PCIE2_FIR_0x02012800, + PCIE3_FIR_0x02012C00 }; const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_WOF[PROC_PCIE_CONFIG_NUM_PHB] = { PCIE0_FIR_WOF_0x02012008, PCIE1_FIR_WOF_0x02012408, - PCIE2_FIR_WOF_0x02012808 + PCIE2_FIR_WOF_0x02012808, + PCIE3_FIR_WOF_0x02012C08 }; const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0[PROC_PCIE_CONFIG_NUM_PHB] = { PCIE0_FIR_ACTION0_0x02012006, PCIE1_FIR_ACTION0_0x02012406, - PCIE2_FIR_ACTION0_0x02012806 + PCIE2_FIR_ACTION0_0x02012806, + PCIE3_FIR_ACTION0_0x02012C06 }; const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1[PROC_PCIE_CONFIG_NUM_PHB] = { PCIE0_FIR_ACTION1_0x02012007, PCIE1_FIR_ACTION1_0x02012407, - PCIE2_FIR_ACTION1_0x02012807 + PCIE2_FIR_ACTION1_0x02012807, + PCIE3_FIR_ACTION1_0x02012C07 }; const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK[PROC_PCIE_CONFIG_NUM_PHB] = { PCIE0_FIR_MASK_0x02012003, PCIE1_FIR_MASK_0x02012403, - PCIE2_FIR_MASK_0x02012803 + PCIE2_FIR_MASK_0x02012803, + PCIE3_FIR_MASK_0x02012C03 }; const uint64_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0_VAL = 0x5B0F819000000000ULL; diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C index 3d2148aa5..a4e986408 100644 --- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_setup_bars.C,v 1.24 2014/08/05 20:43:38 jmcgill Exp $ +// $Id: proc_setup_bars.C,v 1.25 2014/11/18 17:43:18 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars.C,v $ //------------------------------------------------------------------------------ // *| @@ -948,6 +948,17 @@ fapi::ReturnCode proc_setup_bars_process_chip( FAPI_DBG("proc_setup_bars_process_chip: Target: %s", io_smp_chip.chip->this_chip.toEcmdString()); + // determine number of PHBs + FAPI_DBG("proc_setup_bars_process_chip: Querying PHB configuration"); + rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_NUM_PHB, + &(io_smp_chip.chip->this_chip), + io_smp_chip.num_phb); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_PROC_PCIE_NUM_PHB"); + break; + } + // get PCIe/DSMP mux attributes FAPI_DBG("proc_setup_bars_process_chip: Querying PCIe/DSMP mux attribute"); rc = proc_fab_smp_get_pcie_dsmp_mux_attrs(&(io_smp_chip.chip->this_chip), @@ -1469,6 +1480,7 @@ fapi::ReturnCode proc_setup_bars_l3_write_local_chip_memory_bar_attr( // function: wrapper function to write PCIe BARs specific to enabled local // chip non-mirrored/mirrored memory ranges // parameters: i_target => chip target +// i_num_phb => number of PHBs // i_non_mirrored_range => structure representing chip non-mirrored // address range // i_mirrored_range => structure representing chip mirrored @@ -1478,6 +1490,7 @@ fapi::ReturnCode proc_setup_bars_l3_write_local_chip_memory_bar_attr( //------------------------------------------------------------------------------ fapi::ReturnCode proc_setup_bars_pcie_write_local_chip_memory_bars( const fapi::Target& i_target, + const uint8_t i_num_phb, const proc_setup_bars_addr_range& i_non_mirrored_range, const proc_setup_bars_addr_range& i_mirrored_range) { @@ -1487,7 +1500,7 @@ fapi::ReturnCode proc_setup_bars_pcie_write_local_chip_memory_bars( FAPI_DBG("proc_setup_bars_pcie_write_local_chip_memory_bars: Start"); // loop over all units for (uint8_t u = 0; - u < PROC_SETUP_BARS_PCIE_NUM_UNITS; + u < i_num_phb; u++) { if (i_non_mirrored_range.enabled) @@ -1677,6 +1690,7 @@ fapi::ReturnCode proc_setup_bars_l3_write_local_node_memory_bar_attr( // function: wrapper function to write PCIe BARs specific to enabled local // node non-mirrored/mirrored memory ranges // parameters: i_target => chip target +// i_num_phb => number of PHBs // i_non_mirrored_range => structure representing node non-mirrored // address range // i_mirrored_range => structure representing node mirrored @@ -1686,6 +1700,7 @@ fapi::ReturnCode proc_setup_bars_l3_write_local_node_memory_bar_attr( //------------------------------------------------------------------------------ fapi::ReturnCode proc_setup_bars_pcie_write_local_node_memory_bars( const fapi::Target& i_target, + const uint8_t i_num_phb, const proc_setup_bars_addr_range& i_non_mirrored_range, const proc_setup_bars_addr_range& i_mirrored_range) { @@ -1695,7 +1710,7 @@ fapi::ReturnCode proc_setup_bars_pcie_write_local_node_memory_bars( FAPI_DBG("proc_setup_bars_pcie_write_local_node_memory_bars: Start"); // loop over all units for (uint8_t u = 0; - u < PROC_SETUP_BARS_PCIE_NUM_UNITS; + u < i_num_phb; u++) { if (i_non_mirrored_range.enabled) @@ -1740,6 +1755,7 @@ fapi::ReturnCode proc_setup_bars_pcie_write_local_node_memory_bars( // chip near/far foreign memory ranges // NOTE: only links which are marked for processing will be acted on // parameters: i_target => chip target +// i_num_phb => number of PHBs // i_process_links => array of boolean values dictating which // links should be acted on (one per link) // i_foreign_near_ranges => array of structures representing @@ -1751,6 +1767,7 @@ fapi::ReturnCode proc_setup_bars_pcie_write_local_node_memory_bars( //------------------------------------------------------------------------------ fapi::ReturnCode proc_setup_bars_pcie_write_foreign_memory_bars( const fapi::Target& i_target, + const uint8_t i_num_phb, const bool i_process_links[PROC_FAB_SMP_NUM_F_LINKS], const proc_setup_bars_addr_range i_foreign_near_ranges[PROC_FAB_SMP_NUM_F_LINKS], const proc_setup_bars_addr_range i_foreign_far_ranges[PROC_FAB_SMP_NUM_F_LINKS]) @@ -1762,7 +1779,7 @@ fapi::ReturnCode proc_setup_bars_pcie_write_foreign_memory_bars( // loop over all units for (uint8_t u = 0; - (u < PROC_SETUP_BARS_PCIE_NUM_UNITS) && (rc.ok()); + (u < i_num_phb) && (rc.ok()); u++) { // process ranges @@ -1811,6 +1828,7 @@ fapi::ReturnCode proc_setup_bars_pcie_write_foreign_memory_bars( //------------------------------------------------------------------------------ // function: wrapper function to write enabled PCIe IO BARs // parameters: i_target => chip target +// i_num_phb => number of PHBs // io_addr_ranges => 2D array of address range structures // encapsulating attribute values // (first dimension = unit, second dimension = @@ -1821,6 +1839,7 @@ fapi::ReturnCode proc_setup_bars_pcie_write_foreign_memory_bars( //------------------------------------------------------------------------------ fapi::ReturnCode proc_setup_bars_pcie_write_io_bar_regs( const fapi::Target& i_target, + const uint8_t i_num_phb, const proc_setup_bars_addr_range addr_ranges[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT]) { // return code @@ -1830,7 +1849,7 @@ fapi::ReturnCode proc_setup_bars_pcie_write_io_bar_regs( FAPI_DBG("proc_setup_bars_pcie_write_io_bar_regs: Start"); // loop over all units for (uint8_t u = 0; - u < PROC_SETUP_BARS_PCIE_NUM_UNITS; + u < i_num_phb; u++) { // enable bit/mask bit per range @@ -2040,6 +2059,15 @@ fapi::ReturnCode proc_setup_bars_pcie_write_io_bar_regs( // PCIE2 IO BAR2 (PCIE2_IO_BAR2_0x02012842) // PCIE2 IO BAR Enable (PCIE2_IO_BAR_EN_0x02012845) // +// PCIE3 Nodal Non-Mirrored BAR (PCIE3_NODAL_BAR0_0x02012C10) +// PCIE3 Nodal Mirrored BAR (PCIE3_NODAL_BAR1_0x02012C11) +// PCIE3 IO BAR0 (PCIE3_IO_BAR0_0x02012C40) +// PCIE3 IO BAR0 Mask (PCIE3_IO_MASK0_0x02012C43) +// PCIE3 IO BAR1 (PCIE3_IO_BAR1_0x02012C41) +// PCIE3 IO BAR1 Mask (PCIE3_IO_MASK1_0x02012C44) +// PCIE3 IO BAR2 (PCIE3_IO_BAR2_0x02012C42) +// PCIE3 IO BAR Enable (PCIE3_IO_BAR_EN_0x02012C45) +// //------------------------------------------------------------------------------ fapi::ReturnCode proc_setup_bars_write_local_chip_region_bars( @@ -2346,6 +2374,7 @@ proc_setup_bars_write_local_chip_region_bars( { rc = proc_setup_bars_pcie_write_local_chip_memory_bars( i_smp_chip.chip->this_chip, + i_smp_chip.num_phb, i_smp_chip.non_mirrored_range, i_smp_chip.mirrored_range); if (!rc.ok()) @@ -2360,6 +2389,7 @@ proc_setup_bars_write_local_chip_region_bars( { rc = proc_setup_bars_pcie_write_io_bar_regs( i_smp_chip.chip->this_chip, + i_smp_chip.num_phb, i_smp_chip.pcie_ranges); if (!rc.ok()) { @@ -2405,6 +2435,9 @@ proc_setup_bars_write_local_chip_region_bars( // PCIE2 Group Non-Mirrored BAR (PCIE2_GROUP_BAR0_0x02012812) // PCIE2 Group Mirrored BAR (PCIE2_GROUP_BAR1_0x02012813) // +// PCIE3 Group Non-Mirrored BAR (PCIE3_GROUP_BAR0_0x02012C12) +// PCIE3 Group Mirrored BAR (PCIE3_GROUP_BAR1_0x02012C13) +// //------------------------------------------------------------------------------ fapi::ReturnCode proc_setup_bars_write_local_node_region_bars( @@ -2511,6 +2544,7 @@ proc_setup_bars_write_local_node_region_bars( { rc = proc_setup_bars_pcie_write_local_node_memory_bars( i_smp_chip.chip->this_chip, + i_smp_chip.num_phb, i_smp_node.non_mirrored_range, i_smp_node.mirrored_range); if (!rc.ok()) @@ -2718,11 +2752,16 @@ proc_setup_bars_write_remote_node_region_bars( // PCIE1 F1 Near BAR (PCIE1_NEAR_BAR_F1_0x02012416) // PCIE1 F1 Far BAR (PCIE1_FAR_BAR_F1_0x02012417) // -// PCIE2 F0 Near BAR (PCIE2_NEAR_BAR_F0_0x02012484) +// PCIE2 F0 Near BAR (PCIE2_NEAR_BAR_F0_0x02012814) // PCIE2 F0 Far BAR (PCIE2_FAR_BAR_F0_0x02012815) // PCIE2 F1 Near BAR (PCIE2_NEAR_BAR_F1_0x02012816) // PCIE2 F1 Far BAR (PCIE2_FAR_BAR_F1_0x02012817) // +// PCIE3 F0 Near BAR (PCIE3_NEAR_BAR_F0_0x02012C14) +// PCIE3 F0 Far BAR (PCIE3_FAR_BAR_F0_0x02012C15) +// PCIE3 F1 Near BAR (PCIE3_NEAR_BAR_F1_0x02012C16) +// PCIE3 F1 Far BAR (PCIE3_FAR_BAR_F1_0x02012C17) +// //------------------------------------------------------------------------------ fapi::ReturnCode proc_setup_bars_write_foreign_region_bars( @@ -2746,6 +2785,7 @@ proc_setup_bars_write_foreign_region_bars( { rc = proc_setup_bars_pcie_write_foreign_memory_bars( i_smp_chip.chip->this_chip, + i_smp_chip.num_phb, process_links, i_smp_chip.foreign_near_ranges, i_smp_chip.foreign_far_ranges); diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_defs.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_defs.H index 4cc618325..f05058f54 100644 --- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_defs.H +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_defs.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014 */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,13 +22,13 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_setup_bars_defs.H,v 1.1 2014/08/05 20:43:46 jmcgill Exp $ +// $Id: proc_setup_bars_defs.H,v 1.2 2014/11/18 17:43:18 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars_defs.H,v $ //------------------------------------------------------------------------------ // *| // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM -// *! *** *** +// *! *** *** // *| // *! TITLE : proc_setup_bars_defs.H // *! DESCRIPTION : Structure/constant definitions for proc_setup_bars HWP (FAPI) @@ -94,7 +94,7 @@ const uint8_t PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES = 8; const uint8_t PROC_SETUP_BARS_NUM_MIRRORED_RANGES = 4; // PCIe unit contstants -const uint8_t PROC_SETUP_BARS_PCIE_NUM_UNITS = 3; +const uint8_t PROC_SETUP_BARS_PCIE_NUM_UNITS = 4; const uint8_t PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT = 3; @@ -242,6 +242,8 @@ struct proc_setup_bars_smp_chip // partial good attributes bool nx_enabled; bool pcie_enabled; + // number of valid PCIe PHBs + uint8_t num_phb; // select for PCIe/DSMP mux (one per link) bool pcie_not_f_link[PROC_FAB_SMP_NUM_F_LINKS]; // real address ranges covered by resources on this chip @@ -982,28 +984,32 @@ const uint32_t PROC_SETUP_BARS_PCIE_CHIP_NON_MIRRORED_BAR[PROC_SETUP_BARS_PCIE_N { PCIE0_NODAL_BAR0_0x02012010, PCIE1_NODAL_BAR0_0x02012410, - PCIE2_NODAL_BAR0_0x02012810 + PCIE2_NODAL_BAR0_0x02012810, + PCIE3_NODAL_BAR0_0x02012C10, }; const uint32_t PROC_SETUP_BARS_PCIE_CHIP_MIRRORED_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS] = { PCIE0_NODAL_BAR1_0x02012011, PCIE1_NODAL_BAR1_0x02012411, - PCIE2_NODAL_BAR1_0x02012811 + PCIE2_NODAL_BAR1_0x02012811, + PCIE3_NODAL_BAR1_0x02012C11 }; const uint32_t PROC_SETUP_BARS_PCIE_NODE_NON_MIRRORED_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS] = { PCIE0_GROUP_BAR0_0x02012012, PCIE1_GROUP_BAR0_0x02012412, - PCIE2_GROUP_BAR0_0x02012812 + PCIE2_GROUP_BAR0_0x02012812, + PCIE3_GROUP_BAR0_0x02012C12 }; const uint32_t PROC_SETUP_BARS_PCIE_NODE_MIRRORED_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS] = { PCIE0_GROUP_BAR1_0x02012013, PCIE1_GROUP_BAR1_0x02012413, - PCIE2_GROUP_BAR1_0x02012813 + PCIE2_GROUP_BAR1_0x02012813, + PCIE3_GROUP_BAR1_0x02012C13 }; const uint32_t PROC_SETUP_BARS_PCIE_FOREIGN_NEAR_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_FAB_SMP_NUM_F_LINKS] = @@ -1019,6 +1025,10 @@ const uint32_t PROC_SETUP_BARS_PCIE_FOREIGN_NEAR_BAR[PROC_SETUP_BARS_PCIE_NUM_UN { PCIE2_NEAR_BAR_F0_0x02012814, PCIE2_NEAR_BAR_F1_0x02012816 + }, + { + PCIE3_NEAR_BAR_F0_0x02012C14, + PCIE3_NEAR_BAR_F1_0x02012C16 } }; @@ -1035,6 +1045,10 @@ const uint32_t PROC_SETUP_BARS_PCIE_FOREIGN_FAR_BAR[PROC_SETUP_BARS_PCIE_NUM_UNI { PCIE2_FAR_BAR_F0_0x02012815, PCIE2_FAR_BAR_F1_0x02012817 + }, + { + PCIE3_FAR_BAR_F0_0x02012C15, + PCIE3_FAR_BAR_F1_0x02012C17 } }; @@ -1091,6 +1105,10 @@ const uint32_t PROC_SETUP_BARS_PCIE_BAR_REGS_MMIO[PROC_SETUP_BARS_PCIE_NUM_UNITS { PCIE2_IO_BAR0_0x02012840, PCIE2_IO_BAR1_0x02012841 + }, + { + PCIE3_IO_BAR0_0x02012C40, + PCIE3_IO_BAR1_0x02012C41 } }; @@ -1124,6 +1142,10 @@ const uint32_t PROC_SETUP_BARS_PCIE_BAR_MASK_REGS_MMIO[PROC_SETUP_BARS_PCIE_NUM_ { PCIE2_IO_MASK0_0x02012843, PCIE2_IO_MASK1_0x02012844 + }, + { + PCIE3_IO_MASK0_0x02012C43, + PCIE3_IO_MASK1_0x02012C44 } }; @@ -1165,6 +1187,10 @@ const uint32_t PROC_SETUP_BARS_PCIE_BAR_REGS_PHB[PROC_SETUP_BARS_PCIE_NUM_UNITS] { PCIE2_IO_BAR2_0x02012842, PCIE2_ASB_BAR_0x0901280B + }, + { + PCIE3_IO_BAR2_0x02012C42, + PCIE3_ASB_BAR_0x09012C0B } }; @@ -1179,7 +1205,8 @@ const uint32_t PROC_SETUP_BARS_PCIE_BAR_EN_REGS[PROC_SETUP_BARS_PCIE_NUM_UNITS] { PCIE0_IO_BAR_EN_0x02012045, PCIE1_IO_BAR_EN_0x02012445, - PCIE2_IO_BAR_EN_0x02012845 + PCIE2_IO_BAR_EN_0x02012845, + PCIE3_IO_BAR_EN_0x02012C45 }; // ETU Reset register field/bit definitions @@ -1187,7 +1214,8 @@ const uint32_t PROC_SETUP_BARS_PCIE_ETU_RESET_REGS[PROC_SETUP_BARS_PCIE_NUM_UNIT { PCIE0_ETU_RESET_0x0901200A, PCIE1_ETU_RESET_0x0901240A, - PCIE2_ETU_RESET_0x0901280A + PCIE2_ETU_RESET_0x0901280A, + PCIE3_ETU_RESET_0x09012C0A }; diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml index d157828ec..9a6516302 100644 --- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012,2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2012,2015 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -20,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_setup_bars_mmio_attributes.xml,v 1.4 2013/05/23 19:42:28 jmcgill Exp $ --> +<!-- $Id: proc_setup_bars_mmio_attributes.xml,v 1.5 2014/11/18 17:44:22 jmcgill Exp $ --> <!-- proc_setup_bars_mmio_attributes.xml --> <attributes> <!-- ********************************************************************* --> @@ -267,12 +269,12 @@ creator: platform consumer: proc_setup_bars firmware notes: - first dimension: PCIE unit number (0:2) + first dimension: PCIE unit number (0:3) second dimension: BAR number (0:2) </description> <valueType>uint8</valueType> <enum>DISABLE = 0x0, ENABLE = 0x1</enum> - <array>3,3</array> + <array>4 3</array> <platInit/> <persistRuntime/> </attribute> @@ -285,13 +287,13 @@ consumer: proc_setup_bars firmware notes: 64-bit address representing BAR RA - first dimension: PCIE unit number (0:2) + first dimension: PCIE unit number (0:3) second dimension: BAR number (0:2) NOTE: BAR0/1 registers cover RA 14:47 NOTE: BAR2 registers covers RA 14:51 </description> <valueType>uint64</valueType> - <array>3,3</array> + <array>4 3</array> <platInit/> <persistRuntime/> </attribute> @@ -303,7 +305,7 @@ creator: platform consumer: proc_setup_bars firmware notes: - first dimension: PCIE unit number (0:2) + first dimension: PCIE unit number (0:3) second dimension: BAR number (0:2) NOTE: supported BAR0/1 sizes are from 64KB-1PB NOTE: only supported BAR2 size is 4KB @@ -347,7 +349,7 @@ 64_KB = 0x0000000000010000, 4_KB = 0x0000000000001000 </enum> - <array>3,3</array> + <array>4 3</array> <platInit/> <persistRuntime/> </attribute> diff --git a/src/usr/hwpf/hwp/include/common_scom_addresses.H b/src/usr/hwpf/hwp/include/common_scom_addresses.H index d5a2d35f4..439eea9fc 100755 --- a/src/usr/hwpf/hwp/include/common_scom_addresses.H +++ b/src/usr/hwpf/hwp/include/common_scom_addresses.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,7 +27,6 @@ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM -// *! *** *** //------------------------------------------------------------------------------ // *! TITLE : common_scom_addresses.H // *! DESCRIPTION : Defines for common/generic scom addresses shared between P8/Centaur diff --git a/src/usr/hwpf/hwp/include/p8_scom_addresses.H b/src/usr/hwpf/hwp/include/p8_scom_addresses.H index ceeb32737..fcda18cd5 100755 --- a/src/usr/hwpf/hwp/include/p8_scom_addresses.H +++ b/src/usr/hwpf/hwp/include/p8_scom_addresses.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,7 +27,6 @@ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM -// *! *** *** //------------------------------------------------------------------------------ // *! TITLE : p8_scom_addresses.H // *! DESCRIPTION : Defines for P8 scom addresses diff --git a/src/usr/hwpf/hwp/initfiles/p8.a_x_pci_dmi_fir.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.a_x_pci_dmi_fir.scom.initfile index 2d322b957..f5a6dfd7e 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.a_x_pci_dmi_fir.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.a_x_pci_dmi_fir.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: p8.a_x_pci_dmi_fir.scom.initfile,v 1.11 2014/10/02 14:08:08 jmcgill Exp $ +#-- $Id: p8.a_x_pci_dmi_fir.scom.initfile,v 1.12 2014/11/18 17:21:01 jmcgill Exp $ #------------------------------------------------------------------------------- #-- #-- (C) Copyright International Business Machines Corp. 2011 @@ -27,9 +27,9 @@ define abus_enabled = (ATTR_PROC_A_ENABLE == ENUM_ATTR_PROC_A_ENABLE_ENABLE); define pcie_enabled = (ATTR_PROC_PCIE_ENABLE == ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE); define trace_on_scom = (ATTR_CHIP_EC_FEATURE_TRACE_CONTROL_ON_SCOM != 0); -define is_venice = (ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC != 0); -define is_naples = (ATTR_CHIP_EC_FEATURE_NAPLES_SPECIFIC != 0); +define nv_present = (ATTR_CHIP_EC_FEATURE_NV_PRESENT != 0); +define single_xbus_present = (ATTR_CHIP_EC_FEATURE_SINGLE_XBUS_PRESENT != 0); #-------------------------------------------------------------------------------- #-- SCOM initializations @@ -290,19 +290,19 @@ scom 0x8009A9E002011E3F { #-- XBUS01.X0.BUSCTL.SCOM.FIR_ACTION0_REG scom 0x04011006 { bits, scom_data, expr; - 0:63, 0x0000000000000000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x0000000000000000, ((xbus_enabled) && (!single_xbus_present)); } #-- XBUS01.X0.BUSCTL.SCOM.FIR_ACTION1_REG scom 0x04011007 { bits, scom_data, expr; - 0:63, 0xFFFFFFFFFFFFC000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0xFFFFFFFFFFFFC000, ((xbus_enabled) && (!single_xbus_present)); } #-- XBUS01.X0.BUSCTL.SCOM.FIR_MASK_REG scom 0x04011003 { bits, scom_data, expr; - 0:63, 0xDFFFFFFFFFFFC000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0xDFFFFFFFFFFFC000, ((xbus_enabled) && (!single_xbus_present)); } #-- X1 @@ -331,93 +331,93 @@ scom 0x04011403 { #-- XBUS23.X0.BUSCTL.SCOM.FIR_ACTION0_REG scom 0x04011806 { bits, scom_data, expr; - 0:63, 0x0000000000000000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x0000000000000000, ((xbus_enabled) && (!single_xbus_present)); } #-- XBUS23.X0.BUSCTL.SCOM.FIR_ACTION1_REG scom 0x04011807 { bits, scom_data, expr; - 0:63, 0xFFFFFFFFFFFFC000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0xFFFFFFFFFFFFC000, ((xbus_enabled) && (!single_xbus_present)); } #-- XBUS23.X0.BUSCTL.SCOM.FIR_MASK_REG scom 0x04011803 { bits, scom_data, expr; - 0:63, 0xDFFFFFFFFFFFC000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0xDFFFFFFFFFFFC000, ((xbus_enabled) && (!single_xbus_present)); } #-- X2 #-- XBUS23.X1.BUSCTL.SCOM.FIR_ACTION0_REG scom 0x04011C06 { bits, scom_data, expr; - 0:63, 0x0000000000000000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x0000000000000000, ((xbus_enabled) && (!single_xbus_present)); } #-- XBUS23.X1.BUSCTL.SCOM.FIR_ACTION1_REG scom 0x04011C07 { bits, scom_data, expr; - 0:63, 0xFFFFFFFFFFFFC000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0xFFFFFFFFFFFFC000, ((xbus_enabled) && (!single_xbus_present)); } #-- XBUS23.X1.BUSCTL.SCOM.FIR_MASK_REG scom 0x04011C03 { bits, scom_data, expr; - 0:63, 0xDFFFFFFFFFFFC000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0xDFFFFFFFFFFFC000, ((xbus_enabled) && (!single_xbus_present)); } #-- bus powerdown settings #-- X0 RX_MODE_PL (broadcast to all groups/lanes), set RX_LANE_PDWN scom 0x800001FF0401103F { bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); } #-- X0 TX_MODE_PL (broadcast to all groups/lanes), set TX_LANE_PDWN scom 0x800405FF0401103F { bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); } #-- X0 RX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all scom 0x800929E00401103F { bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); } #-- X0 RX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all scom 0x800931E00401103F { bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); } #-- X0 RX_CLK_MODE_PG (broadcast to all groups), set RX_CLK_PDWN scom 0x800801E00401103F { bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); } #-- X0 TX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all scom 0x800D1DE00401103F { bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); } #-- X0 TX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all scom 0x800D25E00401103F { bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); } #-- X0 TX_CLK_MODE_PG (broadcast to all groups), set TX_CLK_PDWN scom 0x800C05E00401103F { bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); } #-- X0 RX_FENCE_PG (broadcast to all groups), set RX_FENCE scom 0x8009A9E00401103F { bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); } #-- X1 RX_MODE_PL (broadcast to all groups/lanes), set RX_LANE_PDWN @@ -477,109 +477,109 @@ scom 0x8009A9E00401143F { #-- X2 RX_MODE_PL (broadcast to all groups/lanes), set RX_LANE_PDWN scom 0x800001FF04011C3F { bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); } #-- X2 TX_MODE_PL (broadcast to all groups/lanes), set TX_LANE_PDWN scom 0x800405FF04011C3F { bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); } #-- X2 RX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all scom 0x800929E004011C3F { bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); } #-- X2 RX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all scom 0x800931E004011C3F { bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); } #-- X2 RX_CLK_MODE_PG (broadcast to all groups), set RX_CLK_PDWN scom 0x800801E004011C3F { bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); } #-- X2 TX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all scom 0x800D1DE004011C3F { bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); } #-- X2 TX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all scom 0x800D25E004011C3F { bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); } #-- X2 TX_CLK_MODE_PG (broadcast to all groups), set TX_CLK_PDWN scom 0x800C05E004011C3F { bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); } #-- X2 RX_FENCE_PG (broadcast to all groups), set RX_FENCE scom 0x8009A9E004011C3F { bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); } #-- X3 RX_MODE_PL (broadcast to all groups/lanes), set RX_LANE_PDWN scom 0x800001FF0401183F { bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); } #-- X3 TX_MODE_PL (broadcast to all groups/lanes), set TX_LANE_PDWN scom 0x800405FF0401183F { bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); } #-- X3 RX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all scom 0x800929E00401183F { bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); } #-- X3 RX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all scom 0x800931E00401183F { bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); } #-- X3 RX_CLK_MODE_PG (broadcast to all groups), set RX_CLK_PDWN scom 0x800801E00401183F { bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); } #-- X3 TX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all scom 0x800D1DE00401183F { bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); } #-- X3 TX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all scom 0x800D25E00401183F { bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); } #-- X3 TX_CLK_MODE_PG (broadcast to all groups), set TX_CLK_PDWN scom 0x800C05E00401183F { bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); } #-- X3 RX_FENCE_PG (broadcast to all groups), set RX_FENCE scom 0x8009A9E00401183F { bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && ((is_venice)||(is_naples))); + 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); } @@ -669,110 +669,110 @@ scom 0x08010C03 { #-- NVBUS1.BUSCTL.SCOM.FIR_ACTION0_REG scom 0x08010C46 { bits, scom_data, expr; - 0:63, 0x0000000000000000, (abus_enabled) && (is_naples); + 0:63, 0x0000000000000000, (abus_enabled) && (nv_present); } #-- NVBUS1.BUSCTL.SCOM.FIR_ACTION1_REG scom 0x08010C47 { bits, scom_data, expr; - 0:63, 0xFFFFFFFFFFFFC000, (abus_enabled) && (is_naples); + 0:63, 0xFFFFFFFFFFFFC000, (abus_enabled) && (nv_present); } #-- NVBUS1.BUSCTL.SCOM.FIR_MASK_REG scom 0x08010C43 { bits, scom_data, expr; - 0:63, 0xDFFFFFFFFFFFC000, (abus_enabled) && (is_naples); + 0:63, 0xDFFFFFFFFFFFC000, (abus_enabled) && (nv_present); } #-- ABUS bus initialization/powerdown settings #-- ABUS.TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID1_PG scom 0x800C940008010C3F { bits, scom_data, expr; - 48:53, 0b000001, (abus_enabled) && (!is_naples); + 48:53, 0b000001, (abus_enabled) && (!nv_present); } #-- ABUS.RX0.RXCTL.RX_CTL_REGS.RX_ID1_PG scom 0x8008500008010C3F { bits, scom_data, expr; - 48:53, 0b000001, (abus_enabled) && (!is_naples); + 48:53, 0b000001, (abus_enabled) && (!nv_present); } #-- ABUS.TX_WRAP.TX1.TXCTL.TX_CTL_REGS.TX_ID1_PG scom 0x800C942008010C3F { bits, scom_data, expr; - 48:53, 0b000010, (abus_enabled) && (!is_naples); + 48:53, 0b000010, (abus_enabled) && (!nv_present); } #-- ABUS.RX1.RXCTL.RX_CTL_REGS.RX_ID1_PG scom 0x8008502008010C3F { bits, scom_data, expr; - 48:53, 0b000010, (abus_enabled) && (!is_naples); + 48:53, 0b000010, (abus_enabled) && (!nv_present); } #-- ABUS.TX_WRAP.TX2.TXCTL.TX_CTL_REGS.TX_ID1_PG scom 0x800C944008010C3F { bits, scom_data, expr; - 48:53, 0b000011, (abus_enabled) && (!is_naples); + 48:53, 0b000011, (abus_enabled) && (!nv_present); } #-- ABUS.RX2.RXCTL.RX_CTL_REGS.RX_ID1_PG scom 0x8008504008010C3F { bits, scom_data, expr; - 48:53, 0b000011, (abus_enabled) && (!is_naples); + 48:53, 0b000011, (abus_enabled) && (!nv_present); } #-- ABUS RX_MODE_PL (broadcast to all groups/lanes), set RX_LANE_PDWN scom 0x800001FF08010C3F { bits, scom_data, expr; - 0:63, 0x0000000000008000, (abus_enabled) && (!is_naples); + 0:63, 0x0000000000008000, (abus_enabled) && (!nv_present); } #-- ABUS TX_MODE_PL (broadcast to all groups/lanes), set TX_LANE_PDWN scom 0x800405FF08010C3F { bits, scom_data, expr; - 0:63, 0x0000000000008000, (abus_enabled) && (!is_naples); + 0:63, 0x0000000000008000, (abus_enabled) && (!nv_present); } #-- ABUS RX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all scom 0x800929E008010C3F { bits, scom_data, expr; - 0:63, 0x000000000000FFFF, (abus_enabled) && (!is_naples); + 0:63, 0x000000000000FFFF, (abus_enabled) && (!nv_present); } #-- ABUS RX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all scom 0x800931E008010C3F { bits, scom_data, expr; - 0:63, 0x000000000000FFFF, (abus_enabled) && (!is_naples); + 0:63, 0x000000000000FFFF, (abus_enabled) && (!nv_present); } #-- ABUS RX_CLK_MODE_PG (broadcast to all groups), set RX_CLK_PDWN scom 0x800801E008010C3F { bits, scom_data, expr; - 0:63, 0x0000000000008000, (abus_enabled) && (!is_naples); + 0:63, 0x0000000000008000, (abus_enabled) && (!nv_present); } #-- ABUS TX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all scom 0x800D1DE008010C3F { bits, scom_data, expr; - 0:63, 0x000000000000FFFF, (abus_enabled) && (!is_naples); + 0:63, 0x000000000000FFFF, (abus_enabled) && (!nv_present); } #-- ABUS TX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all scom 0x800D25E008010C3F { bits, scom_data, expr; - 0:63, 0x000000000000FFFF, (abus_enabled) && (!is_naples); + 0:63, 0x000000000000FFFF, (abus_enabled) && (!nv_present); } #-- ABUS TX_CLK_MODE_PG (broadcast to all groups), set TX_CLK_PDWN scom 0x800C05E008010C3F { bits, scom_data, expr; - 0:63, 0x0000000000008000, (abus_enabled) && (!is_naples); + 0:63, 0x0000000000008000, (abus_enabled) && (!nv_present); } #-- ABUS RX_FENCE_PG (broadcast to all groups), set RX_FENCE scom 0x8009A9E008010C3F { bits, scom_data, expr; - 0:63, 0x0000000000008000, (abus_enabled) && (!is_naples); + 0:63, 0x0000000000008000, (abus_enabled) && (!nv_present); } #-- ABUS PB (PBES) @@ -781,19 +781,19 @@ scom 0x8009A9E008010C3F { #-- ES.PBES_WRAP_TOP.PBES_TOP.MISC_IO.SCOM.PB_IOA_FIR_ACTION0_REG scom 0x08010806 { bits, scom_data, expr; - 0:63, 0x0000000000000000, (abus_enabled) && (!is_naples); + 0:63, 0x0000000000000000, (abus_enabled) && (!nv_present); } #-- ES.PBES_WRAP_TOP.PBES_TOP.MISC_IO.SCOM.PB_IOA_FIR_ACTION1_REG scom 0x08010807 { bits, scom_data, expr; - 0:63, 0x0249861800000000, (abus_enabled) && (!is_naples); + 0:63, 0x0249861800000000, (abus_enabled) && (!nv_present); } #-- ES.PBES_WRAP_TOP.PBES_TOP.MISC_IO.SCOM.PB_IOA_FIR_MASK_REG scom 0x08010803 { bits, scom_data, expr; - 0:63, 0xFFFFFFFFFC000000, (abus_enabled) && (!is_naples); + 0:63, 0xFFFFFFFFFC000000, (abus_enabled) && (!nv_present); } #-- ABUS pervasive LFIR @@ -839,19 +839,19 @@ scom 0x080107CB { #-- ES.PBES_WRAP_TOP.PBES_TOP.MISC_IOF.SCOM.PB_IOF_FIR_ACTION0_REG scom 0x09010806 { bits, scom_data, expr; - 0:63, 0xFE082030FE082030, (pcie_enabled) && (!is_naples); + 0:63, 0xFE082030FE082030, (pcie_enabled) && (!nv_present); } #-- ES.PBES_WRAP_TOP.PBES_TOP.MISC_IOF.SCOM.PB_IOF_FIR_ACTION1_REG scom 0x09010807 { bits, scom_data, expr; - 0:63, 0x01D7DFCC01D7DFCC, (pcie_enabled) && (!is_naples); + 0:63, 0x01D7DFCC01D7DFCC, (pcie_enabled) && (!nv_present); } #-- ES.PBES_WRAP_TOP.PBES_TOP.MISC_IOF.SCOM.PB_IOF_FIR_MASK_REG scom 0x09010803 { bits, scom_data, expr; - 0:63, 0xFFFFFFFFFFFFFFFF, (pcie_enabled) && (!is_naples); + 0:63, 0xFFFFFFFFFFFFFFFF, (pcie_enabled) && (!nv_present); } #-- PCIE pervasive LFIR diff --git a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile index 800df287c..b78305ff4 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: p8.abus.custom.scom.initfile,v 1.14 2014/02/20 15:28:36 garyp Exp $ +#-- $Id: p8.abus.custom.scom.initfile,v 1.15 2014/11/18 17:23:22 jmcgill Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: @@ -352,139 +352,139 @@ rx_wt_lane_disabled, 0b1; #TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004341408010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b010, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b010, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } #TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004341508010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b001, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b001, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } #TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004341308010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b011, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b011, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } #TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004341608010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b000, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b000, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } #TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004341108010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b101, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b101, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } #TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004341008010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b110, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b110, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } #TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004341208010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b100, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b100, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } #TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340F08010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b111, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b111, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } #TX_WRAP.TX0.TXPACKS#2.TXPACK_2.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340C08010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b010, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b010, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } #TX_WRAP.TX0.TXPACKS#2.TXPACK_2.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340D08010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b001, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b001, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } #TX_WRAP.TX0.TXPACKS#2.TXPACK_2.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340E08010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b000, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b000, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } #TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340108010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b001, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b001, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } #TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340208010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b010, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b010, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } #TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340008010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b000, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b000, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } #TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340308010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b011, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b011, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } #TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340608010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b110, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b110, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } #TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340508010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b101, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b101, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } #TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340708010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b111, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b111, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } #TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340408010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b100, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b100, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } #TX_WRAP.TX0.TXPACKS#5.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340908010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b001, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b001, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } #TX_WRAP.TX0.TXPACKS#5.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340A08010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b010, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b010, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } #TX_WRAP.TX0.TXPACKS#5.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340808010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b000, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b000, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } #TX_WRAP.TX0.TXPACKS#5.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340B08010C3F { bits, scom_data, expr; - tx_prbs_tap_id, 0b011, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; + tx_prbs_tap_id, 0b011, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } diff --git a/src/usr/hwpf/hwp/initfiles/p8.cxa.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.cxa.scom.initfile index e515fe735..153b3aba3 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.cxa.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.cxa.scom.initfile @@ -1,7 +1,7 @@ -#-- $Id: p8.cxa.scom.initfile,v 1.4 2014/08/05 21:26:13 jmcgill Exp $ +#-- $Id: p8.cxa.scom.initfile,v 1.5 2014/11/18 17:22:30 jmcgill Exp $ #------------------------------------------------------------------------------- #-- -#-- (C) Copyright International Business Machines Corp. 2013 +#-- (C) Copyright International Business Machines Corp. 2011 #-- All Rights Reserved -- Property of IBM #-- *** *** #-- @@ -21,8 +21,9 @@ SyntaxVersion = 1 #-------------------------------------------------------------------------------- #-- Defines #-------------------------------------------------------------------------------- -define capp_hang_control_on_scom = (ATTR_CHIP_EC_FEATURE_CAPP_HANG_CONTROL_ON_SCOM != 0); +define capp_hang_ctl_on_scom = (ATTR_CHIP_EC_FEATURE_CAPP_HANG_CONTROL_ON_SCOM != 0); define capp_prod = (ATTR_CHIP_EC_FEATURE_CAPP_PROD != 0); +define capp_dual = (ATTR_CHIP_EC_FEATURE_DUAL_CAPP_PRESENT != 0); #-------------------------------------------------------------------------------- #-- SCOM initializations @@ -31,21 +32,37 @@ define capp_prod = (ATTR_CHIP_EC_FEATURE_CAPP_PROD != 0); #-- APC Master Config Register scom 0x02013019 { - bits , scom_data, expr; - 4:7 , 0b0000, (capp_hang_control_on_scom); #-- HANG_POLL_SCALE + bits , scom_data, expr; + 4:7 , 0b0000, (capp_hang_ctl_on_scom); #-- HANG_POLL_SCALE +} + +scom 0x02013199 { + bits , scom_data, expr; + 4:7 , 0b0000, (capp_dual && capp_hang_ctl_on_scom); } #-- CAPP Snoop Control Register scom 0x0201301B { - bits , scom_data, expr; - 45:47 , 0b111, (capp_prod); #-- CXA_SNP_MASTER_ADDRESS_PIPELINE_WAIT_COUNT - 48:51 , 0b0010, (capp_hang_control_on_scom); #-- CXA_SNP_DATA_HANG_POLL_SCALE + bits , scom_data, expr; + 45:47 , 0b111, (capp_prod); #-- CXA_SNP_MASTER_ADDRESS_PIPELINE_WAIT_COUNT + 48:51 , 0b0010, (capp_hang_ctl_on_scom); #-- CXA_SNP_DATA_HANG_POLL_SCALE +} + +scom 0x0201319B { + bits , scom_data, expr; + 45:47 , 0b111, (capp_dual && capp_prod); + 48:51 , 0b0010, (capp_dual && capp_hang_ctl_on_scom); } #-- CAPP Transport Control Register scom 0x0201301C { bits , scom_data; - 15:18 , 0b1000; #-- TLBI_DATA_POLL_PULSE_DIV + 15:18 , 0b1000; #-- TLBI_DATA_POLL_PULSE_DIV +} + +scom 0x0201319C { + bits , scom_data, expr; + 15:18 , 0b1000, (capp_dual); } #-- CAPP Flush uOP1 Configuration Register @@ -54,178 +71,353 @@ scom 0x02013803 { 0:63 , 0xB188280728000000; } +scom 0x02013983 { + bits , scom_data, expr; + 0:63 , 0xB188280728000000, (capp_dual); +} + #-- CAPP Flush uOP2 Configuration Register scom 0x02013804 { bits , scom_data; 0:63 , 0xB188400F00000000; } +scom 0x02013984 { + bits , scom_data, expr; + 0:63 , 0xB188400F00000000, (capp_dual); +} + #-- CXA FIR Action0/1 Registers #-- action0,1 = 00 : checkstop #-- 01 : recovered attention #-- 10 : recoverable interrupt #-- 11 : local checkstop = CAPP Machine Check + scom 0x02013006 { - bits , scom_data; #--Action - 0 , 0b0; #-- 0b00 masked BAR PE - 1 , 0b0; #-- 0b00 xstop Register PE - 2 , 0b0; #-- 0b01 recovered attn Master Array CE - 3 , 0b0; #-- 0b00 xstop Master Array UE - 4 , 0b1; #-- 0b11 capp mach check Timer Expired Recoverable Epoch - 5 , 0b0; #-- 0b00 xstop Timer Expired Xstop RCS sequencer hang - 6 , 0b1; #-- 0b11 capp mach check PSL Cmd UE - 7 , 0b1; #-- 0b11 capp mach check PSL Cmd SUE - 8 , 0b0; #-- 0b01 recovered attn Snoop Array CE - 9 , 0b0; #-- 0b00 xstop Snoop Array UE - 10 , 0b0; #-- 0b00 xstop Recovery Failed - 11 , 0b1; #-- 0b11 capp mach check Illegal LPC Bar Access DD2 only - 12 , 0b1; #-- 0b11 capp mach check XPT Recoverable err DD2 only - 13 , 0b1; #-- 0b11 capp mach check Master Recoverable Err - 14 , 0b0; #-- 0b00 masked Spare - 15 , 0b0; #-- 0b00 masked Scom satellite parity Err - 16 , 0b0; #-- 0b00 xstop Master Sys Xstop Err - 17 , 0b0; #-- 0b00 xstop Snooper Sys Xstop Err - 18 , 0b0; #-- 0b00 xstop XPT Sys Xstop Err - 19 , 0b0; #-- 0b00 masked Master Uop Err1 For Lab Use only - 20 , 0b0; #-- 0b00 masked Master Uop Err2 For Lab Use only - 21 , 0b0; #-- 0b00 masked Master Uop Err3 For Lab Use only - 22 , 0b0; #-- 0b00 masked Snooper Uop Err1 For Lab Use only - 23 , 0b0; #-- 0b00 masked Snooper Uop Err2 For Lab Use only - 24 , 0b0; #-- 0b00 masked Snooper Uop Err3 For Lab Use only - 25 , 0b0; #-- 0b00 xstop Unsolicited PowerBus Data or Cresp - 26 , 0b0; #-- 0b00 xstop PowerBus parity Err - 27 , 0b0; #-- 0b00 masked PowerBus Data Hang Err - 28 , 0b0; #-- 0b00 masked PowerBus Hang Err - 29 , 0b0; #-- 0b00 xstop PowerBus Address Err on LD class APC op - 30 , 0b0; #-- 0b00 xstop PowerBus Address Err on ST class APC op - 31 , 0b1; #-- 0b11 capp mach check PHB Link Down - 32 , 0b0; #-- 0b00 masked LD class Foreign Link err - 33 , 0b0; #-- 0b00 masked Foreign Link Hang err - 34 , 0b0; #-- 0b01 recovered attn XPT PowerBus CE - 35 , 0b0; #-- 0b00 masked XPT PowerBus UE - 36 , 0b0; #-- 0b00 masked XPT PowerBus SUE - 37 , 0b1; #-- 0b11 capp mach check TLBI Timeout Err - 38 , 0b0; #-- 0b00 xstop TLBI Seq Err - 39 , 0b0; #-- 0b00 xstop TLBI Bad Op Err - 40 , 0b0; #-- 0b00 xstop TLBI Seq Num Parity Err - 41 , 0b0; #-- 0b00 masked ST class Foreign Link Fail - 42 , 0b0; #-- 0b00 masked TimeBase Err DD2 only - 43 , 0b0; #-- 0b00 masked XPT Informational DD2 only - 44 , 0b0; #-- 0b00 masked Spare - 45 , 0b0; #-- 0b00 masked Spare - 46 , 0b0; #-- 0b00 masked Spare - 47 , 0b0; #-- 0b00 masked Scom satellite parity error Copy 1 - 48 , 0b0; #-- 0b00 masked Scom satellite parity error Copy 2 + bits , scom_data; #--Action + 0 , 0b0; #-- 0b00 masked BAR PE + 1 , 0b0; #-- 0b00 xstop Register PE + 2 , 0b0; #-- 0b01 recovered attn Master Array CE + 3 , 0b0; #-- 0b00 xstop Master Array UE + 4 , 0b1; #-- 0b11 capp mach check Timer Expired Recoverable Epoch + 5 , 0b0; #-- 0b00 xstop Timer Expired Xstop RCS sequencer hang + 6 , 0b1; #-- 0b11 capp mach check PSL Cmd UE + 7 , 0b1; #-- 0b11 capp mach check PSL Cmd SUE + 8 , 0b0; #-- 0b01 recovered attn Snoop Array CE + 9 , 0b0; #-- 0b00 xstop Snoop Array UE + 10 , 0b0; #-- 0b00 xstop Recovery Failed + 11 , 0b1; #-- 0b11 capp mach check Illegal LPC Bar Access DD2 only + 12 , 0b1; #-- 0b11 capp mach check XPT Recoverable err DD2 only + 13 , 0b1; #-- 0b11 capp mach check Master Recoverable Err + 14 , 0b0; #-- 0b00 masked Spare + 15 , 0b0; #-- 0b00 masked Scom satellite parity Err + 16 , 0b0; #-- 0b00 xstop Master Sys Xstop Err + 17 , 0b0; #-- 0b00 xstop Snooper Sys Xstop Err + 18 , 0b0; #-- 0b00 xstop XPT Sys Xstop Err + 19 , 0b0; #-- 0b00 masked Master Uop Err1 For Lab Use only + 20 , 0b0; #-- 0b00 masked Master Uop Err2 For Lab Use only + 21 , 0b0; #-- 0b00 masked Master Uop Err3 For Lab Use only + 22 , 0b0; #-- 0b00 masked Snooper Uop Err1 For Lab Use only + 23 , 0b0; #-- 0b00 masked Snooper Uop Err2 For Lab Use only + 24 , 0b0; #-- 0b00 masked Snooper Uop Err3 For Lab Use only + 25 , 0b0; #-- 0b00 xstop Unsolicited PowerBus Data or Cresp + 26 , 0b0; #-- 0b00 xstop PowerBus parity Err + 27 , 0b0; #-- 0b00 masked PowerBus Data Hang Err + 28 , 0b0; #-- 0b00 masked PowerBus Hang Err + 29 , 0b0; #-- 0b00 xstop PowerBus Address Err on LD class APC op + 30 , 0b0; #-- 0b00 xstop PowerBus Address Err on ST class APC op + 31 , 0b1; #-- 0b11 capp mach check PHB Link Down + 32 , 0b0; #-- 0b00 masked LD class Foreign Link err + 33 , 0b0; #-- 0b00 masked Foreign Link Hang err + 34 , 0b0; #-- 0b01 recovered attn XPT PowerBus CE + 35 , 0b0; #-- 0b00 masked XPT PowerBus UE + 36 , 0b0; #-- 0b00 masked XPT PowerBus SUE + 37 , 0b1; #-- 0b11 capp mach check TLBI Timeout Err + 38 , 0b0; #-- 0b00 xstop TLBI Seq Err + 39 , 0b0; #-- 0b00 xstop TLBI Bad Op Err + 40 , 0b0; #-- 0b00 xstop TLBI Seq Num Parity Err + 41 , 0b0; #-- 0b00 masked ST class Foreign Link Fail + 42 , 0b0; #-- 0b00 masked TimeBase Err DD2 only + 43 , 0b0; #-- 0b00 masked XPT Informational DD2 only + 44 , 0b0; #-- 0b00 masked Spare + 45 , 0b0; #-- 0b00 masked Spare + 46 , 0b0; #-- 0b00 masked Spare + 47 , 0b0; #-- 0b00 masked Scom satellite parity error Copy 1 + 48 , 0b0; #-- 0b00 masked Scom satellite parity error Copy 2 +} + +scom 0x02013186 { + bits , scom_data, expr; #--Action + 0 , 0b0, (capp_dual); #-- 0b00 masked BAR PE + 1 , 0b0, (capp_dual); #-- 0b00 xstop Register PE + 2 , 0b0, (capp_dual); #-- 0b01 recovered attn Master Array CE + 3 , 0b0, (capp_dual); #-- 0b00 xstop Master Array UE + 4 , 0b1, (capp_dual); #-- 0b11 capp mach check Timer Expired Recoverable Epoch + 5 , 0b0, (capp_dual); #-- 0b00 xstop Timer Expired Xstop RCS sequencer hang + 6 , 0b1, (capp_dual); #-- 0b11 capp mach check PSL Cmd UE + 7 , 0b1, (capp_dual); #-- 0b11 capp mach check PSL Cmd SUE + 8 , 0b0, (capp_dual); #-- 0b01 recovered attn Snoop Array CE + 9 , 0b0, (capp_dual); #-- 0b00 xstop Snoop Array UE + 10 , 0b0, (capp_dual); #-- 0b00 xstop Recovery Failed + 11 , 0b1, (capp_dual); #-- 0b11 capp mach check Illegal LPC Bar Access DD2 only + 12 , 0b1, (capp_dual); #-- 0b11 capp mach check XPT Recoverable err DD2 only + 13 , 0b1, (capp_dual); #-- 0b11 capp mach check Master Recoverable Err + 14 , 0b0, (capp_dual); #-- 0b00 masked Spare + 15 , 0b0, (capp_dual); #-- 0b00 masked Scom satellite parity Err + 16 , 0b0, (capp_dual); #-- 0b00 xstop Master Sys Xstop Err + 17 , 0b0, (capp_dual); #-- 0b00 xstop Snooper Sys Xstop Err + 18 , 0b0, (capp_dual); #-- 0b00 xstop XPT Sys Xstop Err + 19 , 0b0, (capp_dual); #-- 0b00 masked Master Uop Err1 For Lab Use only + 20 , 0b0, (capp_dual); #-- 0b00 masked Master Uop Err2 For Lab Use only + 21 , 0b0, (capp_dual); #-- 0b00 masked Master Uop Err3 For Lab Use only + 22 , 0b0, (capp_dual); #-- 0b00 masked Snooper Uop Err1 For Lab Use only + 23 , 0b0, (capp_dual); #-- 0b00 masked Snooper Uop Err2 For Lab Use only + 24 , 0b0, (capp_dual); #-- 0b00 masked Snooper Uop Err3 For Lab Use only + 25 , 0b0, (capp_dual); #-- 0b00 xstop Unsolicited PowerBus Data or Cresp + 26 , 0b0, (capp_dual); #-- 0b00 xstop PowerBus parity Err + 27 , 0b0, (capp_dual); #-- 0b00 masked PowerBus Data Hang Err + 28 , 0b0, (capp_dual); #-- 0b00 masked PowerBus Hang Err + 29 , 0b0, (capp_dual); #-- 0b00 xstop PowerBus Address Err on LD class APC op + 30 , 0b0, (capp_dual); #-- 0b00 xstop PowerBus Address Err on ST class APC op + 31 , 0b1, (capp_dual); #-- 0b11 capp mach check PHB Link Down + 32 , 0b0, (capp_dual); #-- 0b00 masked LD class Foreign Link err + 33 , 0b0, (capp_dual); #-- 0b00 masked Foreign Link Hang err + 34 , 0b0, (capp_dual); #-- 0b01 recovered attn XPT PowerBus CE + 35 , 0b0, (capp_dual); #-- 0b00 masked XPT PowerBus UE + 36 , 0b0, (capp_dual); #-- 0b00 masked XPT PowerBus SUE + 37 , 0b1, (capp_dual); #-- 0b11 capp mach check TLBI Timeout Err + 38 , 0b0, (capp_dual); #-- 0b00 xstop TLBI Seq Err + 39 , 0b0, (capp_dual); #-- 0b00 xstop TLBI Bad Op Err + 40 , 0b0, (capp_dual); #-- 0b00 xstop TLBI Seq Num Parity Err + 41 , 0b0, (capp_dual); #-- 0b00 masked ST class Foreign Link Fail + 42 , 0b0, (capp_dual); #-- 0b00 masked TimeBase Err DD2 only + 43 , 0b0, (capp_dual); #-- 0b00 masked XPT Informational DD2 only + 44 , 0b0, (capp_dual); #-- 0b00 masked Spare + 45 , 0b0, (capp_dual); #-- 0b00 masked Spare + 46 , 0b0, (capp_dual); #-- 0b00 masked Spare + 47 , 0b0, (capp_dual); #-- 0b00 masked Scom satellite parity error Copy 1 + 48 , 0b0, (capp_dual); #-- 0b00 masked Scom satellite parity error Copy 2 } + scom 0x02013007 { - bits , scom_data; #--Action - 0 , 0b0; #-- 0b00 masked BAR PE - 1 , 0b0; #-- 0b00 xstop Register PE - 2 , 0b1; #-- 0b01 recovered attn Master Array CE - 3 , 0b0; #-- 0b10 xstop Master Array UE - 4 , 0b1; #-- 0b11 capp mach check Timer Expired Recoverable Epoch - 5 , 0b0; #-- 0b00 xstop Timer Expired Xstop RCS sequencer hang - 6 , 0b1; #-- 0b11 capp mach check PSL Cmd UE - 7 , 0b1; #-- 0b11 capp mach check PSL Cmd SUE - 8 , 0b1; #-- 0b01 recovered attn Snoop Array CE - 9 , 0b0; #-- 0b00 xstop Snoop Array UE - 10 , 0b0; #-- 0b00 xstop Recovery Failed - 11 , 0b1; #-- 0b11 capp mach check Illegal LPC Bar Access DD2 only - 12 , 0b1; #-- 0b11 capp mach check XPT Recoverable err DD2 only - 13 , 0b1; #-- 0b11 capp mach check Master Recoverable Err - 14 , 0b0; #-- 0b00 masked Spare - 15 , 0b0; #-- 0b00 masked Scom satellite parity Err - 16 , 0b0; #-- 0b00 xstop Master Sys Xstop Err - 17 , 0b0; #-- 0b00 xstop Snooper Sys Xstop Err - 18 , 0b0; #-- 0b00 xstop XPT Sys Xstop Err - 19 , 0b0; #-- 0b00 masked Master Uop Err1 For Lab Use only - 20 , 0b0; #-- 0b00 masked Master Uop Err2 For Lab Use only - 21 , 0b0; #-- 0b00 masked Master Uop Err3 For Lab Use only - 22 , 0b0; #-- 0b00 masked Snooper Uop Err1 For Lab Use only - 23 , 0b0; #-- 0b00 masked Snooper Uop Err2 For Lab Use only - 24 , 0b0; #-- 0b00 masked Snooper Uop Err3 For Lab Use only - 25 , 0b0; #-- 0b00 xstop Unsolicited PowerBus Data or Cresp - 26 , 0b0; #-- 0b00 xstop PowerBus parity Err - 27 , 0b0; #-- 0b00 masked PowerBus Data Hang Err - 28 , 0b0; #-- 0b00 masked PowerBus Hang Err - 29 , 0b0; #-- 0b00 xstop PowerBus Address Err on LD class APC op - 30 , 0b0; #-- 0b00 xstop PowerBus Address Err on ST class APC op - 31 , 0b1; #-- 0b11 capp mach check PHB Link Down - 32 , 0b0; #-- 0b00 masked LD class Foreign Link err - 33 , 0b0; #-- 0b00 masked Foreign Link Hang err - 34 , 0b1; #-- 0b01 recovered attn XPT PowerBus CE - 35 , 0b0; #-- 0b00 masked XPT PowerBus UE - 36 , 0b0; #-- 0b00 masked XPT PowerBus SUE - 37 , 0b1; #-- 0b11 capp mach check TLBI Timeout Err - 38 , 0b0; #-- 0b00 xstop TLBI Seq Err - 39 , 0b0; #-- 0b00 xstop TLBI Bad Op Err - 40 , 0b0; #-- 0b00 xstop TLBI Seq Num Parity Err - 41 , 0b0; #-- 0b00 masked ST class Foreign Link Fail - 42 , 0b0; #-- 0b00 masked TimeBase Err DD2 only - 43 , 0b0; #-- 0b00 masked XPT Informational DD2 only - 44 , 0b0; #-- 0b00 masked Spare - 45 , 0b0; #-- 0b00 masked Spare - 46 , 0b0; #-- 0b00 masked Spare - 47 , 0b0; #-- 0b00 masked Scom satellite parity error Copy 1 - 48 , 0b0; #-- 0b00 masked Scom satellite parity error Copy 2 + bits , scom_data; #--Action + 0 , 0b0; #-- 0b00 masked BAR PE + 1 , 0b0; #-- 0b00 xstop Register PE + 2 , 0b1; #-- 0b01 recovered attn Master Array CE + 3 , 0b0; #-- 0b10 xstop Master Array UE + 4 , 0b1; #-- 0b11 capp mach check Timer Expired Recoverable Epoch + 5 , 0b0; #-- 0b00 xstop Timer Expired Xstop RCS sequencer hang + 6 , 0b1; #-- 0b11 capp mach check PSL Cmd UE + 7 , 0b1; #-- 0b11 capp mach check PSL Cmd SUE + 8 , 0b1; #-- 0b01 recovered attn Snoop Array CE + 9 , 0b0; #-- 0b00 xstop Snoop Array UE + 10 , 0b0; #-- 0b00 xstop Recovery Failed + 11 , 0b1; #-- 0b11 capp mach check Illegal LPC Bar Access DD2 only + 12 , 0b1; #-- 0b11 capp mach check XPT Recoverable err DD2 only + 13 , 0b1; #-- 0b11 capp mach check Master Recoverable Err + 14 , 0b0; #-- 0b00 masked Spare + 15 , 0b0; #-- 0b00 masked Scom satellite parity Err + 16 , 0b0; #-- 0b00 xstop Master Sys Xstop Err + 17 , 0b0; #-- 0b00 xstop Snooper Sys Xstop Err + 18 , 0b0; #-- 0b00 xstop XPT Sys Xstop Err + 19 , 0b0; #-- 0b00 masked Master Uop Err1 For Lab Use only + 20 , 0b0; #-- 0b00 masked Master Uop Err2 For Lab Use only + 21 , 0b0; #-- 0b00 masked Master Uop Err3 For Lab Use only + 22 , 0b0; #-- 0b00 masked Snooper Uop Err1 For Lab Use only + 23 , 0b0; #-- 0b00 masked Snooper Uop Err2 For Lab Use only + 24 , 0b0; #-- 0b00 masked Snooper Uop Err3 For Lab Use only + 25 , 0b0; #-- 0b00 xstop Unsolicited PowerBus Data or Cresp + 26 , 0b0; #-- 0b00 xstop PowerBus parity Err + 27 , 0b0; #-- 0b00 masked PowerBus Data Hang Err + 28 , 0b0; #-- 0b00 masked PowerBus Hang Err + 29 , 0b0; #-- 0b00 xstop PowerBus Address Err on LD class APC op + 30 , 0b0; #-- 0b00 xstop PowerBus Address Err on ST class APC op + 31 , 0b1; #-- 0b11 capp mach check PHB Link Down + 32 , 0b0; #-- 0b00 masked LD class Foreign Link err + 33 , 0b0; #-- 0b00 masked Foreign Link Hang err + 34 , 0b1; #-- 0b01 recovered attn XPT PowerBus CE + 35 , 0b0; #-- 0b00 masked XPT PowerBus UE + 36 , 0b0; #-- 0b00 masked XPT PowerBus SUE + 37 , 0b1; #-- 0b11 capp mach check TLBI Timeout Err + 38 , 0b0; #-- 0b00 xstop TLBI Seq Err + 39 , 0b0; #-- 0b00 xstop TLBI Bad Op Err + 40 , 0b0; #-- 0b00 xstop TLBI Seq Num Parity Err + 41 , 0b0; #-- 0b00 masked ST class Foreign Link Fail + 42 , 0b0; #-- 0b00 masked TimeBase Err DD2 only + 43 , 0b0; #-- 0b00 masked XPT Informational DD2 only + 44 , 0b0; #-- 0b00 masked Spare + 45 , 0b0; #-- 0b00 masked Spare + 46 , 0b0; #-- 0b00 masked Spare + 47 , 0b0; #-- 0b00 masked Scom satellite parity error Copy 1 + 48 , 0b0; #-- 0b00 masked Scom satellite parity error Copy 2 } +scom 0x02013187 { + bits , scom_data, expr; #--Action + 0 , 0b0, (capp_dual); #-- 0b00 masked BAR PE + 1 , 0b0, (capp_dual); #-- 0b00 xstop Register PE + 2 , 0b1, (capp_dual); #-- 0b01 recovered attn Master Array CE + 3 , 0b0, (capp_dual); #-- 0b10 xstop Master Array UE + 4 , 0b1, (capp_dual); #-- 0b11 capp mach check Timer Expired Recoverable Epoch + 5 , 0b0, (capp_dual); #-- 0b00 xstop Timer Expired Xstop RCS sequencer hang + 6 , 0b1, (capp_dual); #-- 0b11 capp mach check PSL Cmd UE + 7 , 0b1, (capp_dual); #-- 0b11 capp mach check PSL Cmd SUE + 8 , 0b1, (capp_dual); #-- 0b01 recovered attn Snoop Array CE + 9 , 0b0, (capp_dual); #-- 0b00 xstop Snoop Array UE + 10 , 0b0, (capp_dual); #-- 0b00 xstop Recovery Failed + 11 , 0b1, (capp_dual); #-- 0b11 capp mach check Illegal LPC Bar Access DD2 only + 12 , 0b1, (capp_dual); #-- 0b11 capp mach check XPT Recoverable err DD2 only + 13 , 0b1, (capp_dual); #-- 0b11 capp mach check Master Recoverable Err + 14 , 0b0, (capp_dual); #-- 0b00 masked Spare + 15 , 0b0, (capp_dual); #-- 0b00 masked Scom satellite parity Err + 16 , 0b0, (capp_dual); #-- 0b00 xstop Master Sys Xstop Err + 17 , 0b0, (capp_dual); #-- 0b00 xstop Snooper Sys Xstop Err + 18 , 0b0, (capp_dual); #-- 0b00 xstop XPT Sys Xstop Err + 19 , 0b0, (capp_dual); #-- 0b00 masked Master Uop Err1 For Lab Use only + 20 , 0b0, (capp_dual); #-- 0b00 masked Master Uop Err2 For Lab Use only + 21 , 0b0, (capp_dual); #-- 0b00 masked Master Uop Err3 For Lab Use only + 22 , 0b0, (capp_dual); #-- 0b00 masked Snooper Uop Err1 For Lab Use only + 23 , 0b0, (capp_dual); #-- 0b00 masked Snooper Uop Err2 For Lab Use only + 24 , 0b0, (capp_dual); #-- 0b00 masked Snooper Uop Err3 For Lab Use only + 25 , 0b0, (capp_dual); #-- 0b00 xstop Unsolicited PowerBus Data or Cresp + 26 , 0b0, (capp_dual); #-- 0b00 xstop PowerBus parity Err + 27 , 0b0, (capp_dual); #-- 0b00 masked PowerBus Data Hang Err + 28 , 0b0, (capp_dual); #-- 0b00 masked PowerBus Hang Err + 29 , 0b0, (capp_dual); #-- 0b00 xstop PowerBus Address Err on LD class APC op + 30 , 0b0, (capp_dual); #-- 0b00 xstop PowerBus Address Err on ST class APC op + 31 , 0b1, (capp_dual); #-- 0b11 capp mach check PHB Link Down + 32 , 0b0, (capp_dual); #-- 0b00 masked LD class Foreign Link err + 33 , 0b0, (capp_dual); #-- 0b00 masked Foreign Link Hang err + 34 , 0b1, (capp_dual); #-- 0b01 recovered attn XPT PowerBus CE + 35 , 0b0, (capp_dual); #-- 0b00 masked XPT PowerBus UE + 36 , 0b0, (capp_dual); #-- 0b00 masked XPT PowerBus SUE + 37 , 0b1, (capp_dual); #-- 0b11 capp mach check TLBI Timeout Err + 38 , 0b0, (capp_dual); #-- 0b00 xstop TLBI Seq Err + 39 , 0b0, (capp_dual); #-- 0b00 xstop TLBI Bad Op Err + 40 , 0b0, (capp_dual); #-- 0b00 xstop TLBI Seq Num Parity Err + 41 , 0b0, (capp_dual); #-- 0b00 masked ST class Foreign Link Fail + 42 , 0b0, (capp_dual); #-- 0b00 masked TimeBase Err DD2 only + 43 , 0b0, (capp_dual); #-- 0b00 masked XPT Informational DD2 only + 44 , 0b0, (capp_dual); #-- 0b00 masked Spare + 45 , 0b0, (capp_dual); #-- 0b00 masked Spare + 46 , 0b0, (capp_dual); #-- 0b00 masked Spare + 47 , 0b0, (capp_dual); #-- 0b00 masked Scom satellite parity error Copy 1 + 48 , 0b0, (capp_dual); #-- 0b00 masked Scom satellite parity error Copy 2 +} #-- CXA CAPP FIR Mask Register scom 0x02013003 { - bits , scom_data, expr; - 0 , 0b1, any; #-- BAR PE - 1 , 0b1, (!capp_prod); #-- mask for DD1 Register PE - 1 , 0b0, (capp_prod); #-- Register PE - 2 , 0b0, any; #-- Master Array CE - 3 , 0b0, any; #-- Master Array UE - 4 , 0b0, any; #-- Timer Expired Recoverable Epoch - 5 , 0b0, any; #-- Timer Expired Xstop RCS sequencer hang - 6 , 0b0, any; #-- PSL Cmd UE - 7 , 0b0, any; #-- PSL Cmd SUE - 8 , 0b0, any; #-- Snoop Array CE - 9 , 0b0, any; #-- Snoop Array UE - 10 , 0b0, any; #-- Recovery Failed - 11 , 0b1, (!capp_prod); #-- mask for DD1 Illegal LPC Bar Access DD2 only - 11 , 0b0, (capp_prod); #-- Illegal LPC Bar Access DD2 only - 12 , 0b1, (!capp_prod); #-- mask for DD1 XPT Recoverable err DD2 only - 12 , 0b0, (capp_prod); #-- XPT Recoverable err DD2 only - 13 , 0b0, any; #-- Master Recoverable Err - 14 , 0b1, any; #-- Spare - 15 , 0b1, any; #-- Scom satellite parity Err - 16 , 0b0, any; #-- Master Sys Xstop Err - 17 , 0b0, any; #-- Snooper Sys Xstop Err - 18 , 0b1, (!capp_prod); #-- mask for DD1 XPT Sys Xstop Err - 18 , 0b0, (capp_prod); #-- XPT Sys Xstop Err - 19 , 0b1, any; #-- Master Uop Err1 For Lab Use only - 20 , 0b1, any; #-- Master Uop Err2 For Lab Use only - 21 , 0b1, any; #-- Master Uop Err3 For Lab Use only - 22 , 0b1, any; #-- Snooper Uop Err1 łor Lab Use only - 23 , 0b1, any; #-- Snooper Uop Err2 łor Lab Use only - 24 , 0b1, any; #-- Snooper Uop Err3 łor Lab Use only - 25 , 0b0, any; #-- Unsolicited PowerBus Data or Cresp - 26 , 0b1, (!capp_prod); #-- mask for DD1 PowerBus Parity Err - 26 , 0b0, (capp_prod); #-- PowerBus Parity Err - 27 , 0b1, any; #-- PowerBus Data Hang Err - 28 , 0b1, any; #-- PowerBus Hang Err - 29 , 0b0, any; #-- PowerBus Address Err on LD class APC op - 30 , 0b0, any; #-- PowerBus Address Err on ST class APC op - 31 , 0b0, any; #-- PHB Link Down - 32 , 0b1, any; #-- LD class Foreign Link err - 33 , 0b1, any; #-- Foreign Link Hang err - 34 , 0b0, any; #-- XPT PowerBus CE - 35 , 0b1, any; #-- XPT PowerBus UE - 36 , 0b1, any; #-- XPT PowerBus SUE - 37 , 0b0, any; #-- TLBI Timeout Err - 38 , 0b0, any; #-- TLBI Seq Err - 39 , 0b0, any; #-- TLBI Bad Op Err - 40 , 0b0, any; #-- TLBI Seq Num Parity Err - 41 , 0b1, any; #-- ST class Foreign Link Fail - 42 , 0b1, any; #-- TimeBase Err DD2 only - 43 , 0b1, any; #-- XPT Informational DD2 only - 44 , 0b1, any; #-- Spare - 45 , 0b1, any; #-- Spare - 46 , 0b1, any; #-- Spare - 47 , 0b1, any; #-- Scom satellite parity error Copy 1 - 48 , 0b1, any; #-- Scom satellite parity error Copy 2 + bits , scom_data, expr; + 0 , 0b1, any; #-- BAR PE + 1 , 0b1, (!capp_prod); #-- mask for DD1 Register PE + 1 , 0b0, (capp_prod); #-- Register PE + 2 , 0b0, any; #-- Master Array CE + 3 , 0b0, any; #-- Master Array UE + 4 , 0b0, any; #-- Timer Expired Recoverable Epoch + 5 , 0b0, any; #-- Timer Expired Xstop RCS sequencer hang + 6 , 0b0, any; #-- PSL Cmd UE + 7 , 0b0, any; #-- PSL Cmd SUE + 8 , 0b0, any; #-- Snoop Array CE + 9 , 0b0, any; #-- Snoop Array UE + 10 , 0b0, any; #-- Recovery Failed + 11 , 0b1, (!capp_prod); #-- mask for DD1 Illegal LPC Bar Access DD2 only + 11 , 0b0, (capp_prod); #-- Illegal LPC Bar Access DD2 only + 12 , 0b1, (!capp_prod); #-- mask for DD1 XPT Recoverable err DD2 only + 12 , 0b0, (capp_prod); #-- XPT Recoverable err DD2 only + 13 , 0b0, any; #-- Master Recoverable Err + 14 , 0b1, any; #-- Spare + 15 , 0b1, any; #-- Scom satellite parity Err + 16 , 0b0, any; #-- Master Sys Xstop Err + 17 , 0b0, any; #-- Snooper Sys Xstop Err + 18 , 0b1, (!capp_prod); #-- mask for DD1 XPT Sys Xstop Err + 18 , 0b0, (capp_prod); #-- XPT Sys Xstop Err + 19 , 0b1, any; #-- Master Uop Err1 For Lab Use only + 20 , 0b1, any; #-- Master Uop Err2 For Lab Use only + 21 , 0b1, any; #-- Master Uop Err3 For Lab Use only + 22 , 0b1, any; #-- Snooper Uop Err1 łor Lab Use only + 23 , 0b1, any; #-- Snooper Uop Err2 łor Lab Use only + 24 , 0b1, any; #-- Snooper Uop Err3 łor Lab Use only + 25 , 0b0, any; #-- Unsolicited PowerBus Data or Cresp + 26 , 0b1, (!capp_prod); #-- mask for DD1 PowerBus Parity Err + 26 , 0b0, (capp_prod); #-- PowerBus Parity Err + 27 , 0b1, any; #-- PowerBus Data Hang Err + 28 , 0b1, any; #-- PowerBus Hang Err + 29 , 0b0, any; #-- PowerBus Address Err on LD class APC op + 30 , 0b0, any; #-- PowerBus Address Err on ST class APC op + 31 , 0b0, any; #-- PHB Link Down + 32 , 0b1, any; #-- LD class Foreign Link err + 33 , 0b1, any; #-- Foreign Link Hang err + 34 , 0b0, any; #-- XPT PowerBus CE + 35 , 0b1, any; #-- XPT PowerBus UE + 36 , 0b1, any; #-- XPT PowerBus SUE + 37 , 0b0, any; #-- TLBI Timeout Err + 38 , 0b0, any; #-- TLBI Seq Err + 39 , 0b0, any; #-- TLBI Bad Op Err + 40 , 0b0, any; #-- TLBI Seq Num Parity Err + 41 , 0b1, any; #-- ST class Foreign Link Fail + 42 , 0b1, any; #-- TimeBase Err DD2 only + 43 , 0b1, any; #-- XPT Informational DD2 only + 44 , 0b1, any; #-- Spare + 45 , 0b1, any; #-- Spare + 46 , 0b1, any; #-- Spare + 47 , 0b1, any; #-- Scom satellite parity error Copy 1 + 48 , 0b1, any; #-- Scom satellite parity error Copy 2 } + +scom 0x02013183 { + bits , scom_data, expr; + 0 , 0b1, (capp_dual); #-- BAR PE + 1 , 0b1, (capp_dual && !capp_prod); #-- Register PE + 1 , 0b0, (capp_dual && capp_prod); #-- Register PE + 2 , 0b0, (capp_dual); #-- Master Array CE + 3 , 0b0, (capp_dual); #-- Master Array UE + 4 , 0b0, (capp_dual); #-- Timer Expired Recoverable Epoch + 5 , 0b0, (capp_dual); #-- Timer Expired Xstop RCS sequencer hang + 6 , 0b0, (capp_dual); #-- PSL Cmd UE + 7 , 0b0, (capp_dual); #-- PSL Cmd SUE + 8 , 0b0, (capp_dual); #-- Snoop Array CE + 9 , 0b0, (capp_dual); #-- Snoop Array UE + 10 , 0b0, (capp_dual); #-- Recovery Failed + 11 , 0b1, (capp_dual && !capp_prod); #-- Illegal LPC Bar Access DD2 only + 11 , 0b0, (capp_dual && capp_prod); #-- Illegal LPC Bar Access DD2 only + 12 , 0b1, (capp_dual && !capp_prod); #-- XPT Recoverable err DD2 only + 12 , 0b0, (capp_dual && capp_prod); #-- XPT Recoverable err DD2 only + 13 , 0b0, (capp_dual); #-- Master Recoverable Err + 14 , 0b1, (capp_dual); #-- Spare + 15 , 0b1, (capp_dual); #-- Scom satellite parity Err + 16 , 0b0, (capp_dual); #-- Master Sys Xstop Err + 17 , 0b0, (capp_dual); #-- Snooper Sys Xstop Err + 18 , 0b1, (capp_dual && !capp_prod); #-- XPT Sys Xstop Err + 18 , 0b0, (capp_dual && capp_prod); #-- XPT Sys Xstop Err + 19 , 0b1, (capp_dual); #-- Master Uop Err1 For Lab Use only + 20 , 0b1, (capp_dual); #-- Master Uop Err2 For Lab Use only + 21 , 0b1, (capp_dual); #-- Master Uop Err3 For Lab Use only + 22 , 0b1, (capp_dual); #-- Snooper Uop Err1 łor Lab Use only + 23 , 0b1, (capp_dual); #-- Snooper Uop Err2 łor Lab Use only + 24 , 0b1, (capp_dual); #-- Snooper Uop Err3 łor Lab Use only + 25 , 0b0, (capp_dual); #-- Unsolicited PowerBus Data or Cresp + 26 , 0b1, (capp_dual && !capp_prod); #-- PowerBus Parity Err + 26 , 0b0, (capp_dual && capp_prod); #-- PowerBus Parity Err + 27 , 0b1, (capp_dual); #-- PowerBus Data Hang Err + 28 , 0b1, (capp_dual); #-- PowerBus Hang Err + 29 , 0b0, (capp_dual); #-- PowerBus Address Err on LD class APC op + 30 , 0b0, (capp_dual); #-- PowerBus Address Err on ST class APC op + 31 , 0b0, (capp_dual); #-- PHB Link Down + 32 , 0b1, (capp_dual); #-- LD class Foreign Link err + 33 , 0b1, (capp_dual); #-- Foreign Link Hang err + 34 , 0b0, (capp_dual); #-- XPT PowerBus CE + 35 , 0b1, (capp_dual); #-- XPT PowerBus UE + 36 , 0b1, (capp_dual); #-- XPT PowerBus SUE + 37 , 0b0, (capp_dual); #-- TLBI Timeout Err + 38 , 0b0, (capp_dual); #-- TLBI Seq Err + 39 , 0b0, (capp_dual); #-- TLBI Bad Op Err + 40 , 0b0, (capp_dual); #-- TLBI Seq Num Parity Err + 41 , 0b1, (capp_dual); #-- ST class Foreign Link Fail + 42 , 0b1, (capp_dual); #-- TimeBase Err DD2 only + 43 , 0b1, (capp_dual); #-- XPT Informational DD2 only + 44 , 0b1, (capp_dual); #-- Spare + 45 , 0b1, (capp_dual); #-- Spare + 46 , 0b1, (capp_dual); #-- Spare + 47 , 0b1, (capp_dual); #-- Scom satellite parity error Copy 1 + 48 , 0b1, (capp_dual); #-- Scom satellite parity error Copy 2 +}
\ No newline at end of file diff --git a/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile index 371853dca..1d57ad2ca 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: p8.fbc.scom.initfile,v 1.17 2014/10/01 14:47:35 szhong Exp $ +#-- $Id: p8.fbc.scom.initfile,v 1.18 2014/11/18 17:24:13 jmcgill Exp $ #------------------------------------------------------------------------------- #-- #-- (C) Copyright International Business Machines Corp. 2011 @@ -28,7 +28,7 @@ define xbus_enabled = (ATTR_PROC_X_ENABLE == ENUM_ATTR_PROC_X_ENABLE_ENABLE); define abus_enabled = (ATTR_PROC_A_ENABLE == ENUM_ATTR_PROC_A_ENABLE_ENABLE); define pcie_enabled = (ATTR_PROC_PCIE_ENABLE == ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE); define mcd_hang_poll_bug = (ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG != 0); -define is_naples = (ATTR_CHIP_EC_FEATURE_NAPLES_SPECIFIC !=0); +define nv_present = (ATTR_CHIP_EC_FEATURE_NV_PRESENT != 0); #-------------------------------------------------------------------------------- #-- SCOM initializations @@ -148,31 +148,31 @@ scom 0x04010C0A { #-- PB A Link Mode Register (PB_IOA_MODE / 0x0801080A) scom 0x0801080A { bits, scom_data, expr; - a_avp_mode, 0b0, (abus_enabled) && (!is_naples); #-- A AVP mode + a_avp_mode, 0b0, (abus_enabled) && (!nv_present); #-- A AVP mode } #-- PB A Link Framer Configuration Register (PB_IOA_FMR_CFG / 0x08010813) scom 0x08010813 { bits, scom_data, expr; - a_tod_wait_limit, 0b0001, (abus_enabled) && (!is_naples); #-- A bus TOD wait limit - a_prsp_wait_limit, 0b1000, (abus_enabled) && (!is_naples); #-- A bus presp wait limit - a_cc_wait_limit, 0b1100, (abus_enabled) && (!is_naples); #-- A bus cresp credit wait limit - a0_dc_wait_limit, 0b1100, (abus_enabled) && (!is_naples); #-- A0 bus data credit wait limit - a1_dc_wait_limit, 0b1100, (abus_enabled) && (!is_naples); #-- A1 bus data credit wait limit - a2_dc_wait_limit, 0b1100, (abus_enabled) && (!is_naples); #-- A2 bus data credit wait limit - a_ow_pack, 0b0, (abus_enabled) && (!is_naples); #-- OW pack disabled - a_ow_pack_priority, 0b0, (abus_enabled) && (!is_naples); #-- low priority + a_tod_wait_limit, 0b0001, (abus_enabled) && (!nv_present); #-- A bus TOD wait limit + a_prsp_wait_limit, 0b1000, (abus_enabled) && (!nv_present); #-- A bus presp wait limit + a_cc_wait_limit, 0b1100, (abus_enabled) && (!nv_present); #-- A bus cresp credit wait limit + a0_dc_wait_limit, 0b1100, (abus_enabled) && (!nv_present); #-- A0 bus data credit wait limit + a1_dc_wait_limit, 0b1100, (abus_enabled) && (!nv_present); #-- A1 bus data credit wait limit + a2_dc_wait_limit, 0b1100, (abus_enabled) && (!nv_present); #-- A2 bus data credit wait limit + a_ow_pack, 0b0, (abus_enabled) && (!nv_present); #-- OW pack disabled + a_ow_pack_priority, 0b0, (abus_enabled) && (!nv_present); #-- low priority } #-- PB F Link Mode Register (PB_IOF_MODE / 0x0901080A) scom 0x0901080A { bits, scom_data, expr; - f_avp_mode, 0b0, (pcie_enabled) && (!is_naples); #-- F AVP mode + f_avp_mode, 0b0, (pcie_enabled) && (!nv_present); #-- F AVP mode } #-- PB F Link Framer Configuration Register (PB_IOF_FMR_CFG / 0x09010813) scom 0x09010813 { bits, scom_data, expr; - f_ow_pack, 0b0, (pcie_enabled) && (!is_naples); #-- OW pack disabled - f_ow_pack_priority, 0b0, (pcie_enabled) && (!is_naples); #-- low priority + f_ow_pack, 0b0, (pcie_enabled) && (!nv_present); #-- OW pack disabled + f_ow_pack_priority, 0b0, (pcie_enabled) && (!nv_present); #-- low priority } diff --git a/src/usr/hwpf/hwp/initfiles/p8.pe.phase1.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.pe.phase1.scom.initfile index b49030479..f0d223850 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.pe.phase1.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.pe.phase1.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: p8.pe.phase1.scom.initfile,v 1.6 2013/12/13 02:28:52 ricmata Exp $ +#-- $Id: p8.pe.phase1.scom.initfile,v 1.7 2014/11/18 17:25:31 jmcgill Exp $ #------------------------------------------------------------------------------- #-- #-- (C) Copyright International Business Machines Corp. 2011 @@ -23,7 +23,16 @@ SyntaxVersion = 1 #-- Defines #-------------------------------------------------------------------------------- -define lane32 = (ATTR_CHIP_EC_FEATURE_32_PCIE_LANES != 0); +define iop0 = (ATTR_PROC_PCIE_NUM_IOP >= 1); +define iop1 = (ATTR_PROC_PCIE_NUM_IOP >= 2); +define iop2 = (ATTR_PROC_PCIE_NUM_IOP >= 3); + +define lane_00_07 = (ATTR_PROC_PCIE_NUM_LANES >= 8); +define lane_08_15 = (ATTR_PROC_PCIE_NUM_LANES >= 16); +define lane_16_23 = (ATTR_PROC_PCIE_NUM_LANES >= 24); +define lane_24_31 = (ATTR_PROC_PCIE_NUM_LANES >= 32); +define lane_32_40 = (ATTR_PROC_PCIE_NUM_LANES >= 40); + define zcal_override = (ATTR_CHIP_EC_FEATURE_ZCAL_OVERRIDE != 0); #-------------------------------------------------------------------------------- @@ -36,1220 +45,1220 @@ define zcal_override = (ATTR_CHIP_EC_FEATURE_ZCAL_OVERRIDE != 0); #-- IOP PLL FIR Action0 Register scom 0x09011406 { - bits, scom_data; - 0:63, 0x0000000000000000; + bits, scom_data, expr; + 0:63, 0x0000000000000000, (iop0); } #-- IOP PLL FIR Action1 Register scom 0x09011407 { - bits, scom_data; - 0:63, 0xFF00000000000000; + bits, scom_data, expr; + 0:63, 0xFF00000000000000, (iop0); } #-- IOP PLL FIR Mask Register scom 0x09011403 { - bits, scom_data; - 0:63, 0xFF80000000000000; + bits, scom_data, expr; + 0:63, 0xFF80000000000000, (iop0); } #-- G3 PLL Control Register 0 scom 0x800008010901143F { - bits, scom_data; - 51:63, ATTR_PROC_PCIE_IOP_G3_PLL_CONTROL0[0]; + bits, scom_data, expr; + 51:63, ATTR_PROC_PCIE_IOP_G3_PLL_CONTROL0[0], (iop0); } #-- G2 PLL Control Register 0 scom 0x800008050901143F { - bits, scom_data; - 51:63, ATTR_PROC_PCIE_IOP_G2_PLL_CONTROL0[0]; + bits, scom_data, expr; + 51:63, ATTR_PROC_PCIE_IOP_G2_PLL_CONTROL0[0], (iop0); } #-- PLL Global Control Register 0 scom 0x800008080901143F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0[0]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0[0], (iop0); } #-- PLL Global Control Register 1 scom 0x800008090901143F { - bits, scom_data; - 51:63, ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1[0]; + bits, scom_data, expr; + 51:63, ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1[0], (iop0); } #-- PCS Control Register 0 scom 0x800008800901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_PCS_CONTROL0[0]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_PCS_CONTROL0[0], (iop0); } #-- PCS Control Register 1 scom 0x800008810901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_PCS_CONTROL1[0]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_PCS_CONTROL1[0], (iop0); } #-- TX FIFO Control Register (A0) scom 0x800004000901143F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop0 && lane_00_07); } #-- TX FIFO Control Register (A1) scom 0x800004400901143F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop0 && lane_00_07); } #-- TX FIFO Control Register (A2) scom 0x800004800901143F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop0 && lane_00_07); } #-- TX FIFO Control Register (A3) scom 0x800004C00901143F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop0 && lane_00_07); } #-- TX FIFO Control Register (A4) scom 0x800005000901143F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop0 && lane_00_07); } #-- TX FIFO Control Register (A5) scom 0x800005400901143F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop0 && lane_00_07); } #-- TX FIFO Control Register (A6) scom 0x800005800901143F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop0 && lane_00_07); } #-- TX FIFO Control Register (A7) scom 0x800005C00901143F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop0 && lane_00_07); } #-- TX FIFO Control Register (B0) scom 0x800006000901143F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop0 && lane_08_15); } #-- TX FIFO Control Register (B1) scom 0x800006400901143F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop0 && lane_08_15); } #-- TX FIFO Control Register (B2) scom 0x800006800901143F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop0 && lane_08_15); } #-- TX FIFO Control Register (B3) scom 0x800006C00901143F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop0 && lane_08_15); } #-- TX FIFO Control Register (B4) scom 0x800007000901143F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop0 && lane_08_15); } #-- TX FIFO Control Register (B5) scom 0x800007400901143F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop0 && lane_08_15); } #-- TX FIFO Control Register (B6) scom 0x800007800901143F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop0 && lane_08_15); } #-- TX FIFO Control Register (B7) scom 0x800007C00901143F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop0 && lane_08_15); } #-- TX FIFO Offset Register (A0) scom 0x800004010901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][0]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][0], (iop0 && lane_00_07); } #-- TX FIFO Offset Register (A1) scom 0x800004410901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][1]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][1], (iop0 && lane_00_07); } #-- TX FIFO Offset Register (A2) scom 0x800004810901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][2]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][2], (iop0 && lane_00_07); } #-- TX FIFO Offset Register (A3) scom 0x800004C10901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][3]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][3], (iop0 && lane_00_07); } #-- TX FIFO Offset Register (A4) scom 0x800005010901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][4]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][4], (iop0 && lane_00_07); } #-- TX FIFO Offset Register (A5) scom 0x800005410901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][5]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][5], (iop0 && lane_00_07); } #-- TX FIFO Offset Register (A6) scom 0x800005810901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][6]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][6], (iop0 && lane_00_07); } #-- TX FIFO Offset Register (A7) scom 0x800005C10901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][7]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][7], (iop0 && lane_00_07); } #-- TX FIFO Offset Register (B0) scom 0x800006010901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][8]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][8], (iop0 && lane_08_15); } #-- TX FIFO Offset Register (B1) scom 0x800006410901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][9]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][9], (iop0 && lane_08_15); } #-- TX FIFO Offset Register (B2) scom 0x800006810901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][10]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][10], (iop0 && lane_08_15); } #-- TX FIFO Offset Register (B3) scom 0x800006C10901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][11]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][11], (iop0 && lane_08_15); } #-- TX FIFO Offset Register (B4) scom 0x800007010901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][12]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][12], (iop0 && lane_08_15); } #-- TX FIFO Offset Register (B5) scom 0x800007410901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][13]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][13], (iop0 && lane_08_15); } #-- TX FIFO Offset Register (B6) scom 0x800007810901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][14]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][14], (iop0 && lane_08_15); } #-- TX FIFO Offset Register (B7) scom 0x800007C10901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][15]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][15], (iop0 && lane_08_15); } #-- TX Receiver Detect Control Register (A0) scom 0x800004020901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][0]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][0], (iop0 && lane_00_07); } #-- TX Receiver Detect Control Register (A1) scom 0x800004420901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][1]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][1], (iop0 && lane_00_07); } #-- TX Receiver Detect Control Register (A2) scom 0x800004820901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][2]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][2], (iop0 && lane_00_07); } #-- TX Receiver Detect Control Register (A3) scom 0x800004C20901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][3]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][3], (iop0 && lane_00_07); } #-- TX Receiver Detect Control Register (A4) scom 0x800005020901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][4]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][4], (iop0 && lane_00_07); } #-- TX Receiver Detect Control Register (A5) scom 0x800005420901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][5]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][5], (iop0 && lane_00_07); } #-- TX Receiver Detect Control Register (A6) scom 0x800005820901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][6]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][6], (iop0 && lane_00_07); } #-- TX Receiver Detect Control Register (A7) scom 0x800005C20901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][7]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][7], (iop0 && lane_00_07); } #-- TX Receiver Detect Control Register (B0) scom 0x800006020901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][8]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][8], (iop0 && lane_08_15); } #-- TX Receiver Detect Control Register (B1) scom 0x800006420901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][9]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][9], (iop0 && lane_08_15); } #-- TX Receiver Detect Control Register (B2) scom 0x800006820901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][10]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][10], (iop0 && lane_08_15); } #-- TX Receiver Detect Control Register (B3) scom 0x800006C20901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][11]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][11], (iop0 && lane_08_15); } #-- TX Receiver Detect Control Register (B4) scom 0x800007020901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][12]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][12], (iop0 && lane_08_15); } #-- TX Receiver Detect Control Register (B5) scom 0x800007420901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][13]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][13], (iop0 && lane_08_15); } #-- TX Receiver Detect Control Register (B6) scom 0x800007820901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][14]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][14], (iop0 && lane_08_15); } #-- TX Receiver Detect Control Register (B7) scom 0x800007C20901143F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][15]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][15], (iop0 && lane_08_15); } #-- TX Bandwidth Loss Coefficient Register (A0) scom 0x8000041B0901143F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][0]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][0], (iop0 && lane_00_07); } #-- TX Bandwidth Loss Coefficient Register (A1) scom 0x8000045B0901143F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][1]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][1], (iop0 && lane_00_07); } #-- TX Bandwidth Loss Coefficient Register (A2) scom 0x8000049B0901143F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][2]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][2], (iop0 && lane_00_07); } #-- TX Bandwidth Loss Coefficient Register (A3) scom 0x800004DB0901143F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][3]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][3], (iop0 && lane_00_07); } #-- TX Bandwidth Loss Coefficient Register (A4) scom 0x8000051B0901143F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][4]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][4], (iop0 && lane_00_07); } #-- TX Bandwidth Loss Coefficient Register (A5) scom 0x8000055B0901143F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][5]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][5], (iop0 && lane_00_07); } #-- TX Bandwidth Loss Coefficient Register (A6) scom 0x8000059B0901143F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][6]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][6], (iop0 && lane_00_07); } #-- TX Bandwidth Loss Coefficient Register (A7) scom 0x800005DB0901143F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][7]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][7], (iop0 && lane_00_07); } #-- TX Bandwidth Loss Coefficient Register (B0) scom 0x8000061B0901143F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][8]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][8], (iop0 && lane_08_15); } #-- TX Bandwidth Loss Coefficient Register (B1) scom 0x8000065B0901143F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][9]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][9], (iop0 && lane_08_15); } #-- TX Bandwidth Loss Coefficient Register (B2) scom 0x8000069B0901143F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][10]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][10], (iop0 && lane_08_15); } #-- TX Bandwidth Loss Coefficient Register (B3) scom 0x800006DB0901143F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][11]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][11], (iop0 && lane_08_15); } #-- TX Bandwidth Loss Coefficient Register (B4) scom 0x8000071B0901143F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][12]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][12], (iop0 && lane_08_15); } #-- TX Bandwidth Loss Coefficient Register (B5) scom 0x8000075B0901143F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][13]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][13], (iop0 && lane_08_15); } #-- TX Bandwidth Loss Coefficient Register (B6) scom 0x8000079B0901143F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][14]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][14], (iop0 && lane_08_15); } #-- TX Bandwidth Loss Coefficient Register (B7) scom 0x800007DB0901143F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][15]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][15], (iop0 && lane_08_15); } #-- RX VGA Control Register2 (A0) scom 0x8000000C0901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][0]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][0], (iop0 && lane_00_07); } #-- RX VGA Control Register2 (A1) scom 0x8000004C0901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][1]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][1], (iop0 && lane_00_07); } #-- RX VGA Control Register2 (A2) scom 0x8000008C0901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][2]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][2], (iop0 && lane_00_07); } #-- RX VGA Control Register2 (A3) scom 0x800000CC0901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][3]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][3], (iop0 && lane_00_07); } #-- RX VGA Control Register2 (A4) scom 0x8000010C0901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][4]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][4], (iop0 && lane_00_07); } #-- RX VGA Control Register2 (A5) scom 0x8000014C0901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][5]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][5], (iop0 && lane_00_07); } #-- RX VGA Control Register2 (A6) scom 0x8000018C0901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][6]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][6], (iop0 && lane_00_07); } #-- RX VGA Control Register2 (A7) scom 0x800001CC0901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][7]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][7], (iop0 && lane_00_07); } #-- RX VGA Control Register2 (B0) scom 0x8000020C0901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][8]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][8], (iop0 && lane_08_15); } #-- RX VGA Control Register2 (B1) scom 0x8000024C0901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][9]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][9], (iop0 && lane_08_15); } #-- RX VGA Control Register2 (B2) scom 0x8000028C0901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][10]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][10], (iop0 && lane_08_15); } #-- RX VGA Control Register2 (B3) scom 0x800002CC0901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][11]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][11], (iop0 && lane_08_15); } #-- RX VGA Control Register2 (B4) scom 0x8000030C0901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][12]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][12], (iop0 && lane_08_15); } #-- RX VGA Control Register2 (B5) scom 0x8000034C0901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][13]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][13], (iop0 && lane_08_15); } #-- RX VGA Control Register2 (B6) scom 0x8000038C0901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][14]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][14], (iop0 && lane_08_15); } #-- RX VGA Control Register2 (B7) scom 0x800003CC0901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][15]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][15], (iop0 && lane_08_15); } #-- RX Receiver Peaking Register (A0) scom 0x800000100901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][0]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][0], (iop0 && lane_00_07); } #-- RX Receiver Peaking Register (A1) scom 0x800000500901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][1]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][1], (iop0 && lane_00_07); } #-- RX Receiver Peaking Register (A2) scom 0x800000900901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][2]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][2], (iop0 && lane_00_07); } #-- RX Receiver Peaking Register (A3) scom 0x800000D00901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][3]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][3], (iop0 && lane_00_07); } #-- RX Receiver Peaking Register (A4) scom 0x800001100901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][4]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][4], (iop0 && lane_00_07); } #-- RX Receiver Peaking Register (A5) scom 0x800001500901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][5]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][5], (iop0 && lane_00_07); } #-- RX Receiver Peaking Register (A6) scom 0x800001900901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][6]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][6], (iop0 && lane_00_07); } #-- RX Receiver Peaking Register (A7) scom 0x800001D00901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][7]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][7], (iop0 && lane_00_07); } #-- RX Receiver Peaking Register (B0) scom 0x800002100901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][8]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][8], (iop0 && lane_08_15); } #-- RX Receiver Peaking Register (B1) scom 0x800002500901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][9]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][9], (iop0 && lane_08_15); } #-- RX Receiver Peaking Register (B2) scom 0x800002900901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][10]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][10], (iop0 && lane_08_15); } #-- RX Receiver Peaking Register (B3) scom 0x800002D00901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][11]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][11], (iop0 && lane_08_15); } #-- RX Receiver Peaking Register (B4) scom 0x800003100901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][12]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][12], (iop0 && lane_08_15); } #-- RX Receiver Peaking Register (B5) scom 0x800003500901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][13]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][13], (iop0 && lane_08_15); } #-- RX Receiver Peaking Register (B6) scom 0x800003900901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][14]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][14], (iop0 && lane_08_15); } #-- RX Receiver Peaking Register (B7) scom 0x800003D00901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][15]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][15], (iop0 && lane_08_15); } #-- RX Signal Detect Level Register (A0) scom 0x800000370901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][0]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][0], (iop0 && lane_00_07); } #-- RX Signal Detect Level Register (A1) scom 0x800000770901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][1]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][1], (iop0 && lane_00_07); } #-- RX Signal Detect Level Register (A2) scom 0x800000B70901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][2]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][2], (iop0 && lane_00_07); } #-- RX Signal Detect Level Register (A3) scom 0x800000F70901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][3]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][3], (iop0 && lane_00_07); } #-- RX Signal Detect Level Register (A4) scom 0x800001370901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][4]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][4], (iop0 && lane_00_07); } #-- RX Signal Detect Level Register (A5) scom 0x800001770901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][5]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][5], (iop0 && lane_00_07); } #-- RX Signal Detect Level Register (A6) scom 0x800001B70901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][6]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][6], (iop0 && lane_00_07); } #-- RX Signal Detect Level Register (A7) scom 0x800001F70901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][7]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][7], (iop0 && lane_00_07); } #-- RX Signal Detect Level Register (B0) scom 0x800002370901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][8]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][8], (iop0 && lane_08_15); } #-- RX Signal Detect Level Register (B1) scom 0x800002770901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][9]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][9], (iop0 && lane_08_15); } #-- RX Signal Detect Level Register (B2) scom 0x800002B70901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][10]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][10], (iop0 && lane_08_15); } #-- RX Signal Detect Level Register (B3) scom 0x800002F70901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][11]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][11], (iop0 && lane_08_15); } #-- RX Signal Detect Level Register (B4) scom 0x800003370901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][12]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][12], (iop0 && lane_08_15); } #-- RX Signal Detect Level Register (B5) scom 0x800003770901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][13]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][13], (iop0 && lane_08_15); } #-- RX Signal Detect Level Register (B6) scom 0x800003B70901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][14]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][14], (iop0 && lane_08_15); } #-- RX Signal Detect Level Register (B7) scom 0x800003F70901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][15]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][15], (iop0 && lane_08_15); } #-- TX GEN1 Coefficient Override Register (A0) scom 0x800004100901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][0]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][0], (iop0 && lane_00_07); } #-- TX GEN1 Coefficient Override Register (A1) scom 0x800004500901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][1]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][1], (iop0 && lane_00_07); } #-- TX GEN1 Coefficient Override Register (A2) scom 0x800004900901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][2]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][2], (iop0 && lane_00_07); } #-- TX GEN1 Coefficient Override Register (A3) scom 0x800004D00901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][3]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][3], (iop0 && lane_00_07); } #-- TX GEN1 Coefficient Override Register (A4) scom 0x800005100901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][4]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][4], (iop0 && lane_00_07); } #-- TX GEN1 Coefficient Override Register (A5) scom 0x800005500901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][5]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][5], (iop0 && lane_00_07); } #-- TX GEN1 Coefficient Override Register (A6) scom 0x800005900901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][6]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][6], (iop0 && lane_00_07); } #-- TX GEN1 Coefficient Override Register (A7) scom 0x800005D00901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][7]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][7], (iop0 && lane_00_07); } #-- TX GEN1 Coefficient Override Register (B0) scom 0x800006100901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][8]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][8], (iop0 && lane_08_15); } #-- TX GEN1 Coefficient Override Register (B1) scom 0x800006500901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][9]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][9], (iop0 && lane_08_15); } #-- TX GEN1 Coefficient Override Register (B2) scom 0x800006900901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][10]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][10], (iop0 && lane_08_15); } #-- TX GEN1 Coefficient Override Register (B3) scom 0x800006D00901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][11]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][11], (iop0 && lane_08_15); } #-- TX GEN1 Coefficient Override Register (B4) scom 0x800007100901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][12]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][12], (iop0 && lane_08_15); } #-- TX GEN1 Coefficient Override Register (B5) scom 0x800007500901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][13]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][13], (iop0 && lane_08_15); } #-- TX GEN1 Coefficient Override Register (B6) scom 0x800007900901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][14]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][14], (iop0 && lane_08_15); } #-- TX GEN1 Coefficient Override Register (B7) scom 0x800007D00901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][15]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][15], (iop0 && lane_08_15); } #-- TX GEN2 Coefficient Override Register (A0) scom 0x800004110901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][0]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][0], (iop0 && lane_00_07); } #-- TX GEN2 Coefficient Override Register (A1) scom 0x800004510901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][1]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][1], (iop0 && lane_00_07); } #-- TX GEN2 Coefficient Override Register (A2) scom 0x800004910901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][2]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][2], (iop0 && lane_00_07); } #-- TX GEN2 Coefficient Override Register (A3) scom 0x800004D10901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][3]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][3], (iop0 && lane_00_07); } #-- TX GEN2 Coefficient Override Register (A4) scom 0x800005110901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][4]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][4], (iop0 && lane_00_07); } #-- TX GEN2 Coefficient Override Register (A5) scom 0x800005510901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][5]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][5], (iop0 && lane_00_07); } #-- TX GEN2 Coefficient Override Register (A6) scom 0x800005910901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][6]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][6], (iop0 && lane_00_07); } #-- TX GEN2 Coefficient Override Register (A7) scom 0x800005D10901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][7]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][7], (iop0 && lane_00_07); } #-- TX GEN2 Coefficient Override Register (B0) scom 0x800006110901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][8]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][8], (iop0 && lane_08_15); } #-- TX GEN2 Coefficient Override Register (B1) scom 0x800006510901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][9]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][9], (iop0 && lane_08_15); } #-- TX GEN2 Coefficient Override Register (B2) scom 0x800006910901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][10]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][10], (iop0 && lane_08_15); } #-- TX GEN2 Coefficient Override Register (B3) scom 0x800006D10901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][11]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][11], (iop0 && lane_08_15); } #-- TX GEN1 Coefficient Override Register (B4) scom 0x800007110901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][12]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][12], (iop0 && lane_08_15); } #-- TX GEN2 Coefficient Override Register (B5) scom 0x800007510901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][13]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][13], (iop0 && lane_08_15); } #-- TX GEN2 Coefficient Override Register (B6) scom 0x800007910901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][14]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][14], (iop0 && lane_08_15); } #-- TX GEN2 Coefficient Override Register (B7) scom 0x800007D10901143F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][15]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][15], (iop0 && lane_08_15); } #-- RX Phase Rotator Flywheel Control Register (A0) scom 0x8000002F0901143F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop0 && lane_00_07); } #-- RX Phase Rotator Flywheel Control Register (A1) scom 0x8000006F0901143F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop0 && lane_00_07); } #-- RX Phase Rotator Flywheel Control Register (A2) scom 0x800000AF0901143F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop0 && lane_00_07); } #-- RX Phase Rotator Flywheel Control Register (A3) scom 0x800000EF0901143F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop0 && lane_00_07); } #-- RX Phase Rotator Flywheel Control Register (A4) scom 0x8000012F0901143F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop0 && lane_00_07); } #-- RX Phase Rotator Flywheel Control Register (A5) scom 0x8000016F0901143F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop0 && lane_00_07); } #-- RX Phase Rotator Flywheel Control Register (A6) scom 0x800001AF0901143F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop0 && lane_00_07); } #-- RX Phase Rotator Flywheel Control Register (A7) scom 0x800001EF0901143F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop0 && lane_00_07); } #-- RX Phase Rotator Flywheel Control Register (B0) scom 0x8000022F0901143F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop0 && lane_08_15); } #-- RX Phase Rotator Flywheel Control Register (B1) scom 0x8000026F0901143F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop0 && lane_08_15); } #-- RX Phase Rotator Flywheel Control Register (B2) scom 0x800002AF0901143F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop0 && lane_08_15); } #-- RX Phase Rotator Flywheel Control Register (B3) scom 0x800002EF0901143F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop0 && lane_08_15); } #-- RX Phase Rotator Flywheel Control Register (B4) scom 0x8000032F0901143F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop0 && lane_08_15); } #-- RX Phase Rotator Flywheel Control Register (B5) scom 0x8000036F0901143F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop0 && lane_08_15); } #-- RX Phase Rotator Flywheel Control Register (B6) scom 0x800003AF0901143F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop0 && lane_08_15); } #-- RX Phase Rotator Flywheel Control Register (B7) scom 0x800003EF0901143F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop0 && lane_08_15); } #-- DFE Function Control Register 1 (A0) scom 0x8000001F0901143F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop0 && lane_00_07); } #-- DFE Function Control Register 1 (A1) scom 0x8000005F0901143F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop0 && lane_00_07); } #-- DFE Function Control Register 1 (A2) scom 0x8000009F0901143F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop0 && lane_00_07); } #-- DFE Function Control Register 1 (A3) scom 0x800000DF0901143F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop0 && lane_00_07); } #-- DFE Function Control Register 1 (A4) scom 0x8000011F0901143F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop0 && lane_00_07); } #-- DFE Function Control Register 1 (A5) scom 0x8000015F0901143F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop0 && lane_00_07); } #-- DFE Function Control Register 1 (A6) scom 0x8000019F0901143F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop0 && lane_00_07); } #-- DFE Function Control Register 1 (A7) scom 0x800001DF0901143F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop0 && lane_00_07); } #-- DFE Function Control Register 1 (B0) scom 0x8000021F0901143F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop0 && lane_08_15); } #-- DFE Function Control Register 1 (B1) scom 0x8000025F0901143F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop0 && lane_08_15); } #-- DFE Function Control Register 1 (B2) scom 0x8000029F0901143F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop0 && lane_08_15); } #-- DFE Function Control Register 1 (B3) scom 0x800002DF0901143F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop0 && lane_08_15); } #-- DFE Function Control Register 1 (B4) scom 0x8000031F0901143F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop0 && lane_08_15); } #-- DFE Function Control Register 1 (B5) scom 0x8000035F0901143F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop0 && lane_08_15); } #-- DFE Function Control Register 1 (B6) scom 0x8000039F0901143F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop0 && lane_08_15); } #-- DFE Function Control Register 1 (B7) scom 0x800003DF0901143F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop0 && lane_08_15); } #-- Receiver Configuration Mode Register (A0) scom 0x800000000901143F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop0 && lane_00_07); } #-- Receiver Configuration Mode Register (A1) scom 0x800000400901143F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop0 && lane_00_07); } #-- Receiver Configuration Mode Register (A2) scom 0x800000800901143F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop0 && lane_00_07); } #-- Receiver Configuration Mode Register (A3) scom 0x800000C00901143F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop0 && lane_00_07); } #-- Receiver Configuration Mode Register (A4) scom 0x800001000901143F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop0 && lane_00_07); } #-- Receiver Configuration Mode Register (A5) scom 0x800001400901143F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop0 && lane_00_07); } #-- Receiver Configuration Mode Register (A6) scom 0x800001800901143F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop0 && lane_00_07); } #-- Receiver Configuration Mode Register (A7) scom 0x800001C00901143F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop0 && lane_00_07); } #-- Receiver Configuration Mode Register (B0) scom 0x800002000901143F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop0 && lane_08_15); } #-- Receiver Configuration Mode Register (B1) scom 0x800002400901143F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop0 && lane_08_15); } #-- Receiver Configuration Mode Register (B2) scom 0x800002800901143F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop0 && lane_08_15); } #-- Receiver Configuration Mode Register (B3) scom 0x800002C00901143F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop0 && lane_08_15); } #-- Receiver Configuration Mode Register (B4) scom 0x800003000901143F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop0 && lane_08_15); } #-- Receiver Configuration Mode Register (B5) scom 0x800003400901143F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop0 && lane_08_15); } #-- Receiver Configuration Mode Register (B6) scom 0x800003800901143F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop0 && lane_08_15); } #-- Receiver Configuration Mode Register (B7) scom 0x800003C00901143F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop0 && lane_08_15); } #-- ZCAL Control Register scom 0x800008400901143F { - bits, scom_data; - 53:60, ATTR_PROC_PCIE_IOP_ZCAL_CONTROL[0]; + bits, scom_data, expr; + 53:60, ATTR_PROC_PCIE_IOP_ZCAL_CONTROL[0], (iop0); } #-- ZCAL Override Register scom 0x800008420901143F { - bits, scom_data, expr; - 48:63, 0xEC30, (zcal_override); + bits, scom_data, expr; + 48:63, 0xEC30, (iop0 && zcal_override); } @@ -1259,1218 +1268,1865 @@ scom 0x800008420901143F { #-- IOP PLL FIR Action0 Register scom 0x09011846 { - bits, scom_data; - 0:63, 0x0000000000000000; + bits, scom_data, expr; + 0:63, 0x0000000000000000, (iop1); } #-- IOP PLL FIR Action1 Register scom 0x09011847 { - bits, scom_data; - 0:63, 0xFF00000000000000; + bits, scom_data, expr; + 0:63, 0xFF00000000000000, (iop1); } #-- IOP PLL FIR Mask Register scom 0x09011843 { - bits, scom_data; - 0:63, 0xFF80000000000000; + bits, scom_data expr; + 0:63, 0xFF80000000000000, (iop1); } #-- G3 PLL Control Register 0 scom 0x800008010901187F { - bits, scom_data; - 51:63, ATTR_PROC_PCIE_IOP_G3_PLL_CONTROL0[1]; + bits, scom_data, expr; + 51:63, ATTR_PROC_PCIE_IOP_G3_PLL_CONTROL0[1], (iop1); } #-- G2 PLL Control Register 0 scom 0x800008050901187F { - bits, scom_data; - 51:63, ATTR_PROC_PCIE_IOP_G2_PLL_CONTROL0[1]; + bits, scom_data, expr; + 51:63, ATTR_PROC_PCIE_IOP_G2_PLL_CONTROL0[1], (iop1); } #-- PLL Global Control Register 0 scom 0x800008080901187F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0[1]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0[1], (iop1); } #-- PLL Global Control Register 1 scom 0x800008090901187F { - bits, scom_data; - 51:63, ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1[1]; + bits, scom_data, expr; + 51:63, ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1[1], (iop1); } #-- PCS Control Register 0 scom 0x800008800901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_PCS_CONTROL0[1]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_PCS_CONTROL0[1], (iop1); } #-- PCS Control Register 1 scom 0x800008810901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_PCS_CONTROL1[1]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_PCS_CONTROL1[1], (iop1); } #-- TX FIFO Control Register (A0) scom 0x800004000901187F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop1 && lane_16_23); } #-- TX FIFO Control Register (A1) scom 0x800004400901187F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop1 && lane_16_23); } #-- TX FIFO Control Register (A2) scom 0x800004800901187F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop1 && lane_16_23); } #-- TX FIFO Control Register (A3) scom 0x800004C00901187F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop1 && lane_16_23); } #-- TX FIFO Control Register (A4) scom 0x800005000901187F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop1 && lane_16_23); } #-- TX FIFO Control Register (A5) scom 0x800005400901187F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop1 && lane_16_23); } #-- TX FIFO Control Register (A6) scom 0x800005800901187F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop1 && lane_16_23); } #-- TX FIFO Control Register (A7) scom 0x800005C00901187F { - bits, scom_data; - 53:56, 0b1111; + bits, scom_data, expr; + 53:56, 0b1111, (iop1 && lane_16_23); } #-- TX FIFO Control Register (B0) scom 0x800006000901187F { - bits, scom_data, expr; - 53:56, 0b1111, (lane32); + bits, scom_data, expr; + 53:56, 0b1111, (iop1 && lane_24_31); } #-- TX FIFO Control Register (B1) scom 0x800006400901187F { - bits, scom_data, expr; - 53:56, 0b1111, (lane32); + bits, scom_data, expr; + 53:56, 0b1111, (iop1 && lane_24_31); } #-- TX FIFO Control Register (B2) scom 0x800006800901187F { - bits, scom_data, expr; - 53:56, 0b1111, (lane32); + bits, scom_data, expr; + 53:56, 0b1111, (iop1 && lane_24_31); } #-- TX FIFO Control Register (B3) scom 0x800006C00901187F { - bits, scom_data, expr; - 53:56, 0b1111, (lane32); + bits, scom_data, expr; + 53:56, 0b1111, (iop1 && lane_24_31); } #-- TX FIFO Control Register (B4) scom 0x800007000901187F { - bits, scom_data, expr; - 53:56, 0b1111, (lane32); + bits, scom_data, expr; + 53:56, 0b1111, (iop1 && lane_24_31); } #-- TX FIFO Control Register (B5) scom 0x800007400901187F { - bits, scom_data, expr; - 53:56, 0b1111, (lane32); + bits, scom_data, expr; + 53:56, 0b1111, (iop1 && lane_24_31); } #-- TX FIFO Control Register (B6) scom 0x800007800901187F { - bits, scom_data, expr; - 53:56, 0b1111, (lane32); + bits, scom_data, expr; + 53:56, 0b1111, (iop1 && lane_24_31); } #-- TX FIFO Control Register (B7) scom 0x800007C00901187F { - bits, scom_data, expr; - 53:56, 0b1111, (lane32); + bits, scom_data, expr; + 53:56, 0b1111, (iop1 && lane_24_31); } #-- TX FIFO Offset Register (A0) scom 0x800004010901187F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][0]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][0], (iop1 && lane_16_23); } #-- TX FIFO Offset Register (A1) scom 0x800004410901187F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][1]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][1], (iop1 && lane_16_23); } #-- TX FIFO Offset Register (A2) scom 0x800004810901187F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][2]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][2], (iop1 && lane_16_23); } #-- TX FIFO Offset Register (A3) scom 0x800004C10901187F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][3]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][3], (iop1 && lane_16_23); } #-- TX FIFO Offset Register (A4) scom 0x800005010901187F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][4]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][4], (iop1 && lane_16_23); } #-- TX FIFO Offset Register (A5) scom 0x800005410901187F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][5]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][5], (iop1 && lane_16_23); } #-- TX FIFO Offset Register (A6) scom 0x800005810901187F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][6]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][6], (iop1 && lane_16_23); } #-- TX FIFO Offset Register (A7) scom 0x800005C10901187F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][7]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][7], (iop1 && lane_16_23); } #-- TX FIFO Offset Register (B0) scom 0x800006010901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][8], (lane32); + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][8], (iop1 && lane_24_31); } #-- TX FIFO Offset Register (B1) scom 0x800006410901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][9], (lane32); + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][9], (iop1 && lane_24_31); } #-- TX FIFO Offset Register (B2) scom 0x800006810901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][10], (lane32); + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][10], (iop1 && lane_24_31); } #-- TX FIFO Offset Register (B3) scom 0x800006C10901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][11], (lane32); + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][11], (iop1 && lane_24_31); } #-- TX FIFO Offset Register (B4) scom 0x800007010901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][12], (lane32); + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][12], (iop1 && lane_24_31); } #-- TX FIFO Offset Register (B5) scom 0x800007410901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][13], (lane32); + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][13], (iop1 && lane_24_31); } #-- TX FIFO Offset Register (B6) scom 0x800007810901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][14], (lane32); + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][14], (iop1 && lane_24_31); } #-- TX FIFO Offset Register (B7) scom 0x800007C10901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][15], (lane32); + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][15], (iop1 && lane_24_31); } #-- TX Receiver Detect Control Register (A0) scom 0x800004020901187F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][0]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][0], (iop1 && lane_16_23); } #-- TX Receiver Detect Control Register (A1) scom 0x800004420901187F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][1]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][1], (iop1 && lane_16_23); } #-- TX Receiver Detect Control Register (A2) scom 0x800004820901187F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][2]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][2], (iop1 && lane_16_23); } #-- TX Receiver Detect Control Register (A3) scom 0x800004C20901187F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][3]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][3], (iop1 && lane_16_23); } #-- TX Receiver Detect Control Register (A4) scom 0x800005020901187F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][4]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][4], (iop1 && lane_16_23); } #-- TX Receiver Detect Control Register (A5) scom 0x800005420901187F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][5]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][5], (iop1 && lane_16_23); } #-- TX Receiver Detect Control Register (A6) scom 0x800005820901187F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][6]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][6], (iop1 && lane_16_23); } #-- TX Receiver Detect Control Register (A7) scom 0x800005C20901187F { - bits, scom_data; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][7]; + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][7], (iop1 && lane_16_23); } #-- TX Receiver Detect Control Register (B0) scom 0x800006020901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][8], (lane32); + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][8], (iop1 && lane_24_31); } #-- TX Receiver Detect Control Register (B1) scom 0x800006420901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][9], (lane32); + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][9], (iop1 && lane_24_31); } #-- TX Receiver Detect Control Register (B2) scom 0x800006820901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][10], (lane32); + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][10], (iop1 && lane_24_31); } #-- TX Receiver Detect Control Register (B3) scom 0x800006C20901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][11], (lane32); + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][11], (iop1 && lane_24_31); } #-- TX Receiver Detect Control Register (B4) scom 0x800007020901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][12], (lane32); + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][12], (iop1 && lane_24_31); } #-- TX Receiver Detect Control Register (B5) scom 0x800007420901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][13], (lane32); + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][13], (iop1 && lane_24_31); } #-- TX Receiver Detect Control Register (B6) scom 0x800007820901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][14], (lane32); + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][14], (iop1 && lane_24_31); } #-- TX Receiver Detect Control Register (B7) scom 0x800007C20901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][15], (lane32); + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][15], (iop1 && lane_24_31); } #-- TX Bandwidth Loss Coefficient Register (A0) scom 0x8000041B0901187F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][0]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][0], (iop1 && lane_16_23); } #-- TX Bandwidth Loss Coefficient Register (A1) scom 0x8000045B0901187F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][1]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][1], (iop1 && lane_16_23); } #-- TX Bandwidth Loss Coefficient Register (A2) scom 0x8000049B0901187F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][2]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][2], (iop1 && lane_16_23); } #-- TX Bandwidth Loss Coefficient Register (A3) scom 0x800004DB0901187F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][3]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][3], (iop1 && lane_16_23); } #-- TX Bandwidth Loss Coefficient Register (A4) scom 0x8000051B0901187F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][4]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][4], (iop1 && lane_16_23); } #-- TX Bandwidth Loss Coefficient Register (A5) scom 0x8000055B0901187F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][5]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][5], (iop1 && lane_16_23); } #-- TX Bandwidth Loss Coefficient Register (A6) scom 0x8000059B0901187F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][6]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][6], (iop1 && lane_16_23); } #-- TX Bandwidth Loss Coefficient Register (A7) scom 0x800005DB0901187F { - bits, scom_data; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][7]; + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][7], (iop1 && lane_16_23); } #-- TX Bandwidth Loss Coefficient Register (B0) scom 0x8000061B0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][8], (lane32); + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][8], (iop1 && lane_24_31); } #-- TX Bandwidth Loss Coefficient Register (B1) scom 0x8000065B0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][9], (lane32); + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][9], (iop1 && lane_24_31); } #-- TX Bandwidth Loss Coefficient Register (B2) scom 0x8000069B0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][10], (lane32); + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][10], (iop1 && lane_24_31); } #-- TX Bandwidth Loss Coefficient Register (B3) scom 0x800006DB0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][11], (lane32); + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][11], (iop1 && lane_24_31); } #-- TX Bandwidth Loss Coefficient Register (B4) scom 0x8000071B0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][12], (lane32); + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][12], (iop1 && lane_24_31); } #-- TX Bandwidth Loss Coefficient Register (B5) scom 0x8000075B0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][13], (lane32); + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][13], (iop1 && lane_24_31); } #-- TX Bandwidth Loss Coefficient Register (B6) scom 0x8000079B0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][14], (lane32); + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][14], (iop1 && lane_24_31); } #-- TX Bandwidth Loss Coefficient Register (B7) scom 0x800007DB0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][15], (lane32); + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][15], (iop1 && lane_24_31); } #-- RX VGA Control Register2 (A0) scom 0x8000000C0901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][0]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][0], (iop1 && lane_16_23); } #-- RX VGA Control Register2 (A1) scom 0x8000004C0901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][1]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][1], (iop1 && lane_16_23); } #-- RX VGA Control Register2 (A2) scom 0x8000008C0901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][2]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][2], (iop1 && lane_16_23); } #-- RX VGA Control Register2 (A3) scom 0x800000CC0901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][3]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][3], (iop1 && lane_16_23); } #-- RX VGA Control Register2 (A4) scom 0x8000010C0901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][4]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][4], (iop1 && lane_16_23); } #-- RX VGA Control Register2 (A5) scom 0x8000014C0901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][5]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][5], (iop1 && lane_16_23); } #-- RX VGA Control Register2 (A6) scom 0x8000018C0901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][6]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][6], (iop1 && lane_16_23); } #-- RX VGA Control Register2 (A7) scom 0x800001CC0901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][7]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][7], (iop1 && lane_16_23); } #-- RX VGA Control Register2 (B0) scom 0x8000020C0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][8], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][8], (iop1 && lane_24_31); } #-- RX VGA Control Register2 (B1) scom 0x8000024C0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][9], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][9], (iop1 && lane_24_31); } #-- RX VGA Control Register2 (B2) scom 0x8000028C0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][10], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][10], (iop1 && lane_24_31); } #-- RX VGA Control Register2 (B3) scom 0x800002CC0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][11], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][11], (iop1 && lane_24_31); } #-- RX VGA Control Register2 (B4) scom 0x8000030C0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][12], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][12], (iop1 && lane_24_31); } #-- RX VGA Control Register2 (B5) scom 0x8000034C0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][13], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][13], (iop1 && lane_24_31); } #-- RX VGA Control Register2 (B6) scom 0x8000038C0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][14], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][14], (iop1 && lane_24_31); } #-- RX VGA Control Register2 (B7) scom 0x800003CC0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][15], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][15], (iop1 && lane_24_31); } #-- RX Receiver Peaking Register (A0) scom 0x800000100901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][0]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][0], (iop1 && lane_16_23); } #-- RX Receiver Peaking Register (A1) scom 0x800000500901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][1]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][1], (iop1 && lane_16_23); } #-- RX Receiver Peaking Register (A2) scom 0x800000900901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][2]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][2], (iop1 && lane_16_23); } #-- RX Receiver Peaking Register (A3) scom 0x800000D00901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][3]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][3], (iop1 && lane_16_23); } #-- RX Receiver Peaking Register (A4) scom 0x800001100901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][4]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][4], (iop1 && lane_16_23); } #-- RX Receiver Peaking Register (A5) scom 0x800001500901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][5]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][5], (iop1 && lane_16_23); } #-- RX Receiver Peaking Register (A6) scom 0x800001900901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][6]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][6], (iop1 && lane_16_23); } #-- RX Receiver Peaking Register (A7) scom 0x800001D00901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][7]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][7], (iop1 && lane_16_23); } #-- RX Receiver Peaking Register (B0) scom 0x800002100901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][8], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][8], (iop1 && lane_24_31); } #-- RX Receiver Peaking Register (B1) scom 0x800002500901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][9], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][9], (iop1 && lane_24_31); } #-- RX Receiver Peaking Register (B2) scom 0x800002900901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][10], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][10], (iop1 && lane_24_31); } #-- RX Receiver Peaking Register (B3) scom 0x800002D00901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][11], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][11], (iop1 && lane_24_31); } #-- RX Receiver Peaking Register (B4) scom 0x800003100901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][12], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][12], (iop1 && lane_24_31); } #-- RX Receiver Peaking Register (B5) scom 0x800003500901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][13], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][13], (iop1 && lane_24_31); } #-- RX Receiver Peaking Register (B6) scom 0x800003900901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][14], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][14], (iop1 && lane_24_31); } #-- RX Receiver Peaking Register (B7) scom 0x800003D00901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][15], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][15], (iop1 && lane_24_31); } #-- RX Signal Detect Level Register (A0) scom 0x800000370901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][0]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][0], (iop1 && lane_16_23); } #-- RX Signal Detect Level Register (A1) scom 0x800000770901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][1]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][1], (iop1 && lane_16_23); } #-- RX Signal Detect Level Register (A2) scom 0x800000B70901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][2]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][2], (iop1 && lane_16_23); } #-- RX Signal Detect Level Register (A3) scom 0x800000F70901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][3]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][3], (iop1 && lane_16_23); } #-- RX Signal Detect Level Register (A4) scom 0x800001370901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][4]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][4], (iop1 && lane_16_23); } #-- RX Signal Detect Level Register (A5) scom 0x800001770901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][5]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][5], (iop1 && lane_16_23); } #-- RX Signal Detect Level Register (A6) scom 0x800001B70901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][6]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][6], (iop1 && lane_16_23); } #-- RX Signal Detect Level Register (A7) scom 0x800001F70901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][7]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][7], (iop1 && lane_16_23); } #-- RX Signal Detect Level Register (B0) scom 0x800002370901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][8], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][8], (iop1 && lane_24_31); } #-- RX Signal Detect Level Register (B1) scom 0x800002770901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][9], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][9], (iop1 && lane_24_31); } #-- RX Signal Detect Level Register (B2) scom 0x800002B70901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][10], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][10], (iop1 && lane_24_31); } #-- RX Signal Detect Level Register (B3) scom 0x800002F70901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][11], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][11], (iop1 && lane_24_31); } #-- RX Signal Detect Level Register (B4) scom 0x800003370901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][12], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][12], (iop1 && lane_24_31); } #-- RX Signal Detect Level Register (B5) scom 0x800003770901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][13], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][13], (iop1 && lane_24_31); } #-- RX Signal Detect Level Register (B6) scom 0x800003B70901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][14], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][14], (iop1 && lane_24_31); } #-- RX Signal Detect Level Register (B7) scom 0x800003F70901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][15], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][15], (iop1 && lane_24_31); } #-- TX GEN1 Coefficient Override Register (A0) scom 0x800004100901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][0]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][0], (iop1 && lane_16_23); } #-- TX GEN1 Coefficient Override Register (A1) scom 0x800004500901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][1]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][1], (iop1 && lane_16_23); } #-- TX GEN1 Coefficient Override Register (A2) scom 0x800004900901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][2]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][2], (iop1 && lane_16_23); } #-- TX GEN1 Coefficient Override Register (A3) scom 0x800004D00901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][3]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][3], (iop1 && lane_16_23); } #-- TX GEN1 Coefficient Override Register (A4) scom 0x800005100901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][4]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][4], (iop1 && lane_16_23); } #-- TX GEN1 Coefficient Override Register (A5) scom 0x800005500901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][5]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][5], (iop1 && lane_16_23); } #-- TX GEN1 Coefficient Override Register (A6) scom 0x800005900901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][6]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][6], (iop1 && lane_16_23); } #-- TX GEN1 Coefficient Override Register (A7) scom 0x800005D00901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][7]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][7], (iop1 && lane_16_23); } #-- TX GEN1 Coefficient Override Register (B0) scom 0x800006100901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][8], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][8], (iop1 && lane_24_31); } #-- TX GEN1 Coefficient Override Register (B1) scom 0x800006500901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][9], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][9], (iop1 && lane_24_31); } #-- TX GEN1 Coefficient Override Register (B2) scom 0x800006900901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][10], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][10], (iop1 && lane_24_31); } #-- TX GEN1 Coefficient Override Register (B3) scom 0x800006D00901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][11], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][11], (iop1 && lane_24_31); } #-- TX GEN1 Coefficient Override Register (B4) scom 0x800007100901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][12], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][12], (iop1 && lane_24_31); } #-- TX GEN1 Coefficient Override Register (B5) scom 0x800007500901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][13], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][13], (iop1 && lane_24_31); } #-- TX GEN1 Coefficient Override Register (B6) scom 0x800007900901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][14], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][14], (iop1 && lane_24_31); } #-- TX GEN1 Coefficient Override Register (B7) scom 0x800007D00901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][15], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][15], (iop1 && lane_24_31); } #-- TX GEN2 Coefficient Override Register (A0) scom 0x800004110901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][0]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][0], (iop1 && lane_16_23); } #-- TX GEN2 Coefficient Override Register (A1) scom 0x800004510901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][1]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][1], (iop1 && lane_16_23); } #-- TX GEN2 Coefficient Override Register (A2) scom 0x800004910901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][2]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][2], (iop1 && lane_16_23); } #-- TX GEN2 Coefficient Override Register (A3) scom 0x800004D10901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][3]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][3], (iop1 && lane_16_23); } #-- TX GEN2 Coefficient Override Register (A4) scom 0x800005110901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][4]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][4], (iop1 && lane_16_23); } #-- TX GEN2 Coefficient Override Register (A5) scom 0x800005510901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][5]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][5], (iop1 && lane_16_23); } #-- TX GEN2 Coefficient Override Register (A6) scom 0x800005910901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][6]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][6], (iop1 && lane_16_23); } #-- TX GEN2 Coefficient Override Register (A7) scom 0x800005D10901187F { - bits, scom_data; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][7]; + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][7], (iop1 && lane_16_23); } #-- TX GEN2 Coefficient Override Register (B0) scom 0x800006110901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][8], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][8], (iop1 && lane_24_31); } #-- TX GEN2 Coefficient Override Register (B1) scom 0x800006510901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][9], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][9], (iop1 && lane_24_31); } #-- TX GEN2 Coefficient Override Register (B2) scom 0x800006910901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][10], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][10], (iop1 && lane_24_31); } #-- TX GEN2 Coefficient Override Register (B3) scom 0x800006D10901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][11], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][11], (iop1 && lane_24_31); } #-- TX GEN1 Coefficient Override Register (B4) scom 0x800007110901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][12], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][12], (iop1 && lane_24_31); } #-- TX GEN2 Coefficient Override Register (B5) scom 0x800007510901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][13], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][13], (iop1 && lane_24_31); } #-- TX GEN2 Coefficient Override Register (B6) scom 0x800007910901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][14], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][14], (iop1 && lane_24_31); } #-- TX GEN2 Coefficient Override Register (B7) scom 0x800007D10901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][15], (lane32); + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][15], (iop1 && lane_24_31); } #-- RX Phase Rotator Flywheel Control Register (A0) scom 0x8000002F0901187F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop1 && lane_16_23); } #-- RX Phase Rotator Flywheel Control Register (A1) scom 0x8000006F0901187F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop1 && lane_16_23); } #-- RX Phase Rotator Flywheel Control Register (A2) scom 0x800000AF0901187F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop1 && lane_16_23); } #-- RX Phase Rotator Flywheel Control Register (A3) scom 0x800000EF0901187F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop1 && lane_16_23); } #-- RX Phase Rotator Flywheel Control Register (A4) scom 0x8000012F0901187F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop1 && lane_16_23); } #-- RX Phase Rotator Flywheel Control Register (A5) scom 0x8000016F0901187F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop1 && lane_16_23); } #-- RX Phase Rotator Flywheel Control Register (A6) scom 0x800001AF0901187F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop1 && lane_16_23); } #-- RX Phase Rotator Flywheel Control Register (A7) scom 0x800001EF0901187F { - bits, scom_data; - 56:59, 0b1110; + bits, scom_data, expr; + 56:59, 0b1110, (iop1 && lane_16_23); } #-- RX Phase Rotator Flywheel Control Register (B0) scom 0x8000022F0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (lane32); + bits, scom_data, expr; + 56:59, 0b1110, (iop1 && lane_24_31); } #-- RX Phase Rotator Flywheel Control Register (B1) scom 0x8000026F0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (lane32); + bits, scom_data, expr; + 56:59, 0b1110, (iop1 && lane_24_31); } #-- RX Phase Rotator Flywheel Control Register (B2) scom 0x800002AF0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (lane32); + bits, scom_data, expr; + 56:59, 0b1110, (iop1 && lane_24_31); } #-- RX Phase Rotator Flywheel Control Register (B3) scom 0x800002EF0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (lane32); + bits, scom_data, expr; + 56:59, 0b1110, (iop1 && lane_24_31); } #-- RX Phase Rotator Flywheel Control Register (B4) scom 0x8000032F0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (lane32); + bits, scom_data, expr; + 56:59, 0b1110, (iop1 && lane_24_31); } #-- RX Phase Rotator Flywheel Control Register (B5) scom 0x8000036F0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (lane32); + bits, scom_data, expr; + 56:59, 0b1110, (iop1 && lane_24_31); } #-- RX Phase Rotator Flywheel Control Register (B6) scom 0x800003AF0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (lane32); + bits, scom_data, expr; + 56:59, 0b1110, (iop1 && lane_24_31); } #-- RX Phase Rotator Flywheel Control Register (B7) scom 0x800003EF0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (lane32); + bits, scom_data, expr; + 56:59, 0b1110, (iop1 && lane_24_31); } #-- DFE Function Control Register 1 (A0) scom 0x8000001F0901187F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop1 && lane_16_23); } #-- DFE Function Control Register 1 (A1) scom 0x8000005F0901187F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop1 && lane_16_23); } #-- DFE Function Control Register 1 (A2) scom 0x8000009F0901187F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop1 && lane_16_23); } #-- DFE Function Control Register 1 (A3) scom 0x800000DF0901187F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop1 && lane_16_23); } #-- DFE Function Control Register 1 (A4) scom 0x8000011F0901187F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop1 && lane_16_23); } #-- DFE Function Control Register 1 (A5) scom 0x8000015F0901187F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop1 && lane_16_23); } #-- DFE Function Control Register 1 (A6) scom 0x8000019F0901187F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop1 && lane_16_23); } #-- DFE Function Control Register 1 (A7) scom 0x800001DF0901187F { - bits, scom_data; - 49, 0b0; + bits, scom_data, expr; + 49, 0b0, (iop1 && lane_16_23); } #-- DFE Function Control Register 1 (B0) scom 0x8000021F0901187F { - bits, scom_data, expr; - 49, 0b0, (lane32); + bits, scom_data, expr; + 49, 0b0, (iop1 && lane_24_31); } #-- DFE Function Control Register 1 (B1) scom 0x8000025F0901187F { - bits, scom_data, expr; - 49, 0b0, (lane32); + bits, scom_data, expr; + 49, 0b0, (iop1 && lane_24_31); } #-- DFE Function Control Register 1 (B2) scom 0x8000029F0901187F { - bits, scom_data, expr; - 49, 0b0, (lane32); + bits, scom_data, expr; + 49, 0b0, (iop1 && lane_24_31); } #-- DFE Function Control Register 1 (B3) scom 0x800002DF0901187F { - bits, scom_data, expr; - 49, 0b0, (lane32); + bits, scom_data, expr; + 49, 0b0, (iop1 && lane_24_31); } #-- DFE Function Control Register 1 (B4) scom 0x8000031F0901187F { - bits, scom_data, expr; - 49, 0b0, (lane32); + bits, scom_data, expr; + 49, 0b0, (iop1 && lane_24_31); } #-- DFE Function Control Register 1 (B5) scom 0x8000035F0901187F { - bits, scom_data, expr; - 49, 0b0, (lane32); + bits, scom_data, expr; + 49, 0b0, (iop1 && lane_24_31); } #-- DFE Function Control Register 1 (B6) scom 0x8000039F0901187F { - bits, scom_data, expr; - 49, 0b0, (lane32); + bits, scom_data, expr; + 49, 0b0, (iop1 && lane_24_31); } #-- DFE Function Control Register 1 (B7) scom 0x800003DF0901187F { - bits, scom_data, expr; - 49, 0b0, (lane32); + bits, scom_data, expr; + 49, 0b0, (iop1 && lane_24_31); } #-- Receiver Configuration Mode Register (A0) scom 0x800000000901187F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop1 && lane_16_23); } #-- Receiver Configuration Mode Register (A1) scom 0x800000400901187F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop1 && lane_16_23); } #-- Receiver Configuration Mode Register (A2) scom 0x800000800901187F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop1 && lane_16_23); } #-- Receiver Configuration Mode Register (A3) scom 0x800000C00901187F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop1 && lane_16_23); } #-- Receiver Configuration Mode Register (A4) scom 0x800001000901187F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop1 && lane_16_23); } #-- Receiver Configuration Mode Register (A5) scom 0x800001400901187F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop1 && lane_16_23); } #-- Receiver Configuration Mode Register (A6) scom 0x800001800901187F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop1 && lane_16_23); } #-- Receiver Configuration Mode Register (A7) scom 0x800001C00901187F { - bits, scom_data; - 49, 0b1; + bits, scom_data, expr; + 49, 0b1, (iop1 && lane_16_23); } #-- Receiver Configuration Mode Register (B0) scom 0x800002000901187F { - bits, scom_data, expr; - 49, 0b1, (lane32); + bits, scom_data, expr; + 49, 0b1, (iop1 && lane_24_31); } #-- Receiver Configuration Mode Register (B1) scom 0x800002400901187F { - bits, scom_data, expr; - 49, 0b1, (lane32); + bits, scom_data, expr; + 49, 0b1, (iop1 && lane_24_31); } #-- Receiver Configuration Mode Register (B2) scom 0x800002800901187F { - bits, scom_data, expr; - 49, 0b1, (lane32); + bits, scom_data, expr; + 49, 0b1, (iop1 && lane_24_31); } #-- Receiver Configuration Mode Register (B3) scom 0x800002C00901187F { - bits, scom_data, expr; - 49, 0b1, (lane32); + bits, scom_data, expr; + 49, 0b1, (iop1 && lane_24_31); } #-- Receiver Configuration Mode Register (B4) scom 0x800003000901187F { - bits, scom_data, expr; - 49, 0b1, (lane32); + bits, scom_data, expr; + 49, 0b1, (iop1 && lane_24_31); } #-- Receiver Configuration Mode Register (B5) scom 0x800003400901187F { - bits, scom_data, expr; - 49, 0b1, (lane32); + bits, scom_data, expr; + 49, 0b1, (iop1 && lane_24_31); } #-- Receiver Configuration Mode Register (B6) scom 0x800003800901187F { - bits, scom_data, expr; - 49, 0b1, (lane32); + bits, scom_data, expr; + 49, 0b1, (iop1 && lane_24_31); } #-- Receiver Configuration Mode Register (B7) scom 0x800003C00901187F { - bits, scom_data, expr; - 49, 0b1, (lane32); + bits, scom_data, expr; + 49, 0b1, (iop1 && lane_24_31); } #-- ZCAL Control Register scom 0x800008400901187F { - bits, scom_data; - 53:60, ATTR_PROC_PCIE_IOP_ZCAL_CONTROL[1]; + bits, scom_data, expr; + 53:60, ATTR_PROC_PCIE_IOP_ZCAL_CONTROL[1], (iop1); } #-- ZCAL Override Register scom 0x800008420901187F { - bits, scom_data, expr; - 48:63, 0xEC30, (zcal_override); + bits, scom_data, expr; + 48:63, 0xEC30, (iop1 && zcal_override); +} + + +#-- +#-- IOP 2 +#-- + +#-- IOP PLL FIR Action0 Register +scom 0x09011C46 { + bits, scom_data, expr; + 0:63, 0x0000000000000000, (iop2); +} + +#-- IOP PLL FIR Action1 Register +scom 0x09011C47 { + bits, scom_data, expr; + 0:63, 0xFF00000000000000, (iop2); +} + +#-- IOP PLL FIR Mask Register +scom 0x09011C43 { + bits, scom_data, expr; + 0:63, 0xFF80000000000000, (iop2); +} + +#-- G3 PLL Control Register 0 +scom 0x8000080109011C7F { + bits, scom_data, expr; + 51:63, ATTR_PROC_PCIE_IOP_G3_PLL_CONTROL0[2], (iop2); +} + +#-- G2 PLL Control Register 0 +scom 0x8000080509011C7F { + bits, scom_data, expr; + 51:63, ATTR_PROC_PCIE_IOP_G2_PLL_CONTROL0[2], (iop2); +} + +#-- PLL Global Control Register 0 +scom 0x8000080809011C7F { + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0[2], (iop2); +} + +#-- PLL Global Control Register 1 +scom 0x8000080909011C7F { + bits, scom_data, expr; + 51:63, ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1[2], (iop2); +} + +#-- PCS Control Register 0 +scom 0x8000088009011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_PCS_CONTROL0[2], (iop2); +} + +#-- PCS Control Register 1 +scom 0x8000088109011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_PCS_CONTROL1[2], (iop2); +} + +#-- TX FIFO Control Register (A0) +scom 0x8000040009011C7F { + bits, scom_data, expr; + 53:56, 0b1111, (iop2 && lane_32_40); +} + +#-- TX FIFO Control Register (A1) +scom 0x8000044009011C7F { + bits, scom_data, expr; + 53:56, 0b1111, (iop2 && lane_32_40); +} + +#-- TX FIFO Control Register (A2) +scom 0x8000048009011C7F { + bits, scom_data, expr; + 53:56, 0b1111, (iop2 && lane_32_40); +} + +#-- TX FIFO Control Register (A3) +scom 0x800004C009011C7F { + bits, scom_data, expr; + 53:56, 0b1111, (iop2 && lane_32_40); +} + +#-- TX FIFO Control Register (A4) +scom 0x8000050009011C7F { + bits, scom_data, expr; + 53:56, 0b1111, (iop2 && lane_32_40); +} + +#-- TX FIFO Control Register (A5) +scom 0x8000054009011C7F { + bits, scom_data, expr; + 53:56, 0b1111, (iop2 && lane_32_40); +} + +#-- TX FIFO Control Register (A6) +scom 0x8000058009011C7F { + bits, scom_data, expr; + 53:56, 0b1111, (iop2 && lane_32_40); +} + +#-- TX FIFO Control Register (A7) +scom 0x800005C009011C7F { + bits, scom_data, expr; + 53:56, 0b1111, (iop2 && lane_32_40); +} + +#-- TX FIFO Offset Register (A0) +scom 0x8000040109011C7F { + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[2][0], (iop2 && lane_32_40); +} + +#-- TX FIFO Offset Register (A1) +scom 0x8000044109011C7F { + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[2][1], (iop2 && lane_32_40); +} + +#-- TX FIFO Offset Register (A2) +scom 0x8000048109011C7F { + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[2][2], (iop2 && lane_32_40); +} + +#-- TX FIFO Offset Register (A3) +scom 0x800004C109011C7F { + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[2][3], (iop2 && lane_32_40); +} + +#-- TX FIFO Offset Register (A4) +scom 0x8000050109011C7F { + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[2][4], (iop2 && lane_32_40); +} + +#-- TX FIFO Offset Register (A5) +scom 0x8000054109011C7F { + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[2][5], (iop2 && lane_32_40); +} + +#-- TX FIFO Offset Register (A6) +scom 0x8000058109011C7F { + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[2][6], (iop2 && lane_32_40); +} + +#-- TX FIFO Offset Register (A7) +scom 0x800005C109011C7F { + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[2][7], (iop2 && lane_32_40); +} + +#-- TX Receiver Detect Control Register (A0) +scom 0x8000040209011C7F { + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[2][0], (iop2 && lane_32_40); +} + +#-- TX Receiver Detect Control Register (A1) +scom 0x8000044209011C7F { + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[2][1], (iop2 && lane_32_40); +} + +#-- TX Receiver Detect Control Register (A2) +scom 0x8000048209011C7F { + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[2][2], (iop2 && lane_32_40); +} + +#-- TX Receiver Detect Control Register (A3) +scom 0x800004C209011C7F { + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[2][3], (iop2 && lane_32_40); +} + +#-- TX Receiver Detect Control Register (A4) +scom 0x8000050209011C7F { + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[2][4], (iop2 && lane_32_40); +} + +#-- TX Receiver Detect Control Register (A5) +scom 0x8000054209011C7F { + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[2][5], (iop2 && lane_32_40); +} + +#-- TX Receiver Detect Control Register (A6) +scom 0x8000058209011C7F { + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[2][6], (iop2 && lane_32_40); +} + +#-- TX Receiver Detect Control Register (A7) +scom 0x800005C209011C7F { + bits, scom_data, expr; + 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[2][7], (iop2 && lane_32_40); +} + +#-- TX Bandwidth Loss Coefficient Register (A0) +scom 0x8000041B09011C7F { + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[2][0], (iop2 && lane_32_40); +} + +#-- TX Bandwidth Loss Coefficient Register (A1) +scom 0x8000045B09011C7F { + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[2][1], (iop2 && lane_32_40); +} + +#-- TX Bandwidth Loss Coefficient Register (A2) +scom 0x8000049B09011C7F { + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[2][2], (iop2 && lane_32_40); +} + +#-- TX Bandwidth Loss Coefficient Register (A3) +scom 0x800004DB09011C7F { + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[2][3], (iop2 && lane_32_40); +} + +#-- TX Bandwidth Loss Coefficient Register (A4) +scom 0x8000051B09011C7F { + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[2][4], (iop2 && lane_32_40); +} + +#-- TX Bandwidth Loss Coefficient Register (A5) +scom 0x8000055B09011C7F { + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[2][5], (iop2 && lane_32_40); +} + +#-- TX Bandwidth Loss Coefficient Register (A6) +scom 0x8000059B09011C7F { + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[2][6], (iop2 && lane_32_40); +} + +#-- TX Bandwidth Loss Coefficient Register (A7) +scom 0x800005DB09011C7F { + bits, scom_data, expr; + 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[2][7], (iop2 && lane_32_40); +} + +#-- RX VGA Control Register2 (A0) +scom 0x8000000C09011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[2][0], (iop2 && lane_32_40); +} + +#-- RX VGA Control Register2 (A1) +scom 0x8000004C09011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[2][1], (iop2 && lane_32_40); +} + +#-- RX VGA Control Register2 (A2) +scom 0x8000008C09011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[2][2], (iop2 && lane_32_40); +} + +#-- RX VGA Control Register2 (A3) +scom 0x800000CC09011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[2][3], (iop2 && lane_32_40); +} + +#-- RX VGA Control Register2 (A4) +scom 0x8000010C09011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[2][4], (iop2 && lane_32_40); +} + +#-- RX VGA Control Register2 (A5) +scom 0x8000014C09011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[2][5], (iop2 && lane_32_40); +} + +#-- RX VGA Control Register2 (A6) +scom 0x8000018C09011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[2][6], (iop2 && lane_32_40); +} + +#-- RX VGA Control Register2 (A7) +scom 0x800001CC09011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[2][7], (iop2 && lane_32_40); +} + +#-- RX Receiver Peaking Register (A0) +scom 0x8000001009011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[2][0], (iop2 && lane_32_40); +} + +#-- RX Receiver Peaking Register (A1) +scom 0x8000005009011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[2][1], (iop2 && lane_32_40); +} + +#-- RX Receiver Peaking Register (A2) +scom 0x8000009009011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[2][2], (iop2 && lane_32_40); +} + +#-- RX Receiver Peaking Register (A3) +scom 0x800000D009011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[2][3], (iop2 && lane_32_40); +} + +#-- RX Receiver Peaking Register (A4) +scom 0x8000011009011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[2][4], (iop2 && lane_32_40); +} + +#-- RX Receiver Peaking Register (A5) +scom 0x8000015009011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[2][5], (iop2 && lane_32_40); +} + +#-- RX Receiver Peaking Register (A6) +scom 0x8000019009011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[2][6], (iop2 && lane_32_40); +} + +#-- RX Receiver Peaking Register (A7) +scom 0x800001D009011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[2][7], (iop2 && lane_32_40); +} + +#-- RX Signal Detect Level Register (A0) +scom 0x8000003709011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[2][0], (iop2 && lane_32_40); +} + +#-- RX Signal Detect Level Register (A1) +scom 0x8000007709011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[2][1], (iop2 && lane_32_40); +} + +#-- RX Signal Detect Level Register (A2) +scom 0x800000B709011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[2][2], (iop2 && lane_32_40); +} + +#-- RX Signal Detect Level Register (A3) +scom 0x800000F709011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[2][3], (iop2 && lane_32_40); +} + +#-- RX Signal Detect Level Register (A4) +scom 0x8000013709011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[2][4], (iop2 && lane_32_40); +} + +#-- RX Signal Detect Level Register (A5) +scom 0x8000017709011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[2][5], (iop2 && lane_32_40); +} + +#-- RX Signal Detect Level Register (A6) +scom 0x800001B709011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[2][6], (iop2 && lane_32_40); +} + +#-- RX Signal Detect Level Register (A7) +scom 0x800001F709011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[2][7], (iop2 && lane_32_40); +} + +#-- TX GEN1 Coefficient Override Register (A0) +scom 0x8000041009011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[2][0], (iop2 && lane_32_40); +} + +#-- TX GEN1 Coefficient Override Register (A1) +scom 0x8000045009011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[2][1], (iop2 && lane_32_40); +} + +#-- TX GEN1 Coefficient Override Register (A2) +scom 0x8000049009011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[2][2], (iop2 && lane_32_40); +} + +#-- TX GEN1 Coefficient Override Register (A3) +scom 0x800004D009011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[2][3], (iop2 && lane_32_40); +} + +#-- TX GEN1 Coefficient Override Register (A4) +scom 0x8000051009011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[2][4], (iop2 && lane_32_40); +} + +#-- TX GEN1 Coefficient Override Register (A5) +scom 0x8000055009011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[2][5], (iop2 && lane_32_40); +} + +#-- TX GEN1 Coefficient Override Register (A6) +scom 0x8000059009011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[2][6], (iop2 && lane_32_40); +} + +#-- TX GEN1 Coefficient Override Register (A7) +scom 0x800005D009011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[2][7], (iop2 && lane_32_40); +} + +#-- TX GEN2 Coefficient Override Register (A0) +scom 0x8000041109011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[2][0], (iop2 && lane_32_40); +} + +#-- TX GEN2 Coefficient Override Register (A1) +scom 0x8000045109011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[2][1], (iop2 && lane_32_40); +} + +#-- TX GEN2 Coefficient Override Register (A2) +scom 0x8000049109011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[2][2], (iop2 && lane_32_40); +} + +#-- TX GEN2 Coefficient Override Register (A3) +scom 0x800004D109011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[2][3], (iop2 && lane_32_40); +} + +#-- TX GEN2 Coefficient Override Register (A4) +scom 0x8000051109011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[2][4], (iop2 && lane_32_40); +} + +#-- TX GEN2 Coefficient Override Register (A5) +scom 0x8000055109011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[2][5], (iop2 && lane_32_40); +} + +#-- TX GEN2 Coefficient Override Register (A6) +scom 0x8000059109011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[2][6], (iop2 && lane_32_40); +} + +#-- TX GEN2 Coefficient Override Register (A7) +scom 0x800005D109011C7F { + bits, scom_data, expr; + 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[2][7], (iop2 && lane_32_40); +} + +#-- RX Phase Rotator Flywheel Control Register (A0) +scom 0x8000002F09011C7F { + bits, scom_data, expr; + 56:59, 0b1110, (iop2 && lane_32_40); +} + +#-- RX Phase Rotator Flywheel Control Register (A1) +scom 0x8000006F09011C7F { + bits, scom_data, expr; + 56:59, 0b1110, (iop2 && lane_32_40); +} + +#-- RX Phase Rotator Flywheel Control Register (A2) +scom 0x800000AF09011C7F { + bits, scom_data, expr; + 56:59, 0b1110, (iop2 && lane_32_40); +} + +#-- RX Phase Rotator Flywheel Control Register (A3) +scom 0x800000EF09011C7F { + bits, scom_data, expr; + 56:59, 0b1110, (iop2 && lane_32_40); +} + +#-- RX Phase Rotator Flywheel Control Register (A4) +scom 0x8000012F09011C7F { + bits, scom_data, expr; + 56:59, 0b1110, (iop2 && lane_32_40); +} + +#-- RX Phase Rotator Flywheel Control Register (A5) +scom 0x8000016F09011C7F { + bits, scom_data, expr; + 56:59, 0b1110, (iop2 && lane_32_40); +} + +#-- RX Phase Rotator Flywheel Control Register (A6) +scom 0x800001AF09011C7F { + bits, scom_data, expr; + 56:59, 0b1110, (iop2 && lane_32_40); +} + +#-- RX Phase Rotator Flywheel Control Register (A7) +scom 0x800001EF09011C7F { + bits, scom_data, expr; + 56:59, 0b1110, (iop2 && lane_32_40); +} + +#-- DFE Function Control Register 1 (A0) +scom 0x8000001F09011C7F { + bits, scom_data, expr; + 49, 0b0, (iop2 && lane_32_40); +} + +#-- DFE Function Control Register 1 (A1) +scom 0x8000005F09011C7F { + bits, scom_data, expr; + 49, 0b0, (iop2 && lane_32_40); +} + +#-- DFE Function Control Register 1 (A2) +scom 0x8000009F09011C7F { + bits, scom_data, expr; + 49, 0b0, (iop2 && lane_32_40); +} + +#-- DFE Function Control Register 1 (A3) +scom 0x800000DF09011C7F { + bits, scom_data, expr; + 49, 0b0, (iop2 && lane_32_40); +} + +#-- DFE Function Control Register 1 (A4) +scom 0x8000011F09011C7F { + bits, scom_data, expr; + 49, 0b0, (iop2 && lane_32_40); +} + +#-- DFE Function Control Register 1 (A5) +scom 0x8000015F09011C7F { + bits, scom_data, expr; + 49, 0b0, (iop2 && lane_32_40); +} + +#-- DFE Function Control Register 1 (A6) +scom 0x8000019F09011C7F { + bits, scom_data, expr; + 49, 0b0, (iop2 && lane_32_40); +} + +#-- DFE Function Control Register 1 (A7) +scom 0x800001DF09011C7F { + bits, scom_data, expr; + 49, 0b0, (iop2 && lane_32_40); +} + +#-- Receiver Configuration Mode Register (A0) +scom 0x8000000009011C7F { + bits, scom_data, expr; + 49, 0b1, (iop2 && lane_32_40); +} + +#-- Receiver Configuration Mode Register (A1) +scom 0x8000004009011C7F { + bits, scom_data, expr; + 49, 0b1, (iop2 && lane_32_40); +} + +#-- Receiver Configuration Mode Register (A2) +scom 0x8000008009011C7F { + bits, scom_data, expr; + 49, 0b1, (iop2 && lane_32_40); +} + +#-- Receiver Configuration Mode Register (A3) +scom 0x800000C009011C7F { + bits, scom_data, expr; + 49, 0b1, (iop2 && lane_32_40); +} + +#-- Receiver Configuration Mode Register (A4) +scom 0x8000010009011C7F { + bits, scom_data, expr; + 49, 0b1, (iop2 && lane_32_40); +} + +#-- Receiver Configuration Mode Register (A5) +scom 0x8000014009011C7F { + bits, scom_data, expr; + 49, 0b1, (iop2 && lane_32_40); +} + +#-- Receiver Configuration Mode Register (A6) +scom 0x8000018009011C7F { + bits, scom_data, expr; + 49, 0b1, (iop2 && lane_32_40); +} + +#-- Receiver Configuration Mode Register (A7) +scom 0x800001C009011C7F { + bits, scom_data, expr; + 49, 0b1, (iop2 && lane_32_40); +} + +#-- ZCAL Control Register +scom 0x8000084009011C7F { + bits, scom_data, expr; + 53:60, ATTR_PROC_PCIE_IOP_ZCAL_CONTROL[2], (iop2); +} + +#-- ZCAL Override Register +scom 0x8000084209011C7F { + bits, scom_data, expr; + 48:63, 0xEC30, (iop2 && zcal_override); } diff --git a/src/usr/hwpf/hwp/initfiles/p8.pe.phase2.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.pe.phase2.scom.initfile index d6afe6cf3..8d9357c4e 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.pe.phase2.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.pe.phase2.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: p8.pe.phase2.scom.initfile,v 1.5 2013/11/13 17:20:20 jmcgill Exp $ +#-- $Id: p8.pe.phase2.scom.initfile,v 1.6 2014/11/18 17:26:01 jmcgill Exp $ #------------------------------------------------------------------------------- #-- #-- (C) Copyright International Business Machines Corp. 2011 @@ -23,6 +23,11 @@ SyntaxVersion = 1 #-- Defines #-------------------------------------------------------------------------------- +define phb0 = (ATTR_PROC_PCIE_NUM_PHB >= 1); +define phb1 = (ATTR_PROC_PCIE_NUM_PHB >= 2); +define phb2 = (ATTR_PROC_PCIE_NUM_PHB >= 3); +define phb3 = (ATTR_PROC_PCIE_NUM_PHB >= 4); + define def_nest_freq_r0 = (SYS.ATTR_FREQ_PB >= 2200); define def_nest_freq_r1 = ((SYS.ATTR_FREQ_PB <= 1700) && (SYS.ATTR_FREQ_PB < 2200)); define def_nest_freq_r2 = (SYS.ATTR_FREQ_PB < 1700); @@ -30,49 +35,164 @@ define def_nest_freq_r2 = (SYS.ATTR_FREQ_PB < 1700); define enable_enh_ive_ordering = (ATTR_CHIP_EC_FEATURE_ENABLE_IVE_PERFORMANCE_ORDERING != 0); define enable_dmar_ooo = (ATTR_CHIP_EC_FEATURE_ENABLE_PCI_DMAR_OOO != 0); + #-------------------------------------------------------------------------------- #-- SCOM initializations #-------------------------------------------------------------------------------- #-- PBCQ Mode Control Register -scom 0x02012(0,4,8)0B { +scom 0x0201200B { + bits, scom_data, expr; + 12, 0b1, (phb0); #-- disable group scope on TCE read requests + 26, 0b1, (phb0 && enable_enh_ive_ordering); #-- enable enhanced IVE performance ordering only where supported (HW226407) + 27, 0b1, (phb0); #-- force IVE write operations to system scope +} + +scom 0x0201240B { + bits, scom_data, expr; + 12, 0b1, (phb1); + 26, 0b1, (phb1 && enable_enh_ive_ordering); + 27, 0b1, (phb1); +} + +scom 0x0201280B { + bits, scom_data, expr; + 12, 0b1, (phb2); + 26, 0b1, (phb2 && enable_enh_ive_ordering); + 27, 0b1, (phb2); +} + +scom 0x02012C0B { bits, scom_data, expr; - 12, 0b1, any; #-- disable group scope on TCE read requests - 26, 0b1, (enable_enh_ive_ordering); #-- enable enhanced IVE performance ordering only where supported (HW226407) - 27, 0b1, any; #-- force IVE write operations to system scope + 12, 0b1, (phb3); + 26, 0b1, (phb3 && enable_enh_ive_ordering); + 27, 0b1, (phb3); } #-- PCI Hardware Configuration 0 Register -scom 0x02012(0,4,8)18 { - bits, scom_data; - 0:3, 0b0000; #-- hang poll scale (reg=0, scale of 1) - 4:7, 0b0010; #-- data poll scale (reg=2, scale of 3) - 8:11, 0b0000; #-- data poll scale (PE) (reg=0, scale of 1) - 17, 0b1; #-- disable out-of-order store behavior +scom 0x02012018 { + bits, scom_data, expr; + 0:3, 0b0000, (phb0); #-- hang poll scale (reg=0, scale of 1) + 4:7, 0b0010, (phb0); #-- data poll scale (reg=2, scale of 3) + 8:11, 0b0000, (phb0); #-- data poll scale (PE) (reg=0, scale of 1) + 17, 0b1, (phb0); #-- disable out-of-order store behavior +} + +scom 0x02012418 { + bits, scom_data, expr; + 0:3, 0b0000, (phb1); + 4:7, 0b0010, (phb1); + 8:11, 0b0000, (phb1); + 17, 0b1, (phb1); +} + +scom 0x02012818 { + bits, scom_data, expr; + 0:3, 0b0000, (phb2); + 4:7, 0b0010, (phb2); + 8:11, 0b0000, (phb2); + 17, 0b1, (phb2); +} + +scom 0x02012C18 { + bits, scom_data, expr; + 0:3, 0b0000, (phb3); + 4:7, 0b0010, (phb3); + 8:11, 0b0000, (phb3); + 17, 0b1, (phb3); } #-- PCI Hardware Configuration 1 Register -scom 0x02012(0,4,8)19 { - bits, scom_data; - 22, 0b0; #-- diable OOO DMA read +scom 0x02012019 { + bits, scom_data, expr; + 22, 0b0, (phb0); #-- diable OOO DMA read +} + +scom 0x02012419 { + bits, scom_data, expr; + 22, 0b0, (phb1); +} + +scom 0x02012819 { + bits, scom_data, expr; + 22, 0b0, (phb2); +} + +scom 0x02012C19 { + bits, scom_data, expr; + 22, 0b0, (phb3); } #-- PCI Nest Clock Trace Control Register -scom 0x02012(0,4,8)0D { - bits, scom_data; - 0:3, 0b1001; #-- enable trace, select inbound + address info +scom 0x0201200D { + bits, scom_data, expr; + 0:3, 0b1001, (phb0); #-- enable trace, select inbound + address info +} + +scom 0x0201240D { + bits, scom_data, expr; + 0:3, 0b1001, (phb1); +} + +scom 0x0201280D { + bits, scom_data, expr; + 0:3, 0b1001, (phb2); +} + +scom 0x02012C0D { + bits, scom_data, expr; + 0:3, 0b1001, (phb3); } #-- PB AIB Control/Status Register -scom 0x09012(0,4,8)0F { - bits, scom_data, expr; - 0:2, 0b011, (def_nest_freq_r0); #-- Maximum Ch0 command credit given to ETU - 0:2, 0b010, (def_nest_freq_r1); - 0:2, 0b001, (def_nest_freq_r2); - 3:5, 0b001, any; #-- Maximum Ch1 command credit given to ETU - 6:8, 0b011, (def_nest_freq_r0); #-- Maximum Ch2 command credit given to ETU - 6:8, 0b010, (def_nest_freq_r1 || def_nest_freq_r2); - 9:11, 0b000, any; #-- Maximum Ch3 command credit given to ETU - 12:13, 0b11, any; #-- Overcommit of inbound speed matching buffer (HW245629) - 30:31, 0b11, any; #-- enable PCI clock tracing w/ ETU as default +scom 0x0901200F { + bits, scom_data, expr; + 0:2, 0b011, (phb0 && def_nest_freq_r0); #-- Maximum Ch0 command credit given to ETU + 0:2, 0b010, (phb0 && def_nest_freq_r1); + 0:2, 0b001, (phb0 && def_nest_freq_r2); + 3:5, 0b001, (phb0); #-- Maximum Ch1 command credit given to ETU + 6:8, 0b011, (phb0 && def_nest_freq_r0); #-- Maximum Ch2 command credit given to ETU + 6:8, 0b010, (phb0 && (def_nest_freq_r1 || def_nest_freq_r2)); + 9:11, 0b000, (phb0); #-- Maximum Ch3 command credit given to ETU + 12:13, 0b11, (phb0); #-- Overcommit of inbound speed matching buffer (HW245629) + 30:31, 0b11, (phb0); #-- enable PCI clock tracing w/ ETU as default +} + +scom 0x0901240F { + bits, scom_data, expr; + 0:2, 0b011, (phb1 && def_nest_freq_r0); + 0:2, 0b010, (phb1 && def_nest_freq_r1); + 0:2, 0b001, (phb1 && def_nest_freq_r2); + 3:5, 0b001, (phb1); + 6:8, 0b011, (phb1 && def_nest_freq_r0); + 6:8, 0b010, (phb1 && (def_nest_freq_r1 || def_nest_freq_r2)); + 9:11, 0b000, (phb1); + 12:13, 0b11, (phb1); + 30:31, 0b11, (phb1); +} + +scom 0x0901280F { + bits, scom_data, expr; + 0:2, 0b011, (phb2 && def_nest_freq_r0); + 0:2, 0b010, (phb2 && def_nest_freq_r1); + 0:2, 0b001, (phb2 && def_nest_freq_r2); + 3:5, 0b001, (phb2); + 6:8, 0b011, (phb2 && def_nest_freq_r0); + 6:8, 0b010, (phb2 && (def_nest_freq_r1 || def_nest_freq_r2)); + 9:11, 0b000, (phb2); + 12:13, 0b11, (phb2); + 30:31, 0b11, (phb2); +} + +scom 0x09012C0F { + bits, scom_data, expr; + 0:2, 0b011, (phb3 && def_nest_freq_r0); + 0:2, 0b010, (phb3 && def_nest_freq_r1); + 0:2, 0b001, (phb3 && def_nest_freq_r2); + 3:5, 0b001, (phb3); + 6:8, 0b011, (phb3 && def_nest_freq_r0); + 6:8, 0b010, (phb3 && (def_nest_freq_r1 || def_nest_freq_r2)); + 9:11, 0b000, (phb3); + 12:13, 0b11, (phb3); + 30:31, 0b11, (phb3); } diff --git a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C index a86dc56db..f6c033582 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C +++ b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -1011,6 +1011,9 @@ errlHndl_t computeProcPcieConfigAttrs( i_pProcChipTarget ? i_pProcChipTarget->getAttr<TARGETING::ATTR_HUID>() : 0); + // TODO: + // RTC 109249: Update comments for 40 lanes in Naples + // Currently there are two IOP config tables, one for procs with 24 usable // PCIE lanes and one for proces with 32 usable PCIE lanes. In general, the // code accumulates the current configuration of the IOPs from the MRW and @@ -1270,37 +1273,41 @@ errlHndl_t computeProcPcieConfigAttrs( } // Pick the appropriate IOP configuration table - if( i_pProcChipTarget->getAttr<TARGETING::ATTR_IOP_LANES_PER_PROC>() + if( i_pProcChipTarget->getAttr<TARGETING::ATTR_PROC_PCIE_NUM_LANES>() == IOP_LANES_PER_PROC_32X) { pLaneConfigTableBegin = x32_laneConfigTable; pLaneConfigTableEnd = x32_end; } else if( i_pProcChipTarget->getAttr< - TARGETING::ATTR_IOP_LANES_PER_PROC>() + TARGETING::ATTR_PROC_PCIE_NUM_LANES>() == IOP_LANES_PER_PROC_24X) { pLaneConfigTableBegin = x24_laneConfigTable; pLaneConfigTableEnd = x24_end; } + + // TODO: + // RTC 109249: Support Naples with 40 lanes + else { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, ERR_MRK "computeProcPcieConfigAttrs> " - "Code bug! Unsupported ATTR_IOP_LANES_PER_PROC attribute for " + "Code bug! Unsupported ATTR_PROC_PCIE_NUM_LANES attribute for " "processor with HUID of 0x%08X. Expected 24 or 32, but read " "value of %d.", i_pProcChipTarget->getAttr<TARGETING::ATTR_HUID>(), i_pProcChipTarget->getAttr< - TARGETING::ATTR_IOP_LANES_PER_PROC>()); + TARGETING::ATTR_PROC_PCIE_NUM_LANES>()); /*@ * @errortype * @moduleid ISTEP_COMPUTE_PCIE_CONFIG_ATTRS * @reasoncode ISTEP_INVALID_ATTR_VALUE * @userdata1[0:31] Target's HUID - * @userdata2[32:63] ATTR_IOP_LANES_PER_PROC attribute value - * @devdesc Illegal ATTR_IOP_LANES_PER_PROC attribute read + * @userdata2[32:63] ATTR_PROC_PCIE_NUM_LANES attribute value + * @devdesc Illegal ATTR_PROC_PCIE_NUM_LANES attribute read * from a processor chip target. * @custdesc A problem isolated to firmware or firmware * customization occurred during the IPL of the @@ -1313,7 +1320,7 @@ errlHndl_t computeProcPcieConfigAttrs( TWO_UINT32_TO_UINT64( i_pProcChipTarget->getAttr<TARGETING::ATTR_HUID>(), i_pProcChipTarget->getAttr< - TARGETING::ATTR_IOP_LANES_PER_PROC>()), + TARGETING::ATTR_PROC_PCIE_NUM_LANES>()), 0, true); ERRORLOG::ErrlUserDetailsTarget(i_pProcChipTarget).addToLog(pError); diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C index d49b010f6..b0b1cd34e 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_chiplet_scominit.C,v 1.24 2014/10/17 16:41:10 jmcgill Exp $ +// $Id: proc_chiplet_scominit.C,v 1.26 2014/11/20 18:00:37 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_chiplet_scominit.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -71,6 +71,7 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target) fapi::Target master_mcs; uint8_t enable_xbus_resonant_clocking = 0x0; uint8_t i2c_slave_address = 0x0; + uint8_t dual_capp_present = 0x0; ecmdDataBufferBase data(64); ecmdDataBufferBase cfam_data(32); @@ -249,6 +250,30 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target) break; } + // get dual CAPP presence attribute + FAPI_DBG("proc_chiplet_scominit: Querying dual CAPP feature attribute"); + rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_DUAL_CAPP_PRESENT, + &i_target, + dual_capp_present); + if (!rc.ok()) + { + FAPI_ERR("proc_chiplet_scominit: Error querying ATTR_CHIP_EC_FEATURE_DUAL_CAPP_PRESENT"); + break; + } + + if (dual_capp_present != 0) + { + rc = fapiPutScom(i_target, + CAPP1_APC_MASTER_LCO_TARGET_0x020131A1, + data); + if (!rc.ok()) + { + FAPI_ERR("proc_chiplet_scominit: fapiPutScom error (CAPP1_APC_MASTER_LCO_TARGET_0x020131A1) on %s", + i_target.toEcmdString()); + break; + } + } + // execute AS SCOM initfile FAPI_INF("proc_chiplet_scominit: Executing %s on %s", PROC_CHIPLET_SCOMINIT_AS_IF, i_target.toEcmdString()); @@ -346,7 +371,6 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target) break; } - if (enable_xbus_resonant_clocking) { FAPI_DBG("proc_chiplet_scominit: Enabling XBUS resonant clocking"); @@ -414,7 +438,6 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target) break; } - // determine set of functional MCS chiplets rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_MCS_CHIPLET, diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C index f2a8183d8..ee4080bbf 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_pcie_scominit.C,v 1.10 2014/08/05 15:15:13 kahnevan Exp $ +// $Id: proc_pcie_scominit.C,v 1.11 2014/11/18 17:38:50 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_scominit.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -54,7 +54,9 @@ extern "C" { // set master IOP lane configuration and IOP swap bits via PCIe GP4 // set PHB iovalids via PCIe GP0 // remove IOP logic from reset via PCIe GP4 -// parameters: i_target => processor chip target +// parameters: i_target => processor chip target +// i_num_iop => number of IOP units +// i_num_phb => number of PHB units // returns: FAPI_RC_SUCCESS if all actions are successful, // RC_PROC_PCIE_SCOMINIT_IOP_CONFIG_ATTR_ERR if invalid IOP lane // configuration attribute value is presented, @@ -63,7 +65,9 @@ extern "C" { // else error //------------------------------------------------------------------------------ fapi::ReturnCode proc_pcie_scominit_iop_init( - const fapi::Target & i_target) + const fapi::Target & i_target, + uint8_t i_num_iop, + uint8_t i_num_phb) { fapi::ReturnCode rc; uint32_t rc_ecmd = 0; @@ -118,7 +122,7 @@ fapi::ReturnCode proc_pcie_scominit_iop_init( FAPI_ERR("proc_pcie_scominit_iop_init: Error from FAPI_ATTR_GET (ATTR_PROC_PCIE_IOP_SWAP)"); break; } - for (size_t i = 0; (i < PROC_PCIE_SCOMINIT_NUM_IOP) && rc.ok(); i++) + for (size_t i = 0; (i < i_num_iop) && rc.ok(); i++) { FAPI_DBG("proc_pcie_scominit_iop_init: ATTR_PROC_PCIE_IOP_SWAP[%zd]= %02X", i, iop_swap[i]); @@ -145,7 +149,7 @@ fapi::ReturnCode proc_pcie_scominit_iop_init( (PCIE_GP4_IOP_LANE_CFG_END_BIT- PCIE_GP4_IOP_LANE_CFG_START_BIT+1)); - for (size_t i = 0; (i < PROC_PCIE_SCOMINIT_NUM_IOP) && !rc_ecmd; i++) + for (size_t i = 0; (i < i_num_iop) && !rc_ecmd; i++) { rc_ecmd |= gp4_data.insertFromRight( iop_swap[i], @@ -191,14 +195,14 @@ fapi::ReturnCode proc_pcie_scominit_iop_init( break; } - for (size_t i = 0; (i < PROC_PCIE_SCOMINIT_NUM_PHB); i++) + for (size_t i = 0; (i < i_num_phb); i++) { phb_active[i] = ((phb_active_mask >> (7-i)) & 0x1)?(true):(false); refclock_active[i] = ((refclock_active_mask >> (7-i)) & 0x1)?(true):(false); } // set PCIe GP0 mask for PHB iovalid/refclock enable - for (size_t i = 0; (i < PROC_PCIE_SCOMINIT_NUM_PHB) && !rc_ecmd; i++) + for (size_t i = 0; (i < i_num_phb) && !rc_ecmd; i++) { rc_ecmd |= gp0_data.writeBit( PCIE_GP0_PHB_IOVALID_BIT[i], @@ -226,7 +230,7 @@ fapi::ReturnCode proc_pcie_scominit_iop_init( // set PCIe GP4 mask for IOP reset rc_ecmd |= gp4_data.flushTo0(); - for (size_t i = 0; (i < PROC_PCIE_SCOMINIT_NUM_IOP) && !rc_ecmd; i++) + for (size_t i = 0; (i < i_num_iop) && !rc_ecmd; i++) { rc_ecmd |= gp4_data.setBit( PCIE_GP4_IOP_RESET_BIT[i]); @@ -319,12 +323,14 @@ fapi::ReturnCode proc_pcie_scominit_iop_config( //------------------------------------------------------------------------------ // function: mark IOP programming complete (executed after all IOP // customization is complete) -// parameters: i_target => processor chip target +// parameters: i_target => processor chip target +// i_num_iop => number of IOP units // returns: FAPI_RC_SUCCESS if program complete is successful for all IOPs, // else error //------------------------------------------------------------------------------ fapi::ReturnCode proc_pcie_scominit_iop_complete( - const fapi::Target & i_target) + const fapi::Target & i_target, + uint8_t i_num_iop) { fapi::ReturnCode rc; uint32_t rc_ecmd = 0; @@ -347,7 +353,7 @@ fapi::ReturnCode proc_pcie_scominit_iop_complete( } // set IOP program complete - for (size_t i = 0; i < PROC_PCIE_SCOMINIT_NUM_IOP; i++) + for (size_t i = 0; i < i_num_iop; i++) { rc = fapiPutScomUnderMask(i_target, PROC_PCIE_SCOMINIT_PLL_GLOBAL_CONTROL2[i], @@ -366,7 +372,7 @@ fapi::ReturnCode proc_pcie_scominit_iop_complete( } // configure IOP FIR - for (size_t i = 0; i < PROC_PCIE_SCOMINIT_NUM_IOP; i++) + for (size_t i = 0; i < i_num_iop; i++) { rc_ecmd |= data.flushTo0(); if (rc_ecmd) @@ -438,6 +444,8 @@ fapi::ReturnCode proc_pcie_scominit( { fapi::ReturnCode rc; uint8_t pcie_enabled; + uint8_t num_phb; + uint8_t num_iop; // mark HWP entry FAPI_INF("proc_pcie_scominit: Start"); @@ -463,11 +471,30 @@ fapi::ReturnCode proc_pcie_scominit( break; } - // initialize/configure/finalize IOP programming (only if partial good + // initialize/configure/finalize PHB & IOP programming (only if partial good // attribute is set) if (pcie_enabled == fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE) { - rc = proc_pcie_scominit_iop_init(i_target); + // determine PHB/IOP configuration + rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_NUM_PHB, + &i_target, + num_phb); + if (!rc.ok()) + { + FAPI_ERR("proc_pcie_scominit: Error from FAPI_ATTR_GET (ATTR_PROC_PCIE_NUM_PHB)"); + break; + } + + rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_NUM_IOP, + &i_target, + num_iop); + if (!rc.ok()) + { + FAPI_ERR("proc_pcie_scominit: Error from FAPI_ATTR_GET (ATTR_PROC_PCIE_NUM_IOP)"); + break; + } + + rc = proc_pcie_scominit_iop_init(i_target, num_iop, num_phb); if (!rc.ok()) { FAPI_ERR("proc_pcie_scominit: Error from proc_pcie_scominit_iop_init"); @@ -481,7 +508,7 @@ fapi::ReturnCode proc_pcie_scominit( break; } - rc = proc_pcie_scominit_iop_complete(i_target); + rc = proc_pcie_scominit_iop_complete(i_target, num_iop); if (!rc.ok()) { FAPI_ERR("proc_pcie_scominit: Error from proc_pcie_scominit_iop_complete"); diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H index f7d2f13c5..59797ffa1 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_pcie_scominit.H,v 1.6 2013/10/28 03:57:13 jmcgill Exp $ +// $Id: proc_pcie_scominit.H,v 1.7 2014/11/18 17:38:50 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_scominit.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -61,41 +61,46 @@ const char * const PROC_PCIE_SCOMINIT_PHASE1_IF = "p8.pe.phase1.scom.if"; // PCIe physical constants -const uint8_t PROC_PCIE_SCOMINIT_NUM_IOP = 2; -const uint8_t PROC_PCIE_SCOMINIT_NUM_PHB = 3; +const uint8_t PROC_PCIE_SCOMINIT_NUM_IOP = 3; +const uint8_t PROC_PCIE_SCOMINIT_NUM_PHB = 4; // PCIe GP0 register field/bit definitions const uint32_t PCIE_GP0_PHB_IOVALID_BIT[PROC_PCIE_SCOMINIT_NUM_PHB] = { 48, 49, - 50 + 50, + 51 }; const uint32_t PCIE_GP0_PHB_REFCLOCK_DRIVE_EN_BIT[PROC_PCIE_SCOMINIT_NUM_PHB] = { 52, 53, - 54 + 54, + 55 }; // PCIe GP4 register field/bit definitions const uint32_t PCIE_GP4_IOP_RESET_BIT[PROC_PCIE_SCOMINIT_NUM_IOP] = { 37, - 38 + 38, + 39 }; const uint32_t PCIE_GP4_IOP_LANE_CFG_START_BIT = 41; const uint32_t PCIE_GP4_IOP_LANE_CFG_END_BIT = 44; const uint32_t PCIE_GP4_IOP_SWAP_START_BIT[PROC_PCIE_SCOMINIT_NUM_IOP] = { 47, - 53 + 53, + 50 }; const uint32_t PCIE_GP4_IOP_SWAP_END_BIT[PROC_PCIE_SCOMINIT_NUM_IOP] = { 49, - 55 + 55, + 52 }; // Murano/Venice support lane configurations bewtween 0x0 & 0xC, @@ -108,7 +113,8 @@ const uint8_t PCIE_GP4_IOP_SWAP_MAX = 0x7; const uint64_t PROC_PCIE_SCOMINIT_PLL_GLOBAL_CONTROL2[PROC_PCIE_SCOMINIT_NUM_IOP] = { PCIE_IOP0_PLL_GLOBAL_CONTROL2_0x8000080A0901143F, - PCIE_IOP1_PLL_GLOBAL_CONTROL2_0x8000080A0901187F + PCIE_IOP1_PLL_GLOBAL_CONTROL2_0x8000080A0901187F, + PCIE_IOP2_PLL_GLOBAL_CONTROL2_0x8000080A09011C7F }; const uint32_t PLL_GLOBAL_CONTROL2_PROG_COMPLETE_BIT = 50; @@ -116,19 +122,22 @@ const uint32_t PLL_GLOBAL_CONTROL2_PROG_COMPLETE_BIT = 50; const uint32_t PROC_PCIE_SCOMINIT_PLL_FIR[PROC_PCIE_SCOMINIT_NUM_IOP] = { PCIE_IOP0_PLL_FIR_0x09011400, - PCIE_IOP1_PLL_FIR_0x09011840 + PCIE_IOP1_PLL_FIR_0x09011840, + PCIE_IOP2_PLL_FIR_0x09011C40 }; const uint32_t PROC_PCIE_SCOMINIT_PLL_FIR_WOF[PROC_PCIE_SCOMINIT_NUM_IOP] = { PCIE_IOP0_PLL_FIR_WOF_0x09011408, - PCIE_IOP1_PLL_FIR_WOF_0x09011848 + PCIE_IOP1_PLL_FIR_WOF_0x09011848, + PCIE_IOP2_PLL_FIR_WOF_0x09011C48 }; const uint32_t PROC_PCIE_SCOMINIT_PLL_FIR_MASK[PROC_PCIE_SCOMINIT_NUM_IOP] = { PCIE_IOP0_PLL_FIR_MASK_0x09011403, - PCIE_IOP1_PLL_FIR_MASK_0x09011843 + PCIE_IOP1_PLL_FIR_MASK_0x09011843, + PCIE_IOP2_PLL_FIR_MASK_0x09011C43 }; const uint64_t PCIE_PLL_FIR_MASK_VAL = 0x0080000000000000ULL; diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml index d4582c7d4..7efcf7449 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012,2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2012,2015 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -20,11 +22,54 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_pcie_scominit_attributes.xml,v 1.6 2013/12/09 21:52:08 jmcgill Exp $ --> +<!-- $Id: proc_pcie_scominit_attributes.xml,v 1.7 2014/11/18 17:46:06 jmcgill Exp $ --> <!-- proc_pcie_scominit_attributes.xml --> <attributes> <!-- ********************************************************************* --> <attribute> + <id>ATTR_PROC_PCIE_NUM_PHB</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + creator: platform + Number of PCIe PHB units present on target + Murano/Venice: 3 + Naples: 4 + </description> + <valueType>uint8</valueType> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_PCIE_NUM_IOP</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + creator: platform + Number of PCIe IOP units present on target + Murano/Venice: 2 + Naples: 3 + </description> + <valueType>uint8</valueType> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_PCIE_NUM_LANES</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + creator: platform + Number of PCIe I/O lanes supported by target + Murano: 24 + Venice: 32 + Naples: 40 + </description> + <valueType>uint8</valueType> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> <id>ATTR_PROC_PCIE_IOP_CONFIG</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>PCIE IOP lane configuration @@ -46,10 +91,10 @@ consumer: proc_pcie_scominit firmware notes: Encoded PCIE IOP swap configuration - Array index: IOP number (0:1) + Array index: IOP number (0:2) </description> <valueType>uint8</valueType> - <array>2</array> + <array>3</array> <platInit/> <persistRuntime/> </attribute> @@ -62,7 +107,7 @@ consumer: proc_pcie_scominit firmware notes: Bit mask defining set of active/valid PHBs - bit0=PHB0, bit1=PHB1, bit2=PHB2 + bit0=PHB0, bit1=PHB1, bit2=PHB2, bit3=PHB3 </description> <valueType>uint8</valueType> <platInit/> @@ -77,7 +122,7 @@ consumer: proc_pcie_scominit firmware notes: Bit mask defining state of refclock drive enables - bit0=PCI0, bit1=PCI1, bit2=PCI2 + bit0=PCI0, bit1=PCI1, bit2=PCI2, bit3=PCI3 </description> <valueType>uint8</valueType> <platInit/> @@ -93,10 +138,10 @@ firmware notes: PCIe Gen3 PLL Control Register 0. ATUNE/CPISEL. - Array index: IOP number(0:1) + Array index: IOP number(0:2) </description> <valueType>uint32</valueType> - <array>2</array> + <array>3</array> <platInit/> </attribute> <!-- ********************************************************************* --> @@ -109,10 +154,10 @@ notes: PCIe Gen2/Gen1 PLL Control Register 0. ATUNE/CPISEL. - Array index: IOP number (0:1) + Array index: IOP number (0:2) </description> <valueType>uint32</valueType> - <array>2</array> + <array>3</array> <platInit/> </attribute> <!-- ********************************************************************* --> @@ -125,10 +170,10 @@ notes: PCIe PLL Global Control Register 0. REFISRC/REFISINK. - Array index: IOP number (0:1) + Array index: IOP number (0:2) </description> <valueType>uint32</valueType> - <array>2</array> + <array>3</array> <platInit/> </attribute> <!-- ********************************************************************* --> @@ -141,10 +186,10 @@ notes: PCIe PLL Global Control Register 1. ENBGDOCPSRC/ENBGDOCAMP/REFVREG. - Array index: IOP number (0:1) + Array index: IOP number (0:2) </description> <valueType>uint32</valueType> - <array>2</array> + <array>3</array> <platInit/> </attribute> <!-- ********************************************************************* --> @@ -158,10 +203,10 @@ PCIe PCS Control Register 0. BITLOCKTIME/ADDDREMDELTA_810_B/STARTUPDELTA_810_B/ADDDREMDELTA_810_A/ STARTUPDELTA_A/RXREJECTHANDLING/EQCOMLETERESPONSE. - Array index: IOP number (0:1) + Array index: IOP number (0:2) </description> <valueType>uint32</valueType> - <array>2</array> + <array>3</array> <platInit/> </attribute> <!-- ********************************************************************* --> @@ -175,10 +220,10 @@ PCIe PCS Control Register 1. RXSIGDETSETTING/ADDDREMDELTA_128130_B/STARTUPDELTA_128130_B/ ADDDREMDELTA_128130_A/STARTUPDELTA_128130_A. - Array index: IOP number (0:1) + Array index: IOP number (0:2) </description> <valueType>uint32</valueType> - <array>2</array> + <array>3</array> <platInit/> </attribute> <!-- ********************************************************************* --> @@ -191,11 +236,11 @@ notes: PCIe TX FIFO Offset Register. G3OFFSET/G2OFFSET/G1OFFSET. - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <valueType>uint32</valueType> - <array>2,16</array> + <array>3 16</array> <platInit/> </attribute> <!-- ********************************************************************* --> @@ -208,11 +253,11 @@ notes: PCIe TX Receiver Detect Control Register. VREFSEL/RCVRDETCNT/DETDRVC/PH1WAIT. - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <valueType>uint32</valueType> - <array>2,16</array> + <array>3 16</array> <platInit/> </attribute> <!-- ********************************************************************* --> @@ -225,11 +270,11 @@ notes: PCIe TX Bandwidth Loss Coefficient Register. GEN3BWCOEFF/GEN2BWCOEFF/GEN1BWCOEFF. - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <valueType>uint32</valueType> - <array>2,16</array> + <array>3 16</array> <platInit/> </attribute> <!-- ********************************************************************* --> @@ -242,11 +287,11 @@ notes: PCIe RX VGA Control Register 2. GAIN2/GAIN1. - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <valueType>uint32</valueType> - <array>2,16</array> + <array>3 16</array> <platInit/> </attribute> <!-- ********************************************************************* --> @@ -259,11 +304,11 @@ notes: PCIe RX Receiver Peaking Value Register. PEAK1/PEAK2/PEAK3. - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <valueType>uint32</valueType> - <array>2,16</array> + <array>3 16</array> <platInit/> </attribute> <!-- ********************************************************************* --> @@ -276,11 +321,11 @@ notes: PCIe RX Signal Detect Level Register. SDLVL3/SDLVL2/SDLVL1. - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <valueType>uint32</valueType> - <array>2,16</array> + <array>3 16</array> <platInit/> </attribute> <!-- ********************************************************************* --> @@ -292,11 +337,11 @@ consumer: proc_pcie_scominit notes: PCIe TX FFE (Gen1) - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <valueType>uint32</valueType> - <array>2,16</array> + <array>3 16</array> <platInit/> </attribute> <!-- ********************************************************************* --> @@ -308,11 +353,11 @@ consumer: proc_pcie_scominit notes: PCIe TX FFE (Gen2) - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <valueType>uint32</valueType> - <array>2,16</array> + <array>3 16</array> <platInit/> </attribute> <!-- ********************************************************************* --> @@ -325,10 +370,10 @@ notes: PCIe ZCAL Control Register. CMPEVALDLY. - Array index: IOP number (0:1) + Array index: IOP number (0:2) </description> <valueType>uint32</valueType> - <array>2</array> + <array>3</array> <platInit/> </attribute> <!-- ********************************************************************* --> diff --git a/src/usr/hwpf/hwp/proc_chip_ec_feature.xml b/src/usr/hwpf/hwp/proc_chip_ec_feature.xml index 3f14981f9..40e0b694d 100644 --- a/src/usr/hwpf/hwp/proc_chip_ec_feature.xml +++ b/src/usr/hwpf/hwp/proc_chip_ec_feature.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2013,2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2013,2015 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -22,14 +22,16 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_chip_ec_feature.xml,v 1.60 2014/10/29 21:33:52 szhong Exp $ --> +<!-- $Id: proc_chip_ec_feature.xml,v 1.61 2014/11/18 17:48:26 jmcgill Exp $ --> <!-- Defines the attributes that are based on EC level --> <attributes> + <!-- ********************************************************************* --> <attribute> - <id>ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC</id> + <id>ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> - For Venice specific inits. Returns true if Venice. + Returns true if ABUS TX Per-Lane PRBS Tap Selector should be set. True if: + Venice EC 0x10 or greater </description> <chipEcFeature> <chip> @@ -39,13 +41,94 @@ <test>GREATER_THAN_OR_EQUAL</test> </ec> </chip> - </chipEcFeature> + </chipEcFeature> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_TA_PB_T1_PRESENT</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Returns if a chip contains PB_T1 trace array. True if: + Venice EC 0x10 or greater + Naples EC 0x10 or greater + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_VENICE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_NAPLES</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_TA_A_T1_PRESENT</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Returns if a chip contains A_T1 trace array. True if: + Naples EC 0x10 or greater + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NAPLES</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_SINGLE_XBUS_PRESENT</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Returns true if a single XBUS is present. True if: Murano + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_MURANO</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_NV_PRESENT</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Returns if a chip contains NV chiplet/link logic. True if: + Naples EC 0x10 or greater + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NAPLES</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> - <id>ATTR_CHIP_EC_FEATURE_NAPLES_SPECIFIC</id> + <id>ATTR_CHIP_EC_FEATURE_DUAL_CAPP_PRESENT</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> - For Naples specific inits. Returns true if Naples. + Returns if a chip contains two CAPP units. True if: + Naples EC 0x10 or greater </description> <chipEcFeature> <chip> @@ -57,6 +140,25 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_SET_LEGACY_NODE_ID_VALID_MBOX_BIT</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Set legacy node ID valid mailbox indicator bit. True if: + Murano EC 0x10 or greater + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_MURANO</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_USE_POLLING_PROT</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -90,6 +192,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_HW_BUG_PIBSLVRESET</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -105,6 +208,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_BOOT_FREQ_LESS_PSAVE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -123,6 +227,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_HW_BUG_PLLINIT</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -140,6 +245,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_SECURE_IOVALID_PRESENT</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -165,6 +271,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_NOT_SUPPORT_SBE_CFAM_START</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -182,6 +289,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_NOT_SUPPORT_SBE_AUTO_START</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -199,31 +307,7 @@ </chip> </chipEcFeature> </attribute> - <attribute> - <id>ATTR_CHIP_EC_FEATURE_32_PCIE_LANES</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description> - Returns if a chip contains 32 lanes of PCIE I/O. True if: - Venice EC 0x10 or greater - Naples EC 0x10 or greater - </description> - <chipEcFeature> - <chip> - <name>ENUM_ATTR_NAME_VENICE</name> - <ec> - <value>0x10</value> - <test>GREATER_THAN_OR_EQUAL</test> - </ec> - </chip> - <chip> - <name>ENUM_ATTR_NAME_NAPLES</name> - <ec> - <value>0x10</value> - <test>GREATER_THAN_OR_EQUAL</test> - </ec> - </chip> - </chipEcFeature> - </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_CAPP_HANG_CONTROL_ON_SCOM</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -257,6 +341,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_CAPP_PROD</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -290,6 +375,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_NX_HANG_CONTROL_ON_SCOM</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -323,6 +409,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_HCA_SPLIT_HANG_CONTROL</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -356,6 +443,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_RECAL_DFE_ENABLE</id> <targetType>TARGET_TYPE_PROC_CHIP,TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -397,6 +485,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_RECAL_DDC_ENABLE</id> <targetType>TARGET_TYPE_PROC_CHIP,TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -438,6 +527,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_RECAL_CTLE_ENABLE</id> <targetType>TARGET_TYPE_PROC_CHIP,TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -479,6 +569,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_LCTANK_PLL_VCO_BUG</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -496,6 +587,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_XBUS_DLL_SLOW_MURANO</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -513,6 +605,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_ADU_PBINIT_LAUNCH_BUG</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -538,6 +631,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_MCS_ECC_BYPASS_DISABLE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -563,6 +657,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_MCS_MURDD1_FIR_CONTROL</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -580,6 +675,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_MCS_VENDD1_FIR_CONTROL</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -597,6 +693,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_MCS_P8_DD2_FIR_CONTROL</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -630,6 +727,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_TRACE_CONTROL_ON_SCOM</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -663,6 +761,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_MPIPL_AISS_WINKLE_ENTRY</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -688,6 +787,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_WE5_VER2</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -722,6 +822,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_C8_VER3</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -755,6 +856,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_C8_VER2</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -773,6 +875,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_FBC_UX_SCOPE_ARB_RR</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -799,6 +902,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_FBC_UX_SCOPE_ARB_LFSR_ON_STARVATION_ELSE_RR</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -825,6 +929,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_FBC_UX_LOCAL_ARB_RR</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -851,6 +956,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_C10_VER2</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -884,6 +990,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -910,6 +1017,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_PCBS_ERR_RESET</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -943,6 +1051,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_IO_TRAINING_SLS_WORKAROUND</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -959,6 +1068,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_IO_TRAINING_DLL_WORKAROUND</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -975,6 +1085,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_DCCAL_PLL_WORKAROUND</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -990,6 +1101,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_XBUS_RESONANT_CLK_VALID</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -1015,6 +1127,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_RESONANT_CLK_VALID</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -1048,6 +1161,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_AISS_SPECIAL_WAKEUP</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -1082,6 +1196,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_OCC_CE_FIR_DISABLE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -1099,6 +1214,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_ENABLE_IVE_PERFORMANCE_ORDERING</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -1132,6 +1248,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_ENABLE_PCI_DMAR_OOO</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -1165,6 +1282,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_ZCAL_OVERRIDE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -1182,6 +1300,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_IVRM_WINKLE_BUG</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -1215,6 +1334,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_PROC_EC_MSS_RECONFIG_POSSIBLE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -1225,7 +1345,7 @@ Murano EC greater than or equal to 0x20 Venice EC greater than or equal to 0x20 Naples EC greater than or equal to 0x10 - </description> + </description> <chipEcFeature> <chip> <name>ENUM_ATTR_NAME_MURANO</name> @@ -1250,6 +1370,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CEN_EC_THROTTLE_SYNC_POSSIBLE</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -1265,6 +1386,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_PROC_EC_CORE_HANG_PULSE_BUG</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -1282,7 +1404,8 @@ </chip> </chipEcFeature> </attribute> - <attribute> + <!-- ********************************************************************* --> + <attribute> <id>ATTR_PROC_EC_PBA_PREFETCH_ENABLE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> @@ -1315,7 +1438,8 @@ </chip> </chipEcFeature> </attribute> - <attribute> + <!-- ********************************************************************* --> + <attribute> <id>ATTR_PROC_EC_OHA_L3_PURGE_ABORT_ENABLE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> @@ -1341,6 +1465,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_PFET_POWEROFF_BUG</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -1366,6 +1491,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_OCC_DISABLE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -1385,6 +1511,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_HW_BUG_PBASLVRESET</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -1402,6 +1529,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_HCA_BAR_SCOM_BUG</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -1428,6 +1556,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_HW_BUG_TOD_ERROR_MASK_NOT_WRITABLE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -1444,4 +1573,5 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> </attributes> diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_tp_collect_dbg_data/proc_tp_collect_dbg_data.C b/src/usr/hwpf/hwp/slave_sbe/proc_tp_collect_dbg_data/proc_tp_collect_dbg_data.C index dcaf271f9..d376b9c7b 100644 --- a/src/usr/hwpf/hwp/slave_sbe/proc_tp_collect_dbg_data/proc_tp_collect_dbg_data.C +++ b/src/usr/hwpf/hwp/slave_sbe/proc_tp_collect_dbg_data/proc_tp_collect_dbg_data.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014 */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,7 +27,6 @@ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 // *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** //------------------------------------------------------------------------------ // *! TITLE : proc_tp_collect_dbg_data.C // *! DESCRIPTION : Procedure to collect TP debug data diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_tp_collect_dbg_data/proc_tp_collect_dbg_data.H b/src/usr/hwpf/hwp/slave_sbe/proc_tp_collect_dbg_data/proc_tp_collect_dbg_data.H index 04ef54421..a9b0092a4 100644 --- a/src/usr/hwpf/hwp/slave_sbe/proc_tp_collect_dbg_data/proc_tp_collect_dbg_data.H +++ b/src/usr/hwpf/hwp/slave_sbe/proc_tp_collect_dbg_data/proc_tp_collect_dbg_data.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014 */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,7 +27,6 @@ ///------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 // *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** //------------------------------------------------------------------------------ // *! TITLE : proc_tp_collect_dbg_data.C // *! DESCRIPTION : Header file for procedure to collect TP debug data diff --git a/src/usr/hwpf/hwp/winkle_ring_accessors/n1_10_winkle_ring.attributes b/src/usr/hwpf/hwp/winkle_ring_accessors/n1_10_winkle_ring.attributes index b6d113935..6d92a0afe 100644 --- a/src/usr/hwpf/hwp/winkle_ring_accessors/n1_10_winkle_ring.attributes +++ b/src/usr/hwpf/hwp/winkle_ring_accessors/n1_10_winkle_ring.attributes @@ -1,3 +1,4 @@ +# $Id: n1_10_winkle_ring.attributes,v 1.1 2014/11/06 22:44:21 szhong Exp $ #===============================================================================BEGIN Entry # #SELECT=0 @@ -24,33 +25,33 @@ # EHP.EX.RCMD1_I2C_RCV_CTL.SERIAL_MODEQ.SHIFT_DATAQ.ESC.L2(0:5) 0b100100 #------------------------------------------------------------------------------- Attribute View -ATTR_PROC_EX_FUNC_L3_LENGTH u32 49193 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[0] u32[64] 0x14C00080 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[1] u32[64] 0x14C30008 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[2] u32[64] 0x14C5000A -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[3] u32[64] 0x14D50080 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[4] u32[64] 0x14D80008 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[5] u32[64] 0x14DA000A -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[6] u32[64] 0x1576000F -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[7] u32[64] 0x15F10003 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[8] u32[64] 0x15F200C0 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[9] u32[64] 0x16890001 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[10] u32[64] 0x168A0020 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[11] u32[64] 0x168B0048 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[12] u32[64] 0x16ED0002 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[13] u32[64] 0x16EE0004 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[14] u32[64] 0x16F50001 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[15] u32[64] 0x16F60020 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[16] u32[64] 0x16F70048 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[17] u32[64] 0x17DD0008 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[18] u32[64] 0x17E90008 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[19] u32[64] 0x17EC0004 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[20] u32[64] 0x17ED0080 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[21] u32[64] 0x17F40008 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[22] u32[64] 0x18000008 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[23] u32[64] 0x18030004 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[24] u32[64] 0x18040080 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[25] u32[64] 0xFFFF0000 +ATTR_PROC_EX_FUNC_L3_LENGTH u32 49198 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[0] u32[64] 0x14C00020 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[1] u32[64] 0x14C30002 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[2] u32[64] 0x14C50002 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[3] u32[64] 0x14C60080 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[4] u32[64] 0x14D50020 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[5] u32[64] 0x14D80002 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[6] u32[64] 0x14DA0002 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[7] u32[64] 0x14DB0080 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[8] u32[64] 0x15770078 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[9] u32[64] 0x15F2001E +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[10] u32[64] 0x168A0009 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[11] u32[64] 0x168B0002 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[12] u32[64] 0x168C0040 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[13] u32[64] 0x16EE0010 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[14] u32[64] 0x16EF0020 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[15] u32[64] 0x16F60009 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[16] u32[64] 0x16F70002 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[17] u32[64] 0x16F80040 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[18] u32[64] 0x17DE0040 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[19] u32[64] 0x17EA0040 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[20] u32[64] 0x17ED0024 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[21] u32[64] 0x17F50040 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[22] u32[64] 0x18010040 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[23] u32[64] 0x18040024 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[24] u32[64] 0xFFFF0000 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[25] u32[64] 0x00000000 ATTR_PROC_EX_FUNC_L3_DELTA_DATA[26] u32[64] 0x00000000 ATTR_PROC_EX_FUNC_L3_DELTA_DATA[27] u32[64] 0x00000000 ATTR_PROC_EX_FUNC_L3_DELTA_DATA[28] u32[64] 0x00000000 @@ -117,32 +118,32 @@ ATTR_PROC_EX_FUNC_L3_DELTA_DATA[63] u32[64] 0x00000000 # EHP.EX.RCMD1_I2C_RCV_CTL.SERIAL_MODEQ.SHIFT_DATAQ.ESC.L2(0:5) 0b100100 #------------------------------------------------------------------------------- Attribute View -ATTR_PROC_EX_FUNC_L3_LENGTH u32 49193 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[0] u32[64] 0x14C00080 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[1] u32[64] 0x14C30008 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[2] u32[64] 0x14C5000A -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[3] u32[64] 0x14D50080 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[4] u32[64] 0x14D80008 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[5] u32[64] 0x14DA000A -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[6] u32[64] 0x1576000F -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[7] u32[64] 0x15F10003 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[8] u32[64] 0x15F200C0 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[9] u32[64] 0x168A00A0 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[10] u32[64] 0x168B0028 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[11] u32[64] 0x16ED0012 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[12] u32[64] 0x16EE0014 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[13] u32[64] 0x16F600A0 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[14] u32[64] 0x16F70028 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[15] u32[64] 0x17DD0008 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[16] u32[64] 0x17E90008 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[17] u32[64] 0x17EC0004 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[18] u32[64] 0x17ED0080 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[19] u32[64] 0x17F40008 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[20] u32[64] 0x18000008 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[21] u32[64] 0x18030004 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[22] u32[64] 0x18040080 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[23] u32[64] 0xFFFF0000 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[24] u32[64] 0x00000000 +ATTR_PROC_EX_FUNC_L3_LENGTH u32 49198 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[0] u32[64] 0x14C00020 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[1] u32[64] 0x14C30002 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[2] u32[64] 0x14C50002 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[3] u32[64] 0x14C60080 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[4] u32[64] 0x14D50020 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[5] u32[64] 0x14D80002 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[6] u32[64] 0x14DA0002 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[7] u32[64] 0x14DB0080 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[8] u32[64] 0x15770078 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[9] u32[64] 0x15F2001E +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[10] u32[64] 0x168A0005 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[11] u32[64] 0x168B0001 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[12] u32[64] 0x168C0040 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[13] u32[64] 0x16EE0090 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[14] u32[64] 0x16EF00A0 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[15] u32[64] 0x16F60005 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[16] u32[64] 0x16F70001 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[17] u32[64] 0x16F80040 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[18] u32[64] 0x17DE0040 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[19] u32[64] 0x17EA0040 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[20] u32[64] 0x17ED0024 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[21] u32[64] 0x17F50040 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[22] u32[64] 0x18010040 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[23] u32[64] 0x18040024 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[24] u32[64] 0xFFFF0000 ATTR_PROC_EX_FUNC_L3_DELTA_DATA[25] u32[64] 0x00000000 ATTR_PROC_EX_FUNC_L3_DELTA_DATA[26] u32[64] 0x00000000 ATTR_PROC_EX_FUNC_L3_DELTA_DATA[27] u32[64] 0x00000000 @@ -204,27 +205,27 @@ ATTR_PROC_EX_FUNC_L3_DELTA_DATA[63] u32[64] 0x00000000 # EHP.EX.RCMD1_I2C_RCV_CTL.SERIAL_MODEQ.SHIFT_DATAQ.ESC.L2(0:5) 0b100100 #------------------------------------------------------------------------------- Attribute View -ATTR_PROC_EX_FUNC_L3_LENGTH u32 49193 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[0] u32[64] 0x14C00080 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[1] u32[64] 0x14C30008 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[2] u32[64] 0x14C5000A -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[3] u32[64] 0x14D50080 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[4] u32[64] 0x14D80008 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[5] u32[64] 0x14DA000A -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[6] u32[64] 0x16890001 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[7] u32[64] 0x168A00A0 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[8] u32[64] 0x168B0068 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[9] u32[64] 0x16F50001 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[10] u32[64] 0x16F600A0 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[11] u32[64] 0x16F70068 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[12] u32[64] 0x17DD0008 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[13] u32[64] 0x17E90008 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[14] u32[64] 0x17EC0004 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[15] u32[64] 0x17ED0080 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[16] u32[64] 0x17F40008 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[17] u32[64] 0x18000008 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[18] u32[64] 0x18030004 -ATTR_PROC_EX_FUNC_L3_DELTA_DATA[19] u32[64] 0x18040080 +ATTR_PROC_EX_FUNC_L3_LENGTH u32 49198 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[0] u32[64] 0x14C00020 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[1] u32[64] 0x14C30002 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[2] u32[64] 0x14C50002 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[3] u32[64] 0x14C60080 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[4] u32[64] 0x14D50020 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[5] u32[64] 0x14D80002 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[6] u32[64] 0x14DA0002 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[7] u32[64] 0x14DB0080 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[8] u32[64] 0x168A000D +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[9] u32[64] 0x168B0003 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[10] u32[64] 0x168C0040 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[11] u32[64] 0x16F6000D +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[12] u32[64] 0x16F70003 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[13] u32[64] 0x16F80040 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[14] u32[64] 0x17DE0040 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[15] u32[64] 0x17EA0040 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[16] u32[64] 0x17ED0024 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[17] u32[64] 0x17F50040 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[18] u32[64] 0x18010040 +ATTR_PROC_EX_FUNC_L3_DELTA_DATA[19] u32[64] 0x18040024 ATTR_PROC_EX_FUNC_L3_DELTA_DATA[20] u32[64] 0xFFFF0000 ATTR_PROC_EX_FUNC_L3_DELTA_DATA[21] u32[64] 0x00000000 ATTR_PROC_EX_FUNC_L3_DELTA_DATA[22] u32[64] 0x00000000 diff --git a/src/usr/hwpf/plat/fapiPlatAttributeService.C b/src/usr/hwpf/plat/fapiPlatAttributeService.C index 48701c101..6e4f40039 100644 --- a/src/usr/hwpf/plat/fapiPlatAttributeService.C +++ b/src/usr/hwpf/plat/fapiPlatAttributeService.C @@ -922,7 +922,7 @@ fapi::ReturnCode fapiPlatGetProcNxMmioBarSize ( fapi::ReturnCode fapiPlatGetProcPcieBarEnable ( const fapi::Target * i_pTarget, - uint8_t (&o_pcieBarEnable) [3][3] ) + uint8_t (&o_pcieBarEnable) [4][3] ) { fapi::ReturnCode l_rc; uint64_t l_procNum = 0; @@ -973,7 +973,7 @@ fapi::ReturnCode fapiPlatGetProcPcieBarEnable ( fapi::ReturnCode fapiPlatGetProcPcieBarBaseAddr ( const fapi::Target * i_pTarget, - uint64_t (&o_pcieBarBase) [3][3] ) + uint64_t (&o_pcieBarBase) [4][3] ) { fapi::ReturnCode l_rc; uint64_t l_procNum = 0; @@ -1058,7 +1058,7 @@ fapi::ReturnCode fapiPlatGetProcPcieBarBaseAddr ( fapi::ReturnCode fapiPlatGetProcPcieBarSize ( const fapi::Target * i_pTarget, - uint64_t (&o_pcieBarSize) [3][3] ) + uint64_t (&o_pcieBarSize) [4][3] ) { fapi::ReturnCode l_rc; uint64_t l_procNum = 0; diff --git a/src/usr/runtime/common/hsvc_exdata.C b/src/usr/runtime/common/hsvc_exdata.C index e20fee874..a8c22453c 100644 --- a/src/usr/runtime/common/hsvc_exdata.C +++ b/src/usr/runtime/common/hsvc_exdata.C @@ -5,7 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -20,10 +22,10 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// Generated on Wed Jul 9 14:34:55 CDT 2014 by dcrowell from +// Generated on Wed Feb 18 09:37:26 CST 2015 by cswenson from // ./create_hsvc_data.pl -w ../../xml/attribute_info/chip_attributes.xml ../../xml/attribute_info/common_attributes.xml ../../xml/attribute_info/freq_attributes.xml ../../xml/attribute_info/L2_L3_attributes.xml ../../xml/attribute_info/p8_xip_customize_attributes.xml ../../xml/attribute_info/pm_hwp_attributes.xml ../../xml/attribute_info/pm_plat_attributes.xml ../../xml/attribute_info/poreve_memory_attributes.xml ../../xml/attribute_info/proc_chip_ec_feature.xml ../../xml/attribute_info/proc_fab_smp_fabric_attributes.xml ../../xml/attribute_info/proc_pll_ring_attributes.xml ../../xml/attribute_info/proc_setup_bars_l3_attributes.xml ../../xml/attribute_info/proc_winkle_scan_override_attributes.xml ../../xml/attribute_info/scratch_attributes.xml ../../xml/attribute_info/system_attributes.xml ../../xml/attribute_info/unit_attributes.xml // -- Input: ../../xml/attribute_info/chip_attributes.xml -- -// No attributes found +HSVC_LOAD_ATTR( ATTR_TARGET_SCOMABLE ); // -- Input: ../../xml/attribute_info/common_attributes.xml -- HSVC_LOAD_ATTR( ATTR_FUNCTIONAL ); // -- Input: ../../xml/attribute_info/freq_attributes.xml -- diff --git a/src/usr/runtime/common/hsvc_procdata.C b/src/usr/runtime/common/hsvc_procdata.C index aa3132063..8e177143f 100644 --- a/src/usr/runtime/common/hsvc_procdata.C +++ b/src/usr/runtime/common/hsvc_procdata.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// Generated on Wed Jul 9 14:34:55 CDT 2014 by dcrowell from +// Generated on Wed Feb 18 09:37:26 CST 2015 by cswenson from // ./create_hsvc_data.pl -w ../../xml/attribute_info/chip_attributes.xml ../../xml/attribute_info/common_attributes.xml ../../xml/attribute_info/freq_attributes.xml ../../xml/attribute_info/L2_L3_attributes.xml ../../xml/attribute_info/p8_xip_customize_attributes.xml ../../xml/attribute_info/pm_hwp_attributes.xml ../../xml/attribute_info/pm_plat_attributes.xml ../../xml/attribute_info/poreve_memory_attributes.xml ../../xml/attribute_info/proc_chip_ec_feature.xml ../../xml/attribute_info/proc_fab_smp_fabric_attributes.xml ../../xml/attribute_info/proc_pll_ring_attributes.xml ../../xml/attribute_info/proc_setup_bars_l3_attributes.xml ../../xml/attribute_info/proc_winkle_scan_override_attributes.xml ../../xml/attribute_info/scratch_attributes.xml ../../xml/attribute_info/system_attributes.xml ../../xml/attribute_info/unit_attributes.xml // -- Input: ../../xml/attribute_info/chip_attributes.xml -- HSVC_LOAD_ATTR( ATTR_CHIP_HAS_SBE ); @@ -33,6 +33,7 @@ HSVC_LOAD_ATTR( ATTR_EX_L2_SINGLE_MEMBER_ENABLE ); HSVC_LOAD_ATTR( ATTR_FABRIC_CHIP_ID ); HSVC_LOAD_ATTR( ATTR_FABRIC_NODE_ID ); HSVC_LOAD_ATTR( ATTR_FSI_GP_REG_SCOM_ACCESS ); +HSVC_LOAD_ATTR( ATTR_I2C_SLAVE_ADDRESS ); HSVC_LOAD_ATTR_P( ATTR_NAME ); HSVC_LOAD_ATTR( ATTR_OSCSWITCH_CTL0 ); HSVC_LOAD_ATTR( ATTR_OSCSWITCH_CTL1 ); @@ -40,6 +41,7 @@ HSVC_LOAD_ATTR( ATTR_OSCSWITCH_CTL2 ); HSVC_LOAD_ATTR( ATTR_PCI_OSCSWITCH_CONFIG ); HSVC_LOAD_ATTR( ATTR_PROC_BOOT_VOLTAGE_VID ); HSVC_LOAD_ATTR( ATTR_PROC_DCM_INSTALLED ); +HSVC_LOAD_ATTR( ATTR_TARGET_SCOMABLE ); // -- Input: ../../xml/attribute_info/common_attributes.xml -- HSVC_LOAD_ATTR( ATTR_FUNCTIONAL ); HSVC_LOAD_ATTR( ATTR_POS ); @@ -166,13 +168,12 @@ HSVC_LOAD_ATTR( ATTR_SBE_SEEPROM_I2C_ADDRESS_BYTES ); HSVC_LOAD_ATTR( ATTR_SBE_SEEPROM_I2C_DEVICE_ADDRESS ); HSVC_LOAD_ATTR( ATTR_SBE_SEEPROM_I2C_PORT ); // -- Input: ../../xml/attribute_info/proc_chip_ec_feature.xml -- -HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_32_PCIE_LANES ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_ADU_PBINIT_LAUNCH_BUG ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_AISS_SPECIAL_WAKEUP ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_BOOT_FREQ_LESS_PSAVE ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_CAPP_HANG_CONTROL_ON_SCOM ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_CAPP_PROD ); -//HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_CFAM_RESET_SBE_START_WA ); +HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_DUAL_CAPP_PRESENT ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_ENABLE_IVE_PERFORMANCE_ORDERING ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_ENABLE_PCI_DMAR_OOO ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_C10_VER2 ); @@ -182,10 +183,12 @@ HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_WE5_VER2 ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_FBC_UX_LOCAL_ARB_RR ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_FBC_UX_SCOPE_ARB_LFSR_ON_STARVATION_ELSE_RR ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_FBC_UX_SCOPE_ARB_RR ); +HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_HCA_BAR_SCOM_BUG ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_HCA_SPLIT_HANG_CONTROL ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_HW_BUG_PBASLVRESET ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_HW_BUG_PIBSLVRESET ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_HW_BUG_PLLINIT ); +HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_HW_BUG_TOD_ERROR_MASK_NOT_WRITABLE ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_IVRM_WINKLE_BUG ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_LCTANK_PLL_VCO_BUG ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG ); @@ -196,6 +199,7 @@ HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_MCS_VENDD1_FIR_CONTROL ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_MPIPL_AISS_WINKLE_ENTRY ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_NOT_SUPPORT_SBE_AUTO_START ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_NOT_SUPPORT_SBE_CFAM_START ); +HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_NV_PRESENT ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_NX_HANG_CONTROL_ON_SCOM ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_OCC_CE_FIR_DISABLE ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_OCC_DISABLE ); @@ -205,9 +209,15 @@ HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_RECAL_DDC_ENABLE ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_RECAL_DFE_ENABLE ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_RESONANT_CLK_VALID ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_SECURE_IOVALID_PRESENT ); +HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID ); +HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_SET_LEGACY_NODE_ID_VALID_MBOX_BIT ); +HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_SINGLE_XBUS_PRESENT ); +HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_TA_A_T1_PRESENT ); +HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_TA_PB_T1_PRESENT ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_TRACE_CONTROL_ON_SCOM ); -HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC ); +HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_USE_POLLING_PROT ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_XBUS_DLL_SLOW_MURANO ); +HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_XBUS_RESONANT_CLK_VALID ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_FEATURE_ZCAL_OVERRIDE ); HSVC_LOAD_ATTR( ATTR_CHIP_EC_PFET_POWEROFF_BUG ); HSVC_LOAD_ATTR( ATTR_DCCAL_PLL_WORKAROUND ); diff --git a/src/usr/runtime/common/hsvc_sysdata.C b/src/usr/runtime/common/hsvc_sysdata.C index 827c165dc..b9a94e380 100644 --- a/src/usr/runtime/common/hsvc_sysdata.C +++ b/src/usr/runtime/common/hsvc_sysdata.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// Generated on Wed Jul 9 14:34:55 CDT 2014 by dcrowell from +// Generated on Wed Feb 18 09:37:26 CST 2015 by cswenson from // ./create_hsvc_data.pl -w ../../xml/attribute_info/chip_attributes.xml ../../xml/attribute_info/common_attributes.xml ../../xml/attribute_info/freq_attributes.xml ../../xml/attribute_info/L2_L3_attributes.xml ../../xml/attribute_info/p8_xip_customize_attributes.xml ../../xml/attribute_info/pm_hwp_attributes.xml ../../xml/attribute_info/pm_plat_attributes.xml ../../xml/attribute_info/poreve_memory_attributes.xml ../../xml/attribute_info/proc_chip_ec_feature.xml ../../xml/attribute_info/proc_fab_smp_fabric_attributes.xml ../../xml/attribute_info/proc_pll_ring_attributes.xml ../../xml/attribute_info/proc_setup_bars_l3_attributes.xml ../../xml/attribute_info/proc_winkle_scan_override_attributes.xml ../../xml/attribute_info/scratch_attributes.xml ../../xml/attribute_info/system_attributes.xml ../../xml/attribute_info/unit_attributes.xml // -- Input: ../../xml/attribute_info/chip_attributes.xml -- @@ -70,6 +70,7 @@ HSVC_LOAD_ATTR( ATTR_PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY ); HSVC_LOAD_ATTR( ATTR_PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY ); HSVC_LOAD_ATTR( ATTR_PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY ); HSVC_LOAD_ATTR( ATTR_PM_SAFE_FREQUENCY ); +HSVC_LOAD_ATTR( ATTR_PM_SLEEP_ENABLE ); HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_FREQUENCY ); HSVC_LOAD_ATTR( ATTR_PM_SPIVID_FREQUENCY ); HSVC_LOAD_ATTR( ATTR_PM_SYSTEM_IVRMS_ENABLED ); @@ -80,7 +81,6 @@ HSVC_LOAD_ATTR( ATTR_PROC_R_LOADLINE_VCS ); HSVC_LOAD_ATTR( ATTR_PROC_R_LOADLINE_VDD ); HSVC_LOAD_ATTR( ATTR_PROC_VRM_VOFFSET_VCS ); HSVC_LOAD_ATTR( ATTR_PROC_VRM_VOFFSET_VDD ); -HSVC_LOAD_ATTR( ATTR_PM_SLEEP_ENABLE ); // -- Input: ../../xml/attribute_info/poreve_memory_attributes.xml -- // No attributes found // -- Input: ../../xml/attribute_info/proc_chip_ec_feature.xml -- diff --git a/src/usr/runtime/populate_attributes.C b/src/usr/runtime/populate_attributes.C index c128ce63f..6a6024219 100644 --- a/src/usr/runtime/populate_attributes.C +++ b/src/usr/runtime/populate_attributes.C @@ -209,9 +209,9 @@ struct system_data_t struct node_data_t { enum { - MAX_PROCS_RSV = P8_MAX_PROCS*2, //leave space for double + MAX_PROCS_RSV = P8_MAX_PROCS+4, //leave space for double MAX_EX_RSV = MAX_PROCS_RSV*P8_MAX_EX_PER_PROC, - NUM_PROC_ATTRIBUTES = 225, + NUM_PROC_ATTRIBUTES = 250, NUM_EX_ATTRIBUTES = 20, MAX_ATTRIBUTES = MAX_PROCS_RSV*NUM_PROC_ATTRIBUTES + MAX_EX_RSV*NUM_EX_ATTRIBUTES diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index 11ea981e5..295786aef 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -5504,11 +5504,11 @@ firmware notes: Used as override attribute for pstate procedure consumer: proc_pcie_scominit firmware notes: Encoded PCIE IOP swap configuration - Array index: IOP number (0:1) + Array index: IOP number (0:2) </description> <simpleType> <uint8_t></uint8_t> - <array>2</array> + <array>3</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -5526,7 +5526,7 @@ firmware notes: Used as override attribute for pstate procedure consumer: proc_pcie_scominit firmware notes: Bit mask defining set of active/valid PHBs - bit0=PHB0, bit1=PHB1, bit2=PHB2 + bit0=PHB0, bit1=PHB1, bit2=PHB2, bit3=PHB3 </description> <simpleType><uint8_t></uint8_t></simpleType> <persistency>non-volatile</persistency> @@ -5546,11 +5546,11 @@ firmware notes: Used as override attribute for pstate procedure firmware notes: PCIe Gen3 PLL Control Register 0. ATUNE/CPISEL. - Array index: IOP number(0:1) + Array index: IOP number(0:2) </description> <simpleType> <uint32_t></uint32_t> - <array>2</array> + <array>3</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -5568,11 +5568,11 @@ firmware notes: Used as override attribute for pstate procedure firmware notes: PCIe Gen2/Gen1 PLL Control Register 0. ATUNE/CPISEL. - Array index: IOP number(0:1) + Array index: IOP number(0:2) </description> <simpleType> <uint32_t></uint32_t> - <array>2</array> + <array>3</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -5590,11 +5590,11 @@ firmware notes: Used as override attribute for pstate procedure notes: PCIe PLL Global Control Register 0. REFISRC/REFISINK. - Array index: IOP number (0:1) + Array index: IOP number (0:2) </description> <simpleType> <uint32_t></uint32_t> - <array>2</array> + <array>3</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -5612,11 +5612,11 @@ firmware notes: Used as override attribute for pstate procedure notes: PCIe PLL Global Control Register 1. ENBGDOCPSRC/ENBGDOCAMP/REFVREG. - Array index: IOP number (0:1) + Array index: IOP number (0:2) </description> <simpleType> <uint32_t></uint32_t> - <array>2</array> + <array>3</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -5635,11 +5635,11 @@ firmware notes: Used as override attribute for pstate procedure PCIe PCS Control Register 0. BITLOCKTIME/ADDDREMDELTA_810_B/STARTUPDELTA_810_B/ADDDREMDELTA_810_A/ STARTUPDELTA_A/RXREJECTHANDLING/EQCOMLETERESPONSE. - Array index: IOP number (0:1) + Array index: IOP number (0:2) </description> <simpleType> <uint32_t></uint32_t> - <array>2</array> + <array>3</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -5658,11 +5658,11 @@ firmware notes: Used as override attribute for pstate procedure PCIe PCS Control Register 1. RXSIGDETSETTING/ADDDREMDELTA_128130_B/STARTUPDELTA_128130_B/ ADDDREMDELTA_128130_A/STARTUPDELTA_128130_A. - Array index: IOP number (0:1) + Array index: IOP number (0:2) </description> <simpleType> <uint32_t></uint32_t> - <array>2</array> + <array>3</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -5680,12 +5680,12 @@ firmware notes: Used as override attribute for pstate procedure notes: PCIe TX FIFO Offset Register. G3OFFSET/G2OFFSET/G1OFFSET. - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <simpleType> <uint32_t></uint32_t> - <array>2,16</array> + <array>3,16</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -5703,12 +5703,12 @@ firmware notes: Used as override attribute for pstate procedure notes: PCIe TX Receiver Detect Control Register. VREFSEL/RCVRDETCNT/DETDRVC/PH1WAIT. - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <simpleType> <uint32_t></uint32_t> - <array>2,16</array> + <array>3,16</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -5726,12 +5726,12 @@ firmware notes: Used as override attribute for pstate procedure notes: PCIe TX Bandwidth Loss Coefficient Register. GEN3BWCOEFF/GEN2BWCOEFF/GEN1BWCOEFF. - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <simpleType> <uint32_t></uint32_t> - <array>2,16</array> + <array>3,16</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -5749,12 +5749,12 @@ firmware notes: Used as override attribute for pstate procedure notes: PCIe RX VGA Control Register 2. GAIN2/GAIN1. - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <simpleType> <uint32_t></uint32_t> - <array>2,16</array> + <array>3,16</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -5772,12 +5772,12 @@ firmware notes: Used as override attribute for pstate procedure notes: PCIe RX Receiver Peaking Value Register. PEAK1/PEAK2/PEAK3. - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <simpleType> <uint32_t></uint32_t> - <array>2,16</array> + <array>3,16</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -5795,12 +5795,12 @@ firmware notes: Used as override attribute for pstate procedure notes: PCIe RX Signal Detect Level Register. SDLVL3/SDLVL2/SDLVL1. - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <simpleType> <uint32_t></uint32_t> - <array>2,16</array> + <array>3,16</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -5818,11 +5818,11 @@ firmware notes: Used as override attribute for pstate procedure notes: PCIe ZCAL Control Register. CMPEVALDLY. - Array index: IOP number (0:1) + Array index: IOP number (0:2) </description> <simpleType> <uint32_t></uint32_t> - <array>2</array> + <array>3</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -10642,11 +10642,10 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript consumer: proc_pcie_scominit firmware notes: Bit mask defining state of refclock drive enables - bit0=PCI0, bit1=PCI1, bit2=PCI2 + bit0=PCI0, bit1=PCI1, bit2=PCI2, bit3=PCI3 </description> <simpleType> <uint8_t> - <default>0xE0</default> </uint8_t> </simpleType> <persistency>non-volatile</persistency> @@ -13098,12 +13097,12 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript consumer: proc_pcie_scominit notes: PCIe TX FFE (Gen1) - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <simpleType> <uint32_t></uint32_t> - <array>2,16</array> + <array>3,16</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -13120,12 +13119,12 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript consumer: proc_pcie_scominit notes: PCIe TX FFE (Gen2) - First array index: IOP number (0:1) + First array index: IOP number (0:2) Second array index: Lane number (0:15) </description> <simpleType> <uint32_t></uint32_t> - <array>2,16</array> + <array>3,16</array> </simpleType> <persistency>non-volatile</persistency> <readable/> @@ -14503,22 +14502,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </attribute> <attribute> - <id>IOP_LANES_PER_PROC</id> - <description>Number of PCIE lanes per processor - Creator: Targeting definition - Purpose: Determines which IOP configuration table is used to build the - PE lane config value and PHB active masks for the HWPs - Data format: value of 24 or 32 (lanes per processor) - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> <id>PROC_PCIE_LANE_MASK</id> <description>Effective PCIE Lane Mask Creator: Firmware @@ -14916,6 +14899,64 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </hwpfToHbAttrMap> </attribute> +<attribute> + <id>PROC_PCIE_NUM_PHB</id> + <description> + creator: platform + Number of PCIe PHB units present on target + Murano/Venice: 3 + Naples: 4 + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_PCIE_NUM_PHB</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_PCIE_NUM_IOP</id> + <description> + creator: platform + Number of PCIe IOP units present on target + Murano/Venice: 2 + Naples: 3 + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_PCIE_NUM_IOP</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_PCIE_NUM_LANES</id> + <description> + creator: platform + Number of PCIe I/O lanes supported by target + Murano: 24 + Venice: 32 + Naples: 40 + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_PCIE_NUM_LANES</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + <!-- === Manufacturing threshold Attributes of PRD === --> <attribute> diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index 8d006cc9a..836648a1f 100644 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -564,8 +564,6 @@ <attribute><id>PROC_PCIE_IOP_CONFIG</id></attribute> <attribute><id>PROC_PCIE_IOP_SWAP</id></attribute> <attribute><id>PROC_PCIE_PHB_ACTIVE</id></attribute> - - <attribute><id>IOP_LANES_PER_PROC</id></attribute> <attribute><id>PROC_PCIE_LANE_MASK</id></attribute> <attribute><id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id></attribute> <attribute><id>PROC_PCIE_LANE_MASK_BIFURCATED</id></attribute> @@ -620,10 +618,12 @@ <attribute><id>PROC_BOOT_VOLTAGE_VID</id></attribute> <attribute><id>PROC_PBA_UNTRUSTED_BAR_BASE_ADDR</id></attribute> <attribute><id>PROC_PBA_UNTRUSTED_BAR_SIZE</id></attribute> - <attribute><id>PROC_PCIE_IOP_TX_FFE_GEN1</id></attribute> <attribute><id>PROC_PCIE_IOP_TX_FFE_GEN2</id></attribute> <attribute><id>I2C_SLAVE_ADDRESS</id></attribute> + <attribute><id>PROC_PCIE_NUM_PHB</id></attribute> + <attribute><id>PROC_PCIE_NUM_IOP</id></attribute> + <attribute><id>PROC_PCIE_NUM_LANES</id></attribute> </targetType> <targetType> @@ -636,9 +636,21 @@ <attribute><id>DUMMY_RW</id></attribute> <attribute><id>DUMMY_HEAP_ZERO_DEFAULT</id></attribute> <attribute> - <id>IOP_LANES_PER_PROC</id> + <id>PROC_PCIE_NUM_PHB</id> + <default>3</default> + </attribute> + <attribute> + <id>PROC_PCIE_NUM_IOP</id> + <default>2</default> + </attribute> + <attribute> + <id>PROC_PCIE_NUM_LANES</id> <default>32</default> </attribute> + <attribute> + <id>PROC_PCIE_REFCLOCK_ENABLE</id> + <default>0xE0</default> + </attribute> </targetType> <targetType> @@ -648,10 +660,22 @@ <id>MODEL</id> <default>MURANO</default> </attribute> - <attribute> - <id>IOP_LANES_PER_PROC</id> + <attribute> + <id>PROC_PCIE_NUM_PHB</id> + <default>3</default> + </attribute> + <attribute> + <id>PROC_PCIE_NUM_IOP</id> + <default>2</default> + </attribute> + <attribute> + <id>PROC_PCIE_NUM_LANES</id> <default>24</default> - </attribute> + </attribute> + <attribute> + <id>PROC_PCIE_REFCLOCK_ENABLE</id> + <default>0xE0</default> + </attribute> </targetType> <targetType> @@ -661,10 +685,22 @@ <id>MODEL</id> <default>NAPLES</default> </attribute> - <attribute> - <id>IOP_LANES_PER_PROC</id> - <default>32</default> - </attribute> + <attribute> + <id>PROC_PCIE_NUM_PHB</id> + <default>4</default> + </attribute> + <attribute> + <id>PROC_PCIE_NUM_IOP</id> + <default>3</default> + </attribute> + <attribute> + <id>PROC_PCIE_NUM_LANES</id> + <default>40</default> + </attribute> + <attribute> + <id>PROC_PCIE_REFCLOCK_ENABLE</id> + <default>0xF0</default> + </attribute> </targetType> <targetType> diff --git a/src/usr/targeting/common/xmltohb/target_types_hb.xml b/src/usr/targeting/common/xmltohb/target_types_hb.xml index 39a032fd3..c1f74f3dc 100644 --- a/src/usr/targeting/common/xmltohb/target_types_hb.xml +++ b/src/usr/targeting/common/xmltohb/target_types_hb.xml @@ -118,11 +118,9 @@ <id>XSCOM_VIRTUAL_ADDR</id> </attribute> <attribute><id>IPMI_SENSORS</id></attribute> + <attribute><id>HB_TARGET_SCOMABLE</id></attribute> </targetTypeExtension> - - - <!-- Centaur chip/DMI --> <targetTypeExtension> @@ -161,6 +159,7 @@ <targetTypeExtension> <id>unit-core-power8</id> <attribute><id>IPMI_SENSORS</id></attribute> + <attribute><id>HB_TARGET_SCOMABLE</id></attribute> </targetTypeExtension> <targetTypeExtension> @@ -168,6 +167,7 @@ <attribute> <id>HB_PM_SPWUP_OHA_FLAG</id> </attribute> + <attribute><id>HB_TARGET_SCOMABLE</id></attribute> </targetTypeExtension> <targetTypeExtension> @@ -193,6 +193,22 @@ <attribute><id>N_PLUS_ONE_N_PER_CHIP</id></attribute> <attribute><id>OVERSUB_N_PER_MBA</id></attribute> <attribute><id>OVERSUB_N_PER_CHIP</id></attribute> + <attribute><id>HB_TARGET_SCOMABLE</id></attribute> +</targetTypeExtension> + +<targetTypeExtension> + <id>unit-mcs-power8</id> + <attribute><id>HB_TARGET_SCOMABLE</id></attribute> </targetTypeExtension> +<targetType> + <id>unit-xbus-power8</id> + <attribute><id>HB_TARGET_SCOMABLE</id></attribute> +</targetType> + +<targetType> + <id>unit-abus-power8</id> + <attribute><id>HB_TARGET_SCOMABLE</id></attribute> +</targetType> + </attributes> |
