diff options
Diffstat (limited to 'src')
| -rwxr-xr-x | src/build/tools/addCopyright | 12 | ||||
| -rwxr-xr-x | src/build/tools/applyTargetingStyle | 20 | ||||
| -rw-r--r-- | src/build/tools/insert_newlines.xsl | 40 | ||||
| -rwxr-xr-x | src/build/tools/pre-commit-actions | 6 | ||||
| -rw-r--r-- | src/build/tools/sort_targeting.xsl | 52 | ||||
| -rwxr-xr-x | src/usr/targeting/common/xmltohb/attribute_types.xml | 10834 | ||||
| -rwxr-xr-x | src/usr/targeting/common/xmltohb/attribute_types_cfm.xml | 78 | ||||
| -rwxr-xr-x | src/usr/targeting/common/xmltohb/attribute_types_hb.xml | 1568 | ||||
| -rw-r--r-- | src/usr/targeting/common/xmltohb/attribute_types_openpower.xml | 1763 | ||||
| -rw-r--r-- | src/usr/targeting/common/xmltohb/attribute_types_oppowervm.xml | 744 | ||||
| -rw-r--r-- | src/usr/targeting/common/xmltohb/target_types.xml | 5205 | ||||
| -rw-r--r-- | src/usr/targeting/common/xmltohb/target_types_cfm.xml | 47 | ||||
| -rw-r--r-- | src/usr/targeting/common/xmltohb/target_types_hb.xml | 359 | ||||
| -rw-r--r-- | src/usr/targeting/common/xmltohb/target_types_openpower.xml | 432 | ||||
| -rw-r--r-- | src/usr/targeting/common/xmltohb/target_types_oppowervm.xml | 372 |
15 files changed, 11115 insertions, 10417 deletions
diff --git a/src/build/tools/addCopyright b/src/build/tools/addCopyright index c43f9f323..2e067902a 100755 --- a/src/build/tools/addCopyright +++ b/src/build/tools/addCopyright @@ -459,6 +459,10 @@ sub filetype { return "xml" } + if ( $filename =~ m/\.xsl$/i ) + { + return "xsl" + } if ( $filename =~ m/\.txt$/i ) { return "txt" @@ -777,6 +781,10 @@ sub removeCopyrightBlock { $data = removeProlog( $data, '<!--', '-->' ); } + elsif ( $filetype eq "xsl" ) + { + $data = removeProlog( $data, '<!--', '-->' ); + } elsif ( "Assembly" eq $filetype ) { $data = removeProlog( $data, '\#', '' ); @@ -1035,6 +1043,10 @@ EOF { $IBMCopyrightBlock = addPrologComments($IBMCopyrightBlock, '<!--', '-->'); } + elsif ( "xsl" eq $filetype) + { + $IBMCopyrightBlock = addPrologComments($IBMCopyrightBlock, '<!--', '-->'); + } else { print STDOUT "ERROR: Can\'t handle filetype: $filetype\n"; diff --git a/src/build/tools/applyTargetingStyle b/src/build/tools/applyTargetingStyle new file mode 100755 index 000000000..7fc5d198d --- /dev/null +++ b/src/build/tools/applyTargetingStyle @@ -0,0 +1,20 @@ +#!/usr/bin/bash + +for var in "$@" +do + if [[ $var = *target_types*.xml ]] || [[ $var = *attribute_types*.xml ]] ; + then + echo "Applying targeting sort for file: " + echo " $var" + xsltproc $TOOLSDIR/sort_targeting.xsl $var > temp.xml + rc=$?; if [[ $rc != 0 ]]; then exit $rc; fi + xsltproc $TOOLSDIR/insert_newlines.xsl temp.xml > $var + rc=$?; if [[ $rc != 0 ]]; then exit $rc; fi + rm temp.xml + rc=$?; if [[ $rc != 0 ]]; + then + echo "rm $PROJECT_ROOT/temp.xml failed. Manual removal required." + fi + fi +done + diff --git a/src/build/tools/insert_newlines.xsl b/src/build/tools/insert_newlines.xsl new file mode 100644 index 000000000..637c22b57 --- /dev/null +++ b/src/build/tools/insert_newlines.xsl @@ -0,0 +1,40 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/build/tools/insert_newlines.xsl $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2018 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<xsl:stylesheet version="1.0" xmlns:xsl="http://www.w3.org/1999/XSL/Transform"> + <xsl:output method="xml" indent="no" omit-xml-declaration="yes"/> + + <!-- Copy everything from the source file to the destination as it is but + add newlines if the current match is a child element of the root node. + --> + <xsl:template match="@*|node()"> + <xsl:copy> + <xsl:apply-templates select="@*|node()"/> + </xsl:copy> + <xsl:if test=". = /node()/*"> + <xsl:text>
</xsl:text> + </xsl:if> + </xsl:template> + +</xsl:stylesheet> diff --git a/src/build/tools/pre-commit-actions b/src/build/tools/pre-commit-actions index d47dfff74..a914663d2 100755 --- a/src/build/tools/pre-commit-actions +++ b/src/build/tools/pre-commit-actions @@ -6,7 +6,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2015,2016 +# Contributors Listed Below - COPYRIGHT 2015,2018 # [+] International Business Machines Corp. # # @@ -28,6 +28,7 @@ # the code beautifier astyle. my $copyrightScript = "addCopyright"; +my $xmlSortingScript = "applyTargetingStyle"; ## Make up a list of all staged files ( --cached --name-only ) ## Filter for only Added or Modified ( --diff-filter=AM ) @@ -43,6 +44,9 @@ if ( @fileList ) system "$ENV{'TOOLSDIR'}/$copyrightScript update @fileList"; die("$?") if ($? != 0); + system "$ENV{'TOOLSDIR'}/$xmlSortingScript @fileList"; + die("$?") if ($? != 0); + system "git add @fileList"; exit 1 if ($? != 0); } diff --git a/src/build/tools/sort_targeting.xsl b/src/build/tools/sort_targeting.xsl new file mode 100644 index 000000000..47e5c98b9 --- /dev/null +++ b/src/build/tools/sort_targeting.xsl @@ -0,0 +1,52 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/build/tools/sort_targeting.xsl $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2018 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<xsl:stylesheet version="1.0" xmlns:xsl="http://www.w3.org/1999/XSL/Transform"> +<xsl:output method="xml" indent="yes" omit-xml-declaration="yes"/> +<xsl:strip-space elements="*"/> + +<!-- Setup a key that maps preceding comments to the first following sibling. + That way the output can keep the comments in the same relative position + after sorting has occurred. + --> +<xsl:key name = "k_precedingComment" + match = "comment()" + use = "generate-id(following-sibling::*[1])" /> + +<!-- For each element in the file sort it recursively based on its child + <id> tag. If an element doesn't have a child <id> tag then its order + relative to its parent won't change. + --> +<xsl:template match="*"> + <!-- Add the preceding comments back atop the current matched element --> + <xsl:copy-of select="key('k_precedingComment', generate-id())" /> + <xsl:copy> + <xsl:apply-templates select="@*"/> + <xsl:apply-templates select="node()"> + <xsl:sort select="id"/> + </xsl:apply-templates> + </xsl:copy> +</xsl:template> + +</xsl:stylesheet> diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index 892e8d145..38c3a5b09 100755 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -22,333 +22,725 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> - <attributes> <attribute> - <description>Attribute indicating the target's class</description> - <hasStringConversion></hasStringConversion> - <id>CLASS</id> + <description>Hierarchical path to the target with respect to logical affinity</description> + <id>AFFINITY_PATH</id> + <nativeType> + <name>EntityPath</name> + </nativeType> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + <no_export/> + </attribute> + + <attribute> + <id>ALL_MCS_IN_INTERLEAVING_GROUP</id> + <description> + System attribute. + If all MCS chiplets are in an interleaving group (1=true, 0=false). + - If true the SMP fabric is setup in normal mode and multiple MCSs + are grouped (disallowing systems with memory only under 1 MCS + (i.e. systems with a single C-DIMM)) + - If false the SMP fabric is setup in checkerboard mode. + Provided by the Machine Readable Workbook. + This attribute is based on Machine-Type-Model (MTM) and is setup by + the service processor. + </description> <simpleType> - <enumeration> - <id>CLASS</id> - </enumeration> + <uint8_t> + <default>0x00</default> + </uint8_t> </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> </attribute> <attribute> - <description>Attribute indicating the target's type</description> - <hasStringConversion></hasStringConversion> - <id>TYPE</id> + <description>Chip which contains the FSI master logic that drives this slave when booting from the alternate master processor</description> + <id>ALTFSI_MASTER_CHIP</id> + <nativeType> + <default>physical:sys-0</default> + <name>EntityPath</name> + </nativeType> <persistency>non-volatile</persistency> - <readable></readable> - <simpleType> - <enumeration> - <id>TYPE</id> - </enumeration> - </simpleType> + <readable/> + <no_export/> </attribute> + <attribute> - <description>Attribute indicating the target's model</description> - <hasStringConversion></hasStringConversion> - <id>MODEL</id> + <description>Which port is this chip hanging off of when booting from the alternate master processor</description> + <id>ALTFSI_MASTER_PORT</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <enumeration> - <id>MODEL</id> - </enumeration> + <uint8_t> + <default>0xFF</default> + </uint8_t> </simpleType> + <no_export/> </attribute> <attribute> - <description>Attribute indicating the target's engine type</description> - <hasStringConversion></hasStringConversion> - <id>ENGINE_TYPE</id> - <persistency>non-volatile</persistency> - <readable></readable> + <id>ASYNC_NEST_FREQ_MHZ</id> + <description> + The asynchronous nest frequency + </description> <simpleType> - <enumeration> - <id>ENGINE_TYPE</id> - </enumeration> + <uint32_t> + <default>2000</default> + </uint32_t> </simpleType> + <persistency>non-volatile</persistency> + <readable/> </attribute> + <attribute> + <id>ATTN_AREA_1_ADDR</id> + <description> + Specifies the "intended" starting memory address for PHYP's ATTN area 1. + This is written to by Hostboot and read by FSP as a means for Hostboot to + communicate its intentions of where the ATTN 1 area will be. Hostboot can + then later open up an SBE window for PHYP to dump its debugging info. An + address of 0xFFFFFFFFFFFFFFFF is considered N/A. + </description> + <simpleType> + <uint64_t> + <default>0xFFFFFFFFFFFFFFFF</default> + </uint64_t> + </simpleType> + <persistency>volatile</persistency> + <readable/> + <writeable/> + <no_export/> + </attribute> <attribute> - <description>Dummy attribute with read/write permissions</description> - <hwpfToHbAttrMap> - <id>ATTR_DUMMY_SCRATCH_PLAT_INIT_UINT8</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <id>DUMMY_RW</id> - <persistency>non-volatile</persistency> - <readable></readable> + <id>ATTN_AREA_2_ADDR</id> + <description> + Specifies the "intended" starting memory address for PHYP's ATTN area 2. + This is written to by Hostboot and read by FSP as a means for Hostboot to + communicate its intentions of where the ATTN 2 area will be. Hostboot can + then later open up an SBE window for PHYP to dump its debugging info. An + address of 0xFFFFFFFFFFFFFFFF is considered N/A. + </description> <simpleType> - <array>1,3,5</array> - <uint8_t> - <default>5</default> - </uint8_t> + <uint64_t> + <default>0xFFFFFFFFFFFFFFFF</default> + </uint64_t> </simpleType> - <writeable></writeable> - <ignoreEkb/> + <persistency>volatile</persistency> + <readable/> + <writeable/> + <no_export/> </attribute> <attribute> - <description>Dummy attribute with write-only permissions</description> - <id>DUMMY_WO</id> + <description> + Memory AVDD voltage domain ID. All memory buffers in the same AVDD + voltage domain will share the same ID. IDs are arbitrarily assigned, + used for correlation between HB + HWSV, and are generated by + genHwsvMrwXml.pl + </description> + <id>AVDD_ID</id> <persistency>non-volatile</persistency> + <readable/> <simpleType> - <uint8_t> + <uint16_t> <default>0</default> - </uint8_t> + </uint16_t> </simpleType> - <writeable></writeable> </attribute> <attribute> - <description>Dummy attribute with read-only permissions</description> - <id>DUMMY_RO</id> + <description>Block speculative deconfig in reconfig loop. + Flags when speculative deconfigurations should not be done for + predictive gard records on a reconfig loop IPL due to out of + hardware condition on prior IPL. + 0 = Allow speculative deconfiguration + 1 = Block speculative deconfiguration + </description> + <id>BLOCK_SPEC_DECONFIG</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <uint8_t> - <default>0</default> + <default>0x0</default> </uint8_t> </simpleType> + <writeable/> </attribute> <attribute> - <description>Dummy attribute on the heap with zero initialization</description> - <id>DUMMY_HEAP_ZERO_DEFAULT</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> + <description>BMC FRU ID attribute to report the system firmware levels + to the BMC.</description> + <id>BMC_FRU_ID</id> + <persistency>non-volatile</persistency> + <readable/> <simpleType> - <uint8_t></uint8_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> </attribute> <attribute> - <description>Location code of the Fru target</description> - <id>LOCATION_CODE</id> + <id>BRAZOS_RX_FIFO_OVERRIDE</id> + <description> + Defines where to apply Brazos rx_fifo_final_l2u_dly override settings for SW299500. + </description> <simpleType> - <string> - <sizeInclNull>64</sizeInclNull> - </string> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> </attribute> <attribute> - <description>Physical hierarchical path to the target</description> - <id>PHYS_PATH</id> - <nativeType> - <name>EntityPath</name> - </nativeType> + <description> + Specifies a target's CEC degraded mode domain. For example, all + DIMMs are part of the DIMM CEC degraded mode domain. + </description> + <hasStringConversion/> + <id>CDM_DOMAIN</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + <simpleType> + <enumeration> + <id>CDM_DOMAIN</id> + </enumeration> + </simpleType> </attribute> - <attribute> - <description>Hierarchical path to the target with respect to logical affinity</description> - <id>AFFINITY_PATH</id> - <nativeType> - <name>EntityPath</name> - </nativeType> - <persistency>non-volatile</persistency> - <readable></readable> - <no_export/> - </attribute> + <enumerationType> + <default>NONE</default> + <description> + Enumeration specifying a target's CEC degraded mode domain + </description> + <enumerator> + <name>NONE</name> + <value>0</value> + </enumerator> + <enumerator> + <name>CPU</name> + <value>1</value> + </enumerator> + <enumerator> + <name>DIMM</name> + <value>2</value> + </enumerator> + <enumerator> + <name>FABRIC</name> + <value>3</value> + </enumerator> + <enumerator> + <name>MEM</name> + <value>4</value> + </enumerator> + <enumerator> + <name>IO</name> + <value>5</value> + </enumerator> + <enumerator> + <name>NODE</name> + <value>6</value> + </enumerator> + <enumerator> + <name>CLOCK</name> + <value>7</value> + </enumerator> + <enumerator> + <name>PSI</name> + <value>8</value> + </enumerator> + <enumerator> + <name>FSP</name> + <value>9</value> + </enumerator> + <enumerator> + <name>ALL</name> + <value>10</value> + </enumerator> + <id>CDM_DOMAIN</id> + </enumerationType> <attribute> - <description>Hierarchical path to the target with respect to power</description> - <id>POWER_PATH</id> - <nativeType> - <name>EntityPath</name> - </nativeType> + <description> + Cec Degraded Mode Policy flags + Use the CDM_POLICIES enum to decode. + If the appropriate bit is 1 then the policy mode is enabled, + and those type of Guard records are disabled. + </description> + <id>CDM_POLICIES</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + <simpleType> + <uint8_t> + <default>0x00</default> + </uint8_t> + </simpleType> + <writeable/> </attribute> + <enumerationType> + <description>Enumeration of CDM_POLICIES flags</description> + <enumerator> + <description> + MFG_Guard policy: + Used in MFG only to prevent and disable the following: + . Storing or creation of new Guard records from Diagno`stic or other + faults through error logs. This is all domains, CEC + processor/memory, VPD, FSP, etc. + . Storing or creation of Manual Guard record from user. + NOTE: this does not stop FCO. + . Using an already stored System or Manual Guard record from + deconfiguring resources. This is all domains, CEC + processor/memory, VPD, FSP, etc. + </description> + <name>MANUFACTURING_DISABLED</name> + <value>0x01</value> + </enumerator> + <enumerator> + <description> + Predictive_Guard policy: + Used in Field or development to prevent and disable the following: + . Storing or creation of new Guard records from diagnostics or other + faults through error logs with the error_type of Predictive. + . Using an already stored System Guard record with error_type of + Predictive from deconfiguring resources. + </description> + <name>PREDICTIVE_DISABLED</name> + <value>0x02</value> + </enumerator> + <id>CDM_POLICIES</id> + </enumerationType> + <attribute> <complexType> - <description>Structure which defines a target's primary capabilities. - A target can only support at most FSI SCOM and one of the other two SCOM - types. Applicable for all targets. Structure is read-only. + <description>Structure which defines a they IPL types + Applicable for System target only. </description> <field> <bits>1</bits> <default>0</default> - <description>0b0: Target does not support FSI SCOM; - 0b1: Target supports FSI SCOM + <description> + Perform mainstore dump collection. Only valid for MPIPL + 0b0: Do not collect mainstore dump + 0b1: Perform mainstore dump collection </description> - <name>supportsFsiScom</name> - <type>uint8_t</type> - </field> - <field> - <bits>1</bits> - <default>0</default> - <description>0b0: Target does not support XSCOM; - 0b1: Target supports FSI XSCOM</description> - <name>supportsXscom</name> - <type>uint8_t</type> - </field> - <field> - <bits>1</bits> - <default>0</default> - <description>0b0: Target does not support inband SCOM</description> - <name>supportsInbandScom</name> + <name>PostDump</name> <type>uint8_t</type> </field> <field> - <bits>5</bits> + <bits>7</bits> <default>0</default> - <description>Reserved for future use</description> - <name>reserved</name> + <description>Minor IPL Type</description> + <name>MinorIPLType</name> <type>uint8_t</type> </field> </complexType> - <description>Attribute which describes capabilities of a target</description> - <id>PRIMARY_CAPABILITIES</id> + <description> + Attribute which describes optional IPL flavors + </description> + <id>CEC_IPL_TYPE</id> + <persistency>volatile</persistency> + <readable/> + <writeable/> + </attribute> + + <attribute> + <description>FRU ID attribute for centaur ECID data. This fru ID is used to + report the ECID data to the BMC and make it available for systems which + have then centaur chips soldered to the backplane.</description> + <id>CENTAUR_ECID_FRU_ID</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + <simpleType> + <uint32_t/> + </simpleType> </attribute> <attribute> - <description>CPU Attribute</description> - <id>CPU_ATTR</id> + <description> + DRAM Voltage, each voltage rail would need to have a value. + Computed in mss_volt C code - in millivolts + creator: mss_volt + consumer: mss_eff_cnfg, others + firmware notes: none + </description> + <id>CEN_MSS_VOLT_AVDD_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable/> + <simpleType> + <uint32_t/> + </simpleType> + <writeable/> + </attribute> + + <attribute> + <description> + DRAM Voltage, each voltage rail would need to have a value. + Computed in mss_volt C code - in millivolts + creator: mss_volt + consumer: mss_eff_cnfg, others + firmware notes: none + </description> + <id>CEN_MSS_VOLT_AVDD_OFFSET_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable/> + <simpleType> + <uint32_t/> + </simpleType> + <writeable/> + </attribute> + + <attribute> + <description> + Computed in mss_volt C code - in millivolts + creator: mss_volt + consumer: mss_eff_cnfg, others + firmware notes: none + </description> + <id>CEN_MSS_VOLT_VCS_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable/> + <simpleType> + <uint32_t/> + </simpleType> + <writeable/> + </attribute> + + <attribute> + <description> + Computed in mss_volt C code - in millivolts + creator: mss_volt + consumer: mss_eff_cnfg, others + firmware notes: none + </description> + <id>CEN_MSS_VOLT_VCS_OFFSET_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable/> + <simpleType> + <uint32_t/> + </simpleType> + <writeable/> + </attribute> + + <attribute> + <description> + DRAM Voltage, each voltage rail would need to have a value. + Computed in mss_volt C code - in millivolts + creator: mss_volt + consumer: mss_eff_cnfg, others + firmware notes: none + </description> + <id>CEN_MSS_VOLT_VDDR_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable/> + <simpleType> + <uint32_t/> + </simpleType> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_CEN_MSS_VOLT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> + </attribute> + + <attribute> + <description> + DRAM Voltage, each voltage rail would need to have a value. + Computed in mss_volt C code - in millivolts + creator: mss_volt + consumer: mss_eff_cnfg, others + firmware notes: none + </description> + <id>CEN_MSS_VOLT_VDDR_OFFSET_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable/> + <simpleType> + <uint32_t/> + </simpleType> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_CEN_MSS_VDDR_OFFSET</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> + </attribute> + + <attribute> + <description> + DRAM Voltage, each voltage rail would need to have a value. + Computed in mss_volt C code - in millivolts + creator: mss_volt + consumer: mss_eff_cnfg, others + firmware notes: none + </description> + <id>CEN_MSS_VOLT_VDD_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable/> + <simpleType> + <uint32_t/> + </simpleType> + <writeable/> + </attribute> + + <attribute> + <description> + DRAM Voltage, each voltage rail would need to have a value. + Computed in mss_volt C code - in millivolts + creator: mss_volt + consumer: mss_eff_cnfg, others + firmware notes: none + </description> + <id>CEN_MSS_VOLT_VDD_OFFSET_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable/> + <simpleType> + <uint32_t/> + </simpleType> + <writeable/> + </attribute> + + <attribute> + <description> + DRAM VPP Voltage, each voltage rail would need to have a value. + Computed in mss_volt C code - in millivolts. 0V - DDR3, 2.5V - DDR4 + creator: mss_volt + consumer: mss_eff_cnfg, others + firmware notes: none + </description> + <id>CEN_MSS_VOLT_VPP_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable/> + <simpleType> + <uint32_t/> + </simpleType> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_CEN_MSS_VOLT_VPP</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> + </attribute> + + <attribute> + <description> + DRAM VPP Voltage, each voltage rail would need to have a value. + Computed in mss_volt C code - in millivolts. 0V - DDR3, 2.5V - DDR4 + creator: mss_volt + consumer: mss_eff_cnfg, others + firmware notes: none + </description> + <id>CEN_MSS_VOLT_VPP_OFFSET_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable/> + <simpleType> + <uint32_t/> + </simpleType> + <writeable/> + </attribute> + + <attribute> + <description>The address offset which each Chiplet types pervasive + address space used to represent the a chiplet. + 0x00 to 0x0F => For P9 all non-core and non-cache chiplets + 0x10 to 0x1F => All Cache Chiplets + 0x20 to 0x37 => All Core Chiplets + 0x38 to 0x3F => Multicast Operation + </description> + <id>CHIPLET_ID</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t></uint32_t> + <uint8_t> + <default>0xFF</default> + </uint8_t> </simpleType> </attribute> <attribute> - <complexType> - <description>Structure which defines which SCOM to use at a point in - time. Only applicable if target supports one or more SCOM types. Only - one bit (of the first three) can ever be set at any one time. - </description> - <field> - <bits>1</bits> - <default>0</default> - <description>0b0: Do not use FSI SCOM at this time. 0b1: Use FSI - SCOM at this time</description> - <name>useFsiScom</name> - <type>uint8_t</type> - </field> - <field> - <bits>1</bits> - <default>0</default> - <description>0b0: Do not use XSCOM at this time. 0b1: Use XSCOM at - this time</description> - <name>useXscom</name> - <type>uint8_t</type> - </field> - <field> - <bits>1</bits> - <default>0</default> - <description>0b0: Do not use inband SCOM at this time. 0b1: Use - inband SCOM at this time</description> - <name>useInbandScom</name> - <type>uint8_t</type> - </field> - <field> - <bits>1</bits> - <default>0</default> - <description>0b0: Do not use SBE SCOM at this time. 0b1: Use - SBE SCOM at this time</description> - <name>useSbeScom</name> - <type>uint8_t</type> - </field> - <field> - <bits>4</bits> + <id>CHIP_ID</id> + <description>attribute indicating the chip's ID</description> + <simpleType> + <uint32_t/> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + </attribute> + + <attribute> + <description>A unit (chiplet) 's offset number within the chip. </description> + <id>CHIP_UNIT</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint8_t> <default>0</default> - <description>Reserved for future expansion</description> - <name>reserved</name> - <type>uint8_t</type> - </field> - </complexType> - <description>Attribute storing information about which SCOM path to use</description> - <id>SCOM_SWITCHES</id> - <persistency>volatile</persistency> - <readable></readable> - <writeable></writeable> + </uint8_t> + </simpleType> + <hwpfToHbAttrMap> + <id>ATTR_CHIP_UNIT_POS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> - <description>Chip which contains the FSI master logic that drives this slave when booting from the default master processor</description> - <id>FSI_MASTER_CHIP</id> - <nativeType> - <default>physical:sys-0</default> - <name>EntityPath</name> - </nativeType> + <description>Attribute indicating the target's class</description> + <hasStringConversion/> + <id>CLASS</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <enumeration> + <id>CLASS</id> + </enumeration> + </simpleType> + </attribute> + + <enumerationType> + <default>NA</default> + <description>Enumeration indicating the target's class</description> + <enumerator> + <name>NA</name> + <value>0</value> + </enumerator> + <enumerator> + <name>CARD</name> + <value>1</value> + </enumerator> + <enumerator> + <name>ENC</name> + <value>2</value> + </enumerator> + <enumerator> + <name>CHIP</name> + <value>3</value> + </enumerator> + <enumerator> + <name>UNIT</name> + <value>4</value> + </enumerator> + <enumerator> + <name>DEV</name> + <value>5</value> + </enumerator> + <enumerator> + <name>SYS</name> + <value>6</value> + </enumerator> + <enumerator> + <name>LOGICAL_CARD</name> + <value>7</value> + </enumerator> + <enumerator> + <name>BATTERY</name> + <value>8</value> + </enumerator> + <enumerator> + <name>LED</name> + <value>9</value> + </enumerator> + <enumerator> + <name>SP</name> + <value>10</value> + </enumerator> + <enumerator> + <name>MAX</name> + <value>11</value> + </enumerator> + <id>CLASS</id> + </enumerationType> + + <attribute> + <description>CPU Attribute</description> + <id>CPU_ATTR</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint32_t/> + </simpleType> + </attribute> + + <attribute> + <id>CVPD_MAX_SECTIONS</id> + <description>Max CVPD sections </description> + <simpleType> + <uint32_t> + <default>32</default> + </uint32_t> + </simpleType> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <no_export/> </attribute> <attribute> - <description>Chip which contains the FSI master logic that drives this slave when booting from the alternate master processor</description> - <id>ALTFSI_MASTER_CHIP</id> - <nativeType> - <default>physical:sys-0</default> - <name>EntityPath</name> - </nativeType> + <id>CVPD_SIZE</id> + <description>Size of CDIMM/ISDIMM + This is the size of the centaur vpd or memory buffer vpd. + It varies based on the type of the DIMM. For ISDIMMs, + the size will be 8KB and for CDIMM, it will be 4KB. + </description> + <simpleType> + <uint64_t> + <default>0x2000</default> + </uint64_t> + </simpleType> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <no_export/> </attribute> <attribute> - <description>Type of Master FSI connection to this slave (MFSI or cMFSI)</description> - <hasStringConversion></hasStringConversion> - <id>FSI_MASTER_TYPE</id> + <description>L1 Data Cache Line Size in bytes</description> + <id>DATA_CACHE_LINE_SIZE</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <enumeration> - <default>NO_MASTER</default> - <id>FSI_MASTER_TYPE</id> - </enumeration> + <uint32_t/> </simpleType> - <no_export/> </attribute> <attribute> - <description>Which port is this chip hanging off of when booting from the default master processor</description> - <id>FSI_MASTER_PORT</id> + <description>L1 Data Cache Size in KB</description> + <id>DATA_CACHE_SIZE</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t> - <default>0xFF</default> - </uint8_t> + <uint32_t/> </simpleType> - <no_export/> </attribute> <attribute> - <description>Which port is this chip hanging off of when booting from the alternate master processor</description> - <id>ALTFSI_MASTER_PORT</id> + <description>DCache Associative Sets</description> + <id>DCACHE_ASSOC_SETS</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t> - <default>0xFF</default> - </uint8_t> + <uint32_t/> </simpleType> - <no_export/> </attribute> <attribute> - <description>Slave cascade position</description> - <id>FSI_SLAVE_CASCADE</id> + <description>DCache Line Size in bytes</description> + <id>DCACHE_LINE_SIZE</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint32_t/> + </simpleType> + </attribute> + + <attribute> + <description>If the Target is directly deconfigurable and GARDable; target + may still be deconfigured in 'by association' processing.</description> + <id>DECONFIG_GARDABLE</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <uint8_t> <default>0</default> @@ -358,244 +750,129 @@ </attribute> <attribute> - <complexType> - <description>FSI flags</description> - <field> - <bits>1</bits> - <default>0</default> - <description> - Set on FSI master chips (procs) if that chip uses slaveB - to attach to the acting master chip. - </description> - <name>flipPort</name> - <type>uint16_t</type> - </field> - <field> - <bits>15</bits> - <default>0</default> - <description>Reserved for future expansion</description> - <name>reserved</name> - <type>uint16_t</type> - </field> - </complexType> <description> - Reserved for any special flags we might need to access FSI + Used to tell I2C code whether to run + I2C Engine 2 Port 0 in diag mode or not + 0 = Use Diag Mode + 1 = Disable Diag Mode </description> - <id>FSI_OPTION_FLAGS</id> + <id>DISABLE_I2C_ENGINE2_PORT0_DIAG_MODE</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + <simpleType> + <uint8_t> + <default>1</default> + </uint8_t> + </simpleType> </attribute> <attribute> - <complexType> - <description>struct - 4 booleans and a PLID</description> - <field> - <default>0</default> - <description>if this target was deconfigured, - this will be a special DECONFIGURED_BY_ enum, - OR it will be the errlog EID that caused it, - either directly or by association, - </description> - <name>deconfiguredByEid</name> - <type>uint32_t</type> - </field> - <field> - <bits>1</bits> - <default>0</default> - <description> - 0b0: Target is not powered on (is off); - 0b1: Target is powered on; - </description> - <name>poweredOn</name> - <type>uint8_t</type> - </field> - <field> - <bits>1</bits> - <default>0</default> - <description> - 0b0: Target is not present in the system; - 0b1: Target is present in the system - </description> - <name>present</name> - <type>uint8_t</type> - </field> - <field> - <bits>1</bits> - <default>0</default> - <description> - 0b0: Target is not functional; - 0b1: Target is functional - </description> - <name>functional</name> - <type>uint8_t</type> - </field> - <field> - <bits>1</bits> - <default>0</default> - <description>FSP Only, used by DUMP applet; - 0b0: target is dump capabile; - 0b1: target is not dump capabile; - </description> - <name>dumpfunctional</name> - <type>uint8_t</type> - </field> - <field> - <bits>1</bits> - <default>0</default> - <description>Set for speculative deconfig; - 0b0: target not speculative deconfig; - 0b1: target is speculatively deconfigured; - </description> - <name>specdeconfig</name> - <type>uint8_t</type> - </field> - </complexType> - <description>HardWare Availability Service State Attribute. - Keeps track of Target values poweredOn, present, functional</description> - <id>HWAS_STATE</id> - <persistency>volatile</persistency> - <readable></readable> - <writeable></writeable> + <description> + Indicates if system should consider abus logic when deconfiguring in + _deconfigureAssocProc(), will be overwritten on multi-node system + </description> + <id>DO_ABUS_DECONFIG</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint8_t> + <default>1</default> + </uint8_t> + </simpleType> </attribute> <attribute> - <description>HardWare Availability Service State Changed Attribute. - Keeps track of changedSinceChecked state, indicates if the - target has changed since last checked by the appropriate service. - This is a bit field of flags (see HWAS_CHANGED_BIT enumeration - that follows). - </description> - <id>HWAS_STATE_CHANGED_FLAG</id> + <description> + Defines a negative percentage value that is applied to + the ATTR_NOMINAL_FREQ_MHZ determined from MVPD #V. It + is used to explicitly raise the value of MIN_FREQ_MHZ above + what is specified by MVPD #V data. On FSP systems this + is sourced from the power_management def file. + Value must be between 0 and -100. + A value of zero indicates no override. + </description> + <id>DPO_MIN_FREQ_PERCENT</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + <range> + <min>-100</min> + <max>0</max> + </range> <simpleType> - <uint64_t> - <default>0x0</default> - </uint64_t> + <int32_t> + <default>0</default> + </int32_t> </simpleType> - <writeable></writeable> + <writeable/> </attribute> <attribute> - <description>HardWare Availability Service State Changed Mask. - Used when a target changes (ie, via HCDB change) to set the - HWAS_STATE_CHANGED_FLAG, so that the appropriate services will - all handle the change. - This is a bit field of flags (see HWAS_CHANGED_BIT enumeration - that follows). - </description> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <persistency>non-volatile</persistency> - <readable></readable> + <description>Dummy attribute on the heap with zero initialization</description> + <id>DUMMY_HEAP_ZERO_DEFAULT</id> + <persistency>volatile-zeroed</persistency> + <readable/> <simpleType> - <uint64_t> - <default>0x0</default> - </uint64_t> + <uint8_t/> </simpleType> - <no_export/> </attribute> <attribute> - <description>Block speculative deconfig in reconfig loop. - Flags when speculative deconfigurations should not be done for - predictive gard records on a reconfig loop IPL due to out of - hardware condition on prior IPL. - 0 = Allow speculative deconfiguration - 1 = Block speculative deconfiguration - </description> - <id>BLOCK_SPEC_DECONFIG</id> + <description>Dummy attribute with read-only permissions</description> + <id>DUMMY_RO</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <uint8_t> - <default>0x0</default> + <default>0</default> </uint8_t> </simpleType> - <writeable></writeable> </attribute> <attribute> - <complexType> - <description>Numeric POD type test structure</description> - <field> - <default>physical:sys-0</default> - <description>Entity path for testing purposes</description> - <name>fsiPath</name> - <type>EntityPath</type> - </field> - <field> - <default>CHIP</default> - <description>Class for testing purposes</description> - <name>className</name> - <type>CLASS</type> - </field> - <field> - <default>0xAB</default> - <description>Test uint8</description> - <name>uint8</name> - <type>uint8_t</type> - </field> - <field> - <default>0xABCD</default> - <description>Test uint16</description> - <name>uint16</name> - <type>uint16_t</type> - </field> - <field> - <default>0xABCDEF01</default> - <description>Test uint32</description> - <name>uint32</name> - <type>uint32_t</type> - </field> - <field> - <default>0xABCDEF0123456789</default> - <description>Test uint64</description> - <name>uint64</name> - <type>uint64_t</type> - </field> - <field> - <default>-124</default> - <description>Test int8</description> - <name>int8</name> - <type>int8_t</type> - </field> - <field> - <default>-32764</default> - <description>Test int16</description> - <name>int16</name> - <type>int16_t</type> - </field> - <field> - <default>-2147483644</default> - <description>Test int32</description> - <name>int32</name> - <type>int32_t</type> - </field> - <field> - <default>-9223372036854775804</default> - <description>Test int64</description> - <name>int64</name> - <type>int64_t</type> - </field> - </complexType> - <description>Attribute which tests numeric POD types</description> - <id>NUMERIC_POD_TYPE_TEST</id> + <description>Dummy attribute with read/write permissions</description> + <id>DUMMY_RW</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + <simpleType> + <array>1,3,5</array> + <uint8_t> + <default>5</default> + </uint8_t> + </simpleType> + <writeable/> + <ignoreEkb/> + <hwpfToHbAttrMap> + <id>ATTR_DUMMY_SCRATCH_PLAT_INIT_UINT8</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> - <description>If the Target is directly deconfigurable and GARDable; target - may still be deconfigured in 'by association' processing.</description> - <id>DECONFIG_GARDABLE</id> + <description>Dummy attribute with write-only permissions</description> + <id>DUMMY_WO</id> <persistency>non-volatile</persistency> - <readable></readable> <simpleType> <uint8_t> <default>0</default> </uint8_t> </simpleType> - <no_export/> + <writeable/> + </attribute> + + <attribute> + <id>EC</id> + <description>attribute indicating the chip target's EC level</description> + <simpleType> + <uint8_t/> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <ignoreEkb/> + <hwpfToHbAttrMap> + <id>ATTR_EC</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> @@ -632,27 +909,20 @@ </field> <field> <default>0x02</default> - <description> - The number of bytes a device requires to set its - internal address/offset. DDR4 DIMMs require a special EEPROM - page switching mechanic denoted here by a value of 1 - 0 = Zero Byte Addressing - 1 = One Byte Addressing with page select - 2 = Two Byte Addressing - 3 = OneByte Addressing with no page select - </description> + <description>The number of bytes a device requires to set its + internal address/offset.</description> <name>byteAddrOffset</name> <type>uint8_t</type> </field> <field> - <default>0x0</default> + <default>0x100</default> <description>The number of kilobytes a device can hold. 'Zero' value possible for some devices.</description> <name>maxMemorySizeKB</name> <type>uint64_t</type> </field> <field> - <default>0x01</default> + <default>0x04</default> <description>The number of chips making up an eeprom device. </description> <name>chipCount</name> @@ -667,7 +937,7 @@ <type>uint64_t</type> </field> <field> - <default>0xA</default> + <default>0x0</default> <description>The amount of time in milliseconds a device requires on the completion of a write command to update its internal memory.</description> @@ -675,10 +945,10 @@ <type>uint64_t</type> </field> </complexType> - <description>Information needed to address the EEPROM slaves</description> - <id>EEPROM_VPD_PRIMARY_INFO</id> + <description>Information needed to address the EERPROM slaves</description> + <id>EEPROM_SBE_BACKUP_INFO</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> </attribute> <attribute> @@ -721,14 +991,14 @@ <type>uint8_t</type> </field> <field> - <default>0x0</default> + <default>0x100</default> <description>The number of kilobytes a device can hold. 'Zero' value possible for some devices.</description> <name>maxMemorySizeKB</name> <type>uint64_t</type> </field> <field> - <default>0x01</default> + <default>0x04</default> <description>The number of chips making up an eeprom device. </description> <name>chipCount</name> @@ -743,7 +1013,7 @@ <type>uint64_t</type> </field> <field> - <default>0xA</default> + <default>0x0</default> <description>The amount of time in milliseconds a device requires on the completion of a write command to update its internal memory.</description> @@ -752,9 +1022,9 @@ </field> </complexType> <description>Information needed to address the EERPROM slaves</description> - <id>EEPROM_VPD_BACKUP_INFO</id> + <id>EEPROM_SBE_PRIMARY_INFO</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> </attribute> <attribute> @@ -797,14 +1067,14 @@ <type>uint8_t</type> </field> <field> - <default>0x100</default> + <default>0x0</default> <description>The number of kilobytes a device can hold. 'Zero' value possible for some devices.</description> <name>maxMemorySizeKB</name> <type>uint64_t</type> </field> <field> - <default>0x04</default> + <default>0x01</default> <description>The number of chips making up an eeprom device. </description> <name>chipCount</name> @@ -819,7 +1089,7 @@ <type>uint64_t</type> </field> <field> - <default>0x0</default> + <default>0xA</default> <description>The amount of time in milliseconds a device requires on the completion of a write command to update its internal memory.</description> @@ -828,9 +1098,9 @@ </field> </complexType> <description>Information needed to address the EERPROM slaves</description> - <id>EEPROM_SBE_PRIMARY_INFO</id> + <id>EEPROM_VPD_BACKUP_INFO</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> </attribute> <attribute> @@ -867,20 +1137,27 @@ </field> <field> <default>0x02</default> - <description>The number of bytes a device requires to set its - internal address/offset.</description> + <description> + The number of bytes a device requires to set its + internal address/offset. DDR4 DIMMs require a special EEPROM + page switching mechanic denoted here by a value of 1 + 0 = Zero Byte Addressing + 1 = One Byte Addressing with page select + 2 = Two Byte Addressing + 3 = OneByte Addressing with no page select + </description> <name>byteAddrOffset</name> <type>uint8_t</type> </field> <field> - <default>0x100</default> + <default>0x0</default> <description>The number of kilobytes a device can hold. 'Zero' value possible for some devices.</description> <name>maxMemorySizeKB</name> <type>uint64_t</type> </field> <field> - <default>0x04</default> + <default>0x01</default> <description>The number of chips making up an eeprom device. </description> <name>chipCount</name> @@ -895,7 +1172,7 @@ <type>uint64_t</type> </field> <field> - <default>0x0</default> + <default>0xA</default> <description>The amount of time in milliseconds a device requires on the completion of a write command to update its internal memory.</description> @@ -903,204 +1180,119 @@ <type>uint64_t</type> </field> </complexType> - <description>Information needed to address the EERPROM slaves</description> - <id>EEPROM_SBE_BACKUP_INFO</id> + <description>Information needed to address the EEPROM slaves</description> + <id>EEPROM_VPD_PRIMARY_INFO</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> </attribute> <attribute> - <complexType> - <description>Structure to define the addressing for an I2C - slave device.</description> - <field> - <default>physical:sys-0</default> - <description>Entity path to the chip that contains the I2C - master</description> - <name>i2cMasterPath</name> - <type>EntityPath</type> - </field> - <field> - <default>0x80</default> - <description>I2C master engine. This is a 2-bit - value.</description> - <name>engine</name> - <type>uint8_t</type> - </field> - <field> - <default>0x80</default> - <description>Port from the I2C Master device. This is a 6-bit - value.</description> - <name>port</name> - <type>uint8_t</type> - </field> - <field> - <default>0x80</default> - <description>Device address on the I2C bus. This is a 7-bit value, - but then shifted 1 bit left.</description> - <name>devAddr</name> - <type>uint8_t</type> - </field> - </complexType> - <description>Information needed to address an I2C slave device</description> - <id>TEMP_SENSOR_I2C_CONFIG</id> + <description> + Holds the effective EC of the system. Effective EC is the lowest EC + among all the functional procs in the system. Some cards may "downbin" + the effective ECs of their contained processors, which could lower the + effective EC of the system beyond what would occur when considering + processor ECs alone + </description> + <id>EFFECTIVE_EC</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + <simpleType> + <uint8_t> + <default>0x10</default> + </uint8_t> + </simpleType> + <writeable/> </attribute> <attribute> - <complexType> - <description>Structure to define the addressing for an I2C - TPM.</description> - <field> - <default>0x0</default> - <description>Boolean indicating whether this TPM is available - in the system</description> - <name>tpmEnabled</name> - <type>uint8_t</type> - </field> - <field> - <default>physical:sys-0</default> - <description>Entity path to the chip that contains the I2C - master</description> - <name>i2cMasterPath</name> - <type>EntityPath</type> - </field> - <field> - <default>0x01</default> - <description>Port from the I2C Master device. This is a 6-bit - value.</description> - <name>port</name> - <type>uint8_t</type> - </field> - <field> - <default>0xAE</default> - <description>Device address on the I2C bus for Locality 0. - This is a 7-bit value, but then shifted 1 - bit left.</description> - <name>devAddrLocality0</name> - <type>uint8_t</type> - </field> - <field> - <default>0xA8</default> - <description>Device address on the I2C bus for Locality 1. - This is a 7-bit value, but then shifted 1 - bit left.</description> - <name>devAddrLocality1</name> - <type>uint8_t</type> - </field> - <field> - <default>0xAA</default> - <description>Device address on the I2C bus for Locality 2. - This is a 7-bit value, but then shifted 1 - bit left.</description> - <name>devAddrLocality2</name> - <type>uint8_t</type> - </field> - <field> - <default>0xA4</default> - <description>Device address on the I2C bus for Locality 3. - This is a 7-bit value, but then shifted 1 - bit left.</description> - <name>devAddrLocality3</name> - <type>uint8_t</type> - </field> - <field> - <default>0xA6</default> - <description>Device address on the I2C bus for Locality 4. - This is a 7-bit value, but then shifted 1 - bit left.</description> - <name>devAddrLocality4</name> - <type>uint8_t</type> - </field> - <field> - <default>0x00</default> - <description>I2C master engine. This is a 2-bit - value.</description> - <name>engine</name> - <type>uint8_t</type> - </field> - <field> - <default>0x01</default> - <description>The number of bytes a device requires to set its - internal address/offset.</description> - <name>byteAddrOffset</name> - <type>uint8_t</type> - </field> - </complexType> - <description>Information needed to address the TPM slaves</description> - <id>TPM_INFO</id> - <persistency>non-volatile</persistency> - <readable></readable> + <!-- @fixme --> + <id>EFF_DRAM_COLS</id> + <description>Number of DRAM columns. Initialized and used by HWPs.</description> + <simpleType> + <uint8_t/> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> </attribute> <attribute> - <id>TPM_UNUSABLE</id> - <description> - Indicates whether the TPM is unusable. Hostboot should not read this - value for any purpose other than tracing. This value should only be - written to when there is a certainty that the TPM is not usable. - This attribute is consumed by FSP during alignment check to determine - the optimal boot configuration. This attribute can be removed if TPM - gard is ever supported. - </description> - <range> - <min>0</min> - <max>1</max> - </range> + <!-- @fixme --> + <id>EFF_DRAM_ROWS</id> + <description>Number of DRAM rows. Initialized and used by HWPs.</description> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint8_t/> </simpleType> - <persistency>non-volatile</persistency> - <readable></readable> - <writeable></writeable> - <no_export/> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> </attribute> <attribute> <description> - Indicates the chip's EC level, distinct from ATTR_EC to handle - non-standard mini-ECs, e.g. 1.01, separate from the real - hardware-defined EC level. By default, ATTR_HDAT_EC==ATTR_EC - unless the chip has a mini-EC. + Bitmask of threads to enable for each processor, + Zero means enable all architected threads </description> - <id>HDAT_EC</id> + <id>ENABLED_THREADS</id> <persistency>volatile-zeroed</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t></uint8_t> + <uint64_t/> </simpleType> - <writeable></writeable> + <writeable/> </attribute> <attribute> - <description>A unit (chiplet) 's offset number within the chip. </description> - <hwpfToHbAttrMap> - <id>ATTR_CHIP_UNIT_POS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <id>CHIP_UNIT</id> + <description>Attribute indicating the target's engine type</description> + <hasStringConversion/> + <id>ENGINE_TYPE</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <enumeration> + <id>ENGINE_TYPE</id> + </enumeration> </simpleType> </attribute> + <enumerationType> + <default>NA</default> + <description>Enumeration indicating the target's engine type</description> + <enumerator> + <name>NA</name> + <value>0</value> + </enumerator> + <enumerator> + <name>ENGINE_IIC</name> + <value>1</value> + </enumerator> + <enumerator> + <name>ENGINE_SCOM</name> + <value>2</value> + </enumerator> + <id>ENGINE_TYPE</id> + </enumerationType> + <attribute> - <description>Position of target relative to node</description> - <id>POSITION</id> + <description> + Chip attribute. + Logical fabric chip id for this chip (position within the fabric). + Provided by the Machine Readable Workbook. + Can vary across drawers. + </description> + <id>FABRIC_CHIP_ID</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint16_t> + <uint8_t> <default>0</default> - </uint16_t> + </uint8_t> </simpleType> + <hwpfToHbAttrMap> + <id>ATTR_PROC_FABRIC_CHIP_ID</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> @@ -1110,189 +1302,445 @@ Provided by the Machine Readable Workbook. Can vary across drawers. </description> + <id>FABRIC_GROUP_ID</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> <hwpfToHbAttrMap> <id>ATTR_PROC_FABRIC_GROUP_ID</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <id>FABRIC_GROUP_ID</id> - <persistency>non-volatile</persistency> - <readable></readable> + </attribute> + + <attribute> + <description> + Correlate HDAT node number (physical) to the logical node + (based on the PIR) that contains the host boot image. + </description> + <id>FABRIC_TO_PHYSICAL_NODE_MAP</id> + <persistency>volatile</persistency> + <readable/> <simpleType> + <array>8</array> <uint8_t> + <default>0,255,255,255,255,255,255,255</default> + </uint8_t> + </simpleType> + <writeable/> + </attribute> + + <attribute> + <description>Common name across FAPI environments + chip target -> pu:k0:n0:s0:p00 + DIMM target -> dimm:k0:n0:s0:p00 + chip unit target -> pu.core:k0:n0:s0:p00:c0 + cage/system target -> k0 + + (chip type).(unit type):k(cage,always zero for us):n(node/drawer) + :s(slot,always zero for us):p(chip position):c(core/unit position) + pu = generic processor + </description> + <id>FAPI_NAME</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <string> + <default>unknown</default> + <sizeInclNull>64</sizeInclNull> + </string> + </simpleType> + <no_export/> + </attribute> + + <enumerationType> + <default>NA</default> + <description>Enumeration defining special FAPI_POS values</description> + <enumerator> + <name>NA</name> + <value>0xFFFFFFFF</value> + </enumerator> + <id>FAPI_POS</id> + </enumerationType> + + <attribute> + <description>Field Core Override (FCO) is the override value for the + number of functional cores allowed on the system. + FCO is used when customers order a system with N cores but they only want + to enable less than N cores to lower software license costs. A field in the + anchor VPD is set by manufacturing to specify the maximum number of cores + to enable. The number is maintained, even if some cores are garded out due + to error. + A value of 0 means all cores allowed; + </description> + <id>FIELD_CORE_OVERRIDE</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint32_t> <default>0</default> + </uint32_t> + </simpleType> + <writeable/> + </attribute> + + <attribute> + <description> + This attribute represents the Maximum number of L2 Column Repairs allowed + in the Field. + creator: platform (generated based on MRW data) + </description> + <id>FIELD_TH_P8EX_L2_COL_REPAIRS</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint8_t> + <default>7</default> </uint8_t> </simpleType> </attribute> <attribute> <description> - Chip attribute. - Logical fabric chip id for this chip (position within the fabric). - Provided by the Machine Readable Workbook. - Can vary across drawers. + This attribute represents the Maximum number of L2 Line Deletes allowed + in the Field. + creator: platform (generated based on MRW data) </description> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_CHIP_ID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <id>FABRIC_CHIP_ID</id> + <id>FIELD_TH_P8EX_L2_LINE_DELETES</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <uint8_t> - <default>0</default> + <default>6</default> </uint8_t> </simpleType> </attribute> <attribute> <description> - System attribute. - The lowest frequency that a core can be set to in MHz. - This is the same for all cores in the system. - Data is provided by MVPD #V and is calculated as the - Maximum of the power save frequencies. + This attribute represents the Maximum number of L3 Column Repairs allowed + in the Field. + creator: platform (generated based on MRW data) + </description> + <id>FIELD_TH_P8EX_L3_COL_REPAIRS</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint8_t> + <default>7</default> + </uint8_t> + </simpleType> + </attribute> + + <attribute> + <description> + This attribute represents the Maximum number of L3 Line Deletes allowed + in the Field. + creator: platform (generated based on MRW data) </description> + <id>FIELD_TH_P8EX_L3_LINE_DELETES</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint8_t> + <default>6</default> + </uint8_t> + </simpleType> + </attribute> + + <attribute> + <id>FREQ_CORE_CEILING_MHZ</id> + <description> + The maximum core frequency in MHz. + This is the same for all cores in the system. + Data is provided by MVPD #V and is calculated as + the minimum of the turbo frequencies. + </description> + <simpleType> + <uint32_t/> + </simpleType> + <persistency>volatile</persistency> + <readable/> + <writeable/> + <ignoreEkb/> <hwpfToHbAttrMap> - <id>ATTR_FREQ_CORE_FLOOR_MHZ</id> + <id>ATTR_FREQ_CORE_CEILING_MHZ</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <id>MIN_FREQ_MHZ</id> - <persistency>volatile</persistency> - <readable></readable> + </attribute> + + <attribute> + <id>FREQ_CORE_MAX</id> + <description> + SYSTEM Attribute + Maximum frequency (binary in MHz) that any processor in the system will + run. Used to define the top end of the PState range in the frequency space. + From this, the ATTR_PROCPM_PSTATE0_FREQUENCY is computed using + ATTR_SYSTEM_REFCLK_FREQUENCY to determine the step size. + + Consumers: proc_build_gpstate_table.C (among others) + + Data is is provided by MVPD #V and is calculated as the minimum + of the turbo frequencies + </description> <simpleType> - <uint32_t> - <default>4800</default> - </uint32_t> + <uint32_t/> </simpleType> - <writeable></writeable> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> </attribute> <attribute> + <id>FREQ_PROC_REFCLOCK</id> <description> - Defines a negative percentage value that is applied to - the ATTR_NOMINAL_FREQ_MHZ determined from MVPD #V. It - is used to explicitly raise the value of MIN_FREQ_MHZ above - what is specified by MVPD #V data. On FSP systems this - is sourced from the power_management def file. - Value must be between 0 and -100. - A value of zero indicates no override. + System attribute. + The frequency of the processor refclock in MHz. + Provided by the MRW. </description> - <id>DPO_MIN_FREQ_PERCENT</id> + <simpleType> + <uint32_t/> + </simpleType> <persistency>non-volatile</persistency> - <readable></readable> - <range> - <min>-100</min> - <max>0</max> - </range> + <readable/> + </attribute> + + <attribute> + <description>FRU ID attribute used to report FRU information to the BMC + for each fru in the system.</description> + <global/> + <id>FRU_ID</id> + <persistency>non-volatile</persistency> + <readable/> <simpleType> - <int32_t> + <uint32_t> <default>0</default> - </int32_t> + </uint32_t> </simpleType> - <writeable></writeable> </attribute> <attribute> - <description> - Hardware Unit ID - SSSSNNNNTTTTTTTTiiiiiiiiiiiiiiii - S=System - N=Node Number - T=Target Type (matches TYPE attribute) - i=Instance/Sequence number of target, relative to node - </description> - <id>HUID</id> + <description>Chip which contains the FSI master logic that drives this slave when booting from the default master processor</description> + <id>FSI_MASTER_CHIP</id> + <nativeType> + <default>physical:sys-0</default> + <name>EntityPath</name> + </nativeType> + <persistency>non-volatile</persistency> + <readable/> + <no_export/> + </attribute> + + <attribute> + <description>Which port is this chip hanging off of when booting from the default master processor</description> + <id>FSI_MASTER_PORT</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <default>0xFFFFFFFF</default> - <uint32_t></uint32_t> + <uint8_t> + <default>0xFF</default> + </uint8_t> </simpleType> <no_export/> </attribute> <attribute> - <complexType> - <description>Structure which defines a system's SP functions. - Applicable for System target only. Structure is read-only. - </description> - <field> - <bits>1</bits> - <default>1</default> - <description> - If this flag is set then mailboxEnabled MUST also be set + <description>Type of Master FSI connection to this slave (MFSI or cMFSI)</description> + <hasStringConversion/> + <id>FSI_MASTER_TYPE</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <enumeration> + <default>NO_MASTER</default> + <id>FSI_MASTER_TYPE</id> + </enumeration> + </simpleType> + <no_export/> + </attribute> - 0b0: SP does not support for VPD, payload, ATTR sync, VDDR, TOD; - 0b1: SP supports VPD, payload, ATTR sync, VDDR, TOD - </description> - <name>baseServices</name> - <type>uint32_t</type> - </field> - <field> - <bits>1</bits> - <default>1</default> - <description> - 0b0: SP does not initialize FSI slave logic, Hostboot must; - 0b1: SP does initialize FSI slave logic so Hostboot should not - </description> - <name>fsiSlaveInit</name> - <type>uint32_t</type> - </field> + <enumerationType> + <default>NO_MASTER</default> + <description>Enumeration indicating the master's FSI type</description> + <enumerator> + <name>MFSI</name> + <value>0</value> + </enumerator> + <enumerator> + <name>CMFSI</name> + <value>1</value> + </enumerator> + <enumerator> + <name>NO_MASTER</name> + <value>2</value> + </enumerator> + <id>FSI_MASTER_TYPE</id> + </enumerationType> + + <attribute> + <complexType> + <description>FSI flags</description> <field> <bits>1</bits> <default>0</default> <description> - 0b0: There is no SP mailbox support; - 0b1: There is SP mailbox support - </description> - <name>mailboxEnabled</name> - <type>uint32_t</type> - </field> - <field> - <bits>1</bits> - <default>1</default> - <description> - 0b0: SP does not initialize FSI master logic, Hostboot must; - 0b1: SP does initialize FSI master logic so Hostboot should not - </description> - <name>fsiMasterInit</name> - <type>uint32_t</type> - </field> - <field> - <bits>1</bits> - <default>1</default> - <description> - 0b0: SP does not perform hardware change detection, Hostboot must; - 0b1: SP does perform hardware change detection (HCDB) so Hostboot should not - </description> - <name>hardwareChangeDetection</name> - <type>uint32_t</type> - </field> - <field> - <bits>1</bits> - <default>1</default> - <description> - 0b0: SP does not perform Power Line Disturbance (PLD) detection, Hostboot must; - 0b1: SP does perform Power Line Disturbance (PLD) detection so Hostboot should not + Set on FSI master chips (procs) if that chip uses slaveB + to attach to the acting master chip. </description> - <name>powerLineDisturbance</name> - <type>uint32_t</type> + <name>flipPort</name> + <type>uint16_t</type> </field> <field> - <bits>26</bits> + <bits>15</bits> <default>0</default> - <description>Reserved for future use</description> + <description>Reserved for future expansion</description> <name>reserved</name> - <type>uint32_t</type> + <type>uint16_t</type> </field> </complexType> <description> - Attribute which describes what the SP is or is not doing in this system + Reserved for any special flags we might need to access FSI </description> - <id>SP_FUNCTIONS</id> + <id>FSI_OPTION_FLAGS</id> + <persistency>non-volatile</persistency> + <readable/> + </attribute> + + <attribute> + <description>Slave cascade position</description> + <id>FSI_SLAVE_CASCADE</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <no_export/> + </attribute> + + <attribute> + <description>Size of FSP IO Region</description> + <id>FSP_BAR_SIZE</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint64_t> + <default>0x0000000100000000</default> + </uint64_t> + </simpleType> + </attribute> + + <attribute> + <description>Base Address of FSP IO Region</description> + <id>FSP_BASE_ADDR</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + <simpleType> + <uint64_t> + <default>0x0003FFE000000000</default> + </uint64_t> + </simpleType> + <no_export/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_FSP_BAR_BASE_ADDR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> + </attribute> + + <enumerationType> + <id>FUSED_CORE_MODE_HB</id> + <description>Enum for FUSED_CORE_MODE_HB</description> + <enumerator> + <name>SMT4_DEFAULT</name> + <value>0</value> + </enumerator> + <enumerator> + <name>SMT4_ONLY</name> + <value>1</value> + </enumerator> + <enumerator> + <name>SMT8_ONLY</name> + <value>2</value> + </enumerator> + </enumerationType> + + <attribute> + <id>FUSED_CORE_MODE_HB</id> + <description> + Stores the SMT setting used to determine fused mode. + SMT4_DEFAULT: Nimbus_DD1, boot in SMT4 but can change to SMT8 + SMT4_ONLY: Nimbus_DD2/Cumulus, set based on PVR info + SMT8_ONLY: Nimbus_DD2/Cumulus, set based on PVR info + </description> + <simpleType> + <uint8_t/> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> + </attribute> + + <attribute> + <description> + If not loading PHYP or OPAL, then use this to + decide whether to use FUSED cores or NOT. + </description> + <id>FUSED_CORE_OPTION</id> + <persistency>volatile-zeroed</persistency> + <readable/> + <simpleType> + <uint8_t/> + </simpleType> + <writeable/> + </attribute> + + <enumerationType> + <description>Enum for FUSED_CORE_OPTION</description> + <enumerator> + <name>USING_DEFAULT_CORES</name> + <value>0</value> + </enumerator> + <enumerator> + <name>USING_NORMAL_CORES</name> + <value>1</value> + </enumerator> + <enumerator> + <name>USING_FUSED_CORES</name> + <value>2</value> + </enumerator> + <id>FUSED_CORE_OPTION</id> + </enumerationType> + + <attribute> + <description>Hostboot HRMOR = (HB_HRMOR_NODAL_BASE * node) + offset. </description> + <id>HB_HRMOR_NODAL_BASE</id> + <persistency>volatile</persistency> + <readable/> + <simpleType> + <uint64_t> + <default>0x200000000000</default> + </uint64_t> + </simpleType> + <writeable/> + </attribute> + + <attribute> + <description> + The amount of mainstore that PHYP needs to preserve per node + during MPIPL. + </description> + <id>HB_RSV_MEM_SIZE_MB</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint32_t> + <default>256</default> + </uint32_t> + </simpleType> </attribute> <attribute> @@ -1347,258 +1795,536 @@ </description> <id>HB_SETTINGS</id> <persistency>non-volatile</persistency> - <readable></readable> - <writeable></writeable> + <readable/> + <writeable/> </attribute> <attribute> - <complexType> - <description>Structure which defines a they IPL types - Applicable for System target only. - </description> - <field> - <bits>1</bits> - <default>0</default> - <description> - Perform mainstore dump collection. Only valid for MPIPL - 0b0: Do not collect mainstore dump - 0b1: Perform mainstore dump collection - </description> - <name>PostDump</name> - <type>uint8_t</type> - </field> - <field> - <bits>7</bits> - <default>0</default> - <description>Minor IPL Type</description> - <name>MinorIPLType</name> - <type>uint8_t</type> - </field> - </complexType> <description> - Attribute which describes optional IPL flavors + Indicates the chip's EC level, distinct from ATTR_EC to handle + non-standard mini-ECs, e.g. 1.01, separate from the real + hardware-defined EC level. By default, ATTR_HDAT_EC==ATTR_EC + unless the chip has a mini-EC. </description> - <id>CEC_IPL_TYPE</id> - <persistency>volatile</persistency> - <readable></readable> - <writeable></writeable> + <id>HDAT_EC</id> + <persistency>volatile-zeroed</persistency> + <readable/> + <simpleType> + <uint8_t/> + </simpleType> + <writeable/> </attribute> <attribute> - <description>Test attribute; string with empty default value</description> - <id>TEST_NULL_STRING</id> - <persistency>volatile</persistency> - <readable></readable> + <description> + Number of internal data pointers we have in + the hostboot runtime data section. + </description> + <id>HDAT_HBRT_NUM_SECTIONS</id> + <persistency>volatile-zeroed</persistency> + <readable/> <simpleType> - <string> - <default></default> - <sizeInclNull>10</sizeInclNull> - </string> + <uint32_t/> </simpleType> - <writeable></writeable> + <writeable/> </attribute> <attribute> - <description>Test attribute; smallest string possible given size</description> - <id>TEST_MIN_STRING</id> - <persistency>volatile</persistency> - <readable></readable> + <description> + Biggest size for any of the hostboot + runtime data sections. + </description> + <id>HDAT_HBRT_SECTION_SIZE</id> + <persistency>volatile-zeroed</persistency> + <readable/> <simpleType> - <string> - <default>a</default> - <sizeInclNull>10</sizeInclNull> - </string> + <array>9</array> + <uint64_t/> </simpleType> - <writeable></writeable> + <writeable/> </attribute> + <enumerationType> + <description>Pulled from the MRW, this describes the device + purpose to the HDAT. This is for I2C devices only. + </description> + <enumerator> + <name>CABLE_CARD_PRES</name> + <value>0x1</value> + </enumerator> + <enumerator> + <name>PCI_HOTPLUG_PGOOD</name> + <value>0x2</value> + </enumerator> + <enumerator> + <name>PCI_HOTPLUG_CONTROL</name> + <value>0x3</value> + </enumerator> + <enumerator> + <name>TPM</name> + <value>0x4</value> + </enumerator> + <enumerator> + <name>MODULE_VPD</name> + <value>0x5</value> + </enumerator> + <enumerator> + <name>DIMM_SPD</name> + <value>0x6</value> + </enumerator> + <enumerator> + <name>PROC_MODULE_VPD</name> + <value>0x7</value> + </enumerator> + <enumerator> + <name>SBE_SEEPROM</name> + <value>0x8</value> + </enumerator> + <enumerator> + <name>PLANAR_VPD</name> + <value>0x9</value> + </enumerator> + <enumerator> + <name>NVLINK_CABLE_TOPOLOGY_VERIFICATION</name> + <value>0xA</value> + </enumerator> + <enumerator> + <!-- deprecated --> + <name>NVLINK</name> + <value>0xB</value> + </enumerator> + <enumerator> + <name>NVLINK_CABLE_MICRO_RESET</name> + <value>0xB</value> + </enumerator> + <enumerator> + <name>I2C_ASSOC_WITH_NVLINK_CABLE</name> + <value>0xC</value> + </enumerator> + <enumerator> + <name>WINDOW_OPEN</name> + <value>0xD</value> + </enumerator> + <enumerator> + <name>PHYSICAL_PRESENCE</name> + <value>0xE</value> + </enumerator> + <enumerator> + <name>MEX_FPGA</name> + <value>0xF</value> + </enumerator> + <enumerator> + <name>UNKNOWN</name> + <value>0xFF</value> + </enumerator> + <id>HDAT_I2C_DEVICE_PURPOSE</id> + </enumerationType> + + <enumerationType> + <description>Pulled from the MRW, this describes the device + type to the HDAT. This is for I2C devices only. + </description> + <enumerator> + <name>9551</name> + <value>0x1</value> + </enumerator> + <enumerator> + <!-- deprecated --> + <name>955X</name> + <value>0x1</value> + </enumerator> + <enumerator> + <!-- deprecated --> + <name>SEEPROM</name> + <value>0x2</value> + </enumerator> + <enumerator> + <name>SEEPROM_Atmel28c128</name> + <value>0x2</value> + </enumerator> + <enumerator> + <name>NUVOTON_TPM</name> + <value>0x3</value> + </enumerator> + <enumerator> + <name>MEX_FPGA</name> + <value>0x4</value> + </enumerator> + <enumerator> + <name>UCX90XX</name> + <value>0x5</value> + </enumerator> + <enumerator> + <!-- deprecated --> + <name>NVLINK</name> + <value>0x6</value> + </enumerator> + <enumerator> + <name>9552</name> + <value>0x6</value> + </enumerator> + <enumerator> + <name>9553</name> + <value>0x7</value> + </enumerator> + <enumerator> + <name>9554</name> + <value>0x8</value> + </enumerator> + <enumerator> + <name>9555</name> + <value>0x9</value> + </enumerator> + <enumerator> + <name>SMP_or_OpenCAPI_Cable</name> + <value>0xA</value> + </enumerator> + <enumerator> + <name>SEEPROM_Atmel28c256</name> + <value>0xB</value> + </enumerator> + <enumerator> + <name>UNKNOWN</name> + <value>0xFF</value> + </enumerator> + <id>HDAT_I2C_DEVICE_TYPE</id> + </enumerationType> + <attribute> - <description>Test attribute; largest string possible given size</description> - <id>TEST_MAX_STRING</id> - <persistency>volatile</persistency> - <readable></readable> + <description> + Number of internal data pointers we have in + the hostboot reserved memory section. + </description> + <id>HDAT_RSV_MEM_NUM_SECTIONS</id> + <persistency>volatile-zeroed</persistency> + <readable/> <simpleType> - <string> - <default>abc</default> - <sizeInclNull>4</sizeInclNull> - </string> + <uint32_t/> </simpleType> - <writeable></writeable> + <writeable/> </attribute> <attribute> - <description>Test attribute; string with no default supplied</description> - <id>TEST_NO_DEFAULT_STRING</id> - <persistency>volatile</persistency> - <readable></readable> + <id>HDDW_ORDER</id> + <description>PCIe slot HDDW order definition</description> <simpleType> - <string> - <sizeInclNull>10</sizeInclNull> - </string> + <uint8_t/> </simpleType> - <writeable></writeable> + <persistency>non-volatile</persistency> + <readable/> + <no_export/> </attribute> <attribute> - <description>Common name across FAPI environments - chip target -> pu:k0:n0:s0:p00 - DIMM target -> dimm:k0:n0:s0:p00 - chip unit target -> pu.core:k0:n0:s0:p00:c0 - cage/system target -> k0 - - (chip type).(unit type):k(cage,always zero for us):n(node/drawer) - :s(slot,always zero for us):p(chip position):c(core/unit position) - pu = generic processor + <id>HOMER_PHYS_ADDR</id> + <description> + Physical address where HOMER image is placed in mainstore. </description> - <id>FAPI_NAME</id> - <persistency>non-volatile</persistency> - <readable></readable> <simpleType> - <string> - <default>unknown</default> - <sizeInclNull>64</sizeInclNull> - </string> + <uint64_t/> </simpleType> - <no_export/> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <ignoreEkb/> + <hwpfToHbAttrMap> + <id>ATTR_HOMER_PHYS_ADDR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> - <description>Record offset for this target's VPD</description> - <id>VPD_REC_NUM</id> + <description> + Value of the next PLID that host service should send + </description> + <id>HOSTSVC_PLID</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint16_t> - <default>0xFFFF</default> - </uint16_t> + <uint32_t> + <default>0x89000000</default> + </uint32_t> </simpleType> - <no_export/> + <writeable/> </attribute> <attribute> - <description>Peer target's address of a A/X-bus connection. - NULL means address 0 for no peer target. If a - target instance overrides the default with the - peer target's PHYS_PATH. The target compiler will - convert the valid PHYS_PATH string into the runtime - virtual address of the peer target instance. + <id>HOT_PLUG_POWER_CONTROLLER_INFO</id> + <description>Hot Plug Controller values for a specific processor. + Purpose: Holds information about the hot plug controllers so that a + Hardware procedure is able to turn them on and off. + Data Format: up to 8 Hot Plug Controllers x 7 variables of information + This data is at the processor level. + The needed information and their individual sizes are as follows: + (1) I2C Master processor engine (uint8_t) + (2) I2C Master processor port (uint8_t) + (3) Bus Speed (uint16_t value: 2 uint8_t values: MSB, LSB) + (4) Slave address (uint8_t) + (5) Device type (uint8_t: see SUPPORTED_HOT_PLUG enum) + (6) I2C Master processor node (uint8_t) + (7) I2C Master processor position (uint8_t) + Thus, the information will be 8 bytes. </description> - <id>PEER_TARGET</id> - <persistency>non-volatile</persistency> - <readable></readable> <simpleType> - <Target_t> - <default>NULL</default> - </Target_t> + <uint8_t> + <default>0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + </default> + </uint8_t> + <array>8,8</array> </simpleType> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> - <description>Base address (target HRMOR) of the payload. Value is in MB.</description> - <id>PAYLOAD_BASE</id> - <persistency>volatile</persistency> - <readable></readable> + <description> + Hardware Unit ID + SSSSNNNNTTTTTTTTiiiiiiiiiiiiiiii + S=System + N=Node Number + T=Target Type (matches TYPE attribute) + i=Instance/Sequence number of target, relative to node + </description> + <id>HUID</id> + <persistency>non-volatile</persistency> + <readable/> <simpleType> - <uint64_t> - <default>256</default> - </uint64_t> + <default>0xFFFFFFFF</default> + <uint32_t/> </simpleType> - <writeable></writeable> + <no_export/> </attribute> + <enumerationType> + <description>Enumeration indicating the services that are concerned + with target changes (ie, via HCDB change). + The values can be combined using a bitwise 'OR'. + </description> + <enumerator> + <name>GARD</name> + <value>0x00000001</value> + </enumerator> + <enumerator> + <name>MEMDIAG</name> + <value>0x00000002</value> + </enumerator> + <enumerator> + <name>PSIDIAG</name> + <value>0x00000004</value> + </enumerator> + <enumerator> + <name>DIAG_MASK</name> + <value>0x00000006</value> + </enumerator> + <enumerator> + <name>HOSTSVC_HBEL</name> + <value>0x00000008</value> + </enumerator> + <enumerator> + <name>RESRC_RECOV</name> + <value>0x00000010</value> + </enumerator> + <enumerator> + <name>GARD_APPLIED</name> + <value>0x00000020</value> + </enumerator> + <id>HWAS_CHANGED_BIT</id> + </enumerationType> + <attribute> - <description>The offset from base address of the payload entry-point. - Current default is 0x180</description> - <id>PAYLOAD_ENTRY</id> + <complexType> + <description>struct - 4 booleans and a PLID</description> + <field> + <default>0</default> + <description>if this target was deconfigured, + this will be a special DECONFIGURED_BY_ enum, + OR it will be the errlog EID that caused it, + either directly or by association, + </description> + <name>deconfiguredByEid</name> + <type>uint32_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description> + 0b0: Target is not powered on (is off); + 0b1: Target is powered on; + </description> + <name>poweredOn</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description> + 0b0: Target is not present in the system; + 0b1: Target is present in the system + </description> + <name>present</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description> + 0b0: Target is not functional; + 0b1: Target is functional + </description> + <name>functional</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description>FSP Only, used by DUMP applet; + 0b0: target is dump capabile; + 0b1: target is not dump capabile; + </description> + <name>dumpfunctional</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description>Set for speculative deconfig; + 0b0: target not speculative deconfig; + 0b1: target is speculatively deconfigured; + </description> + <name>specdeconfig</name> + <type>uint8_t</type> + </field> + </complexType> + <description>HardWare Availability Service State Attribute. + Keeps track of Target values poweredOn, present, functional</description> + <id>HWAS_STATE</id> <persistency>volatile</persistency> - <readable></readable> - <simpleType> - <uint64_t> - <default>0x180</default> - </uint64_t> - </simpleType> - <writeable></writeable> + <readable/> + <writeable/> </attribute> <attribute> - <description> - Attribute indicating what kind of payload is to be started. - </description> - <hasStringConversion></hasStringConversion> - <id>PAYLOAD_KIND</id> + <description>HardWare Availability Service State Changed Attribute. + Keeps track of changedSinceChecked state, indicates if the + target has changed since last checked by the appropriate service. + This is a bit field of flags (see HWAS_CHANGED_BIT enumeration + that follows). + </description> + <id>HWAS_STATE_CHANGED_FLAG</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <enumeration> - <id>PAYLOAD_KIND</id> - </enumeration> + <uint64_t> + <default>0x0</default> + </uint64_t> </simpleType> - <writeable></writeable> + <writeable/> </attribute> <attribute> - <description>Hostboot HRMOR = (HB_HRMOR_NODAL_BASE * node) + offset. </description> - <id>HB_HRMOR_NODAL_BASE</id> - <persistency>volatile</persistency> - <readable></readable> + <description>HardWare Availability Service State Changed Mask. + Used when a target changes (ie, via HCDB change) to set the + HWAS_STATE_CHANGED_FLAG, so that the appropriate services will + all handle the change. + This is a bit field of flags (see HWAS_CHANGED_BIT enumeration + that follows). + </description> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + <persistency>non-volatile</persistency> + <readable/> <simpleType> <uint64_t> - <default>0x200000000000</default> + <default>0x0</default> </uint64_t> </simpleType> - <writeable></writeable> + <no_export/> </attribute> <attribute> - <description> - Correlate HDAT node number (physical) to the logical node - (based on the PIR) that contains the host boot image. + <description>Designates the speed at which a given I2C bus should run. + Creator: MRW + Purpose: Used by FW to know the fastest possible bus speed that all of + the devices on a given bus are able to use. + Data Format: 4x13 array of uint16_t values. The first index indicates + the engine number of the bus. The second index indicates the port + number of the bus. The value in the array is the I2C bus speed + used for that engine/port combination in KHz. </description> - <id>FABRIC_TO_PHYSICAL_NODE_MAP</id> - <persistency>volatile</persistency> - <readable></readable> + <id>I2C_BUS_SPEED_ARRAY</id> + <persistency>non-volatile</persistency> + <readable/> <simpleType> - <array>8</array> - <uint8_t> - <default>0,255,255,255,255,255,255,255</default> - </uint8_t> + <array>4,13</array> + <uint16_t> + <default> + 0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0</default> + </uint16_t> </simpleType> - <writeable></writeable> </attribute> <attribute> - <description>XSCOM base address</description> - <id>XSCOM_BASE_ADDRESS</id> + <complexType> + <description>Structure which defines which I2C access method to use at + a point in time. Only applicable if target supports one or more I2C + types. Only one bit (of the first two) can ever be set at any one time. + </description> + <field> + <bits>1</bits> + <default>0</default> + <description>0b0: Do not use FSI I2C at this time. 0b1: Use FSI + I2C at this time</description> + <name>useFsiI2C</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description>0b0: Do not use Host I2C at this time. 0b1: Use + Host I2C at this time</description> + <name>useHostI2C</name> + <type>uint8_t</type> + </field> + <field> + <bits>6</bits> + <default>0</default> + <description>Reserved for future expansion</description> + <name>reserved</name> + <type>uint8_t</type> + </field> + </complexType> + <description>Attribute storing information about which I2C method to use</description> + <id>I2C_SWITCHES</id> <persistency>volatile</persistency> - <readable></readable> - <writeable></writeable> - <simpleType> - <uint64_t></uint64_t> - </simpleType> - <no_export/> + <readable/> + <writeable/> </attribute> <attribute> <description>MCS Inband Scom base address</description> - <hwpfToHbAttrMap> - <id>ATTR_MCS_INBAND_BASE_ADDRESS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> <id>IBSCOM_MCS_BASE_ADDR</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <uint64_t> <default>0x0003E00000000000</default> </uint64_t> </simpleType> + <hwpfToHbAttrMap> + <id>ATTR_MCS_INBAND_BASE_ADDRESS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> <description>PROC Inband Scom base address</description> <id>IBSCOM_PROC_BASE_ADDR</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <uint64_t> <default>0x0003E00000000000</default> @@ -1607,109 +2333,66 @@ </attribute> <attribute> - <description>Indicate that payload should be placed in mirrored memory. - Set by the FSP based on the value of the registry key indicating - the memory mirroring mode. - </description> - <id>PAYLOAD_IN_MIRROR_MEM</id> + <description>ICache Assoc Sets</description> + <id>ICACHE_ASSOC_SETS</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint32_t/> </simpleType> - <writeable></writeable> - <no_export/> </attribute> <attribute> - <description>NPU MMIO BAR base address values - creator: platform - consumer: proc_setup_bars - firmware notes: - 64-bit address representing BAR RA - NOTE: BAR register covers RA 14:51 - first dimension: unit number (0:3) - second dimension: BAR number (0:1) - </description> - <hwpfToHbAttrMap> - <id>ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <id>NPU_MMIO_BAR_BASE_ADDR</id> + <description>ICache Block Size in bytes</description> + <id>ICACHE_BLOCK_SIZE</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <array>4,2</array> - <uint64_t> - <default>0</default> - </uint64_t> + <uint32_t/> </simpleType> </attribute> <attribute> - <description>NPU MMIO BAR size values - creator: platform - consumer: proc_setup_bars - firmware notes: none - first dimension: unit number (0:3) - second dimension: BAR number (0:1) - </description> - <hwpfToHbAttrMap> - <id>ATTR_PROC_NPU_MMIO_BAR_SIZE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <id>NPU_MMIO_BAR_SIZE</id> + <description>Icache Line Size in bytes</description> + <id>ICACHE_LINE_SIZE</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <array>4,2</array> - <uint64_t> - <default>0</default> - </uint64_t> + <uint32_t/> </simpleType> </attribute> <attribute> - <description>Base Address of FSP IO Region</description> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FSP_BAR_BASE_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <id>FSP_BASE_ADDR</id> + <description>ICache Size in KB</description> + <id>ICACHE_SIZE</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint64_t> - <default>0x0003FFE000000000</default> - </uint64_t> + <uint32_t/> </simpleType> - <no_export/> </attribute> <attribute> - <description>Size of FSP IO Region</description> - <id>FSP_BAR_SIZE</id> + <description>Size of IMT IO Region + Set by FSP-based tooling + </description> + <id>IMT_BAR_SIZE</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <uint64_t> - <default>0x0000000100000000</default> + <default>0x0000000000000000</default> </uint64_t> </simpleType> </attribute> <attribute> - <description>Base Address of PSI Bridge Logic</description> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <id>PSI_BRIDGE_BASE_ADDR</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> - <writeable></writeable> + <description>Base Address of In-Memory Trace Region + Set by FSP-based tooling + </description> + <id>IMT_BASE_ADDR</id> + <persistency>non-volatile</persistency> + <readable/> <simpleType> <uint64_t> <default>0xFFFFFFFFFFFFFFFF</default> @@ -1721,8 +2404,8 @@ <description>Base Address of Interrupt Presenter</description> <id>INTP_BASE_ADDR</id> <persistency>volatile-zeroed</persistency> - <readable></readable> - <writeable></writeable> + <readable/> + <writeable/> <simpleType> <uint64_t> <default>0xFFFFFFFFFFFFFFFF</default> @@ -1731,1167 +2414,1570 @@ </attribute> <attribute> - <description>Base Address of PHB Register Space</description> - <id>PHB_BASE_ADDRS</id> - <persistency>non-volatile</persistency> - <readable></readable> + <id>ISTEP_MODE</id> + <description>If True, puts HostBoot into SPLess SingleStep mode.</description> <simpleType> - <array>4</array> - <uint64_t> - <default> - 0xFFFFFFFFFFFFFFFF, - 0xFFFFFFFFFFFFFFFF, - 0xFFFFFFFFFFFFFFFF, - 0xFFFFFFFFFFFFFFFF - </default> - </uint64_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> + <ignoreEkb/> + <hwpfToHbAttrMap> + <id>ATTR_ISTEP_MODE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> - <description>Base Address of PCI 64 bit Memory Space</description> - <id>PCI_BASE_ADDRS_64</id> - <persistency>non-volatile</persistency> - <readable></readable> + <description> + Used to configure the parameters for enabling pause/stop between + isteps. This attribute is set via attribute override. + </description> + <id>ISTEP_PAUSE_CONFIG</id> + <persistency>volatile-zeroed</persistency> + <readable/> <simpleType> - <array>4</array> - <uint64_t></uint64_t> + <uint64_t/> </simpleType> + <writeable/> </attribute> <attribute> - <description>Base Address of PCI 32 bit Memory Space</description> - <id>PCI_BASE_ADDRS_32</id> - <persistency>non-volatile</persistency> - <readable></readable> + <description> + Used to enable pause/stop in between isteps. This attribute is set via + attribute override. + </description> + <id>ISTEP_PAUSE_ENABLE</id> + <persistency>volatile-zeroed</persistency> + <readable/> <simpleType> - <array>4</array> - <uint64_t></uint64_t> + <uint8_t/> </simpleType> + <writeable/> </attribute> <attribute> - <description>Base Address for all mainstore behind this processor</description> - <hwpfToHbAttrMap> - <id>ATTR_PROC_MEM_BASE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <id>MEM_BASE</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> + <description>Indicate an inter-enclosure bus at this endpoint target. + 0 = No, 1 = Yes + </description> + <id>IS_INTER_ENCLOSURE_BUS</id> + <persistency>volatile</persistency> + <readable/> <simpleType> - <uint64_t></uint64_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <writeable></writeable> + <writeable/> </attribute> - + <enumerationType> + <id>KEY_TRANSITION_STATE</id> + <description> + Enum indicating the current Secure Boot key transition state for the + node. + </description> + <enumerator> + <description> + Secure Boot key transition not yet requested for the node + </description> + <name>KEY_TRANSITION_NOT_REQUESTED</name> + <value>0</value> + </enumerator> + <enumerator> + <description> + About to write new system Secure Boot key to first SBE SEEPROM + side in the node + </description> + <name>KEY_TRANSITION_STARTED</name> + <value>1</value> + </enumerator> + <enumerator> + <description> + Failed to apply new system Secure Boot key to one or more functional + SBE SEEPROM sides in the node + </description> + <name>KEY_TRANSITION_FAILED</name> + <value>2</value> + </enumerator> + <enumerator> + <description> + Successfully applied new system Secure Boot key to every functional + SBE SEEPROM side in the node + </description> + <name>KEY_TRANSITION_SUCCEEDED</name> + <value>3</value> + </enumerator> + </enumerationType> <attribute> - <id>CVPD_SIZE</id> - <description>Size of CDIMM/ISDIMM - This is the size of the centaur vpd or memory buffer vpd. - It varies based on the type of the DIMM. For ISDIMMs, - the size will be 8KB and for CDIMM, it will be 4KB. - </description> + <description> + Attribute indicating the status of the Secure Boot key transition for + the node + </description> + <hasStringConversion/> + <id>KEY_TRANSITION_STATE</id> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> <simpleType> - <uint64_t> - <default>0x2000</default> - </uint64_t> + <enumeration> + <id>KEY_TRANSITION_STATE</id> + <default>KEY_TRANSITION_NOT_REQUESTED</default> + </enumeration> </simpleType> + </attribute> + + <attribute> + <description>L2 Cache Assoc Sets</description> + <id>L2_CACHE_ASSOC_SETS</id> <persistency>non-volatile</persistency> <readable/> - <no_export/> -</attribute> - -<attribute> - <id>CVPD_MAX_SECTIONS</id> - <description>Max CVPD sections </description> <simpleType> - <uint32_t> - <default>32</default> - </uint32_t> + <uint32_t/> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> + </attribute> <attribute> - <description>Base Address of RNG IO Region</description> - <hwpfToHbAttrMap> - <id>ATTR_PROC_NX_MMIO_BAR_BASE_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <id>RNG_BASE_ADDR</id> + <description>L2 Cache Line Size in bytes</description> + <id>L2_CACHE_LINE_SIZE</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint64_t> - <default>0xFFFFFFFFFFFFFFFF</default> - </uint64_t> + <uint32_t/> </simpleType> </attribute> <attribute> - <description>Size of RNG IO Region</description> - <id>RNG_BAR_SIZE</id> + <description>L2 Cache Size in KB</description> + <id>L2_CACHE_SIZE</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint64_t> - <default>0x000000000001000</default> - </uint64_t> + <uint32_t/> </simpleType> </attribute> <attribute> - <description>Base Address of In-Memory Trace Region - Set by FSP-based tooling - </description> - <id>IMT_BASE_ADDR</id> + <description>L3 Cache Line Size in bytes</description> + <id>L3_CACHE_LINE_SIZE</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint64_t> - <default>0xFFFFFFFFFFFFFFFF</default> - </uint64_t> + <uint32_t/> </simpleType> </attribute> <attribute> - <description>Size of IMT IO Region - Set by FSP-based tooling - </description> - <id>IMT_BAR_SIZE</id> + <description>L3 Cache Size in KB</description> + <id>L3_CACHE_SIZE</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint64_t> - <default>0x0000000000000000</default> - </uint64_t> + <uint32_t/> </simpleType> </attribute> <attribute> - <description> - The nominal core frequency in MHz. - This is the same for all cores in the system. - Data is provided by MVPD #V. - </description> - <hwpfToHbAttrMap> - <id>ATTR_FREQ_CORE_NOMINAL_MHZ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <id>NOMINAL_FREQ_MHZ</id> - <persistency>volatile</persistency> - <readable></readable> + <description>Location code of the Fru target</description> + <id>LOCATION_CODE</id> <simpleType> - <uint32_t></uint32_t> + <string> + <sizeInclNull>64</sizeInclNull> + </string> </simpleType> - <writeable></writeable> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> - <description> - The ultra turbo frequency in MHz. - This is the same for all cores in the system. - Data is provided by MVPD #V and is calculated as - the minimum of the ultra turbo frequencies. - </description> - <hwpfToHbAttrMap> - <id>ATTR_ULTRA_TURBO_NOMINAL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <id>ULTRA_TURBO_FREQ_MHZ</id> + <description>LPC Bus address - MMIO consumed by PHYP</description> + <id>LPC_BUS_ADDR</id> <persistency>volatile</persistency> - <readable></readable> + <readable/> + <writeable/> <simpleType> - <uint32_t></uint32_t> + <uint64_t/> </simpleType> - <writeable></writeable> + <no_export/> </attribute> <attribute> <description> - Memory AVDD voltage domain ID. All memory buffers in the same AVDD - voltage domain will share the same ID. IDs are arbitrarily assigned, - used for correlation between HB + HWSV, and are generated by - genHwsvMrwXml.pl + System attribute. + The max chiplets per proc available in the system. </description> - <id>AVDD_ID</id> + <id>MAX_CHIPLETS_PER_PROC</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint16_t> - <default>0</default> - </uint16_t> + <uint8_t/> </simpleType> </attribute> <attribute> + <id>MAX_COMPUTE_NODES_PER_SYSTEM</id> <description> - Memory VDD voltage domain ID. All memory buffers in the same VDD - voltage domain will share the same ID. IDs are arbitrarily assigned, - used for correlation between HB + HWSV, and are generated by - genHwsvMrwXml.pl + The max compute nodes available in the system. + Computed value based on CEC enclosures. </description> - <id>VDD_ID</id> - <persistency>non-volatile</persistency> - <readable></readable> <simpleType> - <uint16_t> - <default>0</default> - </uint16_t> + <uint8_t/> </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <no_export/> </attribute> <attribute> <description> - Memory VCS voltage domain ID. All memory buffers in the same VCS - voltage domain will share the same ID. IDs are arbitrarily assigned, - used for correlation between HB + HWSV, and are generated by - genHwsvMrwXml.pl + System attribute. + The max DIMMs per MBA Port available in the system. </description> - <id>VCS_ID</id> + <id>MAX_DIMMS_PER_MBA_PORT</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint16_t> - <default>0</default> - </uint16_t> + <uint8_t/> </simpleType> </attribute> <attribute> + <id>MAX_DMI_PER_PROC</id> <description> - Memory VPP voltage domain ID. All memory buffers in the same VPP - voltage domain will share the same ID. IDs are arbitrarily assigned, - used for correlation between HB + HWSV, and are generated by - genHwsvMrwXml.pl + System attribute. + The max DMI units per proc available in the system. </description> - <id>VPP_ID</id> - <persistency>non-volatile</persistency> - <readable></readable> <simpleType> - <uint16_t> - <default>0</default> - </uint16_t> + <uint8_t> + <default>8</default> + </uint8_t> </simpleType> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> - <description>Voltage Memory Rail Manager ID. Currently HB only needs - to configured the Vddr voltage rail manager during the IPL. The ID - is an arbitary value and needed as correlation token between HB and - HWSV. It will be generated by the genHwsvMrwXml.pl. + <description> + System attribute. + The max EX units per proc chip available in the system. </description> - <id>VDDR_ID</id> + <id>MAX_EXS_PER_PROC_CHIP</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint16_t> - <default>0</default> - </uint16_t> + <uint8_t/> </simpleType> - <no_export/> </attribute> <attribute> <description> - Nest VDDR Voltage Rail ID. The ID is an arbitrary value and is needed as - correlation token between HB and HWSV. It will be generated by the - genHwsvMrwXml.pl + System attribute. + The max MBAS per membuf available in the system. </description> - <id>NEST_VDDR_ID</id> + <id>MAX_MBAS_PER_MEMBUF_CHIP</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint16_t> - <default>0</default> - </uint16_t> + <uint8_t/> </simpleType> </attribute> <attribute> <description> - Nest VIO Voltage Rail ID. The ID is an arbitrary value and is needed as - correlation token between HB and HWSV. It will be generated by the - genHwsvMrwXml.pl + System attribute. + The max MBA ports per MBA available in the system. </description> - <id>NEST_VIO_ID</id> + <id>MAX_MBA_PORTS_PER_MBA</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint16_t> - <default>0</default> - </uint16_t> + <uint8_t/> </simpleType> </attribute> <attribute> <description> - Nest VDD Voltage Rail ID. The ID is an arbitrary value and is needed as - correlation token between HB and HWSV. It will be generated by the - genHwsvMrwXml.pl + System attribute. + The max MCS units available in the system. </description> - <id>NEST_VDD_ID</id> + <id>MAX_MCS_PER_SYSTEM</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint16_t> - <default>0</default> - </uint16_t> + <uint8_t> + <default>4</default> + </uint8_t> + </simpleType> + <no_export/> + </attribute> + + <attribute> + <id>MAX_POWER</id> + <description>Defines the maximum power consumption for a PCIe slot</description> + <simpleType> + <uint8_t/> </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <no_export/> </attribute> <attribute> <description> - Nest VDN Voltage Rail ID. The ID is an arbitrary value and is needed as - correlation token between HB and HWSV. It will be generated by the - genHwsvMrwXml.pl + System attribute. + The max proc chips per node available in the system. </description> - <id>NEST_VDN_ID</id> + <id>MAX_PROC_CHIPS_PER_NODE</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint16_t> - <default>0</default> - </uint16_t> + <uint8_t/> </simpleType> + <no_export/> </attribute> <attribute> + <id>MAX_SBE_SEEPROM_SIZE</id> <description> - Nest VCS Voltage Rail ID. The ID is an arbitrary value and is needed as - correlation token between HB and HWSV. It will be generated by the - genHwsvMrwXml.pl + Defines the maximum Seeprom storage size for the fully-customized SBE image + permitted by the platform. + For platforms (FSP/HB FW) which require the image to be constrained into a + physical storage device (SEEPROM), this should reflect the maximum size of that + memory (e.g., 256KB). + For platforms (Cronus) which may use a customized image in a virtual + envrionment with no physical storage constraints, this size may be + larger than the physical SEEPROM size. </description> - <id>NEST_VCS_ID</id> - <persistency>non-volatile</persistency> - <readable></readable> <simpleType> - <uint16_t> - <default>0</default> - </uint16_t> + <uint32_t> + <default>0x40000</default> + </uint32_t> </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_MAX_SBE_SEEPROM_SIZE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> - <description>VDDR memory programming type - 0 = POWERON - domain is programmed as part of regular power on sequence, - 1 = STATIC - domain needs to be programmed, no special computation needed, - 2 = DYNAMIC - domain needs to be programmed, uses dynamic vid logic, - 3 = DEFAULT - domain needs to be programmed, pgm values in sys xml file + <id>MBA_DIMM</id> + <description> + MBA port DIMM number of this DIMM + (deprecated in favor of POS_ON_MEM_PORT) </description> - <hasStringConversion></hasStringConversion> - <id>MSS_VDDR_PROGRAM</id> - <persistency>non-volatile</persistency> - <readable></readable> <simpleType> <uint8_t> <default>0</default> </uint8_t> </simpleType> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> - <description>VPP memory programming type - 0 = POWERON - domain is programmed as part of regular power on sequence, - 1 = STATIC - domain needs to be programmed, no special computation needed, - 2 = DYNAMIC - domain needs to be programmed, uses dynamic vid logic + <id>MBA_PORT</id> + <description> + MBA port this DIMM is connected to + (deprecated in favor of MEM_PORT) </description> - <hasStringConversion></hasStringConversion> - <id>MSS_VPP_PROGRAM</id> - <persistency>non-volatile</persistency> - <readable></readable> <simpleType> <uint8_t> <default>0</default> </uint8_t> </simpleType> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> - <description>VCS memory programming type - 0 = POWERON - domain is programmed as part of regular power on sequence, - 1 = STATIC - domain needs to be programmed, no special computation needed, - 2 = DYNAMIC - domain needs to be programmed, uses dynamic vid logic + <id>MC_PLL_BUCKET</id> + <description> + MC pll bucket selection in async mode for Cumulus </description> - <hasStringConversion></hasStringConversion> - <id>MSS_VCS_PROGRAM</id> - <persistency>non-volatile</persistency> - <readable></readable> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint8_t/> </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MC_PLL_BUCKET</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> - <description>AVDD memory programming type - 0 = POWERON - domain is programmed as part of regular power on sequence, - 1 = STATIC - domain needs to be programmed, no special computation needed, - 2 = DYNAMIC - domain needs to be programmed, uses dynamic vid logic - </description> - <hasStringConversion></hasStringConversion> - <id>MSS_AVDD_PROGRAM</id> - <persistency>non-volatile</persistency> - <readable></readable> + <description>Memory AVDD voltage domain offset in mV.</description> + <id>MEM_AVDD_OFFSET_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable/> <simpleType> - <uint8_t> + <uint32_t> <default>0</default> - </uint8_t> + </uint32_t> </simpleType> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_AVDD_OFFSET</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> - <description>VDD memory programming type - 0 = POWERON - domain is programmed as part of regular power on sequence, - 1 = STATIC - domain needs to be programmed, no special computation needed, - 2 = DYNAMIC - domain needs to be programmed, uses dynamic vid logic + <description>Base Address for all mainstore behind this processor</description> + <id>MEM_BASE</id> + <persistency>volatile-zeroed</persistency> + <readable/> + <simpleType> + <uint64_t/> + </simpleType> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_MEM_BASE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> + </attribute> + + <attribute> + <id>MEM_PORT</id> + <description> + Memory port this DIMM is connected to </description> - <hasStringConversion></hasStringConversion> - <id>MSS_VDD_PROGRAM</id> - <persistency>non-volatile</persistency> - <readable></readable> <simpleType> <uint8_t> <default>0</default> </uint8_t> </simpleType> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> - <description> - DRAM Voltage, each voltage rail would need to have a value. - Computed in mss_volt C code - in millivolts - creator: mss_volt - consumer: mss_eff_cnfg, others - firmware notes: none - </description> + <description>Memory VCS voltage domain offset in mV.</description> + <id>MEM_VCS_OFFSET_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable/> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <writeable/> <hwpfToHbAttrMap> - <id>ATTR_MSS_VOLT_VDDR</id> + <id>ATTR_MSS_VCS_OFFSET</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <id>MSS_VOLT_VDDR_MILLIVOLTS</id> + </attribute> + + <attribute> + <description>Memory VDDR voltage domain offset in mV.</description> + <id>MEM_VDDR_OFFSET_MILLIVOLTS</id> <persistency>volatile-zeroed</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t></uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <writeable></writeable> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_VDDR_OFFSET</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> - <description> - DRAM VPP Voltage, each voltage rail would need to have a value. - Computed in mss_volt C code - in millivolts. 0V - DDR3, 2.5V - DDR4 - creator: mss_volt - consumer: mss_eff_cnfg, others - firmware notes: none - </description> + <description>Memory VDD voltage domain offset in mV.</description> + <id>MEM_VDD_OFFSET_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable/> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <writeable/> <hwpfToHbAttrMap> - <id>ATTR_MSS_VOLT_VPP</id> + <id>ATTR_MSS_VDD_OFFSET</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <id>MSS_VOLT_VPP_MILLIVOLTS</id> + </attribute> + + <attribute> + <description>Memory VPP voltage domain offset in mV.</description> + <id>MEM_VPP_OFFSET_MILLIVOLTS</id> <persistency>volatile-zeroed</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t></uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <writeable></writeable> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_VPP_OFFSET</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> + <id>MFG_TRACE_ENABLE</id> <description> - Computed in mss_volt C code - in millivolts - creator: mss_volt - consumer: mss_eff_cnfg, others - firmware notes: none + Override this to a non-zero value to have the FAPI manufacturing + traces output to the console or go to a fsp trace buffer when + console not enabled. </description> - <id>MSS_VOLT_VCS_MILLIVOLTS</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> <simpleType> - <uint32_t></uint32_t> + <uint8_t/> </simpleType> - <writeable></writeable> + <persistency>volatile-zeroed</persistency> + <readable/> </attribute> + <enumerationType> + <id>MFG_WRAP_TEST_ABUS_LINKS_SET</id> + <description>Enum for MFG_WRAP_TEST_ABUS_LINKS_SET</description> + <enumerator> + <name>SET_NONE</name> + <value>0x0</value> + </enumerator> + <enumerator> + <name>SET_1</name> + <value>0x1</value> + </enumerator> + <enumerator> + <name>SET_2</name> + <value>0x2</value> + </enumerator> + </enumerationType> + <attribute> + <id>MFG_WRAP_TEST_ABUS_LINKS_SET</id> <description> - DRAM Voltage, each voltage rail would need to have a value. - Computed in mss_volt C code - in millivolts - creator: mss_volt - consumer: mss_eff_cnfg, others - firmware notes: none + Due to fabric limitations, we can only enable 2 links + at a time during wrap testing. This attribute defines + which set this ABUS link belong to. This attribute + will live on the OBUS target. The value will come + from MRW. When the value for this attribute matches + MFG_WRAP_TEST_ABUS_LINKS_SET_ENABLE, then we leave the + OBUSes configured. Otherwise, we deconfigure them. </description> - <id>MSS_VOLT_VDD_MILLIVOLTS</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> <simpleType> - <uint32_t></uint32_t> + <enumeration> + <default>SET_NONE</default> + <id>MFG_WRAP_TEST_ABUS_LINKS_SET</id> + </enumeration> </simpleType> - <writeable></writeable> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> + <id>MFG_WRAP_TEST_ABUS_LINKS_SET_ENABLE</id> <description> - DRAM Voltage, each voltage rail would need to have a value. - Computed in mss_volt C code - in millivolts - creator: mss_volt - consumer: mss_eff_cnfg, others - firmware notes: none + This attribute defines which set of ABUS links to enable + during MST wrap testing. This attribute will live on + the system target. The value will be overriden during + MST testing. When the value of MFG_WRAP_TEST_ABUS_LINKS_SET + on each of the OBUS matches with this value, then we leave the + OBUSes configured. Otherwise, we deconfigure them. </description> - <id>MSS_VOLT_AVDD_MILLIVOLTS</id> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> <persistency>volatile-zeroed</persistency> - <readable></readable> + <readable/> + </attribute> + + <attribute> + <id>MGC_LOAD_SOURCE</id> + <description>defines MGC load source</description> <simpleType> - <uint32_t></uint32_t> + <uint8_t/> </simpleType> - <writeable></writeable> + <persistency>non-volatile</persistency> + <readable/> + <no_export/> </attribute> <attribute> <description> - DRAM Voltage, each voltage rail would need to have a value. - Computed in mss_volt C code - in millivolts - creator: mss_volt - consumer: mss_eff_cnfg, others - firmware notes: none + System attribute. + The lowest frequency that a core can be set to in MHz. + This is the same for all cores in the system. + Data is provided by MVPD #V and is calculated as the + Maximum of the power save frequencies. + </description> + <id>MIN_FREQ_MHZ</id> + <persistency>volatile</persistency> + <readable/> + <simpleType> + <uint32_t> + <default>4800</default> + </uint32_t> + </simpleType> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_FREQ_CORE_FLOOR_MHZ</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> + </attribute> + + <attribute> + <id>MIRROR_BASE_ADDRESS</id> + <description>System Mirrorable Base Address + Bits8-12 Specifies System Selects + Bits13-14 Memory select + Bits15-18 Group ID (within an SMP) + Bits19-21 Chip ID (8 Max) + Bits22-63 Chip internal address (42 bits, 4TB) + Mirroring uses memory select </description> - <id>MSS_VOLT_VDDR_OFFSET_MILLIVOLTS</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> <simpleType> - <uint32_t></uint32_t> + <uint64_t> + <!-- 4PT --> + <default>0x4000000000000</default> + </uint64_t> </simpleType> - <writeable></writeable> + <persistency>non-volatile</persistency> + <readable/> + <no_export/> + <hwpfToHbAttrMap> + <id>ATTR_MIRROR_BASE_ADDRESS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> + <id>MNFG_ABUS_MIN_EYE_HEIGHT</id> <description> - DRAM VPP Voltage, each voltage rail would need to have a value. - Computed in mss_volt C code - in millivolts. 0V - DDR3, 2.5V - DDR4 - creator: mss_volt - consumer: mss_eff_cnfg, others - firmware notes: none + System attribute + 8 bit rx_min_eye_height value for A bus interfaces during system + manufacturing + creator: platform + firmware notes: Attribute value is in the Machine Readable Workbook </description> - <id>MSS_VOLT_VPP_OFFSET_MILLIVOLTS</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> <simpleType> - <uint32_t></uint32_t> + <uint8_t/> </simpleType> - <writeable></writeable> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> + <id>MNFG_ABUS_MIN_EYE_WIDTH</id> <description> - Computed in mss_volt C code - in millivolts - creator: mss_volt - consumer: mss_eff_cnfg, others - firmware notes: none + System attribute + 6 bit rx_min_eye_width value for A bus interfaces during system + manufacturing + creator: platform + firmware notes: Attribute value is in the Machine Readable Workbook </description> - <id>MSS_VOLT_VCS_OFFSET_MILLIVOLTS</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> <simpleType> - <uint32_t></uint32_t> + <uint8_t/> </simpleType> - <writeable></writeable> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> + <id>MNFG_DMI_MIN_EYE_HEIGHT</id> <description> - DRAM Voltage, each voltage rail would need to have a value. - Computed in mss_volt C code - in millivolts - creator: mss_volt - consumer: mss_eff_cnfg, others - firmware notes: none + System attribute. + 8 bit rx_min_eye_height value for DMI bus interfaces during system + manufacturing; used for both centaur and p8 + creator: platform + firmware notes: Attribute value is in the Machine Readable Workbook </description> - <id>MSS_VOLT_VDD_OFFSET_MILLIVOLTS</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> <simpleType> - <uint32_t></uint32_t> + <uint8_t/> </simpleType> - <writeable></writeable> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> + <id>MNFG_DMI_MIN_EYE_WIDTH</id> <description> - DRAM Voltage, each voltage rail would need to have a value. - Computed in mss_volt C code - in millivolts - creator: mss_volt - consumer: mss_eff_cnfg, others - firmware notes: none + System attribute. + 6 bit rx_min_eye_width value for DMI bus interfaces during system + manufacturing; used for both centaur and p8 + creator: platform + firmware notes: Attribute value is in the Machine Readable Workbook </description> - <id>MSS_VOLT_AVDD_OFFSET_MILLIVOLTS</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> <simpleType> - <uint32_t></uint32_t> + <uint8_t/> </simpleType> - <writeable></writeable> + <persistency>non-volatile</persistency> + <readable/> </attribute> + <enumerationType> + <id>MNFG_FLAG</id> + <description>Enumeration indicating the mnfg flags + that are set by the user. The values can be + combined using a bitwise 'OR'. The values will + need to be kept in sync with the FAPI + enumerator values. Also the enumeration type + is used by the ATTR_MNFG_FLAGS attribute. Should + note that the MNFG_FLAG values are of type uint32_t + </description> + <enumerator> + <!-- Use default mfg error thresholds and reporting values --> + <name>THRESHOLDS</name> + <value>0x00000001</value> + </enumerator> + <enumerator> + <!-- Enable AVP execution --> + <name>AVP_ENABLE</name> + <value>0x00000002</value> + </enumerator> + <enumerator> + <!-- Enable HDAT AVPs** --> + <name>HDAT_AVP_ENABLE</name> + <value>0x00000004</value> + </enumerator> + <enumerator> + <!-- All SRCs are terminating (CEC hardware/procedural) --> + <name>SRC_TERM</name> + <value>0x00000008</value> + </enumerator> + <enumerator> + <!-- Enable IPL memory diagnostics to report memory CE --> + <name>IPL_MEMORY_CE_CHECKING</name> + <value>0x00000010</value> + </enumerator> + <enumerator> + <!-- Enable Fast Background Scrub --> + <name>FAST_BACKGROUND_SCRUB</name> + <value>0x00000020</value> + </enumerator> + <enumerator> + <!-- Test DRAM Repairs --> + <name>TEST_DRAM_REPAIRS</name> + <value>0x00000040</value> + </enumerator> + <enumerator> + <!-- Disable Dram Repairs --> + <name>DISABLE_DRAM_REPAIRS</name> + <value>0x00000080</value> + </enumerator> + <enumerator> + <!-- Enable exhaustive pattern test --> + <name>ENABLE_EXHAUSTIVE_PATTERN_TEST</name> + <value>0x00000100</value> + </enumerator> + <enumerator> + <!-- Enable standard pattern test --> + <name>ENABLE_STANDARD_PATTERN_TEST</name> + <value>0x00000200</value> + </enumerator> + <enumerator> + <!-- Enable minimum pattern test --> + <name>ENABLE_MINIMUM_PATTERN_TEST</name> + <value>0x00000400</value> + </enumerator> + <enumerator> + <!-- Disable Fabric eRepair --> + <name>DISABLE_FABRIC_eREPAIR</name> + <value>0x00000800</value> + </enumerator> + <enumerator> + <!-- Disable Memory eRepair --> + <name>DISABLE_MEMORY_eREPAIR</name> + <value>0x00001000</value> + </enumerator> + <enumerator> + <!-- Fabric deploy lane spares --> + <name>FABRIC_DEPLOY_LANE_SPARES</name> + <value>0x00002000</value> + </enumerator> + <enumerator> + <!-- DMI deploy lane spares --> + <name>DMI_DEPLOY_LANE_SPARES</name> + <value>0x00004000</value> + </enumerator> + <enumerator> + <!-- Forcibly run PSI diagnostics --> + <name>PSI_DIAGNOSTIC</name> + <value>0x00008000</value> + </enumerator> + <enumerator> + <!-- Brazos Wrap Config --> + <name>BRAZOS_WRAP_CONFIG</name> + <value>0x00010000</value> + </enumerator> + <enumerator> + <!-- FSP is responsible for updating Processor SBE Image --> + <name>FSP_UPDATE_SBE_IMAGE</name> + <value>0x00020000</value> + </enumerator> + <enumerator> + <!-- Update both sides of SBE Image if update is needed --> + <name>UPDATE_BOTH_SIDES_OF_SBE</name> + <value>0x00040000</value> + </enumerator> + <enumerator> + <!-- Update both sides of SBE Image if update is needed --> + <name>IMMEDIATE_HALT</name> + <value>0x00080000</value> + </enumerator> + </enumerationType> + <attribute> <description> - Bitmask of threads to enable for each processor, - Zero means enable all architected threads + This attribute represents the maximum number of L4 Cache CEs allowed. + creator: platform (generated based on MRW data) </description> - <id>ENABLED_THREADS</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> + <id>MNFG_TH_CEN_L4_CACHE_CES</id> + <persistency>non-volatile</persistency> + <readable/> <simpleType> - <uint64_t></uint64_t> + <uint8_t> + <default>2</default> + </uint8_t> </simpleType> - <writeable></writeable> </attribute> <attribute> <description> - System attribute. - The max proc chips per node available in the system. + This attribute represents the Base threshold (for 2GB DRAM ) of + Memory CEs allowed during IPL. + creator: platform (generated based on MRW data) </description> - <id>MAX_PROC_CHIPS_PER_NODE</id> + <id>MNFG_TH_CEN_MBA_IPL_SOFT_CE_TH_ALGO</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t></uint8_t> + <uint8_t> + <default>2</default> + </uint8_t> </simpleType> - <no_export/> </attribute> <attribute> <description> - System attribute. - The max EX units per proc chip available in the system. + This attribute represents the maximum number of Memory RCEs + allowed per Rank during runtime. + creator: platform (generated based on MRW data) </description> - <id>MAX_EXS_PER_PROC_CHIP</id> + <id>MNFG_TH_CEN_MBA_RT_RCE_PER_RANK</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t></uint8_t> + <uint8_t> + <default>2</default> + </uint8_t> </simpleType> </attribute> <attribute> <description> - System attribute. - The max DIMMs per MBA Port available in the system. + This attribute represents the Base threshold (for 2GB DRAM ) of + Memory CEs allowed during runtime. + creator: platform (generated based on MRW data) </description> - <id>MAX_DIMMS_PER_MBA_PORT</id> + <id>MNFG_TH_CEN_MBA_RT_SOFT_CE_TH_ALGO</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t></uint8_t> + <uint8_t> + <default>2</default> + </uint8_t> </simpleType> </attribute> <attribute> <description> - System attribute. - The max MBA ports per MBA available in the system. + With MNFG thresholds enabled, PRD will make a predictive callout when a + memory intermittent MPE attention count is equal to this value. A value of + 0 defaults to the max threshold of 0xff. </description> - <id>MAX_MBA_PORTS_PER_MBA</id> + <id>MNFG_TH_MEMORY_IMPES</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t></uint8_t> + <uint8_t> + <default>1</default> + </uint8_t> </simpleType> </attribute> <attribute> <description> - System attribute. - The max MBAS per membuf available in the system. + With MNFG thresholds enabled, PRD will make a predictive callout when a + memory intermittent UE attention count is equal to this value. A value of + 0 defaults to the max threshold of 0xff. </description> - <id>MAX_MBAS_PER_MEMBUF_CHIP</id> + <id>MNFG_TH_MEMORY_IUES</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t></uint8_t> + <uint8_t> + <default>1</default> + </uint8_t> </simpleType> </attribute> <attribute> <description> - System attribute. - The max chiplets per proc available in the system. + This attribute represents the Maximum number of L2 Cache CEs allowed + during Manufacturing. + creator: platform (generated based on MRW data) </description> - <id>MAX_CHIPLETS_PER_PROC</id> + <id>MNFG_TH_P8EX_L2_CACHE_CES</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t></uint8_t> + <uint8_t> + <default>1</default> + </uint8_t> </simpleType> </attribute> <attribute> <description> - System attribute. - The max MCS units available in the system. + This attribute represents the Maximum number of L2 Column Repairs allowed + during Manufacturing. + creator: platform (generated based on MRW data) </description> - <id>MAX_MCS_PER_SYSTEM</id> + <id>MNFG_TH_P8EX_L2_COL_REPAIRS</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <uint8_t> - <default>4</default> + <default>0</default> </uint8_t> </simpleType> - <no_export/> </attribute> <attribute> - <description>Attribute to test signed attribute - functionality in the system</description> - <id>TEST_NEGATIVE_FCN</id> + <description> + This attribute represents the Maximum number of L2 Directory CEs allowed + during Manufacturing. + creator: platform (generated based on MRW data) + </description> + <id>MNFG_TH_P8EX_L2_DIR_CES</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <int8_t> - <default>-6</default> - </int8_t> + <uint8_t> + <default>1</default> + </uint8_t> </simpleType> - <writeable></writeable> </attribute> <attribute> - <description>FRU ID attribute used to report FRU information to the BMC - for each fru in the system.</description> - <global></global> - <id>FRU_ID</id> + <description> + This attribute represents the Maximum number of L2 Line Deletes allowed + during Manufacturing. + creator: platform (generated based on MRW data) + </description> + <id>MNFG_TH_P8EX_L2_LINE_DELETES</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t> + <uint8_t> <default>0</default> - </uint32_t> + </uint8_t> </simpleType> </attribute> <attribute> - <description>BMC FRU ID attribute to report the system firmware levels - to the BMC.</description> - <id>BMC_FRU_ID</id> + <description> + This attribute represents the Maximum number of L3 Cache CEs allowed + during Manufacturing. + creator: platform (generated based on MRW data) + </description> + <id>MNFG_TH_P8EX_L3_CACHE_CES</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint8_t> + <default>3</default> + </uint8_t> </simpleType> </attribute> <attribute> - <description>FRU ID attribute for centaur ECID data. This fru ID is used to - report the ECID data to the BMC and make it available for systems which - have then centaur chips soldered to the backplane.</description> - <id>CENTAUR_ECID_FRU_ID</id> + <description> + This attribute represents the Maximum number of L3 Column Repairs allowed + during Manufacturing. + creator: platform (generated based on MRW data) + </description> + <id>MNFG_TH_P8EX_L3_COL_REPAIRS</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t></uint32_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> </attribute> <attribute> <description> - Set to 1 by HWSV to indicate that attribute overrides exist in a PLCK IPL - (not an IPL by steps). This is read by Hostboot to determine if it needs - to request the attribute overrides from HWSV before starting its IPL. + This attribute represents the Maximum number of L3 Directory CEs allowed + during Manufacturing. + creator: platform (generated based on MRW data) </description> - <id>PLCK_IPL_ATTR_OVERRIDES_EXIST</id> + <id>MNFG_TH_P8EX_L3_DIR_CES</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <uint8_t> - <default>0x00</default> + <default>1</default> </uint8_t> </simpleType> - <writeable></writeable> </attribute> <attribute> - <description>Indicate an inter-enclosure bus at this endpoint target. - 0 = No, 1 = Yes + <description> + This attribute represents the Maximum number of L3 Line Deletes allowed + during Manufacturing. + creator: platform (generated based on MRW data) </description> - <id>IS_INTER_ENCLOSURE_BUS</id> - <persistency>volatile</persistency> - <readable></readable> + <id>MNFG_TH_P8EX_L3_LINE_DELETES</id> + <persistency>non-volatile</persistency> + <readable/> <simpleType> <uint8_t> <default>0</default> </uint8_t> </simpleType> - <writeable></writeable> </attribute> <attribute> - <description>Entity path of the peer target of a bus target + <description> + With MNFG thresholds enabled, PRD will make a predictive callout when an + RCD parity error (recovery enabled) attention count is equal to this + value. A value of 0 defaults to the max threshold of 0xff. </description> - <id>PEER_PATH</id> - <nativeType> - <name>EntityPath</name> - <default>physical:na</default> - </nativeType> + <id>MNFG_TH_RCD_PARITY_ERRORS</id> <persistency>non-volatile</persistency> - <readable></readable> - <no_export/> + <readable/> + <simpleType> + <uint8_t> + <default>1</default> + </uint8_t> + </simpleType> </attribute> <attribute> + <id>MNFG_XBUS_MIN_EYE_WIDTH</id> <description> - Cec Degraded Mode Policy flags - Use the CDM_POLICIES enum to decode. - If the appropriate bit is 1 then the policy mode is enabled, - and those type of Guard records are disabled. + System attribute + 6 bit rx_min_eye_width value for X bus interfaces during system + manufacturing + creator: platform + firmware notes: Attribute value is in the Machine Readable Workbook </description> - <id>CDM_POLICIES</id> + <simpleType> + <uint8_t/> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + </attribute> + + <attribute> + <description>Attribute indicating the target's model</description> + <hasStringConversion/> + <id>MODEL</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t> + <enumeration> + <id>MODEL</id> + </enumeration> + </simpleType> + </attribute> + + <enumerationType> + <default>NA</default> + <description>Enumeration indicating the target's model</description> + <enumerator> + <name>NA</name> + <value>0</value> + </enumerator> + <enumerator> + <name>RESERVED</name> + <value>16</value> + </enumerator> + <enumerator> + <name>VENICE</name> + </enumerator> + <enumerator> + <name>MURANO</name> + </enumerator> + <enumerator> + <name>NAPLES</name> + </enumerator> + <enumerator> + <name>NIMBUS</name> + </enumerator> + <enumerator> + <name>CUMULUS</name> + </enumerator> + <enumerator> + <name>AXONE</name> + </enumerator> + <enumerator> + <name>CENTAUR</name> + <value>48</value> + </enumerator> + <enumerator> + <name>EXPLORER</name> + </enumerator> + <enumerator> + <name>JEDEC</name> + <value>80</value> + </enumerator> + <enumerator> + <name>CDIMM</name> + </enumerator> + <enumerator> + <name>POWER8</name> + <value>112</value> + </enumerator> + <enumerator> + <name>POWER9</name> + <value>144</value> + </enumerator> + <enumerator> + <name>CECTPM</name> + </enumerator> + <enumerator> + <name>BMC</name> + </enumerator> + <enumerator> + <name>AST2500</name> + </enumerator> + <id>MODEL</id> + </enumerationType> + + <attribute> + <description>MRU ID attribute for chip/unit class</description> + <id>MRU_ID</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint32_t> <default>0x00</default> - </uint8_t> + </uint32_t> </simpleType> - <writeable></writeable> + <no_export/> </attribute> <attribute> - <description>Field Core Override (FCO) is the override value for the - number of functional cores allowed on the system. - FCO is used when customers order a system with N cores but they only want - to enable less than N cores to lower software license costs. A field in the - anchor VPD is set by manufacturing to specify the maximum number of cores - to enable. The number is maintained, even if some cores are garded out due - to error. - A value of 0 means all cores allowed; + <description>Maximum voltage limit for the dynamic VID DDR3 VDDR + voltage setpoint. In mV. </description> - <id>FIELD_CORE_OVERRIDE</id> + <id>MRW_DDR3_VDDR_MAX_LIMIT</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <uint32_t> <default>0</default> </uint32_t> </simpleType> - <writeable></writeable> </attribute> <attribute> - <description> - Value of the next PLID that host service should send + <description>Maximum voltage limit for the dynamic VID DDR3 VDDR + voltage setpoint. In mV. </description> - <id>HOSTSVC_PLID</id> + <id>MRW_DDR3_VDDR_MAX_LIMIT_POST_DRAM_INIT</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <uint32_t> - <default>0x89000000</default> + <default>0</default> </uint32_t> </simpleType> - <writeable></writeable> + <writeable/> </attribute> <attribute> - <description> - Policy indicating whether to perform the maximum amount of memory - pattern testing possible or not. - Set to 0x01 to perform the maximum amount of memory pattern testing - possible. - Set to 0x00 to perform the default amount of memory pattern testing. + <description>Maximum voltage limit for the dynamic VID DDR4 VDDR voltage + setpoint. In mV. </description> - <id>RUN_MAX_MEM_PATTERNS</id> + <id>MRW_DDR4_VDDR_MAX_LIMIT</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t> + <uint32_t> <default>0</default> - </uint8_t> + </uint32_t> </simpleType> - <writeable></writeable> </attribute> <attribute> - <description>Type of Master, ACTING_MASTER or MASTER_CANDIDATE or - NOT_MASTER</description> - <hasStringConversion></hasStringConversion> - <id>PROC_MASTER_TYPE</id> + <description>Maximum voltage limit for the dynamic VID DDR4 VDDR voltage + setpoint. In mV. + </description> + <id>MRW_DDR4_VDDR_MAX_LIMIT_POST_DRAM_INIT</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t> - <default>NOT_MASTER</default> - </uint8_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <writeable></writeable> - <no_export/> + <writeable/> </attribute> <attribute> - <description>MBA DRAM data bus utilization percent to use to determine cfg_nm_n_per_mba</description> - <id>MSS_DATABUS_UTIL_PER_MBA</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> + <id>MRW_MEM_THROTTLE_DENOMINATOR</id> + <description>Machine Readable Workbook throttle value for denominator cfg_nm_m</description> <simpleType> - <uint8_t></uint8_t> + <uint32_t/> </simpleType> - <writeable></writeable> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> - <description> - Holds the effective EC of the system. Effective EC is the lowest EC - among all the functional procs in the system. Some cards may "downbin" - the effective ECs of their contained processors, which could lower the - effective EC of the system beyond what would occur when considering - processor ECs alone + <description>AVDD memory programming type + 0 = POWERON - domain is programmed as part of regular power on sequence, + 1 = STATIC - domain needs to be programmed, no special computation needed, + 2 = DYNAMIC - domain needs to be programmed, uses dynamic vid logic </description> - <id>EFFECTIVE_EC</id> + <hasStringConversion/> + <id>MSS_AVDD_PROGRAM</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <uint8_t> - <default>0x10</default> + <default>0</default> </uint8_t> </simpleType> - <writeable></writeable> </attribute> <attribute> - <description>MRU ID attribute for chip/unit class</description> - <id>MRU_ID</id> + <description>Units: mV + </description> + <id>MSS_CENT_AVDD_INTERCEPT</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <uint32_t> - <default>0x00</default> + <default>0</default> </uint32_t> </simpleType> - <no_export/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_AVDD_SLOPE_INTERCEPT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> - <description> - Bitmask indicating what role this chip has in tod topology + <description>Units: uV/Membuf </description> - <id>TOD_ROLE</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> + <id>MSS_CENT_AVDD_SLOPE_ACTIVE</id> + <persistency>non-volatile</persistency> + <readable/> <simpleType> - <uint8_t></uint8_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <writeable></writeable> + <hwpfToHbAttrMap> + <id>ATTR_MSS_AVDD_SLOPE_ACTIVE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> - <description> - The amount of mainstore that PHYP needs to preserve per node - during MPIPL. + <description>Units: uV/Membuf </description> - <id>HB_RSV_MEM_SIZE_MB</id> + <id>MSS_CENT_AVDD_SLOPE_INACTIVE</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <uint32_t> - <default>256</default> + <default>0</default> </uint32_t> </simpleType> + <hwpfToHbAttrMap> + <id>ATTR_MSS_AVDD_SLOPE_INACTIVE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> - <description> - Indicates if system should consider abus logic when deconfiguring in - _deconfigureAssocProc(), will be overwritten on multi-node system + <description>Units: mV </description> - <id>DO_ABUS_DECONFIG</id> + <id>MSS_CENT_VCS_INTERCEPT</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> + <writeable/> </attribute> <attribute> - <description>Memory AVDD voltage domain offset in mV.</description> - <hwpfToHbAttrMap> - <id>ATTR_MSS_AVDD_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <id>MEM_AVDD_OFFSET_MILLIVOLTS</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> + <description>Units: uV/Membuf + </description> + <id>MSS_CENT_VCS_SLOPE_ACTIVE</id> + <persistency>non-volatile</persistency> + <readable/> <simpleType> <uint32_t> <default>0</default> </uint32_t> </simpleType> - <writeable></writeable> + <writeable/> </attribute> <attribute> - <description> System attribute array that defines the reconfig loop test cases - consumer: istep dispatcher reconfigLoopTestRunner function - This array is loaded with data via attribute override. The attribute is - then read and then overlayed onto a test case structure. - </description> - <id>RECONFIG_LOOP_TESTS</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> + <description>Units: uV/Membuf + </description> + <id>MSS_CENT_VCS_SLOPE_INACTIVE</id> + <persistency>non-volatile</persistency> + <readable/> <simpleType> - <array>5</array> - <uint64_t></uint64_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <writeable></writeable> + <writeable/> </attribute> <attribute> - <description> - Indicates whether reconfigure loop tests are enabled. - This attribute is set via attribute override + <description>Units: mV </description> - <id>RECONFIG_LOOP_TESTS_ENABLE</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> + <id>MSS_CENT_VDD_INTERCEPT</id> + <persistency>non-volatile</persistency> + <readable/> <simpleType> - <uint8_t></uint8_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <writeable></writeable> + <writeable/> </attribute> <attribute> - <description>Memory VDD voltage domain offset in mV.</description> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VDD_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <id>MEM_VDD_OFFSET_MILLIVOLTS</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> + <description>Units: uV/Membuf + </description> + <id>MSS_CENT_VDD_SLOPE_ACTIVE</id> + <persistency>non-volatile</persistency> + <readable/> <simpleType> <uint32_t> <default>0</default> </uint32_t> </simpleType> - <writeable></writeable> + <writeable/> </attribute> <attribute> - <description>Memory VCS voltage domain offset in mV.</description> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VCS_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <id>MEM_VCS_OFFSET_MILLIVOLTS</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> + <description>Units: uV/Membuf + </description> + <id>MSS_CENT_VDD_SLOPE_INACTIVE</id> + <persistency>non-volatile</persistency> + <readable/> <simpleType> <uint32_t> <default>0</default> </uint32_t> </simpleType> - <writeable></writeable> + <writeable/> </attribute> <attribute> - <description>Memory VPP voltage domain offset in mV.</description> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPP_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <id>MEM_VPP_OFFSET_MILLIVOLTS</id> + <description>MBA DRAM data bus utilization percent to use to determine cfg_nm_n_per_mba</description> + <id>MSS_DATABUS_UTIL_PER_MBA</id> <persistency>volatile-zeroed</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t> + <uint8_t/> + </simpleType> + <writeable/> + </attribute> + + <attribute> + <id>MSS_MBA_ADDR_INTERLEAVE_BIT</id> + <description>sets the Centaur address bits used to interleave addresses between MBA01 and MBA23. valid values are 23 through 32.</description> + <simpleType> + <uint8_t> <default>0</default> - </uint32_t> + </uint8_t> </simpleType> - <writeable></writeable> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> - <description>Memory VDDR voltage domain offset in mV.</description> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VDDR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <id>MEM_VDDR_OFFSET_MILLIVOLTS</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> + <id>MSS_MBA_CACHELINE_INTERLEAVE_MODE</id> + <description>centaur interleave mode. 1 = 256-BIT, 0 = 128-BIT.</description> <simpleType> - <uint32_t> + <uint8_t> <default>0</default> - </uint32_t> + </uint8_t> </simpleType> - <writeable></writeable> + <persistency>non-volatile</persistency> + <readable/> </attribute> + <enumerationType> + <default>NONE</default> + <description> + Enumeration defining the type of power control requested + </description> + <enumerator> + <name>OFF</name> + <value>0</value> + </enumerator> + <enumerator> + <name>POWER_DOWN</name> + <value>1</value> + </enumerator> + <enumerator> + <name>STR</name> + <value>2</value> + </enumerator> + <enumerator> + <name>PD_AND_STR</name> + <value>3</value> + </enumerator> + <id>MSS_MRW_IDLE_POWER_CONTROL_REQUESTED</id> + </enumerationType> + + <enumerationType> + <default>OFF</default> + <description> + Enumeration defining the type of power control requested + </description> + <enumerator> + <name>OFF</name> + <value>0</value> + </enumerator> + <enumerator> + <name>POWER_DOWN</name> + <value>1</value> + </enumerator> + <enumerator> + <name>STR</name> + <value>2</value> + </enumerator> + <enumerator> + <name>PD_AND_STR</name> + <value>3</value> + </enumerator> + <id>MSS_MRW_POWER_CONTROL_REQUESTED</id> + </enumerationType> + + <enumerationType> + <description>Enumeration for Temperature refresh mode</description> + <enumerator> + <name>DISABLE</name> + <value>0</value> + </enumerator> + <enumerator> + <name>ENABLE</name> + <value>1</value> + </enumerator> + <id>MSS_MRW_TEMP_REFRESH_MODE</id> + </enumerationType> + <attribute> + <id>MSS_PHY_SEQ_REFRESH</id> <description> - DRAM Voltage, each voltage rail would need to have a value. - Computed in mss_volt C code - in millivolts - creator: mss_volt - consumer: mss_eff_cnfg, others - firmware notes: none + Controls ENABLE/DISABLE of workaround that sets + the PHY sequencer to trigger refresh after draminit. </description> + <simpleType> + <uint8_t/> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> <hwpfToHbAttrMap> - <id>ATTR_CEN_MSS_VOLT</id> + <id>ATTR_MSS_PHY_SEQ_REFRESH</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <id>CEN_MSS_VOLT_VDDR_MILLIVOLTS</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> + </attribute> + + <attribute> + <description>VCS memory programming type + 0 = POWERON - domain is programmed as part of regular power on sequence, + 1 = STATIC - domain needs to be programmed, no special computation needed, + 2 = DYNAMIC - domain needs to be programmed, uses dynamic vid logic + </description> + <hasStringConversion/> + <id>MSS_VCS_PROGRAM</id> + <persistency>non-volatile</persistency> + <readable/> <simpleType> - <uint32_t></uint32_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <writeable></writeable> </attribute> <attribute> - <description> - DRAM VPP Voltage, each voltage rail would need to have a value. - Computed in mss_volt C code - in millivolts. 0V - DDR3, 2.5V - DDR4 - creator: mss_volt - consumer: mss_eff_cnfg, others - firmware notes: none + <description>VDDR memory programming type + 0 = POWERON - domain is programmed as part of regular power on sequence, + 1 = STATIC - domain needs to be programmed, no special computation needed, + 2 = DYNAMIC - domain needs to be programmed, uses dynamic vid logic, + 3 = DEFAULT - domain needs to be programmed, pgm values in sys xml file </description> - <hwpfToHbAttrMap> - <id>ATTR_CEN_MSS_VOLT_VPP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <id>CEN_MSS_VOLT_VPP_MILLIVOLTS</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> + <hasStringConversion/> + <id>MSS_VDDR_PROGRAM</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + </attribute> + + <attribute> + <description>VDD memory programming type + 0 = POWERON - domain is programmed as part of regular power on sequence, + 1 = STATIC - domain needs to be programmed, no special computation needed, + 2 = DYNAMIC - domain needs to be programmed, uses dynamic vid logic + </description> + <hasStringConversion/> + <id>MSS_VDD_PROGRAM</id> + <persistency>non-volatile</persistency> + <readable/> <simpleType> - <uint32_t></uint32_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <writeable></writeable> </attribute> <attribute> <description> + DRAM Voltage, each voltage rail would need to have a value. Computed in mss_volt C code - in millivolts creator: mss_volt consumer: mss_eff_cnfg, others firmware notes: none </description> - <id>CEN_MSS_VOLT_VCS_MILLIVOLTS</id> + <id>MSS_VOLT_AVDD_MILLIVOLTS</id> <persistency>volatile-zeroed</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t></uint32_t> + <uint32_t/> </simpleType> - <writeable></writeable> + <writeable/> </attribute> <attribute> @@ -2902,84 +3988,191 @@ consumer: mss_eff_cnfg, others firmware notes: none </description> - <id>CEN_MSS_VOLT_VDD_MILLIVOLTS</id> + <id>MSS_VOLT_AVDD_OFFSET_MILLIVOLTS</id> <persistency>volatile-zeroed</persistency> - <readable></readable> + <readable/> + <simpleType> + <uint32_t/> + </simpleType> + <writeable/> + </attribute> + + <attribute> + <description>Units: mV + </description> + <id>MSS_VOLT_DDR3_VDDR_INTERCEPT</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + </attribute> + + <attribute> + <description>Units: mV + </description> + <id>MSS_VOLT_DDR3_VDDR_INTERCEPT_POST_DRAM_INIT</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <writeable/> + </attribute> + + <attribute> + <description>Units: 1/Amps + </description> + <id>MSS_VOLT_DDR3_VDDR_SLOPE</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + </attribute> + + <attribute> + <description>Units: 1/Amps + </description> + <id>MSS_VOLT_DDR3_VDDR_SLOPE_POST_DRAM_INIT</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <writeable/> + </attribute> + + <attribute> + <description>Units: mV + </description> + <id>MSS_VOLT_DDR4_VDDR_INTERCEPT</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + </attribute> + + <attribute> + <description>Units: mV + </description> + <id>MSS_VOLT_DDR4_VDDR_INTERCEPT_POST_DRAM_INIT</id> + <persistency>non-volatile</persistency> + <readable/> <simpleType> - <uint32_t></uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <writeable></writeable> + <writeable/> + </attribute> + + <attribute> + <description>Units: 1/Amps + </description> + <id>MSS_VOLT_DDR4_VDDR_SLOPE</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + </attribute> + + <attribute> + <description>Units: 1/Amps + </description> + <id>MSS_VOLT_DDR4_VDDR_SLOPE_POST_DRAM_INIT</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <writeable/> </attribute> <attribute> <description> - DRAM Voltage, each voltage rail would need to have a value. Computed in mss_volt C code - in millivolts creator: mss_volt consumer: mss_eff_cnfg, others firmware notes: none </description> - <id>CEN_MSS_VOLT_AVDD_MILLIVOLTS</id> + <id>MSS_VOLT_VCS_MILLIVOLTS</id> <persistency>volatile-zeroed</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t></uint32_t> + <uint32_t/> </simpleType> - <writeable></writeable> + <writeable/> </attribute> <attribute> <description> - DRAM Voltage, each voltage rail would need to have a value. Computed in mss_volt C code - in millivolts creator: mss_volt consumer: mss_eff_cnfg, others firmware notes: none - </description> - <hwpfToHbAttrMap> - <id>ATTR_CEN_MSS_VDDR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <id>CEN_MSS_VOLT_VDDR_OFFSET_MILLIVOLTS</id> + </description> + <id>MSS_VOLT_VCS_OFFSET_MILLIVOLTS</id> <persistency>volatile-zeroed</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t></uint32_t> + <uint32_t/> </simpleType> - <writeable></writeable> + <writeable/> </attribute> <attribute> <description> - DRAM VPP Voltage, each voltage rail would need to have a value. - Computed in mss_volt C code - in millivolts. 0V - DDR3, 2.5V - DDR4 - creator: mss_volt - consumer: mss_eff_cnfg, others - firmware notes: none + DRAM Voltage, each voltage rail would need to have a value. + Computed in mss_volt C code - in millivolts + creator: mss_volt + consumer: mss_eff_cnfg, others + firmware notes: none </description> - <id>CEN_MSS_VOLT_VPP_OFFSET_MILLIVOLTS</id> + <id>MSS_VOLT_VDDR_MILLIVOLTS</id> <persistency>volatile-zeroed</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t></uint32_t> + <uint32_t/> </simpleType> - <writeable></writeable> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_VOLT_VDDR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> <description> + DRAM Voltage, each voltage rail would need to have a value. Computed in mss_volt C code - in millivolts creator: mss_volt consumer: mss_eff_cnfg, others firmware notes: none </description> - <id>CEN_MSS_VOLT_VCS_OFFSET_MILLIVOLTS</id> + <id>MSS_VOLT_VDDR_OFFSET_MILLIVOLTS</id> <persistency>volatile-zeroed</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t></uint32_t> + <uint32_t/> </simpleType> - <writeable></writeable> + <writeable/> </attribute> <attribute> @@ -2990,13 +4183,13 @@ consumer: mss_eff_cnfg, others firmware notes: none </description> - <id>CEN_MSS_VOLT_VDD_OFFSET_MILLIVOLTS</id> + <id>MSS_VOLT_VDD_MILLIVOLTS</id> <persistency>volatile-zeroed</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t></uint32_t> + <uint32_t/> </simpleType> - <writeable></writeable> + <writeable/> </attribute> <attribute> @@ -3007,25 +4200,21 @@ consumer: mss_eff_cnfg, others firmware notes: none </description> - <id>CEN_MSS_VOLT_AVDD_OFFSET_MILLIVOLTS</id> + <id>MSS_VOLT_VDD_OFFSET_MILLIVOLTS</id> <persistency>volatile-zeroed</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t></uint32_t> + <uint32_t/> </simpleType> - <writeable></writeable> + <writeable/> </attribute> <attribute> - <description>Units: uV/Membuf + <description>Units: mV </description> - <hwpfToHbAttrMap> - <id>ATTR_MSS_AVDD_SLOPE_ACTIVE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <id>MSS_CENT_AVDD_SLOPE_ACTIVE</id> + <id>MSS_VOLT_VPP_INTERCEPT</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <uint32_t> <default>0</default> @@ -3034,390 +4223,719 @@ </attribute> <attribute> - <description>Units: uV/Membuf + <description>Units: mV </description> - <hwpfToHbAttrMap> - <id>ATTR_MSS_AVDD_SLOPE_INACTIVE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <id>MSS_CENT_AVDD_SLOPE_INACTIVE</id> + <id>MSS_VOLT_VPP_INTERCEPT_POST_DRAM_INIT</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <uint32_t> <default>0</default> </uint32_t> </simpleType> + <writeable/> </attribute> <attribute> - <description>Units: mV + <description> + DRAM VPP Voltage, each voltage rail would need to have a value. + Computed in mss_volt C code - in millivolts. 0V - DDR3, 2.5V - DDR4 + creator: mss_volt + consumer: mss_eff_cnfg, others + firmware notes: none </description> + <id>MSS_VOLT_VPP_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable/> + <simpleType> + <uint32_t/> + </simpleType> + <writeable/> <hwpfToHbAttrMap> - <id>ATTR_MSS_AVDD_SLOPE_INTERCEPT</id> + <id>ATTR_MSS_VOLT_VPP</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> - <id>MSS_CENT_AVDD_INTERCEPT</id> - <persistency>non-volatile</persistency> - <readable></readable> + </attribute> + + <attribute> + <description> + DRAM VPP Voltage, each voltage rail would need to have a value. + Computed in mss_volt C code - in millivolts. 0V - DDR3, 2.5V - DDR4 + creator: mss_volt + consumer: mss_eff_cnfg, others + firmware notes: none + </description> + <id>MSS_VOLT_VPP_OFFSET_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable/> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t/> </simpleType> + <writeable/> </attribute> <attribute> - <description>Units: uV/Membuf + <description>Units: uV/DRAM </description> - <id>MSS_CENT_VDD_SLOPE_ACTIVE</id> + <id>MSS_VOLT_VPP_SLOPE</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <uint32_t> <default>0</default> </uint32_t> </simpleType> - <writeable></writeable> </attribute> <attribute> - <description>Units: uV/Membuf + <description>Units: uV/DRAM </description> - <id>MSS_CENT_VDD_SLOPE_INACTIVE</id> + <id>MSS_VOLT_VPP_SLOPE_POST_DRAM_INIT</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <uint32_t> <default>0</default> </uint32_t> </simpleType> - <writeable></writeable> + <writeable/> </attribute> <attribute> - <description>Units: mV + <description>VPP memory programming type + 0 = POWERON - domain is programmed as part of regular power on sequence, + 1 = STATIC - domain needs to be programmed, no special computation needed, + 2 = DYNAMIC - domain needs to be programmed, uses dynamic vid logic </description> - <id>MSS_CENT_VDD_INTERCEPT</id> + <hasStringConversion/> + <id>MSS_VPP_PROGRAM</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t> + <uint8_t> <default>0</default> - </uint32_t> + </uint8_t> </simpleType> - <writeable></writeable> </attribute> - <attribute> - <description>Units: uV/Membuf + <enumerationType> + <description>Enumeration indicating the multi scome + buffer size. The values can be combined using a + bitwise 'OR'. The values will need to be kept + in sync with the FAPI enumerator values. Also + the enumeration type is used by the + ATTR_MULTI_SCOM_BUFFER_MAX_SIZE. Should + note that the MULTI_SCOM_BUFFER_MAX_SIZE values + are of type uint32_t </description> - <id>MSS_CENT_VCS_SLOPE_ACTIVE</id> - <persistency>non-volatile</persistency> - <readable></readable> + <enumerator> + <name>MULTI_SCOM_BUFFER_SIZE_1KB</name> + <value>0x00000400</value> + </enumerator> + <enumerator> + <name>MULTI_SCOM_BUFFER_SIZE_2KB</name> + <value>0x00000800</value> + </enumerator> + <enumerator> + <name>MULTI_SCOM_BUFFER_SIZE_4KB</name> + <value>0x00001000</value> + </enumerator> + <enumerator> + <name>MULTI_SCOM_BUFFER_SIZE_8KB</name> + <value>0x00002000</value> + </enumerator> + <enumerator> + <name>MULTI_SCOM_BUFFER_SIZE_16KB</name> + <value>0x00004000</value> + </enumerator> + <enumerator> + <name>MULTI_SCOM_BUFFER_SIZE_32KB</name> + <value>0x00008000</value> + </enumerator> + <enumerator> + <name>MULTI_SCOM_BUFFER_SIZE_64KB</name> + <value>0x00010000</value> + </enumerator> + <enumerator> + <name>MULTI_SCOM_BUFFER_SIZE_128KB</name> + <value>0x00020000</value> + </enumerator> + <enumerator> + <name>MULTI_SCOM_BUFFER_SIZE_256KB</name> + <value>0x00040000</value> + </enumerator> + <enumerator> + <name>MULTI_SCOM_BUFFER_SIZE_512KB</name> + <value>0x00080000</value> + </enumerator> + <enumerator> + <name>MULTI_SCOM_BUFFER_SIZE_1MB</name> + <value>0x00100000</value> + </enumerator> + <id>MULTI_SCOM_BUFFER_MAX_SIZE_BIT</id> + </enumerationType> + + <attribute> + <id>NEST_PLL_FREQ_BUCKETS</id> + <description> + Constant defining number of NEST PLL frequency options ('buckets') + to be built into unsigned HW image. + </description> + <simpleType> + <uint8_t> + <default>0x05</default> + </uint8_t> + </simpleType> + <persistency>volatile</persistency> + <readable/> + </attribute> + + <attribute> + <id>NEST_PLL_FREQ_I2CDIV_LIST</id> + <description> + I2C bus divisor + index is bucket number + The values in this list will be factor of 1:64 to the NEST_PLL_FREQ_LIST + </description> <simpleType> <uint32_t> - <default>0</default> + <default>25,29,31,33,37</default> </uint32_t> + <array>5</array> </simpleType> - <writeable></writeable> + <persistency>volatile</persistency> + <readable/> </attribute> <attribute> - <description>Units: uV/Membuf - </description> - <id>MSS_CENT_VCS_SLOPE_INACTIVE</id> - <persistency>non-volatile</persistency> - <readable></readable> + <id>NEST_PLL_FREQ_LIST</id> + <description> + Nest PLL frequency in MHZ + index is bucket number + </description> <simpleType> <uint32_t> - <default>0</default> + <default>1600,1866,2000,2133,2400</default> </uint32_t> + <array>5</array> </simpleType> - <writeable></writeable> + <persistency>volatile</persistency> + <readable/> </attribute> <attribute> - <description>Units: mV + <description> + Nest VCS Voltage Rail ID. The ID is an arbitrary value and is needed as + correlation token between HB and HWSV. It will be generated by the + genHwsvMrwXml.pl </description> - <id>MSS_CENT_VCS_INTERCEPT</id> + <id>NEST_VCS_ID</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t> + <uint16_t> <default>0</default> - </uint32_t> + </uint16_t> </simpleType> - <writeable></writeable> </attribute> <attribute> - <description>Units: uV/DRAM + <description> + Nest VDDR Voltage Rail ID. The ID is an arbitrary value and is needed as + correlation token between HB and HWSV. It will be generated by the + genHwsvMrwXml.pl </description> - <id>MSS_VOLT_VPP_SLOPE</id> + <id>NEST_VDDR_ID</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t> + <uint16_t> <default>0</default> - </uint32_t> + </uint16_t> </simpleType> </attribute> <attribute> - <description>Units: mV + <description> + Nest VDD Voltage Rail ID. The ID is an arbitrary value and is needed as + correlation token between HB and HWSV. It will be generated by the + genHwsvMrwXml.pl </description> - <id>MSS_VOLT_VPP_INTERCEPT</id> + <id>NEST_VDD_ID</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t> + <uint16_t> <default>0</default> - </uint32_t> + </uint16_t> </simpleType> </attribute> <attribute> - <description>Units: uV/DRAM + <description> + Nest VDN Voltage Rail ID. The ID is an arbitrary value and is needed as + correlation token between HB and HWSV. It will be generated by the + genHwsvMrwXml.pl </description> - <id>MSS_VOLT_VPP_SLOPE_POST_DRAM_INIT</id> + <id>NEST_VDN_ID</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t> + <uint16_t> <default>0</default> - </uint32_t> + </uint16_t> </simpleType> - <writeable></writeable> </attribute> <attribute> - <description>Units: mV + <description> + Nest VIO Voltage Rail ID. The ID is an arbitrary value and is needed as + correlation token between HB and HWSV. It will be generated by the + genHwsvMrwXml.pl </description> - <id>MSS_VOLT_VPP_INTERCEPT_POST_DRAM_INIT</id> + <id>NEST_VIO_ID</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t> + <uint16_t> <default>0</default> - </uint32_t> + </uint16_t> </simpleType> - <writeable></writeable> </attribute> <attribute> - <description>Units: 1/Amps + <description> + The nominal core frequency in MHz. + This is the same for all cores in the system. + Data is provided by MVPD #V. </description> - <id>MSS_VOLT_DDR3_VDDR_SLOPE</id> - <persistency>non-volatile</persistency> - <readable></readable> + <id>NOMINAL_FREQ_MHZ</id> + <persistency>volatile</persistency> + <readable/> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t/> </simpleType> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_FREQ_CORE_NOMINAL_MHZ</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> - <description>Units: mV + <description>NPU MMIO BAR base address values + creator: platform + consumer: proc_setup_bars + firmware notes: + 64-bit address representing BAR RA + NOTE: BAR register covers RA 14:51 + first dimension: unit number (0:3) + second dimension: BAR number (0:1) </description> - <id>MSS_VOLT_DDR3_VDDR_INTERCEPT</id> + <id>NPU_MMIO_BAR_BASE_ADDR</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t> + <array>4,2</array> + <uint64_t> <default>0</default> - </uint32_t> + </uint64_t> </simpleType> + <hwpfToHbAttrMap> + <id>ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> - <description>Maximum voltage limit for the dynamic VID DDR3 VDDR - voltage setpoint. In mV. + <description>NPU MMIO BAR size values + creator: platform + consumer: proc_setup_bars + firmware notes: none + first dimension: unit number (0:3) + second dimension: BAR number (0:1) </description> - <id>MRW_DDR3_VDDR_MAX_LIMIT</id> + <id>NPU_MMIO_BAR_SIZE</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t> + <array>4,2</array> + <uint64_t> <default>0</default> - </uint32_t> + </uint64_t> </simpleType> + <hwpfToHbAttrMap> + <id>ATTR_PROC_NPU_MMIO_BAR_SIZE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> + <enumerationType> + <description>Enumeration indicating the BAR size + used with ATTR_PROC_NPU_MMIO_BAR_SIZE</description> + <enumerator> + <name>2_MB</name> + <value>0x0000000000200000</value> + </enumerator> + <enumerator> + <name>1_MB</name> + <value>0x0000000000100000</value> + </enumerator> + <enumerator> + <name>512_KB</name> + <value>0x0000000000080000</value> + </enumerator> + <enumerator> + <name>256_KB</name> + <value>0x0000000000040000</value> + </enumerator> + <enumerator> + <name>128_KB</name> + <value>0x0000000000020000</value> + </enumerator> + <enumerator> + <name>64_KB</name> + <value>0x0000000000010000</value> + </enumerator> + <id>NPU_MMIO_BAR_SIZE</id> + </enumerationType> + <attribute> - <description>Units: 1/Amps + <complexType> + <description>Numeric POD type test structure</description> + <field> + <default>physical:sys-0</default> + <description>Entity path for testing purposes</description> + <name>fsiPath</name> + <type>EntityPath</type> + </field> + <field> + <default>CHIP</default> + <description>Class for testing purposes</description> + <name>className</name> + <type>CLASS</type> + </field> + <field> + <default>0xAB</default> + <description>Test uint8</description> + <name>uint8</name> + <type>uint8_t</type> + </field> + <field> + <default>0xABCD</default> + <description>Test uint16</description> + <name>uint16</name> + <type>uint16_t</type> + </field> + <field> + <default>0xABCDEF01</default> + <description>Test uint32</description> + <name>uint32</name> + <type>uint32_t</type> + </field> + <field> + <default>0xABCDEF0123456789</default> + <description>Test uint64</description> + <name>uint64</name> + <type>uint64_t</type> + </field> + <field> + <default>-124</default> + <description>Test int8</description> + <name>int8</name> + <type>int8_t</type> + </field> + <field> + <default>-32764</default> + <description>Test int16</description> + <name>int16</name> + <type>int16_t</type> + </field> + <field> + <default>-2147483644</default> + <description>Test int32</description> + <name>int32</name> + <type>int32_t</type> + </field> + <field> + <default>-9223372036854775804</default> + <description>Test int64</description> + <name>int64</name> + <type>int64_t</type> + </field> + </complexType> + <description>Attribute which tests numeric POD types</description> + <id>NUMERIC_POD_TYPE_TEST</id> + <persistency>non-volatile</persistency> + <readable/> + </attribute> + + <attribute> + <id>OBUS_BRICK_LANE_MASK</id> + <description> + Lane mask for which 8 lanes belong to this brick + This is a right justified 24-bit value. Only 8 of the + 24 bits will be set representing the lanes belonging to + the associated brick. + Provided by the MRW. + </description> + <simpleType> + <uint32_t/> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + </attribute> + + <attribute> + <id>OBUS_SLOT_INDEX</id> + <description> + Position of the obus slot that the Obus brick is connected to + (represented in decimal). There is only one slot that a given + brick connects to and there are only 6 slots per proc, + so, we just need a single uint8_t representing the position + of the slot. + Provided by the MRW. + </description> + <simpleType> + <uint8_t/> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <no_export/> + </attribute> + + <attribute> + <description> + This attribute is to determine whether an occ is master capable. + An OCC is master capable if it's parent processor is wired to the + APSS. </description> - <id>MSS_VOLT_DDR3_VDDR_SLOPE_POST_DRAM_INIT</id> + <id>OCC_MASTER_CAPABLE</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t> + <uint8_t> <default>0</default> - </uint32_t> + </uint8_t> </simpleType> - <writeable></writeable> + <no_export/> </attribute> <attribute> - <description>Units: mV - </description> - <id>MSS_VOLT_DDR3_VDDR_INTERCEPT_POST_DRAM_INIT</id> + <description>Ordinal ID of a target</description> + <id>ORDINAL_ID</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <uint32_t> - <default>0</default> + <default>0xFFFFFFFF</default> </uint32_t> </simpleType> - <writeable></writeable> + <writeable/> + <no_export/> </attribute> <attribute> - <description>Maximum voltage limit for the dynamic VID DDR3 VDDR - voltage setpoint. In mV. + <description> + Physical entity path of the target's associated pervasive target </description> - <id>MRW_DDR3_VDDR_MAX_LIMIT_POST_DRAM_INIT</id> + <id>PARENT_PERVASIVE</id> + <nativeType> + <name>EntityPath</name> + </nativeType> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + <virtual/> + <no_export/> + </attribute> + + <attribute> + <description>Base address (target HRMOR) of the payload. Value is in MB.</description> + <id>PAYLOAD_BASE</id> + <persistency>volatile</persistency> + <readable/> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint64_t> + <default>256</default> + </uint64_t> </simpleType> - <writeable></writeable> + <writeable/> </attribute> + <attribute> + <description>The offset from base address of the payload entry-point. + Current default is 0x180</description> + <id>PAYLOAD_ENTRY</id> + <persistency>volatile</persistency> + <readable/> + <simpleType> + <uint64_t> + <default>0x180</default> + </uint64_t> + </simpleType> + <writeable/> + </attribute> <attribute> - <description>Units: 1/Amps + <description>Indicate that payload should be placed in mirrored memory. + Set by the FSP based on the value of the registry key indicating + the memory mirroring mode. </description> - <id>MSS_VOLT_DDR4_VDDR_SLOPE</id> + <id>PAYLOAD_IN_MIRROR_MEM</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t> + <uint8_t> <default>0</default> - </uint32_t> + </uint8_t> </simpleType> + <writeable/> + <no_export/> </attribute> <attribute> - <description>Units: mV + <description> + Attribute indicating what kind of payload is to be started. </description> - <id>MSS_VOLT_DDR4_VDDR_INTERCEPT</id> + <hasStringConversion/> + <id>PAYLOAD_KIND</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <enumeration> + <id>PAYLOAD_KIND</id> + </enumeration> </simpleType> + <writeable/> </attribute> - <attribute> - <description>Maximum voltage limit for the dynamic VID DDR4 VDDR voltage - setpoint. In mV. + <enumerationType> + <default>UNKNOWN</default> + <description> + Enumeration indicating what kind of payload is to be started </description> - <id>MRW_DDR4_VDDR_MAX_LIMIT</id> + <enumerator> + <name>UNKNOWN</name> + <value>0</value> + </enumerator> + <enumerator> + <name>PHYP</name> + <value>1</value> + </enumerator> + <enumerator> + <name>SAPPHIRE</name> + <value>2</value> + </enumerator> + <enumerator> + <name>NONE</name> + <value>3</value> + </enumerator> + <id>PAYLOAD_KIND</id> + </enumerationType> + + <attribute> + <id>PCIE_32BIT_DMA_SIZE</id> + <description>PCIe slot 32bit DMA size definition</description> + <simpleType> + <uint8_t/> + </simpleType> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + <no_export/> + </attribute> + + <attribute> + <id>PCIE_32BIT_MMIO_SIZE</id> + <description>PCIe slot 32bit MMIO size definition</description> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint8_t/> </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <no_export/> </attribute> <attribute> - <description>Units: 1/Amps - </description> - <id>MSS_VOLT_DDR4_VDDR_SLOPE_POST_DRAM_INIT</id> + <id>PCIE_64BIT_DMA_SIZE</id> + <description>PCIe slot 64bit DMA size definition</description> + <simpleType> + <uint8_t/> + </simpleType> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + <no_export/> + </attribute> + + <attribute> + <id>PCIE_64BIT_MMIO_SIZE</id> + <description>PCIe slot 64bit MMIO size definition</description> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint8_t/> </simpleType> - <writeable></writeable> + <persistency>non-volatile</persistency> + <readable/> + <no_export/> </attribute> <attribute> - <description>Units: mV - </description> - <id>MSS_VOLT_DDR4_VDDR_INTERCEPT_POST_DRAM_INIT</id> + <id>PCIE_CAPABILITES</id> + <description>Denotes the capabilites of this pcie slot</description> + <simpleType> + <uint8_t/> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <no_export/> + </attribute> + + <attribute> + <description>Base Address of PCI 32 bit Memory Space</description> + <id>PCI_BASE_ADDRS_32</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <array>4</array> + <uint64_t/> </simpleType> - <writeable></writeable> </attribute> <attribute> - <description>Maximum voltage limit for the dynamic VID DDR4 VDDR voltage - setpoint. In mV. - </description> - <id>MRW_DDR4_VDDR_MAX_LIMIT_POST_DRAM_INIT</id> + <description>Base Address of PCI 64 bit Memory Space</description> + <id>PCI_BASE_ADDRS_64</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <array>4</array> + <uint64_t/> </simpleType> - <writeable></writeable> </attribute> <attribute> - <complexType> - <description>Structure which defines which I2C access method to use at - a point in time. Only applicable if target supports one or more I2C - types. Only one bit (of the first two) can ever be set at any one time. - </description> - <field> - <bits>1</bits> - <default>0</default> - <description>0b0: Do not use FSI I2C at this time. 0b1: Use FSI - I2C at this time</description> - <name>useFsiI2C</name> - <type>uint8_t</type> - </field> - <field> - <bits>1</bits> - <default>0</default> - <description>0b0: Do not use Host I2C at this time. 0b1: Use - Host I2C at this time</description> - <name>useHostI2C</name> - <type>uint8_t</type> - </field> - <field> - <bits>6</bits> + <id>PCI_REFCLOCK_RCVR_TERM</id> + <description> + Defines system specific value of PCI refclock receiver termination (FSI GP4 bits 10:11) + </description> + <simpleType> + <uint8_t> <default>0</default> - <description>Reserved for future expansion</description> - <name>reserved</name> - <type>uint8_t</type> - </field> - </complexType> - <description>Attribute storing information about which I2C method to use</description> - <id>I2C_SWITCHES</id> - <persistency>volatile</persistency> - <readable></readable> - <writeable></writeable> + </uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <hasStringConversion/> + <readable/> </attribute> <attribute> <description> - This attribute is to determine whether an occ is master capable. - An OCC is master capable if it's parent processor is wired to the - APSS. + This attribute indicates if the PEC can be bifurcated. The value is determined from the workbook. + 0 - PEC is not bifurcateable + 1 - PEC can be bifurcated + Note: Altering the lane map can be done using the HX keyword. </description> - <id>OCC_MASTER_CAPABLE</id> + <id>PEC_IS_BIFURCATABLE</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + <writeable/> <simpleType> <uint8_t> <default>0</default> @@ -3427,7 +4945,7 @@ </attribute> <attribute> - <description> + <description> This attribute holds the contents of the HX keyword read by the FSP from a PCIe card. The keyword data is used to determine the PHB bifurcation settings. @@ -3457,7 +4975,7 @@ id below is valid Bit 1-3: 0b000 = reserved (when bit 0 = 0b0) - 0b001 -> 0b111 + 0b001 -> 0b111 Bit 4-7 reserved @@ -3487,8 +5005,8 @@ </description> <id>PEC_PCIE_HX_KEYWORD_DATA</id> <persistency>non-volatile</persistency> - <readable></readable> - <writeable></writeable> + <readable/> + <writeable/> <simpleType> <array>9</array> <uint8_t> @@ -3497,50 +5015,6 @@ </simpleType> <no_export/> </attribute> - <attribute> - <description> - This attribute indicates if the PEC can be bifurcated. The value is determined from the workbook. - 0 - PEC is not bifurcateable - 1 - PEC can be bifurcated - Note: Altering the lane map can be done using the HX keyword. - </description> - <id>PEC_IS_BIFURCATABLE</id> - <persistency>non-volatile</persistency> - <readable></readable> - <writeable></writeable> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <no_export/> - </attribute> - - <attribute> - <description>Effective PCIE Lane Mask - Creator: Firmware - Purpose: Holds the effective PCIE lane mask of each PEC after taking - into account any IOP bifurcations. If no IOP bifurcations present, - this is just the value of the PEC_PCIE_LANE_MASK_NON_BIFURCATED - attribute - Data Format: x4 array of uint16_t values. The uint16_t value is a - mask for lane 0, the next for lane 1 and so on until lane 3. - A lane set mask indicates which groups of lanes are assigned to an - IOP. For instance, lane set 0 value of 0xFFFF and lane set 1 value - of 0x0000 for PEC0 means PEC0 is a x16. Lane set 0 value of 0xFF00 - and lane set 1 value of 0x00FF for PEC0, means the IOP is bifurcated - into two x8s. - </description> - <id>PROC_PCIE_LANE_MASK</id> - <persistency>non-volatile</persistency> - <readable></readable> - <simpleType> - <array>4</array> - <uint16_t></uint16_t> - </simpleType> - <writeable></writeable> - <no_export/> - </attribute> <attribute> <description>Effective PCIE IOP reversal configuration @@ -3556,12 +5030,31 @@ </description> <id>PEC_PCIE_IOP_REVERSAL</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + <simpleType> + <array>4</array> + <uint8_t/> + </simpleType> + <writeable/> + </attribute> + + <attribute> + <description>Base PCIE IOP reversal configuration + Creator: Firmware + Purpose: Holds the PCIE IOP reversal value for cases where the IOP + is bifurcated + Data Format: x4 array of uint8_t values. The first uint8_t value is + lane set 0, the second for lane set 2 and so on. The given index in + the array is a mask which specifies which bit to invert in the lane + swap settings for the given lane set + </description> + <id>PEC_PCIE_IOP_REVERSAL_BIFURCATED</id> + <persistency>non-volatile</persistency> + <readable/> <simpleType> <array>4</array> - <uint8_t></uint8_t> + <uint8_t/> </simpleType> - <writeable></writeable> </attribute> <attribute> @@ -3576,10 +5069,28 @@ </description> <id>PEC_PCIE_IOP_REVERSAL_NON_BIFURCATED</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <array>4</array> - <uint8_t></uint8_t> + <uint8_t/> + </simpleType> + </attribute> + + <attribute> + <description>Bifurcated PCIE IOP swap configuration value + Creator: MRW + Purpose: Holds the base IOP swap configuration value for the IOPs in the + case where they are bifurcated. The swap value controls how PCIE + lanes are recordered when the leave the IOP, to provide lane routing + flexibility. + Data Format: A uint8_t value. The value specifices for the hardware how + to swap the PCIE lanes for the given PEC. + </description> + <id>PEC_PCIE_IOP_SWAP_BIFURCATED</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint8_t/> </simpleType> </attribute> @@ -3595,14 +5106,33 @@ </description> <id>PEC_PCIE_IOP_SWAP_NON_BIFURCATED</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t></uint8_t> + <uint8_t/> </simpleType> <no_export/> </attribute> <attribute> + <description>PCIE Lane Mask bifurcated configuration + Creator: MRW + Purpose: Holds the PCIE lane mask assuming IOPs are bifurcated. + Data Format: x4 array of uint16_t values. The first uint8_t value is + lane set 0, the second for lane set 2 and so on. A lane set mask + indicates which groups of lanes are assigned to an IOP. For + instance, lane set 0 value of 0xFF00 and lane set 1 value of 0x00FF + means the IOP is bifurcated into two x8s. + </description> + <id>PEC_PCIE_LANE_MASK_BIFURCATED</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <array>4</array> + <uint16_t/> + </simpleType> + </attribute> + + <attribute> <description>PCIE Lane Mask base configuration Creator: MRW Purpose: Holds the base PCIE lane mask assuming no dynamic IOP @@ -3616,896 +5146,1898 @@ </description> <id>PEC_PCIE_LANE_MASK_NON_BIFURCATED</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <array>4</array> - <uint16_t></uint16_t> + <uint16_t/> </simpleType> <no_export/> </attribute> <attribute> - <description>Base PCIE IOP reversal configuration - Creator: Firmware - Purpose: Holds the PCIE IOP reversal value for cases where the IOP - is bifurcated - Data Format: x4 array of uint8_t values. The first uint8_t value is - lane set 0, the second for lane set 2 and so on. The given index in - the array is a mask which specifies which bit to invert in the lane - swap settings for the given lane set + <description>Entity path of the peer target of a bus target </description> - <id>PEC_PCIE_IOP_REVERSAL_BIFURCATED</id> + <id>PEER_PATH</id> + <nativeType> + <name>EntityPath</name> + <default>physical:na</default> + </nativeType> <persistency>non-volatile</persistency> - <readable></readable> - <simpleType> - <array>4</array> - <uint8_t></uint8_t> - </simpleType> + <readable/> + <no_export/> </attribute> <attribute> - <description>Bifurcated PCIE IOP swap configuration value - Creator: MRW - Purpose: Holds the base IOP swap configuration value for the IOPs in the - case where they are bifurcated. The swap value controls how PCIE - lanes are recordered when the leave the IOP, to provide lane routing - flexibility. - Data Format: A uint8_t value. The value specifices for the hardware how - to swap the PCIE lanes for the given PEC. + <description>Peer target's address of a A/X-bus connection. + NULL means address 0 for no peer target. If a + target instance overrides the default with the + peer target's PHYS_PATH. The target compiler will + convert the valid PHYS_PATH string into the runtime + virtual address of the peer target instance. </description> - <id>PEC_PCIE_IOP_SWAP_BIFURCATED</id> + <id>PEER_TARGET</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t></uint8_t> + <Target_t> + <default>NULL</default> + </Target_t> </simpleType> </attribute> - <attribute> - <description>PCIE Lane Mask bifurcated configuration - Creator: MRW - Purpose: Holds the PCIE lane mask assuming IOPs are bifurcated. - Data Format: x4 array of uint16_t values. The first uint8_t value is - lane set 0, the second for lane set 2 and so on. A lane set mask - indicates which groups of lanes are assigned to an IOP. For - instance, lane set 0 value of 0xFF00 and lane set 1 value of 0x00FF - means the IOP is bifurcated into two x8s. + <enumerationType> + <description> + Enumeration indicating the OFF setting for the core and cache chiplet + VCS PFET controllers </description> - <id>PEC_PCIE_LANE_MASK_BIFURCATED</id> + <enumerator> + <name>NOOFF</name> + <value>0</value> + </enumerator> + <enumerator> + <name>ALLBUT1TO7OFF</name> + <value>1</value> + </enumerator> + <enumerator> + <name>ALLBUT2TO7OFF</name> + <value>2</value> + </enumerator> + <enumerator> + <name>ALLBUT3TO7OFF</name> + <value>3</value> + </enumerator> + <enumerator> + <name>ALLBUT4TO7OFF</name> + <value>4</value> + </enumerator> + <enumerator> + <name>ALLBUT5TO7OFF</name> + <value>5</value> + </enumerator> + <enumerator> + <name>ALLBUT6TO7OFF</name> + <value>6</value> + </enumerator> + <enumerator> + <name>ALLBUT7TO7OFF</name> + <value>7</value> + </enumerator> + <enumerator> + <name>ALLOFF</name> + <value>8</value> + </enumerator> + <id>PFET_VCS_VOFF_SEL</id> + </enumerationType> + + <enumerationType> + <description> + Enumeration indicating the OFF setting for the core and cache chiplet + DD PFET controllers + </description> + <enumerator> + <name>NOOFF</name> + <value>0</value> + </enumerator> + <enumerator> + <name>ALLBUT1TO7OFF</name> + <value>1</value> + </enumerator> + <enumerator> + <name>ALLBUT2TO7OFF</name> + <value>2</value> + </enumerator> + <enumerator> + <name>ALLBUT3TO7OFF</name> + <value>3</value> + </enumerator> + <enumerator> + <name>ALLBUT4TO7OFF</name> + <value>4</value> + </enumerator> + <enumerator> + <name>ALLBUT5TO7OFF</name> + <value>5</value> + </enumerator> + <enumerator> + <name>ALLBUT6TO7OFF</name> + <value>6</value> + </enumerator> + <enumerator> + <name>ALLBUT7TO7OFF</name> + <value>7</value> + </enumerator> + <enumerator> + <name>ALLOFF</name> + <value>8</value> + </enumerator> + <id>PFET_VDD_VOFF_SEL</id> + </enumerationType> + + <attribute> + <id>PG</id> + <description> + Chiplet Partial good info attribute. Provided by Ring scans + </description> + <simpleType> + <uint16_t/> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <ignoreEkb/> + <hwpfToHbAttrMap> + <id>ATTR_PG</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> + </attribute> + + <attribute> + <description>Base Address of PHB Register Space</description> + <id>PHB_BASE_ADDRS</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <array>4</array> - <uint16_t></uint16_t> + <uint64_t> + <default> + 0xFFFFFFFFFFFFFFFF, + 0xFFFFFFFFFFFFFFFF, + 0xFFFFFFFFFFFFFFFF, + 0xFFFFFFFFFFFFFFFF + </default> + </uint64_t> </simpleType> </attribute> <attribute> - <description>Indicates whether PCIE lanes terminate at a pluggable slot - Creator: MRW - Purpose: Used by FW to know whether the given PCIE lanes terminate at a - pluggable slot or not. If this is the case, and the platform - supports bifurcation, the card's VPD should be interrogated to - determine whether to bifurcate the IOP or not. - Data Format: x4 array of uint8_t values. The first value indicates - whether lane set 0 terminates at a pluggable slot. The - next three values indicate the same for lane sets 1-3. A value of - 1 at a given array index indicates the lanes terminate at a - pluggable slot, 0 otherwise. - </description> - <id>PROC_PCIE_IS_SLOT</id> + <description>Physical hierarchical path to the target</description> + <id>PHYS_PATH</id> + <nativeType> + <name>EntityPath</name> + </nativeType> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + </attribute> + + <attribute> + <id>PIB_I2C_NEST_PLL</id> + <description> + i2c pll for the system + default is 0x26 (For PIB @500 MHz (2 GHz nest)) for + I2C speed = ~1Mhz per Andreas Koenig. +</description> <simpleType> - <array>4</array> - <uint8_t></uint8_t> + <uint32_t> + <default>0x026</default> + </uint32_t> </simpleType> + <persistency>volatile</persistency> + <readable/> + <writeable/> </attribute> <attribute> + <id>PIB_I2C_REFCLOCK</id> <description> - Specifies a target's CEC degraded mode domain. For example, all - DIMMs are part of the DIMM CEC degraded mode domain. - </description> - <hasStringConversion></hasStringConversion> - <id>CDM_DOMAIN</id> - <persistency>non-volatile</persistency> - <readable></readable> + i2c reference clock for the system. + default is 0x4 => I2C speed = ~1Mhz per Andreas Koenig +</description> <simpleType> - <enumeration> - <id>CDM_DOMAIN</id> - </enumeration> + <uint32_t> + <default>0x4</default> + </uint32_t> </simpleType> + <persistency>volatile</persistency> + <readable/> + <writeable/> </attribute> <attribute> - <description>Designates the speed at which a given I2C bus should run. - Creator: MRW - Purpose: Used by FW to know the fastest possible bus speed that all of - the devices on a given bus are able to use. - Data Format: 4x13 array of uint16_t values. The first index indicates - the engine number of the bus. The second index indicates the port - number of the bus. The value in the array is the I2C bus speed - used for that engine/port combination in KHz. + <description> + Set to 1 by HWSV to indicate that attribute overrides exist in a PLCK IPL + (not an IPL by steps). This is read by Hostboot to determine if it needs + to request the attribute overrides from HWSV before starting its IPL. </description> - <id>I2C_BUS_SPEED_ARRAY</id> + <id>PLCK_IPL_ATTR_OVERRIDES_EXIST</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <array>4,13</array> - <uint16_t> - <default> - 0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0</default> - </uint16_t> + <uint8_t> + <default>0x00</default> + </uint8_t> </simpleType> + <writeable/> </attribute> + <enumerationType> + <description>Enumeration for the ATTR_PM_APSS_CHIP_SELECT</description> + <enumerator> + <name>NONE</name> + <value>0xFF</value> + </enumerator> + <enumerator> + <name>CS0</name> + <value>0x00</value> + </enumerator> + <enumerator> + <name>CS1</name> + <value>0x01</value> + </enumerator> + <id>PM_APSS_CHIP_SELECT</id> + </enumerationType> + <attribute> + <id>PM_PBAX_NODEID</id> <description> - Used to enable pause/stop in between isteps. This attribute is set via - attribute override. + DEPRECATED!!! Use PBAX_GROUPID instead + PROC_CHIP Attribute + Receive PBAX Nodeid. Value that indicates this PBA's PBAX Node affinity. + This is matched to pbax_nodeid of the PMISC Address phase. + + Provided by the Machine Readable Workbook. </description> - <id>ISTEP_PAUSE_ENABLE</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> <simpleType> - <uint8_t></uint8_t> + <uint8_t/> </simpleType> - <writeable></writeable> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> + <id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> <description> - Used to configure the parameters for enabling pause/stop between - isteps. This attribute is set via attribute override. + SYSTEM Attribute + Frequency (binary in MHz) for the point at which clock sector buffers + should be at full strength. This is to support Vmin operation. + Setting cannot overlap the Low or High bands. + + Provided by the Machine Readable Workbook after system characterization. </description> - <id>ISTEP_PAUSE_CONFIG</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> <simpleType> - <uint64_t></uint64_t> + <uint32_t/> </simpleType> - <writeable></writeable> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> + <id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> <description> - Setting to require(0x1) or not require(0x0) a functional TPM to - boot the system. + SYSTEM Attribute + Frequency (binary in MHz) for the lower end of the High Frequency + Resonant band + + Provided by the Machine Readable Workbook after system characterization. </description> - <id>TPM_REQUIRED</id> - <persistency>non-volatile</persistency> - <readable></readable> - <writeable></writeable> <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> + <uint32_t/> </simpleType> - <range> - <min>0</min> - <max>1</max> - </range> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> + <id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> <description> - This attribute represents the Maximum number of L2 Cache CEs allowed - during Manufacturing. - creator: platform (generated based on MRW data) + SYSTEM Attribute + Frequency (binary in MHz)) for the upper end of the High Frequency + Resonant band + + Provided by the Machine Readable Workbook after system characterization. </description> - <id>MNFG_TH_P8EX_L2_CACHE_CES</id> - <persistency>non-volatile</persistency> - <readable></readable> <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> + <uint32_t/> </simpleType> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> + <id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> <description> - This attribute represents the Maximum number of L2 Directory CEs allowed - during Manufacturing. - creator: platform (generated based on MRW data) + SYSTEM Attribute + Frequency (binary in MHz)) for the lower end of the Low Frequency + Resonant band + + Provided by the Machine Readable Workbook after system characterization. </description> - <id>MNFG_TH_P8EX_L2_DIR_CES</id> - <persistency>non-volatile</persistency> - <readable></readable> <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> + <uint32_t/> </simpleType> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> + <id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> <description> - This attribute represents the Maximum number of L3 Cache CEs allowed - during Manufacturing. - creator: platform (generated based on MRW data) + SYSTEM Attribute + Frequency (binary in MHz) for the upper end of the Low Frequency + Resonant band + + Provided by the Machine Readable Workbook after system characterization. </description> - <id>MNFG_TH_P8EX_L3_CACHE_CES</id> - <persistency>non-volatile</persistency> - <readable></readable> <simpleType> - <uint8_t> - <default>3</default> - </uint8_t> + <uint32_t/> </simpleType> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> + <id>PM_SAFE_FREQUENCY</id> <description> - This attribute represents the Maximum number of L3 Directory CEs allowed - during Manufacturing. - creator: platform (generated based on MRW data) + Frequency (binary in KHz) indicating the frequency that the cores will be moved + to in the event of the loss of the OCC Heartbeat. This value needs to be the maximum + of the DpoMin frequency for proper PowerBus operation and the PowerSave value for + the present part. + + Provided by the Machine Readable Workbook after system characterization. + + The value is translated to the Pstate space. + + Producer: Machine Readable Workbook + + Consumers: p8_build_gpstate_table.C + + DYNAMIC_ATTRIBUTE: ATTR_PM_SAFE_PSTATE </description> - <id>MNFG_TH_P8EX_L3_DIR_CES</id> - <persistency>non-volatile</persistency> - <readable></readable> <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> + <uint32_t/> </simpleType> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> + <id>PM_SLEEP_ENTRY</id> <description> - This attribute represents the Maximum number of L2 Line Deletes allowed - in the Field. - creator: platform (generated based on MRW data) + PROC_CHIP Attribute + +Set Assisted if power off serialization is needed and SLEEP_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency + +Producer: MRWB + +Consumer: proc_pm_init and proc_pcbs_init </description> - <id>FIELD_TH_P8EX_L2_LINE_DELETES</id> + <simpleType> + <uint8_t/> + </simpleType> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + </attribute> + + <attribute> + <id>PM_SLEEP_EXIT</id> + <description> + PROC_CHIP Attribute + +Set to Assisted if power on serialization is needed and SLEEP_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency +Must be set to Assisted if ATTR_PM_SLEEP_TYPE=Deep as this necessary for restore. + +Setting to Hardware is a test mode for Fast only. + +Producer: MRWB + +Consumer: proc_pm_init and proc_pcbs_init. + </description> <simpleType> - <uint8_t> - <default>6</default> - </uint8_t> + <uint8_t/> </simpleType> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> + <id>PM_SLEEP_TYPE</id> <description> - This attribute represents the Maximum number of L3 Line Deletes allowed - in the Field. - creator: platform (generated based on MRW data) + PROC_CHIP Attribute +Selects which voltage level to place the Core domain PFETs upon Sleep entry. 0 = Vret (Fast Sleep Mode), 1 = Voff (Deep Sleep Mode) + +Producer: MRWB + +Consumer: proc_pm_init and proc_pcbs_init </description> - <id>FIELD_TH_P8EX_L3_LINE_DELETES</id> + <simpleType> + <uint8_t/> + </simpleType> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + </attribute> + + <attribute> + <id>PM_SPIVID_FREQUENCY</id> + <description> + SYSTEM Attribute + SPI Clock Frequency (binary in MHz) + + Consumer: proc_pm_effective + + Produces ATTR_PM_SPIVID_CLOCK_DIVIDER + + Provided by the Machine Readable Workbook. + </description> <simpleType> - <uint8_t> - <default>6</default> - </uint8_t> + <uint32_t/> </simpleType> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> + <id>PM_SPIVID_PORT_ENABLE</id> <description> - This attribute represents the Maximum number of L2 Column Repairs allowed - in the Field. - creator: platform (generated based on MRW data) + PROC_CHIP Attribute + Defines the configuration of the SPIVID ports from the target. + - NONE means that no VRM is attached. + - PORTxNONRED means that the indicated port is used in a non-redundant + configuration. + - REDUNDANT means that all three are connected and considered redundant. + + Provided by the Machine Readable Workbook. </description> - <id>FIELD_TH_P8EX_L2_COL_REPAIRS</id> + <simpleType> + <uint8_t/> + </simpleType> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + </attribute> + + <attribute> + <id>PM_SPWUP_FSP</id> + <description> + EX_CHIPLET Attribute + </description> <simpleType> - <uint8_t> - <default>7</default> - </uint8_t> + <uint32_t/> </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> </attribute> <attribute> + <id>PM_SPWUP_OCC</id> <description> - This attribute represents the Maximum number of L3 Column Repairs allowed - in the Field. - creator: platform (generated based on MRW data) + EX_CHIPLET Attribute </description> - <id>FIELD_TH_P8EX_L3_COL_REPAIRS</id> - <persistency>non-volatile</persistency> - <readable></readable> <simpleType> - <uint8_t> - <default>7</default> - </uint8_t> + <uint32_t/> </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> </attribute> <attribute> + <id>PM_SPWUP_PHYP</id> <description> - This attribute represents the Maximum number of L2 Line Deletes allowed - during Manufacturing. - creator: platform (generated based on MRW data) + EX_CHIPLET Attribute </description> - <id>MNFG_TH_P8EX_L2_LINE_DELETES</id> + <simpleType> + <uint32_t/> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + </attribute> + + <attribute> + <id>PM_SYSTEM_IVRM_VPD_MIN_LEVEL</id> + <description>Version level of #M that represents the minimum for IVRM characterized parts. + If this value is non-zero and the #M version level is less than this value, IVRMs are disabled. + If the #M version is greater than or equal to this value, the IVRMs are allowed to be enable from a level of part perspective. + Producer: MRWB + Consumer: p8_build_pstate_datablock.C + </description> + <simpleType> + <uint8_t/> + </simpleType> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + </attribute> + + <attribute> + <id>PM_UNDERVOLTING_FREQ_MAXIMUM</id> + <description> + Override for Maximum frequency for which undervolting is allowed. + + If value = 0, the value of VPD Turbo data point is passed to OCC FW via + Pstate SuperStructure. + + If value != 0, this value will be passed to OCC FW via Pstate SuperStructure + as the ceiling frequency for enabled CPMs. + + Will be internally rounded to the nearest ATTR_PROC_REFCLK_FREQUENCY / 8 value. + + Consumer: OCC FW; OCC Lab Tools + + Provided by the Machine Readable Workbook. + </description> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint8_t/> </simpleType> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> + <id>PM_UNDERVOLTING_FRQ_MINIMUM</id> <description> - This attribute represents the Maximum number of L3 Line Deletes allowed - during Manufacturing. - creator: platform (generated based on MRW data) + Override for Minimum frequency for which undervolting is allowed. + + If value = 0, the value of VPD CPMin data point is passed to OCC FW via + Pstate SuperStructure. + + If value != 0, this value will be passed to OCC FW via Pstate SuperStructure + as the floor frequency for enabled CPMs. + + Will be internally rounded to the nearest ATTR_PROC_REFCLK_FREQUENCY / 8 value. + + Consumer: OCC FW; OCC Lab Tools + + Provided by the Machine Readable Workbook. </description> - <id>MNFG_TH_P8EX_L3_LINE_DELETES</id> + <simpleType> + <uint8_t/> + </simpleType> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + </attribute> + + <attribute> + <id>PM_WINKLE_ENTRY</id> + <description>Setting depends on di/dt charateristics of the system. + + Set Assisted if power off serialization is needed and WINKLE_TYPE=Fast; + Set to Hardware if the system can handle the unrelated powering off between cores. + Hardware setting decreases entry latency + + Producer: MRWB + + Consumer: p8_poreslw_init.C + </description> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint8_t/> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + </attribute> + + <attribute> + <id>PM_WINKLE_EXIT</id> + <description>Setting depends on di/dt charateristics of the system and the setting of ATTR_PM_WINKLE_TYPE. + + Set to Assisted if power on serialization is needed and WINKLE_TYPE=Fast; Set to Hardware if the system + can handle the unrelated powering off between cores. Hardware setting decreases entry latency. + Must be set to Assisted if ATTR_PM_WINKLE_TYPE=Deep as this necessary for restore. + + Setting to Hardware is a test mode for Fast only. + + Producer: MRWB + + Consumer: p8_poreslw_init.C + </description> + <simpleType> + <uint8_t/> </simpleType> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> + <id>PM_WINKLE_TYPE</id> <description> - This attribute represents the Maximum number of L2 Column Repairs allowed - during Manufacturing. - creator: platform (generated based on MRW data) + PROC_CHIP Attribute +Selects which voltage level to place the Core and ECO domain PFETs upon Winkle entry. 0 = Vret (Fast Winkle Mode), 1 = Voff (Deep Winkle Mode) </description> - <id>MNFG_TH_P8EX_L2_COL_REPAIRS</id> + <simpleType> + <uint8_t/> + </simpleType> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + </attribute> + + <attribute> + <description>Save state of the sfc driver flash workarounds for runtime</description> + <id>PNOR_FLASH_WORKAROUNDS</id> + <persistency>volatile-zeroed</persistency> + <readable/> <simpleType> - <uint8_t> + <uint32_t> <default>0</default> - </uint8_t> + </uint32_t> </simpleType> + <writeable/> </attribute> <attribute> - <description> - This attribute represents the Maximum number of L3 Column Repairs allowed - during Manufacturing. - creator: platform (generated based on MRW data) - </description> - <id>MNFG_TH_P8EX_L3_COL_REPAIRS</id> + <description>Position of target relative to node</description> + <id>POSITION</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t> + <uint16_t> <default>0</default> - </uint8_t> + </uint16_t> </simpleType> </attribute> <attribute> + <id>POS_ON_MEM_PORT</id> <description> - This attribute represents the Base threshold (for 2GB DRAM ) of - Memory CEs allowed during runtime. - creator: platform (generated based on MRW data) + Position of this DIMM on its memory port </description> - <id>MNFG_TH_CEN_MBA_RT_SOFT_CE_TH_ALGO</id> - <persistency>non-volatile</persistency> - <readable></readable> <simpleType> <uint8_t> - <default>2</default> + <default>0</default> </uint8_t> </simpleType> + <persistency>non-volatile</persistency> + <readable/> + </attribute> + + <attribute> + <description>Hierarchical path to the target with respect to power</description> + <id>POWER_PATH</id> + <nativeType> + <name>EntityPath</name> + </nativeType> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> + <id>PRD_HWP_PLID</id> <description> - This attribute represents the Base threshold (for 2GB DRAM ) of - Memory CEs allowed during IPL. - creator: platform (generated based on MRW data) + PRD will perform error isolation for certain errors that may cause a HWP + to fail. This attribute will be used by the HWP to store the PLID so that + PRD can subsequently check it for a non-zero value and link the HWP PLID + to the PRD error log. </description> - <id>MNFG_TH_CEN_MBA_IPL_SOFT_CE_TH_ALGO</id> - <persistency>non-volatile</persistency> - <readable></readable> <simpleType> - <uint8_t> - <default>2</default> - </uint8_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + </attribute> + + <attribute> + <complexType> + <description>Structure which defines a target's primary capabilities. + A target can only support at most FSI SCOM and one of the other two SCOM + types. Applicable for all targets. Structure is read-only. + </description> + <field> + <bits>1</bits> + <default>0</default> + <description>0b0: Target does not support FSI SCOM; + 0b1: Target supports FSI SCOM + </description> + <name>supportsFsiScom</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description>0b0: Target does not support XSCOM; + 0b1: Target supports FSI XSCOM</description> + <name>supportsXscom</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description>0b0: Target does not support inband SCOM</description> + <name>supportsInbandScom</name> + <type>uint8_t</type> + </field> + <field> + <bits>5</bits> + <default>0</default> + <description>Reserved for future use</description> + <name>reserved</name> + <type>uint8_t</type> + </field> + </complexType> + <description>Attribute which describes capabilities of a target</description> + <id>PRIMARY_CAPABILITIES</id> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> + <id>PROC_DCM_INSTALLED</id> <description> - This attribute represents the maximum number of Memory RCEs - allowed per Rank during runtime. - creator: platform (generated based on MRW data) + PROC_CHIP Attribute + If true, the chip is installed on a Dual Chip Module + Provided by the Machine Readable Workbook </description> - <id>MNFG_TH_CEN_MBA_RT_RCE_PER_RANK</id> - <persistency>non-volatile</persistency> - <readable></readable> <simpleType> - <uint8_t> - <default>2</default> - </uint8_t> + <uint8_t/> </simpleType> + <persistency>non-volatile</persistency> + <readable/> </attribute> - <attribute> + <enumerationType> + <description>Enumeration indicating the PROC_EPS_TABLE_TYPE</description> + <enumerator> + <name>EPS_TYPE_LE</name> + <value>1</value> + </enumerator> + <enumerator> + <name>EPS_TYPE_HE</name> + <value>2</value> + </enumerator> + <id>PROC_EPS_TABLE_TYPE</id> + </enumerationType> + + <enumerationType> <description> - This attribute represents the maximum number of L4 Cache CEs allowed. - creator: platform (generated based on MRW data) + Enumeration indicating the PROC_FABRIC_A_BUS_WIDTH </description> - <id>MNFG_TH_CEN_L4_CACHE_CES</id> + <enumerator> + <name>2_BYTE</name> + <value>1</value> + </enumerator> + <enumerator> + <name>4_BYTE</name> + <value>2</value> + </enumerator> + <id>PROC_FABRIC_A_BUS_WIDTH</id> + </enumerationType> + + <enumerationType> + <description> + Enumeration indicating the PROC_FABRIC_CAPI_MODE + </description> + <enumerator> + <name>OFF</name> + <value>0x0</value> + </enumerator> + <enumerator> + <name>ON</name> + <value>0x1</value> + </enumerator> + <id>PROC_FABRIC_CAPI_MODE</id> + </enumerationType> + + <enumerationType> + <description>Enumeration indicating the PROC_FABRIC_PUMP_MODE</description> + <enumerator> + <name>MODE1</name> + <value>1</value> + </enumerator> + <enumerator> + <name>MODE2</name> + <value>2</value> + </enumerator> + <id>PROC_FABRIC_PUMP_MODE</id> + </enumerationType> + + <enumerationType> + <description> + Enumeration indicating the PROC_FABRIC_SMP_OPTICS_MODE + </description> + <enumerator> + <name>OPTICS_IS_X_BUS</name> + <value>0x0</value> + </enumerator> + <enumerator> + <name>OPTICS_IS_A_BUS</name> + <value>0x1</value> + </enumerator> + <id>PROC_FABRIC_SMP_OPTICS_MODE</id> + </enumerationType> + + <enumerationType> + <description> + Enumeration indicating the PROC_FABRIC_X_BUS_WIDTH + </description> + <enumerator> + <name>2_BYTE</name> + <value>1</value> + </enumerator> + <enumerator> + <name>4_BYTE</name> + <value>2</value> + </enumerator> + <id>PROC_FABRIC_X_BUS_WIDTH</id> + </enumerationType> + + <attribute> + <description>Type of Master, ACTING_MASTER or MASTER_CANDIDATE or + NOT_MASTER</description> + <hasStringConversion/> + <id>PROC_MASTER_TYPE</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <uint8_t> - <default>2</default> + <default>NOT_MASTER</default> </uint8_t> </simpleType> + <writeable/> + <no_export/> </attribute> - <attribute> + <enumerationType> + <default>NOT_MASTER</default> <description> - With MNFG thresholds enabled, PRD will make a predictive callout when an - RCD parity error (recovery enabled) attention count is equal to this - value. A value of 0 defaults to the max threshold of 0xff. + Enumeration indicating the role of proc as master/alt_master/not_master </description> - <id>MNFG_TH_RCD_PARITY_ERRORS</id> - <persistency>non-volatile</persistency> - <readable></readable> + <enumerator> + <name>ACTING_MASTER</name> + <value>0</value> + </enumerator> + <enumerator> + <name>MASTER_CANDIDATE</name> + <value>1</value> + </enumerator> + <enumerator> + <name>NOT_MASTER</name> + <value>2</value> + </enumerator> + <id>PROC_MASTER_TYPE</id> + </enumerationType> + + <enumerationType> + <description>Enumeration indicating which _PBIEX_ASYNC_SEL should be use</description> + <enumerator> + <name>SEL0</name> + <value>0</value> + </enumerator> + <enumerator> + <name>SEL1</name> + <value>1</value> + </enumerator> + <enumerator> + <name>SEL2</name> + <value>2</value> + </enumerator> + <id>PROC_PBIEX_ASYNC_SEL</id> + </enumerationType> + + <attribute> + <id>PROC_PCIE_IOP_CONFIG</id> + <description>PCIE IOP lane configuration + creator: platform + consumer: proc_pcie_scominit + firmware notes: + Encoded PCIE IOP lane configuration + </description> <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> + <uint8_t/> </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> + <ignoreEkb/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_PCIE_IOP_CONFIG</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> + <id>PROC_PCIE_IOVALID_ENABLE</id> + <!-- TARGET_TYPE_PEC --> <description> - With MNFG thresholds enabled, PRD will make a predictive callout when a - memory intermittent UE attention count is equal to this value. A value of - 0 defaults to the max threshold of 0xff. + PCIE iovalid enable valid mask + creator: platform + consumer: p9_pcie_scominit </description> - <id>MNFG_TH_MEMORY_IUES</id> - <persistency>non-volatile</persistency> - <readable></readable> <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> + <uint8_t/> </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <ignoreEkb/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_PCIE_IOVALID_ENABLE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> - <description> - With MNFG thresholds enabled, PRD will make a predictive callout when a - memory intermittent MPE attention count is equal to this value. A value of - 0 defaults to the max threshold of 0xff. + <description>Indicates whether PCIE lanes terminate at a pluggable slot + Creator: MRW + Purpose: Used by FW to know whether the given PCIE lanes terminate at a + pluggable slot or not. If this is the case, and the platform + supports bifurcation, the card's VPD should be interrogated to + determine whether to bifurcate the IOP or not. + Data Format: x4 array of uint8_t values. The first value indicates + whether lane set 0 terminates at a pluggable slot. The + next three values indicate the same for lane sets 1-3. A value of + 1 at a given array index indicates the lanes terminate at a + pluggable slot, 0 otherwise. </description> - <id>MNFG_TH_MEMORY_IMPES</id> + <id>PROC_PCIE_IS_SLOT</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> + <array>4</array> + <uint8_t/> </simpleType> </attribute> <attribute> - <description> - The number of reconfig loops allowed due to RCD parity errors when - recovery is disabled. PRD will make a predictive callout and stop issuing - reconfigs due to RCD parity errors when RCD_PARITY_RECONFIG_LOOP_COUNT is - greater than this value. A value of 0 indicates that no reconfig loops are - allowed due to RCD parity errors. + <description>PCIE Lane Equalization values for each PHB + Creator: MRW + Purpose: Holds settings which are loaded into the HW to optimize the + PCIE lane signal eye between the chips + PCIE Gen3 endpoints + Data Format: 16 entries of 16 bytes of EQ data per PHB. Each PHB has an EQ + value for each of its 16 lanes. Each value is a uint16 formatted as + follows: + Bit 0:3 - up_rx_hint (bit 0 reserved) + Bit 4:7 - up_tx_preset + Bit 8:11 - dn_rx_hint (bit 0 reserved) + Bit 12:15 - dn_tx_preset </description> - <id>RCD_PARITY_RECONFIG_LOOPS_ALLOWED</id> + <id>PROC_PCIE_LANE_EQUALIZATION_GEN3</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> + <array>16</array> + <uint16_t> + <default> + 0x7777,0x7777,0x7777,0x7777, + 0x7777,0x7777,0x7777,0x7777, + 0x7777,0x7777,0x7777,0x7777, + 0x7777,0x7777,0x7777,0x7777 + </default> + </uint16_t> </simpleType> </attribute> <attribute> - <description> - PRD will increment this count and issue a reconfig loop each time an RCD - parity error (recovery disabled) is detected during Memory Diagnostics. - This value will be cleared at the end of Memory Diagnostics if it is able - to complete without the need to issue a reconfig loop. + <description>PCIE Lane Equalization values for each PHB + Creator: MRW + Purpose: Holds settings which are loaded into the HW to optimize the + PCIE lane signal eye between the chips + PCIE Gen4 endpoints + Data Format: 16 entries of 16 bytes of EQ data per PHB. Each PHB has an EQ + value for each of its 16 lanes. Each value is a uint16 formatted as + follows: + Bit 0:3 - up_rx_hint (bit 0 reserved) + Bit 4:7 - up_tx_preset + Bit 8:11 - dn_rx_hint (bit 0 reserved) + Bit 12:15 - dn_tx_preset </description> - <id>RCD_PARITY_RECONFIG_LOOP_COUNT</id> + <id>PROC_PCIE_LANE_EQUALIZATION_GEN4</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <array>16</array> + <uint16_t> + <default> + 0x7777,0x7777,0x7777,0x7777, + 0x7777,0x7777,0x7777,0x7777, + 0x7777,0x7777,0x7777,0x7777, + 0x7777,0x7777,0x7777,0x7777 + </default> + </uint16_t> </simpleType> - <writeable></writeable> </attribute> <attribute> - <description> - Used to tell if a resource is critical to perform an IPL. If this - attribute is set to 1 and the target is deconfigured, the IPL MUST - terminate. + <description>Effective PCIE Lane Mask + Creator: Firmware + Purpose: Holds the effective PCIE lane mask of each PEC after taking + into account any IOP bifurcations. If no IOP bifurcations present, + this is just the value of the PEC_PCIE_LANE_MASK_NON_BIFURCATED + attribute + Data Format: x4 array of uint16_t values. The uint16_t value is a + mask for lane 0, the next for lane 1 and so on until lane 3. + A lane set mask indicates which groups of lanes are assigned to an + IOP. For instance, lane set 0 value of 0xFFFF and lane set 1 value + of 0x0000 for PEC0 means PEC0 is a x16. Lane set 0 value of 0xFF00 + and lane set 1 value of 0x00FF for PEC0, means the IOP is bifurcated + into two x8s. </description> - <id>RESOURCE_IS_CRITICAL</id> + <id>PROC_PCIE_LANE_MASK</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <array>4</array> + <uint16_t/> </simpleType> + <writeable/> + <no_export/> </attribute> <attribute> - <description>LPC Bus address - MMIO consumed by PHYP</description> - <id>LPC_BUS_ADDR</id> - <persistency>volatile</persistency> - <readable></readable> - <writeable></writeable> + <id>PROC_PCIE_NUM_PEC</id> + <description> + creator: platform + Number of PCIe PEC units present on target + Nimbus: 3 + </description> <simpleType> - <uint64_t></uint64_t> + <uint8_t/> </simpleType> + <persistency>non-volatile</persistency> + <readable/> <no_export/> </attribute> <attribute> - <description>XIVE - Controller Bar address - MMIO consumed by PHYP + <id>PROC_PCIE_PCS_RX_LOFF_CONTROL</id> + <!-- TARGET_TYPE_PEC --> + <description> + PCS rx loff control + creator: platform + consumer: p9_pcie_scominit + firmware notes: + The value of rx loff control for PCS. + Array index: Configuration number + index 0~3 for CONFIG0~3 </description> - <id>XIVE_CONTROLLER_BAR_ADDR</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> - <writeable></writeable> <simpleType> - <uint64_t></uint64_t> + <uint16_t/> + <array>4</array> </simpleType> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> - <description>XIVE - Thread Management Bar address register 1 - MMIO consumed by HB/PHYP + <id>PROC_PCIE_PCS_RX_PHASE_ROTATOR_CNTL</id> + <!-- TARGET_TYPE_PEC --> + <description> + Value of PCS rx phase rotator control + creator: platform + consumer: p9_pcie_scominit </description> - <id>XIVE_THREAD_MGMT1_BAR_ADDR</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> - <writeable></writeable> <simpleType> - <uint64_t></uint64_t> + <uint16_t/> </simpleType> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> - <description>PSIHB - ESB space address - MMIO consumed by PHYP + <id>PROC_PCIE_PCS_RX_SIGDET_CNTL</id> + <!-- TARGET_TYPE_PEC --> + <description> + Value of PCS rx sigdet control + creator: platform + consumer: p9_pcie_scominit </description> - <id>PSI_HB_ESB_ADDR</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> - <writeable></writeable> <simpleType> - <uint64_t></uint64_t> + <uint16_t/> </simpleType> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> + <id>PROC_PCIE_PCS_RX_VGA_CONTRL_REGISTER3</id> + <!-- TARGET_TYPE_PEC --> <description> - If not loading PHYP or OPAL, then use this to - decide whether to use FUSED cores or NOT. + PCS rx vga control register3 + creator: platform + consumer: p9_pcie_scominit + firmware notes: + The value of rx vga control register3. + Array index: Configuration number + index 0~3 for CONFIG0~3 </description> - <id>FUSED_CORE_OPTION</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> <simpleType> - <uint8_t></uint8_t> + <uint16_t/> + <array>4</array> </simpleType> - <writeable></writeable> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> - <description>Icache Line Size in bytes</description> - <id>ICACHE_LINE_SIZE</id> + <id>PROC_PCIE_PCS_SYSTEM_CNTL</id> + <description> + Value of PCS system control + creator: platform + consumer: p9_pcie_scominit + </description> + <simpleType> + <uint16_t/> + </simpleType> + <!-- @fixme --> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + <writeable/> + <ignoreEkb/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_PCIE_PCS_SYSTEM_CNTL</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> + </attribute> + + <attribute> + <id>PROC_PCIE_PCS_TX_FIFO_CONFIG_OFFSET</id> + <!-- TARGET_TYPE_PEC --> + <description> + Value of PCS tx fifo config offset + creator: platform + consumer: p9_pcie_scominit + </description> <simpleType> - <uint32_t></uint32_t> + <uint8_t/> </simpleType> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> - <description>ICache Block Size in bytes</description> - <id>ICACHE_BLOCK_SIZE</id> + <id>PROC_PCIE_PHB_ACTIVE</id> + <description>PCIE PHB valid mask + creator: platform + consumer: proc_pcie_scominit + firmware notes: + Bit mask defining set of active/valid PHBs + bit0=PHB0, bit1=PHB1, bit2=PHB2, bit3=PHB3 + </description> + <simpleType> + <uint8_t/> + </simpleType> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + <writeable/> + </attribute> + + <attribute> + <id>PROC_PCIE_REFCLOCK_ENABLE</id> + <description>PCIE refclock enable valid mask + PCIE refclock enable valid mask + creator: platform + consumer: p9_pcie_scominit + </description> <simpleType> - <uint32_t></uint32_t> + <uint8_t/> </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <ignoreEkb/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_PCIE_REFCLOCK_ENABLE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> - <description>ICache Size in KB</description> - <id>ICACHE_SIZE</id> + <id>PROC_REFCLOCK_RCVR_TERM</id> + <description> + Defines system specific value of processor refclock receiver termination (FSI GP4 bits 8:9) + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> <persistency>non-volatile</persistency> - <readable></readable> + <hasStringConversion/> + <readable/> + </attribute> + + <enumerationType> + <description>Enumeration indicating which chip should be used as the PROC_SELECT_BOOT_MASTER</description> + <enumerator> + <name>PRIMARY</name> + <value>1</value> + </enumerator> + <enumerator> + <name>SECONDARY</name> + <value>2</value> + </enumerator> + <id>PROC_SELECT_BOOT_MASTER</id> + </enumerationType> + + <enumerationType> + <description>Enumeration indicating which SEEPROM image should be used to boot a processor</description> + <enumerator> + <name>FIRST</name> + <value>1</value> + </enumerator> + <enumerator> + <name>SECOND</name> + <value>2</value> + </enumerator> + <id>PROC_SELECT_BOOT_SEEPROM_IMAGE</id> + </enumerationType> + + <attribute> + <id>PROC_SELECT_BOOT_SEEPROM_IMAGE</id> + <description> + Specifies which SEEPROM image should be used to boot a processor + FIRST - the first image was selected + SECOND - the second image was selected + </description> <simpleType> - <uint32_t></uint32_t> + <uint8_t> + <default>1</default> + </uint8_t> </simpleType> + <persistency>volatile</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_SELECT_BOOT_SEEPROM_IMAGE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> + <enumerationType> + <description>Enumeration indicating which SEEPROM image should be used for the boot master</description> + <enumerator> + <name>FIRST</name> + <value>1</value> + </enumerator> + <enumerator> + <name>SECOND</name> + <value>2</value> + </enumerator> + <id>PROC_SELECT_SEEPROM_IMAGE</id> + </enumerationType> + <attribute> - <description>ICache Assoc Sets</description> - <id>ICACHE_ASSOC_SETS</id> - <persistency>non-volatile</persistency> - <readable></readable> + <id>PROC_SELECT_SEEPROM_IMAGE</id> + <description> + Specifies which SEEPROM image should be used for the boot master. + FIRST - the first image was selected + SECOND - the second image was selected + Platforms are expected to set this to FIRST in normal operation + </description> <simpleType> - <uint32_t></uint32_t> + <uint8_t> + <default>1</default> + </uint8_t> </simpleType> + <persistency>volatile</persistency> + <readable/> + <writeable/> </attribute> <attribute> - <description>DCache Line Size in bytes</description> - <id>DCACHE_LINE_SIZE</id> - <persistency>non-volatile</persistency> - <readable></readable> + <description>Base Address of PSI Bridge Logic</description> + <id>PSI_BRIDGE_BASE_ADDR</id> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> <simpleType> - <uint32_t></uint32_t> + <uint64_t> + <default>0xFFFFFFFFFFFFFFFF</default> + </uint64_t> </simpleType> + <hwpfToHbAttrMap> + <id>ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> - <description>DCache Associative Sets</description> - <id>DCACHE_ASSOC_SETS</id> - <persistency>non-volatile</persistency> - <readable></readable> + <description>PSIHB - ESB space address - MMIO consumed by PHYP + </description> + <id>PSI_HB_ESB_ADDR</id> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> <simpleType> - <uint32_t></uint32_t> + <uint64_t/> </simpleType> </attribute> <attribute> - <description>L2 Cache Line Size in bytes</description> - <id>L2_CACHE_LINE_SIZE</id> - <persistency>non-volatile</persistency> - <readable></readable> + <description> + Raw value of system MTM + </description> + <id>RAW_MTM</id> + <persistency>volatile-zeroed</persistency> + <readable/> <simpleType> - <uint32_t></uint32_t> + <string> + <sizeInclNull>64</sizeInclNull> + </string> </simpleType> + <writeable/> </attribute> <attribute> - <description>L2 Cache Size in KB</description> - <id>L2_CACHE_SIZE</id> + <description> + The number of reconfig loops allowed due to RCD parity errors when + recovery is disabled. PRD will make a predictive callout and stop issuing + reconfigs due to RCD parity errors when RCD_PARITY_RECONFIG_LOOP_COUNT is + greater than this value. A value of 0 indicates that no reconfig loops are + allowed due to RCD parity errors. + </description> + <id>RCD_PARITY_RECONFIG_LOOPS_ALLOWED</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t></uint32_t> + <uint8_t> + <default>1</default> + </uint8_t> </simpleType> </attribute> <attribute> - <description>L2 Cache Assoc Sets</description> - <id>L2_CACHE_ASSOC_SETS</id> + <description> + PRD will increment this count and issue a reconfig loop each time an RCD + parity error (recovery disabled) is detected during Memory Diagnostics. + This value will be cleared at the end of Memory Diagnostics if it is able + to complete without the need to issue a reconfig loop. + </description> + <id>RCD_PARITY_RECONFIG_LOOP_COUNT</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t></uint32_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> + <writeable/> </attribute> + <enumerationType> + <description>Enumeration of RECONFIGURE_LOOP flags</description> + <enumerator> + <description> + Indicates HW has been deconfigured + </description> + <name>DECONFIGURE</name> + <value>0x01</value> + </enumerator> + <enumerator> + <description> + Indicates a bad DQ bit was set in the BadDqBitmap + </description> + <name>BAD_DQ_BIT_SET</name> + <value>0x02</value> + </enumerator> + <enumerator> + <description> + An RCD parity error has been detected + </description> + <name>RCD_PARITY_ERROR</name> + <value>0x04</value> + </enumerator> + <id>RECONFIGURE_LOOP</id> + </enumerationType> + <attribute> - <description>L3 Cache Line Size in bytes</description> - <id>L3_CACHE_LINE_SIZE</id> - <persistency>non-volatile</persistency> - <readable></readable> + <description> System attribute array that defines the reconfig loop test cases + consumer: istep dispatcher reconfigLoopTestRunner function + This array is loaded with data via attribute override. The attribute is + then read and then overlayed onto a test case structure. + </description> + <id>RECONFIG_LOOP_TESTS</id> + <persistency>volatile-zeroed</persistency> + <readable/> <simpleType> - <uint32_t></uint32_t> + <array>5</array> + <uint64_t/> </simpleType> + <writeable/> </attribute> <attribute> - <description>L3 Cache Size in KB</description> - <id>L3_CACHE_SIZE</id> - <persistency>non-volatile</persistency> - <readable></readable> + <description> + Indicates whether reconfigure loop tests are enabled. + This attribute is set via attribute override + </description> + <id>RECONFIG_LOOP_TESTS_ENABLE</id> + <persistency>volatile-zeroed</persistency> + <readable/> <simpleType> - <uint32_t></uint32_t> + <uint8_t/> </simpleType> + <writeable/> </attribute> <attribute> - <description>Time Base frequency in MHZ</description> - <id>TIME_BASE</id> + <id>REDUNDANT_CLOCKS</id> + <description> + 1 = System has redundant clock oscillators + 0 = System does not have redundant clock oscillators + From the Machine Readable Workbook + </description> + <simpleType> + <uint8_t/> + </simpleType> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + </attribute> + + <attribute> + <id>REL_POS</id> + <description> + Logical position of this unit/dimm relative to its immediate parent + </description> <simpleType> - <uint32_t> - <default>0x800000</default> - </uint32_t> + <uint8_t> + <default>0xFF</default> + </uint8_t> </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <ignoreEkb/> + <no_export/> + <hwpfToHbAttrMap> + <id>ATTR_REL_POS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> - <description>TLB Data Entries</description> - <id>TLB_DATA_ENTRIES</id> + <description> + Used to tell if a resource is critical to perform an IPL. If this + attribute is set to 1 and the target is deconfigured, the IPL MUST + terminate. + </description> + <id>RESOURCE_IS_CRITICAL</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t></uint32_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> </attribute> <attribute> - <description>TLB Data Associative Sets</description> - <id>TLB_DATA_ASSOC_SETS</id> + <description>Size of RNG IO Region</description> + <id>RNG_BAR_SIZE</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t></uint32_t> + <uint64_t> + <default>0x000000000001000</default> + </uint64_t> </simpleType> </attribute> <attribute> - <description>TLB Instruction Entries</description> - <id>TLB_INSTR_ENTRIES</id> + <description>Base Address of RNG IO Region</description> + <id>RNG_BASE_ADDR</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t></uint32_t> + <uint64_t> + <default>0xFFFFFFFFFFFFFFFF</default> + </uint64_t> </simpleType> + <hwpfToHbAttrMap> + <id>ATTR_PROC_NX_MMIO_BAR_BASE_ADDR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> - <description>TLB Instruction Associative Sets</description> - <id>TLB_INSTR_ASSOC_SETS</id> + <description> + Policy indicating whether to perform the maximum amount of memory + pattern testing possible or not. + Set to 0x01 to perform the maximum amount of memory pattern testing + possible. + Set to 0x00 to perform the default amount of memory pattern testing. + </description> + <id>RUN_MAX_MEM_PATTERNS</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t></uint32_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> + <writeable/> </attribute> <attribute> - <description>Reserve Size in bytes</description> - <id>TLB_RESERVE_SIZE</id> - <persistency>non-volatile</persistency> - <readable></readable> + <id>SBE_COMMIT_ID</id> + <description> + A hexadecimal value of the commit ID associated + with the SBE. + </description> <simpleType> - <uint32_t></uint32_t> + <uint32_t/> </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> </attribute> <attribute> - <description>L1 Data Cache Size in KB</description> - <id>DATA_CACHE_SIZE</id> - <persistency>non-volatile</persistency> - <readable></readable> + <id>SBE_IS_STARTED</id> + <description> + If 0, SBE for the processor has not been started. + Otherwise, SBE for the processor has been started. + </description> <simpleType> - <uint32_t></uint32_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> </attribute> <attribute> - <description>L1 Data Cache Line Size in bytes</description> - <id>DATA_CACHE_LINE_SIZE</id> - <persistency>non-volatile</persistency> - <readable></readable> + <id>SBE_RELEASE_TAG</id> + <description> + An ascii value of the SBE release tag + </description> <simpleType> - <uint32_t></uint32_t> + <string> + <default/> + <sizeInclNull>21</sizeInclNull> + </string> </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> </attribute> <attribute> - <description>Thread Count</description> - <id>THREAD_COUNT</id> - <persistency>non-volatile</persistency> - <readable></readable> + <id>SBE_UPDATE_DISABLE</id> + <description> + Control execution of updateProcessorSbeSeeproms() + + if 0, enable SBE update of processor SEEPROM + if 1, disable SBE update of processor SEEPROM + + Consumer: sbe_update.C + + Default: 0 + </description> <simpleType> - <uint32_t> - <default>0x4</default> - </uint32_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> + <id>SBE_VERSION_INFO</id> <description> - Number of internal data pointers we have in - the hostboot reserved memory section. + A hexadecimal value of the major and minor + version of the SBE. The major info is in the + first 16 bits followed by the minor. + 0:15: Major Version + 16:31: Minor Version </description> - <id>HDAT_RSV_MEM_NUM_SECTIONS</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> <simpleType> - <uint32_t></uint32_t> + <uint32_t/> </simpleType> - <writeable></writeable> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + </attribute> + + <attribute> + <complexType> + <description>Structure which defines which SCOM to use at a point in + time. Only applicable if target supports one or more SCOM types. Only + one bit (of the first three) can ever be set at any one time. + </description> + <field> + <bits>1</bits> + <default>0</default> + <description>0b0: Do not use FSI SCOM at this time. 0b1: Use FSI + SCOM at this time</description> + <name>useFsiScom</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description>0b0: Do not use XSCOM at this time. 0b1: Use XSCOM at + this time</description> + <name>useXscom</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description>0b0: Do not use inband SCOM at this time. 0b1: Use + inband SCOM at this time</description> + <name>useInbandScom</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description>0b0: Do not use SBE SCOM at this time. 0b1: Use + SBE SCOM at this time</description> + <name>useSbeScom</name> + <type>uint8_t</type> + </field> + <field> + <bits>4</bits> + <default>0</default> + <description>Reserved for future expansion</description> + <name>reserved</name> + <type>uint8_t</type> + </field> + </complexType> + <description>Attribute storing information about which SCOM path to use</description> + <id>SCOM_SWITCHES</id> + <persistency>volatile</persistency> + <readable/> + <writeable/> </attribute> <attribute> + <id>SECUREBOOT_PROTECT_DECONFIGURED_TPM</id> <description> - Number of internal data pointers we have in - the hostboot runtime data section. + To deconfigure a TPM in a secure system - 01 to set TDP bit </description> - <id>HDAT_HBRT_NUM_SECTIONS</id> + <simpleType> + <uint8_t/> + </simpleType> <persistency>volatile-zeroed</persistency> - <readable></readable> + <readable/> + <writeable/> + <ignoreEkb/> + <hwpfToHbAttrMap> + <id>ATTR_SECUREBOOT_PROTECT_DECONFIGURED_TPM</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> + </attribute> + + <attribute> + <id>SLOT_INDEX</id> + <description>PCIe slot index definition</description> + <simpleType> + <uint8_t/> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <no_export/> + </attribute> + + <attribute> + <id>SLOT_NAME</id> + <description>PCIe slot name definition</description> <simpleType> - <uint32_t></uint32_t> + <uint8_t/> </simpleType> - <writeable></writeable> + <persistency>non-volatile</persistency> + <readable/> + <no_export/> </attribute> <attribute> + <id>SOCKET_POWER_NOMINAL</id> <description> - Biggest size for any of the hostboot - runtime data sections. + The socket power in nominal mode. + Controls how much power can be used. + This is the same for all cores in the system. + Data is provided by MVPD #V. </description> - <id>HDAT_HBRT_SECTION_SIZE</id> + <simpleType> + <uint32_t/> + </simpleType> <persistency>volatile-zeroed</persistency> - <readable></readable> + <readable/> + <writeable/> + </attribute> + + <attribute> + <id>SOCKET_POWER_TURBO</id> + <description> + The socket power in turbo mode. + Controls how much power can be used. + This is the same for all cores in the system. + Data is provided by MVPD #V. + </description> <simpleType> - <array>9</array> - <uint64_t></uint64_t> + <uint32_t/> </simpleType> - <writeable></writeable> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> </attribute> <attribute> + <complexType> + <description>Structure which defines a system's SP functions. + Applicable for System target only. Structure is read-only. + </description> + <field> + <bits>1</bits> + <default>1</default> + <description> + If this flag is set then mailboxEnabled MUST also be set + + 0b0: SP does not support for VPD, payload, ATTR sync, VDDR, TOD; + 0b1: SP supports VPD, payload, ATTR sync, VDDR, TOD + </description> + <name>baseServices</name> + <type>uint32_t</type> + </field> + <field> + <bits>1</bits> + <default>1</default> + <description> + 0b0: SP does not initialize FSI slave logic, Hostboot must; + 0b1: SP does initialize FSI slave logic so Hostboot should not + </description> + <name>fsiSlaveInit</name> + <type>uint32_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description> + 0b0: There is no SP mailbox support; + 0b1: There is SP mailbox support + </description> + <name>mailboxEnabled</name> + <type>uint32_t</type> + </field> + <field> + <bits>1</bits> + <default>1</default> + <description> + 0b0: SP does not initialize FSI master logic, Hostboot must; + 0b1: SP does initialize FSI master logic so Hostboot should not + </description> + <name>fsiMasterInit</name> + <type>uint32_t</type> + </field> + <field> + <bits>1</bits> + <default>1</default> + <description> + 0b0: SP does not perform hardware change detection, Hostboot must; + 0b1: SP does perform hardware change detection (HCDB) so Hostboot should not + </description> + <name>hardwareChangeDetection</name> + <type>uint32_t</type> + </field> + <field> + <bits>1</bits> + <default>1</default> + <description> + 0b0: SP does not perform Power Line Disturbance (PLD) detection, Hostboot must; + 0b1: SP does perform Power Line Disturbance (PLD) detection so Hostboot should not + </description> + <name>powerLineDisturbance</name> + <type>uint32_t</type> + </field> + <field> + <bits>26</bits> + <default>0</default> + <description>Reserved for future use</description> + <name>reserved</name> + <type>uint32_t</type> + </field> + </complexType> <description> - System control to set the power limit for Workload Optimized - Frequency (WOF) algorithms. This is used to select the - proper VFRT tables. - Producer: TMGT - Consumers: FW that selects VFRT tables + Attribute which describes what the SP is or is not doing in this system </description> - <id>WOF_POWER_LIMIT</id> + <id>SP_FUNCTIONS</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + </attribute> + + <attribute> + <id>START_MEM_ADDRESS_FOR_PAYLOAD_TCE_TOKEN</id> + <description> + Specifies the starting memory address that corresponds to the TCE Token + used by the FSP to transfer the PAYLOAD into system memory. + If 0xFFFFFFFFFFFFFFFF, then invalid; otherwise, valid. + </description> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint64_t> + <default>0xFFFFFFFFFFFFFFFF</default> + </uint64_t> </simpleType> - <writeable></writeable> + <persistency>volatile</persistency> + <readable/> + <writeable/> </attribute> <attribute> - <description>The address offset which each Chiplet types pervasive - address space used to represent the a chiplet. - 0x00 to 0x0F => For P9 all non-core and non-cache chiplets - 0x10 to 0x1F => All Cache Chiplets - 0x20 to 0x37 => All Core Chiplets - 0x38 to 0x3F => Multicast Operation - </description> - <id>CHIPLET_ID</id> - <persistency>non-volatile</persistency> - <readable></readable> + <id>STOP5_DISABLE</id> + <description> Control CME response to execution of PowerPC STOP instruction + if OFF, treat STOP5 as STOP5 + if ON, treat STOP5 as STOP4 + + Producer: ??? + + Consumer: p8_hcode_image_build.C + + Platform default: OFF + </description> <simpleType> <uint8_t> - <default>0xFF</default> + <default>0</default> </uint8_t> </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_STOP5_DISABLE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> - <attribute> + <enumerationType> + <default>NA</default> <description> - Physical entity path of the target's associated pervasive target + Enumeration indication which Hot Plug Controllers are supported by + the current system. </description> - <id>PARENT_PERVASIVE</id> - <nativeType> - <name>EntityPath</name> - </nativeType> + <enumerator> + <name>NA</name> + <value>0</value> + </enumerator> + <enumerator> + <name>MAX5961</name> + <value>0x01</value> + </enumerator> + <enumerator> + <name>PCA9551</name> + <value>0x02</value> + </enumerator> + <id>SUPPORTED_HOT_PLUG</id> + </enumerationType> + + <attribute> + <description> + STOP levels supported at runtime (sent to Host via HDAT): + Bit 0: STOP0 Supported - Quiesce thread only + Bit 1: STOP1 Supported - P8 Nap + Bit 2: STOP2 Supported - P8 Fast Sleep + Bit 3: STOP3 Supported - P8 Fast Sleep using iVRMs + Bit 4: STOP4 supported - P8 Deep Sleep + Bit 5: STOP5 Supported - WOF-friendly "Instant on" + Bit 6,7: Reserved + Bit 8: STOP8 supported - Half Quad Sleep + Bit 9: STOP9 supported - P8 Fast Winkle + Bit 10: Reserved + Bit 11: STOP11 supported - P8 Deep Winkle + Bit 12-15 : Reserved + Bits 16..31 - Reserved + </description> + <id>SUPPORTED_STOP_STATES</id> <persistency>non-volatile</persistency> - <readable></readable> - <virtual></virtual> - <no_export/> + <readable/> + <simpleType> + <uint32_t> + <default>0xEC100000</default> + </uint32_t> + </simpleType> </attribute> <attribute> @@ -4515,7 +7047,7 @@ </description> <id>SUPPORTS_DYNAMIC_MEM_VOLT</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <uint8_t> <default>0</default> @@ -4524,17 +7056,32 @@ </attribute> <attribute> + <id>SYNC_BETWEEN_STEPS</id> + <description> + Attribute to enable targetting attribute sync when in istep mode. + 1 = sync will occur following each substep when ipl'ing in single step mode + 0 = sync will not be done after each step + </description> + <simpleType> + <uint8_t/> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + </attribute> + + <attribute> <description> - This field is of the form "vendor,name" where the name indicates + This field is of the form "vendor,name" where the name indicates the family of the systems. The textual portion of the string has a maximum length of 63 characters to accommodate a terminating NULL. Both vendor and name fields are lower case US ASCII. No special - characters other than ",", "-", and "+" as described below should + characters other than ",", "-", and "+" as described below should be used in the string. </description> <id>SYSTEM_FAMILY</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <string> <default>ibm,p9</default> @@ -4549,16 +7096,16 @@ a type of system within the System Family. The textual portion of the string has a maximum length of 63 characters to accommodate a terminating NULL. Both vendor and name fields are lower case US - ASCII. No special characters other than ",", "-", and "+" as described + ASCII. No special characters other than ",", "-", and "+" as described below should be used in the string. If identification of specific - models within a system type is desired, "-model" should be appended - to the end of the name. The "-model" portion is optional and could be + models within a system type is desired, "-model" should be appended + to the end of the name. The "-model" portion is optional and could be used to identify the packaging, specific model numbers, etc. NOTE: No Hostboot code should ever key off of this value. </description> <id>SYSTEM_TYPE</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <string> <default>ibm,miscopenpower</default> @@ -4568,234 +7115,412 @@ </attribute> <attribute> - <description>TOD CHIP DATA for each CHIP - The size of the TOD CHIP DATA must be equal to the sizeof(TodChipData) - </description> - <id>TOD_CPU_DATA</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> + <id>TCE_START_TOKEN_FOR_HDAT</id> + <description> + Specifies which TCE Token the FSP should start with to transfer the + HDAT section into system memory. + If 0xFFFFFFFF, then invalid; otherwise, valid. + </description> <simpleType> - <array>44</array> - <uint8_t></uint8_t> + <uint32_t> + <default>0xFFFFFFFF</default> + </uint32_t> </simpleType> - <writeable></writeable> + <persistency>volatile</persistency> + <readable/> + <writeable/> </attribute> <attribute> + <id>TCE_START_TOKEN_FOR_PAYLOAD</id> <description> - STOP levels supported at runtime (sent to Host via HDAT): - Bit 0: STOP0 Supported - Quiesce thread only - Bit 1: STOP1 Supported - P8 Nap - Bit 2: STOP2 Supported - P8 Fast Sleep - Bit 3: STOP3 Supported - P8 Fast Sleep using iVRMs - Bit 4: STOP4 supported - P8 Deep Sleep - Bit 5: STOP5 Supported - WOF-friendly "Instant on" - Bit 6,7: Reserved - Bit 8: STOP8 supported - Half Quad Sleep - Bit 9: STOP9 supported - P8 Fast Winkle - Bit 10: Reserved - Bit 11: STOP11 supported - P8 Deep Winkle - Bit 12-15 : Reserved - Bits 16..31 - Reserved + Specifies which TCE Token the FSP should start with to transfer the + PAYLOAD into system memory. + If 0xFFFFFFFF, then invalid; otherwise, valid. </description> - <id>SUPPORTED_STOP_STATES</id> - <persistency>non-volatile</persistency> - <readable></readable> <simpleType> <uint32_t> - <default>0xEC100000</default> + <default>0xFFFFFFFF</default> </uint32_t> </simpleType> + <persistency>volatile</persistency> + <readable/> + <writeable/> </attribute> <attribute> - <description>PCIE Lane Equalization values for each PHB - Creator: MRW - Purpose: Holds settings which are loaded into the HW to optimize the - PCIE lane signal eye between the chips + PCIE Gen3 endpoints - Data Format: 16 entries of 16 bytes of EQ data per PHB. Each PHB has an EQ - value for each of its 16 lanes. Each value is a uint16 formatted as - follows: - Bit 0:3 - up_rx_hint (bit 0 reserved) - Bit 4:7 - up_tx_preset - Bit 8:11 - dn_rx_hint (bit 0 reserved) - Bit 12:15 - dn_tx_preset - </description> - <id>PROC_PCIE_LANE_EQUALIZATION_GEN3</id> + <complexType> + <description>Structure to define the addressing for an I2C + slave device.</description> + <field> + <default>physical:sys-0</default> + <description>Entity path to the chip that contains the I2C + master</description> + <name>i2cMasterPath</name> + <type>EntityPath</type> + </field> + <field> + <default>0x80</default> + <description>I2C master engine. This is a 2-bit + value.</description> + <name>engine</name> + <type>uint8_t</type> + </field> + <field> + <default>0x80</default> + <description>Port from the I2C Master device. This is a 6-bit + value.</description> + <name>port</name> + <type>uint8_t</type> + </field> + <field> + <default>0x80</default> + <description>Device address on the I2C bus. This is a 7-bit value, + but then shifted 1 bit left.</description> + <name>devAddr</name> + <type>uint8_t</type> + </field> + </complexType> + <description>Information needed to address an I2C slave device</description> + <id>TEMP_SENSOR_I2C_CONFIG</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> + </attribute> + + <attribute> + <description>Test attribute; largest string possible given size</description> + <id>TEST_MAX_STRING</id> + <persistency>volatile</persistency> + <readable/> <simpleType> - <array>16</array> - <uint16_t> - <default> - 0x7777,0x7777,0x7777,0x7777, - 0x7777,0x7777,0x7777,0x7777, - 0x7777,0x7777,0x7777,0x7777, - 0x7777,0x7777,0x7777,0x7777 - </default> - </uint16_t> + <string> + <default>abc</default> + <sizeInclNull>4</sizeInclNull> + </string> </simpleType> + <writeable/> </attribute> <attribute> - <description>PCIE Lane Equalization values for each PHB - Creator: MRW - Purpose: Holds settings which are loaded into the HW to optimize the - PCIE lane signal eye between the chips + PCIE Gen4 endpoints - Data Format: 16 entries of 16 bytes of EQ data per PHB. Each PHB has an EQ - value for each of its 16 lanes. Each value is a uint16 formatted as - follows: - Bit 0:3 - up_rx_hint (bit 0 reserved) - Bit 4:7 - up_tx_preset - Bit 8:11 - dn_rx_hint (bit 0 reserved) - Bit 12:15 - dn_tx_preset - </description> - <id>PROC_PCIE_LANE_EQUALIZATION_GEN4</id> + <description>Test attribute; smallest string possible given size</description> + <id>TEST_MIN_STRING</id> + <persistency>volatile</persistency> + <readable/> + <simpleType> + <string> + <default>a</default> + <sizeInclNull>10</sizeInclNull> + </string> + </simpleType> + <writeable/> + </attribute> + + <attribute> + <description>Attribute to test signed attribute + functionality in the system</description> + <id>TEST_NEGATIVE_FCN</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <array>16</array> - <uint16_t> - <default> - 0x7777,0x7777,0x7777,0x7777, - 0x7777,0x7777,0x7777,0x7777, - 0x7777,0x7777,0x7777,0x7777, - 0x7777,0x7777,0x7777,0x7777 - </default> - </uint16_t> + <int8_t> + <default>-6</default> + </int8_t> </simpleType> + <writeable/> </attribute> <attribute> - <description>Ordinal ID of a target</description> - <id>ORDINAL_ID</id> + <description>Test attribute; string with no default supplied</description> + <id>TEST_NO_DEFAULT_STRING</id> + <persistency>volatile</persistency> + <readable/> + <simpleType> + <string> + <sizeInclNull>10</sizeInclNull> + </string> + </simpleType> + <writeable/> + </attribute> + + <attribute> + <description>Test attribute; string with empty default value</description> + <id>TEST_NULL_STRING</id> + <persistency>volatile</persistency> + <readable/> + <simpleType> + <string> + <default/> + <sizeInclNull>10</sizeInclNull> + </string> + </simpleType> + <writeable/> + </attribute> + + <attribute> + <description>Thread Count</description> + <id>THREAD_COUNT</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> <uint32_t> - <default>0xFFFFFFFF</default> + <default>0x4</default> </uint32_t> </simpleType> - <writeable></writeable> - <no_export/> </attribute> <attribute> - <description> - Raw value of system MTM - </description> - <id>RAW_MTM</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> + <description>Time Base frequency in MHZ</description> + <id>TIME_BASE</id> + <persistency>non-volatile</persistency> + <readable/> <simpleType> - <string> - <sizeInclNull>64</sizeInclNull> - </string> + <uint32_t> + <default>0x800000</default> + </uint32_t> </simpleType> - <writeable></writeable> </attribute> <attribute> - <description> - Used to tell INTRP code whether to use the XIVE HW Reset - or a software based reset. - 0 = Software based reset - 1 = XIVE HW reset - </description> - <id>XIVE_HW_RESET</id> + <description>TLB Data Associative Sets</description> + <id>TLB_DATA_ASSOC_SETS</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint32_t/> </simpleType> </attribute> <attribute> - <description> - Used to tell I2C code whether to run - I2C Engine 2 Port 0 in diag mode or not - 0 = Use Diag Mode - 1 = Disable Diag Mode - </description> - <id>DISABLE_I2C_ENGINE2_PORT0_DIAG_MODE</id> + <description>TLB Data Entries</description> + <id>TLB_DATA_ENTRIES</id> <persistency>non-volatile</persistency> - <readable></readable> + <readable/> <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> + <uint32_t/> </simpleType> </attribute> <attribute> - <description>Save state of the sfc driver flash workarounds for runtime</description> - <id>PNOR_FLASH_WORKAROUNDS</id> + <description>TLB Instruction Associative Sets</description> + <id>TLB_INSTR_ASSOC_SETS</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint32_t/> + </simpleType> + </attribute> + + <attribute> + <description>TLB Instruction Entries</description> + <id>TLB_INSTR_ENTRIES</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint32_t/> + </simpleType> + </attribute> + + <attribute> + <description>Reserve Size in bytes</description> + <id>TLB_RESERVE_SIZE</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <uint32_t/> + </simpleType> + </attribute> + + <attribute> + <description>TOD CHIP DATA for each CHIP + The size of the TOD CHIP DATA must be equal to the sizeof(TodChipData) + </description> + <id>TOD_CPU_DATA</id> <persistency>volatile-zeroed</persistency> - <readable></readable> + <readable/> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <array>44</array> + <uint8_t/> + </simpleType> + <writeable/> + </attribute> + + <attribute> + <description> + Bitmask indicating what role this chip has in tod topology + </description> + <id>TOD_ROLE</id> + <persistency>volatile-zeroed</persistency> + <readable/> + <simpleType> + <uint8_t/> </simpleType> - <writeable></writeable> + <writeable/> </attribute> <enumerationType> - <default>NA</default> - <description>Enumeration indicating the target's class</description> + <default>NON_MASTER</default> + <description> + Enumeration indicating what role this chip has in tod topology + </description> <enumerator> - <name>NA</name> + <name>NON_MASTER</name> <value>0</value> </enumerator> <enumerator> - <name>CARD</name> + <name>PRIMARY</name> <value>1</value> </enumerator> <enumerator> - <name>ENC</name> + <name>SECONDARY</name> <value>2</value> </enumerator> - <enumerator> - <name>CHIP</name> - <value>3</value> - </enumerator> - <enumerator> - <name>UNIT</name> - <value>4</value> - </enumerator> - <enumerator> - <name>DEV</name> - <value>5</value> - </enumerator> - <enumerator> - <name>SYS</name> - <value>6</value> - </enumerator> - <enumerator> - <name>LOGICAL_CARD</name> - <value>7</value> - </enumerator> - <enumerator> - <name>BATTERY</name> - <value>8</value> - </enumerator> - <enumerator> - <name>LED</name> - <value>9</value> - </enumerator> - <enumerator> - <name>SP</name> - <value>10</value> - </enumerator> - <enumerator> - <name>MAX</name> - <value>11</value> - </enumerator> - <id>CLASS</id> + <id>TOD_ROLE</id> </enumerationType> + <attribute> + <complexType> + <description>Structure to define the addressing for an I2C + TPM.</description> + <field> + <default>0x0</default> + <description>Boolean indicating whether this TPM is available + in the system</description> + <name>tpmEnabled</name> + <type>uint8_t</type> + </field> + <field> + <default>physical:sys-0</default> + <description>Entity path to the chip that contains the I2C + master</description> + <name>i2cMasterPath</name> + <type>EntityPath</type> + </field> + <field> + <default>0x01</default> + <description>Port from the I2C Master device. This is a 6-bit + value.</description> + <name>port</name> + <type>uint8_t</type> + </field> + <field> + <default>0xAE</default> + <description>Device address on the I2C bus for Locality 0. + This is a 7-bit value, but then shifted 1 + bit left.</description> + <name>devAddrLocality0</name> + <type>uint8_t</type> + </field> + <field> + <default>0xA8</default> + <description>Device address on the I2C bus for Locality 1. + This is a 7-bit value, but then shifted 1 + bit left.</description> + <name>devAddrLocality1</name> + <type>uint8_t</type> + </field> + <field> + <default>0xAA</default> + <description>Device address on the I2C bus for Locality 2. + This is a 7-bit value, but then shifted 1 + bit left.</description> + <name>devAddrLocality2</name> + <type>uint8_t</type> + </field> + <field> + <default>0xA4</default> + <description>Device address on the I2C bus for Locality 3. + This is a 7-bit value, but then shifted 1 + bit left.</description> + <name>devAddrLocality3</name> + <type>uint8_t</type> + </field> + <field> + <default>0xA6</default> + <description>Device address on the I2C bus for Locality 4. + This is a 7-bit value, but then shifted 1 + bit left.</description> + <name>devAddrLocality4</name> + <type>uint8_t</type> + </field> + <field> + <default>0x00</default> + <description>I2C master engine. This is a 2-bit + value.</description> + <name>engine</name> + <type>uint8_t</type> + </field> + <field> + <default>0x01</default> + <description>The number of bytes a device requires to set its + internal address/offset.</description> + <name>byteAddrOffset</name> + <type>uint8_t</type> + </field> + </complexType> + <description>Information needed to address the TPM slaves</description> + <id>TPM_INFO</id> + <persistency>non-volatile</persistency> + <readable/> + </attribute> + + <attribute> + <description> + Setting to require(0x1) or not require(0x0) a functional TPM to + boot the system. + </description> + <id>TPM_REQUIRED</id> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> + <simpleType> + <uint8_t> + <default>1</default> + </uint8_t> + </simpleType> + <range> + <min>0</min> + <max>1</max> + </range> + </attribute> + + <attribute> + <id>TPM_UNUSABLE</id> + <description> + Indicates whether the TPM is unusable. Hostboot should not read this + value for any purpose other than tracing. This value should only be + written to when there is a certainty that the TPM is not usable. + This attribute is consumed by FSP during alignment check to determine + the optimal boot configuration. This attribute can be removed if TPM + gard is ever supported. + </description> + <range> + <min>0</min> + <max>1</max> + </range> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> + <no_export/> + </attribute> + + <attribute> + <description>Attribute indicating the target's type</description> + <hasStringConversion/> + <id>TYPE</id> + <persistency>non-volatile</persistency> + <readable/> + <simpleType> + <enumeration> + <id>TYPE</id> + </enumeration> + </simpleType> + </attribute> + <enumerationType> <default>NA</default> <description>Enumeration indicating the target's type</description> @@ -5056,1767 +7781,232 @@ <value>65</value> </enumerator> <enumerator> - <name>OBUS_BRICK</name> - <value>66</value> - </enumerator> - <enumerator> - <name>NPU</name> - <value>67</value> - </enumerator> - <enumerator> - <name>MC</name> - <value>68</value> - </enumerator> - <enumerator> - <name>TEST_FAIL</name> - <value>69</value> - </enumerator> - <enumerator> - <name>MFREFCLK</name> - <value>70</value> - </enumerator> - <enumerator> - <name>SMPGROUP</name> - <value>71</value> - </enumerator> - <enumerator> - <name>OMI</name> - <value>72</value> - </enumerator> - <enumerator> - <name>MCC</name> - <value>73</value> - </enumerator> - <enumerator> - <name>OMIC</name> - <value>74</value> - </enumerator> - <enumerator> - <name>OCMB_CHIP</name> - <value>75</value> - </enumerator> <enumerator> - <name>MEM_PORT</name> - <value>76</value> - </enumerator> - <enumerator> - <name>LAST_IN_RANGE</name> - <value>77</value> - </enumerator> - <id>TYPE</id> - </enumerationType> - - <enumerationType> - <default>NA</default> - <description>Enumeration indicating the target's model</description> - <enumerator> - <name>NA</name> - <value>0</value> - </enumerator> - <enumerator> - <name>RESERVED</name> - <value>16</value> - </enumerator> - <enumerator> - <name>VENICE</name> - </enumerator> - <enumerator> - <name>MURANO</name> - </enumerator> - <enumerator> - <name>NAPLES</name> - </enumerator> - <enumerator> - <name>NIMBUS</name> - </enumerator> - <enumerator> - <name>CUMULUS</name> - </enumerator> - <enumerator> - <name>AXONE</name> - </enumerator> - <enumerator> - <name>CENTAUR</name> - <value>48</value> - </enumerator> - <enumerator> - <name>EXPLORER</name> - </enumerator> - <enumerator> - <name>JEDEC</name> - <value>80</value> - </enumerator> - <enumerator> - <name>CDIMM</name> - </enumerator> - <enumerator> - <name>POWER8</name> - <value>112</value> - </enumerator> - <enumerator> - <name>POWER9</name> - <value>144</value> - </enumerator> - <enumerator> - <name>CECTPM</name> - </enumerator> - <enumerator> - <name>BMC</name> - </enumerator> - <enumerator> - <name>AST2500</name> - </enumerator> - <id>MODEL</id> - </enumerationType> - - <enumerationType> - <default>NA</default> - <description>Enumeration indicating the target's engine type</description> - <enumerator> - <name>NA</name> - <value>0</value> - </enumerator> - <enumerator> - <name>ENGINE_IIC</name> - <value>1</value> - </enumerator> - <enumerator> - <name>ENGINE_SCOM</name> - <value>2</value> - </enumerator> - <id>ENGINE_TYPE</id> - </enumerationType> - - <enumerationType> - <default>NO_MASTER</default> - <description>Enumeration indicating the master's FSI type</description> - <enumerator> - <name>MFSI</name> - <value>0</value> - </enumerator> - <enumerator> - <name>CMFSI</name> - <value>1</value> - </enumerator> - <enumerator> - <name>NO_MASTER</name> - <value>2</value> - </enumerator> - <id>FSI_MASTER_TYPE</id> - </enumerationType> - - <enumerationType> - <description>Enumeration indicating the services that are concerned - with target changes (ie, via HCDB change). - The values can be combined using a bitwise 'OR'. - </description> - <enumerator> - <name>GARD</name> - <value>0x00000001</value> - </enumerator> - <enumerator> - <name>MEMDIAG</name> - <value>0x00000002</value> - </enumerator> - <enumerator> - <name>PSIDIAG</name> - <value>0x00000004</value> - </enumerator> - <enumerator> - <name>DIAG_MASK</name> - <value>0x00000006</value> - </enumerator> - <enumerator> - <name>HOSTSVC_HBEL</name> - <value>0x00000008</value> - </enumerator> - <enumerator> - <name>RESRC_RECOV</name> - <value>0x00000010</value> - </enumerator> - <enumerator> - <name>GARD_APPLIED</name> - <value>0x00000020</value> - </enumerator> - <id>HWAS_CHANGED_BIT</id> - </enumerationType> - - <enumerationType> - <description>Enumeration indicating the PROC_EPS_TABLE_TYPE</description> - <enumerator> - <name>EPS_TYPE_LE</name> - <value>1</value> - </enumerator> - <enumerator> - <name>EPS_TYPE_HE</name> - <value>2</value> - </enumerator> - <id>PROC_EPS_TABLE_TYPE</id> - </enumerationType> - - <enumerationType> - <description>Enumeration indicating the PROC_FABRIC_PUMP_MODE</description> - <enumerator> - <name>MODE1</name> - <value>1</value> - </enumerator> - <enumerator> - <name>MODE2</name> - <value>2</value> - </enumerator> - <id>PROC_FABRIC_PUMP_MODE</id> - </enumerationType> - - <enumerationType> - <default>UNKNOWN</default> - <description> - Enumeration indicating what kind of payload is to be started - </description> - <enumerator> - <name>UNKNOWN</name> - <value>0</value> - </enumerator> - <enumerator> - <name>PHYP</name> - <value>1</value> - </enumerator> - <enumerator> - <name>SAPPHIRE</name> - <value>2</value> - </enumerator> - <enumerator> - <name>NONE</name> - <value>3</value> - </enumerator> - <id>PAYLOAD_KIND</id> - </enumerationType> - - <enumerationType> - <id>MNFG_FLAG</id> - <description>Enumeration indicating the mnfg flags - that are set by the user. The values can be - combined using a bitwise 'OR'. The values will - need to be kept in sync with the FAPI - enumerator values. Also the enumeration type - is used by the ATTR_MNFG_FLAGS attribute. Should - note that the MNFG_FLAG values are of type uint32_t - </description> - <enumerator> - <!-- Use default mfg error thresholds and reporting values --> - <name>THRESHOLDS</name> - <value>0x00000001</value> - </enumerator> - <enumerator> - <!-- Enable AVP execution --> - <name>AVP_ENABLE</name> - <value>0x00000002</value> - </enumerator> - <enumerator> - <!-- Enable HDAT AVPs** --> - <name>HDAT_AVP_ENABLE</name> - <value>0x00000004</value> - </enumerator> - <enumerator> - <!-- All SRCs are terminating (CEC hardware/procedural) --> - <name>SRC_TERM</name> - <value>0x00000008</value> - </enumerator> - <enumerator> - <!-- Enable IPL memory diagnostics to report memory CE --> - <name>IPL_MEMORY_CE_CHECKING</name> - <value>0x00000010</value> - </enumerator> - <enumerator> - <!-- Enable Fast Background Scrub --> - <name>FAST_BACKGROUND_SCRUB</name> - <value>0x00000020</value> - </enumerator> - <enumerator> - <!-- Test DRAM Repairs --> - <name>TEST_DRAM_REPAIRS</name> - <value>0x00000040</value> - </enumerator> - <enumerator> - <!-- Disable Dram Repairs --> - <name>DISABLE_DRAM_REPAIRS</name> - <value>0x00000080</value> - </enumerator> - <enumerator> - <!-- Enable exhaustive pattern test --> - <name>ENABLE_EXHAUSTIVE_PATTERN_TEST</name> - <value>0x00000100</value> - </enumerator> - <enumerator> - <!-- Enable standard pattern test --> - <name>ENABLE_STANDARD_PATTERN_TEST</name> - <value>0x00000200</value> - </enumerator> - <enumerator> - <!-- Enable minimum pattern test --> - <name>ENABLE_MINIMUM_PATTERN_TEST</name> - <value>0x00000400</value> - </enumerator> - <enumerator> - <!-- Disable Fabric eRepair --> - <name>DISABLE_FABRIC_eREPAIR</name> - <value>0x00000800</value> - </enumerator> - <enumerator> - <!-- Disable Memory eRepair --> - <name>DISABLE_MEMORY_eREPAIR</name> - <value>0x00001000</value> - </enumerator> - <enumerator> - <!-- Fabric deploy lane spares --> - <name>FABRIC_DEPLOY_LANE_SPARES</name> - <value>0x00002000</value> - </enumerator> - <enumerator> - <!-- DMI deploy lane spares --> - <name>DMI_DEPLOY_LANE_SPARES</name> - <value>0x00004000</value> - </enumerator> - <enumerator> - <!-- Forcibly run PSI diagnostics --> - <name>PSI_DIAGNOSTIC</name> - <value>0x00008000</value> - </enumerator> - <enumerator> - <!-- Brazos Wrap Config --> - <name>BRAZOS_WRAP_CONFIG</name> - <value>0x00010000</value> - </enumerator> - <enumerator> - <!-- FSP is responsible for updating Processor SBE Image --> - <name>FSP_UPDATE_SBE_IMAGE</name> - <value>0x00020000</value> - </enumerator> - <enumerator> - <!-- Update both sides of SBE Image if update is needed --> - <name>UPDATE_BOTH_SIDES_OF_SBE</name> - <value>0x00040000</value> - </enumerator> - <enumerator> - <!-- Update both sides of SBE Image if update is needed --> - <name>IMMEDIATE_HALT</name> - <value>0x00080000</value> - </enumerator> -</enumerationType> - - <enumerationType> - <description>Enumeration indicating the BAR size - used with ATTR_PROC_NPU_MMIO_BAR_SIZE</description> - <enumerator> - <name>2_MB</name> - <value>0x0000000000200000</value> - </enumerator> - <enumerator> - <name>1_MB</name> - <value>0x0000000000100000</value> - </enumerator> - <enumerator> - <name>512_KB</name> - <value>0x0000000000080000</value> - </enumerator> - <enumerator> - <name>256_KB</name> - <value>0x0000000000040000</value> - </enumerator> - <enumerator> - <name>128_KB</name> - <value>0x0000000000020000</value> - </enumerator> - <enumerator> - <name>64_KB</name> - <value>0x0000000000010000</value> - </enumerator> - <id>NPU_MMIO_BAR_SIZE</id> - </enumerationType> - - <enumerationType> - <description>Enumeration indicating which chip should be used as the PROC_SELECT_BOOT_MASTER</description> - <enumerator> - <name>PRIMARY</name> - <value>1</value> - </enumerator> - <enumerator> - <name>SECONDARY</name> - <value>2</value> - </enumerator> - <id>PROC_SELECT_BOOT_MASTER</id> - </enumerationType> - - <enumerationType> - <description>Enumeration indicating which SEEPROM image should be used for the boot master</description> - <enumerator> - <name>FIRST</name> - <value>1</value> - </enumerator> - <enumerator> - <name>SECOND</name> - <value>2</value> - </enumerator> - <id>PROC_SELECT_SEEPROM_IMAGE</id> - </enumerationType> - - <enumerationType> - <description>Enumeration indicating which SEEPROM image should be used to boot a processor</description> - <enumerator> - <name>FIRST</name> - <value>1</value> - </enumerator> - <enumerator> - <name>SECOND</name> - <value>2</value> - </enumerator> - <id>PROC_SELECT_BOOT_SEEPROM_IMAGE</id> - </enumerationType> - - <enumerationType> - <description>Enumeration indicating which _PBIEX_ASYNC_SEL should be use</description> - <enumerator> - <name>SEL0</name> - <value>0</value> - </enumerator> - <enumerator> - <name>SEL1</name> - <value>1</value> - </enumerator> - <enumerator> - <name>SEL2</name> - <value>2</value> - </enumerator> - <id>PROC_PBIEX_ASYNC_SEL</id> - </enumerationType> - - <enumerationType> - <description>Enumeration of CDM_POLICIES flags</description> - <enumerator> - <description> - MFG_Guard policy: - Used in MFG only to prevent and disable the following: - . Storing or creation of new Guard records from Diagno`stic or other - faults through error logs. This is all domains, CEC - processor/memory, VPD, FSP, etc. - . Storing or creation of Manual Guard record from user. - NOTE: this does not stop FCO. - . Using an already stored System or Manual Guard record from - deconfiguring resources. This is all domains, CEC - processor/memory, VPD, FSP, etc. - </description> - <name>MANUFACTURING_DISABLED</name> - <value>0x01</value> - </enumerator> - <enumerator> - <description> - Predictive_Guard policy: - Used in Field or development to prevent and disable the following: - . Storing or creation of new Guard records from diagnostics or other - faults through error logs with the error_type of Predictive. - . Using an already stored System Guard record with error_type of - Predictive from deconfiguring resources. - </description> - <name>PREDICTIVE_DISABLED</name> - <value>0x02</value> - </enumerator> - <id>CDM_POLICIES</id> - </enumerationType> - - <enumerationType> - <description>Enumeration indicating the multi scome - buffer size. The values can be combined using a - bitwise 'OR'. The values will need to be kept - in sync with the FAPI enumerator values. Also - the enumeration type is used by the - ATTR_MULTI_SCOM_BUFFER_MAX_SIZE. Should - note that the MULTI_SCOM_BUFFER_MAX_SIZE values - are of type uint32_t - </description> - <enumerator> - <name>MULTI_SCOM_BUFFER_SIZE_1KB</name> - <value>0x00000400</value> - </enumerator> - <enumerator> - <name>MULTI_SCOM_BUFFER_SIZE_2KB</name> - <value>0x00000800</value> - </enumerator> - <enumerator> - <name>MULTI_SCOM_BUFFER_SIZE_4KB</name> - <value>0x00001000</value> - </enumerator> - <enumerator> - <name>MULTI_SCOM_BUFFER_SIZE_8KB</name> - <value>0x00002000</value> - </enumerator> - <enumerator> - <name>MULTI_SCOM_BUFFER_SIZE_16KB</name> - <value>0x00004000</value> - </enumerator> - <enumerator> - <name>MULTI_SCOM_BUFFER_SIZE_32KB</name> - <value>0x00008000</value> - </enumerator> - <enumerator> - <name>MULTI_SCOM_BUFFER_SIZE_64KB</name> - <value>0x00010000</value> - </enumerator> - <enumerator> - <name>MULTI_SCOM_BUFFER_SIZE_128KB</name> - <value>0x00020000</value> - </enumerator> - <enumerator> - <name>MULTI_SCOM_BUFFER_SIZE_256KB</name> - <value>0x00040000</value> - </enumerator> - <enumerator> - <name>MULTI_SCOM_BUFFER_SIZE_512KB</name> - <value>0x00080000</value> - </enumerator> - <enumerator> - <name>MULTI_SCOM_BUFFER_SIZE_1MB</name> - <value>0x00100000</value> - </enumerator> - <id>MULTI_SCOM_BUFFER_MAX_SIZE_BIT</id> - </enumerationType> - - <enumerationType> - <default>NOT_MASTER</default> - <description> - Enumeration indicating the role of proc as master/alt_master/not_master - </description> - <enumerator> - <name>ACTING_MASTER</name> - <value>0</value> - </enumerator> - <enumerator> - <name>MASTER_CANDIDATE</name> - <value>1</value> + <name>OBUS_BRICK</name> + <value>66</value> </enumerator> <enumerator> - <name>NOT_MASTER</name> - <value>2</value> + <name>NPU</name> + <value>67</value> </enumerator> - <id>PROC_MASTER_TYPE</id> - </enumerationType> - - <enumerationType> - <description>Enumeration of RECONFIGURE_LOOP flags</description> <enumerator> - <description> - Indicates HW has been deconfigured - </description> - <name>DECONFIGURE</name> - <value>0x01</value> + <name>MC</name> + <value>68</value> </enumerator> <enumerator> - <description> - Indicates a bad DQ bit was set in the BadDqBitmap - </description> - <name>BAD_DQ_BIT_SET</name> - <value>0x02</value> + <name>TEST_FAIL</name> + <value>69</value> </enumerator> <enumerator> - <description> - An RCD parity error has been detected - </description> - <name>RCD_PARITY_ERROR</name> - <value>0x04</value> + <name>MFREFCLK</name> + <value>70</value> </enumerator> - <id>RECONFIGURE_LOOP</id> - </enumerationType> - - <enumerationType> - <default>NON_MASTER</default> - <description> - Enumeration indicating what role this chip has in tod topology - </description> <enumerator> - <name>NON_MASTER</name> - <value>0</value> + <name>SMPGROUP</name> + <value>71</value> </enumerator> <enumerator> - <name>PRIMARY</name> - <value>1</value> + <name>OMI</name> + <value>72</value> </enumerator> <enumerator> - <name>SECONDARY</name> - <value>2</value> + <name>MCC</name> + <value>73</value> </enumerator> - <id>TOD_ROLE</id> - </enumerationType> - - <enumerationType> - <default>OFF</default> - <description> - Enumeration defining the type of power control requested - </description> <enumerator> - <name>OFF</name> - <value>0</value> + <name>OMIC</name> + <value>74</value> </enumerator> <enumerator> - <name>POWER_DOWN</name> - <value>1</value> + <name>OCMB_CHIP</name> + <value>75</value> </enumerator> <enumerator> - <name>STR</name> - <value>2</value> + <name>MEM_PORT</name> + <value>76</value> </enumerator> <enumerator> - <name>PD_AND_STR</name> - <value>3</value> + <name>LAST_IN_RANGE</name> + <value>77</value> </enumerator> - <id>MSS_MRW_POWER_CONTROL_REQUESTED</id> - </enumerationType> - - <enumerationType> - <default>NONE</default> - <description> - Enumeration defining the type of power control requested - </description> - <enumerator> - <name>OFF</name> - <value>0</value> - </enumerator> - <enumerator> - <name>POWER_DOWN</name> - <value>1</value> - </enumerator> - <enumerator> - <name>STR</name> - <value>2</value> - </enumerator> - <enumerator> - <name>PD_AND_STR</name> - <value>3</value> - </enumerator> - <id>MSS_MRW_IDLE_POWER_CONTROL_REQUESTED</id> - </enumerationType> - - <enumerationType> - <default>NONE</default> - <description> - Enumeration specifying a target's CEC degraded mode domain - </description> - <enumerator> - <name>NONE</name> - <value>0</value> - </enumerator> - <enumerator> - <name>CPU</name> - <value>1</value> - </enumerator> - <enumerator> - <name>DIMM</name> - <value>2</value> - </enumerator> - <enumerator> - <name>FABRIC</name> - <value>3</value> - </enumerator> - <enumerator> - <name>MEM</name> - <value>4</value> - </enumerator> - <enumerator> - <name>IO</name> - <value>5</value> - </enumerator> - <enumerator> - <name>NODE</name> - <value>6</value> - </enumerator> - <enumerator> - <name>CLOCK</name> - <value>7</value> - </enumerator> - <enumerator> - <name>PSI</name> - <value>8</value> - </enumerator> - <enumerator> - <name>FSP</name> - <value>9</value> - </enumerator> - <enumerator> - <name>ALL</name> - <value>10</value> - </enumerator> - <id>CDM_DOMAIN</id> - </enumerationType> - - <enumerationType> - <default>NA</default> - <description> - Enumeration indication which Hot Plug Controllers are supported by - the current system. - </description> - <enumerator> - <name>NA</name> - <value>0</value> - </enumerator> - <enumerator> - <name>MAX5961</name> - <value>0x01</value> - </enumerator> - <enumerator> - <name>PCA9551</name> - <value>0x02</value> - </enumerator> - <id>SUPPORTED_HOT_PLUG</id> - </enumerationType> - - <enumerationType> - <description>Enum for FUSED_CORE_OPTION</description> - <enumerator> - <name>USING_DEFAULT_CORES</name> - <value>0</value> - </enumerator> - <enumerator> - <name>USING_NORMAL_CORES</name> - <value>1</value> - </enumerator> - <enumerator> - <name>USING_FUSED_CORES</name> - <value>2</value> - </enumerator> - <id>FUSED_CORE_OPTION</id> - </enumerationType> - - <enumerationType> - <description>Enumeration for the ATTR_PM_APSS_CHIP_SELECT</description> - <enumerator> - <name>NONE</name> - <value>0xFF</value> - </enumerator> - <enumerator> - <name>CS0</name> - <value>0x00</value> - </enumerator> - <enumerator> - <name>CS1</name> - <value>0x01</value> - </enumerator> - <id>PM_APSS_CHIP_SELECT</id> - </enumerationType> - - <enumerationType> - <description>Enumeration to select WOF Power Limit</description> - <enumerator> - <name>NOMINAL</name> - <value>0</value> - </enumerator> - <enumerator> - <name>TURBO</name> - <value>1</value> - </enumerator> - <id>WOF_POWER_LIMIT</id> - </enumerationType> - - <enumerationType> - <description> - Enumeration indicating the OFF setting for the core and cache chiplet - DD PFET controllers - </description> - <enumerator> - <name>NOOFF</name> - <value>0</value> - </enumerator> - <enumerator> - <name>ALLBUT1TO7OFF</name> - <value>1</value> - </enumerator> - <enumerator> - <name>ALLBUT2TO7OFF</name> - <value>2</value> - </enumerator> - <enumerator> - <name>ALLBUT3TO7OFF</name> - <value>3</value> - </enumerator> - <enumerator> - <name>ALLBUT4TO7OFF</name> - <value>4</value> - </enumerator> - <enumerator> - <name>ALLBUT5TO7OFF</name> - <value>5</value> - </enumerator> - <enumerator> - <name>ALLBUT6TO7OFF</name> - <value>6</value> - </enumerator> - <enumerator> - <name>ALLBUT7TO7OFF</name> - <value>7</value> - </enumerator> - <enumerator> - <name>ALLOFF</name> - <value>8</value> - </enumerator> - <id>PFET_VDD_VOFF_SEL</id> - </enumerationType> - - <enumerationType> - <description> - Enumeration indicating the OFF setting for the core and cache chiplet - VCS PFET controllers - </description> - <enumerator> - <name>NOOFF</name> - <value>0</value> - </enumerator> - <enumerator> - <name>ALLBUT1TO7OFF</name> - <value>1</value> - </enumerator> - <enumerator> - <name>ALLBUT2TO7OFF</name> - <value>2</value> - </enumerator> - <enumerator> - <name>ALLBUT3TO7OFF</name> - <value>3</value> - </enumerator> - <enumerator> - <name>ALLBUT4TO7OFF</name> - <value>4</value> - </enumerator> - <enumerator> - <name>ALLBUT5TO7OFF</name> - <value>5</value> - </enumerator> - <enumerator> - <name>ALLBUT6TO7OFF</name> - <value>6</value> - </enumerator> - <enumerator> - <name>ALLBUT7TO7OFF</name> - <value>7</value> - </enumerator> - <enumerator> - <name>ALLOFF</name> - <value>8</value> - </enumerator> - <id>PFET_VCS_VOFF_SEL</id> - </enumerationType> - - <enumerationType> - <default>NA</default> - <description>Enumeration defining special FAPI_POS values</description> - <enumerator> - <name>NA</name> - <value>0xFFFFFFFF</value> - </enumerator> - <id>FAPI_POS</id> - </enumerationType> - - <enumerationType> - <description> - Enumeration indicating the PROC_FABRIC_A_BUS_WIDTH - </description> - <enumerator> - <name>2_BYTE</name> - <value>1</value> - </enumerator> - <enumerator> - <name>4_BYTE</name> - <value>2</value> - </enumerator> - <id>PROC_FABRIC_A_BUS_WIDTH</id> - </enumerationType> - - <enumerationType> - <description> - Enumeration indicating the PROC_FABRIC_X_BUS_WIDTH - </description> - <enumerator> - <name>2_BYTE</name> - <value>1</value> - </enumerator> - <enumerator> - <name>4_BYTE</name> - <value>2</value> - </enumerator> - <id>PROC_FABRIC_X_BUS_WIDTH</id> - </enumerationType> - - <enumerationType> - <description> - Enumeration indicating the PROC_FABRIC_SMP_OPTICS_MODE - </description> - <enumerator> - <name>OPTICS_IS_X_BUS</name> - <value>0x0</value> - </enumerator> - <enumerator> - <name>OPTICS_IS_A_BUS</name> - <value>0x1</value> - </enumerator> - <id>PROC_FABRIC_SMP_OPTICS_MODE</id> - </enumerationType> - - <enumerationType> - <description> - Enumeration indicating the PROC_FABRIC_CAPI_MODE - </description> - <enumerator> - <name>OFF</name> - <value>0x0</value> - </enumerator> - <enumerator> - <name>ON</name> - <value>0x1</value> - </enumerator> - <id>PROC_FABRIC_CAPI_MODE</id> - </enumerationType> - - <enumerationType> - <description>Enumeration for Voltage Drop Monitor enable</description> - <enumerator> - <name>OFF</name> - <value>0x00</value> - </enumerator> - <enumerator> - <name>ON</name> - <value>0x01</value> - </enumerator> - <id>VDM_ENABLE</id> - </enumerationType> - - <enumerationType> - <description>Enumeration for Temperature refresh mode</description> - <enumerator> - <name>DISABLE</name> - <value>0</value> - </enumerator> - <enumerator> - <name>ENABLE</name> - <value>1</value> - </enumerator> - <id>MSS_MRW_TEMP_REFRESH_MODE</id> - </enumerationType> - - <enumerationType> - <description>Pulled from the MRW, this describes the device - type to the HDAT. This is for I2C devices only. - </description> - <enumerator> - <name>9551</name> - <value>0x1</value> - </enumerator> - <enumerator> - <name>955X</name> <!-- deprecated --> - <value>0x1</value> - </enumerator> - <enumerator> - <name>SEEPROM</name> <!-- deprecated --> - <value>0x2</value> - </enumerator> - <enumerator> - <name>SEEPROM_Atmel28c128</name> - <value>0x2</value> - </enumerator> - <enumerator> - <name>NUVOTON_TPM</name> - <value>0x3</value> - </enumerator> - <enumerator> - <name>MEX_FPGA</name> - <value>0x4</value> - </enumerator> - <enumerator> - <name>UCX90XX</name> - <value>0x5</value> - </enumerator> - <enumerator> - <name>NVLINK</name> <!-- deprecated --> - <value>0x6</value> - </enumerator> - <enumerator> - <name>9552</name> - <value>0x6</value> - </enumerator> - <enumerator> - <name>9553</name> - <value>0x7</value> - </enumerator> - <enumerator> - <name>9554</name> - <value>0x8</value> - </enumerator> - <enumerator> - <name>9555</name> - <value>0x9</value> - </enumerator> - <enumerator> - <name>SMP_or_OpenCAPI_Cable</name> - <value>0xA</value> - </enumerator> - <enumerator> - <name>SEEPROM_Atmel28c256</name> - <value>0xB</value> - </enumerator> - <enumerator> - <name>UNKNOWN</name> - <value>0xFF</value> - </enumerator> - <id>HDAT_I2C_DEVICE_TYPE</id> - </enumerationType> - - <enumerationType> - <description>Pulled from the MRW, this describes the device - purpose to the HDAT. This is for I2C devices only. - </description> - <enumerator> - <name>CABLE_CARD_PRES</name> - <value>0x1</value> - </enumerator> - <enumerator> - <name>PCI_HOTPLUG_PGOOD</name> - <value>0x2</value> - </enumerator> - <enumerator> - <name>PCI_HOTPLUG_CONTROL</name> - <value>0x3</value> - </enumerator> - <enumerator> - <name>TPM</name> - <value>0x4</value> - </enumerator> - <enumerator> - <name>MODULE_VPD</name> - <value>0x5</value> - </enumerator> - <enumerator> - <name>DIMM_SPD</name> - <value>0x6</value> - </enumerator> - <enumerator> - <name>PROC_MODULE_VPD</name> - <value>0x7</value> - </enumerator> - <enumerator> - <name>SBE_SEEPROM</name> - <value>0x8</value> - </enumerator> - <enumerator> - <name>PLANAR_VPD</name> - <value>0x9</value> - </enumerator> - <enumerator> - <name>NVLINK_CABLE_TOPOLOGY_VERIFICATION</name> - <value>0xA</value> - </enumerator> - <enumerator> - <name>NVLINK</name> <!-- deprecated --> - <value>0xB</value> - </enumerator> - <enumerator> - <name>NVLINK_CABLE_MICRO_RESET</name> - <value>0xB</value> - </enumerator> - <enumerator> - <name>I2C_ASSOC_WITH_NVLINK_CABLE</name> - <value>0xC</value> - </enumerator> - <enumerator> - <name>WINDOW_OPEN</name> - <value>0xD</value> - </enumerator> - <enumerator> - <name>PHYSICAL_PRESENCE</name> - <value>0xE</value> - </enumerator> - <enumerator> - <name>MEX_FPGA</name> - <value>0xF</value> - </enumerator> - <enumerator> - <name>UNKNOWN</name> - <value>0xFF</value> - </enumerator> - <id>HDAT_I2C_DEVICE_PURPOSE</id> + <id>TYPE</id> </enumerationType> -<attribute> - <id>FREQ_CORE_MAX</id> + <attribute> <description> - SYSTEM Attribute - Maximum frequency (binary in MHz) that any processor in the system will - run. Used to define the top end of the PState range in the frequency space. - From this, the ATTR_PROCPM_PSTATE0_FREQUENCY is computed using - ATTR_SYSTEM_REFCLK_FREQUENCY to determine the step size. - - Consumers: proc_build_gpstate_table.C (among others) - - Data is is provided by MVPD #V and is calculated as the minimum - of the turbo frequencies + The ultra turbo frequency in MHz. + This is the same for all cores in the system. + Data is provided by MVPD #V and is calculated as + the minimum of the ultra turbo frequencies. </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> -<id>PIB_I2C_NEST_PLL</id> -<description> - i2c pll for the system - default is 0x26 (For PIB @500 MHz (2 GHz nest)) for - I2C speed = ~1Mhz per Andreas Koenig. -</description> - <simpleType> - <uint32_t> - <default>0x026</default> - </uint32_t> - </simpleType> + <id>ULTRA_TURBO_FREQ_MHZ</id> <persistency>volatile</persistency> <readable/> - <writeable/> -</attribute> - -<attribute> - <id>SYNC_BETWEEN_STEPS</id> - <description> - Attribute to enable targetting attribute sync when in istep mode. - 1 = sync will occur following each substep when ipl'ing in single step mode - 0 = sync will not be done after each step - </description> <simpleType> - <uint8_t> - </uint8_t> + <uint32_t/> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> <writeable/> -</attribute> + <hwpfToHbAttrMap> + <id>ATTR_ULTRA_TURBO_NOMINAL</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> + </attribute> -<attribute> - <id>NEST_PLL_FREQ_BUCKETS</id> - <description> - Constant defining number of NEST PLL frequency options ('buckets') - to be built into unsigned HW image. + <attribute> + <id>USE_TCES_FOR_DMAS</id> + <description> + Specifies whether or not the FSP is ready for Hostboot to enable TCEs + for DMAs for the given IPL. This is a temporary attribute which will + be used to phase-in TCE support. + If 0, DO NOT use TCEs; + If 1, use TCEs </description> - <simpleType> + <simpleType> <uint8_t> - <default>0x05</default> + <default>1</default> </uint8_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>NEST_PLL_FREQ_LIST</id> - <description> - Nest PLL frequency in MHZ - index is bucket number - </description> - <simpleType> - <uint32_t> - <default>1600,1866,2000,2133,2400</default> - </uint32_t> - <array>5</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>NEST_PLL_FREQ_I2CDIV_LIST</id> - <description> - I2C bus divisor - index is bucket number - The values in this list will be factor of 1:64 to the NEST_PLL_FREQ_LIST - </description> - <simpleType> - <uint32_t> - <default>25,29,31,33,37</default> - </uint32_t> - <array>5</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>MBA_PORT</id> - <description> - MBA port this DIMM is connected to - (deprecated in favor of MEM_PORT) - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>MEM_PORT</id> - <description> - Memory port this DIMM is connected to - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> </simpleType> - <persistency>non-volatile</persistency> + <persistency>volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>MBA_DIMM</id> + <attribute> <description> - MBA port DIMM number of this DIMM - (deprecated in favor of POS_ON_MEM_PORT) + Memory VCS voltage domain ID. All memory buffers in the same VCS + voltage domain will share the same ID. IDs are arbitrarily assigned, + used for correlation between HB + HWSV, and are generated by + genHwsvMrwXml.pl </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> + <id>VCS_ID</id> <persistency>non-volatile</persistency> <readable/> -</attribute> - -<attribute> - <id>POS_ON_MEM_PORT</id> - <description> - Position of this DIMM on its memory port - </description> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint16_t> + <default>0</default> + </uint16_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>ASYNC_NEST_FREQ_MHZ</id> - <description> - The asynchronous nest frequency + <attribute> + <description>Voltage Memory Rail Manager ID. Currently HB only needs + to configured the Vddr voltage rail manager during the IPL. The ID + is an arbitary value and needed as correlation token between HB and + HWSV. It will be generated by the genHwsvMrwXml.pl. </description> - <simpleType> - <uint32_t> - <default>2000</default> - </uint32_t> - </simpleType> + <id>VDDR_ID</id> <persistency>non-volatile</persistency> <readable/> -</attribute> - -<attribute> - <id>CHIP_ID</id> - <description>attribute indicating the chip's ID</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>SBE_IS_STARTED</id> - <description> - If 0, SBE for the processor has not been started. - Otherwise, SBE for the processor has been started. - </description> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>MIRROR_BASE_ADDRESS</id> - <description>System Mirrorable Base Address - Bits8-12 Specifies System Selects - Bits13-14 Memory select - Bits15-18 Group ID (within an SMP) - Bits19-21 Chip ID (8 Max) - Bits22-63 Chip internal address (42 bits, 4TB) - Mirroring uses memory select - </description> - <simpleType> - <uint64_t> - <default>0x4000000000000</default><!-- 4PT --> - </uint64_t> + <uint16_t> + <default>0</default> + </uint16_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MIRROR_BASE_ADDRESS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> <no_export/> -</attribute> - -<attribute> - <id>PROC_PCIE_PHB_ACTIVE</id> - <description>PCIE PHB valid mask - creator: platform - consumer: proc_pcie_scominit - firmware notes: - Bit mask defining set of active/valid PHBs - bit0=PHB0, bit1=PHB1, bit2=PHB2, bit3=PHB3 - </description> - <simpleType><uint8_t></uint8_t></simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>PROC_PCIE_NUM_PEC</id> - <description> - creator: platform - Number of PCIe PEC units present on target - Nimbus: 3 - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>HOMER_PHYS_ADDR</id> - <description> - Physical address where HOMER image is placed in mainstore. - </description> - <simpleType> - <uint64_t></uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HOMER_PHYS_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <ignoreEkb/> -</attribute> + </attribute> -<attribute> - <id>FREQ_CORE_CEILING_MHZ</id> - <description> - The maximum core frequency in MHz. - This is the same for all cores in the system. - Data is provided by MVPD #V and is calculated as - the minimum of the turbo frequencies. - </description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_FREQ_CORE_CEILING_MHZ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <ignoreEkb/> -</attribute> - -<attribute> - <id>PG</id> - <description> - Chiplet Partial good info attribute. Provided by Ring scans - </description> - <simpleType> - <uint16_t> - </uint16_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <ignoreEkb/> -</attribute> - -<attribute> - <id>SECUREBOOT_PROTECT_DECONFIGURED_TPM</id> + <attribute> <description> - To deconfigure a TPM in a secure system - 01 to set TDP bit + Memory VDD voltage domain ID. All memory buffers in the same VDD + voltage domain will share the same ID. IDs are arbitrarily assigned, + used for correlation between HB + HWSV, and are generated by + genHwsvMrwXml.pl </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> + <id>VDD_ID</id> + <persistency>non-volatile</persistency> <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SECUREBOOT_PROTECT_DECONFIGURED_TPM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <ignoreEkb/> -</attribute> - -<attribute> - <id>PROC_PCIE_PCS_SYSTEM_CNTL</id> - <description> - Value of PCS system control - creator: platform - consumer: p9_pcie_scominit - </description> <simpleType> - <uint16_t></uint16_t> + <uint16_t> + <default>0</default> + </uint16_t> </simpleType> - <persistency>non-volatile</persistency><!-- @fixme --> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_SYSTEM_CNTL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <ignoreEkb/> -</attribute> - -<attribute> - <id>SBE_UPDATE_DISABLE</id> - <description> - Control execution of updateProcessorSbeSeeproms() - - if 0, enable SBE update of processor SEEPROM - if 1, disable SBE update of processor SEEPROM + </attribute> - Consumer: sbe_update.C + <enumerationType> + <description>Enumeration for Voltage Drop Monitor enable</description> + <enumerator> + <name>OFF</name> + <value>0x00</value> + </enumerator> + <enumerator> + <name>ON</name> + <value>0x01</value> + </enumerator> + <id>VDM_ENABLE</id> + </enumerationType> - Default: 0 - </description> + <attribute> + <id>VENDOR_ID</id> + <description>PCIe vendor ID definition</description> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint8_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + <no_export/> + </attribute> -<attribute> - <id>SBE_COMMIT_ID</id> - <description> - A hexadecimal value of the commit ID associated - with the SBE. - </description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> + <attribute> + <description>Record offset for this target's VPD</description> + <id>VPD_REC_NUM</id> + <persistency>non-volatile</persistency> <readable/> - <writeable/> -</attribute> - -<attribute> - <id>SBE_VERSION_INFO</id> - <description> - A hexadecimal value of the major and minor - version of the SBE. The major info is in the - first 16 bits followed by the minor. - 0:15: Major Version - 16:31: Minor Version - </description> <simpleType> - <uint32_t> - </uint32_t> + <uint16_t> + <default>0xFFFF</default> + </uint16_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> + <no_export/> + </attribute> -<attribute> - <id>SBE_RELEASE_TAG</id> + <attribute> <description> - An ascii value of the SBE release tag + Memory VPP voltage domain ID. All memory buffers in the same VPP + voltage domain will share the same ID. IDs are arbitrarily assigned, + used for correlation between HB + HWSV, and are generated by + genHwsvMrwXml.pl </description> - <simpleType> - <string> - <default></default> - <sizeInclNull>21</sizeInclNull> - </string> - </simpleType> - <persistency>volatile-zeroed</persistency> + <id>VPP_ID</id> + <persistency>non-volatile</persistency> <readable/> - <writeable/> -</attribute> - -<attribute> - <id>PROC_PCIE_REFCLOCK_ENABLE</id> - <description>PCIE refclock enable valid mask - PCIE refclock enable valid mask - creator: platform - consumer: p9_pcie_scominit - </description> <simpleType> - <uint8_t> - </uint8_t> + <uint16_t> + <default>0</default> + </uint16_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_REFCLOCK_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <ignoreEkb/> -</attribute> - -<attribute> - <id>PROC_PCIE_IOP_CONFIG</id> - <description>PCIE IOP lane configuration - creator: platform - consumer: proc_pcie_scominit - firmware notes: - Encoded PCIE IOP lane configuration - </description> - <simpleType><uint8_t></uint8_t></simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_IOP_CONFIG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <ignoreEkb/> -</attribute> + </attribute> -<attribute> - <id>PROC_PCIE_IOVALID_ENABLE</id> - <!-- TARGET_TYPE_PEC --> + <attribute> <description> - PCIE iovalid enable valid mask - creator: platform - consumer: p9_pcie_scominit + System control to set the power limit for Workload Optimized + Frequency (WOF) algorithms. This is used to select the + proper VFRT tables. + Producer: TMGT + Consumers: FW that selects VFRT tables </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_IOVALID_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <readable/> - <writeable/> - <ignoreEkb/> -</attribute> - -<attribute> - <id>ISTEP_MODE</id> - <description>If True, puts HostBoot into SPLess SingleStep mode.</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> + <id>WOF_POWER_LIMIT</id> <persistency>non-volatile</persistency> <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_ISTEP_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <ignoreEkb/> -</attribute> - -<attribute> - <id>EC</id> - <description>attribute indicating the chip target's EC level</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EC</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <ignoreEkb/> -</attribute> - -<attribute> - <id>EFF_DRAM_COLS</id><!-- @fixme --> - <description>Number of DRAM columns. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>EFF_DRAM_ROWS</id><!-- @fixme --> - <description>Number of DRAM rows. Initialized and used by HWPs.</description> <simpleType> - <uint8_t> - </uint8_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> <writeable/> -</attribute> - -<attribute> - <id>REDUNDANT_CLOCKS</id> - <description> - 1 = System has redundant clock oscillators - 0 = System does not have redundant clock oscillators - From the Machine Readable Workbook - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<enumerationType> - <id>FUSED_CORE_MODE_HB</id> - <description>Enum for FUSED_CORE_MODE_HB</description> - <enumerator> - <name>SMT4_DEFAULT</name> - <value>0</value> - </enumerator> - <enumerator> - <name>SMT4_ONLY</name> - <value>1</value> - </enumerator> - <enumerator> - <name>SMT8_ONLY</name> - <value>2</value> - </enumerator> -</enumerationType> + </attribute> -<enumerationType> - <id>KEY_TRANSITION_STATE</id> - <description> - Enum indicating the current Secure Boot key transition state for the - node. - </description> - <enumerator> - <description> - Secure Boot key transition not yet requested for the node - </description> - <name>KEY_TRANSITION_NOT_REQUESTED</name> - <value>0</value> - </enumerator> - <enumerator> - <description> - About to write new system Secure Boot key to first SBE SEEPROM - side in the node - </description> - <name>KEY_TRANSITION_STARTED</name> - <value>1</value> - </enumerator> + <enumerationType> + <description>Enumeration to select WOF Power Limit</description> <enumerator> - <description> - Failed to apply new system Secure Boot key to one or more functional - SBE SEEPROM sides in the node - </description> - <name>KEY_TRANSITION_FAILED</name> - <value>2</value> + <name>NOMINAL</name> + <value>0</value> </enumerator> <enumerator> - <description> - Successfully applied new system Secure Boot key to every functional - SBE SEEPROM side in the node - </description> - <name>KEY_TRANSITION_SUCCEEDED</name> - <value>3</value> + <name>TURBO</name> + <value>1</value> </enumerator> -</enumerationType> - -<attribute> - <description> - Attribute indicating the status of the Secure Boot key transition for - the node - </description> - <hasStringConversion></hasStringConversion> - <id>KEY_TRANSITION_STATE</id> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <simpleType> - <enumeration> - <id>KEY_TRANSITION_STATE</id> - <default>KEY_TRANSITION_NOT_REQUESTED</default> - </enumeration> - </simpleType> -</attribute> - -<attribute> - <id>FUSED_CORE_MODE_HB</id> - <description> - Stores the SMT setting used to determine fused mode. - SMT4_DEFAULT: Nimbus_DD1, boot in SMT4 but can change to SMT8 - SMT4_ONLY: Nimbus_DD2/Cumulus, set based on PVR info - SMT8_ONLY: Nimbus_DD2/Cumulus, set based on PVR info - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>SOCKET_POWER_NOMINAL</id> - <description> - The socket power in nominal mode. - Controls how much power can be used. - This is the same for all cores in the system. - Data is provided by MVPD #V. - </description> - <simpleType><uint32_t></uint32_t></simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>SOCKET_POWER_TURBO</id> - <description> - The socket power in turbo mode. - Controls how much power can be used. - This is the same for all cores in the system. - Data is provided by MVPD #V. - </description> - <simpleType><uint32_t></uint32_t></simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> + <id>WOF_POWER_LIMIT</id> + </enumerationType> -<attribute> + <attribute> <id>WOF_TABLE_LID_NUMBER</id> <description> LID id used to load tables for Workload Optimized @@ -6826,1256 +8016,68 @@ </description> <simpleType> <uint32_t> -<!-- @todo-RTC:172776-Get rid of default value that points to ZZ --> + <!-- @todo-RTC:172776-Get rid of default value that points to ZZ --> <default>0x81E00440</default> </uint32_t> </simpleType> <persistency>non-volatile</persistency> <readable/> <writeable/> -</attribute> - -<attribute> - <id>PROC_DCM_INSTALLED</id> - <description> - PROC_CHIP Attribute - If true, the chip is installed on a Dual Chip Module - Provided by the Machine Readable Workbook - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - - -<attribute> - <id>PROC_PCIE_PCS_RX_LOFF_CONTROL</id> - <!-- TARGET_TYPE_PEC --> - <description> - PCS rx loff control - creator: platform - consumer: p9_pcie_scominit - firmware notes: - The value of rx loff control for PCS. - Array index: Configuration number - index 0~3 for CONFIG0~3 - </description> - <simpleType> - <uint16_t></uint16_t> - <array>4</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PROC_PCIE_PCS_RX_PHASE_ROTATOR_CNTL</id> - <!-- TARGET_TYPE_PEC --> - <description> - Value of PCS rx phase rotator control - creator: platform - consumer: p9_pcie_scominit - </description> - <simpleType> - <uint16_t></uint16_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PROC_PCIE_PCS_RX_SIGDET_CNTL</id> - <!-- TARGET_TYPE_PEC --> - <description> - Value of PCS rx sigdet control - creator: platform - consumer: p9_pcie_scominit - </description> - <simpleType> - <uint16_t></uint16_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PROC_PCIE_PCS_TX_FIFO_CONFIG_OFFSET</id> - <!-- TARGET_TYPE_PEC --> - <description> - Value of PCS tx fifo config offset - creator: platform - consumer: p9_pcie_scominit - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>HOT_PLUG_POWER_CONTROLLER_INFO</id> - <description>Hot Plug Controller values for a specific processor. - Purpose: Holds information about the hot plug controllers so that a - Hardware procedure is able to turn them on and off. - Data Format: up to 8 Hot Plug Controllers x 7 variables of information - This data is at the processor level. - The needed information and their individual sizes are as follows: - (1) I2C Master processor engine (uint8_t) - (2) I2C Master processor port (uint8_t) - (3) Bus Speed (uint16_t value: 2 uint8_t values: MSB, LSB) - (4) Slave address (uint8_t) - (5) Device type (uint8_t: see SUPPORTED_HOT_PLUG enum) - (6) I2C Master processor node (uint8_t) - (7) I2C Master processor position (uint8_t) - Thus, the information will be 8 bytes. - </description> - <simpleType> - <uint8_t> - <default>0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - </default> - </uint8_t> - <array>8,8</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PM_UNDERVOLTING_FRQ_MINIMUM</id> - <description> - Override for Minimum frequency for which undervolting is allowed. - - If value = 0, the value of VPD CPMin data point is passed to OCC FW via - Pstate SuperStructure. - - If value != 0, this value will be passed to OCC FW via Pstate SuperStructure - as the floor frequency for enabled CPMs. - - Will be internally rounded to the nearest ATTR_PROC_REFCLK_FREQUENCY / 8 value. - - Consumer: OCC FW; OCC Lab Tools - - Provided by the Machine Readable Workbook. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PM_UNDERVOLTING_FREQ_MAXIMUM</id> - <description> - Override for Maximum frequency for which undervolting is allowed. - - If value = 0, the value of VPD Turbo data point is passed to OCC FW via - Pstate SuperStructure. - - If value != 0, this value will be passed to OCC FW via Pstate SuperStructure - as the ceiling frequency for enabled CPMs. - - Will be internally rounded to the nearest ATTR_PROC_REFCLK_FREQUENCY / 8 value. - - Consumer: OCC FW; OCC Lab Tools - - Provided by the Machine Readable Workbook. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PM_WINKLE_ENTRY</id> - <description>Setting depends on di/dt charateristics of the system. - - Set Assisted if power off serialization is needed and WINKLE_TYPE=Fast; - Set to Hardware if the system can handle the unrelated powering off between cores. - Hardware setting decreases entry latency - - Producer: MRWB - - Consumer: p8_poreslw_init.C - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PM_WINKLE_EXIT</id> - <description>Setting depends on di/dt charateristics of the system and the setting of ATTR_PM_WINKLE_TYPE. - - Set to Assisted if power on serialization is needed and WINKLE_TYPE=Fast; Set to Hardware if the system - can handle the unrelated powering off between cores. Hardware setting decreases entry latency. - Must be set to Assisted if ATTR_PM_WINKLE_TYPE=Deep as this necessary for restore. - - Setting to Hardware is a test mode for Fast only. - - Producer: MRWB - - Consumer: p8_poreslw_init.C - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PM_SPIVID_PORT_ENABLE</id> - <description> - PROC_CHIP Attribute - Defines the configuration of the SPIVID ports from the target. - - NONE means that no VRM is attached. - - PORTxNONRED means that the indicated port is used in a non-redundant - configuration. - - REDUNDANT means that all three are connected and considered redundant. - - Provided by the Machine Readable Workbook. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PM_PBAX_NODEID</id> - <description> - DEPRECATED!!! Use PBAX_GROUPID instead - PROC_CHIP Attribute - Receive PBAX Nodeid. Value that indicates this PBA's PBAX Node affinity. - This is matched to pbax_nodeid of the PMISC Address phase. - - Provided by the Machine Readable Workbook. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PM_SLEEP_ENTRY</id> - <description> - PROC_CHIP Attribute - -Set Assisted if power off serialization is needed and SLEEP_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency - -Producer: MRWB - -Consumer: proc_pm_init and proc_pcbs_init - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PM_SLEEP_EXIT</id> - <description> - PROC_CHIP Attribute - -Set to Assisted if power on serialization is needed and SLEEP_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency -Must be set to Assisted if ATTR_PM_SLEEP_TYPE=Deep as this necessary for restore. - -Setting to Hardware is a test mode for Fast only. - -Producer: MRWB - -Consumer: proc_pm_init and proc_pcbs_init. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PM_SLEEP_TYPE</id> - <description> - PROC_CHIP Attribute -Selects which voltage level to place the Core domain PFETs upon Sleep entry. 0 = Vret (Fast Sleep Mode), 1 = Voff (Deep Sleep Mode) - -Producer: MRWB - -Consumer: proc_pm_init and proc_pcbs_init - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PM_WINKLE_TYPE</id> - <description> - PROC_CHIP Attribute -Selects which voltage level to place the Core and ECO domain PFETs upon Winkle entry. 0 = Vret (Fast Winkle Mode), 1 = Voff (Deep Winkle Mode) - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>MSS_PHY_SEQ_REFRESH</id> - <description> - Controls ENABLE/DISABLE of workaround that sets - the PHY sequencer to trigger refresh after draminit. - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_PHY_SEQ_REFRESH</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + </attribute> -<attribute> - <id>PRD_HWP_PLID</id> - <description> - PRD will perform error isolation for certain errors that may cause a HWP - to fail. This attribute will be used by the HWP to store the PLID so that - PRD can subsequently check it for a non-zero value and link the HWP PLID - to the PRD error log. + <attribute> + <description>XIVE - Controller Bar address + MMIO consumed by PHYP </description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> + <id>XIVE_CONTROLLER_BAR_ADDR</id> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> - - -<attribute> - <id>SLOT_NAME</id> - <description>PCIe slot name definition</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>SLOT_INDEX</id> - <description>PCIe slot index definition</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>PCIE_32BIT_MMIO_SIZE</id> - <description>PCIe slot 32bit MMIO size definition</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - - -<attribute> - <id>PCIE_64BIT_MMIO_SIZE</id> - <description>PCIe slot 64bit MMIO size definition</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>PCIE_32BIT_DMA_SIZE</id> - <description>PCIe slot 32bit DMA size definition</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>PCIE_64BIT_DMA_SIZE</id> - <description>PCIe slot 64bit DMA size definition</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>HDDW_ORDER</id> - <description>PCIe slot HDDW order definition</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - - -<attribute> - <id>MGC_LOAD_SOURCE</id> - <description>defines MGC load source</description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>PCIE_CAPABILITES</id> - <description>Denotes the capabilites of this pcie slot</description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>VENDOR_ID</id> - <description>PCIe vendor ID definition</description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>MAX_POWER</id> - <description>Defines the maximum power consumption for a PCIe slot</description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>OBUS_BRICK_LANE_MASK</id> - <description> - Lane mask for which 8 lanes belong to this brick - This is a right justified 24-bit value. Only 8 of the - 24 bits will be set representing the lanes belonging to - the associated brick. - Provided by the MRW. - </description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>OBUS_SLOT_INDEX</id> - <description> - Position of the obus slot that the Obus brick is connected to - (represented in decimal). There is only one slot that a given - brick connects to and there are only 6 slots per proc, - so, we just need a single uint8_t representing the position - of the slot. - Provided by the MRW. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>MFG_TRACE_ENABLE</id> - <description> - Override this to a non-zero value to have the FAPI manufacturing - traces output to the console or go to a fsp trace buffer when - console not enabled. - </description> - <simpleType><uint8_t></uint8_t></simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> -</attribute> - - -<attribute> - <id>MAX_SBE_SEEPROM_SIZE</id> - <description> - Defines the maximum Seeprom storage size for the fully-customized SBE image - permitted by the platform. - For platforms (FSP/HB FW) which require the image to be constrained into a - physical storage device (SEEPROM), this should reflect the maximum size of that - memory (e.g., 256KB). - For platforms (Cronus) which may use a customized image in a virtual - envrionment with no physical storage constraints, this size may be - larger than the physical SEEPROM size. - </description> - <simpleType> - <uint32_t> - <default>0x40000</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MAX_SBE_SEEPROM_SIZE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>STOP5_DISABLE</id> - <description> Control CME response to execution of PowerPC STOP instruction - if OFF, treat STOP5 as STOP5 - if ON, treat STOP5 as STOP4 - - Producer: ??? - - Consumer: p8_hcode_image_build.C - - Platform default: OFF - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_STOP5_DISABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<!-- Required by FSP --> -<attribute> - <id>FREQ_PROC_REFCLOCK</id> - <description> - System attribute. - The frequency of the processor refclock in MHz. - Provided by the MRW. - </description> - <simpleType><uint32_t></uint32_t></simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>MSS_MBA_ADDR_INTERLEAVE_BIT</id> - <description>sets the Centaur address bits used to interleave addresses between MBA01 and MBA23. valid values are 23 through 32.</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>MSS_MBA_CACHELINE_INTERLEAVE_MODE</id> - <description>centaur interleave mode. 1 = 256-BIT, 0 = 128-BIT.</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PM_SPIVID_FREQUENCY</id> - <description> - SYSTEM Attribute - SPI Clock Frequency (binary in MHz) - - Consumer: proc_pm_effective - - Produces ATTR_PM_SPIVID_CLOCK_DIVIDER - - Provided by the Machine Readable Workbook. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PM_SAFE_FREQUENCY</id> - <description> - Frequency (binary in KHz) indicating the frequency that the cores will be moved - to in the event of the loss of the OCC Heartbeat. This value needs to be the maximum - of the DpoMin frequency for proper PowerBus operation and the PowerSave value for - the present part. - - Provided by the Machine Readable Workbook after system characterization. - - The value is translated to the Pstate space. - - Producer: Machine Readable Workbook - - Consumers: p8_build_gpstate_table.C - - DYNAMIC_ATTRIBUTE: ATTR_PM_SAFE_PSTATE - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> - <description> - SYSTEM Attribute - Frequency (binary in MHz) for the point at which clock sector buffers - should be at full strength. This is to support Vmin operation. - Setting cannot overlap the Low or High bands. - - Provided by the Machine Readable Workbook after system characterization. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> - <description> - SYSTEM Attribute - Frequency (binary in MHz)) for the lower end of the Low Frequency - Resonant band - - Provided by the Machine Readable Workbook after system characterization. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> - <description> - SYSTEM Attribute - Frequency (binary in MHz) for the upper end of the Low Frequency - Resonant band - - Provided by the Machine Readable Workbook after system characterization. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> - <description> - SYSTEM Attribute - Frequency (binary in MHz) for the lower end of the High Frequency - Resonant band - - Provided by the Machine Readable Workbook after system characterization. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> - <description> - SYSTEM Attribute - Frequency (binary in MHz)) for the upper end of the High Frequency - Resonant band - - Provided by the Machine Readable Workbook after system characterization. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>MRW_MEM_THROTTLE_DENOMINATOR</id> - <description>Machine Readable Workbook throttle value for denominator cfg_nm_m</description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PM_SYSTEM_IVRM_VPD_MIN_LEVEL</id> - <description>Version level of #M that represents the minimum for IVRM characterized parts. - If this value is non-zero and the #M version level is less than this value, IVRMs are disabled. - If the #M version is greater than or equal to this value, the IVRMs are allowed to be enable from a level of part perspective. - Producer: MRWB - Consumer: p8_build_pstate_datablock.C - </description> <simpleType> - <uint8_t></uint8_t> + <uint64_t/> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>MNFG_DMI_MIN_EYE_WIDTH</id> - <description> - System attribute. - 6 bit rx_min_eye_width value for DMI bus interfaces during system - manufacturing; used for both centaur and p8 - creator: platform - firmware notes: Attribute value is in the Machine Readable Workbook - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>MNFG_DMI_MIN_EYE_HEIGHT</id> - <description> - System attribute. - 8 bit rx_min_eye_height value for DMI bus interfaces during system - manufacturing; used for both centaur and p8 - creator: platform - firmware notes: Attribute value is in the Machine Readable Workbook - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>MNFG_ABUS_MIN_EYE_WIDTH</id> - <description> - System attribute - 6 bit rx_min_eye_width value for A bus interfaces during system - manufacturing - creator: platform - firmware notes: Attribute value is in the Machine Readable Workbook - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>MNFG_ABUS_MIN_EYE_HEIGHT</id> - <description> - System attribute - 8 bit rx_min_eye_height value for A bus interfaces during system - manufacturing - creator: platform - firmware notes: Attribute value is in the Machine Readable Workbook - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>MNFG_XBUS_MIN_EYE_WIDTH</id> - <description> - System attribute - 6 bit rx_min_eye_width value for X bus interfaces during system - manufacturing - creator: platform - firmware notes: Attribute value is in the Machine Readable Workbook - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>MFG_WRAP_TEST_ABUS_LINKS_SET_ENABLE</id> - <description> - This attribute defines which set of ABUS links to enable - during MST wrap testing. This attribute will live on - the system target. The value will be overriden during - MST testing. When the value of MFG_WRAP_TEST_ABUS_LINKS_SET - on each of the OBUS matches with this value, then we leave the - OBUSes configured. Otherwise, we deconfigure them. - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> -</attribute> - -<enumerationType> - <id>MFG_WRAP_TEST_ABUS_LINKS_SET</id> - <description>Enum for MFG_WRAP_TEST_ABUS_LINKS_SET</description> - <enumerator> - <name>SET_NONE</name> - <value>0x0</value> - </enumerator> - <enumerator> - <name>SET_1</name> - <value>0x1</value> - </enumerator> - <enumerator> - <name>SET_2</name> - <value>0x2</value> - </enumerator> -</enumerationType> + </attribute> -<attribute> - <id>MFG_WRAP_TEST_ABUS_LINKS_SET</id> + <attribute> <description> - Due to fabric limitations, we can only enable 2 links - at a time during wrap testing. This attribute defines - which set this ABUS link belong to. This attribute - will live on the OBUS target. The value will come - from MRW. When the value for this attribute matches - MFG_WRAP_TEST_ABUS_LINKS_SET_ENABLE, then we leave the - OBUSes configured. Otherwise, we deconfigure them. + Used to tell INTRP code whether to use the XIVE HW Reset + or a software based reset. + 0 = Software based reset + 1 = XIVE HW reset </description> - <simpleType> - <enumeration> - <default>SET_NONE</default> - <id>MFG_WRAP_TEST_ABUS_LINKS_SET</id> - </enumeration> - </simpleType> + <id>XIVE_HW_RESET</id> <persistency>non-volatile</persistency> <readable/> -</attribute> -<attribute> - <id>BRAZOS_RX_FIFO_OVERRIDE</id> - <description> - Defines where to apply Brazos rx_fifo_final_l2u_dly override settings for SW299500. - </description> <simpleType> <uint8_t> <default>0</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PROC_PCIE_PCS_RX_VGA_CONTRL_REGISTER3</id> - <!-- TARGET_TYPE_PEC --> - <description> - PCS rx vga control register3 - creator: platform - consumer: p9_pcie_scominit - firmware notes: - The value of rx vga control register3. - Array index: Configuration number - index 0~3 for CONFIG0~3 - </description> - <simpleType> - <uint16_t></uint16_t> - <array>4</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PROC_REFCLOCK_RCVR_TERM</id> - <description> - Defines system specific value of processor refclock receiver termination (FSI GP4 bits 8:9) - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <hasStringConversion/> - <readable/> -</attribute> - -<attribute> - <id>PCI_REFCLOCK_RCVR_TERM</id> - <description> - Defines system specific value of PCI refclock receiver termination (FSI GP4 bits 10:11) - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <hasStringConversion/> - <readable/> -</attribute> - -<!-- End Required by FSP --> - -<attribute> - <id>MAX_DMI_PER_PROC</id> - <description> - System attribute. - The max DMI units per proc available in the system. - </description> - <simpleType> - <uint8_t> - <default>8</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>MC_PLL_BUCKET</id> - <description> - MC pll bucket selection in async mode for Cumulus - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MC_PLL_BUCKET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPWUP_FSP</id> - <description> - EX_CHIPLET Attribute - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>PM_SPWUP_OCC</id> - <description> - EX_CHIPLET Attribute + <attribute> + <description>XIVE - Thread Management Bar address register 1 + MMIO consumed by HB/PHYP </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> + <id>XIVE_THREAD_MGMT1_BAR_ADDR</id> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> - -<attribute> - <id>PM_SPWUP_PHYP</id> - <description> - EX_CHIPLET Attribute - </description> <simpleType> - <uint32_t></uint32_t> + <uint64_t/> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> -<id>PIB_I2C_REFCLOCK</id> -<description> - i2c reference clock for the system. - default is 0x4 => I2C speed = ~1Mhz per Andreas Koenig -</description> - <simpleType> - <uint32_t> - <default>0x4</default> - </uint32_t> - </simpleType> + <attribute> + <description>XSCOM base address</description> + <id>XSCOM_BASE_ADDRESS</id> <persistency>volatile</persistency> <readable/> <writeable/> -</attribute> - -<attribute> - <id>ALL_MCS_IN_INTERLEAVING_GROUP</id> - <description> - System attribute. - If all MCS chiplets are in an interleaving group (1=true, 0=false). - - If true the SMP fabric is setup in normal mode and multiple MCSs - are grouped (disallowing systems with memory only under 1 MCS - (i.e. systems with a single C-DIMM)) - - If false the SMP fabric is setup in checkerboard mode. - Provided by the Machine Readable Workbook. - This attribute is based on Machine-Type-Model (MTM) and is setup by - the service processor. - </description> <simpleType> - <uint8_t> - <default>0x00</default> - </uint8_t> + <uint64_t/> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>PROC_SELECT_SEEPROM_IMAGE</id> - <description> - Specifies which SEEPROM image should be used for the boot master. - FIRST - the first image was selected - SECOND - the second image was selected - Platforms are expected to set this to FIRST in normal operation - </description> - <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>PROC_SELECT_BOOT_SEEPROM_IMAGE</id> - <description> - Specifies which SEEPROM image should be used to boot a processor - FIRST - the first image was selected - SECOND - the second image was selected - </description> - <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_SELECT_BOOT_SEEPROM_IMAGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>USE_TCES_FOR_DMAS</id> - <description> -<!-- @TODO RTC 187906 Remove This Attribute --> - Specifies whether or not the FSP is ready for Hostboot to enable TCEs - for DMAs for the given IPL. This is a temporary attribute which will - be used to phase-in TCE support. - If 0, DO NOT use TCEs; - If 1, use TCEs - </description> - <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>TCE_START_TOKEN_FOR_PAYLOAD</id> - <description> - Specifies which TCE Token the FSP should start with to transfer the - PAYLOAD into system memory. - If 0xFFFFFFFF, then invalid; otherwise, valid. - </description> - <simpleType> - <uint32_t> - <default>0xFFFFFFFF</default> - </uint32_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>START_MEM_ADDRESS_FOR_PAYLOAD_TCE_TOKEN</id> - <description> - Specifies the starting memory address that corresponds to the TCE Token - used by the FSP to transfer the PAYLOAD into system memory. - If 0xFFFFFFFFFFFFFFFF, then invalid; otherwise, valid. - </description> - <simpleType> - <uint64_t> - <default>0xFFFFFFFFFFFFFFFF</default> - </uint64_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>TCE_START_TOKEN_FOR_HDAT</id> - <description> - Specifies which TCE Token the FSP should start with to transfer the - HDAT section into system memory. - If 0xFFFFFFFF, then invalid; otherwise, valid. - </description> - <simpleType> - <uint32_t> - <default>0xFFFFFFFF</default> - </uint32_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>ATTN_AREA_1_ADDR</id> - <description> - Specifies the "intended" starting memory address for PHYP's ATTN area 1. - This is written to by Hostboot and read by FSP as a means for Hostboot to - communicate its intentions of where the ATTN 1 area will be. Hostboot can - then later open up an SBE window for PHYP to dump its debugging info. An - address of 0xFFFFFFFFFFFFFFFF is considered N/A. - </description> - <simpleType> - <uint64_t> - <default>0xFFFFFFFFFFFFFFFF</default> - </uint64_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <no_export/> -</attribute> - -<attribute> - <id>ATTN_AREA_2_ADDR</id> - <description> - Specifies the "intended" starting memory address for PHYP's ATTN area 2. - This is written to by Hostboot and read by FSP as a means for Hostboot to - communicate its intentions of where the ATTN 2 area will be. Hostboot can - then later open up an SBE window for PHYP to dump its debugging info. An - address of 0xFFFFFFFFFFFFFFFF is considered N/A. - </description> - <simpleType> - <uint64_t> - <default>0xFFFFFFFFFFFFFFFF</default> - </uint64_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <no_export/> -</attribute> - -<attribute> - <id>MAX_COMPUTE_NODES_PER_SYSTEM</id> - <description> - The max compute nodes available in the system. - Computed value based on CEC enclosures. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> <no_export/> -</attribute> + </attribute> </attributes> diff --git a/src/usr/targeting/common/xmltohb/attribute_types_cfm.xml b/src/usr/targeting/common/xmltohb/attribute_types_cfm.xml index 7109e5597..0c9e6f468 100755 --- a/src/usr/targeting/common/xmltohb/attribute_types_cfm.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types_cfm.xml @@ -22,69 +22,65 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> - -<attributes> - <!-- ===================================================================== CONCURRENT FIRMWARE UPDATE ATTRIBUTE TYPES Contains the definition of attributes used to test CFM ================================================================= --> - -<attribute> +<attributes> + <attribute> <description> - CFM test attribute - volatile-zeroed + CFM test attribute - non-volatile read-only </description> - <id>CFM_TEST_VZ</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> + <id>CFM_TEST_NV_RO</id> + <persistency>non-volatile</persistency> + <readable/> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t> + <default>0x75804084</default> + </uint32_t> </simpleType> -</attribute> + </attribute> -<attribute> + <attribute> <description> - CFM test attribute - volatile writeable + CFM test attribute - non-volatile writeable </description> - <id>CFM_TEST_V_WR</id> - <persistency>volatile</persistency> - <readable></readable> - <writeable></writeable> + <id>CFM_TEST_NV_WR</id> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> <simpleType> - <uint32_t> - <default>0x33EFE76B</default> - </uint32_t> + <uint32_t> + <default>0x90359461</default> + </uint32_t> </simpleType> -</attribute> + </attribute> -<attribute> + <attribute> <description> - CFM test attribute - non-volatile read-only + CFM test attribute - volatile-zeroed </description> - <id>CFM_TEST_NV_RO</id> - <persistency>non-volatile</persistency> - <readable></readable> + <id>CFM_TEST_VZ</id> + <persistency>volatile-zeroed</persistency> + <readable/> <simpleType> - <uint32_t> - <default>0x75804084</default> - </uint32_t> + <uint32_t/> </simpleType> -</attribute> + </attribute> -<attribute> + <attribute> <description> - CFM test attribute - non-volatile writeable + CFM test attribute - volatile writeable </description> - <id>CFM_TEST_NV_WR</id> - <persistency>non-volatile</persistency> - <readable></readable> - <writeable></writeable> + <id>CFM_TEST_V_WR</id> + <persistency>volatile</persistency> + <readable/> + <writeable/> <simpleType> - <uint32_t> - <default>0x90359461</default> - </uint32_t> + <uint32_t> + <default>0x33EFE76B</default> + </uint32_t> </simpleType> -</attribute> + </attribute> </attributes> diff --git a/src/usr/targeting/common/xmltohb/attribute_types_hb.xml b/src/usr/targeting/common/xmltohb/attribute_types_hb.xml index 6fe4a2966..3b8dfe27b 100755 --- a/src/usr/targeting/common/xmltohb/attribute_types_hb.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types_hb.xml @@ -23,155 +23,120 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> - -<attributes> - <!-- ===================================================================== HOST BOOT ATTRIBUTE TYPES Contains the definition of hostboot attributes which should not be synced to/from FSP ================================================================= --> - -<attribute> - <id>HIDDEN_ERRLOGS_ENABLE</id> +<attributes> + <attribute> + <id>ALLOW_ATTR_OVERRIDES_IN_SECURE_MODE</id> <description> - Used to decide whether or not to prevent INFORMATIONAL/RECOVERED error - logs from being sent to the BMC via SEL/eSEL, saved to the PNOR, and - displayed to the console. - 0 = Prevent INFORMATIONAL/RECOVERED error logs from being processed. - 1 = Send only INFORMATIONAL error logs. - 2 = Send only RECOVERED error logs. - 3 = Allow all hidden error logs to be processed. + Indicates if Attribute Overrides are allowed when the system is booted + in secure mode. The default is 0x0, where attribute overrides are not + allowed. However, the SBE can read mailbox scratch register 3 bit 7 + to set it to 0x1, meaning that attribute overrides are allowed. The SBE + passes this information up to hostboot via the bootloader. + 0x00 = Attribute Overrides are not allowed (default) + 0x01 = Attribute Overrides are allowed </description> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint8_t> + <default>0x00</default> + </uint8_t> </simpleType> - <persistency>volatile</persistency> + <persistency>volatile-zeroed</persistency> + <writeable/> <readable/> -</attribute> - -<enumerationType> - <id>HIDDEN_ERRLOGS_ENABLE</id> - <description>Enumeration of HIDDEN_ERRLOGS_ENABLE</description> - <enumerator> - <name>NO_HIDDEN_LOGS</name> - <value>0</value> - </enumerator> - <enumerator> - <name>ALLOW_INFORMATIONAL</name> - <value>1</value> - </enumerator> - <enumerator> - <name>ALLOW_RECOVERED</name> - <value>2</value> - </enumerator> - <enumerator> - <name>ALLOW_ALL_LOGS</name> - <value>3</value> - </enumerator> -</enumerationType> + <hbOnly/> + </attribute> -<attribute> - <description> - Are we doing checkstop analysis on - systems as we are booting back up based - on information captured in FIRDATA section. - </description> - <id>CHKSTOP_ANALYSIS_ON_STARTUP</id> - <persistency>volatile-zeroed</persistency> - <readable></readable> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <writeable></writeable> -</attribute> - -<enumerationType> - <description>Enum for CHKSTOP_ANALYSIS_ON_STARTUP</description> - <enumerator> - <name>NOT_ANALYZING_DEFAULT</name> - <value>0</value> - </enumerator> - <enumerator> - <name>ANALYZING_CHECKSTOP</name> - <value>1</value> - </enumerator> - <id>CHKSTOP_ANALYSIS_ON_STARTUP</id> -</enumerationType> - -<attribute> - <id>IS_MPIPL_HB</id> - <description>1 = in Memory Preserving IPL mode. 0 = in normal IPL mode.</description> + <attribute> + <id>ATTN_CHK_ALL_PROCS</id> + <description> + Used to tell ATTN code whether to chk MASTER(0) OR all PROCs(1) + when the checkForIplAttns routine is called. + </description> <simpleType> - <uint8_t> - </uint8_t> + <uint8_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_IS_MPIPL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>MPIPL_HB_MDRT_COUNT</id> - <description>Actual MDRT count in Memory Preserving IPL mode.</description> + <attribute> + <id>CENTAUR_REGISTER_CACHE_PTR</id> + <description> + Pointer to Secure Boot Centaur SCOM register cache + </description> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint64_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> - <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>IS_SLAVE_DRAWER</id> - <description>0 = is master node, 1 = is slave node</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> + <attribute> + <description> + Are we doing checkstop analysis on + systems as we are booting back up based + on information captured in FIRDATA section. + </description> + <id>CHKSTOP_ANALYSIS_ON_STARTUP</id> <persistency>volatile-zeroed</persistency> <readable/> + <simpleType> + <uint8_t/> + </simpleType> <writeable/> -</attribute> + </attribute> -<attribute> - <id>XSCOM_VIRTUAL_ADDR</id> - <description>Cached Virtual Address of Xscom memory space for this Chip</description> + <enumerationType> + <description>Enum for CHKSTOP_ANALYSIS_ON_STARTUP</description> + <enumerator> + <name>NOT_ANALYZING_DEFAULT</name> + <value>0</value> + </enumerator> + <enumerator> + <name>ANALYZING_CHECKSTOP</name> + <value>1</value> + </enumerator> + <id>CHKSTOP_ANALYSIS_ON_STARTUP</id> + </enumerationType> + + <attribute> + <id>CLEAR_DIMM_SPD_ENABLE</id> + <description> + Used to enable clearing of SPD on all present DIMMs. This attribute is + set via attribute override. + </description> <simpleType> - <uint64_t> - </uint64_t> + <uint8_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> - <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>FSI_MASTER_MUTEX</id> - <description>Mutex for FSI Master Operations</description> + <attribute> + <id>DRTM_PAYLOAD_ADDR_MB_HB</id> + <description> + Physical address of DRTM payload in megabytes. 0 MB is not considered to + be a valid DRTM payload address + </description> <simpleType> - <hbmutex> - </hbmutex> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> - <hbOnly/> -</attribute> + </attribute> -<attribute> + <attribute> <id>EEPROM_PAGE_ARRAY</id> <description> Used to keep track of which EEPROM page the current I2C master bus is set to @@ -180,1069 +145,1082 @@ 2 = UNKNOWN_PAGE </description> <simpleType> - <uint8_t> - <default>2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2</default> - </uint8_t> - <array>4,4</array> + <uint8_t> + <default>2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2</default> + </uint8_t> + <array>4,4</array> </simpleType> <persistency>volatile</persistency> <readable/> <writeable/> -</attribute> + </attribute> -<!-- For POD Testing --> -<attribute> - <id>HB_MUTEX_TEST_LOCK</id> - <description>Host boot mutex for testing</description> + <attribute> + <id>FORCE_PRE_PAYLOAD_DRTM</id> + <description> + If Hostboot is compiled with CONFIG_DRTM_TRIGGERING, controls + whether Hostboot will initiate a DRTM late launch sequence in place of + loading the payload. This attribute should always be compiled in not to + force the late launch sequence; it is designed to be changed via + attribute overrides only, to facilitate testing. + 0x00: Do not force a DRTM late launch sequence + 0x01: Force a DRTM late launch sequence (if not a DRTM boot) + </description> <simpleType> - <hbmutex> - </hbmutex> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + </attribute> + + <attribute> + <id>FSI_MASTER_MUTEX</id> + <description>Mutex for FSI Master Operations</description> + <simpleType> + <hbmutex/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>I2C_PAGE_MUTEX_0</id> - <description> - Mutex to protect page select operations for I2C Master engine 0 - </description> + <attribute> + <id>FSI_SCOM_MUTEX</id> + <description>Mutex for FSI-based SCOM Operations</description> <simpleType> - <hbmutex></hbmutex> + <hbmutex/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>I2C_PAGE_MUTEX_1</id> + <!-- TODO RTC 122856 When support for HB only volatile attributes with non-zero + default is implemented, update default value to match the description, + Until that happens, code must set the appropriate default if needed. --> + <attribute> + <id>HBRT_HYP_ID</id> <description> - Mutex to protect page select operations for I2C Master engine 1 - </description> + Effective ID used by the hypervisor to specify a given target. A value + of 0xFFFFFFFFFFFFFFFF means invalid/unknown. + </description> <simpleType> - <hbmutex></hbmutex> + <uint64_t> + <default>0</default> + </uint64_t> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>I2C_PAGE_MUTEX_2</id> - <description> - Mutex to protect page select operations for I2C Master engine 2 - </description> + <attribute> + <id>HB_EXISTING_IMAGE</id> + <description>Indicates which logical nodes have a hostboot image.</description> + <!-- Bit position [0-7] (left to right) represents logical node. + '1' means the logical node has an active hostboot image. + --> <simpleType> - <hbmutex></hbmutex> + <uint8_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>I2C_PAGE_MUTEX_3</id> + <attribute> + <id>HB_INITIATED_PM_RESET</id> <description> - Mutex to protect page select operations for I2C Master engine 3 + Indicates that a chip has already been put into reset elsewhere + such that the next reset request will be skipped. </description> <simpleType> - <hbmutex></hbmutex> + <uint8_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> - <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>I2C_ENGINE_MUTEX_0</id> - <description>Mutex for I2C Master engine 0</description> + <enumerationType> + <id>HB_INITIATED_PM_RESET</id> + <description>Enum for HB_INITIATED_PM_RESET</description> + <enumerator> + <!-- Default state, no extra reset has been performed --> + <name>INACTIVE</name> + <value>0</value> + </enumerator> + <enumerator> + <!-- Currently in the middle of doing an extra reset --> + <name>IN_PROGRESS</name> + <value>1</value> + </enumerator> + <enumerator> + <!-- Chip has already been reset --> + <name>COMPLETE</name> + <value>2</value> + </enumerator> + </enumerationType> + + <!-- For POD Testing --> + <attribute> + <id>HB_MUTEX_TEST_LOCK</id> + <description>Host boot mutex for testing</description> <simpleType> - <hbmutex> - </hbmutex> + <hbmutex/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>I2C_ENGINE_MUTEX_1</id> - <description>Mutex for I2C Master engine 1</description> + <attribute> + <id>HB_NODE_COMM_ABUS_MUTEX</id> + <description>Mutex to guard Node Comm ABUS register access</description> <simpleType> - <hbmutex> - </hbmutex> + <hbmutex/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>I2C_ENGINE_MUTEX_2</id> - <description>Mutex for I2C Master engine 2</description> + <attribute> + <id>HB_NODE_COMM_XBUS_MUTEX</id> + <description>Mutex to guard Node Comm XBUS register access</description> <simpleType> - <hbmutex> - </hbmutex> + <hbmutex/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>I2C_ENGINE_MUTEX_3</id> - <description>Mutex for I2C Master engine 3</description> + <attribute> + <id>HB_RSV_MEM_NEXT_SECTION</id> + <description> + The next HB reserved memory section available to assign + a new reserved memory range. + </description> <simpleType> - <hbmutex> - </hbmutex> + <uint8_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> - <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>FSI_SCOM_MUTEX</id> - <description>Mutex for FSI-based SCOM Operations</description> + <attribute> + <id>HB_SBE_SEEPROM_VERSION_MISMATCH</id> + <description> + Describes if the processor's SBE's seeprom versions match or not + 0x0 = MATCH + 0x1 = MISMATCH + </description> + <simpleType> + <uint8_t/> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + </attribute> + + <attribute> + <id>HB_TARGET_SCOMABLE</id> + <description> + This attribute indicates if the target can be SCOMed. + It's used in FSP only but declared here because the attribute + is defined in chip_attributes.xml, which is a common file + between FSP and HB (without this, HB will get a compilation error). + </description> <simpleType> - <hbmutex> - </hbmutex> + <uint8_t> + <default>0x0</default> + </uint8_t> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + <hwpfToHbAttrMap> + <id>ATTR_TARGET_SCOMABLE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> + </attribute> -<attribute> - <id>SCOM_IND_MUTEX</id> - <description>Mutex for Indirect SCOM read operation</description> + <attribute> + <id>HB_TPM_INIT_ATTEMPTED</id> + <description> + Whether TPM initialization was attempted or not + 0x00 (false) = Did not attempt to initialize TPM + 0x01 (true) = Attempted to initialize TPM + </description> <simpleType> - <hbmutex> - </hbmutex> + <uint8_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>SCAN_MUTEX</id> - <description>Mutex for SCAN operations</description> + <attribute> + <id>HB_TPM_LOG_MGR_PTR</id> + <description>Pointer to TPM log manager</description> <simpleType> - <hbmutex> - <default>0</default> - </hbmutex> + <uint64_t> + <default>0</default> + </uint64_t> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>IBSCOM_VIRTUAL_ADDR</id> - <description>Cached Virtual Address of Inband Scom memory space for this Chip</description> + <attribute> + <id>HB_TPM_MUTEX</id> + <description>Mutex to guard TPM access</description> <simpleType> - <uint64_t> - </uint64_t> + <hbmutex/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>IBSCOM_MUTEX</id> - <description>Mutex for Inband SCOM Operations</description> + <attribute> + <id>HIDDEN_ERRLOGS_ENABLE</id> + <description> + Used to decide whether or not to prevent INFORMATIONAL/RECOVERED error + logs from being sent to the BMC via SEL/eSEL, saved to the PNOR, and + displayed to the console. + 0 = Prevent INFORMATIONAL/RECOVERED error logs from being processed. + 1 = Send only INFORMATIONAL error logs. + 2 = Send only RECOVERED error logs. + 3 = Allow all hidden error logs to be processed. + </description> <simpleType> - <hbmutex> - </hbmutex> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>volatile</persistency> + <readable/> + </attribute> + + <enumerationType> + <id>HIDDEN_ERRLOGS_ENABLE</id> + <description>Enumeration of HIDDEN_ERRLOGS_ENABLE</description> + <enumerator> + <name>NO_HIDDEN_LOGS</name> + <value>0</value> + </enumerator> + <enumerator> + <name>ALLOW_INFORMATIONAL</name> + <value>1</value> + </enumerator> + <enumerator> + <name>ALLOW_RECOVERED</name> + <value>2</value> + </enumerator> + <enumerator> + <name>ALLOW_ALL_LOGS</name> + <value>3</value> + </enumerator> + </enumerationType> + + <attribute> + <id>HOMER_HCODE_LOADED</id> + <description> + Attribute to check if HCODE is loaded in HOMER + </description> + <simpleType> + <uint8_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>IBSCOM_ENABLE_OVERRIDE</id> - <description>Used to force IBSCOM enabled for lab testing</description> + <attribute> + <id>HOMER_VIRT_ADDR</id> + <description> + Virtual address where HOMER memory is mapped into. If value is zero, + memory must be mapped into virtual space. + </description> <simpleType> - <uint8_t> - </uint8_t> + <uint64_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> + <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>HB_EXISTING_IMAGE</id> - <description>Indicates which logical nodes have a hostboot image.</description> - <!-- Bit position [0-7] (left to right) represents logical node. - '1' means the logical node has an active hostboot image. - --> + <attribute> + <id>I2C_ENGINE_MUTEX_0</id> + <description>Mutex for I2C Master engine 0</description> <simpleType> - <uint8_t> - </uint8_t> + <hbmutex/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> + <attribute> + <id>I2C_ENGINE_MUTEX_1</id> + <description>Mutex for I2C Master engine 1</description> + <simpleType> + <hbmutex/> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hbOnly/> + </attribute> -<attribute> - <id>HB_TARGET_SCOMABLE</id> - <description> - This attribute indicates if the target can be SCOMed. - It's used in FSP only but declared here because the attribute - is defined in chip_attributes.xml, which is a common file - between FSP and HB (without this, HB will get a compilation error). - </description> + <attribute> + <id>I2C_ENGINE_MUTEX_2</id> + <description>Mutex for I2C Master engine 2</description> <simpleType> - <uint8_t> - <default>0x0</default> - </uint8_t> + <hbmutex/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_TARGET_SCOMABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>OCC_COMMON_AREA_PHYS_ADDR</id> - <description> - Physical address where OCC Common Area is placed in mainstore. - </description> + <attribute> + <id>I2C_ENGINE_MUTEX_3</id> + <description>Mutex for I2C Master engine 3</description> <simpleType> - <uint64_t></uint64_t> + <hbmutex/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>HOMER_VIRT_ADDR</id> + <attribute> + <id>I2C_PAGE_MUTEX_0</id> <description> - Virtual address where HOMER memory is mapped into. If value is zero, - memory must be mapped into virtual space. + Mutex to protect page select operations for I2C Master engine 0 </description> <simpleType> - <uint64_t></uint64_t> + <hbmutex/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>HOMER_HCODE_LOADED</id> + <attribute> + <id>I2C_PAGE_MUTEX_1</id> <description> - Attribute to check if HCODE is loaded in HOMER + Mutex to protect page select operations for I2C Master engine 1 </description> <simpleType> - <uint8_t></uint8_t> + <hbmutex/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<enumerationType> - <id>IPMI_SENSOR_ARRAY</id> - <description>Enumeration defining the offsets into the - IPMI_SENSORS array.</description> - <enumerator> - <name>NAME_OFFSET</name> - <value>0x00</value> - </enumerator> - <enumerator> - <name>NUMBER_OFFSET</name> - <value>0x01</value> - </enumerator> -</enumerationType> - -<enumerationType> - <id>SENSOR_NAME</id> - <description>Enumeration indicating the IPMI sensor name, which will - be used by hostboot when determining the sensor number to return. - The sensor name consists of one byte of sensor type plus one byte of - sub-type, to differentiate similar sensors under the same target. - Our implementaion uses the IPMI defined entity ID as the sub-type. - </description> - <enumerator> - <name>PROC_TEMP</name> - <value>0x0103</value> - </enumerator> - <enumerator> - <name>DIMM_TEMP</name> - <value>0x0120</value> - </enumerator> - <enumerator> - <name>CORE_TEMP</name> - <value>0x01D0</value> - </enumerator> - <enumerator> - <name>STATE</name> - <value>0x0500</value> - </enumerator> - <enumerator> - <name>MEMBUF_TEMP</name> - <value>0x01D1</value> - </enumerator> - <enumerator> - <name>GPU_TEMP</name> - <value>0x01D8</value> - </enumerator> - <enumerator> - <name>GPU_MEM_TEMP</name> - <value>0x01D9</value> - </enumerator> - <enumerator> - <name>VRM_VDD_TEMP</name> - <value>0x01DA</value> - </enumerator> - <enumerator> - <name>GPU_STATE</name> - <value>0x17D8</value> - </enumerator> - <enumerator> - <name>PROC_STATE</name> - <value>0x0703</value> - </enumerator> - <enumerator> - <name>CORE_STATE</name> - <value>0x07D0</value> - </enumerator> - <enumerator> - <name>HOST_AUTO_REBOOT_CONTROL</name> - <value>0x0921</value> - </enumerator> - <enumerator> - <name>DIMM_STATE</name> - <value>0x0C20</value> - </enumerator> - <enumerator> - <name>HB_VOLATILE</name> - <value>0x0C21</value> - </enumerator> - <enumerator> - <name>MEMBUF_STATE</name> - <value>0x0CD1</value> - </enumerator> - <enumerator> - <name>FW_BOOT_PROGRESS</name> - <value>0x0F22</value> - </enumerator> - <enumerator> - <name>SYSTEM_EVENT</name> - <value>0x1201</value> - </enumerator> - <enumerator> - <name>OS_BOOT</name> - <value>0x1F23</value> - </enumerator> - <enumerator> - <name>HOST_STATUS</name> - <value>0x2223</value> - </enumerator> - <enumerator> - <name>OCC_ACTIVE</name> - <value>0x07D2</value> - </enumerator> - <enumerator> - <name>CORE_FREQ</name> - <value>0xC1D0</value> - </enumerator> - <enumerator> - <name>APSS_CHANNEL</name> - <value>0xC2D7</value> - </enumerator> - <enumerator> - <name>PCI_ACTIVE</name> - <value>0xC423</value> - </enumerator> - <enumerator> - <name>REBOOT_COUNT</name> - <value>0xC322</value> - </enumerator> - <enumerator> - <name>FAULT</name> - <value>0xC700</value> - </enumerator> - <enumerator> - <name>BACKPLANE_FAULT</name> - <value>0xC707</value> - </enumerator> - <enumerator> - <name>REF_CLOCK_FAULT</name> - <value>0xC7D4</value> - </enumerator> - <enumerator> - <name>PCI_CLOCK_FAULT</name> - <value>0xC7D5</value> - </enumerator> - <enumerator> - <name>TOD_CLOCK_FAULT</name> - <value>0xC7D6</value> - </enumerator> - <enumerator> - <name>APSS_FAULT</name> - <value>0xC7D7</value> - </enumerator> - <!-- default callout set to BackPlane --> - <enumerator> - <name>VRM_VDD_FAULT</name> - <value>0xC707</value> - </enumerator> - <enumerator> - <name>DERATING_FACTOR</name> - <value>0xC815</value> - </enumerator> - <enumerator> - <name>REDUNDANT_PS_POLICY</name> - <value>0xCA22</value> - </enumerator> - <enumerator> - <name>TURBO_ALLOWED</name> - <value>0xCB03</value> - </enumerator> - <enumerator> - <name>TPM_REQUIRED</name> - <value>0xCC03</value> - </enumerator> -</enumerationType> - -<attribute> - <id>SBE_FFDC_ADDR</id> + <attribute> + <id>I2C_PAGE_MUTEX_2</id> <description> - Virtual address where SBE FFDC is placed in mainstore. + Mutex to protect page select operations for I2C Master engine 2 </description> <simpleType> - <uint64_t></uint64_t> + <hbmutex/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>SBE_COMM_ADDR</id> + <attribute> + <id>I2C_PAGE_MUTEX_3</id> <description> - Virtual address where SBE Communications are placed in mainstore. - This area is used for SBE message passing and may contain an SBE - command or the response to it from HBRT. + Mutex to protect page select operations for I2C Master engine 3 </description> <simpleType> - <uint64_t></uint64_t> + <hbmutex/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>SERIAL_NUMBER</id> - <description>The serial number for a particular FRU target</description> + <attribute> + <id>IBSCOM_ENABLE_OVERRIDE</id> + <description>Used to force IBSCOM enabled for lab testing</description> <simpleType> - <uint8_t> - </uint8_t> - <array>18</array> + <uint8_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SERIAL_NUMBER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>PART_NUMBER</id> - <description>The part number for a particular FRU target</description> + <attribute> + <id>IBSCOM_MUTEX</id> + <description>Mutex for Inband SCOM Operations</description> <simpleType> - <uint8_t> - </uint8_t> - <array>20</array> + <hbmutex/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PART_NUMBER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>VPD_SWITCHES</id> - <description>Attribute storing VPD state information</description> - <complexType> - <description>VPD flags</description> - <field> - <name>pnorCacheValid</name> - <description>Set when this target's VPD data has been loaded - from EEPROM into the PNOR. - </description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>pnorCacheValidRT</name> - <description>See pnorCacheValid. Allows runtime version to be - set separately from common version. - </description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>disableWriteToPnorRT</name> - <description>Set to disable write-thru to PNOR at runtime - </description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>reserved</name> - <description>Reserved for future expansion</description> - <type>uint8_t</type> - <bits>5</bits> - <default>0</default> - </field> - </complexType> + <attribute> + <id>IBSCOM_VIRTUAL_ADDR</id> + <description>Cached Virtual Address of Inband Scom memory space for this Chip</description> + <simpleType> + <uint64_t/> + </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> + <hbOnly/> + </attribute> -<attribute> - <id>SPCWKUP_COUNT</id> - <description> - Keep track of the calls to Special Wakeup. Increment for each - call to enable, decrement for each call to disable. Not - thread-safe, used at runtime which is single-threaded. + <attribute> + <id>IPC_NODE_BUFFER_GLOBAL_ADDRESS</id> + <description>Global IPC Buffer Addresseses for each Node + dimension: node number (0:7) </description> <simpleType> - <uint32_t> - </uint32_t> + <uint64_t/> + <array>8</array> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> - <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>MSS_VOLT_VPP_SLOPE_EFF_CONFIG</id> - <description>Units: uV/DRAM + <enumerationType> + <id>IPMI_SENSOR_ARRAY</id> + <description>Enumeration defining the offsets into the + IPMI_SENSORS array.</description> + <enumerator> + <name>NAME_OFFSET</name> + <value>0x00</value> + </enumerator> + <enumerator> + <name>NUMBER_OFFSET</name> + <value>0x01</value> + </enumerator> + </enumerationType> + + <attribute> + <id>IS_DRTM_MPIPL_HB</id> + <description> + Indicates if this is a DRTM MPIPL flow or not. + 0x00 = Not a DRTM MPIPL + 0x01 = DRTM MPIPL </description> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> - <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>MSS_VOLT_VPP_INTERCEPT_EFF_CONFIG</id> - <description>Units: mV - </description> + <attribute> + <id>IS_MPIPL_HB</id> + <description>1 = in Memory Preserving IPL mode. 0 = in normal IPL mode.</description> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint8_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + <hwpfToHbAttrMap> + <id>ATTR_IS_MPIPL</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> + </attribute> -<attribute> - <id>MSS_VOLT_DDR3_VDDR_SLOPE_EFF_CONFIG</id> - <description>Units: 1/Amps - </description> + <attribute> + <id>IS_SLAVE_DRAWER</id> + <description>0 = is master node, 1 = is slave node</description> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> - <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>MSS_VOLT_DDR3_VDDR_INTERCEPT_EFF_CONFIG</id> - <description>Units: mV + <attribute> + <id>MASTER_MBOX_SCRATCH</id> + <description> + Value of the master mailbox scratch regs + at the beginning of the boot. Need to save these + away since HB uses some of them for communication purposes. </description> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t/> + <array>8</array> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>MRW_DDR3_VDDR_MAX_LIMIT_EFF_CONFIG</id> - <description>Maximum voltage limit for the dynamic VID DDR3 VDDR - voltage setpoint. In mV. + <attribute> + <id>MEMD_OFFSET</id> + <description> + Working offset for MEMD section, this allows us to move between + the different MEMD instances and the MEMD header. </description> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint64_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> - <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>MSS_VOLT_DDR4_VDDR_SLOPE_EFF_CONFIG</id> - <description>Units: 1/Amps - </description> + <attribute> + <id>MPIPL_HB_MDRT_COUNT</id> + <description>Actual MDRT count in Memory Preserving IPL mode.</description> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>MSS_VOLT_DDR4_VDDR_INTERCEPT_EFF_CONFIG</id> - <description>Units: mV + <attribute> + <id>MRW_DDR3_VDDR_MAX_LIMIT_EFF_CONFIG</id> + <description>Maximum voltage limit for the dynamic VID DDR3 VDDR + voltage setpoint. In mV. </description> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> + <attribute> <id>MRW_DDR4_VDDR_MAX_LIMIT_EFF_CONFIG</id> <description>Maximum voltage limit for the dynamic VID DDR4 VDDR voltage setpoint. In mV. </description> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>CLEAR_DIMM_SPD_ENABLE</id> - <description> - Used to enable clearing of SPD on all present DIMMs. This attribute is - set via attribute override. + <attribute> + <id>MSS_VOLT_DDR3_VDDR_INTERCEPT_EFF_CONFIG</id> + <description>Units: mV </description> <simpleType> - <uint8_t></uint8_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> + <hbOnly/> + </attribute> -<attribute> - <id>WOF_FREQUENCY_UPLIFT_SELECTED</id> - <description> - The selected WOF frequency uplift table. - </description> - <simpleType> - <uint16_t> - </uint16_t> - <array>22,13</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hbOnly/> -</attribute> - -<!-- TODO RTC 122856 When support for HB only volatile attributes with non-zero - default is implemented, update default value to match the description, - Until that happens, code must set the appropriate default if needed. --> -<attribute> - <id>HBRT_HYP_ID</id> - <description> - Effective ID used by the hypervisor to specify a given target. A value - of 0xFFFFFFFFFFFFFFFF means invalid/unknown. - </description> - <simpleType> - <uint64_t> - <default>0</default> - </uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hbOnly/> -</attribute> - -<attribute> - <id>IS_DRTM_MPIPL_HB</id> - <description> - Indicates if this is a DRTM MPIPL flow or not. - 0x00 = Not a DRTM MPIPL - 0x01 = DRTM MPIPL + <attribute> + <id>MSS_VOLT_DDR3_VDDR_SLOPE_EFF_CONFIG</id> + <description>Units: 1/Amps </description> <simpleType> - <uint8_t><default>0</default></uint8_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> + <hbOnly/> + </attribute> -<attribute> - <id>DRTM_PAYLOAD_ADDR_MB_HB</id> - <description> - Physical address of DRTM payload in megabytes. 0 MB is not considered to - be a valid DRTM payload address + <attribute> + <id>MSS_VOLT_DDR4_VDDR_INTERCEPT_EFF_CONFIG</id> + <description>Units: mV </description> <simpleType> - <uint32_t><default>0</default></uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> + <hbOnly/> + </attribute> -<attribute> - <id>FORCE_PRE_PAYLOAD_DRTM</id> - <description> - If Hostboot is compiled with CONFIG_DRTM_TRIGGERING, controls - whether Hostboot will initiate a DRTM late launch sequence in place of - loading the payload. This attribute should always be compiled in not to - force the late launch sequence; it is designed to be changed via - attribute overrides only, to facilitate testing. - 0x00: Do not force a DRTM late launch sequence - 0x01: Force a DRTM late launch sequence (if not a DRTM boot) + <attribute> + <id>MSS_VOLT_DDR4_VDDR_SLOPE_EFF_CONFIG</id> + <description>Units: 1/Amps </description> <simpleType> - <uint8_t><default>0</default></uint8_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> -</attribute> + <writeable/> + <hbOnly/> + </attribute> -<attribute> - <id>ATTN_CHK_ALL_PROCS</id> - <description> - Used to tell ATTN code whether to chk MASTER(0) OR all PROCs(1) - when the checkForIplAttns routine is called. + <attribute> + <id>MSS_VOLT_VPP_INTERCEPT_EFF_CONFIG</id> + <description>Units: mV </description> <simpleType> - <uint8_t></uint8_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> + <hbOnly/> + </attribute> -<attribute> - <id>MASTER_MBOX_SCRATCH</id> - <description> - Value of the master mailbox scratch regs - at the beginning of the boot. Need to save these - away since HB uses some of them for communication purposes. + <attribute> + <id>MSS_VOLT_VPP_SLOPE_EFF_CONFIG</id> + <description>Units: uV/DRAM </description> <simpleType> - <uint32_t></uint32_t> - <array>8</array> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>HB_RSV_MEM_NEXT_SECTION</id> + <attribute> + <id>OCC_COMMON_AREA_PHYS_ADDR</id> <description> - The next HB reserved memory section available to assign - a new reserved memory range. + Physical address where OCC Common Area is placed in mainstore. </description> <simpleType> - <uint8_t></uint8_t> + <uint64_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> - -<!-- TPM Attributes --> + <hbOnly/> + </attribute> -<attribute> - <id>HB_TPM_INIT_ATTEMPTED</id> - <description> - Whether TPM initialization was attempted or not - 0x00 (false) = Did not attempt to initialize TPM - 0x01 (true) = Attempted to initialize TPM - </description> + <attribute> + <id>PART_NUMBER</id> + <description>The part number for a particular FRU target</description> <simpleType> - <uint8_t></uint8_t> + <uint8_t/> + <array>20</array> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> - -<enumerationType> - <id>TPM_ROLE</id> - <description> - Enumeration of possible roles a TPM can play within a node. A TPM has - the primary role if it's connected to the acting master processor, - otherwise it has the backup role. - </description> - <enumerator> - <name>TPM_PRIMARY</name> - <value>0</value> - </enumerator> - <enumerator> - <name>TPM_BACKUP</name> - <value>1</value> - </enumerator> -</enumerationType> + <hwpfToHbAttrMap> + <id>ATTR_PART_NUMBER</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> + </attribute> -<attribute> - <id>TPM_ROLE</id> + <attribute> + <id>SBE_COMM_ADDR</id> <description> - Whether the TPM is primary or backup within its parent node. It is - dynamically computed during the boot. + Virtual address where SBE Communications are placed in mainstore. + This area is used for SBE message passing and may contain an SBE + command or the response to it from HBRT. </description> <simpleType> - <uint8_t></uint8_t> + <uint64_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>HB_TPM_MUTEX</id> - <description>Mutex to guard TPM access</description> + <attribute> + <id>SBE_FFDC_ADDR</id> + <description> + Virtual address where SBE FFDC is placed in mainstore. + </description> <simpleType> - <hbmutex> - </hbmutex> + <uint64_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>HB_TPM_LOG_MGR_PTR</id> - <description>Pointer to TPM log manager</description> + <attribute> + <id>SCAN_MUTEX</id> + <description>Mutex for SCAN operations</description> <simpleType> - <uint64_t> - <default>0</default> - </uint64_t> + <hbmutex> + <default>0</default> + </hbmutex> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>ALLOW_ATTR_OVERRIDES_IN_SECURE_MODE</id> - <description> - Indicates if Attribute Overrides are allowed when the system is booted - in secure mode. The default is 0x0, where attribute overrides are not - allowed. However, the SBE can read mailbox scratch register 3 bit 7 - to set it to 0x1, meaning that attribute overrides are allowed. The SBE - passes this information up to hostboot via the bootloader. - 0x00 = Attribute Overrides are not allowed (default) - 0x01 = Attribute Overrides are allowed - </description> + <attribute> + <id>SCOM_IND_MUTEX</id> + <description>Mutex for Indirect SCOM read operation</description> <simpleType> - <uint8_t> - <default>0x00</default> - </uint8_t> + <hbmutex/> </simpleType> <persistency>volatile-zeroed</persistency> - <writeable/> <readable/> + <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>MEMD_OFFSET</id> - <description> - Working offset for MEMD section, this allows us to move between - the different MEMD instances and the MEMD header. + <enumerationType> + <id>SENSOR_NAME</id> + <description>Enumeration indicating the IPMI sensor name, which will + be used by hostboot when determining the sensor number to return. + The sensor name consists of one byte of sensor type plus one byte of + sub-type, to differentiate similar sensors under the same target. + Our implementaion uses the IPMI defined entity ID as the sub-type. </description> + <enumerator> + <name>PROC_TEMP</name> + <value>0x0103</value> + </enumerator> + <enumerator> + <name>DIMM_TEMP</name> + <value>0x0120</value> + </enumerator> + <enumerator> + <name>CORE_TEMP</name> + <value>0x01D0</value> + </enumerator> + <enumerator> + <name>STATE</name> + <value>0x0500</value> + </enumerator> + <enumerator> + <name>MEMBUF_TEMP</name> + <value>0x01D1</value> + </enumerator> + <enumerator> + <name>GPU_TEMP</name> + <value>0x01D8</value> + </enumerator> + <enumerator> + <name>GPU_MEM_TEMP</name> + <value>0x01D9</value> + </enumerator> + <enumerator> + <name>VRM_VDD_TEMP</name> + <value>0x01DA</value> + </enumerator> + <enumerator> + <name>GPU_STATE</name> + <value>0x17D8</value> + </enumerator> + <enumerator> + <name>PROC_STATE</name> + <value>0x0703</value> + </enumerator> + <enumerator> + <name>CORE_STATE</name> + <value>0x07D0</value> + </enumerator> + <enumerator> + <name>HOST_AUTO_REBOOT_CONTROL</name> + <value>0x0921</value> + </enumerator> + <enumerator> + <name>DIMM_STATE</name> + <value>0x0C20</value> + </enumerator> + <enumerator> + <name>HB_VOLATILE</name> + <value>0x0C21</value> + </enumerator> + <enumerator> + <name>MEMBUF_STATE</name> + <value>0x0CD1</value> + </enumerator> + <enumerator> + <name>FW_BOOT_PROGRESS</name> + <value>0x0F22</value> + </enumerator> + <enumerator> + <name>SYSTEM_EVENT</name> + <value>0x1201</value> + </enumerator> + <enumerator> + <name>OS_BOOT</name> + <value>0x1F23</value> + </enumerator> + <enumerator> + <name>HOST_STATUS</name> + <value>0x2223</value> + </enumerator> + <enumerator> + <name>OCC_ACTIVE</name> + <value>0x07D2</value> + </enumerator> + <enumerator> + <name>CORE_FREQ</name> + <value>0xC1D0</value> + </enumerator> + <enumerator> + <name>APSS_CHANNEL</name> + <value>0xC2D7</value> + </enumerator> + <enumerator> + <name>PCI_ACTIVE</name> + <value>0xC423</value> + </enumerator> + <enumerator> + <name>REBOOT_COUNT</name> + <value>0xC322</value> + </enumerator> + <enumerator> + <name>FAULT</name> + <value>0xC700</value> + </enumerator> + <enumerator> + <name>BACKPLANE_FAULT</name> + <value>0xC707</value> + </enumerator> + <enumerator> + <name>REF_CLOCK_FAULT</name> + <value>0xC7D4</value> + </enumerator> + <enumerator> + <name>PCI_CLOCK_FAULT</name> + <value>0xC7D5</value> + </enumerator> + <enumerator> + <name>TOD_CLOCK_FAULT</name> + <value>0xC7D6</value> + </enumerator> + <enumerator> + <name>APSS_FAULT</name> + <value>0xC7D7</value> + </enumerator> + <!-- default callout set to BackPlane --> + <enumerator> + <name>VRM_VDD_FAULT</name> + <value>0xC707</value> + </enumerator> + <enumerator> + <name>DERATING_FACTOR</name> + <value>0xC815</value> + </enumerator> + <enumerator> + <name>REDUNDANT_PS_POLICY</name> + <value>0xCA22</value> + </enumerator> + <enumerator> + <name>TURBO_ALLOWED</name> + <value>0xCB03</value> + </enumerator> + <enumerator> + <name>TPM_REQUIRED</name> + <value>0xCC03</value> + </enumerator> + </enumerationType> + + <attribute> + <id>SERIAL_NUMBER</id> + <description>The serial number for a particular FRU target</description> <simpleType> - <uint64_t></uint64_t> + <uint8_t/> + <array>18</array> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> + <hbOnly/> + <hwpfToHbAttrMap> + <id>ATTR_SERIAL_NUMBER</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> + </attribute> -<attribute> - <id>CENTAUR_REGISTER_CACHE_PTR</id> + <attribute> + <id>SPCWKUP_COUNT</id> <description> - Pointer to Secure Boot Centaur SCOM register cache + Keep track of the calls to Special Wakeup. Increment for each + call to enable, decrement for each call to disable. Not + thread-safe, used at runtime which is single-threaded. </description> <simpleType> - <uint64_t></uint64_t> + <uint32_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> + <hbOnly/> + </attribute> -<attribute> - <id>IPC_NODE_BUFFER_GLOBAL_ADDRESS</id> - <description>Global IPC Buffer Addresseses for each Node - dimension: node number (0:7) + <enumerationType> + <id>TPM_ROLE</id> + <description> + Enumeration of possible roles a TPM can play within a node. A TPM has + the primary role if it's connected to the acting master processor, + otherwise it has the backup role. </description> - <simpleType> - <uint64_t></uint64_t> - <array>8</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable /> - <writeable /> -</attribute> + <enumerator> + <name>TPM_PRIMARY</name> + <value>0</value> + </enumerator> + <enumerator> + <name>TPM_BACKUP</name> + <value>1</value> + </enumerator> + </enumerationType> -<attribute> - <id>HB_NODE_COMM_XBUS_MUTEX</id> - <description>Mutex to guard Node Comm XBUS register access</description> + <attribute> + <id>TPM_ROLE</id> + <description> + Whether the TPM is primary or backup within its parent node. It is + dynamically computed during the boot. + </description> <simpleType> - <hbmutex> - </hbmutex> + <uint8_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>HB_NODE_COMM_ABUS_MUTEX</id> - <description>Mutex to guard Node Comm ABUS register access</description> - <simpleType> - <hbmutex> - </hbmutex> - </simpleType> + <attribute> + <id>VPD_SWITCHES</id> + <description>Attribute storing VPD state information</description> + <complexType> + <description>VPD flags</description> + <field> + <name>pnorCacheValid</name> + <description>Set when this target's VPD data has been loaded + from EEPROM into the PNOR. + </description> + <type>uint8_t</type> + <bits>1</bits> + <default>0</default> + </field> + <field> + <name>pnorCacheValidRT</name> + <description>See pnorCacheValid. Allows runtime version to be + set separately from common version. + </description> + <type>uint8_t</type> + <bits>1</bits> + <default>0</default> + </field> + <field> + <name>disableWriteToPnorRT</name> + <description>Set to disable write-thru to PNOR at runtime + </description> + <type>uint8_t</type> + <bits>1</bits> + <default>0</default> + </field> + <field> + <name>reserved</name> + <description>Reserved for future expansion</description> + <type>uint8_t</type> + <bits>5</bits> + <default>0</default> + </field> + </complexType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> - <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>HB_SBE_SEEPROM_VERSION_MISMATCH</id> + <attribute> + <id>WOF_FREQUENCY_UPLIFT_SELECTED</id> <description> - Describes if the processor's SBE's seeprom versions match or not - 0x0 = MATCH - 0x1 = MISMATCH - </description> + The selected WOF frequency uplift table. + </description> <simpleType> - <uint8_t> - </uint8_t> + <uint16_t/> + <array>22,13</array> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> + <hbOnly/> + </attribute> -<attribute> - <id>HB_INITIATED_PM_RESET</id> - <description> - Indicates that a chip has already been put into reset elsewhere - such that the next reset request will be skipped. - </description> + <attribute> + <id>XSCOM_VIRTUAL_ADDR</id> + <description>Cached Virtual Address of Xscom memory space for this Chip</description> <simpleType> - <uint8_t/> + <uint64_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> - -<enumerationType> - <id>HB_INITIATED_PM_RESET</id> - <description>Enum for HB_INITIATED_PM_RESET</description> - <enumerator> - <!-- Default state, no extra reset has been performed --> - <name>INACTIVE</name> - <value>0</value> - </enumerator> - <enumerator> - <!-- Currently in the middle of doing an extra reset --> - <name>IN_PROGRESS</name> - <value>1</value> - </enumerator> - <enumerator> - <!-- Chip has already been reset --> - <name>COMPLETE</name> - <value>2</value> - </enumerator> -</enumerationType> + <hbOnly/> + </attribute> </attributes> diff --git a/src/usr/targeting/common/xmltohb/attribute_types_openpower.xml b/src/usr/targeting/common/xmltohb/attribute_types_openpower.xml index ba995a93a..99aa13feb 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types_openpower.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types_openpower.xml @@ -22,8 +22,6 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<attributes> - <!-- ===================================================================== Contains the definition of attributes that are only available on openpower systems. This file is only compiled when @@ -31,179 +29,365 @@ FSP based systems. ===================================================================== --> - -<attribute> +<attributes> + <attribute> <id>ADC_CHANNEL_FUNC_IDS</id> <description>ADC Channel function id. 16 channels.</description> <simpleType> - <uint8_t></uint8_t> - <array>16</array> + <uint8_t/> + <array>16</array> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>ADC_CHANNEL_SENSOR_NUMBERS</id> - <description>ADC Channel IPMI sensor numbers. 16 channels.</description> + <attribute> + <id>ADC_CHANNEL_GAINS</id> + <description>ADC channel gain * 1000. 16 channels.</description> <simpleType> - <uint32_t></uint32_t> - <array>16</array> + <uint32_t/> + <array>16</array> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> + <attribute> <id>ADC_CHANNEL_GNDS</id> <description>ADC Channel ground. 16 channels.</description> <simpleType> - <uint8_t></uint8_t> - <array>16</array> + <uint8_t/> + <array>16</array> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>ADC_CHANNEL_GAINS</id> - <description>ADC channel gain * 1000. 16 channels.</description> + <attribute> + <id>ADC_CHANNEL_OFFSETS</id> + <description>ADC channel offset * 1000. 16 channels</description> <simpleType> - <uint32_t></uint32_t> - <array>16</array> + <uint32_t/> + <array>16</array> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>ADC_CHANNEL_OFFSETS</id> - <description>ADC channel offset * 1000. 16 channels</description> + <attribute> + <id>ADC_CHANNEL_SENSOR_NUMBERS</id> + <description>ADC Channel IPMI sensor numbers. 16 channels.</description> <simpleType> - <uint32_t></uint32_t> - <array>16</array> + <uint32_t/> + <array>16</array> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> + <attribute> + <id>ALLOW_CALLHOME_ESELS_TO_BMC</id> + <description>Flag used to allow sending informational call-home errors as ESELS to the BMC</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + </attribute> + + <attribute> <id>APSS_GPIO_PORT_MODES</id> <description>APSS GPIO PORT MODES</description> <simpleType> - <uint8_t></uint8_t> - <array>2</array> + <uint8_t/> + <array>2</array> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> + <attribute> <id>APSS_GPIO_PORT_PINS</id> <description>APSS GPIO PORT PINS Port0 pin 0-7 Port1 pin 8-15 </description> <simpleType> - <uint8_t></uint8_t> - <array>16</array> + <uint8_t/> + <array>16</array> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> + <attribute> + <id>BMC_HW_CHIP_TYPE</id> + <description>The type of hardware of the BMC</description> + <simpleType> + <string> + <default>ast2500</default> + <sizeInclNull>32</sizeInclNull> + </string> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + </attribute> + + <attribute> + <id>BMC_MANUFACTURER</id> + <description>The manufacturer of the BMC</description> + <simpleType> + <string> + <default>ibm</default> + <sizeInclNull>32</sizeInclNull> + </string> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + </attribute> + + <attribute> + <id>BMC_MAX_ERROR_LOG_SIZE</id> + <description>max size of error log that can be sent to BMC</description> + <simpleType> + <uint32_t> + <default>2048</default> + </uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + </attribute> + + <attribute> + <id>BMC_SW_TYPE</id> + <description>The software type of the BMC</description> + <simpleType> + <string> + <default>openbmc</default> + <sizeInclNull>32</sizeInclNull> + </string> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + </attribute> + + <attribute> + <id>CALCULATED_MAX_SYS_POWER_EXCLUDING_GPUS</id> + <description> + HTMGT calculates the total non-GPU maximum power in W when the + CPUs are at max frequency and memory at max power (least throttled) + and then adds MISC_SYSTEM_COMPONENTS_MAX_POWER_WATTS + </description> + <simpleType> + <uint16_t> + <default>0x0000</default> + </uint16_t> + </simpleType> + <persistency>volatile</persistency> + <readable/> + <writeable/> + </attribute> + + <attribute> + <id>CALCULATED_PROC_MEMORY_POWER_DROP</id> + <description> + HTMGT calculates the total processor/memory power drop in W when the + CPUs are at min frequency and memory at min power (most throttled). + This is the how much CALCULATED_MAX_SYS_POWER_EXCLUDING_GPUS + can be reduced by. + </description> + <simpleType> + <uint16_t> + <default>0x0000</default> + </uint16_t> + </simpleType> + <persistency>volatile</persistency> + <readable/> + <writeable/> + </attribute> + + <enumerationType> + <id>ENTITY_ID</id> + <description>Enumeration indicating the IPMI entity ID, these values are + defined in the IPMI specification. These values will be used in place + of target type when events are sent to the BMC.</description> + <enumerator> + <name>NA</name> + <value>0</value> + </enumerator> + <enumerator> + <name>OTHER</name> + <value>0x01</value> + </enumerator> + <enumerator> + <name>PROCESSOR</name> + <value>0x03</value> + </enumerator> + <enumerator> + <name>SYSTEM_BOARD</name> + <value>0x07</value> + </enumerator> + <enumerator> + <name>POWER_MGMT</name> + <value>0x15</value> + </enumerator> + <enumerator> + <name>CHASSIS</name> + <value>0x17</value> + </enumerator> + <enumerator> + <name>MEMORY_DEVICE</name> + <value>0x20</value> + </enumerator> + <enumerator> + <name>SYS_MGMT_SOFTWARE</name> + <value>0x21</value> + </enumerator> + <enumerator> + <name>BIOS</name> + <value>0x22</value> + </enumerator> + <enumerator> + <name>OS</name> + <value>0x23</value> + </enumerator> + <enumerator> + <name>CORE</name> + <value>0xD0</value> + </enumerator> + <enumerator> + <name>MEMBUF</name> + <value>0xD1</value> + </enumerator> + <enumerator> + <name>OCC</name> + <value>0xD2</value> + </enumerator> + <enumerator> + <name>REF_CLOCK</name> + <value>0xD4</value> + </enumerator> + <enumerator> + <name>PCI_CLOCK</name> + <value>0xD5</value> + </enumerator> + <enumerator> + <name>TOD_CLOCK</name> + <value>0xD6</value> + </enumerator> + <enumerator> + <name>APSS</name> + <value>0xD7</value> + </enumerator> + <enumerator> + <name>GPU_CORE</name> + <value>0xD8</value> + </enumerator> + <enumerator> + <name>GPU_MEMORY</name> + <value>0xD9</value> + </enumerator> + </enumerationType> + + <attribute> <id>GPIO_INFO</id> <description>Information needed to address GPIO device</description> <complexType> - <description>Structure to define the addessing for an I2C + <description>Structure to define the addessing for an I2C slave device.</description> - <field> - <name>i2cMasterPath</name> - <description>Entity path to the chip that contains the I2C + <field> + <name>i2cMasterPath</name> + <description>Entity path to the chip that contains the I2C master</description> - <type>EntityPath</type> - <default>physical:sys-0</default> - </field> - <field> - <name>port</name> - <description>Port from the I2C Master device. This is a 6-bit + <type>EntityPath</type> + <default>physical:sys-0</default> + </field> + <field> + <name>port</name> + <description>Port from the I2C Master device. This is a 6-bit value.</description> - <type>uint8_t</type> - <default>0</default> - </field> - <field> - <name>devAddr</name> - <description>Device address on the I2C bus. This is a 7-bit value, + <type>uint8_t</type> + <default>0</default> + </field> + <field> + <name>devAddr</name> + <description>Device address on the I2C bus. This is a 7-bit value, but then shifted 1 bit left.</description> - <type>uint8_t</type> - <default>0</default> - </field> - <field> - <name>engine</name> - <description>I2C master engine. This is a 2-bit + <type>uint8_t</type> + <default>0</default> + </field> + <field> + <name>engine</name> + <description>I2C master engine. This is a 2-bit value.</description> - <type>uint8_t</type> - <default>0</default> - </field> - <field> - <name>vddrPin</name> - <description> + <type>uint8_t</type> + <default>0</default> + </field> + <field> + <name>vddrPin</name> + <description> Logical GPIO pin number used to enabled/disable VDDR </description> - <type>uint8_t</type> - <default>0</default> - </field> + <type>uint8_t</type> + <default>0</default> + </field> </complexType> <persistency>non-volatile</persistency> <readable/> -</attribute> - -<attribute> - <id>HDAT_I2C_ENGINE</id> - <description> - This attribute holds the values of the I2C Engine from the i2c device - connections as defined in the MRW. It is parsed into a struct in i2c.C - </description> - <simpleType> - <uint8_t></uint8_t> - <array>32</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>HDAT_I2C_MASTER_PORT</id> - <description> - This attribute holds the values of the I2C Master Port from the i2c - device connections as defined in the MRW. It is parsed into a - struct in i2c.C + <attribute> + <id>GPU_SENSORS</id> + <description>Attribute to hold 3 possible GPU sensors. + Includes sensor types, ids, and OBUS_CFG bits </description> <simpleType> - <uint8_t></uint8_t> - <array>32</array> + <uint16_t/> + <array>3,7</array> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + <no_export/> + </attribute> -<attribute> - <id>HDAT_I2C_DEVICE_TYPE</id> + <enumerationType> + <id>GPU_SENSOR_ARRAY</id> <description> - This attribute holds the values of the I2C device type from the i2c - device connections as defined in the MRW. It is parsed into a - struct in i2c.C + Enumeration defining the offsets into the GPU_SENSORS array. </description> - <simpleType> - <uint8_t></uint8_t> - <array>32</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + <enumerator> + <name>FUNC_OFFSET</name> + <value>0x00</value> + </enumerator> + <enumerator> + <name>FUNC_ID_OFFSET</name> + <value>0x01</value> + </enumerator> + <enumerator> + <name>TEMP_OFFSET</name> + <value>0x02</value> + </enumerator> + <enumerator> + <name>TEMP_ID_OFFSET</name> + <value>0x03</value> + </enumerator> + <enumerator> + <name>MEM_TEMP_OFFSET</name> + <value>0x04</value> + </enumerator> + <enumerator> + <name>MEM_TEMP_ID_OFFSET</name> + <value>0x05</value> + </enumerator> + <enumerator> + <name>OBUS_CFG_OFFSET</name> + <value>0x06</value> + </enumerator> + </enumerationType> -<attribute> + <attribute> <id>HDAT_I2C_ADDR</id> <description> This attribute holds the values of the I2C address from the i2c @@ -211,44 +395,46 @@ struct in i2c.C </description> <simpleType> - <uint8_t></uint8_t> - <array>32</array> + <uint8_t/> + <array>32</array> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>HDAT_I2C_SLAVE_PORT</id> + <attribute> + <id>HDAT_I2C_BUS_FREQ</id> <description> - This attribute holds the values of the I2C slave port from the i2c - device connections as defined in the MRW. It is parsed into a - struct in i2c.C + This attribute holds the values of the I2C bus frequency in Hz from + the i2c device connections as defined in the MRW. It is parsed + into a struct in i2c.C </description> <simpleType> - <uint8_t></uint8_t> - <array>32</array> + <uint32_t/> + <array>32</array> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>HDAT_I2C_BUS_FREQ</id> + <attribute> + <id>HDAT_I2C_DEVICE_LABEL</id> <description> - This attribute holds the values of the I2C bus frequency in Hz from - the i2c device connections as defined in the MRW. It is parsed - into a struct in i2c.C + This attribute holds the string descriptions of the I2C devices from + the i2c device connections as defined in the MRW. It is parsed into + a struct in i2c.C </description> <simpleType> - <uint32_t></uint32_t> - <array>32</array> + <string> + <sizeInclNull>64</sizeInclNull> + </string> + <array>32</array> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> + <attribute> <id>HDAT_I2C_DEVICE_PURPOSE</id> <description> This attribute holds the values of the I2C device purpose from the i2c @@ -256,1071 +442,876 @@ struct in i2c.C </description> <simpleType> - <uint8_t></uint8_t> - <array>32</array> + <uint8_t/> + <array>32</array> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>HDAT_I2C_DEVICE_LABEL</id> + <attribute> + <id>HDAT_I2C_DEVICE_TYPE</id> <description> - This attribute holds the string descriptions of the I2C devices from - the i2c device connections as defined in the MRW. It is parsed into - a struct in i2c.C + This attribute holds the values of the I2C device type from the i2c + device connections as defined in the MRW. It is parsed into a + struct in i2c.C </description> <simpleType> - <string> - <sizeInclNull>64</sizeInclNull> - </string> - <array>32</array> + <uint8_t/> + <array>32</array> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> + <attribute> <id>HDAT_I2C_ELEMENTS</id> <description> This attribute holds the number of elements that were found under this particular target, and how many devices are stored in the arrays. </description> <simpleType> - <uint8_t><default>0</default></uint8_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>IPMI_INSTANCE</id> - <description>Holds the IPMI instance number for this entity.</description> + <attribute> + <id>HDAT_I2C_ENGINE</id> + <description> + This attribute holds the values of the I2C Engine from the i2c device + connections as defined in the MRW. It is parsed into a struct in i2c.C + </description> <simpleType> - <uint32_t> - </uint32_t> + <uint8_t/> + <array>32</array> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>IPMI_SENSORS</id> - <description>Attribute to hold 16 pairs of sensor name, sensor number - pairs. A sensor name consists of one byte of general sensor type - and one byte of sub-type</description> + <attribute> + <id>HDAT_I2C_MASTER_PORT</id> + <description> + This attribute holds the values of the I2C Master Port from the i2c + device connections as defined in the MRW. It is parsed into a + struct in i2c.C + </description> <simpleType> - <uint16_t></uint16_t> - <array>16,2</array> + <uint8_t/> + <array>32</array> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<enumerationType> - <id>GPU_SENSOR_ARRAY</id> + <attribute> + <id>HDAT_I2C_SLAVE_PORT</id> <description> - Enumeration defining the offsets into the GPU_SENSORS array. - </description> - <enumerator> - <name>FUNC_OFFSET</name> - <value>0x00</value> - </enumerator> - <enumerator> - <name>FUNC_ID_OFFSET</name> - <value>0x01</value> - </enumerator> - <enumerator> - <name>TEMP_OFFSET</name> - <value>0x02</value> - </enumerator> - <enumerator> - <name>TEMP_ID_OFFSET</name> - <value>0x03</value> - </enumerator> - <enumerator> - <name>MEM_TEMP_OFFSET</name> - <value>0x04</value> - </enumerator> - <enumerator> - <name>MEM_TEMP_ID_OFFSET</name> - <value>0x05</value> - </enumerator> - <enumerator> - <name>OBUS_CFG_OFFSET</name> - <value>0x06</value> - </enumerator> -</enumerationType> - -<attribute> - <id>GPU_SENSORS</id> - <description>Attribute to hold 3 possible GPU sensors. - Includes sensor types, ids, and OBUS_CFG bits + This attribute holds the values of the I2C slave port from the i2c + device connections as defined in the MRW. It is parsed into a + struct in i2c.C </description> <simpleType> - <uint16_t></uint16_t> - <array>3,7</array> + <uint8_t/> + <array>32</array> </simpleType> <persistency>non-volatile</persistency> <readable/> - <no_export/> -</attribute> - + </attribute> -<attribute> - <id>OP_TRACE_LITE</id> - <description> - Enable Trace lite on openpower. + <attribute> + <id>HTMGT_INTERNAL_FLAGS</id> + <description>HTMGT internal flags </description> <simpleType> - <uint8_t> - <default></default> - </uint8_t> + <uint32_t> + <default>0x00000000</default> + </uint32_t> + </simpleType> + <persistency>volatile</persistency> + <readable/> + <writeable/> + </attribute> + + <attribute> + <id>HTMGT_SAFEMODE</id> + <description>1 = in safemode. 0 = in normal mode.</description> + <simpleType> + <uint8_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>OPEN_POWER_DIMM_THROTTLE_TEMP_DEG_C</id> - <description> - DIMM temperature threshold where throttling will - occur in degrees C + <attribute> + <id>HTMGT_SAVED_POWER_LIMIT</id> + <description>User power limit information from the BMC to be used if + communication with the BMC is lost after system is powered on. + Used internally by HTMGT. </description> <simpleType> - <uint64_t></uint64_t> + <uint32_t/> </simpleType> - <persistency>non-volatile</persistency> + <persistency>volatile-zeroed</persistency> <readable/> -</attribute> + <writeable/> + </attribute> -<attribute> - <id>OPEN_POWER_DIMM_ERROR_TEMP_DEG_C</id> - <description> - DIMM temperature where an error will be generated - in degrees C - </description> + <attribute> + <id>IPMI_INSTANCE</id> + <description>Holds the IPMI instance number for this entity.</description> <simpleType> - <uint64_t></uint64_t> + <uint32_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>OPEN_POWER_MEMCTRL_THROTTLE_TEMP_DEG_C</id> - <description> - Memory controller temperature threshold - where throttling will occur in degrees C - </description> + <!-- IPMI Sensor numbers are defined in the IPMI spec as 8 bit values. However +in the hostboot code they will be defined as a uint16_t to allow us to add +additonal information. An example relates to error logs returned by the OCC, +we might want to pass the Entity ID in the upper byte of the sensor ID, this +would allow hostboot to search only the target type identifed by the Entity +ID for the sensor number returned with the elog. --> + <!-- attribute to hold 16 pairs of sensor type, sensor number values --> + <attribute> + <id>IPMI_MAX_BUFFER_SIZE</id> + <description>max buffer size to use for ipmi messages</description> + <simpleType> + <uint32_t/> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hbOnly/> + </attribute> + + <attribute> + <id>IPMI_SENSORS</id> + <description>Attribute to hold 16 pairs of sensor name, sensor number + pairs. A sensor name consists of one byte of general sensor type + and one byte of sub-type</description> <simpleType> - <uint64_t></uint64_t> + <uint16_t/> + <array>16,2</array> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>OPEN_POWER_PROC_WEIGHT</id> + <attribute> + <id>IS_MPIPL_SUPPORTED</id> <description> - Weight factor (in 1/10ths) for each core DTS to calculate a core - temperature. + Specifies if the mpipl is supported on this platform + 0 : No , 1 : Yes </description> <simpleType> - <uint64_t></uint64_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>OPEN_POWER_QUAD_WEIGHT</id> + <attribute> + <id>MAX_VDD_CURRENT_READING</id> <description> - Weight factor (in 1/10ths) for each quad (cache) DTS to calculate a core - temperature. + Maximum theoretical Vdd current reading in 10mA units. + Used when VDD_CURRENT_OVERFLOW_WORKAROUND_ENABLE is set. </description> <simpleType> - <uint64_t></uint64_t> + <uint16_t> + <default>0x0000</default> + </uint16_t> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>OPEN_POWER_PROC_DVFS_TEMP_DEG_C</id> + <attribute> + <id>MISC_SYSTEM_COMPONENTS_MAX_POWER_WATTS</id> <description> - Processor temperature where DVFS will occur in degrees C + Power used by components other than CPU, memory, + or GPUs in Watts </description> <simpleType> - <uint64_t></uint64_t> + <uint16_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>OPEN_POWER_MEMCTRL_ERROR_TEMP_DEG_C</id> + <attribute> + <id>MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP</id> <description> - Memory controller temperature where an error will occur - in degrees C + Machine Readable Workbook safe mode throttle value for + numerator cfg_nm_n_per_chip </description> <simpleType> - <uint64_t></uint64_t> + <uint32_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>OPEN_POWER_N_BULK_POWER_LIMIT_WATTS</id> + <attribute> + <id>MSS_UTIL_N_PER_MBA</id> <description> - N mode bulk power supply limit in Watts + cfg_nm_n_per_mba throttle N value that was calculated from + MSS_DATABUS_UTIL_PER_MBA </description> <simpleType> - <uint64_t></uint64_t> + <uint32_t/> </simpleType> - <persistency>non-volatile</persistency> + <persistency>volatile-zeroed</persistency> <readable/> -</attribute> + <writeable/> + </attribute> -<attribute> - <id>OPEN_POWER_N_MAX_MEM_POWER_WATTS</id> + <attribute> + <id>NO_APSS_PROC_POWER_VCS_VIO_WATTS</id> <description> - Maximum power allocated to DIMMs in Watts + A constant power (in watts) that the OCC is to add onto Vdd and Vdn + power to represent any processor part that is not measured(i.e.Vcs,Vio) + This is used by the OCC to calculate a total processor socket power. </description> <simpleType> - <uint64_t></uint64_t> + <uint16_t> + <default>0</default> + </uint16_t> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>MISC_SYSTEM_COMPONENTS_MAX_POWER_WATTS</id> + <attribute> + <id>N_PLUS_ONE_MEM_POWER</id> <description> - Power used by components other than CPU, memory, - or GPUs in Watts + Maximum memory power in centiWatts with throttle + set to nominal/turbo </description> <simpleType> - <uint16_t></uint16_t> + <uint32_t> + <default>0,0</default> + </uint32_t> + <array>2</array> </simpleType> - <persistency>non-volatile</persistency> + <persistency>volatile-zeroed</persistency> <readable/> -</attribute> + <writeable/> + </attribute> -<attribute> - <id>OPEN_POWER_MEMCTRL_READ_TIMEOUT_SEC</id> + <attribute> + <id>N_PLUS_ONE_N_PER_CHIP</id> <description> - Memory controller read timeout in seconds + Static per chip numerator setting when not in oversubscription. </description> <simpleType> - <uint64_t></uint64_t> + <uint16_t> + <default>0,0</default> + </uint16_t> + <array>2</array> </simpleType> - <persistency>non-volatile</persistency> + <persistency>volatile-zeroed</persistency> <readable/> -</attribute> + <writeable/> + </attribute> -<attribute> - <id>OPEN_POWER_DIMM_READ_TIMEOUT_SEC</id> + <attribute> + <id>N_PLUS_ONE_N_PER_MBA</id> <description> - DIMM read timeout in seconds + Static per MBA numerator setting when not in + oversubscription. Calculated based on MRW memory + power with redundant power. Lowest per MBA numerator + ever allowed when OCC is throttling due to OT. </description> <simpleType> - <uint64_t></uint64_t> + <uint16_t> + <default>0,0</default> + </uint16_t> + <array>2</array> </simpleType> - <persistency>non-volatile</persistency> + <persistency>volatile-zeroed</persistency> <readable/> -</attribute> + <writeable/> + </attribute> -<attribute> - <id>OPEN_POWER_PROC_ERROR_TEMP_DEG_C</id> - <description> - Processor temperature error threshold in degrees C + <attribute> + <id>OCC_CONTROL_DATA</id> + <description>OCC operational data </description> <simpleType> - <uint64_t></uint64_t> + <uint8_t/> + <array>256</array> </simpleType> - <persistency>non-volatile</persistency> + <persistency>volatile-zeroed</persistency> <readable/> -</attribute> + <writeable/> + </attribute> -<attribute> - <id>OPEN_POWER_MIN_MEM_UTILIZATION_THROTTLING</id> + <attribute> + <id>OPAL_MODEL</id> <description> - Minimum memory utilization percent (from 0-100) - for memory throttling + Specifies the compatible model name for Opal to key off of. + This is sourced from the MRW and should be of the format + 'vendor,model', e.g. 'tyan,palmetto'. </description> <simpleType> - <uint8_t></uint8_t> + <string> + <default>ibm,miscopenpower</default> + <sizeInclNull>32</sizeInclNull> + </string> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>OPEN_POWER_MIN_MEM_UTILIZATION_POWER_CAP</id> + <attribute> + <id>OPEN_POWER_DIMM_ERROR_TEMP_DEG_C</id> <description> - Minimum memory utilization percent (from 0-100) - for power capping + DIMM temperature where an error will be generated + in degrees C </description> <simpleType> - <uint8_t></uint8_t> + <uint64_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>OPEN_POWER_VRM_READ_TIMEOUT_SEC</id> + <attribute> + <id>OPEN_POWER_DIMM_READ_TIMEOUT_SEC</id> <description> - VRM read timeout in seconds (from 0-255) - Use 0 to disable VRM OT monitoring + DIMM read timeout in seconds </description> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint64_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>OPEN_POWER_PROC_READ_TIMEOUT_SEC</id> + <attribute> + <id>OPEN_POWER_DIMM_THROTTLE_TEMP_DEG_C</id> <description> - Processor read timeout in seconds + DIMM temperature threshold where throttling will + occur in degrees C </description> <simpleType> - <uint64_t></uint64_t> + <uint64_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>OPEN_POWER_REGULATOR_EFFICIENCY_FACTOR</id> + <attribute> + <id>OPEN_POWER_GPU_ERROR_TEMP_DEG_C</id> <description> - Regulator efficiency factor + GPU core temperature error threshold in degrees C </description> <simpleType> - <uint64_t></uint64_t> + <uint8_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>OPEN_POWER_MIN_POWER_CAP_WATTS</id> + <attribute> + <id>OPEN_POWER_GPU_MEM_ERROR_TEMP_DEG_C</id> <description> - Minimum hard power cap in Watts + GPU memory temperature error threshold in degrees C </description> <simpleType> - <uint64_t></uint64_t> + <uint8_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>OPEN_POWER_SOFT_MIN_PCAP_WATTS</id> + <attribute> + <id>OPEN_POWER_GPU_MEM_READ_TIMEOUT_SEC</id> <description> - Minimum soft power cap in Watts + GPU memory temperature read timeout in seconds </description> <simpleType> - <uint64_t></uint64_t> + <uint8_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>OPEN_POWER_N_PLUS_ONE_BULK_POWER_LIMIT_WATTS</id> + <attribute> + <id>OPEN_POWER_GPU_READ_TIMEOUT_SEC</id> <description> - N+1 bulk power limit in Watts for systems running - with redundant power supplies (default) + GPU core temperature read timeout in seconds </description> <simpleType> - <uint64_t></uint64_t> + <uint8_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>OPEN_POWER_N_PLUS_ONE_HPC_BULK_POWER_LIMIT_WATTS</id> + <attribute> + <id>OPEN_POWER_MEMCTRL_ERROR_TEMP_DEG_C</id> <description> - N+1 bulk power limit in Watts for High Performance Computing - systems running with a non-redundant power supply policy + Memory controller temperature where an error will occur + in degrees C </description> <simpleType> - <uint64_t> - <default>0</default> - </uint64_t> + <uint64_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>OPEN_POWER_N_PLUS_ONE_MAX_MEM_POWER_WATTS</id> + <attribute> + <id>OPEN_POWER_MEMCTRL_READ_TIMEOUT_SEC</id> <description> - N+1 max memory power in Watts + Memory controller read timeout in seconds </description> <simpleType> - <uint64_t></uint64_t> + <uint64_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>OPEN_POWER_TURBO_MODE_SUPPORTED</id> + <attribute> + <id>OPEN_POWER_MEMCTRL_THROTTLE_TEMP_DEG_C</id> <description> - If this system supports Turbo frequency mode. - 0x00 = no - 0x01 = yes + Memory controller temperature threshold + where throttling will occur in degrees C </description> <simpleType> - <uint8_t></uint8_t> + <uint64_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>OPEN_POWER_GPU_READ_TIMEOUT_SEC</id> + <attribute> + <id>OPEN_POWER_MIN_MEM_UTILIZATION_POWER_CAP</id> <description> - GPU core temperature read timeout in seconds + Minimum memory utilization percent (from 0-100) + for power capping </description> <simpleType> - <uint8_t></uint8_t> + <uint8_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>OPEN_POWER_GPU_ERROR_TEMP_DEG_C</id> + <attribute> + <id>OPEN_POWER_MIN_MEM_UTILIZATION_THROTTLING</id> <description> - GPU core temperature error threshold in degrees C + Minimum memory utilization percent (from 0-100) + for memory throttling </description> <simpleType> - <uint8_t></uint8_t> + <uint8_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>OPEN_POWER_GPU_MEM_READ_TIMEOUT_SEC</id> + <attribute> + <id>OPEN_POWER_MIN_POWER_CAP_WATTS</id> <description> - GPU memory temperature read timeout in seconds + Minimum hard power cap in Watts </description> <simpleType> - <uint8_t></uint8_t> + <uint64_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>OPEN_POWER_GPU_MEM_ERROR_TEMP_DEG_C</id> + <attribute> + <id>OPEN_POWER_N_BULK_POWER_LIMIT_WATTS</id> <description> - GPU memory temperature error threshold in degrees C + N mode bulk power supply limit in Watts </description> <simpleType> - <uint8_t></uint8_t> + <uint64_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>OPAL_MODEL</id> + <attribute> + <id>OPEN_POWER_N_MAX_MEM_POWER_WATTS</id> <description> - Specifies the compatible model name for Opal to key off of. - This is sourced from the MRW and should be of the format - 'vendor,model', e.g. 'tyan,palmetto'. + Maximum power allocated to DIMMs in Watts </description> <simpleType> - <string> - <default>ibm,miscopenpower</default> - <sizeInclNull>32</sizeInclNull> - </string> + <uint64_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>IS_MPIPL_SUPPORTED</id> + <attribute> + <id>OPEN_POWER_N_PLUS_ONE_BULK_POWER_LIMIT_WATTS</id> <description> - Specifies if the mpipl is supported on this platform - 0 : No , 1 : Yes + N+1 bulk power limit in Watts for systems running + with redundant power supplies (default) </description> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint64_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<enumerationType> - <id>ENTITY_ID</id> - <description>Enumeration indicating the IPMI entity ID, these values are - defined in the IPMI specification. These values will be used in place - of target type when events are sent to the BMC.</description> - <enumerator> - <name>NA</name> - <value>0</value> - </enumerator> - <enumerator> - <name>OTHER</name> - <value>0x01</value> - </enumerator> - <enumerator> - <name>PROCESSOR</name> - <value>0x03</value> - </enumerator> - <enumerator> - <name>SYSTEM_BOARD</name> - <value>0x07</value> - </enumerator> - <enumerator> - <name>POWER_MGMT</name> - <value>0x15</value> - </enumerator> - <enumerator> - <name>CHASSIS</name> - <value>0x17</value> - </enumerator> - <enumerator> - <name>MEMORY_DEVICE</name> - <value>0x20</value> - </enumerator> - <enumerator> - <name>SYS_MGMT_SOFTWARE</name> - <value>0x21</value> - </enumerator> - <enumerator> - <name>BIOS</name> - <value>0x22</value> - </enumerator> - <enumerator> - <name>OS</name> - <value>0x23</value> - </enumerator> - <enumerator> - <name>CORE</name> - <value>0xD0</value> - </enumerator> - <enumerator> - <name>MEMBUF</name> - <value>0xD1</value> - </enumerator> - <enumerator> - <name>OCC</name> - <value>0xD2</value> - </enumerator> - <enumerator> - <name>REF_CLOCK</name> - <value>0xD4</value> - </enumerator> - <enumerator> - <name>PCI_CLOCK</name> - <value>0xD5</value> - </enumerator> - <enumerator> - <name>TOD_CLOCK</name> - <value>0xD6</value> - </enumerator> - <enumerator> - <name>APSS</name> - <value>0xD7</value> - </enumerator> - <enumerator> - <name>GPU_CORE</name> - <value>0xD8</value> - </enumerator> - <enumerator> - <name>GPU_MEMORY</name> - <value>0xD9</value> - </enumerator> -</enumerationType> - - -<enumerationType> - <id>SENSOR_TYPE</id> - <description>Enumeration indicating the IPMI sensor type, these values - are defined in the IPMI specification. These values will be used when - sending sensor reading events to the BMC.</description> - <enumerator> - <name>NA</name> - <value>0</value> - </enumerator> - <enumerator> - <name>TEMPERATURE</name> - <value>0x01</value> - </enumerator> - <enumerator> - <name>PROCESSOR</name> - <value>0x07</value> - </enumerator> - <enumerator> - <name>POWER_UNIT</name> - <value>0x09</value> - </enumerator> - <enumerator> - <name>MEMORY</name> - <value>0x0c</value> - </enumerator> - <enumerator> - <name>SYS_FW_PROGRESS</name> - <value>0x0F</value> - </enumerator> - <enumerator> - <name>SYS_EVENT</name> - <value>0x12</value> - </enumerator> - <enumerator> - <name>ADDIN_CARD</name> - <value>0x17</value> - </enumerator> - <enumerator> - <name>OS_BOOT</name> - <value>0x1F</value> - </enumerator> - <enumerator> - <name>APCI_POWER_STATE</name> - <value>0x22</value> - </enumerator> - <enumerator> - <name>FREQ</name> - <value>0xC1</value> - </enumerator> - <enumerator> - <name>POWER</name> - <value>0xC2</value> - </enumerator> - <enumerator> - <name>BOOT_COUNT</name> - <value>0xC3</value> - </enumerator> - <enumerator> - <name>PCI_LINK_PRES</name> - <value>0xC4</value> - </enumerator> - <enumerator> - <name>PWR_LIMIT_ACTIVE</name> - <value>0xC4</value> - </enumerator> - <enumerator> - <name>FAULT</name> - <value>0xC7</value> - </enumerator> -</enumerationType> - -<!-- IPMI Sensor numbers are defined in the IPMI spec as 8 bit values. However -in the hostboot code they will be defined as a uint16_t to allow us to add -additonal information. An example relates to error logs returned by the OCC, -we might want to pass the Entity ID in the upper byte of the sensor ID, this -would allow hostboot to search only the target type identifed by the Entity -ID for the sensor number returned with the elog. --> - -<!-- attribute to hold 16 pairs of sensor type, sensor number values --> - -<attribute> - <id>IPMI_MAX_BUFFER_SIZE</id> - <description>max buffer size to use for ipmi messages</description> + <attribute> + <id>OPEN_POWER_N_PLUS_ONE_HPC_BULK_POWER_LIMIT_WATTS</id> + <description> + N+1 bulk power limit in Watts for High Performance Computing + systems running with a non-redundant power supply policy + </description> <simpleType> - <uint32_t> - </uint32_t> + <uint64_t> + <default>0</default> + </uint64_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> - <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>BMC_MAX_ERROR_LOG_SIZE</id> - <description>max size of error log that can be sent to BMC</description> + <attribute> + <id>OPEN_POWER_N_PLUS_ONE_MAX_MEM_POWER_WATTS</id> + <description> + N+1 max memory power in Watts + </description> <simpleType> - <uint32_t> - <default>2048</default> - </uint32_t> + <uint64_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>BMC_MANUFACTURER</id> - <description>The manufacturer of the BMC</description> + <attribute> + <id>OPEN_POWER_PROC_DVFS_TEMP_DEG_C</id> + <description> + Processor temperature where DVFS will occur in degrees C + </description> <simpleType> - <string> - <default>ibm</default> - <sizeInclNull>32</sizeInclNull> - </string> + <uint64_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>BMC_HW_CHIP_TYPE</id> - <description>The type of hardware of the BMC</description> + <attribute> + <id>OPEN_POWER_PROC_ERROR_TEMP_DEG_C</id> + <description> + Processor temperature error threshold in degrees C + </description> <simpleType> - <string> - <default>ast2500</default> - <sizeInclNull>32</sizeInclNull> - </string> + <uint64_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>BMC_SW_TYPE</id> - <description>The software type of the BMC</description> + <attribute> + <id>OPEN_POWER_PROC_READ_TIMEOUT_SEC</id> + <description> + Processor read timeout in seconds + </description> <simpleType> - <string> - <default>openbmc</default> - <sizeInclNull>32</sizeInclNull> - </string> + <uint64_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> - -<!-- Start of HTMGT attributes --> + </attribute> -<attribute> - <id>HTMGT_SAFEMODE</id> - <description>1 = in safemode. 0 = in normal mode.</description> + <attribute> + <id>OPEN_POWER_PROC_WEIGHT</id> + <description> + Weight factor (in 1/10ths) for each core DTS to calculate a core + temperature. + </description> <simpleType> - <uint8_t> - </uint8_t> + <uint64_t/> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> - <hbOnly/> -</attribute> + </attribute> -<attribute> - <id>PSTATE_TABLE</id> - <description>HTMGT PSTATE data</description> + <attribute> + <id>OPEN_POWER_QUAD_WEIGHT</id> + <description> + Weight factor (in 1/10ths) for each quad (cache) DTS to calculate a core + temperature. + </description> <simpleType> - <uint8_t></uint8_t> - <array>3656</array> + <uint64_t/> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>PSTATE_TABLE_MFG</id> - <description>HTMGT PSTATE data for mfg</description> + <attribute> + <id>OPEN_POWER_REGULATOR_EFFICIENCY_FACTOR</id> + <description> + Regulator efficiency factor + </description> <simpleType> - <uint8_t></uint8_t> - <array>3656</array> + <uint64_t/> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>OCC_CONTROL_DATA</id> - <description>OCC operational data + <attribute> + <id>OPEN_POWER_SOFT_MIN_PCAP_WATTS</id> + <description> + Minimum soft power cap in Watts </description> <simpleType> - <uint8_t></uint8_t> - <array>256</array> + <uint64_t/> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>HTMGT_INTERNAL_FLAGS</id> - <description>HTMGT internal flags + <attribute> + <id>OPEN_POWER_TURBO_MODE_SUPPORTED</id> + <description> + If this system supports Turbo frequency mode. + 0x00 = no + 0x01 = yes </description> <simpleType> - <uint32_t> - <default>0x00000000</default> - </uint32_t> + <uint8_t/> </simpleType> - <persistency>volatile</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>OT_MIN_N_PER_MBA</id> + <attribute> + <id>OPEN_POWER_VRM_READ_TIMEOUT_SEC</id> <description> - Lowest per MBA numerator ever allowed when OCC is - throttling due to OT. + VRM read timeout in seconds (from 0-255) + Use 0 to disable VRM OT monitoring </description> <simpleType> - <uint16_t> - <default>0,0</default> - </uint16_t> - <array>2</array> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>OT_MEM_POWER</id> + <attribute> + <id>OPEN_POWER_VRM_VDD_DVFS_TEMP_DEG_C</id> <description> - Maximum memory power in centiWatts with throttle - set to minimum. + VRM Vdd Temperature in degrees C to invoke DVFS (clip max Pstate) </description> <simpleType> - <uint32_t> - <default>0,0</default> - </uint32_t> - <array>2</array> + <uint8_t> + <default>0xFF</default> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>N_PLUS_ONE_N_PER_MBA</id> + <attribute> + <id>OPEN_POWER_VRM_VDD_ERROR_TEMP_DEG_C</id> <description> - Static per MBA numerator setting when not in - oversubscription. Calculated based on MRW memory - power with redundant power. Lowest per MBA numerator - ever allowed when OCC is throttling due to OT. + VRM Vdd Temperature in degrees C that an overtemp error will be logged </description> <simpleType> - <uint16_t> - <default>0,0</default> - </uint16_t> - <array>2</array> + <uint8_t> + <default>0xFF</default> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>N_PLUS_ONE_N_PER_CHIP</id> + <attribute> + <id>OPEN_POWER_VRM_VDD_READ_TIMEOUT_SEC</id> <description> - Static per chip numerator setting when not in oversubscription. + Maximum time in seconds allowed without having a new VRM Vdd + temperature before DVFS will occur </description> <simpleType> - <uint16_t> - <default>0,0</default> - </uint16_t> - <array>2</array> + <uint8_t> + <default>0xFF</default> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>N_PLUS_ONE_MEM_POWER</id> + <attribute> + <id>OP_TRACE_LITE</id> <description> - Maximum memory power in centiWatts with throttle - set to nominal/turbo + Enable Trace lite on openpower. </description> <simpleType> - <uint32_t> - <default>0,0</default> - </uint32_t> - <array>2</array> + <uint8_t> + <default/> + </uint8_t> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> + <hbOnly/> + </attribute> -<attribute> - <id>POWERCAP_N_PER_MBA</id> + <attribute> + <id>OT_MEM_POWER</id> <description> - Static per slot numerator setting when power is being capped. + Maximum memory power in centiWatts with throttle + set to minimum. </description> <simpleType> - <uint16_t> - <default>0,0</default> - </uint16_t> - <array>2</array> + <uint32_t> + <default>0,0</default> + </uint32_t> + <array>2</array> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> + </attribute> -<attribute> - <id>POWERCAP_N_PER_CHIP</id> + <attribute> + <id>OT_MIN_N_PER_MBA</id> <description> - Static per chip numerator setting when power is being capped. + Lowest per MBA numerator ever allowed when OCC is + throttling due to OT. </description> <simpleType> - <uint16_t> - <default>0,0</default> - </uint16_t> - <array>2</array> + <uint16_t> + <default>0,0</default> + </uint16_t> + <array>2</array> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> + </attribute> -<attribute> + <attribute> <id>POWERCAP_MEM_POWER</id> <description> Maximum memory power in centiWatts with when power is being capped. </description> <simpleType> - <uint32_t> - <default>0,0</default> - </uint32_t> - <array>2</array> + <uint32_t> + <default>0,0</default> + </uint32_t> + <array>2</array> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> + </attribute> -<attribute> - <id>CALCULATED_MAX_SYS_POWER_EXCLUDING_GPUS</id> + <attribute> + <id>POWERCAP_N_PER_CHIP</id> <description> - HTMGT calculates the total non-GPU maximum power in W when the - CPUs are at max frequency and memory at max power (least throttled) - and then adds MISC_SYSTEM_COMPONENTS_MAX_POWER_WATTS + Static per chip numerator setting when power is being capped. </description> <simpleType> - <uint16_t> - <default>0x0000</default> - </uint16_t> + <uint16_t> + <default>0,0</default> + </uint16_t> + <array>2</array> </simpleType> - <persistency>volatile</persistency> + <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> + </attribute> -<attribute> - <id>CALCULATED_PROC_MEMORY_POWER_DROP</id> + <attribute> + <id>POWERCAP_N_PER_MBA</id> <description> - HTMGT calculates the total processor/memory power drop in W when the - CPUs are at min frequency and memory at min power (most throttled). - This is the how much CALCULATED_MAX_SYS_POWER_EXCLUDING_GPUS - can be reduced by. + Static per slot numerator setting when power is being capped. </description> <simpleType> - <uint16_t> - <default>0x0000</default> - </uint16_t> + <uint16_t> + <default>0,0</default> + </uint16_t> + <array>2</array> </simpleType> - <persistency>volatile</persistency> + <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> + </attribute> -<attribute> - <id>NO_APSS_PROC_POWER_VCS_VIO_WATTS</id> - <description> - A constant power (in watts) that the OCC is to add onto Vdd and Vdn - power to represent any processor part that is not measured(i.e.Vcs,Vio) - This is used by the OCC to calculate a total processor socket power. - </description> - <simpleType> - <uint16_t> - <default>0</default> - </uint16_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> -<attribute> - <id>OPEN_POWER_VRM_VDD_DVFS_TEMP_DEG_C</id> - <description> - VRM Vdd Temperature in degrees C to invoke DVFS (clip max Pstate) - </description> - <simpleType> - <uint8_t> - <default>0xFF</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> -<attribute> - <id>OPEN_POWER_VRM_VDD_ERROR_TEMP_DEG_C</id> - <description> - VRM Vdd Temperature in degrees C that an overtemp error will be logged - </description> - <simpleType> - <uint8_t> - <default>0xFF</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> -<attribute> - <id>OPEN_POWER_VRM_VDD_READ_TIMEOUT_SEC</id> + <attribute> + <id>PROC_MHZ_PER_WATT</id> <description> - Maximum time in seconds allowed without having a new VRM Vdd - temperature before DVFS will occur + Frequency (in MHz) for 1 Watt of processor power change. Used by the + power capping algorithm to determine how much to change the frequency + based on power available. + This is used in populating CALCULATED_MAX_SYS_POWER_EXCLUDING_GPUS </description> <simpleType> - <uint8_t> - <default>0xFF</default> - </uint8_t> + <uint16_t> + <default>28</default> + </uint16_t> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> + <attribute> <id>PROC_SOCKET_POWER_WATTS</id> <description> The maximum power a single procesor socket can support (in watts) This is used to populate CALCULATED_MAX_SYS_POWER_EXCLUDING_GPUS </description> <simpleType> - <uint16_t> - <default>250</default> - </uint16_t> + <uint16_t> + <default>250</default> + </uint16_t> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>PROC_MHZ_PER_WATT</id> - <description> - Frequency (in MHz) for 1 Watt of processor power change. Used by the - power capping algorithm to determine how much to change the frequency - based on power available. - This is used in populating CALCULATED_MAX_SYS_POWER_EXCLUDING_GPUS - </description> + <attribute> + <id>PSTATE_TABLE</id> + <description>HTMGT PSTATE data</description> <simpleType> - <uint16_t> - <default>28</default> - </uint16_t> + <uint8_t/> + <array>3656</array> </simpleType> - <persistency>non-volatile</persistency> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + </attribute> + + <attribute> + <id>PSTATE_TABLE_MFG</id> + <description>HTMGT PSTATE data for mfg</description> + <simpleType> + <uint8_t/> + <array>3656</array> + </simpleType> + <persistency>volatile-zeroed</persistency> <readable/> -</attribute> + <writeable/> + </attribute> -<attribute> + <attribute> <id>REPORT_THROTTLE_BELOW_NOMINAL</id> <description> Indicates if OCC should wait to report DVFS due to power/thermal until @@ -1332,27 +1323,86 @@ ID for the sensor number returned with the elog. --> 0 = OCC report throttling when max freq. lowered below turbo </description> <simpleType> - <uint8_t><default>0</default></uint8_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + </attribute> -<attribute> - <id>HTMGT_SAVED_POWER_LIMIT</id> - <description>User power limit information from the BMC to be used if - communication with the BMC is lost after system is powered on. - Used internally by HTMGT. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> + <enumerationType> + <id>SENSOR_TYPE</id> + <description>Enumeration indicating the IPMI sensor type, these values + are defined in the IPMI specification. These values will be used when + sending sensor reading events to the BMC.</description> + <enumerator> + <name>NA</name> + <value>0</value> + </enumerator> + <enumerator> + <name>TEMPERATURE</name> + <value>0x01</value> + </enumerator> + <enumerator> + <name>PROCESSOR</name> + <value>0x07</value> + </enumerator> + <enumerator> + <name>POWER_UNIT</name> + <value>0x09</value> + </enumerator> + <enumerator> + <name>MEMORY</name> + <value>0x0c</value> + </enumerator> + <enumerator> + <name>SYS_FW_PROGRESS</name> + <value>0x0F</value> + </enumerator> + <enumerator> + <name>SYS_EVENT</name> + <value>0x12</value> + </enumerator> + <enumerator> + <name>ADDIN_CARD</name> + <value>0x17</value> + </enumerator> + <enumerator> + <name>OS_BOOT</name> + <value>0x1F</value> + </enumerator> + <enumerator> + <name>APCI_POWER_STATE</name> + <value>0x22</value> + </enumerator> + <enumerator> + <name>FREQ</name> + <value>0xC1</value> + </enumerator> + <enumerator> + <name>POWER</name> + <value>0xC2</value> + </enumerator> + <enumerator> + <name>BOOT_COUNT</name> + <value>0xC3</value> + </enumerator> + <enumerator> + <name>PCI_LINK_PRES</name> + <value>0xC4</value> + </enumerator> + <enumerator> + <name>PWR_LIMIT_ACTIVE</name> + <value>0xC4</value> + </enumerator> + <enumerator> + <name>FAULT</name> + <value>0xC7</value> + </enumerator> + </enumerationType> -<attribute> + <attribute> <id>VDD_CURRENT_OVERFLOW_WORKAROUND_ENABLE</id> <description> Used to enable Vdd current overflow worakaround. @@ -1361,69 +1411,12 @@ ID for the sensor number returned with the elog. --> Set to 0 to disable. </description> <simpleType> - <uint16_t> - <default>0x0000</default> - </uint16_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>MAX_VDD_CURRENT_READING</id> - <description> - Maximum theoretical Vdd current reading in 10mA units. - Used when VDD_CURRENT_OVERFLOW_WORKAROUND_ENABLE is set. - </description> - <simpleType> - <uint16_t> - <default>0x0000</default> - </uint16_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<!-- end HTMGT attributes --> - -<attribute> - <id>MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP</id> - <description> - Machine Readable Workbook safe mode throttle value for - numerator cfg_nm_n_per_chip - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>MSS_UTIL_N_PER_MBA</id> - <description> - cfg_nm_n_per_mba throttle N value that was calculated from - MSS_DATABUS_UTIL_PER_MBA - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>ALLOW_CALLHOME_ESELS_TO_BMC</id> - <description>Flag used to allow sending informational call-home errors as ESELS to the BMC</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint16_t> + <default>0x0000</default> + </uint16_t> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> - + </attribute> </attributes> diff --git a/src/usr/targeting/common/xmltohb/attribute_types_oppowervm.xml b/src/usr/targeting/common/xmltohb/attribute_types_oppowervm.xml index fdc17c8d5..2c8e3d8da 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types_oppowervm.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types_oppowervm.xml @@ -22,8 +22,6 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<attributes> - <!-- ===================================================================== Contains the definition of attributes that are only available on openpower systems for a PowerVM build. This file is only compiled when @@ -31,603 +29,589 @@ FSP based systems. ===================================================================== --> - -<attribute> - <id>PROC_HW_TOPOLOGY</id> - <description>Hardware topology for HDAT - creator:MRW - consumer:HDAT - firmware notes: - Hardware Topology 2 Bytes - Byte 1: - bit 0-3: Node Id - bit 4-7: Socket id inside the node - bit 8-11: Proc id inside socket - bit 12-15:Hub Id inside proc +<attributes> + <attribute> + <id>ASCII_VPD_LX_KEYWORD</id> + <description>LX keyword VPD data for HDAT module </description> <simpleType> - <uint16_t> - </uint16_t> + <uint64_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + <writeable/> + </attribute> -<enumerationType> + <enumerationType> <id>CHIP_VER</id> <description>Enumeration indicating the chip version</description> <enumerator> - <name>DD10</name> - <value>0x10</value> + <name>DD10</name> + <value>0x10</value> </enumerator> <enumerator> - <name>DD11</name> - <value>0x11</value> + <name>DD11</name> + <value>0x11</value> </enumerator> <enumerator> - <name>DD20</name> - <value>0x20</value> + <name>DD20</name> + <value>0x20</value> </enumerator> <enumerator> - <name>DD21</name> - <value>0x21</value> + <name>DD21</name> + <value>0x21</value> </enumerator> <default>DD10</default> -</enumerationType> - -<enumerationType> - <id>HW_VER</id> - <description>Enumeration indicating the chip HW version</description> - <enumerator> - <name>FSP_HW_VER</name> - <value>0x2</value> - </enumerator> - <enumerator> - <name>BMC_HW_VER</name> - <value>0x3</value> - </enumerator> - <default>BMC_HW_VER</default> -</enumerationType> - -<enumerationType> - <id>SW_VER</id> - <description>Enumeration indicating the SW version</description> - <enumerator> - <name>FSP_SW_VER</name> - <value>0x1</value> - </enumerator> - <enumerator> - <name>BMC_SW_VER</name> - <value>0x2</value> - </enumerator> - <default>BMC_SW_VER</default> -</enumerationType> - -<enumerationType> - <id>ROLE</id> - <description>Enumeration indicating the master's FSI type</description> - <enumerator> - <name>PRIMARY</name> - <value>1</value> - </enumerator> - <enumerator> - <name>BACKUP</name> - <value>0</value> - </enumerator> - <default>PRIMARY</default> -</enumerationType> + </enumerationType> -<attribute> + <attribute> <id>CHIP_VER</id> <description>Attribute indicating the target's chip version</description> <simpleType> - <enumeration> - <id>CHIP_VER</id> - </enumeration> + <enumeration> + <id>CHIP_VER</id> + </enumeration> </simpleType> <persistency>non-volatile</persistency> <readable/> <hasStringConversion/> -</attribute> + </attribute> -<attribute> - <id>HW_VER</id> - <description>Attribute indicating the target's hw version</description> + <attribute> + <id>CREATE_DEF_PARTITION</id> + <description> + User configuration for creating default partition + </description> <simpleType> - <enumeration> - <id>HW_VER</id> - </enumeration> + <uint8_t/> </simpleType> - <persistency>non-volatile</persistency> + <persistency>volatile-zeroed</persistency> <readable/> - <hasStringConversion/> -</attribute> + <writeable/> + </attribute> -<attribute> - <id>SW_VER</id> - <description>Attribute indicating the target's software version</description> + <attribute> + <id>ENLARGED_IO_SLOT_COUNT</id> + <description> + User configuration for Enlarged IO SLot Count + </description> <simpleType> - <enumeration> - <id>SW_VER</id> - </enumeration> + <uint8_t/> </simpleType> - <persistency>non-volatile</persistency> + <persistency>volatile-zeroed</persistency> <readable/> - <hasStringConversion/> -</attribute> + <writeable/> + </attribute> -<attribute> - <id>ROLE</id> - <description>Attribute indicating the target's role</description> + <attribute> + <id>HUGE_PAGE_COUNT</id> + <description> + Huge Memory Page Count + </description> <simpleType> - <enumeration> - <id>ROLE</id> - </enumeration> + <uint16_t/> </simpleType> - <persistency>non-volatile</persistency> + <persistency>volatile-zeroed</persistency> <readable/> - <hasStringConversion/> -</attribute> + <writeable/> + </attribute> -<attribute> - <id>PHYP_SYSTEM_TYPE</id> - <description>PHYP system type value for habanero - and barreleye (0x3015 and 0x3016 respectively). - The value is updated in the system xml. + <attribute> + <id>HUGE_PAGE_SIZE</id> + <description> + Huge Memory Page Size </description> <simpleType> - <uint32_t> - </uint32_t> + <uint8_t/> </simpleType> - <persistency>non-volatile</persistency> + <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> + </attribute> -<attribute> - <id>ASCII_VPD_LX_KEYWORD</id> - <description>LX keyword VPD data for HDAT module - </description> + <enumerationType> + <id>HW_VER</id> + <description>Enumeration indicating the chip HW version</description> + <enumerator> + <name>FSP_HW_VER</name> + <value>0x2</value> + </enumerator> + <enumerator> + <name>BMC_HW_VER</name> + <value>0x3</value> + </enumerator> + <default>BMC_HW_VER</default> + </enumerationType> + + <attribute> + <id>HW_VER</id> + <description>Attribute indicating the target's hw version</description> <simpleType> - <uint64_t> - </uint64_t> + <enumeration> + <id>HW_VER</id> + </enumeration> </simpleType> <persistency>non-volatile</persistency> <readable/> + <hasStringConversion/> + </attribute> + + <attribute> + <id>HYPERVISOR_IPL_DESTINATION</id> + <description> + Hypervisor IPL Destination + </description> + <simpleType> + <uint8_t/> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> <writeable/> -</attribute> + </attribute> -<attribute> - <id>ENLARGED_IO_SLOT_COUNT</id> + <attribute> + <id>HYPERVISOR_IPL_SIDE</id> <description> - User configuration for Enlarged IO SLot Count + Platform IPL Side </description> <simpleType> - <uint8_t> - </uint8_t> + <uint8_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> + </attribute> -<attribute> - <id>CREATE_DEF_PARTITION</id> + <attribute> + <id>HYP_DISPATCH_WHEEL</id> <description> - User configuration for creating default partition + Hypervisor Dispatch Wheel </description> <simpleType> - <uint8_t> - </uint8_t> + <uint8_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> + </attribute> -<attribute> - <id>IPL_ATTRIBUTES</id> - <description> + <attribute> + <id>IPL_ATTRIBUTES</id> + <description> Assorted list of differnt IPL attributes passed via HDAT </description> - <complexType> - <description>struct - 8 booleans </description> - <field> - <name>createDefaultPartition</name> - <description> + <complexType> + <description>struct - 8 booleans </description> + <field> + <name>createDefaultPartition</name> + <description> 0b0: Dont create default partition; 0b1: Create default partition; </description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>clickToAcceptState</name> - <description> + <type>uint8_t</type> + <bits>1</bits> + <default>0</default> + </field> + <field> + <name>clickToAcceptState</name> + <description> 0b0: Customer has not accepted license agreement; 0b1: Customer has accepted license agreement; </description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>disableVirtIO</name> - <description> + <type>uint8_t</type> + <bits>1</bits> + <default>0</default> + </field> + <field> + <name>disableVirtIO</name> + <description> 0b0: Enable Virtual IO Connections between partitions; 0b1: Disable Virtual IO Connections between partitions; </description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>resetPCINumbers</name> - <description> + <type>uint8_t</type> + <bits>1</bits> + <default>0</default> + </field> + <field> + <name>resetPCINumbers</name> + <description> 0b0: Do not reset PCI Numbers; 0b1: Reset PCI Numbers; </description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>clearHypNVRAM</name> - <description> + <type>uint8_t</type> + <bits>1</bits> + <default>0</default> + </field> + <field> + <name>clearHypNVRAM</name> + <description> 0b0: Do not clear HYP NVRAM; 0b1: Clear HYP NVRAM; </description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>deleteHYPSELs</name> - <description> + <type>uint8_t</type> + <bits>1</bits> + <default>0</default> + </field> + <field> + <name>deleteHYPSELs</name> + <description> 0b0: Do not delete SELs originating from HYP; 0b1: Delete SELs originating from HYP; </description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>deleteHBSELs</name> - <description> + <type>uint8_t</type> + <bits>1</bits> + <default>0</default> + </field> + <field> + <name>deleteHBSELs</name> + <description> 0b0: Do not delete SELs originating from Hostboot; 0b1: Delete SELs originating from Hostboot; </description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>deleteBMCSELs</name> - <description> + <type>uint8_t</type> + <bits>1</bits> + <default>0</default> + </field> + <field> + <name>deleteBMCSELs</name> + <description> 0b0: Do not delete SELs originating from BMC; 0b1: Delete SELs originating from BMC; </description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - </complexType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>PRESERVE_MDC_PARTITION_VPD</id> - <description> - MFG setting to preserve MDC partition vpd - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> + <type>uint8_t</type> + <bits>1</bits> + <default>0</default> + </field> + </complexType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> + </attribute> -<attribute> - <id>HYPERVISOR_IPL_SIDE</id> + <attribute> + <id>IPS_ENABLE</id> <description> - Platform IPL Side + Indicates if Idle Power Save is enabled. This is independent of + the OPEN_POWER_PM_MODE (DPS and IPS can be enabled at the same time). + Valid Values: 0 = Disabled (default), 1 = Enabled. + See IPS_ENTER / IPS_EXIT attributes for IPS configuration. </description> <simpleType> - <uint8_t> - </uint8_t> + <uint8_t> + <!-- disabled --> + <default>0</default> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>OS_IPL_MODE</id> + <attribute> + <id>IPS_ENTER_TIME_SECONDS</id> <description> - Operating System IPL Mode + When IPS is enabled, this defines the delay time in seconds + (between 10 and 600) to enter Idle Power Save. </description> <simpleType> - <uint8_t> - </uint8_t> + <uint16_t> + <default>240</default> + </uint16_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>LMB_SIZE</id> + <attribute> + <id>IPS_ENTER_UTILIZATION_PERCENT</id> <description> - Logical Memory Block Size + When IPS is enabled, this defines the utilization threshold as a + percent (between 0 and 100) to enter Idle Power Save. This value + should be less than IPS_EXIT_UTILIZATION_PERCENT. </description> <simpleType> - <uint8_t> - </uint8_t> + <uint8_t> + <default>8</default> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>MAX_HSL_OPTICONNECT_CONNECTIONS</id> + <attribute> + <id>IPS_EXIT_TIME_SECONDS</id> <description> - User configuration for max HSL Opticonnect connections + When IPS is enabled, this defines the delay time in seconds + (between 10 and 600) to exit Idle Power Save. </description> <simpleType> - <uint8_t> - </uint8_t> + <uint16_t> + <default>10</default> + </uint16_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>HUGE_PAGE_COUNT</id> + <attribute> + <id>IPS_EXIT_UTILIZATION_PERCENT</id> <description> - Huge Memory Page Count + When IPS is enabled, this defines the utilization threshold as a + percent (between 0 and 100) to exit Idle Power Save. This value + should be greater than IPS_ENTER_UTILIZATION_PERCENT. </description> <simpleType> - <uint16_t> - </uint16_t> + <uint8_t> + <default>12</default> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>HUGE_PAGE_SIZE</id> + <attribute> + <id>LMB_SIZE</id> <description> - Huge Memory Page Size + Logical Memory Block Size </description> <simpleType> - <uint8_t> - </uint8_t> + <uint8_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> + </attribute> -<attribute> - <id>VLAN_SWITCHES</id> + <attribute> + <id>MAX_HSL_OPTICONNECT_CONNECTIONS</id> <description> - Number of VLAN Switches + User configuration for max HSL Opticonnect connections </description> <simpleType> - <uint8_t> - </uint8_t> + <uint8_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> + </attribute> -<attribute> - <id>VTPM_ENABLED</id> + <attribute> + <id>OPEN_POWER_PM_MODE</id> <description> - Virtual TPM Enabled + Power management mode the system should use. + Valid values: 1 = Nominal (default), + 5 = Static Power Save (percentage below nominal whose value + is defined in OPEN_POWER_PM_MODE_FREQ_PERCENT), + 6 = Dynamic Power Save - Favor Energy (DPS-FE), + 10 = Dynamic Power Save - Favor Performance (DPS-FP), + 11 = Fixed Frequency Override - (percentage above nominal whose + value is defined in OPEN_POWER_PM_MODE_FREQ_PERCENT) </description> <simpleType> - <uint8_t> - </uint8_t> + <uint8_t> + <!-- Nominal --> + <default>1</default> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>HYPERVISOR_IPL_DESTINATION</id> + <attribute> + <id>OPEN_POWER_PM_MODE_FREQ_PERCENT</id> <description> - Hypervisor IPL Destination + Percentage from nominal that the processors should run at when + OPEN_POWER_PM_MODE is set to Static Power Save or + Fixed Frequency Override (ignored on all other modes). + Unit is in tenths of a percent (150 = 15.0%). + Static Power Save (5): percentage to decrease frequency, + Fixed Frequency Override (11): percentage to increase frequency </description> <simpleType> - <uint8_t> - </uint8_t> + <uint16_t/> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>HYP_DISPATCH_WHEEL</id> + <attribute> + <id>OS_IPL_MODE</id> <description> - Hypervisor Dispatch Wheel + Operating System IPL Mode </description> <simpleType> - <uint8_t> - </uint8_t> + <uint8_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> + </attribute> -<attribute> - <id>SYSTEM_BRAND_NAME</id> - <description> - Brand Name of OEM systems + <attribute> + <id>PHYP_SYSTEM_TYPE</id> + <description>PHYP system type value for habanero + and barreleye (0x3015 and 0x3016 respectively). + The value is updated in the system xml. </description> <simpleType> - <string> - <sizeInclNull>64</sizeInclNull> - </string> + <uint32_t/> </simpleType> <persistency>non-volatile</persistency> <readable/> <writeable/> -</attribute> + </attribute> -<attribute> - <id>SLCA_INDEX</id> + <attribute> + <id>PRESERVE_MDC_PARTITION_VPD</id> <description> - SLCA index for this FRU + MFG setting to preserve MDC partition vpd </description> <simpleType> - <uint32_t> - </uint32_t> + <uint8_t/> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> -</attribute> + </attribute> -<attribute> - <id>SLCA_RID</id> - <description> - SLCA RID for this FRU + <attribute> + <id>PROC_HW_TOPOLOGY</id> + <description>Hardware topology for HDAT + creator:MRW + consumer:HDAT + firmware notes: + Hardware Topology 2 Bytes + Byte 1: + bit 0-3: Node Id + bit 4-7: Socket id inside the node + bit 8-11: Proc id inside socket + bit 12-15:Hub Id inside proc </description> <simpleType> - <uint32_t> - </uint32_t> + <uint16_t/> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>OPEN_POWER_PM_MODE</id> - <description> - Power management mode the system should use. - Valid values: 1 = Nominal (default), - 5 = Static Power Save (percentage below nominal whose value - is defined in OPEN_POWER_PM_MODE_FREQ_PERCENT), - 6 = Dynamic Power Save - Favor Energy (DPS-FE), - 10 = Dynamic Power Save - Favor Performance (DPS-FP), - 11 = Fixed Frequency Override - (percentage above nominal whose - value is defined in OPEN_POWER_PM_MODE_FREQ_PERCENT) - </description> + <enumerationType> + <id>ROLE</id> + <description>Enumeration indicating the master's FSI type</description> + <enumerator> + <name>PRIMARY</name> + <value>1</value> + </enumerator> + <enumerator> + <name>BACKUP</name> + <value>0</value> + </enumerator> + <default>PRIMARY</default> + </enumerationType> + + <attribute> + <id>ROLE</id> + <description>Attribute indicating the target's role</description> <simpleType> - <uint8_t> - <default>1</default> <!-- Nominal --> - </uint8_t> + <enumeration> + <id>ROLE</id> + </enumeration> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + <hasStringConversion/> + </attribute> -<attribute> - <id>OPEN_POWER_PM_MODE_FREQ_PERCENT</id> + <attribute> + <id>SLCA_INDEX</id> <description> - Percentage from nominal that the processors should run at when - OPEN_POWER_PM_MODE is set to Static Power Save or - Fixed Frequency Override (ignored on all other modes). - Unit is in tenths of a percent (150 = 15.0%). - Static Power Save (5): percentage to decrease frequency, - Fixed Frequency Override (11): percentage to increase frequency + SLCA index for this FRU </description> - <simpleType><uint16_t></uint16_t></simpleType> - <persistency>non-volatile</persistency> + <simpleType> + <uint32_t/> + </simpleType> + <persistency>volatile-zeroed</persistency> <readable/> -</attribute> + <writeable/> + </attribute> -<attribute> - <id>IPS_ENABLE</id> + <attribute> + <id>SLCA_RID</id> <description> - Indicates if Idle Power Save is enabled. This is independent of - the OPEN_POWER_PM_MODE (DPS and IPS can be enabled at the same time). - Valid Values: 0 = Disabled (default), 1 = Enabled. - See IPS_ENTER / IPS_EXIT attributes for IPS configuration. + SLCA RID for this FRU </description> <simpleType> - <uint8_t> - <default>0</default> <!-- disabled --> - </uint8_t> + <uint32_t/> </simpleType> - <persistency>non-volatile</persistency> + <persistency>volatile-zeroed</persistency> <readable/> -</attribute> + <writeable/> + </attribute> -<attribute> - <id>IPS_ENTER_TIME_SECONDS</id> - <description> - When IPS is enabled, this defines the delay time in seconds - (between 10 and 600) to enter Idle Power Save. - </description> + <enumerationType> + <id>SW_VER</id> + <description>Enumeration indicating the SW version</description> + <enumerator> + <name>FSP_SW_VER</name> + <value>0x1</value> + </enumerator> + <enumerator> + <name>BMC_SW_VER</name> + <value>0x2</value> + </enumerator> + <default>BMC_SW_VER</default> + </enumerationType> + + <attribute> + <id>SW_VER</id> + <description>Attribute indicating the target's software version</description> <simpleType> - <uint16_t> - <default>240</default> - </uint16_t> + <enumeration> + <id>SW_VER</id> + </enumeration> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + <hasStringConversion/> + </attribute> -<attribute> - <id>IPS_ENTER_UTILIZATION_PERCENT</id> + <attribute> + <id>SYSTEM_BRAND_NAME</id> <description> - When IPS is enabled, this defines the utilization threshold as a - percent (between 0 and 100) to enter Idle Power Save. This value - should be less than IPS_EXIT_UTILIZATION_PERCENT. + Brand Name of OEM systems </description> <simpleType> - <uint8_t> - <default>8</default> - </uint8_t> + <string> + <sizeInclNull>64</sizeInclNull> + </string> </simpleType> <persistency>non-volatile</persistency> <readable/> -</attribute> + <writeable/> + </attribute> -<attribute> - <id>IPS_EXIT_TIME_SECONDS</id> + <attribute> + <id>VLAN_SWITCHES</id> <description> - When IPS is enabled, this defines the delay time in seconds - (between 10 and 600) to exit Idle Power Save. + Number of VLAN Switches </description> <simpleType> - <uint16_t> - <default>10</default> - </uint16_t> + <uint8_t/> </simpleType> - <persistency>non-volatile</persistency> + <persistency>volatile-zeroed</persistency> <readable/> -</attribute> + <writeable/> + </attribute> -<attribute> - <id>IPS_EXIT_UTILIZATION_PERCENT</id> + <attribute> + <id>VTPM_ENABLED</id> <description> - When IPS is enabled, this defines the utilization threshold as a - percent (between 0 and 100) to exit Idle Power Save. This value - should be greater than IPS_ENTER_UTILIZATION_PERCENT. + Virtual TPM Enabled </description> <simpleType> - <uint8_t> - <default>12</default> - </uint8_t> + <uint8_t/> </simpleType> - <persistency>non-volatile</persistency> + <persistency>volatile-zeroed</persistency> <readable/> -</attribute> + <writeable/> + </attribute> </attributes> diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index 0b6468e96..c5245785d 100644 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -24,2555 +24,2780 @@ <!-- --> <!-- IBM_PROLOG_END_TAG --> <attributes> -<targetType> - <id>base</id> - <attribute> - <id>CLASS</id> - </attribute> - <attribute> - <id>TYPE</id> - </attribute> - <attribute> - <id>MODEL</id> - </attribute> - <attribute> - <id>HUID</id> - </attribute> - <attribute> - <id>PHYS_PATH</id> - </attribute> - <attribute> - <id>AFFINITY_PATH</id> - </attribute> - <attribute> - <id>PRIMARY_CAPABILITIES</id> - </attribute> - <attribute> - <id>HWAS_STATE</id> - </attribute> - <attribute> - <id>HWAS_STATE_CHANGED_FLAG</id> - </attribute> - <attribute> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <default>0</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>0</default> - <id>RESOURCE_IS_CRITICAL</id> - </attribute> - <attribute> - <id>ORDINAL_ID</id> - </attribute> - <attribute> - <id>FAPI_NAME</id> - </attribute> - <attribute> - <id>PNOR_FLASH_WORKAROUNDS</id> - </attribute> -</targetType> - -<targetType> - <id>chip</id> - <parent>base</parent> - <attribute> - <default>CHIP</default> - <id>CLASS</id> - </attribute> - <attribute> - <id>POSITION</id> - </attribute> - <attribute> - <id>FSI_MASTER_CHIP</id> - </attribute> - <attribute> - <id>ALTFSI_MASTER_CHIP</id> - </attribute> - <attribute> - <default>NO_MASTER</default> - <id>FSI_MASTER_TYPE</id> - </attribute> - <attribute> - <id>MRU_ID</id> - </attribute> - <attribute> - <id>FSI_MASTER_PORT</id> - </attribute> - <attribute> - <id>ALTFSI_MASTER_PORT</id> - </attribute> - <attribute> - <id>FSI_SLAVE_CASCADE</id> - </attribute> - <attribute> - <id>FSI_OPTION_FLAGS</id> - </attribute> - <attribute> - <id>EC</id> - </attribute> - <attribute> - <id>CHIP_ID</id> - </attribute> - <attribute> - <id>FRU_ID</id> - </attribute> - <attribute> - <id>HDAT_EC</id> - </attribute> - <attribute><id>PRD_HWP_PLID</id></attribute> -</targetType> - -<targetType> - <id>chip-processor</id> - <parent>chip</parent> - <attribute> - <default>PROC</default> - <id>TYPE</id> - </attribute> - <attribute> - <id>PROC_MASTER_TYPE</id> - </attribute> - <attribute> - <default> - <field> - <id>supportsFsiScom</id> - <value>1</value> - </field> - <field> - <id>supportsXscom</id> - <value>1</value> - </field> - <field> - <id>supportsInbandScom</id> - <value>0</value> - </field> - <field> - <id>reserved</id> - <value>0</value> - </field> - </default> - <id>PRIMARY_CAPABILITIES</id> - </attribute> - <attribute><id>FABRIC_GROUP_ID</id></attribute> - <attribute><id>FABRIC_CHIP_ID</id></attribute> - <attribute> - <id>SCOM_SWITCHES</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>0x00000031</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <id>VPD_REC_NUM</id> - </attribute> - <attribute><id>HOT_PLUG_POWER_CONTROLLER_INFO</id></attribute> - <attribute><id>PM_UNDERVOLTING_FRQ_MINIMUM</id></attribute> - <attribute><id>PM_UNDERVOLTING_FREQ_MAXIMUM</id></attribute> - <attribute><id>PM_SPIVID_PORT_ENABLE</id></attribute> - <attribute><id>PM_PBAX_NODEID</id></attribute> - <attribute><id>PM_SLEEP_ENTRY</id></attribute> - <attribute><id>PM_SLEEP_EXIT</id></attribute> - <attribute><id>PM_SLEEP_TYPE</id></attribute> - <attribute><id>PM_WINKLE_ENTRY</id></attribute> - <attribute><id>PM_WINKLE_EXIT</id></attribute> - <attribute><id>PM_WINKLE_TYPE</id></attribute> - <attribute> - <id>TOD_ROLE</id> - </attribute> - <attribute> - <default> - <field> - <id>useFsiI2C</id> - <value>1</value> - </field> - <field> - <id>useHostI2C</id> - <value>0</value> - </field> - <field> - <id>reserved</id> - <value>0</value> - </field> - </default> - <id>I2C_SWITCHES</id> - </attribute> - <attribute> - <default>FABRIC</default> - <id>CDM_DOMAIN</id> - </attribute> - <attribute> - <id>TOD_CPU_DATA</id> - </attribute> - <attribute> - <id>ICACHE_ASSOC_SETS</id> - </attribute> - <attribute> - <id>ICACHE_SIZE</id> - </attribute> - <attribute> - <id>ICACHE_LINE_SIZE</id> - </attribute> - <attribute> - <id>ICACHE_BLOCK_SIZE</id> - </attribute> - <attribute> - <id>DCACHE_LINE_SIZE</id> - </attribute> - <attribute> - <id>DCACHE_ASSOC_SETS</id> - </attribute> - <attribute> - <id>DATA_CACHE_SIZE</id> - </attribute> - <attribute> - <id>DATA_CACHE_LINE_SIZE</id> - </attribute> - <attribute> - <id>L2_CACHE_LINE_SIZE</id> - </attribute> - <attribute> - <id>L2_CACHE_SIZE</id> - </attribute> - <attribute> - <id>L2_CACHE_ASSOC_SETS</id> - </attribute> - <attribute> - <id>L3_CACHE_LINE_SIZE</id> - </attribute> - <attribute> - <id>L3_CACHE_SIZE</id> - </attribute> - <attribute> - <id>TLB_DATA_ENTRIES</id> - </attribute> - <attribute> - <id>TLB_INSTR_ENTRIES</id> - </attribute> - <attribute> - <id>TLB_DATA_ASSOC_SETS</id> - </attribute> - <attribute> - <id>TLB_INSTR_ASSOC_SETS</id> - </attribute> - <attribute> - <id>TLB_RESERVE_SIZE</id> - </attribute> - <attribute> - <id>TIME_BASE</id> - </attribute> - <attribute> - <id>CPU_ATTR</id> - </attribute> - <attribute> - <id>XIVE_HW_RESET</id> - </attribute> - <attribute> - <id>DISABLE_I2C_ENGINE2_PORT0_DIAG_MODE</id> - </attribute> - <attribute> - <id>LOCATION_CODE</id> - </attribute> - <attribute> - <id>SBE_COMMIT_ID</id> - </attribute> - <attribute> - <id>SBE_VERSION_INFO</id> - </attribute> - <attribute> - <id>SBE_RELEASE_TAG</id> - </attribute> -</targetType> - -<targetType> - <id>unit</id> - <parent>base</parent> - <attribute> - <default>UNIT</default> - <id>CLASS</id> - </attribute> - <attribute> - <id>MRU_ID</id> - </attribute> - <attribute><id>CHIP_UNIT</id></attribute> - <attribute> - <default> - <field> - <id>supportsFsiScom</id> - <value>1</value> - </field> - <field> - <id>supportsXscom</id> - <value>1</value> - </field> - <field> - <id>supportsInbandScom</id> - <value>0</value> - </field> - <field> - <id>reserved</id> - <value>0</value> - </field> - </default> - <id>PRIMARY_CAPABILITIES</id> - </attribute> - <attribute> - <id>CHIPLET_ID</id> - </attribute> - <attribute> - <id>REL_POS</id> - </attribute> - <attribute><id>PRD_HWP_PLID</id></attribute> -</targetType> - -<!-- Generic OCMB --> -<targetType> - <id>chip-ocmb</id> - <parent>chip</parent> - <attribute> - <default>OCMB_CHIP</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>0x00000033</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <id>FRU_ID</id> - </attribute> -</targetType> - -<!-- Explorer OCMB --> -<targetType> - <id>chip-ocmb-explorer</id> - <parent>chip-ocmb</parent> - <attribute> - <default>EXPLORER</default> - <id>MODEL</id> - </attribute> -</targetType> - -<!-- mem_port --> -<targetType> - <id>unit-mem_port</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>MEM_PORT</default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000033</default> - </attribute> - <attribute> - <id>CDM_DOMAIN</id> - <default>MEM</default> - </attribute> -</targetType> - -<targetType> - <id>chip-membuf-centaur</id> - <parent>chip</parent> - <attribute> - <default>MEMBUF</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>CENTAUR</default> - <id>MODEL</id> - </attribute> - <attribute> - <default> - <field> - <id>supportsFsiScom</id> - <value>1</value> - </field> - <field> - <id>supportsXscom</id> - <value>0</value> - </field> - <field> - <id>supportsInbandScom</id> - <value>1</value> - </field> - <field> - <id>reserved</id> - <value>0</value> - </field> - </default> - <id>PRIMARY_CAPABILITIES</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>0x00000033</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <default> - <field> - <id>useSbeScom</id> - <value>1</value> - </field> - <field> - <id>useFsiScom</id> - <value>0</value> - </field> - <field> - <id>useXscom</id> - <value>0</value> - </field> - <field> - <id>useInbandScom</id> - <value>0</value> - </field> - <field> - <id>reserved</id> - <value>0</value> - </field> - </default> - <id>SCOM_SWITCHES</id> - </attribute> - <attribute> - <default>0,0,0,0,0,400,0,400,400,0,0,0,0,0,0,0</default> - <id>I2C_BUS_SPEED_ARRAY</id> - </attribute> - <attribute> - <default>0xFF</default> - <id>CENTAUR_ECID_FRU_ID</id> - </attribute> - <attribute> - <id>CEN_MSS_VOLT_VDD_MILLIVOLTS</id> - </attribute> - <attribute> - <id>CEN_MSS_VOLT_AVDD_MILLIVOLTS</id> - </attribute> - <attribute> - <id>CEN_MSS_VOLT_VCS_MILLIVOLTS</id> - </attribute> - <attribute> - <id>CEN_MSS_VOLT_VPP_MILLIVOLTS</id> - </attribute> - <attribute> - <id>CEN_MSS_VOLT_VDDR_MILLIVOLTS</id> - </attribute> - <attribute> - <id>CEN_MSS_VOLT_VDD_OFFSET_MILLIVOLTS</id> - </attribute> - <attribute> - <id>CEN_MSS_VOLT_AVDD_OFFSET_MILLIVOLTS</id> - </attribute> - <attribute> - <id>CEN_MSS_VOLT_VCS_OFFSET_MILLIVOLTS</id> - </attribute> - <attribute> - <id>CEN_MSS_VOLT_VDDR_OFFSET_MILLIVOLTS</id> - </attribute> - <attribute> - <id>VDD_ID</id> - </attribute> - <attribute> - <id>AVDD_ID</id> - </attribute> - <attribute> - <id>VCS_ID</id> - </attribute> - <attribute> - <id>VPP_ID</id> - </attribute> - <attribute> - <id>VDDR_ID</id> - </attribute> - <attribute> - <id>VPD_REC_NUM</id> - </attribute> - <attribute> - <default> - <field> - <id>useFsiI2C</id> - <value>1</value> - </field> - <field> - <id>useHostI2C</id> - <value>0</value> - </field> - <field> - <id>reserved</id> - <value>0</value> - </field> - </default> - <id>I2C_SWITCHES</id> - </attribute> - <attribute> - <default>MEM</default> - <id>CDM_DOMAIN</id> - </attribute> - <attribute> - <id>FRU_ID</id> - </attribute> -</targetType> - -<targetType> - <id>card</id> - <parent>base</parent> - <attribute> - <default>CARD</default> - <id>CLASS</id> - </attribute> - <attribute> - <id>LOCATION_CODE</id> - </attribute> -</targetType> - -<targetType> - <id>lcard-dimm</id> - <parent>card</parent> - <attribute> - <default>DIMM</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>LOGICAL_CARD</default> - <id>CLASS</id> - </attribute> - <attribute> - <id>POSITION</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>0x00000033</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <id>TEMP_SENSOR_I2C_CONFIG</id> - </attribute> - <attribute> - <id>VPD_REC_NUM</id> - </attribute> - <attribute> - <default>DIMM</default> - <id>CDM_DOMAIN</id> - </attribute> - <attribute> - <id>FRU_ID</id> - </attribute> - <attribute><id>REL_POS</id></attribute> - <attribute><id>MBA_PORT</id></attribute><!-- deprecated --> - <attribute><id>MEM_PORT</id></attribute> - <attribute><id>MBA_DIMM</id></attribute><!-- deprecated --> - <attribute><id>POS_ON_MEM_PORT</id></attribute> -</targetType> - -<targetType> - <id>lcard-dimm-jedec</id> - <attribute> - <default>JEDEC</default> - <id>MODEL</id> - </attribute> - <parent>lcard-dimm</parent> - <attribute> - <id>CEN_DQ_TO_DIMM_CONN_DQ</id> - </attribute> -</targetType> - -<targetType> - <id>lcard-dimm-cdimm</id> - <parent>lcard-dimm</parent> - <attribute> - <default>CDIMM</default> - <id>MODEL</id> - </attribute> -</targetType> - -<targetType> - <id>lcard-dimm-ddr4</id> - <parent>lcard-dimm</parent> -</targetType> - -<targetType> - <id>chip-fcdimm-ddr4</id> - <parent>lcard-dimm-cdimm</parent> -</targetType> - -<targetType> - <id>occ</id> - <parent>unit</parent> - <attribute> - <default>OCC</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>POWER9</default> - <id>MODEL</id> - </attribute> - <attribute> - <id>OCC_MASTER_CAPABLE</id> - </attribute> - <attribute> - <id>FRU_ID</id> - </attribute> -</targetType> - -<targetType> - <id>sys-sys-power9</id> - <parent>base</parent> - <attribute><id>FUSED_CORE_MODE_HB</id></attribute> - <attribute><id>WOF_TABLE_LID_NUMBER</id></attribute> - <attribute><id>SOCKET_POWER_NOMINAL</id></attribute> - <attribute><id>SOCKET_POWER_TURBO</id></attribute> - <attribute><id>FREQ_CORE_MAX</id></attribute> - <attribute><id>ULTRA_TURBO_FREQ_MHZ</id></attribute> - <attribute><id>PIB_I2C_NEST_PLL</id></attribute> - <attribute><id>NEST_PLL_FREQ_BUCKETS</id></attribute> - <attribute><id>NEST_PLL_FREQ_LIST</id></attribute> - <attribute><id>SBE_UPDATE_DISABLE</id></attribute> - <attribute><id>NEST_PLL_FREQ_I2CDIV_LIST</id></attribute> - <attribute><id>PROC_REFCLOCK_RCVR_TERM</id></attribute> - <attribute><id>PCI_REFCLOCK_RCVR_TERM</id></attribute> - <attribute><id>SYNC_BETWEEN_STEPS</id></attribute> - <attribute><id>MIRROR_BASE_ADDRESS</id></attribute> - <attribute><id>CVPD_SIZE</id></attribute> - <attribute><id>CVPD_MAX_SECTIONS</id></attribute> - <attribute> - <default>SYS</default> - <id>CLASS</id> - </attribute> - <attribute> - <default>SYS</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>POWER9</default> - <id>MODEL</id> - </attribute> - <attribute> - <default>0x00010000</default> - <id>HUID</id> - </attribute> - <attribute> - <default>physical:sys-0</default> - <id>PHYS_PATH</id> - </attribute> - <attribute> - <default>affinity:sys-0</default> - <id>AFFINITY_PATH</id> - </attribute> - <attribute> - <default>0x000603FC00000000</default> - <id>XSCOM_BASE_ADDRESS</id> - </attribute> - <attribute> - <default>0x0006030000000000</default> - <id>LPC_BUS_ADDR</id> - </attribute> - <attribute> - <id>HB_HRMOR_NODAL_BASE</id> - </attribute> - <attribute> - <id>TPM_REQUIRED</id> - </attribute> - <attribute> - <id>MAX_PROC_CHIPS_PER_NODE</id> - </attribute> - <attribute> - <id>MAX_EXS_PER_PROC_CHIP</id> - </attribute> - <attribute> - <default>43</default> - <id>MAX_CHIPLETS_PER_PROC</id> - </attribute> - <attribute> - <id>MAX_MCS_PER_SYSTEM</id> - </attribute> - <attribute> - <id>TEST_NEGATIVE_FCN</id> - </attribute> - <attribute> - <id>RECONFIG_LOOP_TESTS</id> - </attribute> - <attribute> - <id>ISTEP_PAUSE_ENABLE</id> - </attribute> - <attribute> - <id>ISTEP_PAUSE_CONFIG</id> - </attribute> - <attribute> - <id>FRU_ID</id> - </attribute> - <attribute> - <id>BMC_FRU_ID</id> - </attribute> - <attribute> - <id>DPO_MIN_FREQ_PERCENT</id> - </attribute> - <attribute> - <id>ASYNC_NEST_FREQ_MHZ</id> - </attribute> - <attribute> - <id>MNFG_TH_P8EX_L2_CACHE_CES</id> - </attribute> - <attribute> - <id>MNFG_TH_P8EX_L2_DIR_CES</id> - </attribute> - <attribute> - <id>MNFG_TH_P8EX_L3_CACHE_CES</id> - </attribute> - <attribute> - <id>MNFG_TH_P8EX_L3_DIR_CES</id> - </attribute> - <attribute> - <id>FIELD_TH_P8EX_L2_LINE_DELETES</id> - </attribute> - <attribute> - <id>FIELD_TH_P8EX_L3_LINE_DELETES</id> - </attribute> - <attribute> - <id>FIELD_TH_P8EX_L2_COL_REPAIRS</id> - </attribute> - <attribute> - <id>FIELD_TH_P8EX_L3_COL_REPAIRS</id> - </attribute> - <attribute> - <id>MNFG_TH_P8EX_L2_LINE_DELETES</id> - </attribute> - <attribute> - <id>MNFG_TH_P8EX_L3_LINE_DELETES</id> - </attribute> - <attribute> - <id>MNFG_TH_P8EX_L2_COL_REPAIRS</id> - </attribute> - <attribute> - <id>MNFG_TH_P8EX_L3_COL_REPAIRS</id> - </attribute> - <attribute> - <id>MNFG_TH_CEN_MBA_RT_SOFT_CE_TH_ALGO</id> - </attribute> - <attribute> - <id>MNFG_TH_CEN_MBA_IPL_SOFT_CE_TH_ALGO</id> - </attribute> - <attribute> - <id>MNFG_TH_CEN_MBA_RT_RCE_PER_RANK</id> - </attribute> - <attribute> - <id>MNFG_TH_CEN_L4_CACHE_CES</id> - </attribute> - <attribute> - <id>MNFG_TH_RCD_PARITY_ERRORS</id> - </attribute> - <attribute> - <id>MNFG_TH_MEMORY_IUES</id> - </attribute> - <attribute> - <id>MNFG_TH_MEMORY_IMPES</id> - </attribute> - <attribute> - <id>RCD_PARITY_RECONFIG_LOOPS_ALLOWED</id> - </attribute> - <attribute> - <id>BLOCK_SPEC_DECONFIG</id> - </attribute> - <attribute> - <id>MAX_PROC_CHIPS_PER_NODE</id> - </attribute> - <attribute> - <id>MAX_EXS_PER_PROC_CHIP</id> - </attribute> - <attribute> - <id>MAX_MBAS_PER_MEMBUF_CHIP</id> - </attribute> - <attribute> - <id>MAX_MBA_PORTS_PER_MBA</id> - </attribute> - <attribute> - <id>MAX_DIMMS_PER_MBA_PORT</id> - </attribute> - <attribute> - <id>MAX_CHIPLETS_PER_PROC</id> - </attribute> - <attribute> - <id>MAX_MCS_PER_SYSTEM</id> - </attribute> - <attribute> - <id>FABRIC_TO_PHYSICAL_NODE_MAP</id> - </attribute> - <attribute> - <id>RUN_MAX_MEM_PATTERNS</id> - </attribute> - <attribute> - <id>SP_FUNCTIONS</id> - </attribute> - <attribute> - <id>HB_SETTINGS</id> - </attribute> - <attribute> - <id>CEC_IPL_TYPE</id> - </attribute> - <attribute> - <id>PAYLOAD_KIND</id> - </attribute> - <attribute> - <id>PAYLOAD_BASE</id> - </attribute> - <attribute> - <id>PAYLOAD_ENTRY</id> - </attribute> - <attribute> - <id>ENABLED_THREADS</id> - </attribute> - <attribute> - <id>ISTEP_MODE</id> - </attribute> - <attribute> - <id>RECONFIG_LOOP_TESTS_ENABLE</id> - </attribute> - <attribute> - <id>ISTEP_PAUSE_ENABLE</id> - </attribute> - <attribute> - <id>ISTEP_PAUSE_CONFIG</id> - </attribute> - <attribute> - <id>CDM_POLICIES</id> - </attribute> - <attribute> - <id>HOSTSVC_PLID</id> - </attribute> - <attribute> - <id>FABRIC_TO_PHYSICAL_NODE_MAP</id> - </attribute> - <attribute> - <id>NUMERIC_POD_TYPE_TEST</id> - </attribute> - <attribute> - <id>TEST_NULL_STRING</id> - </attribute> - <attribute> - <default>Z</default> - <id>TEST_MIN_STRING</id> - </attribute> - <attribute> - <id>TEST_MAX_STRING</id> - </attribute> - <attribute> - <id>TEST_NO_DEFAULT_STRING</id> - </attribute> - <attribute> - <id>DO_ABUS_DECONFIG</id> - </attribute> - <attribute> - <id>PLCK_IPL_ATTR_OVERRIDES_EXIST</id> - </attribute> - <attribute> - <id>PAYLOAD_IN_MIRROR_MEM</id> - </attribute> - <attribute> - <id>FUSED_CORE_OPTION</id> - </attribute> - <attribute> - <id>EFFECTIVE_EC</id> - </attribute> - <attribute> - <id>HB_RSV_MEM_SIZE_MB</id> - </attribute> - <attribute> - <id>THREAD_COUNT</id> - </attribute> - <attribute> - <id>SYSTEM_IPL_PHASE</id> - </attribute> - <attribute> - <id>FREQ_CORE_CEILING_MHZ</id> - </attribute> - <attribute> - <id>HDAT_RSV_MEM_NUM_SECTIONS</id> - </attribute> - <attribute> - <id>HDAT_HBRT_NUM_SECTIONS</id> - </attribute> - <attribute> - <id>HDAT_HBRT_SECTION_SIZE</id> - </attribute> - <attribute> - <id>MSS_VOLT_DDR3_VDDR_SLOPE</id> - </attribute> - <attribute> - <id>MSS_VOLT_DDR3_VDDR_INTERCEPT</id> - </attribute> - <attribute> - <id>MSS_VOLT_DDR4_VDDR_SLOPE</id> - </attribute> - <attribute> - <id>MSS_VOLT_DDR4_VDDR_INTERCEPT</id> - </attribute> - <attribute> - <id>MRW_DDR3_VDDR_MAX_LIMIT</id> - </attribute> - <attribute> - <id>MRW_DDR4_VDDR_MAX_LIMIT</id> - </attribute> - <attribute> - <id>MSS_VOLT_DDR3_VDDR_SLOPE_POST_DRAM_INIT</id> - </attribute> - <attribute> - <id>MSS_VOLT_DDR3_VDDR_INTERCEPT_POST_DRAM_INIT</id> - </attribute> - <attribute> - <id>MRW_DDR3_VDDR_MAX_LIMIT_POST_DRAM_INIT</id> - </attribute> - <attribute> - <id>MSS_VOLT_DDR4_VDDR_SLOPE_POST_DRAM_INIT</id> - </attribute> - <attribute> - <id>MSS_VOLT_DDR4_VDDR_INTERCEPT_POST_DRAM_INIT</id> - </attribute> - <attribute> - <id>MRW_DDR4_VDDR_MAX_LIMIT_POST_DRAM_INIT</id> - </attribute> - <attribute> - <id>MSS_VOLT_VPP_SLOPE</id> - </attribute> - <attribute> - <id>MSS_VOLT_VPP_INTERCEPT</id> - </attribute> - <attribute> - <id>SUPPORTS_DYNAMIC_MEM_VOLT</id> - </attribute> - <attribute> - <id>MSS_VDD_PROGRAM</id> - </attribute> - <attribute> - <id>MSS_AVDD_PROGRAM</id> - </attribute> - <attribute> - <id>MSS_VCS_PROGRAM</id> - </attribute> - <attribute> - <id>MSS_VPP_PROGRAM</id> - </attribute> - <attribute> - <id>MSS_VDDR_PROGRAM</id> - </attribute> - <attribute> - <id>FSP_BAR_SIZE</id> - </attribute> - <attribute> - <id>WOF_POWER_LIMIT</id> - </attribute> - <attribute> - <id>STOP5_DISABLE</id> - </attribute> - <attribute> - <id>SUPPORTED_STOP_STATES</id> - </attribute> - <attribute> - <id>SYSTEM_FAMILY</id> - </attribute> - <attribute> - <id>SYSTEM_TYPE</id> - </attribute> - <attribute> - <id>MAX_SBE_SEEPROM_SIZE</id> - </attribute> - <attribute> - <id>RAW_MTM</id> - </attribute> - <attribute> - <id>MFG_TRACE_ENABLE</id> - </attribute> - <attribute> - <id>MFG_WRAP_TEST_ABUS_LINKS_SET_ENABLE</id> - </attribute> - <attribute> - <id>FREQ_PROC_REFCLOCK</id> - </attribute> - <attribute> - <id>X_EREPAIR_THRESHOLD_FIELD</id> - </attribute> - <attribute><id>O_EREPAIR_THRESHOLD_FIELD</id></attribute> - <attribute><id>DMI_EREPAIR_THRESHOLD_FIELD</id></attribute> - <attribute><id>X_EREPAIR_THRESHOLD_MNFG</id></attribute> - <attribute><id>O_EREPAIR_THRESHOLD_MNFG</id></attribute> - <attribute><id>DMI_EREPAIR_THRESHOLD_MNFG</id></attribute> - <attribute><id>MSS_MBA_ADDR_INTERLEAVE_BIT</id></attribute> - <attribute><id>MSS_MBA_CACHELINE_INTERLEAVE_MODE</id></attribute> - <attribute><id>PM_SPIVID_FREQUENCY</id></attribute> - <attribute><id>PM_SAFE_FREQUENCY</id></attribute> - <attribute><id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id></attribute> - <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id></attribute> - <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id></attribute> - <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id></attribute> - <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id></attribute> - <attribute><id>MRW_MEM_THROTTLE_DENOMINATOR</id></attribute> - <attribute><id>PM_SYSTEM_IVRM_VPD_MIN_LEVEL</id></attribute> - <attribute><id>MNFG_DMI_MIN_EYE_WIDTH</id></attribute> - <attribute><id>MNFG_DMI_MIN_EYE_HEIGHT</id></attribute> - <attribute><id>MNFG_ABUS_MIN_EYE_WIDTH</id></attribute> - <attribute><id>MNFG_ABUS_MIN_EYE_HEIGHT</id></attribute> - <attribute><id>MNFG_XBUS_MIN_EYE_WIDTH</id></attribute> - <attribute><id>REDUNDANT_CLOCKS</id></attribute> - <attribute><id>BRAZOS_RX_FIFO_OVERRIDE</id></attribute> - <attribute><id>MAX_DMI_PER_PROC</id></attribute> - <attribute><id>PIB_I2C_REFCLOCK</id></attribute> - <attribute><id>USE_TCES_FOR_DMAS</id></attribute> - <!--fsp requirement--> - <attribute> - <id>BOOT_FREQ_MHZ</id> - </attribute> - <attribute> - <id>MAX_COMPUTE_NODES_PER_SYSTEM</id> - </attribute> -</targetType> - -<targetType> - <id>enc-node-power9</id> - <parent>base</parent> - <attribute> - <default>ENC</default> - <id>CLASS</id> - </attribute> - <attribute> - <default>NODE</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>POWER9</default> - <id>MODEL</id> - </attribute> - <attribute> - <id>FIELD_CORE_OVERRIDE</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>0x00000039</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <default>NODE</default> - <id>CDM_DOMAIN</id> - </attribute> - <attribute> - <id>FRU_ID</id> - </attribute> - <attribute> - <id>KEY_TRANSITION_STATE</id> - </attribute> - <attribute> - <id>EEPROM_VPD_PRIMARY_INFO</id> - </attribute> - <attribute> - <id>HDAT_RSV_MEM_NUM_SECTIONS</id> - </attribute> - <attribute> - <id>HDAT_HBRT_NUM_SECTIONS</id> - </attribute> - <attribute> - <id>HDAT_HBRT_SECTION_SIZE</id> - </attribute> - <attribute> - <id>VPD_REC_NUM</id> - </attribute> - <attribute><id>MSS_VOLT_VPP_SLOPE_EFF_CONFIG</id></attribute> - <attribute><id>MSS_VOLT_VPP_INTERCEPT_EFF_CONFIG</id></attribute> - <attribute><id>MSS_VOLT_DDR3_VDDR_SLOPE_EFF_CONFIG</id></attribute> - <attribute><id>MSS_VOLT_DDR3_VDDR_INTERCEPT_EFF_CONFIG</id></attribute> - <attribute><id>MRW_DDR3_VDDR_MAX_LIMIT_EFF_CONFIG</id></attribute> - <attribute><id>MSS_VOLT_DDR4_VDDR_SLOPE_EFF_CONFIG</id></attribute> - <attribute><id>MSS_VOLT_DDR4_VDDR_INTERCEPT_EFF_CONFIG</id></attribute> - <attribute><id>MRW_DDR4_VDDR_MAX_LIMIT_EFF_CONFIG</id></attribute> - <attribute><id>TCE_START_TOKEN_FOR_PAYLOAD</id></attribute> - <attribute><id>START_MEM_ADDRESS_FOR_PAYLOAD_TCE_TOKEN</id></attribute> - <attribute><id>TCE_START_TOKEN_FOR_HDAT</id></attribute> - <attribute> - <default>0xFFFFFFFFFFFFFFFF</default> - <id>ATTN_AREA_1_ADDR</id> - </attribute> - <attribute> - <default>0xFFFFFFFFFFFFFFFF</default> - <id>ATTN_AREA_2_ADDR</id> - </attribute> -</targetType> - -<targetType> - <id>chip-tpm-cectpm</id> - <parent>chip</parent> - <attribute> - <default>TPM</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>CECTPM</default> - <id>MODEL</id> - </attribute> - <attribute> - <id>TPM_INFO</id> - </attribute> - <attribute> - <id>TPM_UNUSABLE</id> - </attribute> -</targetType> - -<!-- This special TPM target exists only to adapt Hostboot's TPM target to + <targetType> + <id>base</id> + <attribute> + <id>AFFINITY_PATH</id> + </attribute> + <attribute> + <id>CLASS</id> + </attribute> + <attribute> + <default>0</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <id>FAPI_NAME</id> + </attribute> + <attribute> + <id>HUID</id> + </attribute> + <attribute> + <id>HWAS_STATE</id> + </attribute> + <attribute> + <id>HWAS_STATE_CHANGED_FLAG</id> + </attribute> + <attribute> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>MODEL</id> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + </attribute> + <attribute> + <id>PHYS_PATH</id> + </attribute> + <attribute> + <id>PNOR_FLASH_WORKAROUNDS</id> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + </attribute> + <attribute> + <default>0</default> + <id>RESOURCE_IS_CRITICAL</id> + </attribute> + <attribute> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>card</id> + <parent>base</parent> + <attribute> + <default>CARD</default> + <id>CLASS</id> + </attribute> + <attribute> + <id>LOCATION_CODE</id> + </attribute> + </targetType> + + <targetType> + <id>chip</id> + <parent>base</parent> + <attribute> + <id>ALTFSI_MASTER_CHIP</id> + </attribute> + <attribute> + <id>ALTFSI_MASTER_PORT</id> + </attribute> + <attribute> + <id>CHIP_ID</id> + </attribute> + <attribute> + <default>CHIP</default> + <id>CLASS</id> + </attribute> + <attribute> + <id>EC</id> + </attribute> + <attribute> + <id>FRU_ID</id> + </attribute> + <attribute> + <id>FSI_MASTER_CHIP</id> + </attribute> + <attribute> + <id>FSI_MASTER_PORT</id> + </attribute> + <attribute> + <default>NO_MASTER</default> + <id>FSI_MASTER_TYPE</id> + </attribute> + <attribute> + <id>FSI_OPTION_FLAGS</id> + </attribute> + <attribute> + <id>FSI_SLAVE_CASCADE</id> + </attribute> + <attribute> + <id>HDAT_EC</id> + </attribute> + <attribute> + <id>MRU_ID</id> + </attribute> + <attribute> + <id>POSITION</id> + </attribute> + <attribute> + <id>PRD_HWP_PLID</id> + </attribute> + </targetType> + + <!-- This special TPM target exists only to adapt Hostboot's TPM target to various workbooks' TPM target; all attributes should be declared against the parent target --> -<targetType> + <targetType> <id>chip-NPCT501</id> <parent>chip-tpm-cectpm</parent> -</targetType> - -<targetType> - <id>chip-processor-power9</id> - <parent>chip-processor</parent> - <attribute> - <id>DUMMY_HEAP_ZERO_DEFAULT</id> - </attribute> - <attribute> - <id>EEPROM_VPD_PRIMARY_INFO</id> - </attribute> - <attribute> - <id>EEPROM_VPD_BACKUP_INFO</id> - </attribute> - <attribute> - <id>EEPROM_SBE_PRIMARY_INFO</id> - </attribute> - <attribute> - <id>EEPROM_SBE_BACKUP_INFO</id> - </attribute> - <attribute> - <default>0,0,0,0,0,0,0,0,0,0,0,0</default> - <id>I2C_BUS_SPEED_ARRAY</id> - </attribute> - <attribute> - <id>FSP_BAR_SIZE</id> - </attribute> - <attribute> - <id>PHB_BASE_ADDRS</id> - </attribute> - <attribute> - <id>PCI_BASE_ADDRS_64</id> - </attribute> - <attribute> - <id>PCI_BASE_ADDRS_32</id> - </attribute> - <attribute> - <id>RNG_BAR_SIZE</id> - </attribute> - <attribute> - <id>IMT_BASE_ADDR</id> - </attribute> - <attribute> - <id>IMT_BAR_SIZE</id> - </attribute> - <attribute> - <id>XIVE_CONTROLLER_BAR_ADDR</id> - </attribute> - <attribute> - <id>PSI_HB_ESB_ADDR</id> - </attribute> - <attribute> - <id>XIVE_THREAD_MGMT1_BAR_ADDR</id> - </attribute> - <attribute> - <id>XSCOM_BASE_ADDRESS</id> - </attribute> - <attribute> - <default>FABRIC</default> - <id>CDM_DOMAIN</id> - </attribute> - <attribute> - <id>ISTEP_MODE</id> - </attribute> - <attribute> - <default>32</default> - <id>DATA_CACHE_SIZE</id> - </attribute> - <attribute> - <default>10240</default> - <id>L3_CACHE_SIZE</id> - </attribute> - <attribute> - <default>8</default> - <id>ICACHE_ASSOC_SETS</id> - </attribute> - <attribute> - <default>1024</default> - <id>TLB_DATA_ENTRIES</id> - </attribute> - <attribute> - <default>0</default> - <id>TLB_INSTR_ENTRIES</id> - </attribute> - <attribute> - <default>4</default> - <id>TLB_DATA_ASSOC_SETS</id> - </attribute> - <attribute> - <default>0</default> - <id>TLB_INSTR_ASSOC_SETS</id> - </attribute> - <attribute> - <default>128</default> - <id>TLB_RESERVE_SIZE</id> - </attribute> - <attribute> - <default>128</default> - <id>DATA_CACHE_LINE_SIZE</id> - </attribute> - <attribute> - <default>128</default> - <id>L3_CACHE_LINE_SIZE</id> - </attribute> - <attribute> - <default>128</default> - <id>DCACHE_LINE_SIZE</id> - </attribute> - <attribute> - <default>8</default> - <id>DCACHE_ASSOC_SETS</id> - </attribute> - <attribute> - <default>128</default> - <id>ICACHE_BLOCK_SIZE</id> - </attribute> - <attribute> - <default>32</default> - <id>ICACHE_SIZE</id> - </attribute> - <attribute> - <default>128</default> - <id>ICACHE_LINE_SIZE</id> - </attribute> - <attribute> - <default>0x0000001D</default> - <id>CPU_ATTR</id> - </attribute> - <attribute> - <default>128</default> - <id>L2_CACHE_LINE_SIZE</id> - </attribute> - <attribute> - <default>512</default> - <id>L2_CACHE_SIZE</id> - </attribute> - <attribute> - <default>8</default> - <id>L2_CACHE_ASSOC_SETS</id> - </attribute> - <attribute> - <id>NEST_VDD_ID</id> - </attribute> - <attribute> - <id>NEST_VDN_ID</id> - </attribute> - <attribute> - <id>NEST_VCS_ID</id> - </attribute> - <attribute> - <id>NEST_VIO_ID</id> - </attribute> - <attribute> - <id>NEST_VDDR_ID</id> - </attribute> - <attribute> - <id>TOD_CPU_DATA</id> - </attribute> - <attribute> - <id>SECUREBOOT_PROTECT_DECONFIGURED_TPM</id> - </attribute> - <attribute><id>FSP_BASE_ADDR</id></attribute> - <attribute><id>PSI_BRIDGE_BASE_ADDR</id></attribute> - <attribute><id>INTP_BASE_ADDR</id></attribute> - <attribute><id>PROC_DCM_INSTALLED</id></attribute> - <attribute><id>SBE_IS_STARTED</id></attribute> - <attribute><id>PROC_PCIE_PHB_ACTIVE</id></attribute> - <attribute><id>LPC_BUS_ADDR</id></attribute> -</targetType> - -<targetType> - <id>chip-processor-nimbus</id> - <parent>chip-processor-power9</parent> - <attribute> - <default>NIMBUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<targetType> - <id>chip-processor-cumulus</id> - <parent>chip-processor-power9</parent> - <attribute> - <default>CUMULUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<!-- p9 sub-units --> -<!-- EQ chiplet: Use same EQ target for Nimbus and Cumulus + </targetType> + + <targetType> + <id>chip-bmc-ast2500</id> + <parent>sp</parent> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/bmc-0</default> + </attribute> + <attribute> + <default> + <field> + <id>deconfiguredByEid</id> + <value>0</value> + </field> + <field> + <id>dumpfunctional</id> + <value>0</value> + </field> + <field> + <id>functional</id> + <value>1</value> + </field> + <field> + <id>poweredOn</id> + <value>1</value> + </field> + <field> + <id>present</id> + <value>1</value> + </field> + <field> + <id>specdeconfig</id> + <value>0</value> + </field> + </default> + <id>HWAS_STATE</id> + </attribute> + <attribute> + <default>AST2500</default> + <id>MODEL</id> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/bmc-0</default> + </attribute> + <attribute> + <default>BMC</default> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>chip-fcdimm-ddr4</id> + <parent>lcard-dimm-cdimm</parent> + </targetType> + + <targetType> + <id>chip-membuf-centaur</id> + <parent>chip</parent> + <attribute> + <id>AVDD_ID</id> + </attribute> + <attribute> + <default>MEM</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <default>0xFF</default> + <id>CENTAUR_ECID_FRU_ID</id> + </attribute> + <attribute> + <id>CEN_MSS_VOLT_AVDD_MILLIVOLTS</id> + </attribute> + <attribute> + <id>CEN_MSS_VOLT_AVDD_OFFSET_MILLIVOLTS</id> + </attribute> + <attribute> + <id>CEN_MSS_VOLT_VCS_MILLIVOLTS</id> + </attribute> + <attribute> + <id>CEN_MSS_VOLT_VCS_OFFSET_MILLIVOLTS</id> + </attribute> + <attribute> + <id>CEN_MSS_VOLT_VDDR_MILLIVOLTS</id> + </attribute> + <attribute> + <id>CEN_MSS_VOLT_VDDR_OFFSET_MILLIVOLTS</id> + </attribute> + <attribute> + <id>CEN_MSS_VOLT_VDD_MILLIVOLTS</id> + </attribute> + <attribute> + <id>CEN_MSS_VOLT_VDD_OFFSET_MILLIVOLTS</id> + </attribute> + <attribute> + <id>CEN_MSS_VOLT_VPP_MILLIVOLTS</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <id>FRU_ID</id> + </attribute> + <attribute> + <default>0x00000033</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <default>0,0,0,0,0,400,0,400,400,0,0,0,0,0,0,0</default> + <id>I2C_BUS_SPEED_ARRAY</id> + </attribute> + <attribute> + <default> + <field> + <id>reserved</id> + <value>0</value> + </field> + <field> + <id>useFsiI2C</id> + <value>1</value> + </field> + <field> + <id>useHostI2C</id> + <value>0</value> + </field> + </default> + <id>I2C_SWITCHES</id> + </attribute> + <attribute> + <default>CENTAUR</default> + <id>MODEL</id> + </attribute> + <attribute> + <default> + <field> + <id>reserved</id> + <value>0</value> + </field> + <field> + <id>supportsFsiScom</id> + <value>1</value> + </field> + <field> + <id>supportsInbandScom</id> + <value>1</value> + </field> + <field> + <id>supportsXscom</id> + <value>0</value> + </field> + </default> + <id>PRIMARY_CAPABILITIES</id> + </attribute> + <attribute> + <default> + <field> + <id>reserved</id> + <value>0</value> + </field> + <field> + <id>useFsiScom</id> + <value>0</value> + </field> + <field> + <id>useInbandScom</id> + <value>0</value> + </field> + <field> + <id>useSbeScom</id> + <value>1</value> + </field> + <field> + <id>useXscom</id> + <value>0</value> + </field> + </default> + <id>SCOM_SWITCHES</id> + </attribute> + <attribute> + <default>MEMBUF</default> + <id>TYPE</id> + </attribute> + <attribute> + <id>VCS_ID</id> + </attribute> + <attribute> + <id>VDDR_ID</id> + </attribute> + <attribute> + <id>VDD_ID</id> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + </attribute> + <attribute> + <id>VPP_ID</id> + </attribute> + </targetType> + + <!-- Generic OCMB --> + <targetType> + <id>chip-ocmb</id> + <parent>chip</parent> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <id>FRU_ID</id> + </attribute> + <attribute> + <default>0x00000033</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <default>OCMB_CHIP</default> + <id>TYPE</id> + </attribute> + </targetType> + + <!-- Explorer OCMB --> + <targetType> + <id>chip-ocmb-explorer</id> + <parent>chip-ocmb</parent> + <attribute> + <default>EXPLORER</default> + <id>MODEL</id> + </attribute> + </targetType> + + <targetType> + <id>chip-processor</id> + <parent>chip</parent> + <attribute> + <default>FABRIC</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <id>CPU_ATTR</id> + </attribute> + <attribute> + <id>DATA_CACHE_LINE_SIZE</id> + </attribute> + <attribute> + <id>DATA_CACHE_SIZE</id> + </attribute> + <attribute> + <id>DCACHE_ASSOC_SETS</id> + </attribute> + <attribute> + <id>DCACHE_LINE_SIZE</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <id>DISABLE_I2C_ENGINE2_PORT0_DIAG_MODE</id> + </attribute> + <attribute> + <id>FABRIC_CHIP_ID</id> + </attribute> + <attribute> + <id>FABRIC_GROUP_ID</id> + </attribute> + <attribute> + <id>HOT_PLUG_POWER_CONTROLLER_INFO</id> + </attribute> + <attribute> + <default>0x00000031</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <default> + <field> + <id>reserved</id> + <value>0</value> + </field> + <field> + <id>useFsiI2C</id> + <value>1</value> + </field> + <field> + <id>useHostI2C</id> + <value>0</value> + </field> + </default> + <id>I2C_SWITCHES</id> + </attribute> + <attribute> + <id>ICACHE_ASSOC_SETS</id> + </attribute> + <attribute> + <id>ICACHE_BLOCK_SIZE</id> + </attribute> + <attribute> + <id>ICACHE_LINE_SIZE</id> + </attribute> + <attribute> + <id>ICACHE_SIZE</id> + </attribute> + <attribute> + <id>L2_CACHE_ASSOC_SETS</id> + </attribute> + <attribute> + <id>L2_CACHE_LINE_SIZE</id> + </attribute> + <attribute> + <id>L2_CACHE_SIZE</id> + </attribute> + <attribute> + <id>L3_CACHE_LINE_SIZE</id> + </attribute> + <attribute> + <id>L3_CACHE_SIZE</id> + </attribute> + <attribute> + <id>LOCATION_CODE</id> + </attribute> + <attribute> + <id>PM_PBAX_NODEID</id> + </attribute> + <attribute> + <id>PM_SLEEP_ENTRY</id> + </attribute> + <attribute> + <id>PM_SLEEP_EXIT</id> + </attribute> + <attribute> + <id>PM_SLEEP_TYPE</id> + </attribute> + <attribute> + <id>PM_SPIVID_PORT_ENABLE</id> + </attribute> + <attribute> + <id>PM_UNDERVOLTING_FREQ_MAXIMUM</id> + </attribute> + <attribute> + <id>PM_UNDERVOLTING_FRQ_MINIMUM</id> + </attribute> + <attribute> + <id>PM_WINKLE_ENTRY</id> + </attribute> + <attribute> + <id>PM_WINKLE_EXIT</id> + </attribute> + <attribute> + <id>PM_WINKLE_TYPE</id> + </attribute> + <attribute> + <default> + <field> + <id>reserved</id> + <value>0</value> + </field> + <field> + <id>supportsFsiScom</id> + <value>1</value> + </field> + <field> + <id>supportsInbandScom</id> + <value>0</value> + </field> + <field> + <id>supportsXscom</id> + <value>1</value> + </field> + </default> + <id>PRIMARY_CAPABILITIES</id> + </attribute> + <attribute> + <id>PROC_MASTER_TYPE</id> + </attribute> + <attribute> + <id>SBE_COMMIT_ID</id> + </attribute> + <attribute> + <id>SBE_RELEASE_TAG</id> + </attribute> + <attribute> + <id>SBE_VERSION_INFO</id> + </attribute> + <attribute> + <id>SCOM_SWITCHES</id> + </attribute> + <attribute> + <id>TIME_BASE</id> + </attribute> + <attribute> + <id>TLB_DATA_ASSOC_SETS</id> + </attribute> + <attribute> + <id>TLB_DATA_ENTRIES</id> + </attribute> + <attribute> + <id>TLB_INSTR_ASSOC_SETS</id> + </attribute> + <attribute> + <id>TLB_INSTR_ENTRIES</id> + </attribute> + <attribute> + <id>TLB_RESERVE_SIZE</id> + </attribute> + <attribute> + <id>TOD_CPU_DATA</id> + </attribute> + <attribute> + <id>TOD_ROLE</id> + </attribute> + <attribute> + <default>PROC</default> + <id>TYPE</id> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + </attribute> + <attribute> + <id>XIVE_HW_RESET</id> + </attribute> + </targetType> + + <targetType> + <id>chip-processor-cumulus</id> + <parent>chip-processor-power9</parent> + <attribute> + <default>CUMULUS</default> + <id>MODEL</id> + </attribute> + </targetType> + + <targetType> + <id>chip-processor-nimbus</id> + <parent>chip-processor-power9</parent> + <attribute> + <default>NIMBUS</default> + <id>MODEL</id> + </attribute> + </targetType> + + <targetType> + <id>chip-processor-power9</id> + <parent>chip-processor</parent> + <attribute> + <default>FABRIC</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <default>0x0000001D</default> + <id>CPU_ATTR</id> + </attribute> + <attribute> + <default>128</default> + <id>DATA_CACHE_LINE_SIZE</id> + </attribute> + <attribute> + <default>32</default> + <id>DATA_CACHE_SIZE</id> + </attribute> + <attribute> + <default>8</default> + <id>DCACHE_ASSOC_SETS</id> + </attribute> + <attribute> + <default>128</default> + <id>DCACHE_LINE_SIZE</id> + </attribute> + <attribute> + <id>DUMMY_HEAP_ZERO_DEFAULT</id> + </attribute> + <attribute> + <id>EEPROM_SBE_BACKUP_INFO</id> + </attribute> + <attribute> + <id>EEPROM_SBE_PRIMARY_INFO</id> + </attribute> + <attribute> + <id>EEPROM_VPD_BACKUP_INFO</id> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + </attribute> + <attribute> + <id>FSP_BAR_SIZE</id> + </attribute> + <attribute> + <id>FSP_BASE_ADDR</id> + </attribute> + <attribute> + <default>0,0,0,0,0,0,0,0,0,0,0,0</default> + <id>I2C_BUS_SPEED_ARRAY</id> + </attribute> + <attribute> + <default>8</default> + <id>ICACHE_ASSOC_SETS</id> + </attribute> + <attribute> + <default>128</default> + <id>ICACHE_BLOCK_SIZE</id> + </attribute> + <attribute> + <default>128</default> + <id>ICACHE_LINE_SIZE</id> + </attribute> + <attribute> + <default>32</default> + <id>ICACHE_SIZE</id> + </attribute> + <attribute> + <id>IMT_BAR_SIZE</id> + </attribute> + <attribute> + <id>IMT_BASE_ADDR</id> + </attribute> + <attribute> + <id>INTP_BASE_ADDR</id> + </attribute> + <attribute> + <id>ISTEP_MODE</id> + </attribute> + <attribute> + <default>8</default> + <id>L2_CACHE_ASSOC_SETS</id> + </attribute> + <attribute> + <default>128</default> + <id>L2_CACHE_LINE_SIZE</id> + </attribute> + <attribute> + <default>512</default> + <id>L2_CACHE_SIZE</id> + </attribute> + <attribute> + <default>128</default> + <id>L3_CACHE_LINE_SIZE</id> + </attribute> + <attribute> + <default>10240</default> + <id>L3_CACHE_SIZE</id> + </attribute> + <attribute> + <id>LPC_BUS_ADDR</id> + </attribute> + <attribute> + <id>NEST_VCS_ID</id> + </attribute> + <attribute> + <id>NEST_VDDR_ID</id> + </attribute> + <attribute> + <id>NEST_VDD_ID</id> + </attribute> + <attribute> + <id>NEST_VDN_ID</id> + </attribute> + <attribute> + <id>NEST_VIO_ID</id> + </attribute> + <attribute> + <id>PCI_BASE_ADDRS_32</id> + </attribute> + <attribute> + <id>PCI_BASE_ADDRS_64</id> + </attribute> + <attribute> + <id>PHB_BASE_ADDRS</id> + </attribute> + <attribute> + <id>PROC_DCM_INSTALLED</id> + </attribute> + <attribute> + <id>PROC_PCIE_PHB_ACTIVE</id> + </attribute> + <attribute> + <id>PSI_BRIDGE_BASE_ADDR</id> + </attribute> + <attribute> + <id>PSI_HB_ESB_ADDR</id> + </attribute> + <attribute> + <id>RNG_BAR_SIZE</id> + </attribute> + <attribute> + <id>SBE_IS_STARTED</id> + </attribute> + <attribute> + <id>SECUREBOOT_PROTECT_DECONFIGURED_TPM</id> + </attribute> + <attribute> + <default>4</default> + <id>TLB_DATA_ASSOC_SETS</id> + </attribute> + <attribute> + <default>1024</default> + <id>TLB_DATA_ENTRIES</id> + </attribute> + <attribute> + <default>0</default> + <id>TLB_INSTR_ASSOC_SETS</id> + </attribute> + <attribute> + <default>0</default> + <id>TLB_INSTR_ENTRIES</id> + </attribute> + <attribute> + <default>128</default> + <id>TLB_RESERVE_SIZE</id> + </attribute> + <attribute> + <id>TOD_CPU_DATA</id> + </attribute> + <attribute> + <id>XIVE_CONTROLLER_BAR_ADDR</id> + </attribute> + <attribute> + <id>XIVE_THREAD_MGMT1_BAR_ADDR</id> + </attribute> + <attribute> + <id>XSCOM_BASE_ADDRESS</id> + </attribute> + </targetType> + + <targetType> + <id>chip-tpm-cectpm</id> + <parent>chip</parent> + <attribute> + <default>CECTPM</default> + <id>MODEL</id> + </attribute> + <attribute> + <id>TPM_INFO</id> + </attribute> + <attribute> + <id>TPM_UNUSABLE</id> + </attribute> + <attribute> + <default>TPM</default> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>enc-node-power9</id> + <parent>base</parent> + <attribute> + <default>0xFFFFFFFFFFFFFFFF</default> + <id>ATTN_AREA_1_ADDR</id> + </attribute> + <attribute> + <default>0xFFFFFFFFFFFFFFFF</default> + <id>ATTN_AREA_2_ADDR</id> + </attribute> + <attribute> + <default>NODE</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <default>ENC</default> + <id>CLASS</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + </attribute> + <attribute> + <id>FIELD_CORE_OVERRIDE</id> + </attribute> + <attribute> + <id>FRU_ID</id> + </attribute> + <attribute> + <id>HDAT_HBRT_NUM_SECTIONS</id> + </attribute> + <attribute> + <id>HDAT_HBRT_SECTION_SIZE</id> + </attribute> + <attribute> + <id>HDAT_RSV_MEM_NUM_SECTIONS</id> + </attribute> + <attribute> + <default>0x00000039</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>KEY_TRANSITION_STATE</id> + </attribute> + <attribute> + <default>POWER9</default> + <id>MODEL</id> + </attribute> + <attribute> + <id>MRW_DDR3_VDDR_MAX_LIMIT_EFF_CONFIG</id> + </attribute> + <attribute> + <id>MRW_DDR4_VDDR_MAX_LIMIT_EFF_CONFIG</id> + </attribute> + <attribute> + <id>MSS_VOLT_DDR3_VDDR_INTERCEPT_EFF_CONFIG</id> + </attribute> + <attribute> + <id>MSS_VOLT_DDR3_VDDR_SLOPE_EFF_CONFIG</id> + </attribute> + <attribute> + <id>MSS_VOLT_DDR4_VDDR_INTERCEPT_EFF_CONFIG</id> + </attribute> + <attribute> + <id>MSS_VOLT_DDR4_VDDR_SLOPE_EFF_CONFIG</id> + </attribute> + <attribute> + <id>MSS_VOLT_VPP_INTERCEPT_EFF_CONFIG</id> + </attribute> + <attribute> + <id>MSS_VOLT_VPP_SLOPE_EFF_CONFIG</id> + </attribute> + <attribute> + <id>START_MEM_ADDRESS_FOR_PAYLOAD_TCE_TOKEN</id> + </attribute> + <attribute> + <id>TCE_START_TOKEN_FOR_HDAT</id> + </attribute> + <attribute> + <id>TCE_START_TOKEN_FOR_PAYLOAD</id> + </attribute> + <attribute> + <default>NODE</default> + <id>TYPE</id> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + </attribute> + </targetType> + + <targetType> + <id>eth</id> + <parent>unit</parent> + <attribute> + <default>UNIT</default> + <id>CLASS</id> + </attribute> + <attribute> + <default>ETH</default> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>fan</id> + <parent>unit</parent> + <attribute> + <default>UNIT</default> + <id>CLASS</id> + </attribute> + <attribute> + <default>FAN</default> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>lcard-dimm</id> + <parent>card</parent> + <attribute> + <default>DIMM</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <default>LOGICAL_CARD</default> + <id>CLASS</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <id>FRU_ID</id> + </attribute> + <attribute> + <default>0x00000033</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <!-- deprecated --> + <attribute> + <id>MBA_DIMM</id> + </attribute> + <!-- deprecated --> + <attribute> + <id>MBA_PORT</id> + </attribute> + <attribute> + <id>MEM_PORT</id> + </attribute> + <attribute> + <id>POSITION</id> + </attribute> + <attribute> + <id>POS_ON_MEM_PORT</id> + </attribute> + <attribute> + <id>REL_POS</id> + </attribute> + <attribute> + <id>TEMP_SENSOR_I2C_CONFIG</id> + </attribute> + <attribute> + <default>DIMM</default> + <id>TYPE</id> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + </attribute> + </targetType> + + <targetType> + <id>lcard-dimm-cdimm</id> + <parent>lcard-dimm</parent> + <attribute> + <default>CDIMM</default> + <id>MODEL</id> + </attribute> + </targetType> + + <targetType> + <id>lcard-dimm-ddr4</id> + <parent>lcard-dimm</parent> + </targetType> + + <targetType> + <id>lcard-dimm-jedec</id> + <parent>lcard-dimm</parent> + <attribute> + <id>CEN_DQ_TO_DIMM_CONN_DQ</id> + </attribute> + <attribute> + <default>JEDEC</default> + <id>MODEL</id> + </attribute> + </targetType> + + <targetType> + <id>occ</id> + <parent>unit</parent> + <attribute> + <id>FRU_ID</id> + </attribute> + <attribute> + <default>POWER9</default> + <id>MODEL</id> + </attribute> + <attribute> + <id>OCC_MASTER_CAPABLE</id> + </attribute> + <attribute> + <default>OCC</default> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>panel</id> + <parent>unit</parent> + <attribute> + <default>PANEL</default> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>power-supply</id> + <parent>unit</parent> + <attribute> + <default>UNIT</default> + <id>CLASS</id> + </attribute> + <attribute> + <default>PS</default> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>sp</id> + <parent>base</parent> + <attribute> + <default>SP</default> + <id>CLASS</id> + </attribute> + <attribute> + <default>SP</default> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>sys-sys-power9</id> + <parent>base</parent> + <attribute> + <default>affinity:sys-0</default> + <id>AFFINITY_PATH</id> + </attribute> + <attribute> + <id>ASYNC_NEST_FREQ_MHZ</id> + </attribute> + <attribute> + <id>BLOCK_SPEC_DECONFIG</id> + </attribute> + <attribute> + <id>BMC_FRU_ID</id> + </attribute> + <!--fsp requirement--> + <attribute> + <id>BOOT_FREQ_MHZ</id> + </attribute> + <attribute> + <id>BRAZOS_RX_FIFO_OVERRIDE</id> + </attribute> + <attribute> + <id>CDM_POLICIES</id> + </attribute> + <attribute> + <id>CEC_IPL_TYPE</id> + </attribute> + <attribute> + <default>SYS</default> + <id>CLASS</id> + </attribute> + <attribute> + <id>CVPD_MAX_SECTIONS</id> + </attribute> + <attribute> + <id>CVPD_SIZE</id> + </attribute> + <attribute> + <id>DMI_EREPAIR_THRESHOLD_FIELD</id> + </attribute> + <attribute> + <id>DMI_EREPAIR_THRESHOLD_MNFG</id> + </attribute> + <attribute> + <id>DO_ABUS_DECONFIG</id> + </attribute> + <attribute> + <id>DPO_MIN_FREQ_PERCENT</id> + </attribute> + <attribute> + <id>EFFECTIVE_EC</id> + </attribute> + <attribute> + <id>ENABLED_THREADS</id> + </attribute> + <attribute> + <id>FABRIC_TO_PHYSICAL_NODE_MAP</id> + </attribute> + <attribute> + <id>FABRIC_TO_PHYSICAL_NODE_MAP</id> + </attribute> + <attribute> + <id>FIELD_TH_P8EX_L2_COL_REPAIRS</id> + </attribute> + <attribute> + <id>FIELD_TH_P8EX_L2_LINE_DELETES</id> + </attribute> + <attribute> + <id>FIELD_TH_P8EX_L3_COL_REPAIRS</id> + </attribute> + <attribute> + <id>FIELD_TH_P8EX_L3_LINE_DELETES</id> + </attribute> + <attribute> + <id>FREQ_CORE_CEILING_MHZ</id> + </attribute> + <attribute> + <id>FREQ_CORE_MAX</id> + </attribute> + <attribute> + <id>FREQ_PROC_REFCLOCK</id> + </attribute> + <attribute> + <id>FRU_ID</id> + </attribute> + <attribute> + <id>FSP_BAR_SIZE</id> + </attribute> + <attribute> + <id>FUSED_CORE_MODE_HB</id> + </attribute> + <attribute> + <id>FUSED_CORE_OPTION</id> + </attribute> + <attribute> + <id>HB_HRMOR_NODAL_BASE</id> + </attribute> + <attribute> + <id>HB_RSV_MEM_SIZE_MB</id> + </attribute> + <attribute> + <id>HB_SETTINGS</id> + </attribute> + <attribute> + <id>HDAT_HBRT_NUM_SECTIONS</id> + </attribute> + <attribute> + <id>HDAT_HBRT_SECTION_SIZE</id> + </attribute> + <attribute> + <id>HDAT_RSV_MEM_NUM_SECTIONS</id> + </attribute> + <attribute> + <id>HOSTSVC_PLID</id> + </attribute> + <attribute> + <default>0x00010000</default> + <id>HUID</id> + </attribute> + <attribute> + <id>ISTEP_MODE</id> + </attribute> + <attribute> + <id>ISTEP_PAUSE_CONFIG</id> + </attribute> + <attribute> + <id>ISTEP_PAUSE_CONFIG</id> + </attribute> + <attribute> + <id>ISTEP_PAUSE_ENABLE</id> + </attribute> + <attribute> + <id>ISTEP_PAUSE_ENABLE</id> + </attribute> + <attribute> + <default>0x0006030000000000</default> + <id>LPC_BUS_ADDR</id> + </attribute> + <attribute> + <default>43</default> + <id>MAX_CHIPLETS_PER_PROC</id> + </attribute> + <attribute> + <id>MAX_CHIPLETS_PER_PROC</id> + </attribute> + <attribute> + <id>MAX_COMPUTE_NODES_PER_SYSTEM</id> + </attribute> + <attribute> + <id>MAX_DIMMS_PER_MBA_PORT</id> + </attribute> + <attribute> + <id>MAX_DMI_PER_PROC</id> + </attribute> + <attribute> + <id>MAX_EXS_PER_PROC_CHIP</id> + </attribute> + <attribute> + <id>MAX_EXS_PER_PROC_CHIP</id> + </attribute> + <attribute> + <id>MAX_MBAS_PER_MEMBUF_CHIP</id> + </attribute> + <attribute> + <id>MAX_MBA_PORTS_PER_MBA</id> + </attribute> + <attribute> + <id>MAX_MCS_PER_SYSTEM</id> + </attribute> + <attribute> + <id>MAX_MCS_PER_SYSTEM</id> + </attribute> + <attribute> + <id>MAX_PROC_CHIPS_PER_NODE</id> + </attribute> + <attribute> + <id>MAX_PROC_CHIPS_PER_NODE</id> + </attribute> + <attribute> + <id>MAX_SBE_SEEPROM_SIZE</id> + </attribute> + <attribute> + <id>MFG_TRACE_ENABLE</id> + </attribute> + <attribute> + <id>MFG_WRAP_TEST_ABUS_LINKS_SET_ENABLE</id> + </attribute> + <attribute> + <id>MIRROR_BASE_ADDRESS</id> + </attribute> + <attribute> + <id>MNFG_ABUS_MIN_EYE_HEIGHT</id> + </attribute> + <attribute> + <id>MNFG_ABUS_MIN_EYE_WIDTH</id> + </attribute> + <attribute> + <id>MNFG_DMI_MIN_EYE_HEIGHT</id> + </attribute> + <attribute> + <id>MNFG_DMI_MIN_EYE_WIDTH</id> + </attribute> + <attribute> + <id>MNFG_TH_CEN_L4_CACHE_CES</id> + </attribute> + <attribute> + <id>MNFG_TH_CEN_MBA_IPL_SOFT_CE_TH_ALGO</id> + </attribute> + <attribute> + <id>MNFG_TH_CEN_MBA_RT_RCE_PER_RANK</id> + </attribute> + <attribute> + <id>MNFG_TH_CEN_MBA_RT_SOFT_CE_TH_ALGO</id> + </attribute> + <attribute> + <id>MNFG_TH_MEMORY_IMPES</id> + </attribute> + <attribute> + <id>MNFG_TH_MEMORY_IUES</id> + </attribute> + <attribute> + <id>MNFG_TH_P8EX_L2_CACHE_CES</id> + </attribute> + <attribute> + <id>MNFG_TH_P8EX_L2_COL_REPAIRS</id> + </attribute> + <attribute> + <id>MNFG_TH_P8EX_L2_DIR_CES</id> + </attribute> + <attribute> + <id>MNFG_TH_P8EX_L2_LINE_DELETES</id> + </attribute> + <attribute> + <id>MNFG_TH_P8EX_L3_CACHE_CES</id> + </attribute> + <attribute> + <id>MNFG_TH_P8EX_L3_COL_REPAIRS</id> + </attribute> + <attribute> + <id>MNFG_TH_P8EX_L3_DIR_CES</id> + </attribute> + <attribute> + <id>MNFG_TH_P8EX_L3_LINE_DELETES</id> + </attribute> + <attribute> + <id>MNFG_TH_RCD_PARITY_ERRORS</id> + </attribute> + <attribute> + <id>MNFG_XBUS_MIN_EYE_WIDTH</id> + </attribute> + <attribute> + <default>POWER9</default> + <id>MODEL</id> + </attribute> + <attribute> + <id>MRW_DDR3_VDDR_MAX_LIMIT</id> + </attribute> + <attribute> + <id>MRW_DDR3_VDDR_MAX_LIMIT_POST_DRAM_INIT</id> + </attribute> + <attribute> + <id>MRW_DDR4_VDDR_MAX_LIMIT</id> + </attribute> + <attribute> + <id>MRW_DDR4_VDDR_MAX_LIMIT_POST_DRAM_INIT</id> + </attribute> + <attribute> + <id>MRW_MEM_THROTTLE_DENOMINATOR</id> + </attribute> + <attribute> + <id>MSS_AVDD_PROGRAM</id> + </attribute> + <attribute> + <id>MSS_MBA_ADDR_INTERLEAVE_BIT</id> + </attribute> + <attribute> + <id>MSS_MBA_CACHELINE_INTERLEAVE_MODE</id> + </attribute> + <attribute> + <id>MSS_VCS_PROGRAM</id> + </attribute> + <attribute> + <id>MSS_VDDR_PROGRAM</id> + </attribute> + <attribute> + <id>MSS_VDD_PROGRAM</id> + </attribute> + <attribute> + <id>MSS_VOLT_DDR3_VDDR_INTERCEPT</id> + </attribute> + <attribute> + <id>MSS_VOLT_DDR3_VDDR_INTERCEPT_POST_DRAM_INIT</id> + </attribute> + <attribute> + <id>MSS_VOLT_DDR3_VDDR_SLOPE</id> + </attribute> + <attribute> + <id>MSS_VOLT_DDR3_VDDR_SLOPE_POST_DRAM_INIT</id> + </attribute> + <attribute> + <id>MSS_VOLT_DDR4_VDDR_INTERCEPT</id> + </attribute> + <attribute> + <id>MSS_VOLT_DDR4_VDDR_INTERCEPT_POST_DRAM_INIT</id> + </attribute> + <attribute> + <id>MSS_VOLT_DDR4_VDDR_SLOPE</id> + </attribute> + <attribute> + <id>MSS_VOLT_DDR4_VDDR_SLOPE_POST_DRAM_INIT</id> + </attribute> + <attribute> + <id>MSS_VOLT_VPP_INTERCEPT</id> + </attribute> + <attribute> + <id>MSS_VOLT_VPP_SLOPE</id> + </attribute> + <attribute> + <id>MSS_VPP_PROGRAM</id> + </attribute> + <attribute> + <id>NEST_PLL_FREQ_BUCKETS</id> + </attribute> + <attribute> + <id>NEST_PLL_FREQ_I2CDIV_LIST</id> + </attribute> + <attribute> + <id>NEST_PLL_FREQ_LIST</id> + </attribute> + <attribute> + <id>NUMERIC_POD_TYPE_TEST</id> + </attribute> + <attribute> + <id>O_EREPAIR_THRESHOLD_FIELD</id> + </attribute> + <attribute> + <id>O_EREPAIR_THRESHOLD_MNFG</id> + </attribute> + <attribute> + <id>PAYLOAD_BASE</id> + </attribute> + <attribute> + <id>PAYLOAD_ENTRY</id> + </attribute> + <attribute> + <id>PAYLOAD_IN_MIRROR_MEM</id> + </attribute> + <attribute> + <id>PAYLOAD_KIND</id> + </attribute> + <attribute> + <id>PCI_REFCLOCK_RCVR_TERM</id> + </attribute> + <attribute> + <default>physical:sys-0</default> + <id>PHYS_PATH</id> + </attribute> + <attribute> + <id>PIB_I2C_NEST_PLL</id> + </attribute> + <attribute> + <id>PIB_I2C_REFCLOCK</id> + </attribute> + <attribute> + <id>PLCK_IPL_ATTR_OVERRIDES_EXIST</id> + </attribute> + <attribute> + <id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> + </attribute> + <attribute> + <id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> + </attribute> + <attribute> + <id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> + </attribute> + <attribute> + <id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> + </attribute> + <attribute> + <id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> + </attribute> + <attribute> + <id>PM_SAFE_FREQUENCY</id> + </attribute> + <attribute> + <id>PM_SPIVID_FREQUENCY</id> + </attribute> + <attribute> + <id>PM_SYSTEM_IVRM_VPD_MIN_LEVEL</id> + </attribute> + <attribute> + <id>PROC_REFCLOCK_RCVR_TERM</id> + </attribute> + <attribute> + <id>RAW_MTM</id> + </attribute> + <attribute> + <id>RCD_PARITY_RECONFIG_LOOPS_ALLOWED</id> + </attribute> + <attribute> + <id>RECONFIG_LOOP_TESTS</id> + </attribute> + <attribute> + <id>RECONFIG_LOOP_TESTS_ENABLE</id> + </attribute> + <attribute> + <id>REDUNDANT_CLOCKS</id> + </attribute> + <attribute> + <id>RUN_MAX_MEM_PATTERNS</id> + </attribute> + <attribute> + <id>SBE_UPDATE_DISABLE</id> + </attribute> + <attribute> + <id>SOCKET_POWER_NOMINAL</id> + </attribute> + <attribute> + <id>SOCKET_POWER_TURBO</id> + </attribute> + <attribute> + <id>SP_FUNCTIONS</id> + </attribute> + <attribute> + <id>STOP5_DISABLE</id> + </attribute> + <attribute> + <id>SUPPORTED_STOP_STATES</id> + </attribute> + <attribute> + <id>SUPPORTS_DYNAMIC_MEM_VOLT</id> + </attribute> + <attribute> + <id>SYNC_BETWEEN_STEPS</id> + </attribute> + <attribute> + <id>SYSTEM_FAMILY</id> + </attribute> + <attribute> + <id>SYSTEM_IPL_PHASE</id> + </attribute> + <attribute> + <id>SYSTEM_TYPE</id> + </attribute> + <attribute> + <id>TEST_MAX_STRING</id> + </attribute> + <attribute> + <default>Z</default> + <id>TEST_MIN_STRING</id> + </attribute> + <attribute> + <id>TEST_NEGATIVE_FCN</id> + </attribute> + <attribute> + <id>TEST_NO_DEFAULT_STRING</id> + </attribute> + <attribute> + <id>TEST_NULL_STRING</id> + </attribute> + <attribute> + <id>THREAD_COUNT</id> + </attribute> + <attribute> + <id>TPM_REQUIRED</id> + </attribute> + <attribute> + <default>SYS</default> + <id>TYPE</id> + </attribute> + <attribute> + <id>ULTRA_TURBO_FREQ_MHZ</id> + </attribute> + <attribute> + <id>USE_TCES_FOR_DMAS</id> + </attribute> + <attribute> + <id>WOF_POWER_LIMIT</id> + </attribute> + <attribute> + <id>WOF_TABLE_LID_NUMBER</id> + </attribute> + <attribute> + <default>0x000603FC00000000</default> + <id>XSCOM_BASE_ADDRESS</id> + </attribute> + <attribute> + <id>X_EREPAIR_THRESHOLD_FIELD</id> + </attribute> + <attribute> + <id>X_EREPAIR_THRESHOLD_MNFG</id> + </attribute> + </targetType> + + <targetType> + <id>uart</id> + <parent>unit</parent> + <attribute> + <default>UNIT</default> + <id>CLASS</id> + </attribute> + <attribute> + <default>UART</default> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>unit</id> + <parent>base</parent> + <attribute> + <id>CHIPLET_ID</id> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + </attribute> + <attribute> + <default>UNIT</default> + <id>CLASS</id> + </attribute> + <attribute> + <id>MRU_ID</id> + </attribute> + <attribute> + <id>PRD_HWP_PLID</id> + </attribute> + <attribute> + <default> + <field> + <id>reserved</id> + <value>0</value> + </field> + <field> + <id>supportsFsiScom</id> + <value>1</value> + </field> + <field> + <id>supportsInbandScom</id> + <value>0</value> + </field> + <field> + <id>supportsXscom</id> + <value>1</value> + </field> + </default> + <id>PRIMARY_CAPABILITIES</id> + </attribute> + <attribute> + <id>REL_POS</id> + </attribute> + </targetType> + + <targetType> + <id>unit-capp-cumulus</id> + <parent>unit-capp-power9</parent> + <attribute> + <default>CUMULUS</default> + <id>MODEL</id> + </attribute> + </targetType> + + <targetType> + <id>unit-capp-nimbus</id> + <parent>unit-capp-power9</parent> + <attribute> + <default>NIMBUS</default> + <id>MODEL</id> + </attribute> + </targetType> + + <!-- CAPP + Nimbus : 2 per chip + Cumulus: 2 --> + <targetType> + <id>unit-capp-power9</id> + <parent>unit</parent> + <attribute> + <default>FABRIC</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000031</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <default> + <field> + <id>reserved</id> + <value>0</value> + </field> + <field> + <id>supportsFsiScom</id> + <value>0</value> + </field> + <field> + <id>supportsInbandScom</id> + <value>0</value> + </field> + <field> + <id>supportsXscom</id> + <value>0</value> + </field> + </default> + <id>PRIMARY_CAPABILITIES</id> + </attribute> + <attribute> + <default>CAPP</default> + <id>TYPE</id> + </attribute> + </targetType> + + <!-- CORE: Use same CORE target for both Nimbus and Cumulus + A collection of 4 threads --> + <targetType> + <id>unit-core-power9</id> + <parent>unit</parent> + <attribute> + <default>CPU</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000031</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <default>CORE</default> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>unit-dmi-cumulus</id> + <parent>unit-dmi-power9</parent> + <attribute> + <default>CUMULUS</default> + <id>MODEL</id> + </attribute> + </targetType> + + <!-- DMI + Nimbus : None + Cumulus: 2 per MI (total of 8 per chip) --> + <targetType> + <id>unit-dmi-power9</id> + <parent>unit</parent> + <attribute> + <id>CDM_DOMAIN</id> + <default>MEM</default> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000033</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <default>DMI</default> + <id>TYPE</id> + </attribute> + </targetType> + + <!-- EQ chiplet: Use same EQ target for Nimbus and Cumulus 6 EQs on Nimbus Quad: 2 ex's and one ep --> -<targetType> - <id>unit-eq-power9</id> - <parent>unit</parent> - <attribute> - <default>EQ</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>0x00000031</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <id>PARENT_PERVASIVE</id> - </attribute> - <attribute> - <default>CPU</default> - <id>CDM_DOMAIN</id> - </attribute> -</targetType> - -<!-- EX: Use same EX target for both Nimbus and Cumulus + <targetType> + <id>unit-eq-power9</id> + <parent>unit</parent> + <attribute> + <default>CPU</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000031</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <default>EQ</default> + <id>TYPE</id> + </attribute> + </targetType> + + <!-- EX: Use same EX target for both Nimbus and Cumulus 2 EXs per EQ EX (L2/L3, 2x Core) --> -<targetType> - <id>unit-ex-power9</id> - <parent>unit</parent> - <attribute> - <default>EX</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>0x00000031</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <default>CPU</default> - <id>CDM_DOMAIN</id> - </attribute> -</targetType> - -<!-- CORE: Use same CORE target for both Nimbus and Cumulus - A collection of 4 threads --> -<targetType> - <id>unit-core-power9</id> - <parent>unit</parent> - <attribute> - <default>CORE</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>0x00000031</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <id>PARENT_PERVASIVE</id> - </attribute> - <attribute> - <default>CPU</default> - <id>CDM_DOMAIN</id> - </attribute> -</targetType> - -<!-- MCS - Nimbus : 4 MCS under each chip - (MCUnit left has two, MCUnit right has two) - Cumulus: None --> -<targetType> - <id>unit-mcs-power9</id> - <parent>unit</parent> - <attribute> - <default>MCS</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>0x00000033</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <id>EEPROM_VPD_PRIMARY_INFO</id> - </attribute> - <attribute><id>IBSCOM_MCS_BASE_ADDR</id></attribute> - <attribute> - <id>PARENT_PERVASIVE</id> - </attribute> - <attribute> - <id>VPD_REC_NUM</id> - </attribute> - <attribute> - <default>MEM</default> - <id>CDM_DOMAIN</id> - </attribute> - <!--fsp requirement--> - <attribute> - <id>EI_BUS_TX_MSBSWAP</id> - </attribute> -</targetType> - -<targetType> - <id>unit-mcs-nimbus</id> - <parent>unit-mcs-power9</parent> - <attribute> - <default>NIMBUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<!-- MCA + <targetType> + <id>unit-ex-power9</id> + <parent>unit</parent> + <attribute> + <default>CPU</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000031</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <default>EX</default> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>unit-l4-centaur</id> + <parent>unit-l4-power9</parent> + <attribute> + <id>CDM_DOMAIN</id> + <default>MEM</default> + </attribute> + <attribute> + <default>CENTAUR</default> + <id>MODEL</id> + </attribute> + </targetType> + + <targetType> + <id>unit-l4-power9</id> + <parent>unit</parent> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + <default>0x00000033</default> + </attribute> + <attribute> + <default>L4</default> + <id>TYPE</id> + </attribute> + </targetType> + + <!-- Centaur MBA --> + <targetType> + <id>unit-mba-centaur</id> + <parent>unit</parent> + <attribute> + <id>CDM_DOMAIN</id> + <default>MEM</default> + </attribute> + <attribute> + <id>DECONFIG_GARDABLE</id> + <default>1</default> + </attribute> + <attribute> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + <default>0x00000033</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>MBA</default> + </attribute> + </targetType> + + <targetType> + <id>unit-mc-axone</id> + <parent>unit-mc-power9</parent> + <attribute> + <id>MODEL</id> + <default>AXONE</default> + </attribute> + </targetType> + + <targetType> + <id>unit-mc-cumulus</id> + <parent>unit-mc-power9</parent> + <attribute> + <id>MODEL</id> + <default>CUMULUS</default> + </attribute> + </targetType> + + <!-- MC + Nimbus : None + Cumulus: 2 per chip + Axone : 2 per chip --> + <targetType> + <id>unit-mc-power9</id> + <parent>unit</parent> + <attribute> + <id>CDM_DOMAIN</id> + <default>MEM</default> + </attribute> + <attribute> + <id>DECONFIG_GARDABLE</id> + <default>1</default> + </attribute> + <attribute> + <default>0x00000033</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <id>TYPE</id> + <default>MC</default> + </attribute> + </targetType> + + <targetType> + <id>unit-mca-nimbus</id> + <parent>unit-mca-power9</parent> + <attribute> + <default>NIMBUS</default> + <id>MODEL</id> + </attribute> + </targetType> + + <!-- MCA Nimbus : 2 MCAs under each MCS (total of 8 per chip) Cumulus: No MCA Tied 1-1 to a DDR port --> -<targetType> - <id>unit-mca-power9</id> - <parent>unit</parent> - <attribute> - <default>MCA</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>0x00000033</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <id>PARENT_PERVASIVE</id> - </attribute> - <attribute> - <default>MEM</default> - <id>CDM_DOMAIN</id> - </attribute> - <attribute><id>RCD_PARITY_RECONFIG_LOOP_COUNT</id></attribute> -</targetType> - -<targetType> - <id>unit-mca-nimbus</id> - <parent>unit-mca-power9</parent> - <attribute> - <default>NIMBUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<!-- MCBIST + <targetType> + <id>unit-mca-power9</id> + <parent>unit</parent> + <attribute> + <default>MEM</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000033</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <id>RCD_PARITY_RECONFIG_LOOP_COUNT</id> + </attribute> + <attribute> + <default>MCA</default> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>unit-mcbist-nimbus</id> + <parent>unit-mcbist-power9</parent> + <attribute> + <default>NIMBUS</default> + <id>MODEL</id> + </attribute> + </targetType> + + <!-- MCBIST Nimbus : 1 per MCU (total of 2 per chip) Cumulus: None --> -<targetType> - <id>unit-mcbist-power9</id> - <parent>unit</parent> - <attribute> - <default>MCBIST</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>0x00000033</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <id>PARENT_PERVASIVE</id> - </attribute> - <attribute> - <default>MEM</default> - <id>CDM_DOMAIN</id> - </attribute> - <attribute> - <id>MSS_VOLT_VCS_MILLIVOLTS</id> - </attribute> - <attribute> - <id>MSS_VOLT_VDD_MILLIVOLTS</id> - </attribute> - <attribute> - <id>MSS_VOLT_AVDD_MILLIVOLTS</id> - </attribute> - <attribute> - <id>MSS_VOLT_VPP_OFFSET_MILLIVOLTS</id> - </attribute> - <attribute> - <id>MSS_VOLT_VDDR_OFFSET_MILLIVOLTS</id> - </attribute> - <attribute> - <id>MSS_VOLT_VCS_OFFSET_MILLIVOLTS</id> - </attribute> - <attribute> - <id>MSS_VOLT_VDD_OFFSET_MILLIVOLTS</id> - </attribute> - <attribute> - <id>MSS_VOLT_AVDD_OFFSET_MILLIVOLTS</id> - </attribute> - <attribute> - <id>VPP_ID</id> - </attribute> - <attribute> - <id>VDDR_ID</id> - </attribute> - <attribute> - <id>VCS_ID</id> - </attribute> - <attribute> - <id>VDD_ID</id> - </attribute> - <attribute> - <id>AVDD_ID</id> - </attribute> -</targetType> - -<targetType> - <id>unit-mcbist-nimbus</id> - <parent>unit-mcbist-power9</parent> - <attribute> - <default>NIMBUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<!-- MC - Nimbus : None - Cumulus: 2 per chip - Axone : 2 per chip --> -<targetType> - <id>unit-mc-power9</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>MC</default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute> - <default>0x00000033</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute><id>PARENT_PERVASIVE</id></attribute> - <attribute> - <id>CDM_DOMAIN</id> - <default>MEM</default> - </attribute> -</targetType> - -<targetType> - <id>unit-mc-cumulus</id> - <parent>unit-mc-power9</parent> - <attribute> - <id>MODEL</id> - <default>CUMULUS</default> - </attribute> -</targetType> - -<targetType> - <id>unit-mc-axone</id> - <parent>unit-mc-power9</parent> - <attribute> - <id>MODEL</id> - <default>AXONE</default> - </attribute> -</targetType> - -<!-- MI - Nimbus : None - Cumulus: 4 total per chip (2 per MC) - Axone : 4 total per chip (2 per MC)--> -<targetType> - <id>unit-mi-power9</id> - <parent>unit</parent> - <attribute> - <default>MI</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>0x00000033</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <id>PARENT_PERVASIVE</id> - </attribute> - <attribute> - <id>CDM_DOMAIN</id> - <default>MEM</default> - </attribute> -</targetType> - -<targetType> - <id>unit-mi-cumulus</id> - <parent>unit-mi-power9</parent> - <attribute> - <default>CUMULUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<targetType> - <id>unit-mi-axone</id> - <parent>unit-mi-power9</parent> - <attribute> - <default>AXONE</default> - <id>MODEL</id> - </attribute> -</targetType> - -<!-- OMIC - Nimbus : None - Cumulus: None - Axone : 6 total per chip (3 per MC)--> -<targetType> - <id>unit-omic-power9</id> - <parent>unit</parent> - <attribute> - <default>OMIC</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>0x00000033</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <id>PARENT_PERVASIVE</id> - </attribute> - <attribute> - <id>CDM_DOMAIN</id> - <default>MEM</default> - </attribute> -</targetType> - -<targetType> - <id>unit-omic-axone</id> - <parent>unit-omic-power9</parent> - <attribute> - <default>AXONE</default> - <id>MODEL</id> - </attribute> -</targetType> - -<!-- MCC + <targetType> + <id>unit-mcbist-power9</id> + <parent>unit</parent> + <attribute> + <id>AVDD_ID</id> + </attribute> + <attribute> + <default>MEM</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000033</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>MSS_VOLT_AVDD_MILLIVOLTS</id> + </attribute> + <attribute> + <id>MSS_VOLT_AVDD_OFFSET_MILLIVOLTS</id> + </attribute> + <attribute> + <id>MSS_VOLT_VCS_MILLIVOLTS</id> + </attribute> + <attribute> + <id>MSS_VOLT_VCS_OFFSET_MILLIVOLTS</id> + </attribute> + <attribute> + <id>MSS_VOLT_VDDR_OFFSET_MILLIVOLTS</id> + </attribute> + <attribute> + <id>MSS_VOLT_VDD_MILLIVOLTS</id> + </attribute> + <attribute> + <id>MSS_VOLT_VDD_OFFSET_MILLIVOLTS</id> + </attribute> + <attribute> + <id>MSS_VOLT_VPP_OFFSET_MILLIVOLTS</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <default>MCBIST</default> + <id>TYPE</id> + </attribute> + <attribute> + <id>VCS_ID</id> + </attribute> + <attribute> + <id>VDDR_ID</id> + </attribute> + <attribute> + <id>VDD_ID</id> + </attribute> + <attribute> + <id>VPP_ID</id> + </attribute> + </targetType> + + <targetType> + <id>unit-mcc-axone</id> + <parent>unit-mcc-power9</parent> + <attribute> + <default>AXONE</default> + <id>MODEL</id> + </attribute> + </targetType> + + <!-- MCC Nimbus : None Cumulus: None Axone : 8 total per chip (2 per MI) --> -<targetType> - <id>unit-mcc-power9</id> - <parent>unit</parent> - <attribute> - <default>MCC</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>0x00000033</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <id>PARENT_PERVASIVE</id> - </attribute> - <attribute> - <id>CDM_DOMAIN</id> - <default>MEM</default> - </attribute> -</targetType> - -<targetType> - <id>unit-mcc-axone</id> - <parent>unit-mcc-power9</parent> - <attribute> - <default>AXONE</default> - <id>MODEL</id> - </attribute> -</targetType> - -<!-- DMI + <targetType> + <id>unit-mcc-power9</id> + <parent>unit</parent> + <attribute> + <id>CDM_DOMAIN</id> + <default>MEM</default> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000033</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <default>MCC</default> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>unit-mcs-nimbus</id> + <parent>unit-mcs-power9</parent> + <attribute> + <default>NIMBUS</default> + <id>MODEL</id> + </attribute> + </targetType> + + <!-- MCS + Nimbus : 4 MCS under each chip + (MCUnit left has two, MCUnit right has two) + Cumulus: None --> + <targetType> + <id>unit-mcs-power9</id> + <parent>unit</parent> + <attribute> + <default>MEM</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + </attribute> + <!--fsp requirement--> + <attribute> + <id>EI_BUS_TX_MSBSWAP</id> + </attribute> + <attribute> + <default>0x00000033</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>IBSCOM_MCS_BASE_ADDR</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <default>MCS</default> + <id>TYPE</id> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + </attribute> + </targetType> + + <!-- mem_port --> + <targetType> + <id>unit-mem_port</id> + <parent>unit</parent> + <attribute> + <id>CDM_DOMAIN</id> + <default>MEM</default> + </attribute> + <attribute> + <id>DECONFIG_GARDABLE</id> + <default>1</default> + </attribute> + <attribute> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + <default>0x00000033</default> + </attribute> + <attribute> + <id>TYPE</id> + <default>MEM_PORT</default> + </attribute> + </targetType> + + <targetType> + <id>unit-mi-axone</id> + <parent>unit-mi-power9</parent> + <attribute> + <default>AXONE</default> + <id>MODEL</id> + </attribute> + </targetType> + + <targetType> + <id>unit-mi-cumulus</id> + <parent>unit-mi-power9</parent> + <attribute> + <default>CUMULUS</default> + <id>MODEL</id> + </attribute> + </targetType> + + <!-- MI Nimbus : None - Cumulus: 2 per MI (total of 8 per chip) --> -<targetType> - <id>unit-dmi-power9</id> - <parent>unit</parent> - <attribute> - <default>DMI</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>0x00000033</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <id>PARENT_PERVASIVE</id> - </attribute> - <attribute> - <id>CDM_DOMAIN</id> - <default>MEM</default> - </attribute> -</targetType> - -<targetType> - <id>unit-dmi-cumulus</id> - <parent>unit-dmi-power9</parent> - <attribute> - <default>CUMULUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<!-- OMI (Special has two parents) + Cumulus: 4 total per chip (2 per MC) + Axone : 4 total per chip (2 per MC)--> + <targetType> + <id>unit-mi-power9</id> + <parent>unit</parent> + <attribute> + <id>CDM_DOMAIN</id> + <default>MEM</default> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000033</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <default>MI</default> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>unit-npu-cumulus</id> + <parent>unit-npu-power9</parent> + <attribute> + <id>MODEL</id> + <default>CUMULUS</default> + </attribute> + </targetType> + + <targetType> + <id>unit-npu-nimbus</id> + <parent>unit-npu-power9</parent> + <attribute> + <id>MODEL</id> + <default>NIMBUS</default> + </attribute> + </targetType> + + <!-- One NPU per proc --> + <targetType> + <id>unit-npu-power9</id> + <parent>unit</parent> + <attribute> + <id>DECONFIG_GARDABLE</id> + <default>1</default> + </attribute> + <attribute> + <id>HUID</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <id>TYPE</id> + <default>NPU</default> + </attribute> + </targetType> + + <targetType> + <id>unit-nx-power9</id> + <parent>unit</parent> + <attribute> + <default>FABRIC</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000031</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <default> + <field> + <id>reserved</id> + <value>0</value> + </field> + <field> + <id>supportsFsiScom</id> + <value>0</value> + </field> + <field> + <id>supportsInbandScom</id> + <value>0</value> + </field> + <field> + <id>supportsXscom</id> + <value>0</value> + </field> + </default> + <id>PRIMARY_CAPABILITIES</id> + </attribute> + <attribute> + <default>NX</default> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>unit-obus-brick-cumulus</id> + <parent>unit-obus-brick-power9</parent> + <attribute> + <id>MODEL</id> + <default>CUMULUS</default> + </attribute> + </targetType> + + <targetType> + <id>unit-obus-brick-nimbus</id> + <parent>unit-obus-brick-power9</parent> + <attribute> + <id>MODEL</id> + <default>NIMBUS</default> + </attribute> + </targetType> + + <!-- OBUS Brick + Nimbus : 3 per OBUS + Cumulus: 3 per OBUS --> + <targetType> + <id>unit-obus-brick-power9</id> + <parent>unit</parent> + <attribute> + <id>CDM_DOMAIN</id> + <default>FABRIC</default> + </attribute> + <attribute> + <id>DECONFIG_GARDABLE</id> + <default>1</default> + </attribute> + <attribute> + <id>HUID</id> + </attribute> + <attribute> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + <!-- GARD --> + <default>0x00000001</default> + </attribute> + <attribute> + <id>OBUS_BRICK_LANE_MASK</id> + </attribute> + <attribute> + <id>OBUS_SLOT_INDEX</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <id>TYPE</id> + <default>OBUS_BRICK</default> + </attribute> + </targetType> + + <targetType> + <id>unit-obus-cumulus</id> + <parent>unit-obus-power9</parent> + <attribute> + <default>CUMULUS</default> + <id>MODEL</id> + </attribute> + </targetType> + + <targetType> + <id>unit-obus-nimbus</id> + <parent>unit-obus-power9</parent> + <attribute> + <default>NIMBUS</default> + <id>MODEL</id> + </attribute> + </targetType> + + <!-- OBUS + Nimbus : 2 per chip (OB0 and OB3) + Cumulus: 4 per chip (OB0, OB1, OB2, and OB3) --> + <targetType> + <id>unit-obus-power9</id> + <parent>unit</parent> + <attribute> + <default>FABRIC</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000031</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>MFG_WRAP_TEST_ABUS_LINKS_SET</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <id>PEER_PATH</id> + <default>physical:na</default> + </attribute> + <attribute> + <id>PEER_TARGET</id> + </attribute> + <attribute> + <default>OBUS</default> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>unit-obus-smpgroup</id> + <parent>unit</parent> + <attribute> + <id>CDM_DOMAIN</id> + <default>FABRIC</default> + </attribute> + <attribute> + <id>DECONFIG_GARDABLE</id> + <default>1</default> + </attribute> + <attribute> + <id>HUID</id> + </attribute> + <attribute> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + <default>0x00000001</default> + </attribute> + <attribute> + <id>PEER_PATH</id> + <default>physical:na</default> + </attribute> + <attribute> + <id>PEER_TARGET</id> + </attribute> + <attribute> + <id>TYPE</id> + <default>SMPGROUP</default> + </attribute> + </targetType> + + <targetType> + <id>unit-occ-cumulus</id> + <parent>unit-occ-power9</parent> + <attribute> + <default>CUMULUS</default> + <id>MODEL</id> + </attribute> + </targetType> + + <targetType> + <id>unit-occ-nimbus</id> + <parent>unit-occ-power9</parent> + <attribute> + <default>NIMBUS</default> + <id>MODEL</id> + </attribute> + </targetType> + + <!-- OCC + Nimbus : 1 per chip + Cumulus: 1 --> + <targetType> + <id>unit-occ-power9</id> + <parent>unit</parent> + <attribute> + <default>POWER9</default> + <id>MODEL</id> + </attribute> + <attribute> + <id>OCC_MASTER_CAPABLE</id> + </attribute> + <attribute> + <default>OCC</default> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>unit-omi-axone</id> + <parent>unit-omi-power9</parent> + <attribute> + <default>AXONE</default> + <id>MODEL</id> + </attribute> + </targetType> + + <!-- OMI (Special has two parents) Nimbus : None Cumulus: None Axone: 4 per MI (total of 16 per chip) 3 on OMIC0,1,3,4 2 on OMIC2,5 (still total 16) --> -<targetType> - <id>unit-omi-power9</id> - <parent>unit</parent> - <attribute> - <default>OMI</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>0x00000033</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <id>PARENT_PERVASIVE</id> - </attribute> - <attribute> - <id>CDM_DOMAIN</id> - <default>MEM</default> - </attribute> -</targetType> - -<targetType> - <id>unit-omi-axone</id> - <parent>unit-omi-power9</parent> - <attribute> - <default>AXONE</default> - <id>MODEL</id> - </attribute> -</targetType> - -<!-- PEC corresponds to IOP. Use same PEC target for Nimbus and Cumulus + <targetType> + <id>unit-omi-power9</id> + <parent>unit</parent> + <attribute> + <id>CDM_DOMAIN</id> + <default>MEM</default> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000033</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <default>OMI</default> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>unit-omic-axone</id> + <parent>unit-omic-power9</parent> + <attribute> + <default>AXONE</default> + <id>MODEL</id> + </attribute> + </targetType> + + <!-- OMIC + Nimbus : None + Cumulus: None + Axone : 6 total per chip (3 per MC)--> + <targetType> + <id>unit-omic-power9</id> + <parent>unit</parent> + <attribute> + <id>CDM_DOMAIN</id> + <default>MEM</default> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000033</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <default>OMIC</default> + <id>TYPE</id> + </attribute> + </targetType> + + <!-- PEC corresponds to IOP. Use same PEC target for Nimbus and Cumulus Nimbus : 3 per chip Cumulus: 3 per chip --> -<targetType> - <id>unit-pec-power9</id> - <parent>unit</parent> - <attribute> - <default>PEC</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute><id>PROC_PCIE_PCS_RX_LOFF_CONTROL</id></attribute> - <attribute><id>PROC_PCIE_PCS_RX_PHASE_ROTATOR_CNTL</id></attribute> - <attribute><id>PROC_PCIE_PCS_RX_SIGDET_CNTL</id></attribute> - <attribute><id>PROC_PCIE_PCS_TX_FIFO_CONFIG_OFFSET</id></attribute> - <attribute> - <id>PARENT_PERVASIVE</id> - </attribute> - <attribute> - <id>PROC_PCIE_IOVALID_ENABLE</id> - </attribute> - <attribute> - <id>PROC_PCIE_PCS_SYSTEM_CNTL</id> - </attribute> - <attribute> - <id>PROC_PCIE_REFCLOCK_ENABLE</id> - </attribute> - <attribute> - <id>PROC_PCIE_IOP_CONFIG</id> - </attribute> - <attribute> - <default>IO</default> - <id>CDM_DOMAIN</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>0x00000031</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <id>PROC_PCIE_LANE_MASK</id> - </attribute> - <attribute> - <id>PEC_PCIE_HX_KEYWORD_DATA</id> - </attribute> - <attribute> - <id>PEC_IS_BIFURCATABLE</id> - </attribute> - <attribute> - <id>PEC_PCIE_LANE_MASK_NON_BIFURCATED</id> - </attribute> - <attribute> - <id>PEC_PCIE_LANE_MASK_BIFURCATED</id> - </attribute> - <attribute> - <id>PEC_PCIE_IOP_SWAP_NON_BIFURCATED</id> - </attribute> - <attribute> - <id>PEC_PCIE_IOP_SWAP_BIFURCATED</id> - </attribute> - <attribute> - <id>PEC_PCIE_IOP_REVERSAL</id> - </attribute> - <attribute> - <id>PEC_PCIE_IOP_REVERSAL_NON_BIFURCATED</id> - </attribute> - <attribute> - <id>PEC_PCIE_IOP_REVERSAL_BIFURCATED</id> - </attribute> - <attribute><id>PROC_PCIE_PCS_RX_VGA_CONTRL_REGISTER3</id></attribute> -</targetType> - -<!-- PHB - Nimbus : 6 per PEC (total of 18 per chip) - Cumulus: 6 per PEC --> -<targetType> - <id>unit-phb-power9</id> - <parent>unit</parent> - <attribute> - <default>PHB</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>0x00000031</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <id>PARENT_PERVASIVE</id> - </attribute> - <attribute> - <default>IO</default> - <id>CDM_DOMAIN</id> - </attribute> - <attribute> - <id>PROC_PCIE_LANE_EQUALIZATION_GEN3</id> - </attribute> - <attribute> - <id>PROC_PCIE_LANE_EQUALIZATION_GEN4</id> - </attribute> -</targetType> - -<targetType> - <id>unit-phb-nimbus</id> - <parent>unit-phb-power9</parent> - <attribute> - <default>NIMBUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<targetType> - <id>unit-phb-cumulus</id> - <parent>unit-phb-power9</parent> - <attribute> - <default>CUMULUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<!-- OBUS - Nimbus : 2 per chip (OB0 and OB3) - Cumulus: 4 per chip (OB0, OB1, OB2, and OB3) --> -<targetType> - <id>unit-obus-power9</id> - <parent>unit</parent> - <attribute> - <default>OBUS</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <id>PARENT_PERVASIVE</id> - </attribute> - <attribute> - <id>PEER_TARGET</id> - </attribute> - <attribute> - <id>PEER_PATH</id> - <default>physical:na</default> - </attribute> - <attribute> - <default>FABRIC</default> - <id>CDM_DOMAIN</id> - </attribute> - <attribute> - <default>0x00000031</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <id>MFG_WRAP_TEST_ABUS_LINKS_SET</id> - </attribute> -</targetType> - -<targetType> - <id>unit-obus-nimbus</id> - <parent>unit-obus-power9</parent> - <attribute> - <default>NIMBUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<targetType> - <id>unit-obus-cumulus</id> - <parent>unit-obus-power9</parent> - <attribute> - <default>CUMULUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<!-- OBUS Brick - Nimbus : 3 per OBUS - Cumulus: 3 per OBUS --> -<targetType> - <id>unit-obus-brick-power9</id> + <targetType> + <id>unit-pec-power9</id> <parent>unit</parent> <attribute> - <id>TYPE</id> - <default>OBUS_BRICK</default> + <default>IO</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000031</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <id>PEC_IS_BIFURCATABLE</id> + </attribute> + <attribute> + <id>PEC_PCIE_HX_KEYWORD_DATA</id> + </attribute> + <attribute> + <id>PEC_PCIE_IOP_REVERSAL</id> + </attribute> + <attribute> + <id>PEC_PCIE_IOP_REVERSAL_BIFURCATED</id> + </attribute> + <attribute> + <id>PEC_PCIE_IOP_REVERSAL_NON_BIFURCATED</id> + </attribute> + <attribute> + <id>PEC_PCIE_IOP_SWAP_BIFURCATED</id> + </attribute> + <attribute> + <id>PEC_PCIE_IOP_SWAP_NON_BIFURCATED</id> + </attribute> + <attribute> + <id>PEC_PCIE_LANE_MASK_BIFURCATED</id> + </attribute> + <attribute> + <id>PEC_PCIE_LANE_MASK_NON_BIFURCATED</id> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_CONFIG</id> + </attribute> + <attribute> + <id>PROC_PCIE_IOVALID_ENABLE</id> + </attribute> + <attribute> + <id>PROC_PCIE_LANE_MASK</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_RX_LOFF_CONTROL</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_RX_PHASE_ROTATOR_CNTL</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_RX_SIGDET_CNTL</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_RX_VGA_CONTRL_REGISTER3</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_SYSTEM_CNTL</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_TX_FIFO_CONFIG_OFFSET</id> </attribute> - <attribute><id>CDM_DOMAIN</id><default>FABRIC</default></attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>HUID</id></attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000001</default> <!-- GARD --> + <attribute> + <id>PROC_PCIE_REFCLOCK_ENABLE</id> + </attribute> + <attribute> + <default>PEC</default> + <id>TYPE</id> </attribute> - <attribute><id>OBUS_BRICK_LANE_MASK</id></attribute> - <attribute><id>OBUS_SLOT_INDEX</id></attribute> - <attribute><id>PARENT_PERVASIVE</id></attribute> -</targetType> + </targetType> -<targetType> - <id>unit-obus-brick-nimbus</id> - <parent>unit-obus-brick-power9</parent> + <targetType> + <id>unit-perv-cumulus</id> + <parent>unit-perv-power9</parent> <attribute> - <id>MODEL</id> - <default>NIMBUS</default> + <default>CUMULUS</default> + <id>MODEL</id> </attribute> -</targetType> + </targetType> -<targetType> - <id>unit-obus-brick-cumulus</id> - <parent>unit-obus-brick-power9</parent> + <targetType> + <id>unit-perv-nimbus</id> + <parent>unit-perv-power9</parent> <attribute> - <id>MODEL</id> - <default>CUMULUS</default> + <default>NIMBUS</default> + <id>MODEL</id> </attribute> -</targetType> + </targetType> -<targetType> - <id>unit-obus-smpgroup</id> + <!-- PERV + Nimbus : 43 (1 per chiplet) + Cumulus: 1 per chiplet --> + <targetType> + <id>unit-perv-power9</id> <parent>unit</parent> <attribute> - <id>TYPE</id> - <default>SMPGROUP</default> + <default>0</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>5</default> + <id>PG</id> </attribute> - <attribute><id>CDM_DOMAIN</id><default>FABRIC</default></attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>HUID</id></attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000001</default> + <attribute> + <default>PERV</default> + <id>TYPE</id> </attribute> + </targetType> + + <targetType> + <id>unit-phb-cumulus</id> + <parent>unit-phb-power9</parent> <attribute> - <id>PEER_TARGET</id> + <default>CUMULUS</default> + <id>MODEL</id> </attribute> + </targetType> + + <targetType> + <id>unit-phb-nimbus</id> + <parent>unit-phb-power9</parent> <attribute> - <id>PEER_PATH</id> - <default>physical:na</default> + <default>NIMBUS</default> + <id>MODEL</id> </attribute> -</targetType> + </targetType> -<!-- One NPU per proc --> -<targetType> - <id>unit-npu-power9</id> + <!-- PHB + Nimbus : 6 per PEC (total of 18 per chip) + Cumulus: 6 per PEC --> + <targetType> + <id>unit-phb-power9</id> <parent>unit</parent> <attribute> - <id>TYPE</id> - <default>NPU</default> + <default>IO</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000031</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <id>PROC_PCIE_LANE_EQUALIZATION_GEN3</id> + </attribute> + <attribute> + <id>PROC_PCIE_LANE_EQUALIZATION_GEN4</id> + </attribute> + <attribute> + <default>PHB</default> + <id>TYPE</id> </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>HUID</id></attribute> - <attribute><id>PARENT_PERVASIVE</id></attribute> -</targetType> + </targetType> -<targetType> - <id>unit-npu-nimbus</id> - <parent>unit-npu-power9</parent> + <targetType> + <id>unit-ppe-cumulus</id> + <parent>unit-ppe-power9</parent> <attribute> - <id>MODEL</id> - <default>NIMBUS</default> + <default>CUMULUS</default> + <id>MODEL</id> </attribute> -</targetType> + </targetType> -<targetType> - <id>unit-npu-cumulus</id> - <parent>unit-npu-power9</parent> + <targetType> + <id>unit-ppe-nimbus</id> + <parent>unit-ppe-power9</parent> <attribute> - <id>MODEL</id> - <default>CUMULUS</default> + <default>NIMBUS</default> + <id>MODEL</id> </attribute> -</targetType> + </targetType> -<!-- PPE + <!-- PPE Nimbus : 21, including the SBE (1 SBE, 1 Powerbus/Fabric PPE, 4 GPEs, 12 CMEs, and 3 IO PPEs. Cumulus: 23 (2 additional IO-PPE instances) --> -<targetType> - <id>unit-ppe-power9</id> - <parent>unit</parent> - <attribute> - <default>PPE</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>0</default> - <id>DECONFIG_GARDABLE</id> - </attribute> -</targetType> - -<targetType> - <id>unit-ppe-nimbus</id> - <parent>unit-ppe-power9</parent> - <attribute> - <default>NIMBUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<targetType> - <id>unit-ppe-cumulus</id> - <parent>unit-ppe-power9</parent> - <attribute> - <default>CUMULUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<!-- PERV - Nimbus : 43 (1 per chiplet) - Cumulus: 1 per chiplet --> -<targetType> - <id>unit-perv-power9</id> - <parent>unit</parent> - <attribute> - <default>PERV</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>0</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>5</default> - <id>PG</id> - </attribute> -</targetType> - -<targetType> - <id>unit-perv-nimbus</id> - <parent>unit-perv-power9</parent> - <attribute> - <default>NIMBUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<targetType> - <id>unit-perv-cumulus</id> - <parent>unit-perv-power9</parent> - <attribute> - <default>CUMULUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<!-- XBUS - Nimbus : 1 per chip - Cumulus: 7 --> -<targetType> - <id>unit-xbus-power9</id> - <parent>unit</parent> - <attribute> - <default>XBUS</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>0x00000031</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <id>PEER_TARGET</id> - </attribute> - <attribute> - <id>PEER_PATH</id> - <default>physical:na</default> - </attribute> - <attribute> - <default>FABRIC</default> - <id>CDM_DOMAIN</id> - </attribute> - <attribute> - <id>PARENT_PERVASIVE</id> - </attribute> -</targetType> - -<targetType> - <id>unit-xbus-nimbus</id> - <parent>unit-xbus-power9</parent> - <attribute> - <default>NIMBUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<targetType> - <id>unit-xbus-cumulus</id> - <parent>unit-xbus-power9</parent> - <attribute> - <default>CUMULUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<!-- CAPP - Nimbus : 2 per chip - Cumulus: 2 --> -<targetType> - <id>unit-capp-power9</id> - <parent>unit</parent> - <attribute> - <default>CAPP</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>0x00000031</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <default> - <field> - <id>supportsFsiScom</id> - <value>0</value> - </field> - <field> - <id>supportsXscom</id> - <value>0</value> - </field> - <field> - <id>supportsInbandScom</id> - <value>0</value> - </field> - <field> - <id>reserved</id> - <value>0</value> - </field> - </default> - <id>PRIMARY_CAPABILITIES</id> - </attribute> - <attribute> - <id>PARENT_PERVASIVE</id> - </attribute> - <attribute> - <default>FABRIC</default> - <id>CDM_DOMAIN</id> - </attribute> -</targetType> - -<targetType> - <id>unit-capp-nimbus</id> - <parent>unit-capp-power9</parent> - <attribute> - <default>NIMBUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<targetType> - <id>unit-capp-cumulus</id> - <parent>unit-capp-power9</parent> - <attribute> - <default>CUMULUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<!-- SBE + <targetType> + <id>unit-ppe-power9</id> + <parent>unit</parent> + <attribute> + <default>0</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>PPE</default> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>unit-sbe-cumulus</id> + <parent>unit-sbe-power9</parent> + <attribute> + <default>CUMULUS</default> + <id>MODEL</id> + </attribute> + </targetType> + + <targetType> + <id>unit-sbe-nimbus</id> + <parent>unit-sbe-power9</parent> + <attribute> + <default>NIMBUS</default> + <id>MODEL</id> + </attribute> + </targetType> + + <!-- SBE Nimbus : 1 per chip Cumulus: 1 --> -<targetType> - <id>unit-sbe-power9</id> - <parent>unit</parent> - <attribute> - <default>SBE</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>0</default> - <id>DECONFIG_GARDABLE</id> - </attribute> -</targetType> - -<targetType> - <id>unit-sbe-nimbus</id> - <parent>unit-sbe-power9</parent> - <attribute> - <default>NIMBUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<targetType> - <id>unit-sbe-cumulus</id> - <parent>unit-sbe-power9</parent> - <attribute> - <default>CUMULUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<!-- OCC + <targetType> + <id>unit-sbe-power9</id> + <parent>unit</parent> + <attribute> + <default>0</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>SBE</default> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>unit-xbus-cumulus</id> + <parent>unit-xbus-power9</parent> + <attribute> + <default>CUMULUS</default> + <id>MODEL</id> + </attribute> + </targetType> + + <targetType> + <id>unit-xbus-nimbus</id> + <parent>unit-xbus-power9</parent> + <attribute> + <default>NIMBUS</default> + <id>MODEL</id> + </attribute> + </targetType> + + <!-- XBUS Nimbus : 1 per chip - Cumulus: 1 --> -<targetType> - <id>unit-occ-power9</id> - <parent>unit</parent> - <attribute> - <default>OCC</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>POWER9</default> - <id>MODEL</id> - </attribute> - <attribute> - <id>OCC_MASTER_CAPABLE</id> - </attribute> -</targetType> - -<targetType> - <id>unit-occ-nimbus</id> - <parent>unit-occ-power9</parent> - <attribute> - <default>NIMBUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<targetType> - <id>unit-occ-cumulus</id> - <parent>unit-occ-power9</parent> - <attribute> - <default>CUMULUS</default> - <id>MODEL</id> - </attribute> -</targetType> - -<targetType> - <id>unit-l4-power9</id> - <parent>unit</parent> - <attribute> - <default>L4</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000033</default> - </attribute> -</targetType> - -<targetType> - <id>unit-l4-centaur</id> - <parent>unit-l4-power9</parent> - <attribute> - <default>CENTAUR</default> - <id>MODEL</id> - </attribute> - <attribute> - <id>CDM_DOMAIN</id> - <default>MEM</default> - </attribute> -</targetType> - -<!-- Centaur MBA --> -<targetType> - <id>unit-mba-centaur</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>MBA</default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000033</default> - </attribute> - <attribute> - <id>CDM_DOMAIN</id> - <default>MEM</default> - </attribute> -</targetType> - -<targetType> - <id>unit-nx-power9</id> - <parent>unit</parent> - <attribute> - <default>NX</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>1</default> - <id>DECONFIG_GARDABLE</id> - </attribute> - <attribute> - <default>0x00000031</default> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - </attribute> - <attribute> - <default> - <field> - <id>supportsFsiScom</id> - <value>0</value> - </field> - <field> - <id>supportsXscom</id> - <value>0</value> - </field> - <field> - <id>supportsInbandScom</id> - <value>0</value> - </field> - <field> - <id>reserved</id> - <value>0</value> - </field> - </default> - <id>PRIMARY_CAPABILITIES</id> - </attribute> - <attribute> - <default>FABRIC</default> - <id>CDM_DOMAIN</id> - </attribute> -</targetType> - -<targetType> - <id>uart</id> - <parent>unit</parent> - <attribute> - <default>UNIT</default> - <id>CLASS</id> - </attribute> - <attribute> - <default>UART</default> - <id>TYPE</id> - </attribute> -</targetType> - -<targetType> - <id>sp</id> - <parent>base</parent> - <attribute> - <default>SP</default> - <id>CLASS</id> - </attribute> - <attribute> - <default>SP</default> - <id>TYPE</id> - </attribute> -</targetType> - -<targetType> - <id>chip-bmc-ast2500</id> - <parent>sp</parent> - <attribute> - <default>BMC</default> - <id>TYPE</id> - </attribute> - <attribute> - <default>AST2500</default> - <id>MODEL</id> - </attribute> - <attribute> - <id>AFFINITY_PATH</id> - <default>affinity:sys-0/node-0/bmc-0</default> - </attribute> - <attribute> - <id>PHYS_PATH</id> - <default>physical:sys-0/node-0/bmc-0</default> - </attribute> - <attribute> - <default> - <field> - <id>deconfiguredByEid</id> - <value>0</value> - </field> - <field> - <id>poweredOn</id> - <value>1</value> - </field> - <field> - <id>present</id> - <value>1</value> - </field> - <field> - <id>functional</id> - <value>1</value> - </field> - <field> - <id>dumpfunctional</id> - <value>0</value> - </field> - <field> - <id>specdeconfig</id> - <value>0</value> - </field> - </default> - <id>HWAS_STATE</id> - </attribute> -</targetType> - -<targetType> - <id>power-supply</id> - <parent>unit</parent> - <attribute> - <default>UNIT</default> - <id>CLASS</id> - </attribute> - <attribute> - <default>PS</default> - <id>TYPE</id> - </attribute> -</targetType> - -<targetType> - <id>fan</id> - <parent>unit</parent> - <attribute> - <default>UNIT</default> - <id>CLASS</id> - </attribute> - <attribute> - <default>FAN</default> - <id>TYPE</id> - </attribute> -</targetType> - -<targetType> - <id>vrm</id> - <parent>unit</parent> - <attribute> - <default>UNIT</default> - <id>CLASS</id> - </attribute> - <attribute> - <default>VRM</default> - <id>TYPE</id> - </attribute> -</targetType> - -<targetType> - <id>usb</id> - <parent>unit</parent> - <attribute> - <default>UNIT</default> - <id>CLASS</id> - </attribute> - <attribute> - <default>USB</default> - <id>TYPE</id> - </attribute> -</targetType> - -<targetType> - <id>eth</id> - <parent>unit</parent> - <attribute> - <default>UNIT</default> - <id>CLASS</id> - </attribute> - <attribute> - <default>ETH</default> - <id>TYPE</id> - </attribute> -</targetType> - -<targetType> - <id>panel</id> - <parent>unit</parent> - <attribute> - <default>PANEL</default> - <id>TYPE</id> - </attribute> -</targetType> + Cumulus: 7 --> + <targetType> + <id>unit-xbus-power9</id> + <parent>unit</parent> + <attribute> + <default>FABRIC</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000031</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <id>PEER_PATH</id> + <default>physical:na</default> + </attribute> + <attribute> + <id>PEER_TARGET</id> + </attribute> + <attribute> + <default>XBUS</default> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>usb</id> + <parent>unit</parent> + <attribute> + <default>UNIT</default> + <id>CLASS</id> + </attribute> + <attribute> + <default>USB</default> + <id>TYPE</id> + </attribute> + </targetType> + + <targetType> + <id>vrm</id> + <parent>unit</parent> + <attribute> + <default>UNIT</default> + <id>CLASS</id> + </attribute> + <attribute> + <default>VRM</default> + <id>TYPE</id> + </attribute> + </targetType> </attributes> diff --git a/src/usr/targeting/common/xmltohb/target_types_cfm.xml b/src/usr/targeting/common/xmltohb/target_types_cfm.xml index 21ceec16c..f910fd102 100644 --- a/src/usr/targeting/common/xmltohb/target_types_cfm.xml +++ b/src/usr/targeting/common/xmltohb/target_types_cfm.xml @@ -22,29 +22,42 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> - -<attributes> - <!-- ===================================================================== CONCURRENT FIRMWARE UPDATE TARGETS Contains the definition of CFM target type extensions to add CFM attributes to common target types ================================================================= --> +<attributes> + <targetTypeExtension> + <id>chip-processor</id> + <attribute> + <id>CFM_TEST_NV_RO</id> + </attribute> + <attribute> + <id>CFM_TEST_NV_WR</id> + </attribute> + <attribute> + <id>CFM_TEST_VZ</id> + </attribute> + <attribute> + <id>CFM_TEST_V_WR</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> + <targetTypeExtension> <id>sys-sys-power9</id> - <attribute><id>CFM_TEST_VZ</id></attribute> - <attribute><id>CFM_TEST_V_WR</id></attribute> - <attribute><id>CFM_TEST_NV_RO</id></attribute> - <attribute><id>CFM_TEST_NV_WR</id></attribute> -</targetTypeExtension> - -<targetTypeExtension> - <id>chip-processor</id> - <attribute><id>CFM_TEST_VZ</id></attribute> - <attribute><id>CFM_TEST_V_WR</id></attribute> - <attribute><id>CFM_TEST_NV_RO</id></attribute> - <attribute><id>CFM_TEST_NV_WR</id></attribute> -</targetTypeExtension> + <attribute> + <id>CFM_TEST_NV_RO</id> + </attribute> + <attribute> + <id>CFM_TEST_NV_WR</id> + </attribute> + <attribute> + <id>CFM_TEST_VZ</id> + </attribute> + <attribute> + <id>CFM_TEST_V_WR</id> + </attribute> + </targetTypeExtension> </attributes> diff --git a/src/usr/targeting/common/xmltohb/target_types_hb.xml b/src/usr/targeting/common/xmltohb/target_types_hb.xml index be69df9bc..3e5991649 100644 --- a/src/usr/targeting/common/xmltohb/target_types_hb.xml +++ b/src/usr/targeting/common/xmltohb/target_types_hb.xml @@ -23,242 +23,323 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> - -<attributes> - <!-- ===================================================================== HOST BOOT TARGETS Contains the definition of the different types of Hostboot targets and target type extensions to add attributes to common target types ================================================================= --> -<targetTypeExtension> - <id>sys-sys-power9</id> - <attribute><id>IS_MPIPL_HB</id></attribute> - <attribute><id>MPIPL_HB_MDRT_COUNT</id></attribute> - <attribute><id>IBSCOM_ENABLE_OVERRIDE</id></attribute> - <attribute><id>HB_MUTEX_TEST_LOCK</id></attribute> - <attribute><id>HB_EXISTING_IMAGE</id></attribute> - <attribute><id>CLEAR_DIMM_SPD_ENABLE</id></attribute> - <attribute><id>OCC_COMMON_AREA_PHYS_ADDR</id> </attribute> - <attribute><id>ATTN_CHK_ALL_PROCS</id> </attribute> - <attribute><id>MASTER_MBOX_SCRATCH</id> </attribute> - <attribute><id>IS_DRTM_MPIPL_HB</id></attribute> - <attribute><id>DRTM_PAYLOAD_ADDR_MB_HB</id></attribute> - <attribute><id>FORCE_PRE_PAYLOAD_DRTM</id></attribute> - <attribute><id>HB_RSV_MEM_NEXT_SECTION</id></attribute> - <attribute><id>ALLOW_ATTR_OVERRIDES_IN_SECURE_MODE</id></attribute> - <attribute><id>HIDDEN_ERRLOGS_ENABLE</id></attribute> - <attribute><id>CHKSTOP_ANALYSIS_ON_STARTUP</id></attribute> - <attribute><id>IPC_NODE_BUFFER_GLOBAL_ADDRESS</id></attribute> -</targetTypeExtension> - -<targetTypeExtension> - <id>enc-node-power9</id> - <attribute><id>PART_NUMBER</id></attribute> - <attribute><id>SERIAL_NUMBER</id></attribute> - <attribute><id>VPD_SWITCHES</id></attribute> - <attribute><id>IS_SLAVE_DRAWER</id></attribute> -</targetTypeExtension> +<attributes> + <!-- Centaur chip/DMI --> + <targetTypeExtension> + <id>chip-membuf-centaur</id> + <attribute> + <id>CENTAUR_REGISTER_CACHE_PTR</id> + </attribute> + <attribute> + <id>EEPROM_PAGE_ARRAY</id> + <default>2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2</default> + </attribute> + <attribute> + <id>FSI_SCOM_MUTEX</id> + </attribute> + <attribute> + <id>HBRT_HYP_ID</id> + </attribute> + <attribute> + <id>I2C_ENGINE_MUTEX_0</id> + <default>0</default> + </attribute> + <attribute> + <id>I2C_ENGINE_MUTEX_1</id> + <default>0</default> + </attribute> + <attribute> + <id>I2C_PAGE_MUTEX_0</id> + <default>0</default> + </attribute> + <attribute> + <id>I2C_PAGE_MUTEX_1</id> + <default>0</default> + </attribute> + <attribute> + <id>IBSCOM_MUTEX</id> + </attribute> + <attribute> + <id>IBSCOM_VIRTUAL_ADDR</id> + </attribute> + <attribute> + <id>PART_NUMBER</id> + </attribute> + <attribute> + <id>SCAN_MUTEX</id> + </attribute> + <attribute> + <id>SCOM_IND_MUTEX</id> + </attribute> + <attribute> + <id>SERIAL_NUMBER</id> + </attribute> + <attribute> + <id>VPD_SWITCHES</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> + <targetTypeExtension> <id>chip-processor</id> <attribute> - <id>FSI_MASTER_MUTEX</id> + <id>FSI_MASTER_MUTEX</id> + </attribute> + <attribute> + <id>FSI_SCOM_MUTEX</id> </attribute> <attribute> - <id>FSI_SCOM_MUTEX</id> + <id>HBRT_HYP_ID</id> </attribute> <attribute> - <id>SCOM_IND_MUTEX</id> + <id>HB_INITIATED_PM_RESET</id> </attribute> - <attribute><id>SCAN_MUTEX</id></attribute> <attribute> - <id>HOMER_PHYS_ADDR</id> + <id>HB_SBE_SEEPROM_VERSION_MISMATCH</id> </attribute> <attribute> - <id>HOMER_VIRT_ADDR</id> + <id>HOMER_HCODE_LOADED</id> </attribute> <attribute> - <id>HOMER_HCODE_LOADED</id> + <id>HOMER_PHYS_ADDR</id> </attribute> <attribute> - <id>SBE_FFDC_ADDR</id> + <id>HOMER_VIRT_ADDR</id> </attribute> <attribute> - <id>SBE_COMM_ADDR</id> + <id>PART_NUMBER</id> </attribute> <attribute> - <id>VPD_SWITCHES</id> + <id>SBE_COMM_ADDR</id> </attribute> <attribute> - <id>SERIAL_NUMBER</id> + <id>SBE_FFDC_ADDR</id> </attribute> <attribute> - <id>PART_NUMBER</id> + <id>SCAN_MUTEX</id> </attribute> <attribute> - <id>HBRT_HYP_ID</id> + <id>SCOM_IND_MUTEX</id> </attribute> <attribute> - <id>HB_SBE_SEEPROM_VERSION_MISMATCH</id> + <id>SERIAL_NUMBER</id> </attribute> <attribute> - <id>HB_INITIATED_PM_RESET</id> + <id>VPD_SWITCHES</id> </attribute> -</targetTypeExtension> + </targetTypeExtension> -<targetTypeExtension> + <targetTypeExtension> <id>chip-processor-power9</id> <attribute> - <id>I2C_ENGINE_MUTEX_0</id> - <default>0</default> + <id>EEPROM_PAGE_ARRAY</id> + <default>2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2</default> + </attribute> + <attribute> + <id>HB_NODE_COMM_ABUS_MUTEX</id> + </attribute> + <attribute> + <id>HB_NODE_COMM_XBUS_MUTEX</id> + </attribute> + <attribute> + <id>HB_TARGET_SCOMABLE</id> </attribute> <attribute> - <id>I2C_ENGINE_MUTEX_1</id> - <default>0</default> + <id>I2C_ENGINE_MUTEX_0</id> + <default>0</default> </attribute> <attribute> - <id>I2C_ENGINE_MUTEX_2</id> - <default>0</default> + <id>I2C_ENGINE_MUTEX_1</id> + <default>0</default> </attribute> <attribute> - <id>I2C_ENGINE_MUTEX_3</id> - <default>0</default> + <id>I2C_ENGINE_MUTEX_2</id> + <default>0</default> </attribute> <attribute> - <id>I2C_PAGE_MUTEX_0</id> - <default>0</default> + <id>I2C_ENGINE_MUTEX_3</id> + <default>0</default> </attribute> <attribute> - <id>I2C_PAGE_MUTEX_1</id> - <default>0</default> + <id>I2C_PAGE_MUTEX_0</id> + <default>0</default> </attribute> <attribute> - <id>I2C_PAGE_MUTEX_2</id> - <default>0</default> + <id>I2C_PAGE_MUTEX_1</id> + <default>0</default> </attribute> <attribute> - <id>I2C_PAGE_MUTEX_3</id> - <default>0</default> + <id>I2C_PAGE_MUTEX_2</id> + <default>0</default> </attribute> <attribute> - <id>EEPROM_PAGE_ARRAY</id> - <default>2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2</default> + <id>I2C_PAGE_MUTEX_3</id> + <default>0</default> </attribute> <attribute> - <id>XSCOM_VIRTUAL_ADDR</id> + <id>XSCOM_VIRTUAL_ADDR</id> </attribute> - <attribute><id>HB_TARGET_SCOMABLE</id></attribute> - <attribute><id>HB_NODE_COMM_XBUS_MUTEX</id></attribute> - <attribute><id>HB_NODE_COMM_ABUS_MUTEX</id></attribute> -</targetTypeExtension> + </targetTypeExtension> -<!-- Centaur chip/DMI --> + <targetTypeExtension> + <id>chip-tpm-cectpm</id> + <attribute> + <id>HB_TPM_INIT_ATTEMPTED</id> + </attribute> + <attribute> + <id>HB_TPM_LOG_MGR_PTR</id> + </attribute> + <attribute> + <id>HB_TPM_MUTEX</id> + </attribute> + <attribute> + <id>TPM_ROLE</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> - <id>chip-membuf-centaur</id> + <targetTypeExtension> + <id>enc-node-power9</id> <attribute> - <id>FSI_SCOM_MUTEX</id> + <id>IS_SLAVE_DRAWER</id> </attribute> <attribute> - <id>SCOM_IND_MUTEX</id> + <id>PART_NUMBER</id> </attribute> - <attribute><id>SCAN_MUTEX</id></attribute> <attribute> - <id>IBSCOM_VIRTUAL_ADDR</id> + <id>SERIAL_NUMBER</id> </attribute> <attribute> - <id>IBSCOM_MUTEX</id> + <id>VPD_SWITCHES</id> + </attribute> + </targetTypeExtension> + + <targetTypeExtension> + <id>lcard-dimm</id> + <attribute> + <id>PART_NUMBER</id> + </attribute> + <attribute> + <id>SERIAL_NUMBER</id> + </attribute> + <attribute> + <id>VPD_SWITCHES</id> + </attribute> + </targetTypeExtension> + + <targetTypeExtension> + <id>sys-sys-power9</id> + <attribute> + <id>ALLOW_ATTR_OVERRIDES_IN_SECURE_MODE</id> + </attribute> + <attribute> + <id>ATTN_CHK_ALL_PROCS</id> + </attribute> + <attribute> + <id>CHKSTOP_ANALYSIS_ON_STARTUP</id> + </attribute> + <attribute> + <id>CLEAR_DIMM_SPD_ENABLE</id> + </attribute> + <attribute> + <id>DRTM_PAYLOAD_ADDR_MB_HB</id> + </attribute> + <attribute> + <id>FORCE_PRE_PAYLOAD_DRTM</id> + </attribute> + <attribute> + <id>HB_EXISTING_IMAGE</id> + </attribute> + <attribute> + <id>HB_MUTEX_TEST_LOCK</id> + </attribute> + <attribute> + <id>HB_RSV_MEM_NEXT_SECTION</id> </attribute> <attribute> - <id>EEPROM_PAGE_ARRAY</id> - <default>2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2</default> + <id>HIDDEN_ERRLOGS_ENABLE</id> </attribute> <attribute> - <id>I2C_ENGINE_MUTEX_0</id> - <default>0</default> + <id>IBSCOM_ENABLE_OVERRIDE</id> </attribute> <attribute> - <id>I2C_ENGINE_MUTEX_1</id> - <default>0</default> + <id>IPC_NODE_BUFFER_GLOBAL_ADDRESS</id> </attribute> <attribute> - <id>I2C_PAGE_MUTEX_0</id> - <default>0</default> + <id>IS_DRTM_MPIPL_HB</id> </attribute> <attribute> - <id>I2C_PAGE_MUTEX_1</id> - <default>0</default> + <id>IS_MPIPL_HB</id> </attribute> - <attribute><id>VPD_SWITCHES</id></attribute> - <attribute><id>PART_NUMBER</id></attribute> - <attribute><id>SERIAL_NUMBER</id></attribute> <attribute> - <id>HBRT_HYP_ID</id> + <id>MASTER_MBOX_SCRATCH</id> </attribute> - <attribute><id>CENTAUR_REGISTER_CACHE_PTR</id></attribute> -</targetTypeExtension> + <attribute> + <id>MPIPL_HB_MDRT_COUNT</id> + </attribute> + <attribute> + <id>OCC_COMMON_AREA_PHYS_ADDR</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> + <targetTypeExtension> <id>unit-core-power9</id> - <attribute><id>HB_TARGET_SCOMABLE</id></attribute> <attribute> - <id>HBRT_HYP_ID</id> + <id>HBRT_HYP_ID</id> + </attribute> + <attribute> + <id>HB_TARGET_SCOMABLE</id> </attribute> - <attribute><id>SPCWKUP_COUNT</id></attribute> -</targetTypeExtension> - -<targetTypeExtension> - <id>unit-ex-power9</id> - <attribute><id>HB_TARGET_SCOMABLE</id></attribute> <attribute> - <id>HBRT_HYP_ID</id> + <id>SPCWKUP_COUNT</id> </attribute> - <attribute><id>SPCWKUP_COUNT</id></attribute> -</targetTypeExtension> + </targetTypeExtension> -<targetTypeExtension> + <targetTypeExtension> <id>unit-eq-power9</id> - <attribute><id>SPCWKUP_COUNT</id></attribute> -</targetTypeExtension> - -<targetTypeExtension> - <id>lcard-dimm</id> - <attribute><id>VPD_SWITCHES</id></attribute> - <attribute><id>PART_NUMBER</id></attribute> - <attribute><id>SERIAL_NUMBER</id></attribute> -</targetTypeExtension> + <attribute> + <id>SPCWKUP_COUNT</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> - <id>unit-mcs-power9</id> - <attribute><id>MEMD_OFFSET</id></attribute> -</targetTypeExtension> + <targetTypeExtension> + <id>unit-ex-power9</id> + <attribute> + <id>HBRT_HYP_ID</id> + </attribute> + <attribute> + <id>HB_TARGET_SCOMABLE</id> + </attribute> + <attribute> + <id>SPCWKUP_COUNT</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> + <targetTypeExtension> <id>unit-mcs-nimbus</id> - <attribute><id>HB_TARGET_SCOMABLE</id></attribute> - <attribute><id>VPD_SWITCHES</id></attribute> -</targetTypeExtension> - -<targetTypeExtension> - <id>unit-xbus-nimbus</id> - <attribute><id>HB_TARGET_SCOMABLE</id></attribute> -</targetTypeExtension> - -<targetTypeExtension> - <id>chip-tpm-cectpm</id> <attribute> - <id>HB_TPM_LOG_MGR_PTR</id> + <id>HB_TARGET_SCOMABLE</id> </attribute> <attribute> - <id>HB_TPM_MUTEX</id> + <id>VPD_SWITCHES</id> </attribute> + </targetTypeExtension> + + <targetTypeExtension> + <id>unit-mcs-power9</id> <attribute> - <id>TPM_ROLE</id> + <id>MEMD_OFFSET</id> </attribute> + </targetTypeExtension> + + <targetTypeExtension> + <id>unit-xbus-nimbus</id> <attribute> - <id>HB_TPM_INIT_ATTEMPTED</id> + <id>HB_TARGET_SCOMABLE</id> </attribute> -</targetTypeExtension> + </targetTypeExtension> </attributes> diff --git a/src/usr/targeting/common/xmltohb/target_types_openpower.xml b/src/usr/targeting/common/xmltohb/target_types_openpower.xml index dd1a4ffd3..4f6bcbdfe 100644 --- a/src/usr/targeting/common/xmltohb/target_types_openpower.xml +++ b/src/usr/targeting/common/xmltohb/target_types_openpower.xml @@ -22,8 +22,6 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<attributes> - <!-- ===================================================================== Contains the target definition of attributes that are only available on openpower systems. This file is only compiled when @@ -31,153 +29,327 @@ FSP based systems. ===================================================================== --> -<targetTypeExtension> - <id>chip-processor</id> - <attribute><id>HDAT_I2C_ENGINE</id></attribute> - <attribute><id>HDAT_I2C_MASTER_PORT</id></attribute> - <attribute><id>HDAT_I2C_DEVICE_TYPE</id></attribute> - <attribute><id>HDAT_I2C_ADDR</id></attribute> - <attribute><id>HDAT_I2C_SLAVE_PORT</id></attribute> - <attribute><id>HDAT_I2C_BUS_FREQ</id></attribute> - <attribute><id>HDAT_I2C_DEVICE_PURPOSE</id></attribute> - <attribute><id>HDAT_I2C_DEVICE_LABEL</id></attribute> - <attribute><id>HDAT_I2C_ELEMENTS</id></attribute> - <attribute> - <id>IPMI_INSTANCE</id> - <default>0xFF</default> - </attribute> - <attribute><id>GPU_SENSORS</id></attribute> -</targetTypeExtension> +<attributes> + <targetTypeExtension> + <id>chip-bmc-ast2500</id> + <attribute> + <id>BMC_HW_CHIP_TYPE</id> + </attribute> + <attribute> + <id>BMC_MANUFACTURER</id> + </attribute> + <attribute> + <id>BMC_SW_TYPE</id> + </attribute> + <attribute> + <id>FRU_ID</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> - <id>sys-sys-power9</id> - <attribute><id>OCC_CONTROL_DATA</id></attribute> - <attribute><id>HTMGT_INTERNAL_FLAGS</id></attribute> - <attribute><id>HTMGT_SAFEMODE</id></attribute> - <attribute><id>ADC_CHANNEL_FUNC_IDS</id></attribute> - <attribute><id>ADC_CHANNEL_SENSOR_NUMBERS</id></attribute> - <attribute><id>ADC_CHANNEL_GNDS</id></attribute> - <attribute><id>ADC_CHANNEL_GAINS</id></attribute> - <attribute><id>ADC_CHANNEL_OFFSETS</id></attribute> - <attribute><id>APSS_GPIO_PORT_MODES</id></attribute> - <attribute><id>APSS_GPIO_PORT_PINS</id></attribute> - <attribute><id>IPMI_SENSORS</id></attribute> - <attribute><id>IPMI_MAX_BUFFER_SIZE</id></attribute> - <attribute><id>BMC_MAX_ERROR_LOG_SIZE</id></attribute> - <attribute><id>OP_TRACE_LITE</id></attribute> - <attribute><id>OPEN_POWER_DIMM_THROTTLE_TEMP_DEG_C</id></attribute> - <attribute><id>OPEN_POWER_DIMM_ERROR_TEMP_DEG_C</id></attribute> - <attribute><id>OPEN_POWER_MEMCTRL_THROTTLE_TEMP_DEG_C</id></attribute> - <attribute><id>OPEN_POWER_PROC_WEIGHT</id></attribute> - <attribute><id>OPEN_POWER_QUAD_WEIGHT</id></attribute> - <attribute><id>OPEN_POWER_PROC_DVFS_TEMP_DEG_C</id></attribute> - <attribute><id>OPEN_POWER_MEMCTRL_ERROR_TEMP_DEG_C</id></attribute> - <attribute><id>OPEN_POWER_N_BULK_POWER_LIMIT_WATTS</id></attribute> - <attribute><id>OPEN_POWER_N_MAX_MEM_POWER_WATTS</id></attribute> - <attribute><id>MISC_SYSTEM_COMPONENTS_MAX_POWER_WATTS</id></attribute> - <attribute><id>OPEN_POWER_MEMCTRL_READ_TIMEOUT_SEC</id></attribute> - <attribute><id>OPEN_POWER_DIMM_READ_TIMEOUT_SEC</id></attribute> - <attribute><id>OPEN_POWER_PROC_ERROR_TEMP_DEG_C</id></attribute> - <attribute><id>OPEN_POWER_MIN_MEM_UTILIZATION_THROTTLING</id></attribute> - <attribute><id>OPEN_POWER_MIN_MEM_UTILIZATION_POWER_CAP</id></attribute> - <attribute><id>OPEN_POWER_VRM_READ_TIMEOUT_SEC</id></attribute> - <attribute><id>OPEN_POWER_VRM_VDD_DVFS_TEMP_DEG_C</id></attribute> - <attribute><id>OPEN_POWER_VRM_VDD_ERROR_TEMP_DEG_C</id></attribute> - <attribute><id>OPEN_POWER_VRM_VDD_READ_TIMEOUT_SEC</id></attribute> - <attribute><id>OPEN_POWER_PROC_READ_TIMEOUT_SEC</id></attribute> - <attribute><id>OPEN_POWER_REGULATOR_EFFICIENCY_FACTOR</id></attribute> - <attribute><id>OPEN_POWER_MIN_POWER_CAP_WATTS</id></attribute> - <attribute><id>OPEN_POWER_SOFT_MIN_PCAP_WATTS</id></attribute> - <attribute><id>OPEN_POWER_N_PLUS_ONE_BULK_POWER_LIMIT_WATTS</id></attribute> - <attribute><id>OPEN_POWER_N_PLUS_ONE_MAX_MEM_POWER_WATTS</id></attribute> - <attribute><id>OPEN_POWER_TURBO_MODE_SUPPORTED</id></attribute> - <attribute><id>OPEN_POWER_GPU_READ_TIMEOUT_SEC</id></attribute> - <attribute><id>OPEN_POWER_GPU_ERROR_TEMP_DEG_C</id></attribute> - <attribute><id>OPEN_POWER_GPU_MEM_READ_TIMEOUT_SEC</id></attribute> - <attribute><id>OPEN_POWER_GPU_MEM_ERROR_TEMP_DEG_C</id></attribute> - <attribute><id>OPAL_MODEL</id></attribute> - <attribute><id>IS_MPIPL_SUPPORTED</id></attribute> - <attribute><id>CALCULATED_MAX_SYS_POWER_EXCLUDING_GPUS</id></attribute> - <attribute><id>CALCULATED_PROC_MEMORY_POWER_DROP</id></attribute> - <attribute><id>PROC_SOCKET_POWER_WATTS</id></attribute> - <attribute><id>PROC_MHZ_PER_WATT</id></attribute> - <attribute><id>ALLOW_CALLHOME_ESELS_TO_BMC</id></attribute> - <attribute><id>REPORT_THROTTLE_BELOW_NOMINAL</id></attribute> - <attribute><id>HTMGT_SAVED_POWER_LIMIT</id></attribute> - <attribute><id>VDD_CURRENT_OVERFLOW_WORKAROUND_ENABLE</id></attribute> - <attribute><id>MAX_VDD_CURRENT_READING</id></attribute> -</targetTypeExtension> + <targetTypeExtension> + <id>chip-membuf-centaur</id> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + </attribute> + <attribute> + <id>GPIO_INFO</id> + </attribute> + <attribute> + <id>IPMI_SENSORS</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> - <id>enc-node-power9</id> - <attribute><id>IPMI_SENSORS</id></attribute> -</targetTypeExtension> + <targetTypeExtension> + <id>chip-processor</id> + <attribute> + <id>GPU_SENSORS</id> + </attribute> + <attribute> + <id>HDAT_I2C_ADDR</id> + </attribute> + <attribute> + <id>HDAT_I2C_BUS_FREQ</id> + </attribute> + <attribute> + <id>HDAT_I2C_DEVICE_LABEL</id> + </attribute> + <attribute> + <id>HDAT_I2C_DEVICE_PURPOSE</id> + </attribute> + <attribute> + <id>HDAT_I2C_DEVICE_TYPE</id> + </attribute> + <attribute> + <id>HDAT_I2C_ELEMENTS</id> + </attribute> + <attribute> + <id>HDAT_I2C_ENGINE</id> + </attribute> + <attribute> + <id>HDAT_I2C_MASTER_PORT</id> + </attribute> + <attribute> + <id>HDAT_I2C_SLAVE_PORT</id> + </attribute> + <attribute> + <id>IPMI_INSTANCE</id> + <default>0xFF</default> + </attribute> + </targetTypeExtension> -<targetTypeExtension> + <targetTypeExtension> <id>chip-processor-power9</id> - <attribute><id>IPMI_SENSORS</id></attribute> - <attribute><id>NO_APSS_PROC_POWER_VCS_VIO_WATTS</id></attribute> -</targetTypeExtension> + <attribute> + <id>IPMI_SENSORS</id> + </attribute> + <attribute> + <id>NO_APSS_PROC_POWER_VCS_VIO_WATTS</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> - <id>chip-membuf-centaur</id> - <attribute><id>IPMI_SENSORS</id></attribute> + <targetTypeExtension> + <id>enc-node-power9</id> <attribute> - <id>GPIO_INFO</id> + <id>IPMI_SENSORS</id> </attribute> - <attribute><id>EEPROM_VPD_PRIMARY_INFO</id></attribute> -</targetTypeExtension> + </targetTypeExtension> -<targetTypeExtension> + <targetTypeExtension> <id>lcard-dimm</id> - <attribute><id>IPMI_SENSORS</id></attribute> - <attribute><id>EEPROM_VPD_PRIMARY_INFO</id></attribute> -</targetTypeExtension> - -<targetTypeExtension> - <id>unit-occ-power9</id> - <attribute><id>IPMI_SENSORS</id></attribute> -</targetTypeExtension> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + </attribute> + <attribute> + <id>IPMI_SENSORS</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> + <targetTypeExtension> <id>occ</id> - <attribute><id>IPMI_SENSORS</id></attribute> -</targetTypeExtension> + <attribute> + <id>IPMI_SENSORS</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> - <id>unit-core-power9</id> - <attribute><id>IPMI_SENSORS</id></attribute> + <targetTypeExtension> + <id>occ</id> + <attribute> + <id>PSTATE_TABLE</id> + </attribute> + <attribute> + <id>PSTATE_TABLE_MFG</id> + </attribute> + </targetTypeExtension> -</targetTypeExtension> + <targetTypeExtension> + <id>sys-sys-power9</id> + <attribute> + <id>ADC_CHANNEL_FUNC_IDS</id> + </attribute> + <attribute> + <id>ADC_CHANNEL_GAINS</id> + </attribute> + <attribute> + <id>ADC_CHANNEL_GNDS</id> + </attribute> + <attribute> + <id>ADC_CHANNEL_OFFSETS</id> + </attribute> + <attribute> + <id>ADC_CHANNEL_SENSOR_NUMBERS</id> + </attribute> + <attribute> + <id>ALLOW_CALLHOME_ESELS_TO_BMC</id> + </attribute> + <attribute> + <id>APSS_GPIO_PORT_MODES</id> + </attribute> + <attribute> + <id>APSS_GPIO_PORT_PINS</id> + </attribute> + <attribute> + <id>BMC_MAX_ERROR_LOG_SIZE</id> + </attribute> + <attribute> + <id>CALCULATED_MAX_SYS_POWER_EXCLUDING_GPUS</id> + </attribute> + <attribute> + <id>CALCULATED_PROC_MEMORY_POWER_DROP</id> + </attribute> + <attribute> + <id>HTMGT_INTERNAL_FLAGS</id> + </attribute> + <attribute> + <id>HTMGT_SAFEMODE</id> + </attribute> + <attribute> + <id>HTMGT_SAVED_POWER_LIMIT</id> + </attribute> + <attribute> + <id>IPMI_MAX_BUFFER_SIZE</id> + </attribute> + <attribute> + <id>IPMI_SENSORS</id> + </attribute> + <attribute> + <id>IS_MPIPL_SUPPORTED</id> + </attribute> + <attribute> + <id>MAX_VDD_CURRENT_READING</id> + </attribute> + <attribute> + <id>MISC_SYSTEM_COMPONENTS_MAX_POWER_WATTS</id> + </attribute> + <attribute> + <id>OCC_CONTROL_DATA</id> + </attribute> + <attribute> + <id>OPAL_MODEL</id> + </attribute> + <attribute> + <id>OPEN_POWER_DIMM_ERROR_TEMP_DEG_C</id> + </attribute> + <attribute> + <id>OPEN_POWER_DIMM_READ_TIMEOUT_SEC</id> + </attribute> + <attribute> + <id>OPEN_POWER_DIMM_THROTTLE_TEMP_DEG_C</id> + </attribute> + <attribute> + <id>OPEN_POWER_GPU_ERROR_TEMP_DEG_C</id> + </attribute> + <attribute> + <id>OPEN_POWER_GPU_MEM_ERROR_TEMP_DEG_C</id> + </attribute> + <attribute> + <id>OPEN_POWER_GPU_MEM_READ_TIMEOUT_SEC</id> + </attribute> + <attribute> + <id>OPEN_POWER_GPU_READ_TIMEOUT_SEC</id> + </attribute> + <attribute> + <id>OPEN_POWER_MEMCTRL_ERROR_TEMP_DEG_C</id> + </attribute> + <attribute> + <id>OPEN_POWER_MEMCTRL_READ_TIMEOUT_SEC</id> + </attribute> + <attribute> + <id>OPEN_POWER_MEMCTRL_THROTTLE_TEMP_DEG_C</id> + </attribute> + <attribute> + <id>OPEN_POWER_MIN_MEM_UTILIZATION_POWER_CAP</id> + </attribute> + <attribute> + <id>OPEN_POWER_MIN_MEM_UTILIZATION_THROTTLING</id> + </attribute> + <attribute> + <id>OPEN_POWER_MIN_POWER_CAP_WATTS</id> + </attribute> + <attribute> + <id>OPEN_POWER_N_BULK_POWER_LIMIT_WATTS</id> + </attribute> + <attribute> + <id>OPEN_POWER_N_MAX_MEM_POWER_WATTS</id> + </attribute> + <attribute> + <id>OPEN_POWER_N_PLUS_ONE_BULK_POWER_LIMIT_WATTS</id> + </attribute> + <attribute> + <id>OPEN_POWER_N_PLUS_ONE_MAX_MEM_POWER_WATTS</id> + </attribute> + <attribute> + <id>OPEN_POWER_PROC_DVFS_TEMP_DEG_C</id> + </attribute> + <attribute> + <id>OPEN_POWER_PROC_ERROR_TEMP_DEG_C</id> + </attribute> + <attribute> + <id>OPEN_POWER_PROC_READ_TIMEOUT_SEC</id> + </attribute> + <attribute> + <id>OPEN_POWER_PROC_WEIGHT</id> + </attribute> + <attribute> + <id>OPEN_POWER_QUAD_WEIGHT</id> + </attribute> + <attribute> + <id>OPEN_POWER_REGULATOR_EFFICIENCY_FACTOR</id> + </attribute> + <attribute> + <id>OPEN_POWER_SOFT_MIN_PCAP_WATTS</id> + </attribute> + <attribute> + <id>OPEN_POWER_TURBO_MODE_SUPPORTED</id> + </attribute> + <attribute> + <id>OPEN_POWER_VRM_READ_TIMEOUT_SEC</id> + </attribute> + <attribute> + <id>OPEN_POWER_VRM_VDD_DVFS_TEMP_DEG_C</id> + </attribute> + <attribute> + <id>OPEN_POWER_VRM_VDD_ERROR_TEMP_DEG_C</id> + </attribute> + <attribute> + <id>OPEN_POWER_VRM_VDD_READ_TIMEOUT_SEC</id> + </attribute> + <attribute> + <id>OP_TRACE_LITE</id> + </attribute> + <attribute> + <id>PROC_MHZ_PER_WATT</id> + </attribute> + <attribute> + <id>PROC_SOCKET_POWER_WATTS</id> + </attribute> + <attribute> + <id>REPORT_THROTTLE_BELOW_NOMINAL</id> + </attribute> + <attribute> + <id>VDD_CURRENT_OVERFLOW_WORKAROUND_ENABLE</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> - <id>chip-bmc-ast2500</id> - <attribute><id>BMC_MANUFACTURER</id></attribute> - <attribute><id>BMC_HW_CHIP_TYPE</id></attribute> - <attribute><id>BMC_SW_TYPE</id></attribute> - <attribute><id>FRU_ID</id></attribute> -</targetTypeExtension> + <targetTypeExtension> + <id>unit-core-power9</id> + <attribute> + <id>IPMI_SENSORS</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> - <id>occ</id> + <targetTypeExtension> + <id>unit-mcs-power9</id> + <attribute> + <id>N_PLUS_ONE_MEM_POWER</id> + </attribute> + <attribute> + <id>N_PLUS_ONE_N_PER_CHIP</id> + </attribute> <attribute> - <id>PSTATE_TABLE</id> + <id>N_PLUS_ONE_N_PER_MBA</id> </attribute> <attribute> - <id>PSTATE_TABLE_MFG</id> + <id>OT_MEM_POWER</id> </attribute> -</targetTypeExtension> + <attribute> + <id>OT_MIN_N_PER_MBA</id> + </attribute> + <attribute> + <id>POWERCAP_MEM_POWER</id> + </attribute> + <attribute> + <id>POWERCAP_N_PER_CHIP</id> + </attribute> + <attribute> + <id>POWERCAP_N_PER_MBA</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> - <id>unit-mcs-power9</id> - <attribute><id>OT_MIN_N_PER_MBA</id></attribute> - <attribute><id>OT_MEM_POWER</id></attribute> - <attribute><id>N_PLUS_ONE_N_PER_MBA</id></attribute> - <attribute><id>N_PLUS_ONE_N_PER_CHIP</id></attribute> - <attribute><id>N_PLUS_ONE_MEM_POWER</id></attribute> - <attribute><id>POWERCAP_N_PER_MBA</id></attribute> - <attribute><id>POWERCAP_N_PER_CHIP</id></attribute> - <attribute><id>POWERCAP_MEM_POWER</id></attribute> -</targetTypeExtension> + <targetTypeExtension> + <id>unit-occ-power9</id> + <attribute> + <id>IPMI_SENSORS</id> + </attribute> + </targetTypeExtension> </attributes> diff --git a/src/usr/targeting/common/xmltohb/target_types_oppowervm.xml b/src/usr/targeting/common/xmltohb/target_types_oppowervm.xml index e3072464c..4e987c797 100644 --- a/src/usr/targeting/common/xmltohb/target_types_oppowervm.xml +++ b/src/usr/targeting/common/xmltohb/target_types_oppowervm.xml @@ -22,8 +22,6 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<attributes> - <!-- ===================================================================== Contains the target definition of attributes that are only available on openpower systems for a PowerVM build. This file is only compiled when @@ -31,148 +29,276 @@ FSP based systems. ===================================================================== --> - -<targetTypeExtension> +<attributes> + <targetTypeExtension> <id>base</id> - <attribute><id>ORDINAL_ID</id></attribute> -</targetTypeExtension> + <attribute> + <id>ORDINAL_ID</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> - <id>sys-sys-power9</id> - <attribute><id>SERIAL_NUMBER</id></attribute> - <attribute><id>PHYP_SYSTEM_TYPE</id></attribute> - <attribute><id>ASCII_VPD_LX_KEYWORD</id></attribute> - <attribute><id>IPL_ATTRIBUTES</id></attribute> - <attribute><id>PRESERVE_MDC_PARTITION_VPD</id></attribute> - <attribute><id>HYPERVISOR_IPL_SIDE</id><default>0</default></attribute> - <attribute><id>OS_IPL_MODE</id></attribute> - <attribute><id>LMB_SIZE</id></attribute> - <attribute><id>MAX_HSL_OPTICONNECT_CONNECTIONS</id></attribute> - <attribute><id>HUGE_PAGE_COUNT</id></attribute> - <attribute><id>HUGE_PAGE_SIZE</id></attribute> - <attribute><id>VLAN_SWITCHES</id></attribute> - <attribute><id>VTPM_ENABLED</id></attribute> - <attribute><id>HYP_DISPATCH_WHEEL</id></attribute> - <attribute><id>SYSTEM_BRAND_NAME</id></attribute> - <attribute><id>HYPERVISOR_IPL_DESTINATION</id></attribute> - <attribute><id>SLCA_INDEX</id></attribute> - <attribute><id>SLCA_RID</id></attribute> - <attribute><id>OPEN_POWER_PM_MODE</id></attribute> - <attribute><id>OPEN_POWER_PM_MODE_FREQ_PERCENT</id></attribute> - <attribute><id>IPS_ENABLE</id></attribute> - <attribute><id>IPS_ENTER_TIME_SECONDS</id></attribute> - <attribute><id>IPS_ENTER_UTILIZATION_PERCENT</id></attribute> - <attribute><id>IPS_EXIT_TIME_SECONDS</id></attribute> - <attribute><id>IPS_EXIT_UTILIZATION_PERCENT</id></attribute> -</targetTypeExtension> - -<targetTypeExtension> - <id>chip-processor</id> + <targetTypeExtension> + <id>bmc</id> + <attribute> + <id>CHIP_ID</id> + <default>0</default> + </attribute> <attribute> - <id>PROC_HW_TOPOLOGY</id> - <default>0x00000000</default> + <id>CHIP_VER</id> </attribute> <attribute> - <id>SLCA_INDEX</id> - <default>0x00000000</default> + <id>HW_VER</id> </attribute> <attribute> - <id>SLCA_RID</id> - <default>0x00001000</default> + <id>ROLE</id> </attribute> -</targetTypeExtension> + <attribute> + <id>SLCA_INDEX</id> + </attribute> + <attribute> + <id>SLCA_RID</id> + </attribute> + <attribute> + <id>SW_VER</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> - <id>sp</id> - <attribute><id>CHIP_VER</id></attribute> - <attribute><id>CHIP_ID</id></attribute> - <attribute><id>HW_VER</id></attribute> - <attribute><id>SW_VER</id></attribute> - <attribute><id>ROLE</id></attribute> -</targetTypeExtension> - -<targetTypeExtension> - <id>bmc</id> - <attribute><id>CHIP_VER</id></attribute> - <attribute><id>CHIP_ID</id><default>0</default></attribute> - <attribute><id>SLCA_INDEX</id></attribute> - <attribute><id>SLCA_RID</id></attribute> - <attribute><id>HW_VER</id></attribute> - <attribute><id>SW_VER</id></attribute> - <attribute><id>ROLE</id></attribute> -</targetTypeExtension> - -<targetTypeExtension> - <id>lcard-dimm</id> - <attribute><id>SLCA_INDEX</id></attribute> - <attribute><id>SLCA_RID</id></attribute> -</targetTypeExtension> + <targetTypeExtension> + <id>chip-membuf-centaur</id> + <attribute> + <id>SLCA_INDEX</id> + </attribute> + <attribute> + <id>SLCA_RID</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> - <id>unit-pci-power9</id> - <attribute><id>SLCA_INDEX</id></attribute> - <attribute><id>SLCA_RID</id></attribute> -</targetTypeExtension> + <targetTypeExtension> + <id>chip-processor</id> + <attribute> + <id>PROC_HW_TOPOLOGY</id> + <default>0x00000000</default> + </attribute> + <attribute> + <id>SLCA_INDEX</id> + <default>0x00000000</default> + </attribute> + <attribute> + <id>SLCA_RID</id> + <default>0x00001000</default> + </attribute> + </targetTypeExtension> -<targetTypeExtension> + <targetTypeExtension> <id>enc-node-power9</id> - <attribute><id>ENLARGED_IO_SLOT_COUNT</id></attribute> - <attribute><id>SLCA_INDEX</id></attribute> - <attribute><id>SLCA_RID</id></attribute> -</targetTypeExtension> + <attribute> + <id>ENLARGED_IO_SLOT_COUNT</id> + </attribute> + <attribute> + <id>SLCA_INDEX</id> + </attribute> + <attribute> + <id>SLCA_RID</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> - <id>chip-membuf-centaur</id> - <attribute><id>SLCA_INDEX</id></attribute> - <attribute><id>SLCA_RID</id></attribute> -</targetTypeExtension> + <targetTypeExtension> + <id>eth</id> + <attribute> + <id>SLCA_INDEX</id> + </attribute> + <attribute> + <id>SLCA_RID</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> - <id>uart</id> - <attribute><id>SLCA_INDEX</id></attribute> - <attribute><id>SLCA_RID</id></attribute> -</targetTypeExtension> + <targetTypeExtension> + <id>fan</id> + <attribute> + <id>SLCA_INDEX</id> + </attribute> + <attribute> + <id>SLCA_RID</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> - <id>sp</id> - <attribute><id>SLCA_INDEX</id></attribute> - <attribute><id>SLCA_RID</id></attribute> -</targetTypeExtension> + <targetTypeExtension> + <id>lcard-dimm</id> + <attribute> + <id>SLCA_INDEX</id> + </attribute> + <attribute> + <id>SLCA_RID</id> + </attribute> + </targetTypeExtension> + + <targetTypeExtension> + <id>panel</id> + <attribute> + <id>SLCA_INDEX</id> + </attribute> + <attribute> + <id>SLCA_RID</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> + <targetTypeExtension> <id>power-supply</id> - <attribute><id>SLCA_INDEX</id></attribute> - <attribute><id>SLCA_RID</id></attribute> -</targetTypeExtension> + <attribute> + <id>SLCA_INDEX</id> + </attribute> + <attribute> + <id>SLCA_RID</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> - <id>fan</id> - <attribute><id>SLCA_INDEX</id></attribute> - <attribute><id>SLCA_RID</id></attribute> -</targetTypeExtension> + <targetTypeExtension> + <id>sp</id> + <attribute> + <id>CHIP_ID</id> + </attribute> + <attribute> + <id>CHIP_VER</id> + </attribute> + <attribute> + <id>HW_VER</id> + </attribute> + <attribute> + <id>ROLE</id> + </attribute> + <attribute> + <id>SW_VER</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> - <id>vrm</id> - <attribute><id>SLCA_INDEX</id></attribute> - <attribute><id>SLCA_RID</id></attribute> -</targetTypeExtension> + <targetTypeExtension> + <id>sp</id> + <attribute> + <id>SLCA_INDEX</id> + </attribute> + <attribute> + <id>SLCA_RID</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> - <id>usb</id> - <attribute><id>SLCA_INDEX</id></attribute> - <attribute><id>SLCA_RID</id></attribute> -</targetTypeExtension> + <targetTypeExtension> + <id>sys-sys-power9</id> + <attribute> + <id>ASCII_VPD_LX_KEYWORD</id> + </attribute> + <attribute> + <id>HUGE_PAGE_COUNT</id> + </attribute> + <attribute> + <id>HUGE_PAGE_SIZE</id> + </attribute> + <attribute> + <id>HYPERVISOR_IPL_DESTINATION</id> + </attribute> + <attribute> + <id>HYPERVISOR_IPL_SIDE</id> + <default>0</default> + </attribute> + <attribute> + <id>HYP_DISPATCH_WHEEL</id> + </attribute> + <attribute> + <id>IPL_ATTRIBUTES</id> + </attribute> + <attribute> + <id>IPS_ENABLE</id> + </attribute> + <attribute> + <id>IPS_ENTER_TIME_SECONDS</id> + </attribute> + <attribute> + <id>IPS_ENTER_UTILIZATION_PERCENT</id> + </attribute> + <attribute> + <id>IPS_EXIT_TIME_SECONDS</id> + </attribute> + <attribute> + <id>IPS_EXIT_UTILIZATION_PERCENT</id> + </attribute> + <attribute> + <id>LMB_SIZE</id> + </attribute> + <attribute> + <id>MAX_HSL_OPTICONNECT_CONNECTIONS</id> + </attribute> + <attribute> + <id>OPEN_POWER_PM_MODE</id> + </attribute> + <attribute> + <id>OPEN_POWER_PM_MODE_FREQ_PERCENT</id> + </attribute> + <attribute> + <id>OS_IPL_MODE</id> + </attribute> + <attribute> + <id>PHYP_SYSTEM_TYPE</id> + </attribute> + <attribute> + <id>PRESERVE_MDC_PARTITION_VPD</id> + </attribute> + <attribute> + <id>SERIAL_NUMBER</id> + </attribute> + <attribute> + <id>SLCA_INDEX</id> + </attribute> + <attribute> + <id>SLCA_RID</id> + </attribute> + <attribute> + <id>SYSTEM_BRAND_NAME</id> + </attribute> + <attribute> + <id>VLAN_SWITCHES</id> + </attribute> + <attribute> + <id>VTPM_ENABLED</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> - <id>eth</id> - <attribute><id>SLCA_INDEX</id></attribute> - <attribute><id>SLCA_RID</id></attribute> -</targetTypeExtension> + <targetTypeExtension> + <id>uart</id> + <attribute> + <id>SLCA_INDEX</id> + </attribute> + <attribute> + <id>SLCA_RID</id> + </attribute> + </targetTypeExtension> -<targetTypeExtension> - <id>panel</id> - <attribute><id>SLCA_INDEX</id></attribute> - <attribute><id>SLCA_RID</id></attribute> -</targetTypeExtension> + <targetTypeExtension> + <id>unit-pci-power9</id> + <attribute> + <id>SLCA_INDEX</id> + </attribute> + <attribute> + <id>SLCA_RID</id> + </attribute> + </targetTypeExtension> + + <targetTypeExtension> + <id>usb</id> + <attribute> + <id>SLCA_INDEX</id> + </attribute> + <attribute> + <id>SLCA_RID</id> + </attribute> + </targetTypeExtension> + + <targetTypeExtension> + <id>vrm</id> + <attribute> + <id>SLCA_INDEX</id> + </attribute> + <attribute> + <id>SLCA_RID</id> + </attribute> + </targetTypeExtension> </attributes> |
