diff options
Diffstat (limited to 'src/usr')
13 files changed, 1015 insertions, 883 deletions
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C index 20f174449..ca090dde1 100644 --- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_setup_bars.C,v 1.28 2013/05/23 14:54:28 jmcgill Exp $ +// $Id: mss_setup_bars.C,v 1.32 2013/08/16 17:23:27 gpaulraj Exp $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 // *! All Rights Reserved -- Property of IBM @@ -38,6 +38,10 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.32 | gpaulraj | 08/16/13| fixed code +// 1.31 | gpaulraj | 08/13/13| fix HW259884 Mirror BAR Scom Parity Error +// 1.30 | gpaulraj | 08/13/13| added fix HW259884 Mirror BAR Scom Parity Error +// 1.29 | gpaulraj | 08/12/13| fixed mirror BAR issues // 1.27 | jmcgill | 05/21/13| address FW review issues // 1.26 | jmcgill | 04/22/13| rewrite to line up with attribute changes // 1.23 | bellows | 12/04/12| more updates @@ -235,10 +239,37 @@ fapi::ReturnCode mss_setup_bars_init_m_bars( ecmdDataBufferBase MCFGPM(64); ecmdDataBufferBase MCFGPMA(64); + // Defect HW259884 (AddNote by retter) P8 Lab Brazos: Mirror BAR Scom Parity Error - workaround + ecmdDataBufferBase MCIFIR(64); + ecmdDataBufferBase MCIFIRMASK(64); + ecmdDataBufferBase MCSMODE4(64); do { + + rc = fapiGetScom(i_mcs_target, MCS_MCIFIRMASK_0x02011843, MCIFIRMASK); + if (!rc.ok()) + { + FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiGetScom (MCS_MCIFIRMASK_0x02011843"); + break; + } + // Mask MCIFIR bit 25 + rc_ecmd |= MCIFIRMASK.setBit(25); + if (rc_ecmd) + { + FAPI_ERR("mss_setup_bars_init_m_bars: Error 0x%X setting up MCIFIRMASK data buffer", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + rc = fapiPutScom(i_mcs_target, MCS_MCIFIRMASK_0x02011843, MCIFIRMASK); + if (!rc.ok()) + { + FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiPutScom (MCS_MCIFIRMASK_0x02011843"); + break; + } if (i_pri_valid) { + // MCFGPMQ_VALID rc_ecmd |= MCFGPM.setBit(MCFGPM_VALID_BIT); // MCFGPMQ_GROUP_SIZE @@ -318,6 +349,59 @@ fapi::ReturnCode mss_setup_bars_init_m_bars( FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiPutScom (MCS_MCFGPMA_0x02011815"); break; } + + rc = fapiGetScom(i_mcs_target, MCS_MCSMODE4_0x0201181A, MCSMODE4); + if (!rc.ok()) + { + FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiGetScom (MCS_MCSMODE4_0x0201181A"); + break; + } + // set MCSMODE4 bit 0 + rc_ecmd |= MCSMODE4.setBit(0); + rc = fapiPutScom(i_mcs_target, MCS_MCSMODE4_0x0201181A, MCSMODE4); + if (!rc.ok()) + { + FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiPutScom (MCS_MCSMODE4_0x0201181A"); + break; + } + // Clear MCSMODE4 bit 0 + rc_ecmd |= MCSMODE4.clearBit(0); + rc = fapiPutScom(i_mcs_target, MCS_MCSMODE4_0x0201181A, MCSMODE4); + if (!rc.ok()) + { + FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiPutScom (MCS_MCSMODE4_0x0201181A"); + break; + } + + rc = fapiGetScom(i_mcs_target, MCS_MCIFIR_0x02011840, MCIFIR); + if (!rc.ok()) + { + FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiGetScom (MCS_MCIFIR_0x02011840"); + break; + } + // Reset MCIFIR bit 25 + rc_ecmd |= MCIFIR.clearBit(25); + rc = fapiPutScom(i_mcs_target, MCS_MCIFIR_0x02011840, MCIFIR); + if (!rc.ok()) + { + FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiPutScom (MCS_MCIFIR_0x02011840"); + break; + } + + rc = fapiGetScom(i_mcs_target, MCS_MCIFIRMASK_0x02011843, MCIFIRMASK); + if (!rc.ok()) + { + FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiGetScom (MCS_MCIFIRMASK_0x02011843"); + break; + } + // Unmask MCIFIR bit 25 + rc_ecmd |= MCIFIRMASK.clearBit(25); + rc = fapiPutScom(i_mcs_target, MCS_MCIFIRMASK_0x02011843, MCIFIRMASK); + if (!rc.ok()) + { + FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiPutScom (MCS_MCIFIRMASK_0x02011843"); + break; + } } while(0); return rc; @@ -435,18 +519,18 @@ fapi::ReturnCode mss_setup_bars(const fapi::Target& i_pu_target) i++) { // only process valid groups - if (group_data[i][MSS_MCS_GROUP_32_SIZE_INDEX] == 0) + if (group_data[i-8][MSS_MCS_GROUP_32_SIZE_INDEX] == 0) { continue; } - uint32_t mcs_in_group = group_data[i][MSS_MCS_GROUP_32_MCS_IN_GROUP_INDEX]; + uint32_t mcs_in_group = group_data[i-8][MSS_MCS_GROUP_32_MCS_IN_GROUP_INDEX]; for (size_t j = MSS_MCS_GROUP_32_MEMBERS_START_INDEX; (j < MSS_MCS_GROUP_32_MEMBERS_START_INDEX+mcs_in_group) && (rc.ok()); j++) { - if (mcs_pos == group_data[i][j]) + if (mcs_pos == group_data[i-8][j]) { if (m_bar_valid) { @@ -469,7 +553,6 @@ fapi::ReturnCode mss_setup_bars(const fapi::Target& i_pu_target) { break; } - // write mirrored BARs based on group configuration rc = mss_setup_bars_init_m_bars( *iter, diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C index 4acf12bc6..cd99f25db 100644 --- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_setup_bars.C,v 1.15 2013/06/21 15:13:44 jmcgill Exp $ +// $Id: proc_setup_bars.C,v 1.18 2013/08/28 22:00:50 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars.C,v $ //------------------------------------------------------------------------------ // *| @@ -201,7 +201,8 @@ fapi::ReturnCode proc_setup_bars_memory_get_non_mirrored_attrs( // return code fapi::ReturnCode rc; // temporary attribute storage used to build procedure data structures - uint32_t mss_mcs_group_32[OPT_MEMMAP_GROUP_32_DIM1][OPT_MEMMAP_GROUP_32_DIM2]; + uint64_t mem_bases_ack[PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES]; + uint64_t mem_sizes_ack[PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES]; proc_setup_bars_addr_range non_mirrored_ranges[PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES]; // mark function entry @@ -209,13 +210,22 @@ fapi::ReturnCode proc_setup_bars_memory_get_non_mirrored_attrs( do { - // retrieve non-mirrored memory base address/size attributes - rc = FAPI_ATTR_GET(ATTR_MSS_MCS_GROUP_32, + // retrieve non-mirrored memory base address/size ack attributes + rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASES_ACK, i_target, - mss_mcs_group_32); + mem_bases_ack); if (!rc.ok()) { - FAPI_ERR("proc_setup_bars_memory_get_non_mirrored_attrs: Error querying ATTR_MSS_MCS_GROUP_32"); + FAPI_ERR("proc_setup_bars_memory_get_non_mirrored_attrs: Error querying ATTR_PROC_MEM_BASES_ACK"); + break; + } + + rc = FAPI_ATTR_GET(ATTR_PROC_MEM_SIZES_ACK, + i_target, + mem_sizes_ack); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_memory_get_non_mirrored_attrs: Error querying ATTR_PROC_MEM_SIZES_ACK"); break; } @@ -223,10 +233,8 @@ fapi::ReturnCode proc_setup_bars_memory_get_non_mirrored_attrs( for (uint8_t r = 0; r < PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES; r++) { // build range content - non_mirrored_ranges[r].base_addr = - (mss_mcs_group_32[OPT_MEMMAP_GROUP_32_NM_START_INDEX+r][OPT_MEMMAP_GROUP_32_BASE_INDEX])*OPT_MEMMAP_GB; - non_mirrored_ranges[r].size = - (mss_mcs_group_32[OPT_MEMMAP_GROUP_32_NM_START_INDEX+r][OPT_MEMMAP_GROUP_32_SIZE_INDEX])*OPT_MEMMAP_GB; + non_mirrored_ranges[r].base_addr = mem_bases_ack[r]; + non_mirrored_ranges[r].size = mem_sizes_ack[r]; // consider range enabled if size is non-zero non_mirrored_ranges[r].enabled = (non_mirrored_ranges[r].size != 0x0); // check attribute content @@ -318,7 +326,8 @@ fapi::ReturnCode proc_setup_bars_memory_get_mirrored_attrs( // return code fapi::ReturnCode rc; // temporary attribute storage used to build procedure data structures - uint32_t mss_mcs_group_32[OPT_MEMMAP_GROUP_32_DIM1][OPT_MEMMAP_GROUP_32_DIM2]; + uint64_t mirror_bases_ack[PROC_SETUP_BARS_NUM_MIRRORED_RANGES]; + uint64_t mirror_sizes_ack[PROC_SETUP_BARS_NUM_MIRRORED_RANGES]; proc_setup_bars_addr_range mirrored_ranges[PROC_SETUP_BARS_NUM_MIRRORED_RANGES]; // mark function entry @@ -326,13 +335,22 @@ fapi::ReturnCode proc_setup_bars_memory_get_mirrored_attrs( do { - // retrieve mirrored memory base address/size attributes - rc = FAPI_ATTR_GET(ATTR_MSS_MCS_GROUP_32, + // retrieve mirrored memory base address/size ack attributes + rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASES_ACK, i_target, - mss_mcs_group_32); + mirror_bases_ack); if (!rc.ok()) { - FAPI_ERR("proc_setup_bars_memory_get_mirrored_attrs: Error querying ATTR_MSS_MCS_GROUP_32"); + FAPI_ERR("proc_setup_bars_memory_get_mirrored_attrs: Error querying ATTR_PROC_MIRROR_BASES_ACK"); + break; + } + + rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_SIZES_ACK, + i_target, + mirror_sizes_ack); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_memory_get_mirrored_attrs: Error querying ATTR_PROC_MIRROR_SIZES_ACK"); break; } @@ -340,10 +358,8 @@ fapi::ReturnCode proc_setup_bars_memory_get_mirrored_attrs( for (uint8_t r = 0; r < PROC_SETUP_BARS_NUM_MIRRORED_RANGES; r++) { // build range content - mirrored_ranges[r].base_addr = - (mss_mcs_group_32[OPT_MEMMAP_GROUP_32_M_START_INDEX+r][OPT_MEMMAP_GROUP_32_BASE_INDEX])*OPT_MEMMAP_GB; - mirrored_ranges[r].size = - (mss_mcs_group_32[OPT_MEMMAP_GROUP_32_M_START_INDEX+r][OPT_MEMMAP_GROUP_32_SIZE_INDEX])*OPT_MEMMAP_GB; + mirrored_ranges[r].base_addr = mirror_bases_ack[r]; + mirrored_ranges[r].size = mirror_sizes_ack[r]; // consider range enabled if size is non-zero mirrored_ranges[r].enabled = (mirrored_ranges[r].size != 0x0); // check attribute content @@ -1380,57 +1396,12 @@ fapi::ReturnCode proc_setup_bars_insert_chip( io_smp.nodes[node_id].chips[chip_id] = i_smp_chip; // update node address regions - // before merging, check that non-mirrored & mirrored ranges - // are non-overlapping with new ranges from this chip - FAPI_DBG("proc_setup_bars_insert_chip: Non-mirrored ranges prior to merging:"); - io_smp.nodes[node_id].non_mirrored_range.print(); + io_smp.nodes[node_id].non_mirrored_ranges.push_back(&(io_smp.nodes[node_id].chips[chip_id].non_mirrored_range)); i_smp_chip.non_mirrored_range.print(); - if (io_smp.nodes[node_id].non_mirrored_range.overlaps( - i_smp_chip.non_mirrored_range)) - { - FAPI_ERR("proc_setup_bars_insert_chip: Existing node non-mirrored range overlaps chip non-mirrored range"); - const uint64_t& NODE_BASE_ADDR = - io_smp.nodes[node_id].non_mirrored_range.base_addr; - const uint64_t& NODE_SIZE = - io_smp.nodes[node_id].non_mirrored_range.size; - const uint64_t& CHIP_BASE_ADDR = - i_smp_chip.non_mirrored_range.base_addr; - const uint64_t& CHIP_SIZE = - i_smp_chip.non_mirrored_range.size; - FAPI_SET_HWP_ERROR(rc, - RC_PROC_SETUP_BARS_NODE_NON_MIRRORED_RANGE_OVERLAP_ERR); - break; - } - FAPI_DBG("proc_setup_bars_insert_chip: Mirrored ranges prior to merging:"); - io_smp.nodes[node_id].mirrored_range.print(); + io_smp.nodes[node_id].mirrored_ranges.push_back(&(io_smp.nodes[node_id].chips[chip_id].mirrored_range)); i_smp_chip.mirrored_range.print(); - if (io_smp.nodes[node_id].mirrored_range.overlaps( - i_smp_chip.mirrored_range)) - { - FAPI_ERR("proc_setup_bars_insert_chip: Existing node mirrored range overlaps chip mirrored range"); - const uint64_t& NODE_BASE_ADDR = - io_smp.nodes[node_id].mirrored_range.base_addr; - const uint64_t& NODE_SIZE = - io_smp.nodes[node_id].mirrored_range.size; - const uint64_t& CHIP_BASE_ADDR = - i_smp_chip.mirrored_range.base_addr; - const uint64_t& CHIP_SIZE = - i_smp_chip.mirrored_range.size; - FAPI_SET_HWP_ERROR(rc, - RC_PROC_SETUP_BARS_NODE_MIRRORED_RANGE_OVERLAP_ERR); - break; - } - - // update node address ranges (non-mirrored & mirrored) - FAPI_DBG("proc_setup_bars_insert_chip: Ranges after merging:"); - io_smp.nodes[node_id].non_mirrored_range.merge( - i_smp_chip.non_mirrored_range); - io_smp.nodes[node_id].non_mirrored_range.print(); - io_smp.nodes[node_id].mirrored_range.merge( - i_smp_chip.mirrored_range); - io_smp.nodes[node_id].mirrored_range.print(); } while(0); // mark function exit @@ -1492,17 +1463,60 @@ fapi::ReturnCode proc_setup_bars_process_chips( break; } - // perform final power of two adjustment on node specific resources once + // perform final adjustment on node specific resources once // all chips have been processed std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node>::iterator n_iter; for (n_iter = io_smp.nodes.begin(); n_iter != io_smp.nodes.end(); n_iter++) { + FAPI_DBG("Performing final adjustment on n%d", n_iter->first); + + // merge into single range + for (uint8_t r = 0; r < n_iter->second.non_mirrored_ranges.size(); r++) + { + n_iter->second.non_mirrored_ranges[r]->print(); + } + + // before merging, check that non-mirrored & mirrored ranges are non-overlapping + if (proc_setup_bars_common_do_ranges_overlap(n_iter->second.non_mirrored_ranges)) + { + FAPI_ERR("proc_setup_bars_process_chips: Existing node non-mirrored range overlaps chip non-mirrored range"); + const uint8_t& NODE_ID = n_iter->first; + FAPI_SET_HWP_ERROR(rc, + RC_PROC_SETUP_BARS_NODE_NON_MIRRORED_RANGE_OVERLAP_ERR); + break; + } + + if (proc_setup_bars_common_do_ranges_overlap(n_iter->second.mirrored_ranges)) + { + FAPI_ERR("proc_setup_bars_process_chips: Existing node mirrored range overlaps chip mirrored range"); + const uint8_t& NODE_ID = n_iter->first; + FAPI_SET_HWP_ERROR(rc, + RC_PROC_SETUP_BARS_NODE_MIRRORED_RANGE_OVERLAP_ERR); + break; + } + + // merge into single range + for (uint8_t r = 0; r < n_iter->second.non_mirrored_ranges.size(); r++) + { + n_iter->second.non_mirrored_range.merge(*(n_iter->second.non_mirrored_ranges[r])); + } + + for (uint8_t r = 0; r < n_iter->second.mirrored_ranges.size(); r++) + { + n_iter->second.mirrored_range.merge(*(n_iter->second.mirrored_ranges[r])); + } + // update node address ranges (non-mirrored & mirrored) + FAPI_DBG("proc_setup_bars_process_chips: Ranges after merging:"); + n_iter->second.non_mirrored_range.print(); + n_iter->second.mirrored_range.print(); + + // update node address ranges (non-mirrored & mirrored) t + // ensure ranges are power of 2 aligned FAPI_DBG("proc_setup_bars_process_chips: Node %d ranges after power of two alignment:", n_iter->first); - // ensure range is power of 2 aligned if (n_iter->second.non_mirrored_range.enabled && !n_iter->second.non_mirrored_range.is_power_of_2()) { @@ -3513,10 +3527,29 @@ fapi::ReturnCode proc_setup_bars_config_mcd( if (config_mcd) { + uint64_t mcd_fir_mask; + uint8_t mcd_hang_poll_bug; + rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG, + &(p_iter->second.chip->this_chip), + mcd_hang_poll_bug); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_config_mcd: Error querying ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG"); + } + + if (mcd_hang_poll_bug != 0) + { + mcd_fir_mask = MCD_FIR_MASK_RUNTIME_VAL_MCD_HANG_POLL_BUG; + } + else + { + mcd_fir_mask = MCD_FIR_MASK_RUNTIME_VAL_NO_MCD_HANG_POLL_BUG; + } + // unmask MCD FIR rc_ecmd |= mcd_fir_mask_data.setDoubleWord( 0, - MCD_FIR_MASK_RUNTIME_VAL); + mcd_fir_mask); // check buffer manipulation return codes if (rc_ecmd) diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H index 23f36673e..b35c9c120 100644 --- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_setup_bars.H,v 1.9 2013/06/13 13:21:37 jmcgill Exp $ +// $Id: proc_setup_bars.H,v 1.12 2013/08/28 22:00:54 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars.H,v $ //------------------------------------------------------------------------------ // *| @@ -98,7 +98,6 @@ #include <map> #include <fapi.H> #include "proc_fab_smp.H" -#include "opt_memmap.H" #include "p8_scom_addresses.H" @@ -347,9 +346,11 @@ struct proc_setup_bars_smp_node // fabric node ID proc_fab_smp_node_id node_id; // real address ranges covered for mirrored & non-mirrored regions - // considering all chips in node) + // (considering all chips in node) proc_setup_bars_addr_range non_mirrored_range; + std::vector<proc_setup_bars_addr_range*> non_mirrored_ranges; proc_setup_bars_addr_range mirrored_range; + std::vector<proc_setup_bars_addr_range*> mirrored_ranges; }; // structure to represent collection of nodes in SMP topology @@ -996,7 +997,8 @@ const proc_setup_bars_bar_reg_def mcd_f1_bar_reg_def = }; // MCD FIR Register constants -const uint64_t MCD_FIR_MASK_RUNTIME_VAL = 0x2700000000000000ULL; +const uint64_t MCD_FIR_MASK_RUNTIME_VAL_MCD_HANG_POLL_BUG = 0x2F00000000000000ULL; +const uint64_t MCD_FIR_MASK_RUNTIME_VAL_NO_MCD_HANG_POLL_BUG = 0x2700000000000000ULL; // MCD Evn/Odd Recovery Control Register field/bit definitions const uint8_t PROC_SETUP_BARS_NUM_MCD_CFG = 4; diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_errors.xml b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_errors.xml index ddd532140..c8db40655 100644 --- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_errors.xml +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_errors.xml @@ -20,7 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_setup_bars_errors.xml,v 1.4 2013/05/23 19:41:05 jmcgill Exp $ --> +<!-- $Id: proc_setup_bars_errors.xml,v 1.5 2013/08/12 22:16:32 jmcgill Exp $ --> <!-- Error definitions for proc_setup_bars --> <hwpErrors> <!-- *********************************************************************** --> @@ -128,18 +128,12 @@ <hwpError> <rc>RC_PROC_SETUP_BARS_NODE_NON_MIRRORED_RANGE_OVERLAP_ERR</rc> <description>Existing node non-mirrored range overlaps chip non-mirrored range.</description> - <ffdc>NODE_BASE_ADDR</ffdc> - <ffdc>NODE_SIZE</ffdc> - <ffdc>CHIP_BASE_ADDR</ffdc> - <ffdc>CHIP_SIZE</ffdc> + <ffdc>NODE_ID</ffdc> </hwpError> <hwpError> <rc>RC_PROC_SETUP_BARS_NODE_MIRRORED_RANGE_OVERLAP_ERR</rc> <description>Existing node mirrored range overlaps chip mirrored range.</description> - <ffdc>NODE_BASE_ADDR</ffdc> - <ffdc>NODE_SIZE</ffdc> - <ffdc>CHIP_BASE_ADDR</ffdc> - <ffdc>CHIP_SIZE</ffdc> + <ffdc>NODE_ID</ffdc> </hwpError> <hwpError> <rc>RC_PROC_SETUP_BARS_INVALID_BAR_REG_DEF</rc> diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml index 4046388f3..be594585c 100644 --- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml @@ -20,6 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_setup_bars_memory_attributes.xml,v 1.9 2013/07/09 16:26:28 bellows Exp $ --> <!-- proc_setup_bars_memory_attributes.xml --> <attributes> <!-- ********************************************************************* --> @@ -77,6 +78,21 @@ </attribute> <!-- ********************************************************************* --> <attribute> + <id>ATTR_PROC_MEM_BASES_ACK</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Non-mirrored memory base addresses + creator: mss_setup_bars + consumer: opt_mem_map + Mem opt map uses this for the bases of the non-mirror ranges. + (max number based on Venice design) + </description> + <valueType>uint64</valueType> + <array>8</array> + <writeable/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> <id>ATTR_PROC_MEM_SIZES</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>Size of non-mirrored memory regions @@ -95,6 +111,20 @@ </attribute> <!-- ********************************************************************* --> <attribute> + <id>ATTR_PROC_MEM_SIZES_ACK</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Size of non-mirrored memory regions up to a power of 2 + creator: mss_setup_bars + consumer: opt_mem_map + Mem opt map uses this to stack mirror ranges. The real amount of memory behind the mirror group maybe less than the number reported here if there are memory holes + </description> + <valueType>uint64</valueType> + <array>8</array> + <writeable/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> <id>ATTR_PROC_MIRROR_BASE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>Base address for mirrored memory regions @@ -126,6 +156,21 @@ </attribute> <!-- ********************************************************************* --> <attribute> + <id>ATTR_PROC_MIRROR_BASES_ACK</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Mirrored memory base addresses + creator: mss_setup_bars + consumer: consumer: opt_mem_map + Mem opt map uses this for the bases of the mirror ranges. + (max number based on Venice design) + </description> + <valueType>uint64</valueType> + <array>4</array> + <writeable/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> <id>ATTR_PROC_MIRROR_SIZES</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>Size of mirrored memory region @@ -144,6 +189,20 @@ </attribute> <!-- ********************************************************************* --> <attribute> + <id>ATTR_PROC_MIRROR_SIZES_ACK</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Size of mirrored memory region up to a power of 2 + creator: mss_setup_bars + consumer: opt_mem_map + Mem opt map uses this to stack mirror ranges. The real amount of memory behind the mirror group maybe less than the number reported here if there are memory holes + </description> + <valueType>uint64</valueType> + <array>4</array> + <writeable/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> <id>ATTR_PROC_FOREIGN_NEAR_BASE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>Foreign (near) address region base address diff --git a/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile index 73a42d943..1f05f1aea 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: p8.fbc.scom.initfile,v 1.12 2013/06/19 18:58:32 jmcgill Exp $ +#-- $Id: p8.fbc.scom.initfile,v 1.13 2013/08/28 22:03:30 jmcgill Exp $ #------------------------------------------------------------------------------- #-- #-- (C) Copyright International Business Machines Corp. 2011 @@ -27,6 +27,7 @@ define def_x_is_4b = (SYS.ATTR_PROC_X_BUS_WIDTH == ENUM_ATTR_PROC_X_BUS_WIDTH_W4 define xbus_enabled = (ATTR_PROC_X_ENABLE == ENUM_ATTR_PROC_X_ENABLE_ENABLE); define abus_enabled = (ATTR_PROC_A_ENABLE == ENUM_ATTR_PROC_A_ENABLE_ENABLE); define pcie_enabled = (ATTR_PROC_PCIE_ENABLE == ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE); +define mcd_hang_poll_bug = (ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG != 0); #-------------------------------------------------------------------------------- @@ -104,8 +105,12 @@ scom 0x02013406 { #-- MCD FIR Action1 Register (MCDCTL.FIR_ACTION1_REG / 0x02013407) scom 0x02013407 { - bits, scom_data; - 0:63, 0xC800000000000000; + bits, scom_data, expr; + 0:3, 0xC, any; + 4, 0b1, (!mcd_hang_poll_bug); + 4, 0b0, (mcd_hang_poll_bug); + 5:7, 0b000, any; + 8:63, 0x00000000000000, any; } diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C index 37fcc87cb..e9fbcca25 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_grouping.C,v 1.25 2013/05/23 11:18:45 gpaulraj Exp $ +// $Id: mss_eff_grouping.C,v 1.27 2013/08/13 09:52:18 gpaulraj Exp $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -38,6 +38,9 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.27 | gpaulraj | 08-13-13| Fixed alternate BAR settings for Mirror +// 1.26 | gpaulraj | 08-12-13| added mirror policy and HTM/OCC Bar setup +// 1.25 | gpaulraj | 05-23-13| Fixed FW review feedback // 1.24 | bellows | 04-09-13| Updates that really allow checkboard and all group sizes. Before, group size of 1 was all that was possible // 1.23 | bellows | 03-26-13| Allow for checkboard mode with more than one mcs per group // 1.22 | bellows | 03-21-13| Error Logging support @@ -112,6 +115,17 @@ extern "C" { // MSS EFF GROUPING Variables.......... //---------------------------------------------------- +const uint8_t MCS_SIZE = 0; +const uint8_t MCS_IN_GROUP = 1; +const uint8_t GROUP_SIZE = 2; +const uint8_t BASE_ADDR = 3; +const uint8_t MEMBERS_START_ID = 4; +const uint8_t MEMBERS_END = 11; +const uint8_t ALT_VALID = 12; +const uint8_t ALT_SIZE = 13; +const uint8_t ALT_BASE_ADDR = 14; +const uint8_t LARGEST_MBA_SIZE = 15; + ReturnCode mss_eff_grouping( @@ -125,6 +139,10 @@ extern "C" { //uint32_t pos=0; uint64_t mss_base_address; uint64_t mirror_base; + uint64_t occ_sandbox_base; + uint64_t occ_sandbox_size; + uint64_t htm_bar_base; + uint64_t htm_bar_size; //uint32_t MBA_size[8][2]={{0}}; //uint32_t MCS_size[8]={0}; uint32_t l_unit_pos =0; @@ -229,8 +247,7 @@ extern "C" { uint8_t pos1=0; uint8_t pos2=0; uint8_t allowed=0; - - + uint8_t selective_mode=2; for(uint8_t i=0;i<6;i++) config4_pos[i]=0; @@ -239,6 +256,8 @@ extern "C" { if(!rc.ok()) {FAPI_ERR("MSS_INTERLEAVE_ENABLE is not available"); return rc; } rc = FAPI_ATTR_GET(ATTR_ALL_MCS_IN_INTERLEAVING_GROUP, NULL,check_board); // system level attribute if (!rc.ok()) { FAPI_ERR("Error reading ATTR_ALL_MCS_IN_INTERLEAVING_GROUP"); return rc; } + rc = FAPI_ATTR_GET(ATTR_MEM_MIRROR_PLACEMENT_POLICY, NULL,selective_mode); + if (!rc.ok()) { FAPI_ERR("Error reading ATTR_MEM_MIRROR_PLACEMENT_POLICY"); return rc; } if(check_board) // this is a 1 when interleaving is required to be on Only acceptable > 1MCS per group { @@ -281,9 +300,6 @@ extern "C" { if(!(groups_allowed & 0x08)){FAPI_INF("8MCS/GROUP");} if((groups_allowed & 0x02) || (groups_allowed & 0x04)||(groups_allowed & 0x08)){FAPI_INF("FABRIC IS IN CHECKER BOARD MODE BUT YOU ARE ASKING FOR MORE THAN 1MCS/GROUP. YOU ARE NOT GOING TO HAVE PERFOMRANCE YOU COULD GET IF YOU WERE IN CHECKERBOARD MODE");} - - - } else { @@ -547,7 +563,7 @@ extern "C" { uint64_t total_size_non_mirr =0; for(pos=0;pos<=gp_pos;pos++) - { + { eff_grouping_data.groupID[pos][GROUP_SIZE] = eff_grouping_data.groupID[pos][MCS_SIZE]*eff_grouping_data.groupID[pos][MCS_IN_GROUP]; //eff_grouping_data.groupID[pos+8][2]= eff_grouping_data.groupID[pos][2]/2; // group size when mirrored @@ -565,6 +581,7 @@ extern "C" { //eff_grouping_data.groupID[pos+8][GROUP_SIZE] = eff_grouping_data.groupID[pos][GROUP_SIZE]/2; //group size with alternate bars //eff_grouping_data.groupID[pos+8][ALT_SIZE] = eff_grouping_data.groupID[pos][ALT_SIZE]/2; eff_grouping_data.groupID[pos][ALT_VALID] =1; + // eff_grouping_data.groupID[pos+8][ALT_VALID] =1; } total_size_non_mirr += eff_grouping_data.groupID[pos][GROUP_SIZE]; @@ -598,29 +615,51 @@ extern "C" { if(eff_grouping_data.groupID[pos][MCS_SIZE]!=0 && eff_grouping_data.groupID[pos][MCS_IN_GROUP]>1 ) { eff_grouping_data.groupID[pos+8][GROUP_SIZE]= eff_grouping_data.groupID[pos][GROUP_SIZE]/2; // group size when mirrored - - if(eff_grouping_data.groupID[pos][ALT_VALID]) { FAPI_INF("Mirrored group pos %d needs alternate bars defintation group Size %d\n",pos,eff_grouping_data.groupID[pos][GROUP_SIZE]); //mirrored group eff_grouping_data.groupID[pos+8][GROUP_SIZE] = eff_grouping_data.groupID[pos][GROUP_SIZE]/2; //group size with alternate bars eff_grouping_data.groupID[pos+8][ALT_SIZE] = eff_grouping_data.groupID[pos][ALT_SIZE]/2; + eff_grouping_data.groupID[pos+8][ALT_VALID] =1; } } } + if ( selective_mode == 2) + { + mss_base_address = 0; + rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASE,&i_target,mss_base_address); + mss_base_address = mss_base_address >> 30; + if(!rc.ok()) return rc; + + rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASE,&i_target,mirror_base); + mirror_base = mirror_base >> 30; + if(!rc.ok()) return rc; + rc = FAPI_ATTR_GET(ATTR_PROC_HTM_BAR_SIZE,&i_target,htm_bar_size); + if(!rc.ok()) return rc; - rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASE,&i_target,mss_base_address); - mss_base_address = mss_base_address >> 30; - if(!rc.ok()) return rc; + rc = FAPI_ATTR_GET(ATTR_PROC_OCC_SANDBOX_SIZE,&i_target,occ_sandbox_size); + if(!rc.ok()) return rc; + } + + else{ + rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASE,&i_target,mss_base_address); + mss_base_address = mss_base_address >> 30; + if(!rc.ok()) return rc; + + rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASE,&i_target,mirror_base); + mirror_base = mirror_base >> 30; - rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASE,&i_target,mirror_base); - mirror_base = mirror_base >> 30; + if(!rc.ok()) return rc; + rc = FAPI_ATTR_GET(ATTR_PROC_HTM_BAR_SIZE,&i_target,htm_bar_size); + if(!rc.ok()) return rc; - if(!rc.ok()) return rc; + rc = FAPI_ATTR_GET(ATTR_PROC_OCC_SANDBOX_SIZE,&i_target,occ_sandbox_size); + if(!rc.ok()) return rc; + } if( mss_base_address > (mirror_base + total_size_non_mirr/2) || mirror_base > (mss_base_address + total_size_non_mirr)) { @@ -650,7 +689,6 @@ extern "C" { } } - if(eff_grouping_data.groupID[pos][MCS_IN_GROUP]>1 ) { eff_grouping_data.groupID[pos+8][BASE_ADDR]=mirror_base; @@ -658,6 +696,7 @@ extern "C" { if(eff_grouping_data.groupID[pos][ALT_VALID]) { eff_grouping_data.groupID[pos+8][ALT_BASE_ADDR] = eff_grouping_data.groupID[pos+8][BASE_ADDR]+ eff_grouping_data.groupID[pos+8][GROUP_SIZE]/2; //mirrored base address with alternate bars + eff_grouping_data.groupID[pos+8][ALT_VALID] =1; } } @@ -708,10 +747,13 @@ extern "C" { uint64_t mem_bases[8]; + uint64_t mem_bases_ack[8]; uint64_t l_memory_sizes[8]; - //uint64_t mirror_base; + uint64_t l_memory_sizes_ack[8]; uint64_t mirror_bases[4]; + uint64_t mirror_bases_ack[4]; uint64_t l_mirror_sizes[4]; + uint64_t l_mirror_sizes_ack[4]; //uint32_t temp[8]; for(uint8_t i=0;i<8;i++) { @@ -749,22 +791,344 @@ extern "C" { } // base addresses for distinct non-mirrored ranges + mem_bases[0]=eff_grouping_data.groupID[0][BASE_ADDR]; - mem_bases[0] = mem_bases[0] <<30; mem_bases[1]=eff_grouping_data.groupID[1][BASE_ADDR]; - mem_bases[1] = mem_bases[1] <<30; mem_bases[2]=eff_grouping_data.groupID[2][BASE_ADDR]; - mem_bases[2] = mem_bases[2] <<30; mem_bases[3]=eff_grouping_data.groupID[3][BASE_ADDR]; - mem_bases[3] = mem_bases[3] <<30; mem_bases[4]=eff_grouping_data.groupID[4][BASE_ADDR]; - mem_bases[4] = mem_bases[4] <<30; mem_bases[5]=eff_grouping_data.groupID[5][BASE_ADDR]; - mem_bases[5] = mem_bases[5] <<30; mem_bases[6]=eff_grouping_data.groupID[6][BASE_ADDR]; - mem_bases[6] = mem_bases[6] <<30; mem_bases[7]=eff_grouping_data.groupID[7][BASE_ADDR]; - mem_bases[7] = mem_bases[7] <<30; + + mem_bases_ack[0]=eff_grouping_data.groupID[0][BASE_ADDR]; + mem_bases_ack[1]=eff_grouping_data.groupID[1][BASE_ADDR]; + mem_bases_ack[2]=eff_grouping_data.groupID[2][BASE_ADDR]; + mem_bases_ack[3]=eff_grouping_data.groupID[3][BASE_ADDR]; + mem_bases_ack[4]=eff_grouping_data.groupID[4][BASE_ADDR]; + mem_bases_ack[5]=eff_grouping_data.groupID[5][BASE_ADDR]; + mem_bases_ack[6]=eff_grouping_data.groupID[6][BASE_ADDR]; + mem_bases_ack[7]=eff_grouping_data.groupID[7][BASE_ADDR]; + + if(selective_mode == 2) + { + l_memory_sizes[0]=eff_grouping_data.groupID[0][GROUP_SIZE]/2; + l_memory_sizes[1]=eff_grouping_data.groupID[1][GROUP_SIZE]/2; + l_memory_sizes[2]=eff_grouping_data.groupID[2][GROUP_SIZE]/2; + l_memory_sizes[3]=eff_grouping_data.groupID[3][GROUP_SIZE]/2; + l_memory_sizes[4]=eff_grouping_data.groupID[4][GROUP_SIZE]/2; + l_memory_sizes[5]=eff_grouping_data.groupID[5][GROUP_SIZE]/2; + l_memory_sizes[6]=eff_grouping_data.groupID[6][GROUP_SIZE]/2; + l_memory_sizes[7]=eff_grouping_data.groupID[7][GROUP_SIZE]/2; + + } + else + { + // sizes for distinct non-mirrored ranges + l_memory_sizes[0]=eff_grouping_data.groupID[0][MCS_SIZE]* eff_grouping_data.groupID[0][MCS_IN_GROUP]; + l_memory_sizes[1]=eff_grouping_data.groupID[1][MCS_SIZE]* eff_grouping_data.groupID[1][MCS_IN_GROUP]; + l_memory_sizes[2]=eff_grouping_data.groupID[2][MCS_SIZE]* eff_grouping_data.groupID[2][MCS_IN_GROUP]; + l_memory_sizes[3]=eff_grouping_data.groupID[3][MCS_SIZE]* eff_grouping_data.groupID[3][MCS_IN_GROUP]; + l_memory_sizes[4]=eff_grouping_data.groupID[4][MCS_SIZE]* eff_grouping_data.groupID[4][MCS_IN_GROUP]; + l_memory_sizes[5]=eff_grouping_data.groupID[5][MCS_SIZE]* eff_grouping_data.groupID[5][MCS_IN_GROUP]; + l_memory_sizes[6]=eff_grouping_data.groupID[6][MCS_SIZE]* eff_grouping_data.groupID[6][MCS_IN_GROUP]; + l_memory_sizes[7]=eff_grouping_data.groupID[7][MCS_SIZE]* eff_grouping_data.groupID[7][MCS_IN_GROUP]; + } + + l_memory_sizes_ack[0]=eff_grouping_data.groupID[0][GROUP_SIZE]; + l_memory_sizes_ack[1]=eff_grouping_data.groupID[1][GROUP_SIZE]; + l_memory_sizes_ack[2]=eff_grouping_data.groupID[2][GROUP_SIZE]; + l_memory_sizes_ack[3]=eff_grouping_data.groupID[3][GROUP_SIZE]; + l_memory_sizes_ack[4]=eff_grouping_data.groupID[4][GROUP_SIZE]; + l_memory_sizes_ack[5]=eff_grouping_data.groupID[5][GROUP_SIZE]; + l_memory_sizes_ack[6]=eff_grouping_data.groupID[6][GROUP_SIZE]; + l_memory_sizes_ack[7]=eff_grouping_data.groupID[7][GROUP_SIZE]; + + // process mirrored ranges + // + if(selective_mode == 2) + { + uint8_t groupcount =0; + for(i=0;i<8;i++) + { + if(eff_grouping_data.groupID[i][GROUP_SIZE] > 1) { groupcount++;} + } + if(groupcount<7) + { + mem_bases[groupcount+0] = eff_grouping_data.groupID[8][BASE_ADDR] + (eff_grouping_data.groupID[8][GROUP_SIZE]/2); + mem_bases[groupcount+1] = eff_grouping_data.groupID[9][BASE_ADDR] + (eff_grouping_data.groupID[9][GROUP_SIZE]/2); + mem_bases[groupcount+2] = eff_grouping_data.groupID[10][BASE_ADDR] + (eff_grouping_data.groupID[10][GROUP_SIZE]/2); + mem_bases[groupcount+3] = eff_grouping_data.groupID[11][BASE_ADDR] + (eff_grouping_data.groupID[11][GROUP_SIZE]/2); + } + + mirror_bases[0] = 0; //grouping_data.groupID[8][BASE_ADDR]; + mirror_bases[1] = 0; //eff_grouping_data.groupID[9][BASE_ADDR]; + mirror_bases[2] = 0; //eff_grouping_data.groupID[10][BASE_ADDR]; + mirror_bases[3] = 0; //eff_grouping_data.groupID[11][BASE_ADDR]; + } + else + { + + // base addresses for distinct mirrored ranges + mirror_bases[0] = eff_grouping_data.groupID[8][BASE_ADDR]; + mirror_bases[1] = eff_grouping_data.groupID[9][BASE_ADDR]; + mirror_bases[2] = eff_grouping_data.groupID[10][BASE_ADDR]; + mirror_bases[3] = eff_grouping_data.groupID[11][BASE_ADDR]; + } + mirror_bases_ack[0] = eff_grouping_data.groupID[8][BASE_ADDR]; + mirror_bases_ack[1] = eff_grouping_data.groupID[9][BASE_ADDR]; + mirror_bases_ack[2] = eff_grouping_data.groupID[10][BASE_ADDR]; + mirror_bases_ack[3] = eff_grouping_data.groupID[11][BASE_ADDR]; + + + if(selective_mode == 2) + { + uint8_t groupcount =0; + for(i=0;i<8;i++) + { + if(eff_grouping_data.groupID[i][MCS_IN_GROUP] > 1 ) { groupcount++;} + } + if(groupcount<7) + { + l_memory_sizes[groupcount+0] = eff_grouping_data.groupID[8][GROUP_SIZE]/2; + l_memory_sizes[groupcount+1] = eff_grouping_data.groupID[9][GROUP_SIZE]/2; + l_memory_sizes[groupcount+2] = eff_grouping_data.groupID[10][GROUP_SIZE]/2; + l_memory_sizes[groupcount+3] = eff_grouping_data.groupID[11][GROUP_SIZE]/2; + } + l_mirror_sizes[0] =0; + l_mirror_sizes[1] =0; + l_mirror_sizes[2] =0; + l_mirror_sizes[3] =0; + } + else + { + // sizes for distinct mirrored ranges + for(i=0;i<4;i++) + { + if(eff_grouping_data.groupID[i][MCS_IN_GROUP] > 1 ) + l_mirror_sizes[i]= (eff_grouping_data.groupID[i][MCS_SIZE] *eff_grouping_data.groupID[0][MCS_IN_GROUP]) / 2; + else + { + l_mirror_sizes[i] =0; + } + } + } + l_mirror_sizes_ack[0]=eff_grouping_data.groupID[8][GROUP_SIZE]; + l_mirror_sizes_ack[1]=eff_grouping_data.groupID[9][GROUP_SIZE]; + l_mirror_sizes_ack[2]=eff_grouping_data.groupID[10][GROUP_SIZE]; + l_mirror_sizes_ack[3]=eff_grouping_data.groupID[11][GROUP_SIZE]; + + mem_bases[0] = mem_bases[0] <<30; + mem_bases[1] = mem_bases[1] <<30; + mem_bases[2] = mem_bases[2] <<30; + mem_bases[3] = mem_bases[3] <<30; + mem_bases[4] = mem_bases[4] <<30; + mem_bases[5] = mem_bases[5] <<30; + mem_bases[6] = mem_bases[6] <<30; + mem_bases[7] = mem_bases[7] <<30; + + + mem_bases_ack[0] = mem_bases_ack[0] <<30; + mem_bases_ack[1] = mem_bases_ack[1] <<30; + mem_bases_ack[2] = mem_bases_ack[2] <<30; + mem_bases_ack[3] = mem_bases_ack[3] <<30; + mem_bases_ack[4] = mem_bases_ack[4] <<30; + mem_bases_ack[5] = mem_bases_ack[5] <<30; + mem_bases_ack[6] = mem_bases_ack[6] <<30; + mem_bases_ack[7] = mem_bases_ack[7] <<30; + + l_memory_sizes[0] = l_memory_sizes[0] <<30; + l_memory_sizes[1] = l_memory_sizes[1] <<30; + l_memory_sizes[2] = l_memory_sizes[2] <<30; + l_memory_sizes[3] = l_memory_sizes[3] <<30; + l_memory_sizes[4] = l_memory_sizes[4] <<30; + l_memory_sizes[5] = l_memory_sizes[5] <<30; + l_memory_sizes[6] = l_memory_sizes[6] <<30; + l_memory_sizes[7] = l_memory_sizes[7] <<30; + + + l_memory_sizes_ack[0] = l_memory_sizes_ack[0] <<30; + l_memory_sizes_ack[1] = l_memory_sizes_ack[1] <<30; + l_memory_sizes_ack[2] = l_memory_sizes_ack[2] <<30; + l_memory_sizes_ack[3] = l_memory_sizes_ack[3] <<30; + l_memory_sizes_ack[4] = l_memory_sizes_ack[4] <<30; + l_memory_sizes_ack[5] = l_memory_sizes_ack[5] <<30; + l_memory_sizes_ack[6] = l_memory_sizes_ack[6] <<30; + l_memory_sizes_ack[7] = l_memory_sizes_ack[7] <<30; + + mirror_bases[0] = mirror_bases[0]<<30; + mirror_bases[1] = mirror_bases[1]<<30; + mirror_bases[2] = mirror_bases[2]<<30; + mirror_bases[3] = mirror_bases[3]<<30; + + + mirror_bases_ack[0] = mirror_bases_ack[0]<<30; + mirror_bases_ack[1] = mirror_bases_ack[1]<<30; + mirror_bases_ack[2] = mirror_bases_ack[2]<<30; + mirror_bases_ack[3] = mirror_bases_ack[3]<<30; + + l_mirror_sizes[0] = l_mirror_sizes[0]<<30; + l_mirror_sizes[1] = l_mirror_sizes[1]<<30; + l_mirror_sizes[2] = l_mirror_sizes[2]<<30; + l_mirror_sizes[3] = l_mirror_sizes[3]<<30; + + FAPI_DBG(" ATTR_PROC_MIRROR_SIZES[0]: %016llx", l_mirror_sizes[0]); + FAPI_DBG(" ATTR_PROC_MIRROR_SIZES[1]: %016llx", l_mirror_sizes[1]); + FAPI_DBG(" ATTR_PROC_MIRROR_SIZES[2]: %016llx", l_mirror_sizes[2]); + FAPI_DBG(" ATTR_PROC_MIRROR_SIZES[3]: %016llx", l_mirror_sizes[3]); + + l_mirror_sizes_ack[0] = l_mirror_sizes_ack[0]<<30; + l_mirror_sizes_ack[1] = l_mirror_sizes_ack[1]<<30; + l_mirror_sizes_ack[2] = l_mirror_sizes_ack[2]<<30; + l_mirror_sizes_ack[3] = l_mirror_sizes_ack[3]<<30; + + ReturnCode ungroup_rc; + if (selective_mode == 0x02) + { + if (htm_bar_size != 0 || occ_sandbox_size != 0) + { + FAPI_ERR("Selective mode does not support the HTM and OCC SANDBOX BARS"); + // FAPI_SET_HWP_ERROR(ungroup_rc,RC_OPT_MEMMAP_ALLOC_ERR); + break; + } + } + else if(selective_mode == 0x00) + { + uint64_t total_size = 0; + uint8_t memhole =0; + for(i=0;i<8;i++) + { + total_size += l_memory_sizes[i]; + if (eff_grouping_data.groupID[i][ALT_VALID]) { memhole++; } + } + if ((total_size >= (htm_bar_size+occ_sandbox_size)) && ((htm_bar_size+occ_sandbox_size)>0)) + { + uint64_t other_bar_size =0; + other_bar_size = htm_bar_size+occ_sandbox_size ; + uint64_t non_mirroring_size = total_size - other_bar_size; + uint64_t temp_size = 0; + uint8_t done =0; + uint8_t j; + i=0; + while(!done) + { + if ((temp_size <= non_mirroring_size) && ( non_mirroring_size <= (temp_size += l_memory_sizes[i++]))) + { + done = 1; + } + } + j =i; +// if ( (other_bar_size > l_memory_sizes[i-1]) && (memhole==0)) +// { +// l_memory_sizes[i-1] = l_memory_sizes[i-1] - (temp_size - non_mirroring_size); +// for(;i<8;i++){ if (l_memory_sizes[i]) l_memory_sizes[i] =0;} +// } + if (memhole) + { + if( l_memory_sizes[j-1] < other_bar_size ) + { + FAPI_ERR(" MEMORY HTM/OCC BAR not possible "); + FAPI_DBG(" TOTAL MEMORY %016llx", l_memory_sizes[j-1]); + break; + } + else{ l_memory_sizes[i-1] = l_memory_sizes[i-1] - (temp_size - non_mirroring_size);} + } + else{ l_memory_sizes[i-1] = l_memory_sizes[i-1] - (temp_size - non_mirroring_size); for(;i<8;i++){ if (l_memory_sizes[i]) l_memory_sizes[i] =0;}} + + if( htm_bar_size < occ_sandbox_size) + { + occ_sandbox_base = mem_bases[j-1]+l_memory_sizes[j-1]; + htm_bar_base = occ_sandbox_base + occ_sandbox_size; + } + else + { + htm_bar_base = mem_bases[j-1]+l_memory_sizes[j-1]; + occ_sandbox_base = htm_bar_base + htm_bar_size; + } + + FAPI_DBG(" TOTAL MEMORY %016llx", total_size); + FAPI_DBG(" MIRRORING SIZE: %016llx & %d", l_mirror_sizes[j-1], j); + FAPI_DBG(" Requitred MIRRORING SIZE: %016llx ", non_mirroring_size); + FAPI_DBG(" HTM_BASE : %016llx", htm_bar_base) ; + FAPI_DBG(" OCC_BASE : %016llx", occ_sandbox_base); + + } + else if ((total_size >= (htm_bar_size+occ_sandbox_size)) && ((htm_bar_size+occ_sandbox_size) ==0)) {} + else + { + + FAPI_ERR(" Required memory space for the HTM and OCC SANDBOX BARS is not available "); + // FAPI_SET_HWP_ERROR((ungroup_rc,RC_OPT_MEMMAP_ALLOC_ERR); + break; + } + } + else if(selective_mode == 0x01) + { + uint64_t total_size = 0; + uint8_t memhole =0; + uint8_t j=0; + for(i=0;i<4;i++) + { + total_size += l_mirror_sizes[i]; + if (eff_grouping_data.groupID[i][ALT_VALID]) { memhole++; } + } + //if (total_size >= (htm_bar_size+occ_sandbox_size)) + if ((total_size >= (htm_bar_size+occ_sandbox_size)) && ((htm_bar_size+occ_sandbox_size)>0)) + { + uint64_t other_bar_size =0; + other_bar_size = htm_bar_size+occ_sandbox_size ; + uint64_t non_mirroring_size = total_size - other_bar_size; + uint64_t temp_size = 0; + uint8_t done =0; + i=0; + while(!done) + { + if ((temp_size <= non_mirroring_size) && ( non_mirroring_size <= (temp_size += l_mirror_sizes[i++]))) + { + done = 1; + } + } + j = i; +// if ( (other_bar_size > l_mirror_sizes[i-1]) && (memhole==0)) +// { +// l_mirror_sizes[i-1] = l_mirror_sizes[i-1] - (temp_size - non_mirroring_size); +/// for(;i<4;i++){ if (l_mirror_sizes[i]) l_mirror_sizes[i] =0;} +// } + if (memhole) + { + if( l_mirror_sizes[j-1] < other_bar_size ) + { + FAPI_ERR(" MEMORY HTM/OCC BAR not possible "); + FAPI_DBG(" TOTAL MEMORY %016llx", l_memory_sizes[j-1]); + break; + } + else{ l_mirror_sizes[i-1] = l_mirror_sizes[i-1] - (temp_size - non_mirroring_size);} + } + else{ l_mirror_sizes[i-1] = l_mirror_sizes[i-1] - (temp_size - non_mirroring_size); for(;i<8;i++){ if (l_memory_sizes[i]) l_memory_sizes[i] =0;}} + if( htm_bar_size < occ_sandbox_size) + { + occ_sandbox_base = mirror_bases[j-1]+ l_mirror_sizes[j-1]; + htm_bar_size = occ_sandbox_base + occ_sandbox_size; + } + else + { + htm_bar_base = mirror_bases[j-1]+ l_mirror_sizes[j-1]; + occ_sandbox_base = htm_bar_base + htm_bar_size; + } + FAPI_DBG(" TOTAL MEMORY %016llx", total_size); + FAPI_DBG(" MIRRORING SIZE: %016llx & %d", l_mirror_sizes[j-1], j); + FAPI_DBG(" Requitred MIRRORING SIZE: %016llx ", non_mirroring_size); + FAPI_DBG(" HTM_BASE : %016llx", htm_bar_base) ; + FAPI_DBG(" OCC_BASE : %016llx", occ_sandbox_base); + } + else if ((total_size >= (htm_bar_size+occ_sandbox_size)) && ((htm_bar_size+occ_sandbox_size) ==0)) {} + else + { + FAPI_ERR(" Required memory space for the HTM and OCC SANDBOX BARS is not available "); + // FAPI_SET_HWP_ERROR((ungroup_rc,RC_OPT_MEMMAP_ALLOC_ERR); + break; + } + } FAPI_DBG(" ATTR_PROC_MEM_BASES[0]: %016llx", mem_bases[0]); FAPI_DBG(" ATTR_PROC_MEM_BASES[1]: %016llx", mem_bases[1]); @@ -782,23 +1146,23 @@ extern "C" { break; } - // sizes for distinct non-mirrored ranges - l_memory_sizes[0]=eff_grouping_data.groupID[0][GROUP_SIZE]; - l_memory_sizes[0] = l_memory_sizes[0] <<30; - l_memory_sizes[1]=eff_grouping_data.groupID[1][GROUP_SIZE]; - l_memory_sizes[1] = l_memory_sizes[1] <<30; - l_memory_sizes[2]=eff_grouping_data.groupID[2][GROUP_SIZE]; - l_memory_sizes[2] = l_memory_sizes[2] <<30; - l_memory_sizes[3]=eff_grouping_data.groupID[3][GROUP_SIZE]; - l_memory_sizes[3] = l_memory_sizes[3] <<30; - l_memory_sizes[4]=eff_grouping_data.groupID[4][GROUP_SIZE]; - l_memory_sizes[4] = l_memory_sizes[4] <<30; - l_memory_sizes[5]=eff_grouping_data.groupID[5][GROUP_SIZE]; - l_memory_sizes[5] = l_memory_sizes[5] <<30; - l_memory_sizes[6]=eff_grouping_data.groupID[6][GROUP_SIZE]; - l_memory_sizes[6] = l_memory_sizes[6] <<30; - l_memory_sizes[7]=eff_grouping_data.groupID[7][GROUP_SIZE]; - l_memory_sizes[7] = l_memory_sizes[7] <<30; + + FAPI_DBG(" ATTR_PROC_MEM_BASES_ACK[0]: %016llx", mem_bases_ack[0]); + FAPI_DBG(" ATTR_PROC_MEM_BASES_ACK[1]: %016llx", mem_bases_ack[1]); + FAPI_DBG(" ATTR_PROC_MEM_BASES_ACK[2]: %016llx", mem_bases_ack[2]); + FAPI_DBG(" ATTR_PROC_MEM_BASES_ACK[3]: %016llx", mem_bases_ack[3]); + FAPI_DBG(" ATTR_PROC_MEM_BASES_ACK[4]: %016llx", mem_bases_ack[4]); + FAPI_DBG(" ATTR_PROC_MEM_BASES_ACK[5]: %016llx", mem_bases_ack[5]); + FAPI_DBG(" ATTR_PROC_MEM_BASES_ACK[6]: %016llx", mem_bases_ack[6]); + FAPI_DBG(" ATTR_PROC_MEM_BASES_ACK[7]: %016llx", mem_bases_ack[7]); + + rc = FAPI_ATTR_SET(ATTR_PROC_MEM_BASES_ACK, &i_target, mem_bases_ack); + if (!rc.ok()) + { + FAPI_ERR("Error writing ATTR_PROC_MEM_BASES_ACK"); + break; + } + FAPI_DBG(" ATTR_PROC_MEM_SIZES[0]: %016llx", l_memory_sizes[0]); FAPI_DBG(" ATTR_PROC_MEM_SIZES[1]: %016llx", l_memory_sizes[1]); @@ -808,21 +1172,27 @@ extern "C" { FAPI_DBG(" ATTR_PROC_MEM_SIZES[5]: %016llx", l_memory_sizes[5]); FAPI_DBG(" ATTR_PROC_MEM_SIZES[6]: %016llx", l_memory_sizes[6]); FAPI_DBG(" ATTR_PROC_MEM_SIZES[7]: %016llx", l_memory_sizes[7]); - rc = FAPI_ATTR_SET(ATTR_PROC_MEM_SIZES, &i_target, l_memory_sizes); if (!rc.ok()) { FAPI_ERR("Error writing ATTR_PROC_MEM_SIZES"); break; } - FAPI_DBG(" ATTR_PROC_MEM_SIZES[0]: %016llx", l_memory_sizes[0]); - FAPI_DBG(" ATTR_PROC_MEM_SIZES[1]: %016llx", l_memory_sizes[1]); - FAPI_DBG(" ATTR_PROC_MEM_SIZES[2]: %016llx", l_memory_sizes[2]); - FAPI_DBG(" ATTR_PROC_MEM_SIZES[3]: %016llx", l_memory_sizes[3]); - FAPI_DBG(" ATTR_PROC_MEM_SIZES[4]: %016llx", l_memory_sizes[4]); - FAPI_DBG(" ATTR_PROC_MEM_SIZES[5]: %016llx", l_memory_sizes[5]); - FAPI_DBG(" ATTR_PROC_MEM_SIZES[6]: %016llx", l_memory_sizes[6]); - FAPI_DBG(" ATTR_PROC_MEM_SIZES[7]: %016llx", l_memory_sizes[7]); + FAPI_DBG(" ATTR_PROC_MEM_SIZES_ACK[0]: %016llx", l_memory_sizes_ack[0]); + FAPI_DBG(" ATTR_PROC_MEM_SIZES_ACK[1]: %016llx", l_memory_sizes_ack[1]); + FAPI_DBG(" ATTR_PROC_MEM_SIZES_ACK[2]: %016llx", l_memory_sizes_ack[2]); + FAPI_DBG(" ATTR_PROC_MEM_SIZES_ACK[3]: %016llx", l_memory_sizes_ack[3]); + FAPI_DBG(" ATTR_PROC_MEM_SIZES_ACK[4]: %016llx", l_memory_sizes_ack[4]); + FAPI_DBG(" ATTR_PROC_MEM_SIZES_ACK[5]: %016llx", l_memory_sizes_ack[5]); + FAPI_DBG(" ATTR_PROC_MEM_SIZES_ACK[6]: %016llx", l_memory_sizes_ack[6]); + FAPI_DBG(" ATTR_PROC_MEM_SIZES_ACK[7]: %016llx", l_memory_sizes_ack[7]); + + rc = FAPI_ATTR_SET(ATTR_PROC_MEM_SIZES_ACK, &i_target, l_memory_sizes_ack); + if (!rc.ok()) + { + FAPI_ERR("Error writing ATTR_PROC_MEM_SIZES_ACK"); + break; + } rc = FAPI_ATTR_SET(ATTR_MSS_MCS_GROUP_32,&i_target, eff_grouping_data.groupID); if (!rc.ok()) @@ -830,20 +1200,8 @@ extern "C" { FAPI_ERR("Error writing ATTR_MSS_MCS_GROUP"); break; } - // process mirrored ranges - // - - // base addresses for distinct mirrored ranges - mirror_bases[0] = eff_grouping_data.groupID[8][BASE_ADDR]; - mirror_bases[1] = eff_grouping_data.groupID[9][BASE_ADDR]; - mirror_bases[2] = eff_grouping_data.groupID[10][BASE_ADDR]; - mirror_bases[3] = eff_grouping_data.groupID[11][BASE_ADDR]; - mirror_bases[0] = mirror_bases[0]<<30; - mirror_bases[1] = mirror_bases[1]<<30; - mirror_bases[2] = mirror_bases[2]<<30; - mirror_bases[3] = mirror_bases[3]<<30; FAPI_DBG(" ATTR_PROC_MIRROR_BASES[0]: %016llx", mirror_bases[0]); FAPI_DBG(" ATTR_PROC_MIRROR_BASES[1]: %016llx", mirror_bases[1]); FAPI_DBG(" ATTR_PROC_MIRROR_BASES[2]: %016llx", mirror_bases[2]); @@ -856,16 +1214,17 @@ extern "C" { break; } - // sizes for distinct mirrored ranges - l_mirror_sizes[0]=eff_grouping_data.groupID[8][GROUP_SIZE]; - l_mirror_sizes[1]=eff_grouping_data.groupID[9][GROUP_SIZE]; - l_mirror_sizes[2]=eff_grouping_data.groupID[10][GROUP_SIZE]; - l_mirror_sizes[3]=eff_grouping_data.groupID[11][GROUP_SIZE]; + FAPI_DBG(" ATTR_PROC_MIRROR_BASES[0]: %016llx", mirror_bases_ack[0]); + FAPI_DBG(" ATTR_PROC_MIRROR_BASES[1]: %016llx", mirror_bases_ack[1]); + FAPI_DBG(" ATTR_PROC_MIRROR_BASES[2]: %016llx", mirror_bases_ack[2]); + FAPI_DBG(" ATTR_PROC_MIRROR_BASES[3]: %016llx", mirror_bases_ack[3]); - l_mirror_sizes[0] = l_mirror_sizes[0]<<30; - l_mirror_sizes[1] = l_mirror_sizes[1]<<30; - l_mirror_sizes[2] = l_mirror_sizes[2]<<30; - l_mirror_sizes[3] = l_mirror_sizes[3]<<30; + rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_BASES_ACK, &i_target, mirror_bases_ack); + if (!rc.ok()) + { + FAPI_ERR("Error writing ATTR_PROC_MIRROR_BASES_ACK"); + break; + } FAPI_DBG(" ATTR_PROC_MIRROR_SIZES[0]: %016llx", l_mirror_sizes[0]); FAPI_DBG(" ATTR_PROC_MIRROR_SIZES[1]: %016llx", l_mirror_sizes[1]); @@ -878,6 +1237,31 @@ extern "C" { FAPI_ERR("Error writing ATTR_PROC_MIRROR_SIZES"); break; } + FAPI_DBG(" ATTR_PROC_MIRROR_SIZES_ACK[0]: %016llx", l_mirror_sizes_ack[0]); + FAPI_DBG(" ATTR_PROC_MIRROR_SIZES_ACK[1]: %016llx", l_mirror_sizes_ack[1]); + FAPI_DBG(" ATTR_PROC_MIRROR_SIZES_ACK[2]: %016llx", l_mirror_sizes_ack[2]); + FAPI_DBG(" ATTR_PROC_MIRROR_SIZES_ACK[3]: %016llx", l_mirror_sizes_ack[3]); + rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_SIZES_ACK, &i_target, l_mirror_sizes_ack); + if (!rc.ok()) + { + FAPI_ERR("Error writing ATTR_PROC_MIRROR_SIZES_ACK"); + break; + } + rc = FAPI_ATTR_SET(ATTR_PROC_HTM_BAR_BASE_ADDR, &i_target, htm_bar_base); + if (!rc.ok()) + { + FAPI_ERR("Error writing ATTR_PROC_HTM_BAR_BASE_ADDR"); + break; + + } + + rc = FAPI_ATTR_SET( ATTR_PROC_OCC_SANDBOX_BASE_ADDR, &i_target, occ_sandbox_base); + if (!rc.ok()) + { + FAPI_ERR("Error writing ATTR_PROC_OCC_SANDBOX_BASE_ADDR"); + break; + + } }while(0); return rc; } diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.H index 8bb490a9b..dde700e6e 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.H +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_grouping.H,v 1.6 2013/05/23 11:19:17 gpaulraj Exp $ +// $Id: mss_eff_grouping.H,v 1.7 2013/08/12 16:29:18 gpaulraj Exp $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -41,6 +41,7 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.7 | gpaulraj | 08/12/13| moved constants to C file // 1.6 | gpaulraj | 05/22/13| added constants for debugging purpose // 1.5 | bellows | 09/25/12| review updates made // 1.4 | bellows | 08/31/12| object updated, call updated @@ -61,16 +62,16 @@ // Constant definitions //------------------------------------------------------------------------------ -const uint8_t MCS_SIZE = 0; -const uint8_t MCS_IN_GROUP = 1; -const uint8_t GROUP_SIZE = 2; -const uint8_t BASE_ADDR = 3; -const uint8_t MEMBERS_START_ID = 4; -const uint8_t MEMBERS_END = 11; -const uint8_t ALT_VALID = 12; -const uint8_t ALT_SIZE = 13; -const uint8_t ALT_BASE_ADDR = 14; -const uint8_t LARGEST_MBA_SIZE = 15; +//const uint8_t MCS_SIZE = 0; +//const uint8_t MCS_IN_GROUP = 1; +//const uint8_t GROUP_SIZE = 2; +///const uint8_t BASE_ADDR = 3; +//const uint8_t MEMBERS_START_ID = 4; +//const uint8_t MEMBERS_END = 11; +//const uint8_t ALT_VALID = 12; +//const uint8_t ALT_SIZE = 13; +//const uint8_t ALT_BASE_ADDR = 14; +//const uint8_t LARGEST_MBA_SIZE = 15; //------------------------------------------------------------------------------ // Class declaration diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.C index 4dc08f9fd..4071fb920 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.C @@ -20,15 +20,37 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: opt_memmap.C,v 1.8 2013/05/06 15:15:36 jmcgill Exp $ +// $Id: opt_memmap.C,v 1.14 2013/08/29 21:13:47 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/opt_memmap.C,v $ //------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : opt_memmap.C +// *! DESCRIPTION : Layout non-mirrored/mirrored address map (FAPI) +// *! +// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com +// *! BACKUP NAME : Van Lee Email: vanlee@us.ibm.com +// *! +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ // CHANGE HISTORY: //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.14 | thi | 08/29/13| Init variable to avoid HB compiler error. +// 1.13 | jmcgill | 08/29/13| Remove use of reverse iter (HB doesn't support) +// 1.12 | jmcgill | 07/10/13| Update to match new attributes, selective +// | | | aligment policy changes +// 1.11 | jmcgill | 06/11/13| Update for alternate BAR support (mirrored) +// 1.10 | jmcgill | 05/24/13| Updates for alternate BAR support +// 1.9 | jmcgill | 05/23/13| Address FW review issues // 1.8 | jmcgill | 04/28/13| Add HTM/OCC memory allocation, fix namespace // 1.7 | jmcgill | 04/20/13| Rewrite to add additional sorting capabilities // | | | desired for exercisor mirroring testing @@ -48,25 +70,24 @@ // after mss_eff_grouping() // // 1) Call opt_memmap() with i_init = true -// - Each proc's ATTR_PROC_MEM_BASE attribute is set to 0 -// - Each proc's ATTR_PROC_MIRROR_BASE attribute is set to 512TB +// - Each proc's ATTR_PROC_MEM_BASE attribute is set to 0 (512TB for flipped +// alignment) +// - Each proc's ATTR_PROC_MIRROR_BASE attribute is set to 512TB (0 for +// flipped alignment, 8TB for selective alignment) // // This provides a basis for mss_eff_grouping() to stack all on-chip // groups. // // 2) mss_eff_grouping() call -// - The HWP updates each proc's ATTR_PROC_MEM_BASES and ATTR_PROC_MEM_SIZES +// - The HWP updates each proc's ATTR_PROC_[MEM|MIRROR]_[BASES|SIZES] // attributes based on the address regions allocated for installed memory // behind each proc -// - ATTR_MSS_MCS_GROUP_32 encapsulates the properties of each group formed. +// - ATTR_PROC_[MEM|MIRROR]_[BASES|SIZES]_ACK are updated to reflect +// the stackable size of each on chip memory region // // 3) Call opt_memmap() with i_init = false -// - Consume mss_eff_grouping() attributes for each proc -// - Align the per-chip non-mirrored and mirrored stacks on each proc to -// a common origin (0) -// - Associate non-mirrored and mirrored partner groups -// - Resize groups & re-stack if producing selective mirrored config -// - Get "effective stackable" size of non-mirrored/mirrored regions +// - Consume mss_eff_grouping() attributes for each proc to determine +// "effective stackable" size of non-mirrored/mirrored regions // on each proc // - Stack procs based on their effective size and desired placement // policy @@ -76,13 +97,15 @@ // -------- ------------- ------------ -------- // NORMAL nm 0TB 512TB // FLIPPED m 512TB 0TB -// SELECTIVE nm+m 0TB 0TB +// SELECTIVE nm+m 0TB 8TB +// +// - Write ATTR_PROC_[MEM|MIRROR]_BASE attributes to their final +// value +// +// 4) mss_eff_grouping() call +// - Second run will produce properly aligned output attributes based +// on final per-chip base address attributes determine in prior step // -// - Rewrite all attributes produced by mss_eff_grouping to reflect -// chip placement -// - Satisfy requests for HTM/OCC memory reservations on each chip -// (HTM requests will alter ATTR_PROC_MEM_SIZES/ATTR_PROC_MIRROR_SIZES, -// as these must reflect the true usable memory allocated for PHYP) //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ @@ -124,40 +147,25 @@ inline uint64_t PowerOf2Roundedup(uint64_t i_number) } -// class to represent group of memory controllers -// shadows attribute data from mss_eff_grouping procedure -class MemGroup +// class to represent memory region +// filled by attribute data from mss_eff_grouping procedure +class MemRegion { public: - // group type (mirrored/non-mirrored) - enum group_type { nm = 0, m = 8 }; + // region type (mirrored/non-mirrored) + enum group_type { nm = 0, m = 1 }; - // group type + // region type group_type iv_group_type; - // group ID, 1st dimension index to MSS_MCS_GROUP_32[] - uint8_t iv_group_id; - // group ID of partner group - uint8_t iv_partner_group_id; - - // group parameters - uint64_t iv_size_per_mcs; - uint8_t iv_group_size; - uint64_t iv_size; - uint64_t iv_base; - uint8_t iv_mcs_member_ids[OPT_MEMMAP_MAX_NM_REGIONS]; - bool iv_use_alt; - uint64_t iv_size_alt; - uint64_t iv_base_alt; - uint64_t iv_biggest_mba; - // memory allocation state - // portion of size which will be exposed to exerciser/PHYP - uint64_t iv_size_exposed; + // region parameters + uint64_t iv_base; + uint64_t iv_size; // comparison operator for sort - bool operator < (MemGroup rhs) const + bool operator < (MemRegion rhs) const { bool l_lt = true; if (iv_base > rhs.iv_base || @@ -168,136 +176,16 @@ public: return l_lt; } - // adjust base address of group (by negative offset) - void decBase(const uint64_t& offset) - { - iv_base -= offset; - if (iv_use_alt) - { - iv_base_alt -= offset; - } - } - - // adjust base address of group (positive offset) - void incBase(const uint64_t& offset) - { - iv_base += offset; - if (iv_use_alt) - { - iv_base_alt += offset; - } - } - - // halve size of group - // assumes no allocations have been made - void halveSize() - { - iv_size /= 2; - iv_size_per_mcs /= 2; - iv_size_exposed /= 2; - - if (iv_use_alt) - { - iv_size_alt /= 2; - } - - iv_biggest_mba /= 2; - } - - // construct from attribute data array - MemGroup(group_type group_type, uint8_t group_id, uint32_t (*group_data)[OPT_MEMMAP_GROUP_32_DIM2]) - { - iv_group_type = group_type; - iv_group_id = group_id; - iv_partner_group_id = 0xFF; - - // consume data from attributes - iv_size_per_mcs = (uint64_t) (group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_MCS_SIZE_INDEX]) * OPT_MEMMAP_GB; - iv_group_size = (uint8_t) (group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_MCS_IN_GROUP_INDEX]); - iv_size = (uint64_t) (group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_SIZE_INDEX]) * OPT_MEMMAP_GB; - iv_base = (uint64_t) (group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_BASE_INDEX]) * OPT_MEMMAP_GB; - for (uint8_t i = OPT_MEMMAP_GROUP_32_MEMBERS_START_INDEX; - i <= OPT_MEMMAP_GROUP_32_MEMBERS_END_INDEX; - i++) - { - if (i < (OPT_MEMMAP_GROUP_32_MEMBERS_START_INDEX + iv_group_size)) - { - iv_mcs_member_ids[i-OPT_MEMMAP_GROUP_32_MEMBERS_START_INDEX] = (uint8_t) (group_data[iv_group_type+iv_group_id][i]); - } - else - { - iv_mcs_member_ids[i-OPT_MEMMAP_GROUP_32_MEMBERS_START_INDEX] = 0xFF; - } - } - - iv_use_alt = group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_ALT_VALID_INDEX]?(true):(false); - iv_size_alt = (uint64_t) (group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_ALT_SIZE_INDEX]) * OPT_MEMMAP_GB; - iv_base_alt = (uint64_t) (group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_ALT_BASE_INDEX]) * OPT_MEMMAP_GB; - iv_biggest_mba = (uint64_t) (group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_LARGEST_MBA_INDEX]) * OPT_MEMMAP_GB; - - // mark all size as exposed - iv_size_exposed = iv_size; - } + // constructor + MemRegion(MemRegion::group_type type, uint64_t base, uint64_t size) : + iv_group_type(type), iv_base(base), iv_size(size) {} // debug function - void dumpGroup() + void dump() { - FAPI_DBG("Group %d [ %s ]", iv_group_id, (iv_group_type == nm)?("nm"):("m")); + FAPI_DBG("Region [ %s ]", (iv_group_type == nm)?("nm"):("m")); FAPI_DBG(" Base: %016llX", iv_base); FAPI_DBG(" Size: %016llX", iv_size); - FAPI_DBG(" MCs: %d [ %016llX ]", iv_group_size, iv_size_per_mcs); - for (uint8_t i = 0; i < iv_group_size; i++) - { - FAPI_DBG(" : %d", iv_mcs_member_ids[i]); - } - FAPI_DBG(" Alt: %s", (iv_use_alt)?("true"):("false")); - FAPI_DBG(" ABase: %016llX", iv_base_alt); - FAPI_DBG(" ASize: %016llX", iv_size_alt); - FAPI_DBG(" Big MBA: %016llX", iv_biggest_mba); - } - - // flush back to attribute data array - void flushAttributes(uint64_t chip_bases[], uint64_t chip_sizes[], uint32_t (*group_data)[OPT_MEMMAP_GROUP_32_DIM2]) - { - // chip size/range attribute arrays expect addresses in B - chip_bases[iv_group_id] = iv_base; - chip_sizes[iv_group_id] = iv_size_exposed; - - // group attribute arrays expect addresses in GB - group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_MCS_SIZE_INDEX] = (uint32_t) ((iv_size_per_mcs) / OPT_MEMMAP_GB); - group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_MCS_IN_GROUP_INDEX] = iv_group_size; - group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_SIZE_INDEX] = (uint32_t) ((iv_size) / OPT_MEMMAP_GB); - group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_BASE_INDEX] = (uint32_t) ((iv_base) / OPT_MEMMAP_GB); - - for (uint8_t i = OPT_MEMMAP_GROUP_32_MEMBERS_START_INDEX; - i <= OPT_MEMMAP_GROUP_32_MEMBERS_END_INDEX; - i++) - { - group_data[iv_group_type+iv_group_id][i] = iv_mcs_member_ids[i-OPT_MEMMAP_GROUP_32_MEMBERS_START_INDEX]; - - } - - group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_ALT_VALID_INDEX] = (iv_use_alt)?(1):(0); - group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_ALT_SIZE_INDEX] = (uint32_t) ((iv_size_alt) / OPT_MEMMAP_GB); - group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_ALT_BASE_INDEX] = (uint32_t) ((iv_base_alt) / OPT_MEMMAP_GB); - group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_LARGEST_MBA_INDEX] = (uint32_t) ((iv_biggest_mba) / OPT_MEMMAP_GB); - } - - // memory allocation function - // returns true if request can be wholly satisfied by this group, - // false otherwise - bool allocate(uint64_t size_req) - { - if (size_req <= iv_size_exposed) - { - iv_size_exposed -= size_req; - return true; - } - else - { - iv_size_exposed = 0; - return false; - } } }; @@ -307,10 +195,6 @@ class ProcChipMemmap { public: - static const uint8_t PROC_CHIP_MEMMAP_NUM_ALLOCATIONS = 2; - static const uint8_t PROC_CHIP_MEMMAP_HTM_ALLOC_INDEX = 0; - static const uint8_t PROC_CHIP_MEMMAP_OCC_ALLOC_INDEX = 1; - // pointer to processor chip target Target *iv_target; // mirroring policy @@ -321,19 +205,15 @@ public: uint8_t iv_node_id; uint8_t iv_chip_id; - // chip non-mirrored base, effective size, and member groups + // chip non-mirrored base, effective size, and member regions uint64_t iv_nm_base; uint64_t iv_nm_eff_size; - std::vector<MemGroup> iv_nm_groups; + std::vector<MemRegion> iv_nm_regions; - // chip mirrored base, effective size, and member groups + // chip mirrored base, effective size, and member regions uint64_t iv_m_base; uint64_t iv_m_eff_size; - std::vector<MemGroup> iv_m_groups; - - // base/size for allocated memory areas - uint64_t iv_alloc_size[PROC_CHIP_MEMMAP_NUM_ALLOCATIONS]; - uint64_t iv_alloc_base[PROC_CHIP_MEMMAP_NUM_ALLOCATIONS]; + std::vector<MemRegion> iv_m_regions; // comparison operator for sort // sort in increasing size, and decreasing proc position @@ -347,8 +227,10 @@ public: // compute effective size based on mirror policy // sort by non-mirrored size - if ((iv_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL) && - (rhs.iv_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL)) + if (((iv_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL) && + (rhs.iv_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL)) || + ((iv_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_SELECTIVE) && + (rhs.iv_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_SELECTIVE))) { l_this_eff_size = iv_nm_eff_size; l_rhs_eff_size = rhs.iv_nm_eff_size; @@ -360,14 +242,6 @@ public: l_this_eff_size = iv_m_eff_size; l_rhs_eff_size = rhs.iv_m_eff_size; } - // sort by sum of non-mirrored/mirrored sizes - else if ((iv_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_SELECTIVE) && - (rhs.iv_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_SELECTIVE)) - { - l_this_eff_size = PowerOf2Roundedup(iv_nm_eff_size + iv_m_eff_size); - l_rhs_eff_size = PowerOf2Roundedup(rhs.iv_nm_eff_size + rhs.iv_m_eff_size); - } - // perform sort comparison if (l_this_eff_size > l_rhs_eff_size || (l_this_eff_size == l_rhs_eff_size && iv_pos < rhs.iv_pos)) @@ -389,7 +263,6 @@ public: uint64_t l_nm_sizes[OPT_MEMMAP_MAX_NM_REGIONS]; uint64_t l_m_bases[OPT_MEMMAP_MAX_M_REGIONS]; uint64_t l_m_sizes[OPT_MEMMAP_MAX_M_REGIONS]; - uint32_t l_mss_mcs_group_32[OPT_MEMMAP_GROUP_32_DIM1][OPT_MEMMAP_GROUP_32_DIM2]; do { @@ -413,7 +286,7 @@ public: } iv_pos = ((4*iv_node_id)+iv_chip_id); - // retrieve base address for each chip, align to common origin + // retrieve base address for each chip rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASE, iv_target, iv_nm_base); @@ -422,14 +295,6 @@ public: FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_MEM_BASE)"); break; } - if (iv_nm_base != OPT_MEMMAP_BASE_ORIGIN) - { - const uint64_t& ADDR = iv_nm_base; - FAPI_ERR("Unexpected value returned for ATTR_PROC_MEM_BASE (=%016llX)", - iv_nm_base); - FAPI_SET_HWP_ERROR(rc, RC_OPT_MEMMAP_MEM_BASE_ERR); - break; - } rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASE, iv_target, @@ -439,63 +304,44 @@ public: FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_MIRROR_BASE)"); break; } - if (iv_m_base != OPT_MEMMAP_OFFSET_ORIGIN) - { - const uint64_t& ADDR = iv_m_base; - FAPI_ERR("Unexpected value returned for ATTR_PROC_MIRROR_BASE (=%016llX)", - iv_m_base); - FAPI_SET_HWP_ERROR(rc, RC_OPT_MEMMAP_MIRROR_BASE_ERR); - break; - } - iv_m_base -= OPT_MEMMAP_OFFSET_ORIGIN; // retrieve regions (bases and sizes) computed by mss_eff_grouping - rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASES, + rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASES_ACK, iv_target, l_nm_bases); if (!rc.ok()) { - FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_MEM_BASES)"); + FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_MEM_BASES_ACK)"); break; } - rc = FAPI_ATTR_GET(ATTR_PROC_MEM_SIZES, + rc = FAPI_ATTR_GET(ATTR_PROC_MEM_SIZES_ACK, iv_target, l_nm_sizes); if (!rc.ok()) { - FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_MEM_SIZES)"); + FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_MEM_SIZES_ACK)"); break; } - rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASES, + rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASES_ACK, iv_target, l_m_bases); if (!rc.ok()) { - FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_MIRROR_BASES)"); + FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_MIRROR_BASES_ACK)"); break; } - rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_SIZES, + rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_SIZES_ACK, iv_target, l_m_sizes); if (!rc.ok()) { - FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_MIRROR_SIZES)"); - break; - } - - // retrieve data structure describing groups formed by mss_eff_grouping - rc = FAPI_ATTR_GET(ATTR_MSS_MCS_GROUP_32, - iv_target, - l_mss_mcs_group_32); - if (!rc.ok()) - { - FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_MSS_MCS_GROUP_32)"); + FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_MIRROR_SIZES_ACK)"); break; } - // populate non-mirrored groups + // populate non-mirrored regions FAPI_INF("Chip n%d:p%d", iv_node_id, iv_chip_id); for (uint8_t i = 0; i < OPT_MEMMAP_MAX_NM_REGIONS; i++) { @@ -503,176 +349,45 @@ public: { FAPI_INF(" l_nm_bases[%d] = %016llX", i, l_nm_bases[i]); FAPI_INF(" l_nm_sizes[%d] = %016llX", i, l_nm_sizes[i]); - MemGroup g(MemGroup::nm, i, l_mss_mcs_group_32); - if ((l_nm_bases[i] != g.iv_base) || - (l_nm_sizes[i] != g.iv_size)) - { - const uint8_t& GROUP = i; - const uint64_t& MEM_BASES = l_nm_bases[i]; - const uint64_t& MEM_SIZES = l_nm_sizes[i]; - const uint64_t& GROUP_BASE = g.iv_base; - const uint64_t& GROUP_SIZE = g.iv_size; - FAPI_ERR("Inconsistent non-mirrored group content"); - FAPI_SET_HWP_ERROR(rc, - RC_OPT_MEMMAP_NON_MIRROR_GROUP_ERR); - break; - } - iv_nm_groups.push_back(g); + MemRegion r(MemRegion::nm, l_nm_bases[i], l_nm_sizes[i]); + iv_nm_regions.push_back(r); } } - if (!rc.ok()) - { - break; - } - // populate mirrored groups + // populate mirrored regions for (uint8_t i = 0; i < OPT_MEMMAP_MAX_M_REGIONS; i++) { if (l_m_sizes[i] != 0) { // align to common origin - l_m_bases[i] -= OPT_MEMMAP_OFFSET_ORIGIN; FAPI_INF(" l_m_bases[%d] = %016llX", i, l_m_bases[i]); FAPI_INF(" l_m_sizes[%d] = %016llX", i, l_m_sizes[i]); - MemGroup g(MemGroup::m, i, l_mss_mcs_group_32); - // align to common origin - g.decBase(OPT_MEMMAP_OFFSET_ORIGIN); - if ((l_m_bases[i] != g.iv_base) || - (l_m_sizes[i] != g.iv_size)) - { - const uint8_t& GROUP = i; - const uint64_t& MIRROR_BASES = l_m_bases[i]; - const uint64_t& MIRROR_SIZES = l_m_sizes[i]; - const uint64_t& GROUP_BASE = g.iv_base; - const uint64_t& GROUP_SIZE = g.iv_size; - FAPI_ERR("Inconsistent mirrored group content"); - FAPI_SET_HWP_ERROR(rc, - RC_OPT_MEMMAP_MIRROR_GROUP_ERR); - break; - } - iv_m_groups.push_back(g); - } - } - if (!rc.ok()) - { - break; - } - - // dump configuration for non-mirrored groups - for (uint8_t i = 0; i < iv_nm_groups.size(); i++) - { - iv_nm_groups[i].dumpGroup(); - } - // link mirrored group with their non-mirrored partner - for (uint8_t i = 0; i < iv_m_groups.size(); i++) - { - // loop through all non-mirrored groups - // until a match is found - bool match = false; - for (uint8_t j = 0; (j < iv_nm_groups.size()) && (!match); j++) - { - // sizes match? - match = ((iv_m_groups[i].iv_group_id == - iv_nm_groups[j].iv_group_id) && - (iv_m_groups[i].iv_size == - (iv_nm_groups[j].iv_size / 2))); - if (match) - { - // set MCS unit parameters for mirrored group - for (uint8_t k = 0; k < OPT_MEMMAP_MAX_NM_REGIONS; k++) - { - iv_m_groups[i].iv_mcs_member_ids[k] = - iv_nm_groups[j].iv_mcs_member_ids[k]; - } - iv_m_groups[i].iv_group_size = - iv_nm_groups[j].iv_group_size; - iv_m_groups[i].iv_size_per_mcs = - iv_m_groups[i].iv_size / - iv_m_groups[i].iv_group_size; - - // link groups - iv_m_groups[i].iv_partner_group_id = iv_nm_groups[j].iv_group_id; - iv_nm_groups[j].iv_partner_group_id = iv_m_groups[i].iv_group_id; - } - } - // valid mirrored group, but couldn't find non-mirrored partner - if (!match) - { - const uint8_t& GROUP = i; - FAPI_ERR("Unable to find non-mirrored group partner for mirrored group!"); - FAPI_SET_HWP_ERROR(rc, RC_OPT_MEMMAP_GROUP_PARTNER_ERR); - break; - } - // dump configuration for mirrored group - iv_m_groups[i].dumpGroup(); - } - if (!rc.ok()) - { - break; - } - - // compress/re-stack groups for the selective mirror configuration - if (iv_mirror_policy == - ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_SELECTIVE) - { - for (uint8_t i = 0; i < iv_nm_groups.size(); i++) - { - // only multi-member groups (with a mirrrored partner) will - // change in size - if ((iv_nm_groups[i].iv_group_size != 1) && - (iv_nm_groups[i].iv_partner_group_id != 0xFF)) - { - iv_nm_groups[i].halveSize(); - for (uint8_t j = 0; j < iv_m_groups.size(); j++) - { - if (iv_nm_groups[i].iv_partner_group_id == - iv_m_groups[j].iv_group_id) - { - iv_m_groups[j].halveSize(); - } - } - } - } - - // realign each group to origin - for (uint8_t i = 0; i < iv_nm_groups.size(); i++) - { - iv_nm_groups[i].decBase(iv_nm_groups[i].iv_base); - } - for (uint8_t i = 0; i < iv_m_groups.size(); i++) - { - iv_m_groups[i].decBase(iv_m_groups[i].iv_base); - } - - // re-stack set of groups, largest->smallest - uint64_t l_nm_group_base = OPT_MEMMAP_BASE_ORIGIN; - std::sort(iv_nm_groups.begin(), iv_nm_groups.end()); - for (uint8_t i = iv_nm_groups.size(); i != 0; --i) - { - iv_nm_groups[i-1].incBase(l_nm_group_base); - l_nm_group_base += iv_nm_groups[i-1].iv_size; - } - - uint64_t l_m_group_base = OPT_MEMMAP_BASE_ORIGIN; - std::sort(iv_m_groups.begin(), iv_m_groups.end()); - for (uint8_t i = iv_m_groups.size(); i != 0; --i) - { - iv_m_groups[i-1].incBase(l_m_group_base); - l_m_group_base += iv_m_groups[i-1].iv_size; + MemRegion r(MemRegion::m, l_m_bases[i], l_m_sizes[i]); + iv_m_regions.push_back(r); } } // sort regions for effective size calculations - std::sort(iv_nm_groups.begin(), iv_nm_groups.end()); - std::sort(iv_m_groups.begin(), iv_m_groups.end()); + std::sort(iv_nm_regions.begin(), iv_nm_regions.end()); + std::sort(iv_m_regions.begin(), iv_m_regions.end()); // compute effective size of chip address space // this is simply the end address of the last region in // each stack (rounded up to a power of 2) - if (iv_nm_groups.size() != 0) + if (iv_nm_regions.size() != 0) { - iv_nm_eff_size = iv_nm_groups[iv_nm_groups.size()-1].iv_base; - iv_nm_eff_size += iv_nm_groups[iv_nm_groups.size()-1].iv_size; + if (iv_nm_base != iv_nm_regions[0].iv_base) + { + const uint64_t& ADDR = iv_nm_base; + FAPI_ERR("Unexpected value returned for ATTR_PROC_MEM_BASE (=%016llX)", + iv_nm_base); + FAPI_SET_HWP_ERROR(rc, RC_OPT_MEMMAP_MEM_BASE_ERR); + break; + } + + iv_nm_eff_size = iv_nm_regions[iv_nm_regions.size()-1].iv_base - + iv_nm_regions[0].iv_base; + iv_nm_eff_size += iv_nm_regions[iv_nm_regions.size()-1].iv_size; iv_nm_eff_size = PowerOf2Roundedup(iv_nm_eff_size); } else @@ -681,10 +396,20 @@ public: } FAPI_INF(" nm_eff_size = %016llX", iv_nm_eff_size); - if (iv_m_groups.size() != 0) + if (iv_m_regions.size() != 0) { - iv_m_eff_size = iv_m_groups[iv_m_groups.size()-1].iv_base; - iv_m_eff_size += iv_m_groups[iv_m_groups.size()-1].iv_size; + if (iv_m_base != iv_m_regions[0].iv_base) + { + const uint64_t& ADDR = iv_m_base; + FAPI_ERR("Unexpected value returned for ATTR_PROC_MIRROR_BASE (=%016llX)", + iv_m_base); + FAPI_SET_HWP_ERROR(rc, RC_OPT_MEMMAP_MIRROR_BASE_ERR); + break; + } + + iv_m_eff_size = iv_m_regions[iv_m_regions.size()-1].iv_base - + iv_m_regions[0].iv_base; + iv_m_eff_size += iv_m_regions[iv_m_regions.size()-1].iv_size; iv_m_eff_size = PowerOf2Roundedup(iv_m_eff_size); } else @@ -693,239 +418,30 @@ public: } FAPI_INF(" m_eff_size = %016llX", iv_m_eff_size); - // retrieve request for HTM/OCC address space - rc = FAPI_ATTR_GET(ATTR_PROC_HTM_BAR_SIZE, - iv_target, - iv_alloc_size[PROC_CHIP_MEMMAP_HTM_ALLOC_INDEX]); - if (!rc.ok()) - { - FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_HTM_BAR_SIZE)"); - break; - } - - rc = FAPI_ATTR_GET(ATTR_PROC_OCC_SANDBOX_SIZE, - iv_target, - iv_alloc_size[PROC_CHIP_MEMMAP_OCC_ALLOC_INDEX]); - if (!rc.ok()) - { - FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_OCC_SANDBOX_SIZE)"); - break; - } } while(0); return rc; } // establish new non-mirrored base address for this chip - // and adjust all groups to track void setNMBase(const uint64_t& base) { iv_nm_base = base; - for (uint8_t i = 0; i < iv_nm_groups.size(); ++i) - { - iv_nm_groups[i].incBase(base); - } } // establish new mirrored base address for this chip - // and adjust all groups to track void setMBase(const uint64_t& base) { iv_m_base = base; - for (uint8_t i = 0; i < iv_m_groups.size(); ++i) - { - iv_m_groups[i].incBase(base); - } } - // allocate HTM/OCC memory requests for this chip - ReturnCode allocate() - { - ReturnCode rc; - - // groups have already been sorted for stacking - // build ordered list of groups to consider in service of - // allocation requests, based on mirroring mode - std::vector<MemGroup*> alloc_groups; - - do - { - if (iv_mirror_policy == - ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_SELECTIVE) - { - // mirrored groups occupy highest address space, - // then non-mirrored, all are independent - alloc_groups.resize(iv_m_groups.size()+ - iv_nm_groups.size()); - for (uint8_t i = 0; i < iv_m_groups.size(); i++) - { - alloc_groups[iv_m_groups.size()-1-i] = &(iv_m_groups[i]); - } - for (uint8_t i = 0; i < iv_nm_groups.size(); i++) - { - alloc_groups[iv_m_groups.size()+iv_nm_groups.size()-1-i] = &(iv_nm_groups[i]); - } - } - else if (iv_mirror_policy == - ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_FLIPPED) - { - // perform allocation in mirrored space, - // adjust non-mirrored partner group - alloc_groups.resize(iv_m_groups.size()); - for (uint8_t i = 0; i < iv_m_groups.size(); i++) - { - alloc_groups[iv_m_groups.size()-1-i] = &(iv_m_groups[i]); - } - } - else - { - // perform allocation in non-mirrored space, - // adjust mirrored partner group - alloc_groups.resize(iv_nm_groups.size()); - for (uint8_t i = 0; i < iv_nm_groups.size(); i++) - { - alloc_groups[iv_nm_groups.size()-1-i] = &(iv_nm_groups[i]); - } - } - - // perform allocations - for (uint8_t r = 0; - (r < PROC_CHIP_MEMMAP_NUM_ALLOCATIONS) && rc.ok(); - r++) - { - uint64_t alloc_size_req = iv_alloc_size[r]; - iv_alloc_base[r] = 0; - - if (alloc_size_req != 0) - { - bool alloc_done = false; - for (uint8_t i = 0; - (i < alloc_groups.size()) && !alloc_done; - i++) - { - FAPI_DBG("Searching group %d for allocation %d (remaining size: %016llX)", - i, r, alloc_size_req); - // allocate from primary group - alloc_done = alloc_groups[i]->allocate(alloc_size_req); - // take allocation from partner group as well - if (iv_mirror_policy == - ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_FLIPPED) - { - FAPI_DBG("Registering allocation with partner non-mirrored group"); - for (uint8_t j = 0; j < iv_nm_groups.size(); j++) - { - if (alloc_groups[i]->iv_partner_group_id == - iv_nm_groups[j].iv_group_id) - { - (void) iv_nm_groups[j].allocate( - alloc_size_req * 2); - } - } - } - else if (iv_mirror_policy == - ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL) - { - if (alloc_groups[i]->iv_partner_group_id != 0xFF) - { - FAPI_DBG("Registering allocation with partner mirrored group"); - for (uint8_t j = 0; j < iv_m_groups.size(); j++) - { - if (alloc_groups[i]->iv_partner_group_id == - iv_m_groups[j].iv_group_id) - { - (void) iv_m_groups[j].allocate( - alloc_size_req / 2); - } - } - } - } - // if allocation is not completely satisfied, compute - // size request for next iteration - if (!alloc_done) - { - alloc_size_req -= alloc_groups[i]->iv_size_exposed; - } - else - { - iv_alloc_base[r] = alloc_groups[i]->iv_base + - alloc_groups[i]->iv_size_exposed; - } - } - if (!alloc_done) - { - const uint8_t& ALLOC_INDEX = r; - FAPI_ERR("Unable to satisfy %s memory request, size requested exceeds available memory!", - (r == 0)?("HTM"):("OCC")); - FAPI_SET_HWP_ERROR(rc, RC_OPT_MEMMAP_ALLOC_ERR); - break; - } - } - } - } while(0); - - return rc; - } - - // flush group state back to attributes + // flush state back to attributes ReturnCode flushAttributes() { ReturnCode rc; - uint64_t l_mem_bases[OPT_MEMMAP_MAX_NM_REGIONS]; - uint64_t l_mem_sizes[OPT_MEMMAP_MAX_NM_REGIONS]; - uint64_t l_mirror_bases[OPT_MEMMAP_MAX_M_REGIONS]; - uint64_t l_mirror_sizes[OPT_MEMMAP_MAX_M_REGIONS]; - uint32_t l_mss_mcs_group_32[OPT_MEMMAP_GROUP_32_DIM1][OPT_MEMMAP_GROUP_32_DIM2]; do { - // init attribute arrays - for (uint8_t i = 0; i < OPT_MEMMAP_MAX_NM_REGIONS; i++) - { - l_mem_bases[i] = 0; - l_mem_sizes[i] = 0; - } - for (uint8_t i = 0; i < OPT_MEMMAP_MAX_M_REGIONS ; i++) - { - l_mirror_bases[i] = 0; - l_mirror_sizes[i] = 0; - } - for (uint8_t i = 0; i < OPT_MEMMAP_GROUP_32_DIM1; i++) - { - - for (uint8_t j = OPT_MEMMAP_GROUP_32_MCS_SIZE_INDEX; - j <= OPT_MEMMAP_GROUP_32_BASE_INDEX; - j++) - { - l_mss_mcs_group_32[i][j] = 0; - } - for (uint8_t j = OPT_MEMMAP_GROUP_32_MEMBERS_START_INDEX; - j <= OPT_MEMMAP_GROUP_32_MEMBERS_END_INDEX; - j++) - { - l_mss_mcs_group_32[i][j] = 0xFF; - } - for (uint8_t j = OPT_MEMMAP_GROUP_32_ALT_VALID_INDEX; - j <= OPT_MEMMAP_GROUP_32_LARGEST_MBA_INDEX; - j++) - { - l_mss_mcs_group_32[i][j] = 0; - } - } - - // flush attribute data for each group - for (uint8_t i = 0; i < iv_nm_groups.size(); i++) - { - iv_nm_groups[i].flushAttributes(l_mem_bases, - l_mem_sizes, - l_mss_mcs_group_32); - } - for (uint8_t i = 0; i < iv_m_groups.size(); i++) - { - iv_m_groups[i].flushAttributes(l_mirror_bases, - l_mirror_sizes, - l_mss_mcs_group_32); - } - // set base addresses rc = FAPI_ATTR_SET(ATTR_PROC_MEM_BASE, iv_target, @@ -945,74 +461,7 @@ public: break; } - // set non-mirrored region attributes - rc = FAPI_ATTR_SET(ATTR_PROC_MEM_BASES, - iv_target, - l_mem_bases); - if (!rc.ok()) - { - FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_PROC_MEM_BASES)"); - break; - } - - rc = FAPI_ATTR_SET(ATTR_PROC_MEM_SIZES, - iv_target, - l_mem_sizes); - if (!rc.ok()) - { - FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_PROC_MEM_BASES)"); - break; - } - - // set mirrored region attributes - rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_BASES, - iv_target, - l_mirror_bases); - if (!rc.ok()) - { - FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_PROC_MIRROR_BASES)"); - break; - } - - rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_SIZES, - iv_target, - l_mirror_sizes); - if (!rc.ok()) - { - FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_PROC_MIRROR_BASES)"); - break; - } - - // set group definition attributes - rc = FAPI_ATTR_SET(ATTR_MSS_MCS_GROUP_32, - iv_target, - l_mss_mcs_group_32); - if (!rc.ok()) - { - FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_MSS_MCS_GROUP_32)"); - break; - } - - // set HTM/OCC allocation attributes - rc = FAPI_ATTR_SET(ATTR_PROC_HTM_BAR_BASE_ADDR, - iv_target, - iv_alloc_base[PROC_CHIP_MEMMAP_HTM_ALLOC_INDEX]); - if (!rc.ok()) - { - FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_PROC_HTM_BAR_BASE_ADDR)"); - break; - } - - rc = FAPI_ATTR_SET(ATTR_PROC_OCC_SANDBOX_BASE_ADDR, - iv_target, - iv_alloc_base[PROC_CHIP_MEMMAP_OCC_ALLOC_INDEX]); - if (!rc.ok()) - { - FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_PROC_OCC_SANDBOX_BASE_ADDR)"); - break; - } } while(0); - return rc; } }; @@ -1049,7 +498,28 @@ ReturnCode opt_memmap(std::vector<fapi::Target> & i_procs, bool i_init) l_iter != i_procs.end(); ++l_iter) { - uint64_t mem_base = OPT_MEMMAP_BASE_ORIGIN; + uint64_t mem_base; + uint64_t mirror_base; + + if (l_mirror_policy == + ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL) + { + mem_base = OPT_MEMMAP_BASE_ORIGIN; + mirror_base = OPT_MEMMAP_OFFSET_ORIGIN; + } + else if (l_mirror_policy == + ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_FLIPPED) + { + mem_base = OPT_MEMMAP_OFFSET_ORIGIN; + mirror_base = OPT_MEMMAP_BASE_ORIGIN; + } + else if (l_mirror_policy == + ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_SELECTIVE) + { + mem_base = OPT_MEMMAP_BASE_ORIGIN; + mirror_base = OPT_MEMMAP_SELECTIVE_ORIGIN; + } + rc = FAPI_ATTR_SET(ATTR_PROC_MEM_BASE, &(*l_iter), mem_base); @@ -1059,7 +529,6 @@ ReturnCode opt_memmap(std::vector<fapi::Target> & i_procs, bool i_init) break; } - uint64_t mirror_base = OPT_MEMMAP_OFFSET_ORIGIN; rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_BASE, &(*l_iter), mirror_base); @@ -1075,7 +544,7 @@ ReturnCode opt_memmap(std::vector<fapi::Target> & i_procs, bool i_init) } } // second pass of execution - // reorder chips based on their effective size + // reorder chips based on their effective stackable size else { // loop across all chips in system, consume results of @@ -1102,8 +571,8 @@ ReturnCode opt_memmap(std::vector<fapi::Target> & i_procs, bool i_init) std::sort(l_system_memmap.begin(), l_system_memmap.end()); // establish base for alignment of mirrored/non-mirrored regions - uint64_t l_m_base_curr; - uint64_t l_nm_base_curr; + uint64_t l_m_base_curr = 0; + uint64_t l_nm_base_curr = 0; if (l_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL) { @@ -1118,17 +587,18 @@ ReturnCode opt_memmap(std::vector<fapi::Target> & i_procs, bool i_init) l_nm_base_curr = OPT_MEMMAP_OFFSET_ORIGIN; l_m_base_curr = OPT_MEMMAP_BASE_ORIGIN; } - else + else if (l_mirror_policy == + ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_SELECTIVE) { - // start at zero, mirrored region will stack on top - // of non-mirrored address space, handle offset in loop l_nm_base_curr = OPT_MEMMAP_BASE_ORIGIN; - l_m_base_curr = OPT_MEMMAP_BASE_ORIGIN; + l_m_base_curr = OPT_MEMMAP_SELECTIVE_ORIGIN; } // walk through chips, from largest->smallest effective size & // assign base addresses for each group - for (uint8_t i = l_system_memmap.size(); i != 0; --i) + for (uint8_t i = l_system_memmap.size(); + i != 0; + --i) { FAPI_DBG("Stacking chip n%d:p%d (eff nm size = %lld GB, eff m size = %lld GB)...", l_system_memmap[i-1].iv_node_id, @@ -1160,20 +630,11 @@ ReturnCode opt_memmap(std::vector<fapi::Target> & i_procs, bool i_init) l_nm_base_curr += l_system_memmap[i-1].iv_nm_eff_size; l_m_base_curr += l_system_memmap[i-1].iv_m_eff_size; } - else - { - l_nm_base_curr += PowerOf2Roundedup( - l_system_memmap[i-1].iv_nm_eff_size + - l_system_memmap[i-1].iv_m_eff_size); - l_m_base_curr = l_nm_base_curr; - } - - // allocate HTM/OCC memory requests for this chip - rc = l_system_memmap[i-1].allocate(); - if (!rc.ok()) + else if (l_mirror_policy == + ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_SELECTIVE) { - FAPI_ERR("Error from allocate"); - break; + l_nm_base_curr += l_system_memmap[i-1].iv_nm_eff_size; + l_m_base_curr += l_system_memmap[i-1].iv_nm_eff_size / 2; } // flush attributes for this chip diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.H index 35d0790e8..2be7472ab 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.H +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.H @@ -20,15 +20,34 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: opt_memmap.H,v 1.4 2013/05/06 15:14:25 jmcgill Exp $ +// $Id: opt_memmap.H,v 1.7 2013/08/12 16:40:18 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/opt_memmap.H,v $ */ //------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : opt_memmap.H +// *! DESCRIPTION : Layout non-mirrored/mirrored address map (FAPI) +// *! +// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com +// *! BACKUP NAME : Van Lee Email: vanlee@us.ibm.com +// *! +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ // CHANGE HISTORY: //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.7 | jmcgill | 07/10/13| Update to match new attributes, selective +// | | | aligment policy changes +// 1.6 | jmcgill | 05/24/13| Correct index name +// 1.5 | jmcgill | 05/23/13| Address FW review issues // 1.4 | jmcgill | 04/28/13| Shift constant definitions // 1.3 | vanlee | 02/20/13| Added i_init parameter // 1.2 | vanlee | 01/04/13| Added version string @@ -53,38 +72,14 @@ const uint64_t OPT_MEMMAP_GB = 0x0000000040000000ULL; // default origin for non-mirrored/mirrored address regions -const uint64_t OPT_MEMMAP_BASE_ORIGIN = 0; // 0 -const uint64_t OPT_MEMMAP_OFFSET_ORIGIN = 0x0002000000000000LL; // 512TB +const uint64_t OPT_MEMMAP_BASE_ORIGIN = 0; // 0 +const uint64_t OPT_MEMMAP_OFFSET_ORIGIN = 0x0002000000000000LL; // 512TB +const uint64_t OPT_MEMMAP_SELECTIVE_ORIGIN = 0x0000080000000000LL; // 8TB // maximum non-mirrored/mirrored regions supported const uint8_t OPT_MEMMAP_MAX_NM_REGIONS = 8; const uint8_t OPT_MEMMAP_MAX_M_REGIONS = 4; -// attribute index constants -// first array dimension (group ID) -const uint8_t OPT_MEMMAP_GROUP_32_NM_START_INDEX = 0; -const uint8_t OPT_MEMMAP_GROUP_32_NM_END_INDEX = 7; -const uint8_t OPT_MEMMAP_GROUP_32_M_START_INDEX = 8; -const uint8_t OPT_MEMMAP_GROUP_32_M_END_INDEX = 15; - -const uint8_t OPT_MEMMAP_GROUP_32_DIM1 = (OPT_MEMMAP_GROUP_32_M_END_INDEX- - OPT_MEMMAP_GROUP_32_NM_START_INDEX)+1; - -// second array dimension (group definition) -const uint8_t OPT_MEMMAP_GROUP_32_MCS_SIZE_INDEX = 0; -const uint8_t OPT_MEMMAP_GROUP_32_MCS_IN_GROUP_INDEX = 1; -const uint8_t OPT_MEMMAP_GROUP_32_SIZE_INDEX = 2; -const uint8_t OPT_MEMMAP_GROUP_32_BASE_INDEX = 3; -const uint8_t OPT_MEMMAP_GROUP_32_MEMBERS_START_INDEX = 4; -const uint8_t OPT_MEMMAP_GROUP_32_MEMBERS_END_INDEX = 11; -const uint8_t OPT_MEMMAP_GROUP_32_ALT_VALID_INDEX = 12; -const uint8_t OPT_MEMMAP_GROUP_32_ALT_SIZE_INDEX = 13; -const uint8_t OPT_MEMMAP_GROUP_32_ALT_BASE_INDEX = 14; -const uint8_t OPT_MEMMAP_GROUP_32_LARGEST_MBA_INDEX = 15; - -const uint8_t OPT_MEMMAP_GROUP_32_DIM2 = (OPT_MEMMAP_GROUP_32_LARGEST_MBA_INDEX- - OPT_MEMMAP_GROUP_32_MCS_SIZE_INDEX)+1; - //------------------------------------------------------------------------------ // Structure definitions diff --git a/src/usr/hwpf/hwp/proc_chip_ec_feature.xml b/src/usr/hwpf/hwp/proc_chip_ec_feature.xml index 03d35104e..650ca56af 100644 --- a/src/usr/hwpf/hwp/proc_chip_ec_feature.xml +++ b/src/usr/hwpf/hwp/proc_chip_ec_feature.xml @@ -20,7 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_chip_ec_feature.xml,v 1.22 2013/07/16 21:41:12 jmcgill Exp $ --> +<!-- $Id: proc_chip_ec_feature.xml,v 1.23 2013/08/28 21:15:17 jmcgill Exp $ --> <!-- Defines the attributes that are based on EC level --> <attributes> <attribute> @@ -480,4 +480,30 @@ </chip> </chipEcFeature> </attribute> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + True if: + Chip contains MCD hang recovery bug (HW252763) + Murano EC less than 0x20 + Venice EC less than 0x20 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_MURANO</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_VENICE</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> </attributes> diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index cc2ff0815..281858305 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -13157,4 +13157,86 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </hwpfToHbAttrMap> </attribute> +<attribute> + <id>PROC_MIRROR_BASES_ACK</id> + <description>Mirrored memory base addresses + creator: mss_setup_bars + consumer: consumer: opt_mem_map + Mem opt map uses this for the bases of the mirror ranges. + (max number based on Venice design) + </description> + <simpleType> + <uint64_t></uint64_t> + <array>4</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_MIRROR_BASES_ACK</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_MIRROR_SIZES_ACK</id> + <description>Size of mirrored memory region up to a power of 2 + creator: mss_setup_bars + consumer: opt_mem_map + Mem opt map uses this to stack mirror ranges. The real amount of memory behind the mirror group maybe less than the number reported here if there are memory holes + </description> + <simpleType> + <uint64_t></uint64_t> + <array>4</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_MIRROR_SIZES_ACK</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_MEM_BASES_ACK</id> + <description>Non-mirrored memory base addresses + creator: mss_setup_bars + consumer: opt_mem_map + Mem opt map uses this for the bases of the non-mirror ranges. + (max number based on Venice design) + </description> + <simpleType> + <uint64_t></uint64_t> + <array>8</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_MEM_BASES_ACK</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PROC_MEM_SIZES_ACK</id> + <description>Size of non-mirrored memory regions up to a power of 2 + creator: mss_setup_bars + consumer: opt_mem_map + Mem opt map uses this to stack mirror ranges. The real amount of memory behind the mirror group maybe less than the number reported here if there are memory holes + </description> + <simpleType> + <uint64_t></uint64_t> + <array>8</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_MEM_SIZES_ACK</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + </attributes> diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index 911de4dbb..f1dd2083b 100644 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -376,6 +376,13 @@ <!-- TODO RTC 62291. This next attribute moves to hostboot only with this story --> <attribute><id>PROC_SECURITY_SETUP_VECTOR</id></attribute> + + <attribute><id>PROC_MIRROR_BASES_ACK</id></attribute> + <attribute><id>PROC_MIRROR_SIZES_ACK</id></attribute> + <attribute><id>PROC_MEM_BASES_ACK</id></attribute> + <attribute><id>PROC_MEM_SIZES_ACK</id></attribute> + + </targetType> <targetType> |
