diff options
Diffstat (limited to 'src/usr')
-rw-r--r-- | src/usr/ibscom/ibscom.C | 398 | ||||
-rw-r--r-- | src/usr/ibscom/ibscom.H | 75 | ||||
-rw-r--r-- | src/usr/ibscom/makefile | 30 | ||||
-rw-r--r-- | src/usr/ibscom/test/ibscomtest.H | 174 | ||||
-rw-r--r-- | src/usr/ibscom/test/makefile | 28 | ||||
-rw-r--r-- | src/usr/initservice/extinitsvc/extinitsvctasks.H | 12 | ||||
-rw-r--r-- | src/usr/makefile | 2 | ||||
-rw-r--r-- | src/usr/scom/scom.C | 69 | ||||
-rw-r--r-- | src/usr/targeting/common/xmltohb/attribute_types.xml | 19 | ||||
-rw-r--r-- | src/usr/targeting/common/xmltohb/simics_MURANO.system.xml | 64 | ||||
-rw-r--r-- | src/usr/targeting/common/xmltohb/simics_VENICE.system.xml | 256 | ||||
-rw-r--r-- | src/usr/targeting/common/xmltohb/target_types.xml | 5 | ||||
-rwxr-xr-x | src/usr/targeting/xmltohb/genHwsvMrwXml.pl | 14 |
13 files changed, 1114 insertions, 32 deletions
diff --git a/src/usr/ibscom/ibscom.C b/src/usr/ibscom/ibscom.C new file mode 100644 index 000000000..bdde8f4fb --- /dev/null +++ b/src/usr/ibscom/ibscom.C @@ -0,0 +1,398 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/ibscom/ibscom.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/*****************************************************************************/ +// I n c l u d e s +/*****************************************************************************/ +#include <sys/mmio.h> +#include <sys/task.h> +#include <sys/sync.h> +#include <sys/misc.h> +#include <string.h> +#include <devicefw/driverif.H> +#include <trace/interface.H> +#include <errl/errlentry.H> +#include <errl/errlmanager.H> +#include <targeting/common/targetservice.H> +#include <ibscom/ibscomreasoncodes.H> +#include "ibscom.H" +#include <assert.h> +#include <limits.h> + +// Trace definition +trace_desc_t* g_trac_ibscom = NULL; +TRAC_INIT(&g_trac_ibscom, "IBSCOM", KILOBYTE); + +using namespace ERRORLOG; +using namespace TARGETING; + +namespace IBSCOM +{ + + +// Register XSCcom access functions to DD framework +DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD, + DeviceFW::IBSCOM, + TYPE_MEMBUF, + ibscomPerformOp); + + + + +/** + * @brief Internal routine that verifies the validity of input parameters + * for an inband scom access. + * + * @param[in] i_opType Operation type, see DeviceFW::OperationType + * in driverif.H + * @param[in] i_target inband scom target + * @param[in] i_buffer Read: Pointer to output data storage + * Write: Pointer to input data storage + * @param[in] i_buflen Input: size of io_buffer (in bytes) + * @param[in] i_addr Address being accessed (Used for FFDC) + * @return errlHndl_t + */ +errlHndl_t ibscomOpSanityCheck(const DeviceFW::OperationType i_opType, + const Target* i_target, + const void* i_buffer, + const size_t& i_buflen, + const uint64_t i_addr) +{ + errlHndl_t l_err = NULL; + TRACDCOMP(g_trac_ibscom, INFO_MRK + ">>ibscomOpSanityCheck: Entering Function"); + + do + { + // Verify data buffer + if ( (i_buflen < IBSCOM_BUFFER_SIZE) || + (i_buffer == NULL) ) + { + TRACFCOMP(g_trac_ibscom, ERR_MRK + "ibscomOpSanityCheck: Invalid buffer. i_buflen=0x%X", + i_buflen); + /*@ + * @errortype + * @moduleid IBSCOM_SANITY_CHECK + * @reasoncode IBSCOM_INVALID_DATA_BUFFER + * @userdata1 Buffer size + * @userdata2 Inband Scom address + * @devdesc Inband buffer size < 8 bytes or NULL + * data buffer + */ + l_err = new ErrlEntry(ERRL_SEV_UNRECOVERABLE, + IBSCOM_SANITY_CHECK, + IBSCOM_INVALID_DATA_BUFFER, + i_buflen, + i_addr); + break; + } + + // Verify OP type + if ( (i_opType != DeviceFW::READ) && + (i_opType != DeviceFW::WRITE) ) + { + TRACFCOMP(g_trac_ibscom, ERR_MRK + "ibscomOpSanityCheck: Invalid opType. i_opType=0x%X", + i_opType); + /*@ + * @errortype + * @moduleid IBSCOM_SANITY_CHECK + * @reasoncode IBSCOM_INVALID_OP_TYPE + * @userdata1 Operation type + * @userdata2 inband scom address + * @devdesc inband scom invalid operation type + */ + l_err = new ErrlEntry(ERRL_SEV_UNRECOVERABLE, + IBSCOM_SANITY_CHECK, + IBSCOM_INVALID_OP_TYPE, + i_opType, + i_addr); + break; + } + + + } while(0); + + return l_err; +} + +/** + * @brief Get the virtual address of the input target + * for an inband scom access. + * + * Logic: + * If never inband scom to this chip: + * Call mmio_dev_map() to get virtual addr for this slave proc + * Save virtual addr used to this chip's attribute + * Else + * Use virtual address stored in this chip's attributes. + * End if + * + * @param[in] i_target inband scom target + * @param[out] o_virtAddr Target's virtual address + * + * @return errlHndl_t + */ +errlHndl_t getTargetVirtualAddress(Target* i_target, + uint64_t*& o_virtAddr) +{ + errlHndl_t l_err = NULL; + o_virtAddr = NULL; + IBScomBase_t l_IBScomBaseAddr = 0; + + do + { + // Get the virtual addr value of the chip from attribute + o_virtAddr = reinterpret_cast<uint64_t*> + (i_target->getAttr<ATTR_IBSCOM_VIRTUAL_ADDR>()); + + // If the virtual address equals NULL(default) then this is the + // first IBSCOM to this target so we need to allocate + // the virtual address and save it in the xscom address attribute. + if (o_virtAddr == NULL) + { + + TRACDCOMP(g_trac_ibscom, INFO_MRK + "getTargetVirtualAddress: Need to compute virtual address for Centaur"); + + //Get MMIO Offset from parent MCS attribute. + + uint64_t mcsUnit = 0; + + //Get the parent MCS + Target* parentMCS = NULL; + + PredicateCTM l_mcs(CLASS_UNIT, + TYPE_MCS, + MODEL_NA); + + TargetHandleList mcs_list; + targetService(). + getAssociated(mcs_list, + i_target, + TargetService::PARENT_BY_AFFINITY, + TargetService::ALL, + &l_mcs); + + if( mcs_list.size() != 1 ) + { + TRACFCOMP(g_trac_ibscom, ERR_MRK + "getTargetVirtualAddress: mcs_list size is zero"); + /*@ + * @errortype + * @moduleid IBSCOM_GET_TARG_VIRT_ADDR + * @reasoncode IBSCOM_INVALID_CONFIG + * @userdata1[0:31] HUID of Centaur Target + * @userdata2 Not Used + * @devdesc System configuration does not have a Parent MCS + * for the current centaur. + */ + l_err = + new ErrlEntry(ERRL_SEV_UNRECOVERABLE, + IBSCOM_GET_TARG_VIRT_ADDR, + IBSCOM_INVALID_CONFIG, + TWO_UINT32_TO_UINT64( + get_huid(i_target), + 0), + 0); + + break; + } + parentMCS = *(mcs_list.begin()); + + l_IBScomBaseAddr = + parentMCS->getAttr<ATTR_IBSCOM_MCS_BASE_ADDR>(); + + TRACFCOMP(g_trac_ibscom, INFO_MRK + "getTargetVirtualAddress: From Attribute query l_IBScomBaseAddr=0x%llX, i_target=0x%.8x", + l_IBScomBaseAddr, + i_target->getAttr<ATTR_HUID>()); + + //TODO: Remove this workaround when cen_set_inband_addr procedure + // is delivered + /* -- Start Workaround -> Remove with RTC: 52898 -- */ + + //Since the cen_set_inband_addr procedure has not been delivered, + // setting the bar on demand here so inband scoms will work + const uint64_t barAddrs[] = { + 0x02011802, /* MC0.MCS0.LEFT.LEFT.MCFGPRQ */ + 0x02011882, /* MC0.MCS1.LEFT.LEFT.MCFGPRQ */ + 0x02011902, /* MC1.MCS0.LEFT.LEFT.MCFGPRQ */ + 0x02011982, /* MC1.MCS1.LEFT.LEFT.MCFGPRQ */ + 0x02011C02, /* MC2.MCS0.LEFT.LEFT.MCFGPRQ */ + 0x02011C82, /* MC2.MCS1.LEFT.LEFT.MCFGPRQ */ + 0x02011D02, /* MC3.MCS0.LEFT.LEFT.MCFGPRQ */ + 0x02011D82, /* MC3.MCS1.LEFT.LEFT.MCFGPRQ */ + }; + + //Get the parent processor + Target* parentProcChip = NULL; + + PredicateCTM l_proc(CLASS_CHIP, + TYPE_PROC, + MODEL_NA); + + TargetHandleList proc_list; + targetService(). + getAssociated(proc_list, + i_target, + TargetService::PARENT_BY_AFFINITY, + TargetService::ALL, + &l_proc); + + if( proc_list.size() != 1 ) + { + //Since this code is temporary, just assert + TRACFCOMP(g_trac_ibscom, ERR_MRK + "getTargetVirtualAddress: mcs_list size is zero"); + crit_assert(0); + } + parentProcChip = *(proc_list.begin()); + + mcsUnit = + parentMCS->getAttr<ATTR_CHIP_UNIT>(); + + TRACDCOMP(g_trac_ibscom, INFO_MRK + "getTargetVirtualAddress: Setting IBSCOM Bar : barAddr=0x%X, l_IBScomBaseAddr=0x%llX", + barAddrs[mcsUnit], l_IBScomBaseAddr ); + + size_t op_size = sizeof(uint64_t); + l_err = deviceOp( DeviceFW::WRITE, + parentProcChip, + &l_IBScomBaseAddr, + op_size, + DEVICE_SCOM_ADDRESS(barAddrs[mcsUnit]) ); + + if( l_err ) + { + TRACFCOMP(g_trac_ibscom, ERR_MRK + "getTargetVirtualAddress: Error programming IBSCOM Bar : barAddr=0x%X, l_IBScomBaseAddr=0x%llX", + barAddrs[mcsUnit], l_IBScomBaseAddr ); + break; + } + /* -- END Workaround -> Remove with RTC: 52898 -- */ + + // Map target's virtual address + //NOTE: mmio_dev_map only supports 32 GB Allocation. Technically, + //hostboot IBSCOM MMIO allocated 64GB, but the SCOM address space + //is small enough that 32 GB is sufficient. + o_virtAddr = static_cast<uint64_t*> + (mmio_dev_map(reinterpret_cast<void*>(l_IBScomBaseAddr), + THIRTYTWO_GB)); + + // Save the virtual address attribute. + i_target->setAttr<ATTR_IBSCOM_VIRTUAL_ADDR> + (reinterpret_cast<uint64_t>(o_virtAddr)); + } + + } while (0); + + TRACDCOMP(g_trac_ibscom, EXIT_MRK + "getTargetVirtualAddress: o_Virtual Base Address = 0x%llX", + o_virtAddr); + + + return l_err; +} + + +/////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////// +errlHndl_t ibscomPerformOp(DeviceFW::OperationType i_opType, + Target* i_target, + void* io_buffer, + size_t& io_buflen, + int64_t i_accessType, + va_list i_args) +{ + errlHndl_t l_err = NULL; + uint64_t l_addr = va_arg(i_args,uint64_t); + + do + { + TRACDCOMP(g_trac_ibscom, INFO_MRK + ">>ibscomPerformOp: Perform op to SCOM Address 0x%X", + l_addr); + + // inband scom operation sanity check + l_err = ibscomOpSanityCheck(i_opType, i_target, io_buffer, + io_buflen, l_addr); + if (l_err) + { + break; + } + // Set to buffer len to 0 until successfully access + io_buflen = 0; + + // Get the target chip's virtual address + uint64_t* l_virtAddr = NULL; + l_err = getTargetVirtualAddress(i_target, l_virtAddr); + + if (l_err) + { + break; + } + + // The dereferencing should handle Cache inhibited internally + // Use local variable and memcpy to avoid unaligned memory access + uint64_t l_data = 0; + + if (i_opType == DeviceFW::READ) + { + //TODO: Check that address isn't greater than allocated 32GB range + // RTC: 47212 + l_data = l_virtAddr[l_addr]; + + memcpy(io_buffer, &l_data, sizeof(l_data)); + TRACDCOMP(g_trac_ibscom, + "ibscomPerformOp: Read data: %.16llx", + l_data); + + } + else + { + TRACDCOMP(g_trac_ibscom, + "ibscomPerformOp: Write data: %.16llx", + l_data); + memcpy(&l_data, io_buffer, sizeof(l_data)); + l_virtAddr[l_addr] = l_data; + } + + // Check for error or done + //TODO - check for errors RTC: 47212 + //assume successful for now + io_buflen = sizeof(uint64_t); + + TRACDCOMP(g_trac_ibscom, + "ibscomPerformOp: OpType 0x%.16llX, SCOM Address 0x%llX, Virtual Address 0x%llX", + static_cast<uint64_t>(i_opType), + l_addr, + &(l_virtAddr[l_addr])); + + } while (0); + + return l_err; +} + +} // end namespace diff --git a/src/usr/ibscom/ibscom.H b/src/usr/ibscom/ibscom.H new file mode 100644 index 000000000..7bb17b9ad --- /dev/null +++ b/src/usr/ibscom/ibscom.H @@ -0,0 +1,75 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/ibscom/ibscom.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __IBSCOM_H +#define __IBSCOM_H + +/** @file ibscom.H + * @brief Provides the interfaces to perform IBSCOM + */ + +#include <stdint.h> + +/** + * @brief Type definition for IBSCOM address + */ +typedef uint64_t IBScomBase_t; + +namespace IBSCOM +{ + +const size_t IBSCOM_BUFFER_SIZE = 8; // 8 bytes + +/** + * @brief Performs an inband scom access operation + * This function performs an inband scom access operation. It follows a + * pre-defined prototype functions in order to be registered with the + * device-driver framework. + * + * @param[in] i_opType Operation type, see DeviceFW::OperationType + * in driverif.H + * @param[in] i_target inband scom target + * @param[in] io_buffer Read: Pointer to output data storage + * Write: Pointer to input data storage + * @param[in] io_buflen Input: size of io_buffer (in bytes) + * Output: + * Read: Size of output data + * Write: Size of data written + * @param[in] i_accessType DeviceFW::AccessType enum (usrif.H) + * @param[in] i_args This is an argument list for DD framework. + * In this function, there's only one argument, + * which is the MMIO inband scom address + * @return errlHndl_t + */ +errlHndl_t ibscomPerformOp(DeviceFW::OperationType i_opType, + TARGETING::Target* i_target, + void* io_buffer, + size_t& io_buflen, + int64_t i_accessType, + va_list i_args); + + + +}; + + +#endif diff --git a/src/usr/ibscom/makefile b/src/usr/ibscom/makefile new file mode 100644 index 000000000..1ece9f652 --- /dev/null +++ b/src/usr/ibscom/makefile @@ -0,0 +1,30 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/ibscom/makefile $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG +ROOTPATH = ../../.. +MODULE = ibscom + +OBJS = ibscom.o + +SUBDIRS = test.d + +include ${ROOTPATH}/config.mk diff --git a/src/usr/ibscom/test/ibscomtest.H b/src/usr/ibscom/test/ibscomtest.H new file mode 100644 index 000000000..189f78049 --- /dev/null +++ b/src/usr/ibscom/test/ibscomtest.H @@ -0,0 +1,174 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/ibscom/test/ibscomtest.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __IBSCOMTEST_H +#define __IBSCOMTEST_H + +/** + * @file ibscomtest.H + * + * @brief Test case for inband scom code +*/ + +#include <cxxtest/TestSuite.H> +#include <errl/errlmanager.H> +#include <errl/errlentry.H> +#include <devicefw/userif.H> +#include <ibscom/ibscomreasoncodes.H> +#include <devicefw/driverif.H> + +extern trace_desc_t* g_trac_ibscom; + +using namespace TARGETING; + + +class IBscomTest: public CxxTest::TestSuite +{ + public: + + /** + * @brief inband scom test #1 + * Write value and read back to verify + */ + void test_IBscom(void) + { + + //TODO Enable and improve test cases RTC: 52900 + return; + + uint64_t fails = 0; + uint64_t total = 0; + errlHndl_t l_err = NULL; + + TARGETING::Target* l_testTarget = NULL; + + // Target: Find a Centaur on the Master processor + TARGETING::Target* l_procTarget = NULL; + TARGETING::targetService().masterProcChipTargetHandle(l_procTarget); + assert(l_procTarget != NULL); + + TARGETING::PredicateCTM l_cent(TARGETING::CLASS_CHIP, + TARGETING::TYPE_MEMBUF, + TARGETING::MODEL_NA); + TARGETING::PredicatePostfixExpr cent_query; + cent_query.push(&l_cent); + + + TARGETING::TargetHandleList centaur_list; + TARGETING::targetService(). + getAssociated(centaur_list, + l_procTarget, + TARGETING::TargetService::CHILD_BY_AFFINITY, + TARGETING::TargetService::ALL, + ¢_query); + + if( centaur_list.size() < 1 ) + { + TS_FAIL( "test_IBscom> ERROR : Unable to find a Centaur chip" ); + return; + } + l_testTarget = *(centaur_list.begin()); + + uint64_t addr = 0x03010E03; + uint64_t orig_data = 0; + uint64_t data = 0x12345678FEEDB0B0; + size_t op_size = sizeof(uint64_t); + + //Save of initial register content + l_err = deviceRead( l_testTarget, + &orig_data, + op_size, + DEVICE_SCOM_ADDRESS(addr) ); + if( l_err ) + { + TRACFCOMP(g_trac_ibscom, + "IBscomTest::test_IBscom> Orig Read: Error from device : addr=0x%X, RC=%X", + addr, l_err->reasonCode() ); + TS_FAIL( "test_IBscom1> ERROR : Unexpected error log from read1" ); + fails++; + errlCommit(l_err,IBSCOM_COMP_ID); + } + + l_err = deviceOp( DeviceFW::WRITE, + l_testTarget, + &data, + op_size, + DEVICE_IBSCOM_ADDRESS(addr) ); + if( l_err ) + { + TRACFCOMP(g_trac_ibscom, + "IBscomTest::test_IBscom> Write: Error from device : addr=0x%X, RC=%X", + addr, l_err->reasonCode() ); + TS_FAIL( "ScomTest::test_IBscom> ERROR : Error log from write1" ); + fails++; + errlCommit(l_err,IBSCOM_COMP_ID); + } + + total++; + + l_err = deviceOp( DeviceFW::READ, + l_testTarget, + &data, + op_size, + DEVICE_IBSCOM_ADDRESS(addr) ); + if( l_err ) + { + TRACFCOMP(g_trac_ibscom, + "IBscomTest::test_IBscom> Read: Error from device : addr=0x%X, RC=%X", + addr, l_err->reasonCode() ); + TS_FAIL( "test_IBscom> ERROR : Error log from read2" ); + fails++; + errlCommit(l_err,IBSCOM_COMP_ID); + } + + total++; + + //Restore original data. + l_err = deviceWrite( l_testTarget, + &orig_data, + op_size, + DEVICE_SCOM_ADDRESS(addr) ); + + if( l_err ) + { + TRACFCOMP(g_trac_ibscom, + "IBscomTest::test_IBscom> Write Orig Data: Error from device : addr=0x%X, RC=%X", + addr, l_err->reasonCode() ); + TS_FAIL( "test_IBscom> ERROR : Error log from write2" ); + fails++; + errlCommit(l_err,IBSCOM_COMP_ID); + } + + + TS_TRACE("test_IBscom runs successfully!"); + TRACFCOMP(g_trac_ibscom, + "IBscomTest::test_IBscom> %d/%d fails", + fails, total ); + + return; + } + + + +}; + +#endif diff --git a/src/usr/ibscom/test/makefile b/src/usr/ibscom/test/makefile new file mode 100644 index 000000000..1a21fa2d3 --- /dev/null +++ b/src/usr/ibscom/test/makefile @@ -0,0 +1,28 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/ibscom/test/makefile $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG +ROOTPATH = ../../../.. + +MODULE = testibscom +TESTS = *.H + +include ${ROOTPATH}/config.mk diff --git a/src/usr/initservice/extinitsvc/extinitsvctasks.H b/src/usr/initservice/extinitsvc/extinitsvctasks.H index 202ddda81..5ff8c308c 100644 --- a/src/usr/initservice/extinitsvc/extinitsvctasks.H +++ b/src/usr/initservice/extinitsvc/extinitsvctasks.H @@ -163,6 +163,18 @@ const TaskInfo g_exttaskinfolist[] = { } }, + /** + * @brief inband scom code library + */ + { + "libibscom.so" , // taskname + NULL, // no pointer to fn + { + INIT_TASK, // task type + EXT_IMAGE, // Extended Module + } + }, + // TODO: Added this in order to successfull init.. Need to remove this and put // the module load and unload from a the istep dispatcher // PW - Is this really TODO? Don't we need the hwas module from errl to do diff --git a/src/usr/makefile b/src/usr/makefile index 191419605..fc4a6f9c6 100644 --- a/src/usr/makefile +++ b/src/usr/makefile @@ -30,6 +30,6 @@ SUBDIRS = example.d trace.d cxxtest.d testcore.d errl.d devicefw.d \ scom.d xscom.d targeting.d initservice.d hwpf.d \ ecmddatabuffer.d pnor.d i2c.d vfs.d fsi.d hwas.d fsiscom.d \ intr.d spd.d pore.d util.d mbox.d diag.d mvpd.d scan.d \ - runtime.d + runtime.d ibscom.d include ${ROOTPATH}/config.mk diff --git a/src/usr/scom/scom.C b/src/usr/scom/scom.C index dae4ee921..3ada9803e 100644 --- a/src/usr/scom/scom.C +++ b/src/usr/scom/scom.C @@ -1,26 +1,25 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/scom/scom.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2011-2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/scom/scom.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2011,2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ /** * @file scom.C * @@ -419,9 +418,17 @@ errlHndl_t doScomOp(DeviceFW::OperationType i_opType, errlHndl_t l_err = NULL; do{ + TARGETING::ScomSwitches scomSetting; + scomSetting.useXscom = true; //Default to Xscom supported. + if(TARGETING::MASTER_PROCESSOR_CHIP_TARGET_SENTINEL != i_target) + { + scomSetting = + i_target->getAttr<TARGETING::ATTR_SCOM_SWITCHES>(); + } + //Always XSCOM the Master Sentinel if((TARGETING::MASTER_PROCESSOR_CHIP_TARGET_SENTINEL == i_target) || - (i_target->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom)) + (scomSetting.useXscom)) { //do XSCOM l_err = deviceOp(i_opType, @@ -431,7 +438,16 @@ errlHndl_t doScomOp(DeviceFW::OperationType i_opType, DEVICE_XSCOM_ADDRESS(i_addr)); break; } - else if(i_target->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom) + else if(scomSetting.useInbandScom) + { //do IBSCOM + l_err = deviceOp(i_opType, + i_target, + io_buffer, + io_buflen, + DEVICE_IBSCOM_ADDRESS(i_addr)); + if( l_err ) { break; } + } + else if(scomSetting.useFsiScom) { //do FSISCOM l_err = deviceOp(i_opType, i_target, @@ -442,8 +458,7 @@ errlHndl_t doScomOp(DeviceFW::OperationType i_opType, } else { - //@todo - add target info to assert trace - assert(0,"SCOM::scomPerformOp> ATTR_SCOM_SWITCHES does not indicate Xscom or FSISCOM is supported"); + assert(0,"SCOM::scomPerformOp> ATTR_SCOM_SWITCHES does not indicate Xscom, Ibscom, or FSISCOM is supported. i_target=0x%.8x", get_huid(i_target)); break; } diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index cd5291fe5..b00bcb7c7 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -668,6 +668,19 @@ </attribute> <attribute> + <id>IBSCOM_VIRTUAL_ADDR</id> + <description>Cached Virtual Address of Inband Scom memory space for this Chip</description> + <simpleType> + <uint64_t> + <default>0</default> + </uint64_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> +</attribute> + +<attribute> <id>FSI_MASTER_CHIP</id> <description>Chip which contains the FSI master logic that drives this slave</description> <nativeType> @@ -4096,15 +4109,15 @@ </attribute> <attribute> - <id>IBSCOM_BASE_ADDR</id> - <description>System Inband Scom base address</description> + <id>IBSCOM_MCS_BASE_ADDR</id> + <description>MCS Inband Scom base address</description> <simpleType> <uint64_t> - <!-- 992TB, XX per proc/centaur? (@todo RTC:34743) --> <default>0x0003E00000000000</default> </uint64_t> </simpleType> <persistency>non-volatile</persistency> + <!-- Link to ATTR_PROC_INBAND_MCFGPRQ_BASE_ADDRESS (@todo RTC:42177) --> <readable/> </attribute> diff --git a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml index 40b269637..e0ab6dea5 100644 --- a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml +++ b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml @@ -662,6 +662,10 @@ <id>CHIP_UNIT</id> <default>4</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E08000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -680,6 +684,10 @@ <id>CHIP_UNIT</id> <default>5</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E0A000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -698,6 +706,10 @@ <id>CHIP_UNIT</id> <default>6</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E0C000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -716,6 +728,10 @@ <id>CHIP_UNIT</id> <default>7</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E0E000000000</default> + </attribute> </targetInstance> <!-- Murano n0p0 PCI units --> @@ -1360,6 +1376,10 @@ <id>CHIP_UNIT</id> <default>4</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E18000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -1378,6 +1398,10 @@ <id>CHIP_UNIT</id> <default>5</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E1A000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -1396,6 +1420,10 @@ <id>CHIP_UNIT</id> <default>6</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E1C000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -1414,6 +1442,10 @@ <id>CHIP_UNIT</id> <default>7</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E1E000000000</default> + </attribute> </targetInstance> <!-- Murano n0p1 PCI units --> @@ -2059,6 +2091,10 @@ <id>CHIP_UNIT</id> <default>4</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E48000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -2077,6 +2113,10 @@ <id>CHIP_UNIT</id> <default>5</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E4A000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -2095,6 +2135,10 @@ <id>CHIP_UNIT</id> <default>6</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E4C000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -2113,6 +2157,10 @@ <id>CHIP_UNIT</id> <default>7</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E4E000000000</default> + </attribute> </targetInstance> <!-- Murano n0p2 PCI units --> @@ -2757,6 +2805,10 @@ <id>CHIP_UNIT</id> <default>4</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E58000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -2775,6 +2827,10 @@ <id>CHIP_UNIT</id> <default>5</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E5A000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -2793,6 +2849,10 @@ <id>CHIP_UNIT</id> <default>6</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E5C000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -2811,6 +2871,10 @@ <id>CHIP_UNIT</id> <default>7</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E5E000000000</default> + </attribute> </targetInstance> <!-- Murano n0p3 PCI units --> diff --git a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml index 84dacb1e6..498eed08b 100644 --- a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml +++ b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml @@ -854,6 +854,10 @@ <id>CHIP_UNIT</id> <default>0</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E00000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -872,6 +876,10 @@ <id>CHIP_UNIT</id> <default>1</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E02000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -890,6 +898,10 @@ <id>CHIP_UNIT</id> <default>2</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E04000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -908,6 +920,10 @@ <id>CHIP_UNIT</id> <default>3</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E06000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -926,6 +942,10 @@ <id>CHIP_UNIT</id> <default>4</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E08000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -944,6 +964,10 @@ <id>CHIP_UNIT</id> <default>5</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E0A000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -962,6 +986,10 @@ <id>CHIP_UNIT</id> <default>6</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E0C000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -980,6 +1008,10 @@ <id>CHIP_UNIT</id> <default>7</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E0E000000000</default> + </attribute> </targetInstance> <!-- Venice n0p0 PCI units --> @@ -1886,6 +1918,10 @@ <id>CHIP_UNIT</id> <default>0</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E10000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -1904,6 +1940,10 @@ <id>CHIP_UNIT</id> <default>1</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E12000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -1922,6 +1962,10 @@ <id>CHIP_UNIT</id> <default>2</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E14000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -1940,6 +1984,10 @@ <id>CHIP_UNIT</id> <default>3</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E16000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -1958,6 +2006,10 @@ <id>CHIP_UNIT</id> <default>4</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E18000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -1976,6 +2028,10 @@ <id>CHIP_UNIT</id> <default>5</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E1A000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -1994,6 +2050,10 @@ <id>CHIP_UNIT</id> <default>6</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E1C000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -2012,6 +2072,10 @@ <id>CHIP_UNIT</id> <default>7</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E1E000000000</default> + </attribute> </targetInstance> <!-- Venice n0p1 PCI units --> @@ -2918,6 +2982,10 @@ <id>CHIP_UNIT</id> <default>0</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E20000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -2936,6 +3004,10 @@ <id>CHIP_UNIT</id> <default>1</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E22000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -2954,6 +3026,10 @@ <id>CHIP_UNIT</id> <default>2</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E24000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -2972,6 +3048,10 @@ <id>CHIP_UNIT</id> <default>3</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E26000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -2990,6 +3070,10 @@ <id>CHIP_UNIT</id> <default>4</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E28000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -3008,6 +3092,10 @@ <id>CHIP_UNIT</id> <default>5</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E2A000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -3026,6 +3114,10 @@ <id>CHIP_UNIT</id> <default>6</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E2C000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -3044,6 +3136,10 @@ <id>CHIP_UNIT</id> <default>7</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E2E000000000</default> + </attribute> </targetInstance> <!-- Venice n0p2 PCI units --> @@ -3950,6 +4046,10 @@ <id>CHIP_UNIT</id> <default>0</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E30000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -3968,6 +4068,10 @@ <id>CHIP_UNIT</id> <default>1</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E32000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -3986,6 +4090,10 @@ <id>CHIP_UNIT</id> <default>2</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E34000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -4004,6 +4112,10 @@ <id>CHIP_UNIT</id> <default>3</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E36000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -4022,6 +4134,10 @@ <id>CHIP_UNIT</id> <default>4</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E38000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -4040,6 +4156,10 @@ <id>CHIP_UNIT</id> <default>5</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E3A000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -4058,6 +4178,10 @@ <id>CHIP_UNIT</id> <default>6</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E3C000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -4076,6 +4200,10 @@ <id>CHIP_UNIT</id> <default>7</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E3E000000000</default> + </attribute> </targetInstance> <!-- Venice n0p3 PCI units --> @@ -4980,6 +5108,10 @@ <id>CHIP_UNIT</id> <default>0</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E40000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -4998,6 +5130,10 @@ <id>CHIP_UNIT</id> <default>1</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E42000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -5016,6 +5152,10 @@ <id>CHIP_UNIT</id> <default>2</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E44000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -5034,6 +5174,10 @@ <id>CHIP_UNIT</id> <default>3</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E46000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -5052,6 +5196,10 @@ <id>CHIP_UNIT</id> <default>4</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E48000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -5070,6 +5218,10 @@ <id>CHIP_UNIT</id> <default>5</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E4A000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -5088,6 +5240,10 @@ <id>CHIP_UNIT</id> <default>6</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E4C000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -5106,6 +5262,10 @@ <id>CHIP_UNIT</id> <default>7</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E4E000000000</default> + </attribute> </targetInstance> <!-- Vencie n0p4 PCI units --> @@ -6012,6 +6172,10 @@ <id>CHIP_UNIT</id> <default>0</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E50000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -6030,6 +6194,10 @@ <id>CHIP_UNIT</id> <default>1</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E52000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -6048,6 +6216,10 @@ <id>CHIP_UNIT</id> <default>2</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E54000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -6066,6 +6238,10 @@ <id>CHIP_UNIT</id> <default>3</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E56000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -6084,6 +6260,10 @@ <id>CHIP_UNIT</id> <default>4</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E58000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -6102,6 +6282,10 @@ <id>CHIP_UNIT</id> <default>5</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E5A000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -6120,6 +6304,10 @@ <id>CHIP_UNIT</id> <default>6</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E5C000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -6138,6 +6326,10 @@ <id>CHIP_UNIT</id> <default>7</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E5E000000000</default> + </attribute> </targetInstance> <!-- Venice n0p5 PCI units --> @@ -7042,6 +7234,10 @@ <id>CHIP_UNIT</id> <default>0</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E60000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -7060,6 +7256,10 @@ <id>CHIP_UNIT</id> <default>1</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E62000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -7078,6 +7278,10 @@ <id>CHIP_UNIT</id> <default>2</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E64000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -7096,6 +7300,10 @@ <id>CHIP_UNIT</id> <default>3</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E66000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -7114,6 +7322,10 @@ <id>CHIP_UNIT</id> <default>4</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E68000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -7132,6 +7344,10 @@ <id>CHIP_UNIT</id> <default>5</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E6A000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -7150,6 +7366,10 @@ <id>CHIP_UNIT</id> <default>6</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E6C000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -7168,6 +7388,10 @@ <id>CHIP_UNIT</id> <default>7</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E6E000000000</default> + </attribute> </targetInstance> <!-- Venice n0p6 PCI units --> @@ -8073,6 +8297,10 @@ <id>CHIP_UNIT</id> <default>0</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E70000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -8091,6 +8319,10 @@ <id>CHIP_UNIT</id> <default>1</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E72000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -8109,6 +8341,10 @@ <id>CHIP_UNIT</id> <default>2</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E74000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -8127,6 +8363,10 @@ <id>CHIP_UNIT</id> <default>3</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E76000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -8145,6 +8385,10 @@ <id>CHIP_UNIT</id> <default>4</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E78000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -8162,6 +8406,10 @@ <id>CHIP_UNIT</id> <default>5</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E7A000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -8180,6 +8428,10 @@ <id>CHIP_UNIT</id> <default>6</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E7C000000000</default> + </attribute> </targetInstance> <targetInstance> @@ -8198,6 +8450,10 @@ <id>CHIP_UNIT</id> <default>7</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>0x0003E7E000000000</default> + </attribute> </targetInstance> <!-- Venice n0p7 PCI units --> diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index ef8993569..398c2d557 100644 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -71,7 +71,6 @@ <attribute><id>HB_MUTEX_TEST_LOCK</id></attribute> <attribute><id>DUMMY_RW</id></attribute> <attribute><id>XSCOM_BASE_ADDRESS</id></attribute> - <attribute><id>IBSCOM_BASE_ADDR</id></attribute> <attribute><id>TEST_NULL_STRING</id></attribute> <attribute><id>TEST_MIN_STRING</id><default>Z</default></attribute> <attribute><id>TEST_MAX_STRING</id></attribute> @@ -731,6 +730,7 @@ </attribute> <attribute><id>EI_BUS_RX_MSB_LSB_SWAP</id></attribute> <attribute><id>EI_BUS_TX_MSB_LSB_SWAP</id></attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id></attribute> </targetType> <targetType> @@ -836,6 +836,9 @@ <id>SCOM_IND_MUTEX</id> </attribute> <attribute> + <id>IBSCOM_VIRTUAL_ADDR</id> + </attribute> + <attribute> <!-- Centaur memory buffer chips do not have SCOM accessible FSI GP regs --> <id>FSI_GP_REG_SCOM_ACCESS</id> <default>0</default> diff --git a/src/usr/targeting/xmltohb/genHwsvMrwXml.pl b/src/usr/targeting/xmltohb/genHwsvMrwXml.pl index 6a61ad472..05a77245d 100755 --- a/src/usr/targeting/xmltohb/genHwsvMrwXml.pl +++ b/src/usr/targeting/xmltohb/genHwsvMrwXml.pl @@ -1632,6 +1632,16 @@ sub generate_mcs { my ($proc, $mcs, $ordinalId) = @_; my $uidstr = sprintf("0x%02X0B%04X",${node},$mcs+$proc*8+${node}*8*8); + + #IBSCOM address range starts at 0x0003E00000000000 (992 TB) + #128GB per MCS/Centaur + #Addresses assigned by logical node, not physical node + #For Murano, each physical node is 2 logical nodes. + my $nodeOffset = 0x40*(${node}*2+(int($proc/2))); + my $procOffset = 0x10*($proc%2); + my $mcsOffset = $nodeOffset + $procOffset + $mcs*2; + my $mscStr = sprintf("0x0003E%02X00000000", $mcsOffset); + print " <targetInstance> <id>sys${sys}node${node}proc${proc}mcs$mcs</id> @@ -1649,6 +1659,10 @@ sub generate_mcs <id>CHIP_UNIT</id> <default>$mcs</default> </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id> + <!-- baseAddr = 0x0003E00000000000, 128GB per MCS --> + <default>$mscStr</default> + </attribute> <!-- TODO When MRW provides the information, these two attributes should be included. values of X come from MRW. <attribute> |