diff options
Diffstat (limited to 'src/usr')
8 files changed, 501 insertions, 318 deletions
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C index c28ab4349..48529a4f4 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit_training_advanced.C,v 1.43 2014/03/10 16:30:18 jdsloat Exp $ +// $Id: mss_draminit_training_advanced.C,v 1.45 2015/02/09 15:54:37 sglancy Exp $ /* File is created by SARAVANAN SETHURAMAN on Thur 29 Sept 2011. */ //------------------------------------------------------------------------------ @@ -85,6 +85,8 @@ // 1.41 | abhijsau |16-JAN-14| removed EFF_DIMM_TYPE attribute // 1.42 | mjjones |17-Jan-14| Fixed layout and error handling for RAS Review // 1.43 | jdsloat |10-MAR-14| Edited comments +// 1.44 |preeragh |06-NOV-14| Added Sanity checks for wr_vref and rd_vref only at nominal and disabled any other +// 1.45 |sglancy |09-FEB-14| Responded to FW comments // This procedure Schmoo's DRV_IMP, SLEW, VREF (DDR, CEN), RCV_IMP based on attribute from effective config procedure // DQ & DQS Driver impedance, Slew rate, WR_Vref shmoo would call only write_eye shmoo for margin calculation @@ -646,11 +648,11 @@ fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba, uint32_t l_wr_dram_vref_schmoo[MAX_PORT] = {0}; uint32_t l_wr_dram_vref_nom_fc = 0; uint32_t l_wr_dram_vref_in = 0; - i_shmoo_type_valid = WR_EYE; // Hard coded - Temporary + i_shmoo_type_valid = MCBIST; uint8_t index = 0; uint8_t count = 0; - uint8_t shmoo_param_count = 0; + //uint8_t shmoo_param_count = 0; uint32_t l_left_margin = 0; uint32_t l_right_margin = 0; uint32_t l_left_margin_wr_vref_array[MAX_WR_VREF]= {0}; @@ -661,6 +663,19 @@ fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba, if (rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR_VREF_SCHMOO, &i_target_mba, l_wr_dram_vref_schmoo); if (rc) return rc; + + FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++ Patch - Preet - WR_VREF - Check Sanity only at 500 +++++++++++++++++++++++++++"); + rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, + &l_left_margin, &l_right_margin, + l_wr_dram_vref_in); + if(rc) return rc; + rc = set_attribute(i_target_mba); + if (rc) return rc; + + + + i_shmoo_type_valid = WR_EYE; + FAPI_INF("+++++++++++++++++WRITE DRAM VREF Shmoo Attributes Values+++++++++++++++"); FAPI_INF("DRAM_WR_VREF[0] = %d , DRAM_WR_VREF[1] = %d on %s", l_wr_dram_vref_nom[0], @@ -691,18 +706,14 @@ fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba, if (rc) return rc; l_wr_dram_vref_in = l_wr_dram_vref[i_port]; //FAPI_INF(" Calling Shmoo for finding Timing Margin:"); - if (shmoo_param_count) - { - rc = set_attribute(i_target_mba); - if (rc) return rc; - } + rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, &l_left_margin, &l_right_margin, l_wr_dram_vref_in); if (rc) return rc; l_left_margin_wr_vref_array[index] = l_left_margin; l_right_margin_wr_vref_array[index] = l_right_margin; - shmoo_param_count++; + FAPI_INF("Wr Vref = %d ; Min Setup time = %d; Min Hold time = %d", wr_vref_array[index], l_left_margin_wr_vref_array[index], @@ -772,8 +783,8 @@ fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba, uint32_t l_rd_cen_vref_schmoo[MAX_PORT] = {0}; uint8_t index = 0; uint8_t count = 0; - uint8_t shmoo_param_count = 0; - i_shmoo_type_valid = RD_EYE; // Hard coded - Temporary + //uint8_t shmoo_param_count = 0; + //i_shmoo_type_valid = RD_EYE; // Hard coded - Temporary uint32_t l_left_margin = 0; uint32_t l_right_margin = 0; @@ -784,7 +795,19 @@ fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba, if (rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RD_VREF_SCHMOO, &i_target_mba, l_rd_cen_vref_schmoo); if (rc) return rc; - + i_shmoo_type_valid = MCBIST; + + + FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++ Patch - Preet - RD_VREF - Check Sanity only at 500000 +++++++++++++++++++++++++++"); + rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, + &l_left_margin, &l_right_margin, + l_rd_cen_vref_in); + if(rc) return rc; + FAPI_INF(" Setup and Sanity - Check disabled from now on..... Continuing ....."); + rc = set_attribute(i_target_mba); + if (rc) return rc; + + i_shmoo_type_valid = RD_EYE; FAPI_INF("+++++++++++++++++CENTAUR VREF Read Shmoo Attributes values+++++++++++++++"); FAPI_INF("CEN_RD_VREF[0] = %d CEN_RD_VREF[1] = %d on %s", l_rd_cen_vref_nom[0], @@ -794,7 +817,7 @@ fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba, l_rd_cen_vref_schmoo[0], l_rd_cen_vref_schmoo[1], i_target_mba.toEcmdString()); - FAPI_INF("++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); + FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++ Patch - Preet - RD_VREF +++++++++++++++++++++++++++"); if (l_rd_cen_vref_schmoo[i_port] == 0) { @@ -815,18 +838,14 @@ fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba, if (rc) return rc; l_rd_cen_vref_in = l_rd_cen_vref[i_port]; //FAPI_INF(" Calling Shmoo function to find out Timing Margin:"); - if (shmoo_param_count) - { - rc = set_attribute(i_target_mba); - if (rc) return rc; - } + rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, &l_left_margin, &l_right_margin, l_rd_cen_vref_in); if (rc) return rc; l_left_margin_rd_vref_array[index] = l_left_margin; l_right_margin_rd_vref_array[index] = l_right_margin; - shmoo_param_count++; + FAPI_INF("Read Vref = %d ; Min Setup time = %d; Min Hold time = %d", rd_cen_vref_array[index], l_left_margin_rd_vref_array[index], @@ -863,12 +882,12 @@ fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba, l_rd_cen_vref_nom[i_port]); if (rc) return rc; } - FAPI_INF("Restoring mcbist setup attribute..."); - rc = reset_attribute(i_target_mba); - if (rc) return rc; - FAPI_INF("++++ Centaur Read Vref Shmoo function executed successfully ++++"); + + FAPI_INF("++++ Centaur Read Vref Shmoo function executed successfully ++++"); } - return rc; + FAPI_INF("Restoring mcbist setup attribute..."); + rc = reset_attribute(i_target_mba);if (rc) return rc; + return rc; } //------------------------------------------------------------------------------ diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C index 12eb74a82..580c1ef1b 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -23,7 +23,7 @@ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_generic_shmoo.C,v 1.87 2014/02/07 16:54:14 sasethur Exp $ +// $Id: mss_generic_shmoo.C,v 1.92 2014/12/16 11:36:15 sasethur Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -42,6 +42,8 @@ //------------------------------------------------------------------------------ // Version:|Author: | Date: | Comment: // --------|--------|---------|-------------------------------------------------- +// 1.92 |preeragh|15-Dec-14| Reverted Changes to v.1.87 +// 1.88 |rwheeler|10-Nov-14| Updated setup_mcbist for added variable. // 1.87 |abhijsau|7-Feb-14| added sanity check and error call out for schmoo's , removed printing of disconnected DQS. // 1.86 |abhijsau|24-Jan-14| Fixed code as per changes in access delay error check // 1.85 |mjjones |24-Jan-14| Fixed layout and error handling for RAS Review diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.C index 718636c98..663b603e9 100755 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_mcbist.C,v 1.46 2014/01/23 19:35:58 sasethur Exp $ +// $Id: mss_mcbist.C,v 1.51 2015/02/09 15:54:47 sglancy Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -33,13 +33,18 @@ // *! DESCRIPTION : MCBIST Procedures // *! CONTEXT : // *! -// *! OWNER NAME : Devashikamani, Aditya Email: adityamd@in.ibm.com +// *! OWNER NAME : Hosmane, Preetham Email: preeragh@in.ibm.com // *! BACKUP : Sethuraman, Saravanan Email: saravanans@in.ibm.com // *!*************************************************************************** // CHANGE HISTORY: //------------------------------------------------------------------------------ // Version:|Author: | Date: | Comment: // --------|--------|--------|-------------------------------------------------- +// 1.51 |sglancy |02/09/15| Fixed FW comments and adjusted whitespace +// 1.50 |preeragh|01/16/15| Fixed FW comments +// 1.48 |preeragh|01/05/15| Added FW workaround for drand +// 1.48 |preeragh|12/16/14| Revert back changes. v.1.46 +// 1.47 |rwheeler|11/19/14|option to pass in rotate data seed // 1.46 |mjjones |01/20/14|RAS Review Updates // 1.45 |aditya |12/17/13|Added Simple_fix_rf // 1.43 |aditya |10/05/13|Updated fw comments @@ -739,7 +744,7 @@ fapi::ReturnCode cfg_mcb_dgen(const fapi::Target & i_target_mba, } } else if (i_datamode == MCBIST_2D_CUP_PAT8) - { + { //FAPI_DBG(" Inside MCBIST_2D_CUP_PAT8 !"); l_var = 0xFFFFFFFFFFFFFFFFull; l_var1 = 0x0000000000000000ull; l_spare = 0xFFFF0000FFFF0000ull; @@ -944,7 +949,7 @@ fapi::ReturnCode cfg_mcb_dgen(const fapi::Target & i_target_mba, } if (l_random_flag == 1) - { + { //FAPI_DBG("Inside l_rand_flag !"); for (l_index = 0; l_index < MAX_BYTE; l_index++) { @@ -976,39 +981,104 @@ fapi::ReturnCode cfg_mcb_dgen(const fapi::Target & i_target_mba, } } } + + //struct drand48_data randBuffer; + //double l_rand_D = 0; + uint8_t l_rand_l = 0; + uint8_t l_rand_array[8] = {48,52,56,60,64,68,72,76}; + //uint64_t l_data_buffer_64_value = 0; - if (i_mcbrotate == 0) + // get the rotate value loaded into reg, if rotate value 0 / not defined the default to rotate =13 + if(i_mcbrotate == 0) { - l_rotnum = 13; // for random data generation - basic setup + FAPI_DBG("%s:i_mcbrotate == 0 , the l_rotnum is set to 13",i_target_mba.toEcmdString()); + l_rotnum = 13; // for random data generation - basic setup } else { l_rotnum = i_mcbrotate; } + rc_num = rc_num | l_data_buffer_64.flushTo0(); + // get the rotate data seed loaded into reg, if rotate data value = 0 / not defined the default rotate pttern is randomlly generated. - rc_num |= l_data_buffer_4.insert(l_rotnum, 0, 4, 0); - rc_num |= l_data_buffer_64.insert(l_data_buffer_4, 0, 4, 0); - rc_num |= l_data_buffer_16.insert(l_data_buffer1_4, 0, 4); - rc_num |= l_data_buffer_16.insert(l_data_buffer1_4, 4, 4); - rc_num |= l_data_buffer_16.insert(l_data_buffer1_4, 8, 4); - rc_num |= l_data_buffer_16.insert(l_data_buffer1_4, 12, 4); - rc_num |= l_data_buffer_64.insert(l_data_buffer_16, 4, 16, 0); - if (l_print == 0) + // generate the random number + FAPI_DBG("FW workaround for drand !"); + for(l_index1 = 0; l_index1 < 8; l_index1++) + { + //l_rand_8 = drand48_r(); + + //drand48_r(&randBuffer, &l_rand_D); + //l_rand_l = (uint8_t)l_rand_D; + //l_rand_l = static_cast<unsigned int>((l_rand_D * 100) + 0.5); + /*if(l_rand_l == 0x00) + { + l_rand_l = 0xFF; + } + */ + l_rand_l = l_rand_array[l_index1]; + FAPI_DBG("%s:Value of seed drand48_r : %02X",i_target_mba.toEcmdString(), l_rand_l ); + rc_num = rc_num | l_data_buffer_64.insert(l_rand_l,8*l_index1,8); // Source start in sn is given as 24 -- need to ask + + } + + if (rc_num) { - FAPI_INF("Clearing bit 20 of MBA01_MCBIST_MCBDRCRQ_0x030106bd to avoid inversion of data to the write data flow"); + FAPI_ERR( "cfg_mcb_dgen:"); // Error setting up buffers + rc.setEcmdError(rc_num); + return rc; } - rc_num |= l_data_buffer_64.clearBit(20); - if (rc_num) + + // load the mcbist and mba with rotnum and rotdata. + rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBDRSRQ_0x030106bc , l_data_buffer_64); if(rc) return rc;//added + if(l_mbaPosition == 0) { - FAPI_ERR("cfg_mcb_dgen:"); - rc.setEcmdError(rc_num); - return rc; + rc = fapiPutScom(i_target_centaur, 0x0201167F , l_data_buffer_64); if(rc) return rc; + //l_data_buffer_64_value = l_data_buffer_64.getDoubleWord (0); + //FAPI_INF("%s:Value of Rotate data seed %016llX for reg %08X",i_target_mba.toEcmdString(), l_data_buffer_64_value, l_mbs01_mcb_random[l_index] ); + + rc_num = l_data_buffer_16.insert(l_data_buffer_64,0,16); + rc = fapiGetScom(i_target_centaur, 0x02011680 , l_data_buffer_64); if(rc) return rc; + rc_num = rc_num | l_data_buffer_64.insert(l_rotnum,0,4,4); + rc_num = rc_num | l_data_buffer_64.insert(l_data_buffer_16,4,16); + if (rc_num) + { + FAPI_ERR( "cfg_mcb_dgen:"); // Error setting up buffers + rc.setEcmdError(rc_num); + return rc; + } + rc = fapiPutScom(i_target_centaur, 0x02011680 , l_data_buffer_64); if(rc) return rc; + + } + else + { + rc = fapiPutScom(i_target_centaur, 0x0201177F , l_data_buffer_64); if(rc) return rc;//added + //l_data_buffer_64_value = l_data_buffer_64.getDoubleWord (0); + //FAPI_INF("%s:Value of Rotate data seed %016llX for reg %08X",i_target_mba.toEcmdString(), l_data_buffer_64_value, l_mbs23_mcb_random[l_index] ); + + rc_num = rc_num | l_data_buffer_16.insert(l_data_buffer_64,0,16); + rc = fapiGetScom(i_target_centaur, 0x02011780 , l_data_buffer_64); if(rc) return rc; + rc_num = rc_num | l_data_buffer_64.insert(l_rotnum,0,4,4); + rc_num = rc_num | l_data_buffer_64.insert(l_data_buffer_16,4,16); + if (rc_num) + { + FAPI_ERR( "cfg_mcb_dgen:"); // Error setting up buffers + rc.setEcmdError(rc_num); + return rc; + } + rc = fapiPutScom(i_target_centaur, 0x02011780 , l_data_buffer_64); if(rc) return rc; + } - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBDRCRQ_0x030106bd, l_data_buffer_64); - if (rc) return rc; - //if(l_print == 0)FAPI_INF("Function Name: cfg_mcb_dgen"); - //if(l_print == 0)FAPI_INF("Stop Time"); + FAPI_DBG("%s: Preet Clearing bit 20 of MBA01_MCBIST_MCBDRCRQ_0x030106bd to avoid inversion of data to the write data flow",i_target_mba.toEcmdString()); + rc_num = rc_num | l_data_buffer_64.clearBit(20,2); + if (rc_num) + { + FAPI_ERR( "cfg_mcb_dgen:"); // Error setting up buffers + rc.setEcmdError(rc_num); + return rc; + } + rc = fapiPutScom(i_target_mba,MBA01_MCBIST_MCBDRCRQ_0x030106bd,l_data_buffer_64); + return rc; } diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H index dc21c2cd1..d921ce3ca 100755 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_mcbist.H,v 1.42 2014/01/23 19:35:51 sasethur Exp $ +// $Id: mss_mcbist.H,v 1.46 2014/12/16 11:34:58 sasethur Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -33,13 +33,15 @@ // *! DESCRIPTION : MCBIST procedures // *! CONTEXT : // *! -// *! OWNER NAME : Devashikamani, Aditya Email: adityamd@in.ibm.com +// *! OWNER NAME : Preetham Hosmane Email: preeragh@in.ibm.com // *! BACKUP : Sethuraman, Saravanan Email: saravanans@in.ibm.com // *!*************************************************************************** // CHANGE HISTORY: //------------------------------------------------------------------------------- // Version:|Author: | Date: | Comment: // --------|--------|---------|-------------------------------------------------- +// 1.46 |preeragh|12/15/14| Revert back, removed rwheeler changes +// 1.43 |rwheeler|11/19/14|option to pass in rotate data seed // 1.42 |mjjones |01/20/14 |RAS Review Updates // 1.41 |aditya |12/17/13 |Updated mcb_error_map function parameters // 1.40 |rwheeler|10/29/13 |added W_ONLY_INFINITE_RAND test @@ -138,7 +140,11 @@ enum mcbist_test_mem SIMPLE_FIX_RF_RA, TEST_RR, TEST_RF, - W_ONLY_INFINITE_RAND + W_ONLY_INFINITE_RAND, + MCB_2D_CUP_SEQ, + MCB_2D_CUP_RAND, + SHMOO_STRESS_INFINITE, + HYNIX_1_COL }; enum mcbist_data_gen @@ -331,7 +337,7 @@ fapi::ReturnCode start_mcb(const fapi::Target & i_target_mba); fapi::ReturnCode setup_mcbist(const fapi::Target & i_target_mba, mcbist_byte_mask i_mcbbytemask, uint8_t i_mcbrotate, - struct Subtest_info l_sub_info[30]); + struct Subtest_info l_sub_info[30]); fapi::ReturnCode mcb_error_map_print(const fapi::Target & i_target_mba, ecmdDataBufferBase & l_mcb_fail_160, diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C index 562d6c4dc..af2d9648f 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2013,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_mcbist_address.C,v 1.14 2014/01/24 06:59:19 sasethur Exp $ +// $Id: mss_mcbist_address.C,v 1.17 2014/12/16 11:35:38 sasethur Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998, 2013 // *! All Rights Reserved -- Property of IBM @@ -33,13 +33,16 @@ // *! DESCRIPTION : MCBIST procedures // *! CONTEXT : // *! -// *! OWNER NAME : preeragh@in.ibm.com -// *! BACKUP : +// *! OWNER NAME : Preetham Hosmane | preeragh@in.ibm.com +// *! BACKUP : Saravanan Sethuraman // *!*************************************************************************** // CHANGE HISTORY: //------------------------------------------------------------------------------- // Version:|Author: | Date: | Comment: // --------|--------|---------|-------------------------------------------------- +// 1.17 |preeragh|15-Dec-14| Fix FW Review Comments +// 1.16 |rwheeler|10-Nov-14| Update to address_generation for custom address string +// 1.15 |preeragh|03-Nov-14| Fix for 128GB Schmoo // 1.14 |mjjones |20-Jan-13| RAS Review Updates // 1.13 |preet |18-Dec-13| Added 64K default for few addr_mode // 1.12 |preet |17-Dec-13| Added Addr modes @@ -120,16 +123,16 @@ fapi::ReturnCode address_generation(const fapi::Target & i_target_mba, if (rc) return rc; //------------------------------ Debug Stuff ------------------------------- - //FAPI_INF("ATTR_EFF_NUM_RANKS_PER_DIMM is %d ",l_num_ranks_per_dimm[0][0]); - //FAPI_INF("ATTR_EFF_NUM_RANKS_PER_DIMM is %d ",l_num_ranks_per_dimm[0][1]); - //FAPI_INF("ATTR_EFF_NUM_RANKS_PER_DIMM is %d ",l_num_ranks_per_dimm[1][0]); - //FAPI_INF("ATTR_EFF_NUM_RANKS_PER_DIMM is %d ",l_num_ranks_per_dimm[1][1]); - //------------------------------ Debug Stuff ------------------------------- - //FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p0_dim0 is %d ",l_num_master_ranks[0][0]); - //FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p0_dim1 is %d ",l_num_master_ranks[0][1]); - //FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p1_dim0 is %d ",l_num_master_ranks[1][0]); - //FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p1_dim1 is %d ",l_num_master_ranks[1][1]); - //------------------------------------------------------------------------------- + //FAPI_INF("ATTR_EFF_NUM_RANKS_PER_DIMM is %d ",l_num_ranks_per_dimm[0][0]); + //FAPI_INF("ATTR_EFF_NUM_RANKS_PER_DIMM is %d ",l_num_ranks_per_dimm[0][1]); + //FAPI_INF("ATTR_EFF_NUM_RANKS_PER_DIMM is %d ",l_num_ranks_per_dimm[1][0]); + //FAPI_INF("ATTR_EFF_NUM_RANKS_PER_DIMM is %d ",l_num_ranks_per_dimm[1][1]); + //------------------------------ Debug Stuff ------------------------------- + //FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p0_dim0 is %d ",l_num_master_ranks[0][0]); + //FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p0_dim1 is %d ",l_num_master_ranks[0][1]); + //FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p1_dim0 is %d ",l_num_master_ranks[1][0]); + //FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p1_dim1 is %d ",l_num_master_ranks[1][1]); + //------------------------------------------------------------------------------- l_num_ranks_p0_dim0 = l_num_ranks_per_dimm[0][0]; l_num_ranks_p0_dim1 = l_num_ranks_per_dimm[0][1]; @@ -319,7 +322,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, } rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64); if (rc) return rc; - i++; + ////FAPI_INF("Inside strcmp mr3"); l_sbit = 18; @@ -351,7 +354,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64); if (rc) return rc; //FAPI_INF("mr3 Invalid"); - i++; + } ////FAPI_INF("Inside strcmp mr2"); @@ -385,7 +388,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64); if (rc) return rc; //FAPI_INF("mr2 Invalid"); - i++; + } ////FAPI_INF("Inside strcmp mr1"); @@ -419,7 +422,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64); if (rc) return rc; //FAPI_INF("mr1 Invalid"); - i++; + } ////FAPI_INF("Inside strcmp mr0"); @@ -437,7 +440,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, } rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64); if (rc) return rc; - i++; + ////FAPI_INF("Value of i = %d",i); //FAPI_INF("mr0 Invalid\n"); @@ -455,7 +458,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, } rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); if (rc) return rc; - i++; + //FAPI_INF("col2 Invalid"); ////FAPI_INF("Value of i = %d",i); ////FAPI_INF("Inside strcmp cl3"); @@ -488,7 +491,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); if (rc) return rc; //FAPI_INF("Col 3 -- Invalid"); - i++; + } ////FAPI_INF("Inside strcmp cl4"); @@ -522,7 +525,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); if (rc) return rc; //FAPI_INF("Col 4 -- Invalid"); - i++; + } ////FAPI_INF("Inside strcmp cl5"); @@ -555,7 +558,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); if (rc) return rc; //FAPI_INF("Col 5 -- Invalid"); - i++; + } ////FAPI_INF("Inside strcmp cl6"); @@ -589,7 +592,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); if (rc) return rc; //FAPI_INF("Col 6 -- Invalid"); - i++; + } ////FAPI_INF("Inside strcmp cl7"); @@ -623,7 +626,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); if (rc) return rc; //FAPI_INF("Col 7 -- Invalid"); - i++; + } ////FAPI_INF("Inside strcmp cl8"); @@ -657,7 +660,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); if (rc) return rc; //FAPI_INF("Col 8 -- Invalid"); - i++; + } ////FAPI_INF("Inside strcmp cl9"); @@ -691,7 +694,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64); if (rc) return rc; //FAPI_INF("Col 9 -- Invalid"); - i++; + } ////FAPI_INF("Inside strcmp cl11"); @@ -727,7 +730,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); if (rc) return rc; FAPI_DBG("%s:Col 11 -- Invalid", i_target_mba.toEcmdString()); - i++; + } } else @@ -742,7 +745,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); if (rc) return rc; //FAPI_INF("Col 11 -- Invalid"); - i++; + } ////FAPI_INF("Value of i = %d",i); @@ -776,7 +779,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); if (rc) return rc; //FAPI_INF("Col 13 Invalid"); - i++; + } ////FAPI_INF("Value of i = %d",i); ////FAPI_INF("Inside strcmp r0"); @@ -810,7 +813,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); if (rc) return rc; //FAPI_INF("row 0 -- Invalid"); - i++; + } ////FAPI_INF("Inside strcmp r1"); @@ -844,7 +847,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); if (rc) return rc; //FAPI_INF("row 1 -- Invalid"); - i++; + } ////FAPI_INF("Inside strcmp r2"); @@ -878,7 +881,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); if (rc) return rc; //FAPI_INF("row 2 -- Invalid"); - i++; + } ////FAPI_INF("Inside strcmp r3"); @@ -912,7 +915,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); if (rc) return rc; //FAPI_INF("row 3 -- Invalid"); - i++; + } ////FAPI_INF("Inside strcmp r4"); @@ -946,7 +949,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); if (rc) return rc; //FAPI_INF("row 4 -- Invalid"); - i++; + } ////FAPI_INF("Inside strcmp r5"); @@ -980,7 +983,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); if (rc) return rc; //FAPI_INF("row 5 -- Invalid"); - i++; + } ////FAPI_INF("Inside strcmp r6"); @@ -1014,7 +1017,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); if (rc) return rc; //FAPI_INF("row 6 -- Invalid"); - i++; + } ////FAPI_INF("Inside strcmp r7"); @@ -1048,7 +1051,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64); if (rc) return rc; //FAPI_INF("row 7 -- Invalid"); - i++; + } ////FAPI_INF("Inside strcmp r8"); @@ -1082,7 +1085,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); if (rc) return rc; //FAPI_INF("row 8 -- Invalid"); - i++; + } ////FAPI_INF("Inside strcmp r9"); @@ -1116,7 +1119,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); if (rc) return rc; //FAPI_INF("row 9 -- Invalid"); - i++; + } ////FAPI_INF("Inside strcmp r10"); @@ -1150,7 +1153,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); if (rc) return rc; //FAPI_INF("row 10 -- Invalid"); - i++; + } ////FAPI_INF("Inside strcmp r11"); @@ -1184,7 +1187,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); if (rc) return rc; //FAPI_INF("row 11 -- Invalid"); - i++; + } ////FAPI_INF("Inside strcmp r12"); @@ -1218,7 +1221,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); if (rc) return rc; //FAPI_INF("row 12 -- Invalid"); - i++; + } ////FAPI_INF("Inside strcmp r13"); @@ -1252,7 +1255,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); if (rc) return rc; //FAPI_INF("row 13 -- Invalid"); - i++; + } ////FAPI_INF("Inside strcmp r14"); @@ -1286,7 +1289,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); if (rc) return rc; //FAPI_INF("row 14 -- Invalid"); - i++; + } ////FAPI_INF("Inside strcmp r15"); @@ -1319,7 +1322,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); if (rc) return rc; //FAPI_INF("row 15 -- Invalid"); - i++; + } ////FAPI_INF("Value of i = %d",i); ////FAPI_INF("Inside strcmp r16 and l_dram_rows = %d",l_dram_rows); @@ -1353,7 +1356,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, //FAPI_INF("Row 16 Invalid"); rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64); if (rc) return rc; - i++; + } ////FAPI_INF("Value of i = %d",i); @@ -1378,7 +1381,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64); if (rc) return rc; //FAPI_INF("sl2 Invalid"); - i++; + ////FAPI_INF("Value of i = %d",i); ////FAPI_INF("Inside strcmp sl1"); l_sbit = 30; @@ -1399,10 +1402,10 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, } rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64); if (rc) return rc; - i++; + //FAPI_INF("sl1 Invalid"); ////FAPI_INF("Value of i = %d",i); - ////FAPI_INF("Inside strcmp sl0"); + FAPI_INF("Inside strcmp sl0"); l_sbit = 24; l_value = i; rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64); @@ -1422,12 +1425,12 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64); if (rc) return rc; //FAPI_INF("sl0 Invalid"); - i++; + ////FAPI_INF("Value of i = %d",i); //------ Setting Start and end addr counters - //FAPI_INF("Debug - --------------- Setting Start and End Counters -----------\n"); + FAPI_INF("Debug - --------------- Setting Start and End Counters -----------\n"); rc_num = l_data_buffer_rd64.flushTo0(); if (rc_num) { @@ -1438,7 +1441,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, 0x030106d0, l_data_buffer_rd64); if (rc) return rc; l_value = i + 1; - //FAPI_INF("Setting end_addr Value of i = %d",i); + FAPI_INF("Setting end_addr Value of i = %d",i); rc_num = l_data_buffer_rd64.flushTo0(); //Calculate and set Valid bits for end_addr @@ -1498,7 +1501,7 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, { if (l_attr_addr_mode == 0) { - //FAPI_INF("ATTR_EFF_SCHMOO_ADDR_MODE - %d ---- Few Address Mode --------",l_attr_addr_mode); + FAPI_INF("ATTR_EFF_SCHMOO_ADDR_MODE - %d ---- Few Address Mode --------",l_attr_addr_mode); l_sbit = 32; rc_num = l_data_buffer_rd64.flushTo0(); l_start = 24; @@ -1523,9 +1526,9 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, } else if (l_attr_addr_mode == 1) { - //FAPI_INF("ATTR_EFF_SCHMOO_ADDR_MODE - %d ---- QUARTER ADDRESSING Mode --------",l_attr_addr_mode); + FAPI_INF("ATTR_EFF_SCHMOO_ADDR_MODE - %d ---- QUARTER ADDRESSING Mode --------",l_attr_addr_mode); l_readscom_value = l_readscom_value >> 2; - //FAPI_INF("Debug - Final End addr for 0x030106d2 = %016llX",l_readscom_value); + FAPI_INF("Debug - Final End addr for 0x030106d2 = %016llX",l_readscom_value); rc_num = l_data_buffer_rd64.setDoubleWord(0, l_readscom_value); if (rc_num) { @@ -1540,9 +1543,9 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, } else if (l_attr_addr_mode == 2) { - //FAPI_INF("ATTR_EFF_SCHMOO_ADDR_MODE - %d ---- HALF ADDRESSING Mode --------",l_attr_addr_mode); + FAPI_INF("ATTR_EFF_SCHMOO_ADDR_MODE - %d ---- HALF ADDRESSING Mode --------",l_attr_addr_mode); l_readscom_value = l_readscom_value >> 1; - //FAPI_INF("Debug - Final End addr for 0x030106d2 = %016llX",l_readscom_value); + FAPI_INF("Debug - Final End addr for 0x030106d2 = %016llX",l_readscom_value); rc_num = l_data_buffer_rd64.setDoubleWord(0, l_readscom_value); if (rc_num) { @@ -1557,8 +1560,8 @@ fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba, } else { - //FAPI_INF("ATTR_EFF_SCHMOO_ADDR_MODE - %d ---- FULL Address Mode --------",l_attr_addr_mode); - //FAPI_INF("Debug - Final End addr for 0x030106d2 = %016llX",l_readscom_value); + FAPI_INF("ATTR_EFF_SCHMOO_ADDR_MODE - %d ---- FULL Address Mode --------",l_attr_addr_mode); + FAPI_INF("Debug - Final End addr for 0x030106d2 = %016llX",l_readscom_value); rc = fapiPutScom(i_target_mba, 0x030106d2, l_data_buffer_rd64); if (rc) return rc; rc = fapiPutScom(i_target_mba, 0x030106d3, l_data_buffer_rd64); diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H index df245c655..e4682f8b0 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2013,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_mcbist_address.H,v 1.5 2014/01/24 06:59:30 sasethur Exp $ +// $Id: mss_mcbist_address.H,v 1.7 2014/12/16 11:35:52 sasethur Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998, 2013 // *! All Rights Reserved -- Property of IBM @@ -42,6 +42,7 @@ // 1.3 |bellows |03-Apr-13| Added Id for firmware // 1.4 |preeragh|17-Dec-14| Removed unwanted header includes // 1.5 |mjjones |20-Jan-14| RAS Review Updates +// 1.7 |preeragh|15-Dec-14| Fix FW review comments // --------|--------|---------|-------------------------------------------------- //------------------------------------------------------------------------------ #ifndef MSS_MCBIST_ADDRESS_H diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C index f63046f33..9f6fddeea 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_mcbist_common.C,v 1.63 2014/02/07 17:17:46 sasethur Exp $ +// $Id: mss_mcbist_common.C,v 1.72 2015/02/09 15:54:57 sglancy Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -33,13 +33,21 @@ // *! DESCRIPTION : MCBIST Procedures // *! CONTEXT : // *! -// *! OWNER NAME : Devashikamani, Aditya Email: adityamd@in.ibm.com +// *! OWNER NAME : Preetham Hosmane Email: preeragh@in.ibm.com // *! BACKUP : Sethuraman, Saravanan Email: saravanans@in.ibm.com // *!*************************************************************************** // CHANGE HISTORY: //------------------------------------------------------------------------------ // Version:|Author: | Date: | Comment: // --------|--------|--------|-------------------------------------------------- +// 1.72 |sglancy |02/09/15|Fixed FW comments and addressed bugs +// 1.71 |preeragh|01/16/15|Fixed FW comments +// 1.70 |preeragh|12/16/14|Revert to FW build v.1.66 +// 1.68 |rwheeler|11/19/14|option to pass in rotate data seed +// 1.67 |sglancy |11/03/14|Fixed MCBIST to allow for a custom user generated address - removed forcing of l_new_addr=1 +// 1.66 |preeragh|11/03/14|Fix Addressing Map and enable Refresh +// 1.65 | | - | - +// 1.64 |rwheeler|10/24/14|Added thermal sensor data // 1.63 |adityamd|02/07/14|RAS Review Updates // 1.62 |mjjones |01/17/14|RAS Review Updates // 1.61 |aditya |01/15/14|Updated attr ATTR_EFF_CUSTOM_DIMM @@ -104,6 +112,7 @@ #include <fapiTestHwpDq.H> #include <dimmBadDqBitmapFuncs.H> + extern "C" { using namespace fapi; @@ -366,9 +375,10 @@ fapi::ReturnCode setup_mcbist(const fapi::Target & i_target_mba, uint8_t i_port = 0; uint8_t i_rank = 0; - //FAPI_DBG("%s:DEBUG-----Print----Address Gen ",i_target_mba.toEcmdString()); - rc = FAPI_ATTR_GET(ATTR_MCBIST_ADDR_MODES, &i_target_mba, l_new_addr); - if (rc) return rc; + FAPI_DBG("%s:DEBUG-----Print----Address Gen ",i_target_mba.toEcmdString()); + rc = FAPI_ATTR_GET(ATTR_MCBIST_ADDR_MODES, &i_target_mba, l_new_addr); + if (rc) return rc; + FAPI_DBG("DEBUG----- l_new_addr = %d ",l_new_addr); if (l_new_addr != 0) { @@ -380,7 +390,21 @@ fapi::ReturnCode setup_mcbist(const fapi::Target & i_target_mba, return rc; } } - + + FAPI_INF( "+++ Enabling Refresh +++"); + + rc = fapiGetScom(i_target_mba, 0x03010432, l_data_buffer_64); + if(rc) return rc; + //Bit 0 is enable + rc_num = rc_num | l_data_buffer_64.setBit(0); + if(rc_num) + { + rc.setEcmdError(rc_num); + return rc; + } + rc = fapiPutScom(i_target_mba, 0x03010432, l_data_buffer_64); + if(rc)return rc; + if (i_mcbbytemask != NONE) { rc = cfg_byte_mask(i_target_mba); @@ -585,9 +609,12 @@ fapi::ReturnCode poll_mcb(const fapi::Target & i_target_mba, uint32_t l_time_count = 0; uint8_t l_index = 0; uint8_t l_Subtest_no = 0; + uint64_t l_counter = 0x0ll; uint32_t i_mcbtest = 0; uint32_t l_st_ln = 0; uint32_t l_len = 0; + uint32_t l_dts_0 = 0; + uint32_t l_dts_1 = 0; uint8_t l_mcb_stop_on_fail = 0; mcbist_test_mem i_mcbtest1; Target i_target_centaur; @@ -628,12 +655,35 @@ fapi::ReturnCode poll_mcb(const fapi::Target & i_target_mba, l_time_count = 0; FAPI_DBG("%s:POLLING STATUS:POLLING IN PROGRESS...........", i_target_mba.toEcmdString()); + //rc = mss_cen_dimm_temp_sensor(i_target_centaur);if (rc) return rc; + rc = fapiGetScom(i_target_centaur, 0x02050000, l_data_buffer_64);if (rc) return rc; + rc_num = l_data_buffer_64.extractToRight(&l_dts_0, 0, 12); + rc_num = rc_num | l_data_buffer_64.extractToRight(&l_dts_1, 16, 12); + if (rc_num) + { + FAPI_ERR("Buffer error in function poll_mcb"); + rc.setEcmdError(rc_num); + return rc; + } + + FAPI_DBG("%s:DTS Thermal Sensor 0 Results %d", i_target_centaur.toEcmdString(), l_dts_0); + FAPI_DBG("%s:DTS Thermal Sensor 1 Results %d", i_target_centaur.toEcmdString(), l_dts_1); + if (i_flag == 0) { + // Read Counter Reg + + rc = fapiGetScom(i_target_mba, 0x030106b0, l_data_buffer_64); + if (rc) return rc; + l_counter = l_data_buffer_64.getDoubleWord (0); + + FAPI_DBG("%s:MCBCounter %016llX ", i_target_mba.toEcmdString(), l_counter); + + //Read Sub-Test number rc = fapiGetScom(i_target_centaur, 0x02011670, l_data_buffer_64); if (rc) return rc; l_st_ln = 3; - l_len = 4; + l_len = 5; rc_num = l_data_buffer_64.extract(&l_Subtest_no, l_st_ln, l_len); if (rc_num) { @@ -641,8 +691,8 @@ fapi::ReturnCode poll_mcb(const fapi::Target & i_target_mba, rc.setEcmdError(rc_num); return rc; } - - FAPI_DBG("%s:SUBTEST No %d ", i_target_mba.toEcmdString(), l_Subtest_no); + + //FAPI_DBG("%s:SUBTEST No %08x ", i_target_mba.toEcmdString(), l_Subtest_no); rc = FAPI_ATTR_GET(ATTR_MCBIST_TEST_TYPE, &i_target_mba, i_mcbtest); if (rc) return rc;//---------i_mcbtest------->run rc = mss_conversion_testtype(i_target_mba, i_mcbtest, i_mcbtest1); @@ -880,12 +930,10 @@ fapi::ReturnCode poll_mcb(const fapi::Target & i_target_mba, if (*o_mcb_status == 1) { - FAPI_ERR("poll_mcb:MCBIST failed"); - const fapi::Target & MBA_CHIPLET = i_target_mba; - FAPI_SET_HWP_ERROR(rc, RC_MSS_MCBIST_TIMEOUT_ERROR);//We decided to use TIMEOUT ERROR INSTEAD Of RC_MSS_MCBIST_FAILED - //FAPI_SET_HWP_ERROR(rc, RC_MSS_MCBIST_FAILED); - return rc; + FAPI_DBG("poll_mcb:MCBIST failed"); + return rc; } + return rc; } fapi::ReturnCode mcb_error_map_print(const fapi::Target & i_target_mba, @@ -1001,13 +1049,13 @@ fapi::ReturnCode mcb_error_map_print(const fapi::Target & i_target_mba, rc_num |= l_data_buffer1_64.flushTo0(); //FAPI_ERR("Buffer error in function mcb_error_map_print"); - - if (rc_num) //The check for if bad rc_num was misplaced - { - FAPI_ERR("Error in function mcb_error_map_print:"); - rc.setEcmdError(rc_num); - return rc; - } + + if (rc_num) //The check for if bad rc_num was misplaced + { + FAPI_ERR("Error in function mcb_error_map_print:"); + rc.setEcmdError(rc_num); + return rc; + } uint8_t l_num, io_num, l_inter, l_num2, l_index2; l_num = 0; @@ -2736,6 +2784,19 @@ fapi::ReturnCode mss_conversion_testtype(const fapi::Target & i_target_mba, i_mcbtest = W_ONLY_INFINITE_RAND; FAPI_INF("%s:TESTTYPE :W_ONLY_INFINITE_RAND", i_target_mba.toEcmdString()); break; + case 45: + i_mcbtest = MCB_2D_CUP_SEQ; + FAPI_INF("%s:TESTTYPE :MCB_2D_CUP_SEQ", i_target_mba.toEcmdString()); + break; + case 46: + i_mcbtest = MCB_2D_CUP_RAND; + FAPI_INF("%s:TESTTYPE :MCB_2D_CUP_RAND", i_target_mba.toEcmdString()); + break; + case 47: + i_mcbtest = SHMOO_STRESS_INFINITE; + FAPI_INF("%s:TESTTYPE :SHMOO_STRESS_INFINITE", i_target_mba.toEcmdString()); + break; + default: FAPI_INF("%s:Wrong Test_type,so using default test_type", i_target_mba.toEcmdString()); diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C index 43652cb08..e49f80968 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_config_termination.C,v 1.47 2014/04/07 23:01:20 lapietra Exp $ +// $Id: mss_eff_config_termination.C,v 1.48 2014/10/01 22:32:38 asaetow Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_termination.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -44,11 +44,13 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.48 | asaetow |01-OCT-14| Added setting for single-drop 4G1Rx8 and 16G2Rx4 from Ken/Anil for habanero at 1333Mbps under "rdimm_habanero_1333_r10_mba0", "rdimm_habanero_1333_r10_mba1", "rdimm_habanero_1333_r20_mba0", and "rdimm_habanero_1333_r20_mba1". +// | | | Added place holder setting for dual-drop 4G1Rx8 and 16G2Rx4 for habanero at 1333Mbps under "rdimm_habanero_1333_r11_mba0", "rdimm_habanero_1333_r11_mba1", "rdimm_habanero_1333_r22_mba0", and "rdimm_habanero_1333_r22_mba1". // 1.47 | dcadiga |07-APR-14| FFDC Updates // 1.46 | kcook |14-MAR-14| Fixed create_db_ddr4 stub function definition // 1.45 | kcook |14-MAR-14| Added DDR4 support // 1.44 | mjjones |07-MAR-14| Only compile if FAPI_MSSLABONLY defined -// 1.43 | dcadiga |04-MAR-14| Added in ISDimm support for KG +// 1.43 | dcadiga |04-MAR-14| Added in ISDimm support for KG // 1.42 | asaetow |22-JAN-14| Fixed target "const fapi::Target" to "const fapi::Target&" for mss_eff_config.C v1.38 and mss_eff_config_termination.H v1.2 // 1.41 | dcadiga |13-JAN-14| Removed checking of dimm type attribute for CDIMM, replaced with custom dimm type attribute // 1.40 | bellows |02-JAN-14| VPD attribute removal @@ -59,8 +61,8 @@ // 1.35 | bellows |16-SEP-13| Hostboot compile update. // 1.34 | kcook |13-SEP-13| Updated define FAPI_LRDIMM token. // 1.33 | bellows |12-SEP-13| set_vpd_dimm_spare function added before AM keyword shows up -// 1.32 | kcook |27-AUG-13| Removed LRDIMM support to mss_lrdimm_funcs.C. -// 1.31 | kcook |16-AUG-13| Added LRDIMM support. +// 1.32 | kcook |27-AUG-13| Removed LRDIMM support to mss_lrdimm_funcs.C. +// 1.31 | kcook |16-AUG-13| Added LRDIMM support. // 1.30 | dcadiga |07-AUG-13| Fixed hostboot compile issue // 1.29 | dcadiga |05-AUG-13| KG3 allowed, ifdef removed for lab card uint declaration, added 4R support to 1600, changed 4Rx4 / 4Rx8 RCD Drive Settings // 1.28 | asaetow |05-AUG-13| Added temp workaround for incorrect byte33 SPD data in early lab OLD 16G/32G CDIMMs. @@ -75,7 +77,7 @@ // 1.20 | dcadiga |30-APR-13| Fixed Hostboot Compile Error LN 972 // 1.19 | dcadiga |19-APR-13| Added Cdimm RCB/RCC, changed RDIMM settings for MBA0 so that a 1R card will work and a 4R card will work // 1.18 | dcadiga |10-APR-13| Added UDIMM for ICICLE DDR4, fixed DD0 Clk shift -// 1.17 | asaetow |26-MAR-13| Removed width check for RDIMM MBA0 4Rank 1333. +// 1.17 | asaetow |26-MAR-13| Removed width check for RDIMM MBA0 4Rank 1333. // 1.16 | dcadiga |25-MAR-13| Added in 2N Addressing Mode. // 1.15 | dcadiga |14-MAR-13| Fixed simulation issue. // 1.14 | dcadiga |12-MAR-13| Code re-write for new dimms. Confirmed working on all systems @@ -88,11 +90,11 @@ // | | | Fixed (l_attr_is_simulation || 1) to (l_attr_is_simulation != 0) from v1.8 and v1.9. // 1.9 | bellows |12-DEC-12| Changed phase rotators for sim to 0x40 for clocks // 1.8 | bellows |06-DEC-12| Added sim leg for rotator values -// 1.7 | asaetow |18-NOV-12| Changed ATTR_MSS_CAL_STEP_ENABLE from 0x7F back to 0xFF. +// 1.7 | asaetow |18-NOV-12| Changed ATTR_MSS_CAL_STEP_ENABLE from 0x7F back to 0xFF. // 1.6 | asaetow |17-NOV-12| Fixed uint8_t attr_eff_odt_wr for 4R RDIMMs. // 1.5 | asaetow |17-NOV-12| Added PR settings. // | | | Fixed RCD settings for RDIMM. -// 1.4 | asaetow |17-NOV-12| Changed ATTR_MSS_CAL_STEP_ENABLE from 0xFF to 0x7F. +// 1.4 | asaetow |17-NOV-12| Changed ATTR_MSS_CAL_STEP_ENABLE from 0xFF to 0x7F. // 1.3 | asaetow |05-NOV-12| Added Paul's SI value for pre-machine parsable workbook. // | | | NOTE: DO NOT pick-up without memory_attributes.xml v1.45 or newer. // 1.2 | asaetow |05-SEP-12| Added ATTR_MSS_CAL_STEP_ENABLE. @@ -126,16 +128,16 @@ fapi::ReturnCode mss_lrdimm_rewrite_odt( const Target& i_target_mba, uint32_t *var_array_p_array[5]) { ReturnCode rc; - + FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target_mba.toEcmdString()); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_LRDIMM_REWRITE_INVALID_EXEC); return rc; } -ReturnCode mss_lrdimm_term_atts(const Target& i_target_mba) +ReturnCode mss_lrdimm_term_atts(const Target& i_target_mba) { ReturnCode rc; - + FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target_mba.toEcmdString()); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_LRDIMM_TERM_INVALID_EXEC); @@ -148,7 +150,7 @@ ReturnCode mss_lrdimm_term_atts(const Target& i_target_mba) fapi::ReturnCode mss_create_rcd_ddr4(const Target& i_target_mba) { ReturnCode rc; - + FAPI_ERR("Invalid exec of mss_create_rcd_ddr4 on %s!", i_target_mba.toEcmdString()); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_CREATE_RCD_DDR4_INVALID_EXEC); return rc; @@ -157,7 +159,7 @@ fapi::ReturnCode mss_create_rcd_ddr4(const Target& i_target_mba) fapi::ReturnCode mss_create_db_ddr4(const Target& i_target_mba) { ReturnCode rc; - + FAPI_ERR("Invalid exec of mss_create_db_ddr4 on %s!", i_target_mba.toEcmdString()); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_CREATE_DB_DDR4_INVALID_EXEC); @@ -167,7 +169,7 @@ fapi::ReturnCode mss_create_db_ddr4(const Target& i_target_mba) fapi::ReturnCode mss_lrdimm_ddr4_term_atts(const Target& i_target_mba) { ReturnCode rc; - + FAPI_ERR("Invalid exec of mss_lrdimm_ddr4_term_atts on %s!", i_target_mba.toEcmdString()); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_DDR4_TERM_ATTS_INVALID_EXEC); @@ -275,7 +277,7 @@ uint8_t attr_vpd_cen_phase_rot_m1_cntl_odt1[PORT_SIZE]; //Declare the different dimms here: //Cdimm rc_A -uint32_t cdimm_default[STORE_ARRAY_SIZE] = +uint32_t cdimm_default[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF }; @@ -283,7 +285,7 @@ uint32_t cdimm_rca_1r_1333_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF }; -uint32_t cdimm_rca_1r_1600_mba0[STORE_ARRAY_SIZE] = +uint32_t cdimm_rca_1r_1600_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF }; @@ -306,100 +308,100 @@ uint32_t cdimm_rcb4_2r_1600_mba1[210] = /* //RDIMM A/B Ports MBA0 Glacier -uint32_t rdimm_glacier_1600_r10_mba0[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1600_r10_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r20e_mba0[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1333_r20e_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r20e_mba0[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1600_r20e_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r20b_mba0[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1333_r20b_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r20b_mba0[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1600_r20b_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r40_mba0[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1333_r40_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; //RDIMM C/D Ports MBA1 Glacier -uint32_t rdimm_glacier_1333_r10_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1333_r10_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r10_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1600_r10_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r20e_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1333_r20e_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r20e_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1600_r20e_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r20b_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1333_r20b_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r20b_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1600_r20b_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1066_r40_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1066_r40_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r11_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1333_r11_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r11_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1600_r11_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r22e_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1333_r22e_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r22e_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1600_r22e_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r22b_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1333_r22b_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r22b_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1600_r22b_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1066_r44_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1066_r44_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF }; //UDIMM TEMP FOR JAKE ICICLE -uint32_t udimm_glacier_1600_r10_mba0[STORE_ARRAY_SIZE] = +uint32_t udimm_glacier_1600_r10_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF }; -uint32_t udimm_glacier_1600_r10_mba1[STORE_ARRAY_SIZE] = +uint32_t udimm_glacier_1600_r10_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF }; -//KG3 +//KG3 uint32_t rdimm_kg3_1333_r1_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; @@ -454,99 +456,99 @@ uint32_t rdimm_kg3_1600_r4_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RC //RDIMM A/B Ports MBA0 Glacier -uint32_t rdimm_glacier_1600_r10_mba0[210] = +uint32_t rdimm_glacier_1600_r10_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,70,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,7,9,11,10,4,0,3,5,0,0,4,10,3,12,3,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1333_r20e_mba0[210] = +uint32_t rdimm_glacier_1333_r20e_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,67,0,0,0,1,2,2,4,0,1,3,2,5,2,6,3,3,3,2,7,7,7,6,8,6,7,7,0,2,10,0,0,0,10,2,10,2,9,0,0,0,0,0,0,0,0,0,0,71,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,1,3,0,0,3,7,2,9,1,10,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1600_r20e_mba0[210] = +uint32_t rdimm_glacier_1600_r20e_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,66,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,75,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,8,9,11,11,4,0,3,5,0,0,4,10,3,12,3,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1333_r20b_mba0[210] = +uint32_t rdimm_glacier_1333_r20b_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,2,2,4,0,1,3,2,5,2,6,3,3,3,2,6,7,7,6,8,6,7,7,0,2,10,0,0,0,10,2,10,2,9,0,0,0,0,0,0,0,0,0,0,68,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,2,4,0,0,4,8,3,10,2,10,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1600_r20b_mba0[210] = +uint32_t rdimm_glacier_1600_r20b_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,70,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,8,9,11,11,4,0,3,5,0,0,5,10,3,12,3,13,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1333_r40_mba0[210] = +uint32_t rdimm_glacier_1333_r40_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,4,1,1,4,3,5,2,7,3,4,3,3,7,7,7,7,8,7,8,7,0,3,11,0,0,1,11,3,11,3,10,0,0,0,0,0,0,0,0,0,0,71,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,2,4,0,0,4,8,3,10,3,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; //RDIMM C/D Ports MBA1 Glacier -uint32_t rdimm_glacier_1333_r10_mba1[210] = +uint32_t rdimm_glacier_1333_r10_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,12,11,12,11,8,12,13,13,16,12,9,12,11,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,10,10,13,10,11,13,13,12,13,13,9,13,10,12,13,10,10,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1600_r10_mba1[210] = +uint32_t rdimm_glacier_1600_r10_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,15,13,15,14,10,15,16,17,21,15,11,15,13,18,15,9,11,13,8,10,14,7,11,0,10,2,0,0,13,2,12,5,4,2,0,0,0,0,0,0,0,0,0,0,71,0,0,0,12,13,16,13,13,16,16,15,16,17,11,16,12,15,17,12,12,13,11,12,9,10,15,0,4,14,0,0,4,15,4,13,4,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1333_r20e_mba1[210] = +uint32_t rdimm_glacier_1333_r20e_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,0,0,12,11,12,11,8,12,13,13,16,12,9,12,11,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,73,0,0,0,10,10,13,11,11,13,13,12,13,13,9,13,10,12,13,10,10,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1600_r20e_mba1[210] = +uint32_t rdimm_glacier_1600_r20e_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,77,0,0,0,15,13,15,14,10,15,16,17,21,15,11,15,13,18,15,9,11,13,8,10,14,7,11,0,9,1,0,0,13,2,12,5,4,1,0,0,0,0,0,0,0,0,0,0,77,0,0,0,12,13,16,13,13,16,16,15,16,17,11,16,13,15,17,12,12,13,11,12,9,10,15,0,4,14,0,0,4,15,4,13,3,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1333_r20b_mba1[210] = +uint32_t rdimm_glacier_1333_r20b_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,12,10,12,11,8,11,13,13,16,12,9,12,10,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,10,10,13,10,10,13,13,12,13,13,8,13,10,12,13,10,9,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1600_r20b_mba1[210] = +uint32_t rdimm_glacier_1600_r20b_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,14,13,15,14,10,14,16,17,21,15,11,15,13,17,15,9,11,13,8,10,14,7,11,0,10,1,0,0,13,2,12,5,4,1,0,0,0,0,0,0,0,0,0,0,71,0,0,0,12,13,16,13,13,16,16,15,16,16,10,16,12,15,17,12,12,12,11,12,9,9,15,0,4,14,0,0,4,15,4,13,4,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1066_r40_mba1[210] = +uint32_t rdimm_glacier_1066_r40_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,10,9,10,9,7,10,11,11,14,10,7,10,9,12,10,6,7,8,5,7,9,5,7,0,7,1,0,0,9,1,8,3,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,8,8,11,8,9,10,11,10,11,11,7,11,8,10,11,8,8,8,7,8,6,6,10,0,3,10,0,0,3,10,3,9,2,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1333_r11_mba1[210] = +uint32_t rdimm_glacier_1333_r11_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,69,0,18,17,18,17,14,18,19,19,22,18,15,18,17,20,18,13,15,16,13,14,17,12,15,0,11,5,0,0,14,5,13,7,7,5,11,2,0,0,3,3,5,3,8,2,73,0,69,0,16,16,19,16,17,19,19,18,19,19,15,19,16,18,19,16,16,16,15,16,14,14,18,0,7,15,0,0,7,15,7,14,6,13,4,12,0,0,9,14,9,11,4,11,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1600_r11_mba1[210] = +uint32_t rdimm_glacier_1600_r11_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,76,0,71,0,21,20,22,20,17,21,23,23,27,22,18,22,20,24,21,15,18,20,15,17,20,14,18,0,14,6,0,0,17,6,17,10,9,6,13,2,0,0,4,3,5,3,10,3,76,0,71,0,19,20,23,20,20,23,23,22,23,23,17,23,19,22,23,19,19,19,18,19,16,16,22,0,9,19,0,0,9,20,9,18,8,16,4,15,0,0,11,17,10,13,5,13,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1333_r22e_mba1[210] = +uint32_t rdimm_glacier_1333_r22e_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,77,0,72,0,17,16,18,17,14,17,18,19,22,18,15,18,16,19,17,13,14,16,12,14,17,11,14,0,12,5,0,0,14,5,14,8,7,5,11,2,0,0,3,3,5,3,8,2,77,0,72,0,16,16,19,16,16,18,19,18,19,19,14,18,16,18,19,16,15,16,15,16,13,13,18,0,8,15,0,0,8,16,8,15,7,13,4,12,0,0,9,14,9,11,4,11,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1600_r22e_mba1[210] = +uint32_t rdimm_glacier_1600_r22e_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,81,0,77,0,21,19,21,20,16,21,22,23,27,22,17,21,19,23,21,15,17,19,14,16,20,13,17,0,13,5,0,0,16,5,15,8,7,5,13,2,0,0,4,3,5,3,10,2,81,0,77,0,19,19,23,19,19,22,23,21,23,23,17,22,19,21,23,19,18,19,18,19,16,16,22,0,7,17,0,0,8,18,8,16,7,15,4,15,0,0,11,17,10,13,5,13,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1333_r22b_mba1[210] = +uint32_t rdimm_glacier_1333_r22b_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,69,0,16,14,16,15,12,16,17,17,21,16,12,16,14,18,16,10,12,14,10,12,15,9,12,0,12,6,0,0,15,6,14,8,8,6,11,2,0,0,3,3,5,3,8,2,73,0,69,0,14,14,17,14,14,17,17,16,17,17,12,17,14,16,17,13,13,14,13,14,11,11,16,0,8,16,0,0,8,17,8,15,7,14,4,12,0,0,9,14,9,11,4,10,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1600_r22b_mba1[210] = +uint32_t rdimm_glacier_1600_r22b_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,78,0,71,0,20,18,20,19,15,20,21,22,26,21,16,21,18,23,20,14,16,18,13,15,19,12,16,0,16,8,0,0,20,8,19,12,11,8,14,2,0,0,4,3,6,3,10,3,78,0,71,0,17,18,22,18,18,21,22,20,22,22,15,21,17,20,22,17,17,17,16,17,14,14,21,0,11,21,0,0,11,22,11,20,10,18,4,15,0,0,11,17,11,13,5,13,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1066_r44_mba1[210] = +uint32_t rdimm_glacier_1066_r44_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,0x20,0x20,0x20,0x20,0x80,0x80,0x80,0x80,0x20,0x20,0x20,0x20,0x80,0x80,0x80,0x80,0xA0,0x20,0x60,0x20,0xA0,0x80,0x90,0x80,0xA0,0x20,0x60,0x20,0xA0,0x80,0x90,0x80,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,74,0,68,0,15,14,15,14,12,15,16,16,19,15,12,15,14,17,15,11,12,14,10,12,14,9,12,0,12,7,0,0,15,7,14,9,9,7,9,1,0,0,3,2,4,3,7,2,74,0,68,0,13,14,16,14,14,16,16,15,16,16,12,16,13,15,16,13,13,13,12,13,11,11,15,0,9,15,0,0,9,16,9,15,8,14,3,10,0,0,8,12,7,9,3,9,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; //UDIMM TEMP FOR JAKE ICICLE -uint32_t udimm_glacier_1600_r10_mba0[210] = +uint32_t udimm_glacier_1600_r10_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,70,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,7,9,11,10,4,0,3,5,0,0,4,10,3,12,3,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t udimm_glacier_1600_r10_mba1[210] = +uint32_t udimm_glacier_1600_r10_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,15,13,15,14,10,15,16,17,21,15,11,15,13,18,15,9,11,13,8,10,14,7,11,0,10,2,0,0,13,2,12,5,4,2,0,0,0,0,0,0,0,0,0,0,71,0,0,0,12,13,16,13,13,16,16,15,16,17,11,16,12,15,17,12,12,13,11,12,9,10,15,0,4,14,0,0,4,15,4,13,4,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -//KG3 +//KG3 uint32_t rdimm_kg3_1333_r1_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; @@ -624,6 +626,27 @@ uint32_t rdimm_kg4_1600_r4_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100 uint32_t rdimm_kg4_1600_r4_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x40,0x80,0x00,0x00,0x00,0x00,0x40,0x80,0x40,0x80,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; +// habanero_1333 single-drop +uint32_t rdimm_habanero_1333_r10_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,86,0,0,0,7,7,7,7,7,9,7,8,10,6,14,8,9,2,3,15,15,14,12,15,17,16,14,0,12,19,0,0,9,18,4,22,7,17,0,0,0,0,0,0,0,0,0,0,80,0,0,0,12,10,13,12,9,10,11,10,14,10,13,10,14,5,12,15,12,11,12,9,13,11,9,0,10,14,0,0,11,9,11,12,10,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE}; + +uint32_t rdimm_habanero_1333_r10_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,82,0,0,0,15,15,15,12,15,15,16,16,16,15,13,16,12,12,15,13,13,12,11,6,15,11,12,0,20,7,0,0,11,11,11,9,11,10,0,0,0,0,0,0,0,0,0,0,85,0,0,0,9,13,18,14,11,16,17,17,18,19,0,18,14,17,18,15,14,4,13,11,11,12,16,0,14,25,0,0,11,22,3,20,10,19,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE}; + +uint32_t rdimm_habanero_1333_r20_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,86,0,0,0,7,7,7,7,7,9,7,8,10,6,14,8,9,2,3,15,15,14,12,15,17,16,14,0,12,19,0,0,9,18,4,22,7,17,0,0,0,0,0,0,0,0,0,0,80,0,0,0,12,10,13,12,9,10,11,10,14,10,13,10,14,5,12,15,12,11,12,9,13,11,9,0,10,14,0,0,11,9,11,12,10,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE}; + +uint32_t rdimm_habanero_1333_r20_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,82,0,0,0,15,15,15,12,15,15,16,16,16,15,13,16,12,12,15,13,13,12,11,6,15,11,12,0,20,7,0,0,11,11,11,9,11,10,0,0,0,0,0,0,0,0,0,0,85,0,0,0,9,13,18,14,11,16,17,17,18,19,0,18,14,17,18,15,14,4,13,11,11,12,16,0,14,25,0,0,11,22,3,20,10,19,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE}; + +// habanero_1333 dual-drop +uint32_t rdimm_habanero_1333_r11_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,86,0,0,0,7,7,7,7,7,9,7,8,10,6,14,8,9,2,3,15,15,14,12,15,17,16,14,0,12,19,0,0,9,18,4,22,7,17,0,0,0,0,0,0,0,0,0,0,80,0,0,0,12,10,13,12,9,10,11,10,14,10,13,10,14,5,12,15,12,11,12,9,13,11,9,0,10,14,0,0,11,9,11,12,10,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE}; + +uint32_t rdimm_habanero_1333_r11_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,82,0,0,0,15,15,15,12,15,15,16,16,16,15,13,16,12,12,15,13,13,12,11,6,15,11,12,0,20,7,0,0,11,11,11,9,11,10,0,0,0,0,0,0,0,0,0,0,85,0,0,0,9,13,18,14,11,16,17,17,18,19,0,18,14,17,18,15,14,4,13,11,11,12,16,0,14,25,0,0,11,22,3,20,10,19,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE}; + +uint32_t rdimm_habanero_1333_r22_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,86,0,0,0,7,7,7,7,7,9,7,8,10,6,14,8,9,2,3,15,15,14,12,15,17,16,14,0,12,19,0,0,9,18,4,22,7,17,0,0,0,0,0,0,0,0,0,0,80,0,0,0,12,10,13,12,9,10,11,10,14,10,13,10,14,5,12,15,12,11,12,9,13,11,9,0,10,14,0,0,11,9,11,12,10,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE}; + +uint32_t rdimm_habanero_1333_r22_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,82,0,0,0,15,15,15,12,15,15,16,16,16,15,13,16,12,12,15,13,13,12,11,6,15,11,12,0,20,7,0,0,11,11,11,9,11,10,0,0,0,0,0,0,0,0,0,0,85,0,0,0,9,13,18,14,11,16,17,17,18,19,0,18,14,17,18,15,14,4,13,11,11,12,16,0,14,25,0,0,11,22,3,20,10,19,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE}; + + + + //Base Array Which Is Used For Looper To Setup Data uint32_t base_var_array[210]; @@ -646,7 +669,7 @@ extern "C" { uint8_t l_num_ranks_per_dimm_u8array[PORT_SIZE][DIMM_SIZE]; uint8_t l_stack_type_u8array[PORT_SIZE][DIMM_SIZE]; uint8_t l_dimm_size_u8array[PORT_SIZE][DIMM_SIZE]; - // ATTR_EFF_DRAM_GEN: EMPTY = 0, DDR3 = 1, DDR4 = 2, + // ATTR_EFF_DRAM_GEN: EMPTY = 0, DDR3 = 1, DDR4 = 2, uint8_t l_dram_gen_u8; // ATTR_EFF_DIMM_TYPE: CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3, uint8_t l_dimm_type_u8; @@ -705,7 +728,7 @@ extern "C" { if ((l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) && (l_stack_type_u8array[cur_port][cur_dimm] == fapi::ENUM_ATTR_EFF_STACK_TYPE_DDP_QDP) && (l_dram_width_u8 == fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8) && (l_dimm_size_u8array[cur_port][cur_dimm] == 4)) { FAPI_INF("WARNING: Wrong Byte33 SPD detected for OLD 16G/32G CDIMM on %s PORT%d DIMM%d!", i_target_mba.toEcmdString(), cur_port, cur_dimm); FAPI_INF("WARNING: Implimenting workaround on %s PORT%d DIMM%d!", i_target_mba.toEcmdString(), cur_port, cur_dimm); - l_stack_type_modified = 1; + l_stack_type_modified = 1; l_stack_type_u8array[cur_port][cur_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE; } } @@ -742,7 +765,7 @@ extern "C" { } else if(l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM){ - memcpy(base_var_array,rdimm_glacier_1600_r22e_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1600_r22e_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); } else{ @@ -761,7 +784,7 @@ extern "C" { //FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; if( l_target_mba_pos == 0){ if ( l_mss_freq <= 1466 ) { // 1333Mbps - if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { + if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { //Removed Width Check, use settings for either x8 or x4, use 1600 settings for 1333! memcpy(base_var_array,rdimm_kg3_1333_r1_mba0,210*sizeof(uint32_t)); FAPI_INF("LRDIMM: Base - KG3 RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); @@ -786,14 +809,14 @@ extern "C" { else{ FAPI_ERR("Invalid Dimm Type KG3 FREQ %d MBA0\n",l_mss_freq); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG3_FREQ_1333Mbps); return rc; - + } } else if ( l_mss_freq <= 1733 ) { // 1600Mbps - if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { + if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { //Removed Width Check, use settings for either x8 or x4 - memcpy(base_var_array,rdimm_kg3_1600_r1_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_kg3_1600_r1_mba0,210*sizeof(uint32_t)); FAPI_INF("LRDIMM: Base - KG3 LRDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){ @@ -819,17 +842,17 @@ extern "C" { else{ FAPI_ERR("Invalid Dimm Type KG3 FREQ %d MBA0\n",l_mss_freq); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG3_FREQ_1600Mbps); return rc; - + } - }//1600 + }//1600 }//MBA0 else{ if ( l_mss_freq <= 1466 ) { // 1333Mbps - if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { + if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { //Removed Width Check, use settings for either x8 or x4, memcpy(base_var_array,rdimm_kg3_1333_r1_mba1,210*sizeof(uint32_t)); FAPI_INF("LRDIMM: Base - KG3 RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } + } else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 4)){ memcpy(base_var_array,rdimm_kg3_1333_r2e_mba1,210*sizeof(uint32_t)); FAPI_INF("KG3 r2e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); @@ -850,12 +873,12 @@ extern "C" { else{ FAPI_ERR("Invalid Dimm Type KG3 FREQ %d MBA0\n",l_mss_freq); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG3_FREQ_1333Mbps_MBA1); return rc; - + } } else if ( l_mss_freq <= 1733 ) { // 1600Mbps - if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { + if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { //Removed Width Check, use settings for either x8 or x4 memcpy(base_var_array,rdimm_kg3_1600_r1_mba1,210*sizeof(uint32_t)); FAPI_INF("LRDIMM: Base - KG3 RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); @@ -883,9 +906,9 @@ extern "C" { else{ FAPI_ERR("Invalid Dimm Type KG3 FREQ %d MBA0\n",l_mss_freq); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG3_FREQ_1600Mbps_MBA1); return rc; - + } - }//1600 + }//1600 }//MBA1 } #endif @@ -921,7 +944,7 @@ extern "C" { else{ FAPI_ERR("Invalid Dimm Type KG4 FREQ %d MBA0\n",l_mss_freq); - + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG4_FREQ_1333Mbps); return rc; } // memcpy(base_var_array,cdimm_rcb4_2r_1600_mba0,210*sizeof(uint32_t)); @@ -957,7 +980,7 @@ extern "C" { else{ FAPI_ERR("Invalid Dimm Type KG4 FREQ %d MBA0\n",l_mss_freq); - + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG4_FREQ_1600Mbps); return rc; } }//1600 @@ -965,7 +988,7 @@ extern "C" { } - else if((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM) || (l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)){ + else if((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM) || (l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)){ if(l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) { //This is a CDIMM! @@ -990,7 +1013,7 @@ extern "C" { } else{ FAPI_ERR("Invalid Dimm Type CDIMM RCB4 FREQ %d\n",l_mss_freq); - + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_B4_1600Mbps); return rc; } } @@ -1010,14 +1033,14 @@ extern "C" { } else{ FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA0\n",l_mss_freq); - + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_UDIMM_1600Mbps_MBA0); return rc; } } else{ FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA0\n",l_mss_freq); - + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_UDIMM_1600Mbps_MBA0); return rc; } } @@ -1029,14 +1052,14 @@ extern "C" { } else{ FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA1\n",l_mss_freq); - + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_UDIMM_1600Mbps_MBA1); return rc; } } else{ FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA1\n",l_mss_freq); - + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_UDIMM_1600Mbps_MBA1); return rc; } } @@ -1071,7 +1094,7 @@ extern "C" { else{ FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d MBA0\n",l_mss_freq); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA0_1333Mbps); return rc; - + } } else if ( l_mss_freq <= 1733 ) { // 1600Mbps @@ -1099,51 +1122,51 @@ extern "C" { else{ FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d MBA0\n",l_mss_freq); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA0_1600Mbps); return rc; - + } - }//1600 + }//1600 }//MBA0 else{ if ( l_mss_freq <= 1200 ) { // 1066Mbps - if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 4)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 4)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){ + if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 4)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 4)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){ memcpy(base_var_array,rdimm_glacier_1066_r44_mba1,210*sizeof(uint32_t)); + FAPI_INF("RDIMM r44 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ + memcpy(base_var_array,rdimm_glacier_1066_r40_mba1,210*sizeof(uint32_t)); FAPI_INF("RDIMM r44 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } - else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ - memcpy(base_var_array,rdimm_glacier_1066_r40_mba1,210*sizeof(uint32_t)); - FAPI_INF("RDIMM r44 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } + } else{ FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d MBA1\n",l_mss_freq); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA1_1066Mbps); return rc; - + } } else if ( l_mss_freq <= 1466 ) { // 1333Mbps - if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ - memcpy(base_var_array,rdimm_glacier_1333_r10_mba1,210*sizeof(uint32_t)); + if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ + memcpy(base_var_array,rdimm_glacier_1333_r10_mba1,210*sizeof(uint32_t)); FAPI_INF("RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } - else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){ - memcpy(base_var_array,rdimm_glacier_1333_r11_mba1,210*sizeof(uint32_t)); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){ + memcpy(base_var_array,rdimm_glacier_1333_r11_mba1,210*sizeof(uint32_t)); FAPI_INF("RDIMM r11 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } - else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 4)){ - memcpy(base_var_array,rdimm_glacier_1333_r20e_mba1,210*sizeof(uint32_t)); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 4)){ + memcpy(base_var_array,rdimm_glacier_1333_r20e_mba1,210*sizeof(uint32_t)); FAPI_INF("RDIMM r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } - else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 8)){ + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 8)){ memcpy(base_var_array,rdimm_glacier_1333_r20b_mba1,210*sizeof(uint32_t)); - FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } - else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 4)){ - memcpy(base_var_array,rdimm_glacier_1333_r22e_mba1,210*sizeof(uint32_t)); - FAPI_INF("RDIMM r22e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } - else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 8)){ - memcpy(base_var_array,rdimm_glacier_1333_r22b_mba1,210*sizeof(uint32_t)); - FAPI_INF("RDIMM r22b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } + FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 4)){ + memcpy(base_var_array,rdimm_glacier_1333_r22e_mba1,210*sizeof(uint32_t)); + FAPI_INF("RDIMM r22e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 8)){ + memcpy(base_var_array,rdimm_glacier_1333_r22b_mba1,210*sizeof(uint32_t)); + FAPI_INF("RDIMM r22b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } else if((((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 0))) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ //Use 4R MBA0 settings for CD only! memcpy(base_var_array,rdimm_glacier_1333_r40_mba0,210*sizeof(uint32_t)); @@ -1154,35 +1177,35 @@ extern "C" { else{ FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d HERE MBA1\n",l_mss_freq); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA1_1333Mbps); return rc; - + } } else if ( l_mss_freq <= 1733 ) { // 1600Mbps - if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ - memcpy(base_var_array,rdimm_glacier_1600_r10_mba1,210*sizeof(uint32_t)); + if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ + memcpy(base_var_array,rdimm_glacier_1600_r10_mba1,210*sizeof(uint32_t)); FAPI_INF("RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } - else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){ - memcpy(base_var_array,rdimm_glacier_1600_r11_mba1,210*sizeof(uint32_t)); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){ + memcpy(base_var_array,rdimm_glacier_1600_r11_mba1,210*sizeof(uint32_t)); FAPI_INF("RDIMM r11 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } - else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 4)){ - memcpy(base_var_array,rdimm_glacier_1600_r20e_mba1,210*sizeof(uint32_t)); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 4)){ + memcpy(base_var_array,rdimm_glacier_1600_r20e_mba1,210*sizeof(uint32_t)); FAPI_INF("RDIMM r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } - else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 8)){ + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 8)){ memcpy(base_var_array,rdimm_glacier_1600_r20b_mba1,210*sizeof(uint32_t)); - FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } - else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 4)){ - memcpy(base_var_array,rdimm_glacier_1600_r22e_mba1,210*sizeof(uint32_t)); + FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 4)){ + memcpy(base_var_array,rdimm_glacier_1600_r22e_mba1,210*sizeof(uint32_t)); FAPI_INF("RDIMM r22e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } - else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 8)){ - memcpy(base_var_array,rdimm_glacier_1600_r22b_mba1,210*sizeof(uint32_t)); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 8)){ + memcpy(base_var_array,rdimm_glacier_1600_r22b_mba1,210*sizeof(uint32_t)); FAPI_INF("RDIMM r22b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } + } else if((((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 0))) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ //Use 4R MBA0 1333 settings for CD only! memcpy(base_var_array,rdimm_glacier_1333_r40_mba0,210*sizeof(uint32_t)); @@ -1191,7 +1214,7 @@ extern "C" { else{ FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d MBA1\n",l_mss_freq); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA1_1600Mbps); return rc; - + } }//1600 }//MBA1 @@ -1224,7 +1247,7 @@ extern "C" { else{ FAPI_ERR("Invalid Dimm Type LRDIMM FREQ %d HERE MBA1\n",l_mss_freq); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_LRDIMM_MBA1_1333Mbps); return rc; - + } } else if ( l_mss_freq <= 1733 ) { // 1600Mbps @@ -1239,7 +1262,7 @@ extern "C" { else{ FAPI_ERR("Invalid Dimm Type LRDIMM FREQ %d MBA1\n",l_mss_freq); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_LRDIMM_MBA1_1600Mbps); return rc; - + } } }//MBA1 @@ -1256,7 +1279,7 @@ extern "C" { uint32_t *p_b_var_array = &base_var_array[0]; - uint32_t *var_array_p_array[] = {p_1066_mba1_array, p_1333_x4_mba1_array, p_1333_x8_mba1_array, + uint32_t *var_array_p_array[] = {p_1066_mba1_array, p_1333_x4_mba1_array, p_1333_x8_mba1_array, p_1600_x4_mba1_array, p_1600_x8_mba1_array}; rc = mss_lrdimm_rewrite_odt(i_target_mba, p_b_var_array, var_array_p_array); @@ -1264,7 +1287,7 @@ extern "C" { if(rc) { FAPI_ERR("FAILED LRDIMM rewrite ODT_RD"); - + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_LRDIMM_ODT_RD); return rc; } } @@ -1272,7 +1295,7 @@ extern "C" { else{ FAPI_ERR("Invalid Dimm Type of %d", l_dimm_type_u8); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_DIMM_TYPE); return rc; - + } // Now Set All The Attributes @@ -1280,15 +1303,15 @@ extern "C" { attr_eff_dimm_rcd_ibt[0][0] = base_var_array[i++]; // keep 0 attr_eff_dimm_rcd_ibt[0][1] = base_var_array[i++]; // keep 1 attr_eff_dimm_rcd_ibt[1][0] = base_var_array[i++]; // keep 2 - attr_eff_dimm_rcd_ibt[1][1] = base_var_array[i++]; // keep 3 + attr_eff_dimm_rcd_ibt[1][1] = base_var_array[i++]; // keep 3 attr_eff_dimm_rcd_mirror_mode[0][0] = base_var_array[i++]; // keep 4 attr_eff_dimm_rcd_mirror_mode[0][1] = base_var_array[i++]; // keep 5 attr_eff_dimm_rcd_mirror_mode[1][0] = base_var_array[i++]; // keep 6 attr_eff_dimm_rcd_mirror_mode[1][1] = base_var_array[i++]; // keep 7 - //Fix for VPD Mode for lab rdimm - if(((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) || ( l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4) )){ + //Fix for VPD Mode for lab rdimm + if(((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) || ( l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4) ) && (l_lab_raw_card_u8 != fapi::ENUM_ATTR_LAB_ONLY_RAW_CARD_KG3)){ FAPI_INF("RON i %d SHOULD NOT BE HERE\n",i); attr_vpd_dram_ron[0][0] = base_var_array[i++]; attr_vpd_dram_ron[0][1] = base_var_array[i++]; @@ -1717,8 +1740,8 @@ extern "C" { //Now Setup the RCD - Done Here to Steal Code From Anuwats Version Of Eff Config Termination - if ( l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4 && - ( (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || + if ( l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4 && + ( (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) ) { rc = mss_create_rcd_ddr4(i_target_mba); @@ -1730,7 +1753,7 @@ extern "C" { if (rc) { FAPI_ERR("Setting DDR4 RCD words failed \n"); - + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_DDR4_RCD); return rc; } @@ -1746,7 +1769,7 @@ extern "C" { if(l_dram_width_u8 == 4){ l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = 0x0005050080210000LL; } - else { + else { l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = 0x0005550080210000LL; } @@ -1757,10 +1780,10 @@ extern "C" { } else { l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = 0x0000000000000000LL; } - l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_mss_freq_mask; - l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_mss_volt_mask; - l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_rcd_ibt_mask; - l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_rcd_mirror_mode_mask; + l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_mss_freq_mask; + l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_mss_volt_mask; + l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_rcd_ibt_mask; + l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_rcd_mirror_mode_mask; if ( l_mss_freq <= 933 ) { // 800Mbps l_mss_freq_mask = 0x0000000000000000LL; } else if ( l_mss_freq <= 1200 ) { // 1066Mbps @@ -1777,11 +1800,11 @@ extern "C" { l_mss_volt_mask = 0x0000000000000000LL; } else if ( l_mss_volt >= 1270 ) { // 1.35V l_mss_volt_mask = 0x0000000000010000LL; - } else { // 1.2V + } else { // 1.2V FAPI_ERR("Invalid RDIMM ATTR_MSS_VOLT = %d on %s!", l_mss_volt, i_target_mba.toEcmdString()); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_VOLT); return rc; - - } + + } if ( attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF ) { l_rcd_ibt_mask = 0x0000000070000000LL; } else if ( attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100 ) { @@ -1795,7 +1818,7 @@ extern "C" { } else { FAPI_ERR("Invalid DIMM_RCD_IBT on %s!", i_target_mba.toEcmdString()); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_DIMM_RCD_IBT); return rc; - + } if ( attr_eff_dimm_rcd_mirror_mode[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF ) { l_rcd_mirror_mode_mask = 0x0000000000000000LL; @@ -1804,13 +1827,13 @@ extern "C" { } else { FAPI_ERR("Invalid DIMM_RCD_MIRROR_MODE on %s!", i_target_mba.toEcmdString()); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_DIMM_RCD_MIRROR_MODE); return rc; - - + + } - l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_mss_freq_mask; - l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_mss_volt_mask; - l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_rcd_ibt_mask; - l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_rcd_mirror_mode_mask; + l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_mss_freq_mask; + l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_mss_volt_mask; + l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_rcd_ibt_mask; + l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_rcd_mirror_mode_mask; } } } @@ -1925,7 +1948,7 @@ extern "C" { attr_eff_wlo[1] = (uint8_t)0; attr_eff_gpo[0] = (uint8_t)5; attr_eff_gpo[1] = (uint8_t)5; -*/ +*/ if ( l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4 ) { // Set for CDIMM B4 attr_eff_rlo[0] = (uint8_t)0; @@ -1955,13 +1978,13 @@ extern "C" { attr_eff_rlo[0] = (uint8_t)5; attr_eff_rlo[1] = (uint8_t)5; attr_eff_wlo[0] = (uint8_t)1; - attr_eff_wlo[1] = (uint8_t)1; - } + attr_eff_wlo[1] = (uint8_t)1; + } else { attr_eff_rlo[0] = (uint8_t)6; attr_eff_rlo[1] = (uint8_t)6; attr_eff_wlo[0] = (uint8_t)255; // WLO = -1, 2's complement - attr_eff_wlo[1] = (uint8_t)255; + attr_eff_wlo[1] = (uint8_t)255; } attr_eff_gpo[0] = (uint8_t)7; attr_eff_gpo[1] = (uint8_t)7; @@ -1970,9 +1993,9 @@ extern "C" { else{ FAPI_ERR("Invalid Card Type RLO Settings \n"); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_CARD_TYPE_RLO); return rc; + - - } + } @@ -2014,9 +2037,9 @@ extern "C" { // Set attributes rc = FAPI_ATTR_SET(ATTR_MSS_CAL_STEP_ENABLE, &i_target_mba, l_attr_mss_cal_step_enable); if(rc) return rc; - if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) { // do not override DDR4 RCD + if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) { // do not override DDR4 RCD rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc; - } + } rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_IBT, &i_target_mba, attr_eff_dimm_rcd_ibt); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_MIRROR_MODE, &i_target_mba, attr_eff_dimm_rcd_mirror_mode); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, attr_eff_cen_rd_vref); if(rc) return rc; @@ -2053,7 +2076,7 @@ extern "C" { || (l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4) ){ FAPI_INF("IN RDIMM ATTR SETTING\n"); rc = FAPI_ATTR_SET(ATTR_MSS_CAL_STEP_ENABLE, &i_target_mba, l_attr_mss_cal_step_enable); if(rc) return rc; - if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) { // do not override DDR4 RCD + if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) { // do not override DDR4 RCD rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc; } rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_IBT, &i_target_mba, attr_eff_dimm_rcd_ibt); if(rc) return rc; @@ -2213,12 +2236,12 @@ extern "C" { if(l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) - { + { if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) - { + { rc = mss_lrdimm_term_atts(i_target_mba); } - else + else { rc = mss_lrdimm_ddr4_term_atts(i_target_mba); } @@ -2226,7 +2249,7 @@ extern "C" { if (rc) { FAPI_ERR("Setting LR term atts failed \n"); - + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_SETTING_LRDIMM_TERM_ATTRS); return rc; } } @@ -2262,7 +2285,7 @@ extern "C" { { FAPI_ERR("Error retrieving assodiated dimms"); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_ERROR_RETRIEVING_DIMMS); return rc; - + break; } //------------------------------------------------------------------------------ @@ -2378,7 +2401,6 @@ extern "C" { return rc; } -#ifndef CONFIG_VPD_GETMACRO_USE_EFF_ATTR uint32_t slope = 0x0000c1be; uint32_t intercept = 0x0000c06a; rc = FAPI_ATTR_SET(ATTR_CDIMM_VPD_MASTER_POWER_SLOPE, &target_chip, slope); @@ -2392,7 +2414,6 @@ extern "C" { rc = FAPI_ATTR_SET(ATTR_CDIMM_VPD_SUPPLIER_POWER_INTERCEPT, &target_chip, intercept); if (rc) return rc; -#endif } if(rc) break; //////////////////////////////////////////////////////////////////////////////////////////// |
