diff options
Diffstat (limited to 'src/usr/vpd/spdDDR4.H')
| -rwxr-xr-x | src/usr/vpd/spdDDR4.H | 140 |
1 files changed, 69 insertions, 71 deletions
diff --git a/src/usr/vpd/spdDDR4.H b/src/usr/vpd/spdDDR4.H index b71eb92e1..b29a1043f 100755 --- a/src/usr/vpd/spdDDR4.H +++ b/src/usr/vpd/spdDDR4.H @@ -69,76 +69,76 @@ const KeywordData ddr4Data[] = // ------------------------------------------------------------------------------------------ // // Normal fields supported on both DDR3 and DDR4 - { SPD_BYTES_TOTAL, 0x00, 0x01, 0x70, 0x04, false, false, NA }, - { SPD_BYTES_USED, 0x00, 0x01, 0x0F, 0x00, false, false, NA }, - { SPD_MAJOR_REVISION, 0x01, 0x01, 0xF0, 0x04, false, false, NA }, - { SPD_MINOR_REVISION, 0x01, 0x01, 0x0F, 0x00, false, false, NA }, - { BASIC_MEMORY_TYPE, 0x02, 0x01, 0x00, 0x00, false, false, NA }, - { CUSTOM, 0x03, 0x01, 0x80, 0x07, false, false, NA }, - { MODULE_TYPE, 0x03, 0x01, 0x0F, 0x00, false, false, NA }, - { DENSITY, 0x04, 0x01, 0x0F, 0x00, false, false, NA }, - { ROW_ADDRESS, 0x05, 0x01, 0x38, 0x03, false, false, NA }, - { COL_ADDRESS, 0x05, 0x01, 0x07, 0x00, false, false, NA }, - { MODULE_RANKS, 0x0c, 0x01, 0x38, 0x03, false, false, NA }, - { MODULE_DRAM_WIDTH, 0x0c, 0x01, 0x07, 0x00, false, false, NA }, - { MODULE_MEMORY_BUS_WIDTH, 0x0d, 0x01, 0x1f, 0x00, false, false, NA }, - { MODULE_MEMORY_BUS_WIDTH_EXT, 0x0d, 0x01, 0x18, 0x03, false, false, NA }, - { MODULE_MEMORY_BUS_WIDTH_PRI, 0x0d, 0x01, 0x07, 0x00, false, false, NA }, - { TCK_MIN, 0x12, 0x01, 0x00, 0x00, false, false, NA }, - { MIN_CAS_LATENCY, 0x18, 0x01, 0x00, 0x00, false, false, NA }, - { TRCD_MIN, 0x19, 0x01, 0x00, 0x00, false, false, NA }, - { TRP_MIN, 0x1a, 0x01, 0x00, 0x00, false, false, NA }, - { TRC_MIN, 0x1b, 0x02, 0xF0, 0x04, true, false, NA }, - { TRAS_MIN, 0x1b, 0x02, 0x0F, 0x00, false, false, NA }, - { TFAW_MIN, 0x24, 0x02, 0x0F, 0x00, false, false, NA }, - { SDRAM_OPTIONAL_FEATURES, 0x07, 0x01, 0x00, 0x00, false, false, NA }, - { SDRAM_THERMAL_REFRESH_OPTIONS, 0x08, 0x01, 0x00, 0x00, false, false, NA }, - { MODULE_THERMAL_SENSOR, 0x0e, 0x01, 0x00, 0x00, false, false, NA }, - { THERMAL_SENSOR_PRESENT, 0x0e, 0x01, 0x80, 0x07, false, false, NA }, - { SDRAM_DEVICE_TYPE , 0x06, 0x01, 0x80, 0x07, false, false, NA }, - { SDRAM_DIE_COUNT, 0x06, 0x01, 0x70, 0x04, false, false, NA }, - { SDRAM_DEVICE_TYPE_SIGNAL_LOADING, 0x06, 0x01, 0x03, 0x00, false, false, NA }, - { TCKMIN_FINE_OFFSET, 0x7d, 0x01, 0x00, 0x00, false, false, NA }, - { TAAMIN_FINE_OFFSET, 0x7b, 0x01, 0x00, 0x00, false, false, NA }, - { TRCDMIN_FINE_OFFSET, 0x7a, 0x01, 0x00, 0x00, false, false, NA }, - { TRPMIN_FINE_OFFSET, 0x79, 0x01, 0x00, 0x00, false, false, NA }, - { TRCMIN_FINE_OFFSET, 0x78, 0x01, 0x00, 0x00, false, false, NA }, - // Note - All data below 128 is common across all DDR4 DIMMs, even DDIMM - { MODULE_TYPE_SPECIFIC_SECTION, 0x80, 0x80, 0x00, 0x00, false, false, NA }, - { MODULE_MANUFACTURER_ID, 0x141, 0x02, 0x00, 0x00, true, false, NA }, - { MODULE_MANUFACTURING_LOCATION, 0x142, 0x01, 0x00, 0x00, false, false, NA }, - { MODULE_MANUFACTURING_DATE, 0x143, 0x02, 0x00, 0x00, false, false, NA }, - { MODULE_SERIAL_NUMBER, 0x145, 0x04, 0x00, 0x00, false, false, NA }, - { MODULE_PART_NUMBER, 0x149, 0x14, 0x00, 0x00, false, false, NA }, - { DRAM_MANUFACTURER_ID, 0x15f, 0x02, 0x00, 0x00, true, false, NA }, - { MANUFACTURER_SPECIFIC_DATA, 0x161, 0x1d, 0x00, 0x00, false, false, NA }, - { DIMM_BAD_DQ_DATA, 0x180, 0x50, 0x00, 0x00, false, true, NA }, - { MODULE_REVISION_CODE, 0x15d, 0x01, 0x00, 0x00, false, false, NA }, + { SPD_BYTES_TOTAL, 0x00, 0x01, 0x70, 0x04, false, false, ALL }, + { SPD_BYTES_USED, 0x00, 0x01, 0x0F, 0x00, false, false, ALL }, + { SPD_MAJOR_REVISION, 0x01, 0x01, 0xF0, 0x04, false, false, ALL }, + { SPD_MINOR_REVISION, 0x01, 0x01, 0x0F, 0x00, false, false, ALL }, + { BASIC_MEMORY_TYPE, 0x02, 0x01, 0x00, 0x00, false, false, ALL }, + { CUSTOM, 0x03, 0x01, 0x80, 0x07, false, false, ALL }, + { MODULE_TYPE, 0x03, 0x01, 0x0F, 0x00, false, false, ALL }, + { DENSITY, 0x04, 0x01, 0x0F, 0x00, false, false, ALL }, + { ROW_ADDRESS, 0x05, 0x01, 0x38, 0x03, false, false, ALL }, + { COL_ADDRESS, 0x05, 0x01, 0x07, 0x00, false, false, ALL }, + { MODULE_RANKS, 0x0c, 0x01, 0x38, 0x03, false, false, ALL }, + { MODULE_DRAM_WIDTH, 0x0c, 0x01, 0x07, 0x00, false, false, ALL }, + { MODULE_MEMORY_BUS_WIDTH, 0x0d, 0x01, 0x1f, 0x00, false, false, ALL }, + { MODULE_MEMORY_BUS_WIDTH_EXT, 0x0d, 0x01, 0x18, 0x03, false, false, ALL }, + { MODULE_MEMORY_BUS_WIDTH_PRI, 0x0d, 0x01, 0x07, 0x00, false, false, ALL }, + { TCK_MIN, 0x12, 0x01, 0x00, 0x00, false, false, ALL }, + { MIN_CAS_LATENCY, 0x18, 0x01, 0x00, 0x00, false, false, ALL }, + { TRCD_MIN, 0x19, 0x01, 0x00, 0x00, false, false, ALL }, + { TRP_MIN, 0x1a, 0x01, 0x00, 0x00, false, false, ALL }, + { TRC_MIN, 0x1b, 0x02, 0xF0, 0x04, true, false, ALL }, + { TRAS_MIN, 0x1b, 0x02, 0x0F, 0x00, false, false, ALL }, + { TFAW_MIN, 0x24, 0x02, 0x0F, 0x00, false, false, ALL }, + { SDRAM_OPTIONAL_FEATURES, 0x07, 0x01, 0x00, 0x00, false, false, ALL }, + { SDRAM_THERMAL_REFRESH_OPTIONS, 0x08, 0x01, 0x00, 0x00, false, false, ALL }, + { MODULE_THERMAL_SENSOR, 0x0e, 0x01, 0x00, 0x00, false, false, ALL }, + { THERMAL_SENSOR_PRESENT, 0x0e, 0x01, 0x80, 0x07, false, false, ALL }, + { SDRAM_DEVICE_TYPE , 0x06, 0x01, 0x80, 0x07, false, false, ALL }, + { SDRAM_DIE_COUNT, 0x06, 0x01, 0x70, 0x04, false, false, ALL }, + { SDRAM_DEVICE_TYPE_SIGNAL_LOADING, 0x06, 0x01, 0x03, 0x00, false, false, ALL }, + { TCKMIN_FINE_OFFSET, 0x7d, 0x01, 0x00, 0x00, false, false, ALL }, + { TAAMIN_FINE_OFFSET, 0x7b, 0x01, 0x00, 0x00, false, false, ALL }, + { TRCDMIN_FINE_OFFSET, 0x7a, 0x01, 0x00, 0x00, false, false, ALL }, + { TRPMIN_FINE_OFFSET, 0x79, 0x01, 0x00, 0x00, false, false, ALL }, + { TRCMIN_FINE_OFFSET, 0x78, 0x01, 0x00, 0x00, false, false, ALL }, + // Note - All data below 128 is common across all DDR4 DIMMs, except DDIMM + { MODULE_TYPE_SPECIFIC_SECTION, 0x80, 0x80, 0x00, 0x00, false, false, ALL }, + { MODULE_MANUFACTURER_ID, 0x141, 0x02, 0x00, 0x00, true, false, ALL }, + { MODULE_MANUFACTURING_LOCATION, 0x142, 0x01, 0x00, 0x00, false, false, ALL }, + { MODULE_MANUFACTURING_DATE, 0x143, 0x02, 0x00, 0x00, false, false, ALL }, + { MODULE_SERIAL_NUMBER, 0x145, 0x04, 0x00, 0x00, false, false, ALL }, + { MODULE_PART_NUMBER, 0x149, 0x14, 0x00, 0x00, false, false, ALL }, + { DRAM_MANUFACTURER_ID, 0x15f, 0x02, 0x00, 0x00, true, false, ALL }, + { MANUFACTURER_SPECIFIC_DATA, 0x161, 0x1d, 0x00, 0x00, false, false, ALL }, + { DIMM_BAD_DQ_DATA, 0x180, 0x50, 0x00, 0x00, false, true, ALL }, + { MODULE_REVISION_CODE, 0x15d, 0x01, 0x00, 0x00, false, false, ALL }, // Normal fields supported on DDR4 only - { BANK_GROUP_BITS, 0x04, 0x01, 0xC0, 0x06, false, false, NA }, - { BANK_ADDRESS_BITS_DDR4, 0x04, 0x01, 0x30, 0x04, false, false, NA }, - { MODULE_NOMINAL_VOLTAGE_DDR4, 0x0b, 0x01, 0x3F, 0x00, false, false, NA }, - { TIMEBASES_MTB, 0x11, 0x01, 0x0C, 0x02, false, false, NA }, - { TIMEBASES_FTB, 0x11, 0x01, 0x03, 0x00, false, false, NA }, - { TCK_MAX, 0x13, 0x01, 0x00, 0x00, false, false, NA }, - { CAS_LATENCIES_SUPPORTED_DDR4, 0x17, 0x04, 0x00, 0x00, true, false, NA }, - { TRFC1_MIN, 0x1f, 0x02, 0x00, 0x00, true, false, NA }, - { TRFC2_MIN, 0x21, 0x02, 0x00, 0x00, true, false, NA }, - { TRFC4_MIN, 0x23, 0x02, 0x00, 0x00, true, false, NA }, - { TRRDS_MIN, 0x26, 0x01, 0x00, 0x00, false, false, NA }, - { TRRDL_MIN, 0x27, 0x01, 0x00, 0x00, false, false, NA }, - { TCCDL_MIN, 0x28, 0x01, 0x00, 0x00, false, false, NA }, - { CONNECTOR_SDRAM_MAP, 0x3C, 0x12, 0x00, 0x00, false, false, NA }, - { TCCDL_FINE_OFFSET, 0x75, 0x01, 0x00, 0x00, false, false, NA }, - { TRRDL_FINE_OFFSET, 0x76, 0x01, 0x00, 0x00, false, false, NA }, - { TRRDS_FINE_OFFSET, 0x77, 0x01, 0x00, 0x00, false, false, NA }, - { TCKMAX_FINE_OFFSET, 0x7c, 0x01, 0x00, 0x00, false, false, NA }, - { BASE_CONFIG_CRC, 0x7f, 0x02, 0x00, 0x00, true, false, NA }, - { DRAM_STEPPING, 0x160, 0x01, 0x00, 0x00, false, false, NA }, - { MANUFACTURING_SECTION_CRC, 0x17f, 0x02, 0x00, 0x00, true, false, NA }, - { NVM_INIT_TIME, 0xCB, 0x01, 0x00, 0x00, false, false, NA }, - { RAW_MODULE_PRODUCT_ID, 0xc0, 0x02, 0x00, 0x00, false, false, NA }, - { RAW_MODULE_MANUFACTURER_ID, 0x140, 0x02, 0x00, 0x00, false, false, NA }, + { BANK_GROUP_BITS, 0x04, 0x01, 0xC0, 0x06, false, false, ALL }, + { BANK_ADDRESS_BITS_DDR4, 0x04, 0x01, 0x30, 0x04, false, false, ALL }, + { MODULE_NOMINAL_VOLTAGE_DDR4, 0x0b, 0x01, 0x3F, 0x00, false, false, ALL }, + { TIMEBASES_MTB, 0x11, 0x01, 0x0C, 0x02, false, false, ALL }, + { TIMEBASES_FTB, 0x11, 0x01, 0x03, 0x00, false, false, ALL }, + { TCK_MAX, 0x13, 0x01, 0x00, 0x00, false, false, ALL }, + { CAS_LATENCIES_SUPPORTED_DDR4, 0x17, 0x04, 0x00, 0x00, true, false, ALL }, + { TRFC1_MIN, 0x1f, 0x02, 0x00, 0x00, true, false, ALL }, + { TRFC2_MIN, 0x21, 0x02, 0x00, 0x00, true, false, ALL }, + { TRFC4_MIN, 0x23, 0x02, 0x00, 0x00, true, false, ALL }, + { TRRDS_MIN, 0x26, 0x01, 0x00, 0x00, false, false, ALL }, + { TRRDL_MIN, 0x27, 0x01, 0x00, 0x00, false, false, ALL }, + { TCCDL_MIN, 0x28, 0x01, 0x00, 0x00, false, false, ALL }, + { CONNECTOR_SDRAM_MAP, 0x3C, 0x12, 0x00, 0x00, false, false, ALL }, + { TCCDL_FINE_OFFSET, 0x75, 0x01, 0x00, 0x00, false, false, ALL }, + { TRRDL_FINE_OFFSET, 0x76, 0x01, 0x00, 0x00, false, false, ALL }, + { TRRDS_FINE_OFFSET, 0x77, 0x01, 0x00, 0x00, false, false, ALL }, + { TCKMAX_FINE_OFFSET, 0x7c, 0x01, 0x00, 0x00, false, false, ALL }, + { BASE_CONFIG_CRC, 0x7f, 0x02, 0x00, 0x00, true, false, ALL }, + { DRAM_STEPPING, 0x160, 0x01, 0x00, 0x00, false, false, ALL }, + { MANUFACTURING_SECTION_CRC, 0x17f, 0x02, 0x00, 0x00, true, false, ALL }, + { NVM_INIT_TIME, 0xCB, 0x01, 0x00, 0x00, false, false, ALL }, + { RAW_MODULE_PRODUCT_ID, 0xc0, 0x02, 0x00, 0x00, false, false, ALL }, + { RAW_MODULE_MANUFACTURER_ID, 0x140, 0x02, 0x00, 0x00, false, false, ALL }, // Module Specific fields supported on both DDR3 and DDR4 { MODSPEC_COM_NOM_HEIGHT_MAX, 0x80, 0x01, 0x1f, 0x00, false, false, ALL }, { MODSPEC_COM_MAX_THICK_BACK, 0x81, 0x01, 0xf0, 0x04, false, false, ALL }, @@ -186,8 +186,6 @@ const KeywordData ddr4Data[] = { LRMM_ODT_RTT_PARK_2400_3200, 0x9a, 0x01, 0x00, 0x00, false, false, LRMM }, { RMM_CRC, 0xff, 0x02, 0x00, 0x00, true, false, RMM }, { LRMM_CRC, 0xff, 0x02, 0x00, 0x00, true, false, LRMM }, - { OCMB_MODULE_PART_NUMBER, 0x209, 0x30, 0x00, 0x00, false, false, DDIMM }, - { OCMB_MODULE_SERIAL_NUMBER, 0x205, 0x04, 0x00, 0x00, false, false, DDIMM }, { ENTIRE_SPD, 0x00, 0x200, 0x00, 0x00, false, false, ALL }, //--------------------------------------------------------------------------------------- }; |
