1 files changed, 384 insertions, 0 deletions
diff --git a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
index 60b92a9fe..40b269637 100644
--- a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
@@ -326,6 +326,102 @@
         <default>0</default>
     </attribute>
     <!-- End pm_attributes_all_plat.xml -->
+
+    <!-- PROC_PCIE_ attributes -->
+    <attribute>
+        <id>PROC_PCIE_IOP_G2_PLL_CONTROL0</id>
+        <default>
+            0x18F4,0x18F4
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_G3_PLL_CONTROL0</id>
+        <default>
+            0x086C,0x086C
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_PCS_CONTROL0</id>
+        <default>
+            0x3AE8,0x3AE8
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_PCS_CONTROL1</id>
+        <default>
+            0x5CB9,0x5CB9
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0</id>
+        <default>
+            0x146,0x146
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1</id>
+        <default>
+            0x6D7,0x6D7
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_RX_PEAK</id>
+        <default>
+            0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_RX_SDL</id>
+        <default>
+            0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_RX_VGA_CONTROL2</id>
+        <default>
+            0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_TX_BWLOSS1</id>
+        <default>
+            0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_TX_FIFO_OFFSET</id>
+        <default>
+            0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_TX_RCVRDETCNTL</id>
+        <default>
+            0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_ZCAL_CONTROL</id>
+        <default>
+            0x000,0x000
+        </default>
+    </attribute>
+    <!-- End PROC_PCIE_ attributes -->
+
+    <!-- The default value of the following three attributes are written by -->
+    <!-- the FSP. They are included here because VBU/VPO uses faked PNOR.   -->
+    <attribute>
+        <id>PROC_PCIE_IOP_CONFIG</id>
+        <default>0</default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_SWAP</id>
+        <default>0</default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_PHB_ACTIVE</id>
+        <default>0xE0</default>
+    </attribute>
 </targetInstance>
 
 <!-- Murano n0p0 EX units -->
@@ -927,6 +1023,102 @@
         <default>0</default>
     </attribute>
     <!-- End pm_attributes_all_plat.xml -->
+
+    <!-- PROC_PCIE_ attributes -->
+    <attribute>
+        <id>PROC_PCIE_IOP_G2_PLL_CONTROL0</id>
+        <default>
+            0x18F4,0x18F4
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_G3_PLL_CONTROL0</id>
+        <default>
+            0x086C,0x086C
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_PCS_CONTROL0</id>
+        <default>
+            0x3AE8,0x3AE8
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_PCS_CONTROL1</id>
+        <default>
+            0x5CB9,0x5CB9
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0</id>
+        <default>
+            0x146,0x146
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1</id>
+        <default>
+            0x6D7,0x6D7
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_RX_PEAK</id>
+        <default>
+            0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_RX_SDL</id>
+        <default>
+            0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_RX_VGA_CONTROL2</id>
+        <default>
+            0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_TX_BWLOSS1</id>
+        <default>
+            0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_TX_FIFO_OFFSET</id>
+        <default>
+            0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_TX_RCVRDETCNTL</id>
+        <default>
+            0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_ZCAL_CONTROL</id>
+        <default>
+            0x000,0x000
+        </default>
+    </attribute>
+    <!-- End PROC_PCIE_ attributes -->
+
+    <!-- The default value of the following three attributes are written by -->
+    <!-- the FSP. They are included here because VBU/VPO uses faked PNOR.   -->
+    <attribute>
+        <id>PROC_PCIE_IOP_CONFIG</id>
+        <default>0</default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_SWAP</id>
+        <default>0</default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_PHB_ACTIVE</id>
+        <default>0xE0</default>
+    </attribute>
 </targetInstance>
 
 <!-- Murano n0p1 EX units -->
@@ -1529,6 +1721,102 @@
         <default>0</default>
     </attribute>
     <!-- End pm_attributes_all_plat.xml -->
+
+    <!-- PROC_PCIE_ attributes -->
+    <attribute>
+        <id>PROC_PCIE_IOP_G2_PLL_CONTROL0</id>
+        <default>
+            0x18F4,0x18F4
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_G3_PLL_CONTROL0</id>
+        <default>
+            0x086C,0x086C
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_PCS_CONTROL0</id>
+        <default>
+            0x3AE8,0x3AE8
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_PCS_CONTROL1</id>
+        <default>
+            0x5CB9,0x5CB9
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0</id>
+        <default>
+            0x146,0x146
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1</id>
+        <default>
+            0x6D7,0x6D7
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_RX_PEAK</id>
+        <default>
+            0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_RX_SDL</id>
+        <default>
+            0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_RX_VGA_CONTROL2</id>
+        <default>
+            0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_TX_BWLOSS1</id>
+        <default>
+            0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_TX_FIFO_OFFSET</id>
+        <default>
+            0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_TX_RCVRDETCNTL</id>
+        <default>
+            0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_ZCAL_CONTROL</id>
+        <default>
+            0x000,0x000
+        </default>
+    </attribute>
+    <!-- End PROC_PCIE_ attributes -->
+
+    <!-- The default value of the following three attributes are written by -->
+    <!-- the FSP. They are included here because VBU/VPO uses faked PNOR.   -->
+    <attribute>
+        <id>PROC_PCIE_IOP_CONFIG</id>
+        <default>0</default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_SWAP</id>
+        <default>0</default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_PHB_ACTIVE</id>
+        <default>0xE0</default>
+    </attribute>
 </targetInstance>
 
 <!-- Murano n0p2 EX units -->
@@ -2132,6 +2420,102 @@
         <default>0</default>
     </attribute>
     <!-- End pm_attributes_all_plat.xml -->
+
+    <!-- PROC_PCIE_ attributes -->
+    <attribute>
+        <id>PROC_PCIE_IOP_G2_PLL_CONTROL0</id>
+        <default>
+            0x18F4,0x18F4
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_G3_PLL_CONTROL0</id>
+        <default>
+            0x086C,0x086C
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_PCS_CONTROL0</id>
+        <default>
+            0x3AE8,0x3AE8
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_PCS_CONTROL1</id>
+        <default>
+            0x5CB9,0x5CB9
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0</id>
+        <default>
+            0x146,0x146
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1</id>
+        <default>
+            0x6D7,0x6D7
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_RX_PEAK</id>
+        <default>
+            0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_RX_SDL</id>
+        <default>
+            0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_RX_VGA_CONTROL2</id>
+        <default>
+            0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_TX_BWLOSS1</id>
+        <default>
+            0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_TX_FIFO_OFFSET</id>
+        <default>
+            0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_TX_RCVRDETCNTL</id>
+        <default>
+            0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151
+        </default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_ZCAL_CONTROL</id>
+        <default>
+            0x000,0x000
+        </default>
+    </attribute>
+    <!-- End PROC_PCIE_ attributes -->
+
+    <!-- The default value of the following three attributes are written by -->
+    <!-- the FSP. They are included here because VBU/VPO uses faked PNOR.   -->
+    <attribute>
+        <id>PROC_PCIE_IOP_CONFIG</id>
+        <default>0</default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_SWAP</id>
+        <default>0</default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_PHB_ACTIVE</id>
+        <default>0xE0</default>
+    </attribute>
 </targetInstance>
 
 <!-- Murano n0p3 EX units -->