diff options
Diffstat (limited to 'src/usr/isteps/istep10')
-rw-r--r-- | src/usr/isteps/istep10/call_host_rng_bist.C | 114 | ||||
-rw-r--r-- | src/usr/isteps/istep10/call_host_set_voltages.C | 133 | ||||
-rw-r--r-- | src/usr/isteps/istep10/call_proc_abus_scominit.C | 169 | ||||
-rw-r--r-- | src/usr/isteps/istep10/call_proc_cen_ref_clk_enable.C | 302 | ||||
-rw-r--r-- | src/usr/isteps/istep10/call_proc_chiplet_enable_ridi.C | 111 | ||||
-rw-r--r-- | src/usr/isteps/istep10/call_proc_chiplet_scominit.C | 149 | ||||
-rw-r--r-- | src/usr/isteps/istep10/call_proc_enable_osclite.C | 96 | ||||
-rw-r--r-- | src/usr/isteps/istep10/call_proc_npu_scominit.C | 117 | ||||
-rw-r--r-- | src/usr/isteps/istep10/call_proc_obus_scominit.C | 123 | ||||
-rw-r--r-- | src/usr/isteps/istep10/call_proc_pcie_scominit.C | 144 | ||||
-rw-r--r-- | src/usr/isteps/istep10/call_proc_scomoverride_chiplets.C | 129 | ||||
-rw-r--r-- | src/usr/isteps/istep10/host_proc_pcie_scominit.C | 816 | ||||
-rw-r--r-- | src/usr/isteps/istep10/host_proc_pcie_scominit.H | 147 | ||||
-rw-r--r-- | src/usr/isteps/istep10/makefile | 68 |
14 files changed, 2618 insertions, 0 deletions
diff --git a/src/usr/isteps/istep10/call_host_rng_bist.C b/src/usr/isteps/istep10/call_host_rng_bist.C new file mode 100644 index 000000000..b1ccc5144 --- /dev/null +++ b/src/usr/isteps/istep10/call_host_rng_bist.C @@ -0,0 +1,114 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/istep10/call_host_rng_bist.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/** + @file call_host_rng_bist.C + * + * Support file for IStep: nest_chiplets + * Nest Chiplets + * + * HWP_IGNORE_VERSION_CHECK + * + */ +/******************************************************************************/ +// Includes +/******************************************************************************/ +#include <stdint.h> + +#include <trace/interface.H> +#include <initservice/taskargs.H> +#include <errl/errlentry.H> + +#include <isteps/hwpisteperror.H> +#include <errl/errludtarget.H> + +#include <initservice/isteps_trace.H> +#include <initservice/initserviceif.H> + +// targeting support +#include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> + +// MVPD +#include <devicefw/userif.H> +#include <vpd/mvpdenums.H> + +#include <config.h> +#include <fapi2/plat_hwp_invoker.H> +#include <p9_rng_init_phase1.H> + +namespace ISTEP_10 +{ + +using namespace ISTEP; +using namespace ISTEP_ERROR; +using namespace ERRORLOG; +using namespace TARGETING; + +//****************************************************************************** +// wrapper function to call host_rng_bist +//****************************************************************************** +void* call_host_rng_bist( void *io_pArgs ) +{ + + errlHndl_t l_err = NULL; + IStepError l_StepError; + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_host_rng_bist entry" ); + // + // get a list of all the procs in the system + // + TARGETING::TargetHandleList l_cpuTargetList; + getAllChips(l_cpuTargetList, TYPE_PROC); + + // Loop through all processors including master + for (const auto & l_cpu_target: l_cpuTargetList) + { + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>l_fapi2_proc_target( + l_cpu_target); + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running p9_rng_init_phase1 HWP on processor target %.8X", + TARGETING::get_huid(l_cpu_target) ); + + FAPI_INVOKE_HWP(l_err, p9_rng_init_phase1, l_fapi2_proc_target); + if(l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR: call p9_rng_init_phase1, PLID=0x%x", + l_err->plid()); + l_StepError.addErrorDetails(l_err); + errlCommit(l_err, HWPF_COMP_ID); + } + + } // end of going through all processors + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_host_rng_bist exit"); + + return l_StepError.getErrorHandle(); +} + +}; // end namespace diff --git a/src/usr/isteps/istep10/call_host_set_voltages.C b/src/usr/isteps/istep10/call_host_set_voltages.C new file mode 100644 index 000000000..2bca1cff9 --- /dev/null +++ b/src/usr/isteps/istep10/call_host_set_voltages.C @@ -0,0 +1,133 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/istep10/call_host_set_voltages.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/******************************************************************************/ +// Includes +/******************************************************************************/ +#include <stdint.h> +#include <trace/interface.H> +#include <errl/errlentry.H> +#include <initservice/isteps_trace.H> +#include <initservice/initserviceif.H> +#include <isteps/hwpisteperror.H> +// targeting support +#include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> +#include <errl/errlmanager.H> +#include <fapi2/target.H> +#include <fapi2/plat_hwp_invoker.H> + +#include <p9_setup_evid.H> + + +#include <hbToHwsvVoltageMsg.H> + +using namespace TARGETING; +using namespace ERRORLOG; +using namespace ISTEP_ERROR; + +namespace ISTEP_10 +{ + +//***************************************************************************** +// call_host_set_voltages() +//***************************************************************************** +void* call_host_set_voltages(void *io_pArgs) +{ + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "call_host_set_voltages enter"); + + errlHndl_t l_err = NULL; + TargetHandleList l_procList; + IStepError l_stepError; + bool l_noError = true; + do + { + // Get the system's procs + getAllChips( l_procList, + TYPE_PROC, + true ); // true: return functional procs + + // Iterate over the found procs calling p9_setup_evid + for( const auto & l_procTarget : l_procList ) + { + // Cast to fapi2 target + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> + l_fapiProcTarget( l_procTarget ); + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running p9_setup_evid HWP on processor target %.8X", + get_huid( l_procTarget ) ); + + FAPI_INVOKE_HWP( l_err, + p9_setup_evid, + l_fapiProcTarget, + APPLY_VOLTAGE_SETTINGS); + + if( l_err ) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "Error running p9_setup_evid on processor target %.8X", + get_huid( l_procTarget ) ); + l_stepError.addErrorDetails( l_err ); + + errlCommit( l_err, HWPF_COMP_ID ); + l_noError = false; + } + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "Done with p9_setup_evid" ); + } // Processor Loop + + if( l_noError ) + { + //If FSP is present, send voltage information to HWSV + if( INITSERVICE::spBaseServicesEnabled() ) + { + l_err = platform_set_nest_voltages(); + + if( l_err ) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error in call_host_set_voltages::platform_set_nest_voltages()") + + // Create IStep error log and cross reference occurred error + l_stepError.addErrorDetails( l_err ); + + //Commit Error + errlCommit( l_err, ISTEP_COMP_ID ); + + } + } + } + }while( 0 ); + + + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "call_host_set_voltages exit"); + + // end task, returning any errorlogs to IStepDisp + return l_stepError.getErrorHandle(); +} + +}; // end namespace diff --git a/src/usr/isteps/istep10/call_proc_abus_scominit.C b/src/usr/isteps/istep10/call_proc_abus_scominit.C new file mode 100644 index 000000000..745fabae3 --- /dev/null +++ b/src/usr/isteps/istep10/call_proc_abus_scominit.C @@ -0,0 +1,169 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/istep10/call_proc_abus_scominit.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/** + @file call_proc_abus_scominit.C + * + * Support file for IStep: nest_chiplets + * Nest Chiplets + * + * HWP_IGNORE_VERSION_CHECK + * + */ +/******************************************************************************/ +// Includes +/******************************************************************************/ +#include <stdint.h> + +#include <trace/interface.H> +#include <initservice/taskargs.H> +#include <errl/errlentry.H> + +#include <isteps/hwpisteperror.H> +#include <errl/errludtarget.H> + +#include <initservice/isteps_trace.H> +#include <initservice/initserviceif.H> + +// targeting support +#include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> + +#include <pbusLinkSvc.H> +#include <fapi2/target.H> +#include <fapi2/plat_hwp_invoker.H> + +// MVPD +#include <devicefw/userif.H> +#include <vpd/mvpdenums.H> + +#include <config.h> + + +namespace ISTEP_10 +{ + +using namespace ISTEP; +using namespace ISTEP_ERROR; +using namespace ERRORLOG; +using namespace TARGETING; + +//***************************************************************************** +// wrapper function to call proc_abus_scominit +//****************************************************************************** +void* call_proc_abus_scominit( void *io_pArgs ) +{ + errlHndl_t l_err = NULL; + IStepError l_StepError; + + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_proc_abus_scominit entry" ); + + do + { + /* TargetPairs_t is defined in pbusLinkSvc, which is used by + * other isteps too */ + EDI_EI_INITIALIZATION::TargetPairs_t l_AbusConnections; + // Note: + // i_noDuplicate parameter must be set to false because + // two separate calls would be needed: + // A0 <--> A1 + // A1 <--> A0 + // only the first target is used to issue SCOMs + l_err = + EDI_EI_INITIALIZATION::PbusLinkSvc::getTheInstance().getPbusConnections( + l_AbusConnections, TYPE_ABUS, false); + if (l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X : getPbusConnections ABUS returns error", + l_err->reasonCode()); + + // Create IStep error log and cross reference to error that occurred + l_StepError.addErrorDetails( l_err ); + + // Commit the error log + // Log should be deleted and set to NULL in errlCommit. + errlCommit(l_err, HWPF_COMP_ID); + + // Shouldn't continue on this fatal error (no ABUS), break out + break; + } + + // For each ABUS pair + for (const auto & l_AbusConnection: l_AbusConnections) + { + // Make local copies of ABUS targets for ease of use + TARGETING::Target* l_thisAbusTarget = + const_cast<TARGETING::Target*>(l_AbusConnection.first); + TARGETING::Target* l_connectedAbusTarget = + const_cast<TARGETING::Target*>(l_AbusConnection.second); + + // Get this abus fapi2 target + const fapi2::Target<fapi2::TARGET_TYPE_ABUS> l_thisAbusFapi2Target( + (const_cast<TARGETING::Target*>(l_thisAbusTarget))); + + // Get connected abus fapi2 target + const fapi2::Target<fapi2::TARGET_TYPE_ABUS> + l_connectedAbusFapi2Target( + (const_cast<TARGETING::Target*>(l_connectedAbusTarget))); + + // Call HW procedure + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running proc_abus_scominit HWP on " + "Abus target HUID %.8X Connected Abus target HUID %.8X", + TARGETING::get_huid(l_thisAbusTarget), + TARGETING::get_huid(l_connectedAbusTarget)); + + //@TODO RTC:144076 + //FAPI_INVOKE_HWP(l_err, p9_io_abus_scominit, + // l_thisAbusFapi2Target, + // l_connectedAbusFapi2Target); + if (l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR %.8X : proc_abus_scominit HWP returns error. " + "Abus target HUID %.8X, Connected Abus target HUID %.8X", + l_err->reasonCode(), + TARGETING::get_huid(l_thisAbusTarget), + TARGETING::get_huid(l_connectedAbusTarget)); + + // capture the target data in the elog + ErrlUserDetailsTarget(l_thisAbusTarget).addToLog( l_err ); + ErrlUserDetailsTarget(l_connectedAbusTarget).addToLog( l_err ); + + // Create IStep error log and cross ref to error that occurred + l_StepError.addErrorDetails( l_err ); + // We want to continue to the next target instead of exiting, + // Commit the error log and move on + // Note: Error log should already be deleted and set to NULL + // after committing + errlCommit(l_err, HWPF_COMP_ID); + } + } // End abus pair list loop + } while (0); + + return l_StepError.getErrorHandle(); +} +}; diff --git a/src/usr/isteps/istep10/call_proc_cen_ref_clk_enable.C b/src/usr/isteps/istep10/call_proc_cen_ref_clk_enable.C new file mode 100644 index 000000000..3a1ebc45c --- /dev/null +++ b/src/usr/isteps/istep10/call_proc_cen_ref_clk_enable.C @@ -0,0 +1,302 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/istep10/call_proc_cen_ref_clk_enable.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/** + * @file call_proc_cen_ref_clk_enable.C + * + * Support file for IStep: slave_sbe + * Slave SBE + * + * HWP_IGNORE_VERSION_CHECK + */ + +/******************************************************************************/ +// Includes +/******************************************************************************/ +#include <stdint.h> +#include <trace/interface.H> +#include <initservice/taskargs.H> +#include <errl/errlentry.H> +#include <initservice/isteps_trace.H> +#include <initservice/initserviceif.H> +#include <initservice/initsvcreasoncodes.H> +#include <sys/time.h> +#include <devicefw/userif.H> +#include <i2c/i2cif.H> + +// targeting support +#include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> +#include <targeting/namedtarget.H> +#include <targeting/attrsync.H> + +#include <isteps/hwpisteperror.H> + +#include <errl/errludtarget.H> + + + +const uint64_t MS_TO_WAIT_FIRST = 2500; //(2.5 s) +const uint64_t MS_TO_WAIT_OTHERS= 100; //(100 ms) + +using namespace ISTEP; +using namespace ISTEP_ERROR; +using namespace ERRORLOG; +using namespace TARGETING; + +namespace ISTEP_10 +{ + +uint8_t getMembufsAttachedBitMask( TARGETING::Target * i_procChipHandle ); +void fenceAttachedMembufs( TARGETING::Target * i_procChipHandle ); + +//****************************************************************************** +// call_proc_cen_ref_clock_enable +//****************************************************************************** +void* call_proc_cen_ref_clk_enable(void *io_pArgs ) +{ + errlHndl_t l_errl = NULL; + + IStepError l_stepError; + + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_proc_cen_ref_clock_enable enter" ); + + TARGETING::TargetHandleList functionalProcChipList; + + getAllChips(functionalProcChipList, TYPE_PROC, true); + + // loop thru the list of processors + for (TargetHandleList::const_iterator + l_proc_iter = functionalProcChipList.begin(); + l_proc_iter != functionalProcChipList.end(); + ++l_proc_iter) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "target HUID %.8X", + TARGETING::get_huid( *l_proc_iter )); + + uint8_t l_membufsAttached = 0; + // get a bit mask of present/functional dimms assocated with + // this processor + l_membufsAttached = getMembufsAttachedBitMask( *l_proc_iter ); + + //Perform a workaround for GA1 to raise fences on centaurs + //to prevent FSP from analyzing if HB TIs for recoverable + //errors + //RTC 106276 + fenceAttachedMembufs( *l_proc_iter ); + + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "passing target HUID %.8X and 0x%x mask", + TARGETING::get_huid( *l_proc_iter ), l_membufsAttached ); + + if( l_membufsAttached ) + { + + // Cumulus only + // @TODO RTC:144076 + //fapi::Target l_fapiProcTarget( fapi::TARGET_TYPE_PROC_CHIP, + // *l_proc_iter ); + + // Invoke the HWP passing in the proc target and + // a bit mask indicating connected centaurs + // Cumulus only + //@TODO RTC:144076 + //FAPI_INVOKE_HWP(l_errl, + // p9_proc_cen_ref_clk_enable, + // l_fapiProcTarget, l_membufsAttached ); + + if (l_errl) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR : proc_cen_ref_clk_enable", + "failed, returning errorlog" ); + + // capture the target data in the elog + ErrlUserDetailsTarget( *l_proc_iter ).addToLog( l_errl ); + + // Create IStep error log and cross ref error that occurred + l_stepError.addErrorDetails( l_errl ); + + // Commit error log + errlCommit( l_errl, HWPF_COMP_ID ); + } + else + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : proc_cen_ref_clk_enable", + "completed ok"); + } + } + } // endfor + + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_proc_cen_ref_clock_enable exit" ); + + // end task, returning any errorlogs to IStepDisp + return l_stepError.getErrorHandle(); +} + +//****************************************************************************** +// getMembufsAttachedBitMask - helper function for hwp proc_cen_ref_clk_enable +//****************************************************************************** +uint8_t getMembufsAttachedBitMask( TARGETING::Target * i_procTarget ) +{ + const uint8_t MCS_WITH_ATTACHED_CENTAUR_MASK = 0x80; + + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "Finding functional membuf chips downstream from " + "proc chip with HUID of 0x%08X", + i_procTarget->getAttr<TARGETING::ATTR_HUID>()); + + uint8_t l_attachedMembufs = 0; + + // Get list of functional membuf chips downstream from the given + // proc chip + TARGETING::TargetHandleList functionalMembufChipList; + + getChildAffinityTargets( functionalMembufChipList, + const_cast<TARGETING::Target*>(i_procTarget ), + TARGETING::CLASS_CHIP, + TARGETING::TYPE_MEMBUF, + true); + + // loop through the functional membufs + for(TARGETING::TargetHandleList::const_iterator pTargetItr + = functionalMembufChipList.begin(); + pTargetItr != functionalMembufChipList.end(); + pTargetItr++) + { + // Find each functional membuf chip's upstream functional MCS + // unit, if any, and accumulate it into the attached membuf + // chips mask + TARGETING::TargetHandleList functionalMcsUnitList; + + getParentAffinityTargets( functionalMcsUnitList, *pTargetItr, + TARGETING::CLASS_UNIT, TARGETING::TYPE_MCS, + true ); + + if(functionalMcsUnitList.empty()) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "Functional membuf chip with HUID of 0x%08X " + "is not attached to an upstream functional MCS", + (*pTargetItr)->getAttr< + TARGETING::ATTR_HUID>()); + continue; + } + + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "Found functional MCS unit with HUID of 0x%08X " + "upstream from functional membuf chip with HUID of 0x%08X", + ((*functionalMcsUnitList.begin())->getAttr< + TARGETING::ATTR_CHIP_UNIT>()), + (*pTargetItr)->getAttr< + TARGETING::ATTR_HUID>()); + l_attachedMembufs |= + ((MCS_WITH_ATTACHED_CENTAUR_MASK) >> + ((*functionalMcsUnitList.begin())->getAttr< + TARGETING::ATTR_CHIP_UNIT>())); + } + + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "Proc chip with HUID of 0x%08X has attached membuf " + "mask (l_attachedMembufs) of 0x%02X", + i_procTarget->getAttr<TARGETING::ATTR_HUID>(), + l_attachedMembufs); + + // return the bitmask + return l_attachedMembufs; + +} + +//****************************************************************************** +// fenceAttachedMembufs - helper function for hwp proc_cen_ref_clk_enable +//****************************************************************************** +void fenceAttachedMembufs( TARGETING::Target * i_procTarget ) +{ + errlHndl_t l_errl = NULL; + + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "Fencing attached (present) membuf chips downstream from " + "proc chip with HUID of 0x%08X", + i_procTarget->getAttr<TARGETING::ATTR_HUID>()); + + + // Get list of membuf chips downstream from the given proc chip + TARGETING::TargetHandleList MembufChipList; + + getChildAffinityTargetsByState( MembufChipList, + const_cast<TARGETING::Target*>(i_procTarget ), + TARGETING::CLASS_CHIP, + TARGETING::TYPE_MEMBUF, + TARGETING::UTIL_FILTER_PRESENT); + + // loop through the membufs + for(TARGETING::TargetHandleList::const_iterator pTargetItr + = MembufChipList.begin(); + pTargetItr != MembufChipList.end(); + pTargetItr++) + { + //Get CFAM "1012" -- FSI GP3 and set bits 23-27 (various fence bits) + //Note 1012 is ecmd addressing, real address is 0x1048 (byte) + uint64_t l_addr = 0x1048; + const uint32_t l_fence_bits= 0x000001F0; + uint32_t l_data = 0; + size_t l_size = sizeof(uint32_t); + l_errl = deviceRead(*pTargetItr, + &l_data, + l_size, + DEVICE_FSI_ADDRESS(l_addr)); + if (l_errl) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "Failed getcfam 1012 to HUID 0x%08X, ignoring, skipping", + (*pTargetItr)->getAttr<TARGETING::ATTR_HUID>()); + delete l_errl; + l_errl = NULL; + continue; + } + + l_data |= l_fence_bits; + + l_errl = deviceWrite(*pTargetItr, + &l_data, + l_size, + DEVICE_FSI_ADDRESS(l_addr)); + if (l_errl) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "Failed putcfam 1012 to HUID 0x%08X, ignoring, skipping", + (*pTargetItr)->getAttr<TARGETING::ATTR_HUID>()); + delete l_errl; + l_errl = NULL; + continue; + } + } + +} + +} diff --git a/src/usr/isteps/istep10/call_proc_chiplet_enable_ridi.C b/src/usr/isteps/istep10/call_proc_chiplet_enable_ridi.C new file mode 100644 index 000000000..72422e56b --- /dev/null +++ b/src/usr/isteps/istep10/call_proc_chiplet_enable_ridi.C @@ -0,0 +1,111 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/istep10/call_proc_chiplet_enable_ridi.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/** + @file call_proc_chiplet_enable_ridi.C + * + * Support file for IStep: nest_chiplets + * Nest Chiplets + * + * HWP_IGNORE_VERSION_CHECK + * + */ +/******************************************************************************/ +// Includes +/******************************************************************************/ +#include <stdint.h> + +#include <trace/interface.H> +#include <initservice/taskargs.H> +#include <errl/errlentry.H> + +#include <isteps/hwpisteperror.H> + +#include <errl/errludtarget.H> + +#include <initservice/isteps_trace.H> +#include <initservice/initserviceif.H> + +// targeting support +#include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> +#include <fapi2/target.H> +#include <fapi2/plat_hwp_invoker.H> + +#include <p9_chiplet_enable_ridi.H> + + +namespace ISTEP_10 +{ + +using namespace ISTEP; +using namespace ISTEP_ERROR; +using namespace ERRORLOG; +using namespace TARGETING; + +//****************************************************************************** +// wrapper function to call proc_chiplet_enable_ridi +//****************************************************************************** +void* call_proc_chiplet_enable_ridi( void *io_pArgs ) +{ + errlHndl_t l_err = NULL; + IStepError l_StepError; + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_proc_chiplet_enable_ridi entry" ); + // + // get a list of all the procs in the system + // + TARGETING::TargetHandleList l_cpuTargetList; + getAllChips(l_cpuTargetList, TYPE_PROC); + + // Loop through all processors including master + for (const auto & l_cpu_target: l_cpuTargetList) + { + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>l_fapi2_proc_target( + l_cpu_target); + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running p9_chiplet_enable_ridi HWP on processor target %.8X", + TARGETING::get_huid(l_cpu_target) ); + + FAPI_INVOKE_HWP(l_err, p9_chiplet_enable_ridi, l_fapi2_proc_target); + if(l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR: call p9_chiplet_enable_ridi, PLID=0x%x", + l_err->plid()); + l_StepError.addErrorDetails(l_err); + errlCommit(l_err, HWPF_COMP_ID); + } + + } // end of going through all processors + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_proc_chiplet_enable_ridi exit"); + + return l_StepError.getErrorHandle(); +} + +}; // end namespace diff --git a/src/usr/isteps/istep10/call_proc_chiplet_scominit.C b/src/usr/isteps/istep10/call_proc_chiplet_scominit.C new file mode 100644 index 000000000..f7df9989a --- /dev/null +++ b/src/usr/isteps/istep10/call_proc_chiplet_scominit.C @@ -0,0 +1,149 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/istep10/call_proc_chiplet_scominit.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/** + @file call_proc_chiplet_scominit.C + * + * Support file for IStep: nest_chiplets + * Nest Chiplets + * + * HWP_IGNORE_VERSION_CHECK + * + */ +/******************************************************************************/ +// Includes +/******************************************************************************/ +#include <stdint.h> + +#include <trace/interface.H> +#include <initservice/taskargs.H> +#include <errl/errlentry.H> + +#include <isteps/hwpisteperror.H> +#include <errl/errludtarget.H> + +#include <initservice/isteps_trace.H> +#include <initservice/initserviceif.H> + +// targeting support +#include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> + +#include <fapi2/target.H> +#include <fapi2/plat_hwp_invoker.H> + +// MVPD +#include <devicefw/userif.H> +#include <vpd/mvpdenums.H> + +#include <config.h> + +// HWP +#include <p9_chiplet_scominit.H> +#include <p9_psi_scominit.H> + +namespace ISTEP_10 +{ + +using namespace ISTEP; +using namespace ISTEP_ERROR; +using namespace ERRORLOG; +using namespace TARGETING; + +//****************************************************************************** +// wrapper function to call proc_chiplet_scominit +//****************************************************************************** +void* call_proc_chiplet_scominit( void *io_pArgs ) +{ + errlHndl_t l_err = NULL; + IStepError l_StepError; + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_proc_chiplet_scominit entry" ); + + // + // get a list of all the procs in the system + // + TARGETING::TargetHandleList l_cpuTargetList; + getAllChips(l_cpuTargetList, TYPE_PROC); + + // Loop through all processors including master + for (const auto & l_cpu_target: l_cpuTargetList) + { + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>l_fapi2_proc_target( + l_cpu_target); + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running p9_chiplet_scominit HWP on " + "target HUID %.8X", TARGETING::get_huid(l_cpu_target)); + + FAPI_INVOKE_HWP(l_err, p9_chiplet_scominit, l_fapi2_proc_target); + if (l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "ERROR 0x%.8X : " + "p9_chiplet_scominit HWP returns error. target HUID %.8X", + l_err->reasonCode(), TARGETING::get_huid(l_cpu_target)); + + ErrlUserDetailsTarget(l_cpu_target).addToLog( l_err ); + + // Create IStep error log and cross ref to error that occurred + l_StepError.addErrorDetails( l_err ); + + // We want to continue to the next target instead of exiting, + // Commit the error log and move on + // Note: Error log should already be deleted and set to NULL + // after committing + errlCommit(l_err, HWPF_COMP_ID); + } + + //call p9_psi_scominit + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running p9_psi_scominit HWP on " + "target HUID %.8X", TARGETING::get_huid(l_cpu_target)); + FAPI_INVOKE_HWP(l_err,p9_psi_scominit, l_fapi2_proc_target); + if (l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "ERROR 0x%.8X : " + "p9_psi_scominit HWP returns error. target HUID %.8X", + l_err->reasonCode(), TARGETING::get_huid(l_cpu_target)); + + ErrlUserDetailsTarget(l_cpu_target).addToLog( l_err ); + + // Create IStep error log and cross ref to error that occurred + l_StepError.addErrorDetails( l_err ); + + // We want to continue to the next target instead of exiting, + // Commit the error log and move on + // Note: Error log should already be deleted and set to NULL + // after committing + errlCommit(l_err, HWPF_COMP_ID); + } + } // end of going through all processors + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_proc_chiplet_scominit exit" ); + + return l_StepError.getErrorHandle(); +} +}; diff --git a/src/usr/isteps/istep10/call_proc_enable_osclite.C b/src/usr/isteps/istep10/call_proc_enable_osclite.C new file mode 100644 index 000000000..dd3c6147e --- /dev/null +++ b/src/usr/isteps/istep10/call_proc_enable_osclite.C @@ -0,0 +1,96 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/istep10/call_proc_enable_osclite.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/** + @file call_proc_enable_osclite.C + * + * Support file for IStep: nest_chiplets + * Nest Chiplets + * + * HWP_IGNORE_VERSION_CHECK + * + */ +/******************************************************************************/ +// Includes +/******************************************************************************/ +#include <stdint.h> + +#include <trace/interface.H> +#include <initservice/taskargs.H> +#include <errl/errlentry.H> + +#include <isteps/hwpisteperror.H> + +#include <errl/errludtarget.H> + +#include <initservice/isteps_trace.H> +#include <initservice/initserviceif.H> + +// targeting support +#include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> + +// MVPD +#include <devicefw/userif.H> +#include <vpd/mvpdenums.H> + +#include <config.h> + +// -- prototype includes -- +// Add any customized routines that you don't want overwritten into +// "start_clocks_on_nest_chiplets_custom.C" and include +// the prototypes here. +// #include "nest_chiplets_custom.H" +namespace ISTEP_10 +{ + +using namespace ISTEP; +using namespace ISTEP_ERROR; +using namespace ERRORLOG; +using namespace TARGETING; + +//***************************************************************************** +// wrapper function to call proc_enable_osclite +//***************************************************************************** +void* call_proc_enable_osclite(void *io_pArgs) +{ + errlHndl_t l_errl = NULL; + IStepError l_stepError; + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_proc_enable_osclite" ); + + //@TODO RTC:144076 + //call p9_enable_osclite + //Cumulus only + //FAPI_INVOKE_HWP(l_errl,p9_enable_osclite); + if(l_errl) + { + l_stepError.addErrorDetails(l_errl); + errlCommit(l_errl, HWPF_COMP_ID); + } + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_proc_enable_osclite" ); + return l_stepError.getErrorHandle(); +} +}; diff --git a/src/usr/isteps/istep10/call_proc_npu_scominit.C b/src/usr/isteps/istep10/call_proc_npu_scominit.C new file mode 100644 index 000000000..622fc883d --- /dev/null +++ b/src/usr/isteps/istep10/call_proc_npu_scominit.C @@ -0,0 +1,117 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/istep10/call_proc_npu_scominit.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/** + @file call_proc_npu_scominit.C + * + * Support file for IStep: nest_chiplets + * Nest Chiplets + * + * HWP_IGNORE_VERSION_CHECK + * + */ +/******************************************************************************/ +// Includes +/******************************************************************************/ +#include <stdint.h> + +#include <trace/interface.H> +#include <initservice/taskargs.H> +#include <errl/errlentry.H> + +#include <isteps/hwpisteperror.H> + +#include <errl/errludtarget.H> + +#include <initservice/isteps_trace.H> +#include <initservice/initserviceif.H> + +// targeting support +#include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> + +#include <fapi2/target.H> +#include <fapi2/plat_hwp_invoker.H> + +// MVPD +#include <devicefw/userif.H> +#include <vpd/mvpdenums.H> + +#include <config.h> + +#include <p9_npu_scominit.H> + +namespace ISTEP_10 +{ + +using namespace ISTEP; +using namespace ISTEP_ERROR; +using namespace ERRORLOG; +using namespace TARGETING; + +//****************************************************************************** +// wrapper function to call proc_npu_scominit +//****************************************************************************** +void* call_proc_npu_scominit( void *io_pArgs ) +{ + + errlHndl_t l_err = NULL; + IStepError l_StepError; + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_proc_npu_scominit entry" ); + + // + // get a list of all the procs in the system + // + TARGETING::TargetHandleList l_cpuTargetList; + getAllChips(l_cpuTargetList, TYPE_PROC); + + // Loop through all processors, including master + for (const auto & l_cpu_target: l_cpuTargetList) + { + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>l_fapi2_proc_target( + l_cpu_target); + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running p9_npu_scominit HWP on " + "target HUID %.8X", TARGETING::get_huid(l_cpu_target) ); + FAPI_INVOKE_HWP(l_err, p9_npu_scominit, l_fapi2_proc_target); + if(l_err) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X : p9_npu_scominit " + "HWP returns error for HUID %.8X", + l_err->reasonCode(), + TARGETING::get_huid(l_cpu_target) ); + l_StepError.addErrorDetails(l_err); + errlCommit(l_err, HWPF_COMP_ID); + } + } + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_proc_npu_scominit exit" ); + + return l_StepError.getErrorHandle(); +} +}; diff --git a/src/usr/isteps/istep10/call_proc_obus_scominit.C b/src/usr/isteps/istep10/call_proc_obus_scominit.C new file mode 100644 index 000000000..f08d896c6 --- /dev/null +++ b/src/usr/isteps/istep10/call_proc_obus_scominit.C @@ -0,0 +1,123 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/istep10/call_proc_obus_scominit.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/** + @file call_proc_obus_scominit.C + * + * Support file for IStep: nest_chiplets + * Nest Chiplets + * + * HWP_IGNORE_VERSION_CHECK + * + */ +/******************************************************************************/ +// Includes +/******************************************************************************/ +#include <stdint.h> + +#include <trace/interface.H> +#include <initservice/taskargs.H> +#include <errl/errlentry.H> + +#include <isteps/hwpisteperror.H> + +#include <errl/errludtarget.H> + +#include <initservice/isteps_trace.H> +#include <initservice/initserviceif.H> + +// targeting support +#include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> + +#include <pbusLinkSvc.H> +#include <fapi2/target.H> +#include <fapi2/plat_hwp_invoker.H> + +// MVPD +#include <devicefw/userif.H> +#include <vpd/mvpdenums.H> + +#include <config.h> +#include <p9_io_obus_scominit.H> + +namespace ISTEP_10 +{ + +using namespace ISTEP; +using namespace ISTEP_ERROR; +using namespace ERRORLOG; +using namespace TARGETING; + +//****************************************************************************** +// wrapper function to call proc_obus_scominit +//****************************************************************************** +void* call_proc_obus_scominit( void *io_pArgs ) +{ + errlHndl_t l_err = NULL; + IStepError l_StepError; + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_proc_obus_scominit entry" ); + + do { + + // Get all OBUS targets + TARGETING::TargetHandleList l_obusTargetList; + getAllChiplets(l_obusTargetList, TYPE_OBUS); + + for (const auto & l_obusTarget: l_obusTargetList) + { + + const fapi2::Target<fapi2::TARGET_TYPE_OBUS> + l_obusFapi2Target( + (const_cast<TARGETING::Target*>(l_obusTarget))); + + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running p9_io_obus_scominit HWP on " + "This OBUS target %.8X", + TARGETING::get_huid(l_obusTarget)); + + FAPI_INVOKE_HWP(l_err, p9_io_obus_scominit, + l_obusFapi2Target); + + if(l_err) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%x: returned from p9_io_obus_scominit on " + "OBUS target %.8X, PLID=0x%x", + TARGETING::get_huid(l_obusTarget), + l_err->plid()); + l_StepError.addErrorDetails(l_err); + errlCommit(l_err, HWPF_COMP_ID); + } + } // end of looping through Obus pairs + } while (0); + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_proc_obus_scominit exit" ); + + return l_StepError.getErrorHandle(); +} +}; diff --git a/src/usr/isteps/istep10/call_proc_pcie_scominit.C b/src/usr/isteps/istep10/call_proc_pcie_scominit.C new file mode 100644 index 000000000..664a966e9 --- /dev/null +++ b/src/usr/isteps/istep10/call_proc_pcie_scominit.C @@ -0,0 +1,144 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/istep10/call_proc_pcie_scominit.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/** + @file call_proc_pcie_scominit.C + * + * Support file for IStep: nest_chiplets + * Nest Chiplets + * + * HWP_IGNORE_VERSION_CHECK + * + */ +/******************************************************************************/ +// Includes +/******************************************************************************/ +#include <stdint.h> + +#include <trace/interface.H> +#include <initservice/taskargs.H> +#include <errl/errlentry.H> + +#include <isteps/hwpisteperror.H> + +#include <errl/errludtarget.H> + +#include <initservice/isteps_trace.H> +#include <initservice/initserviceif.H> + +// targeting support +#include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> + +#include <fapi2/target.H> +#include <fapi2/plat_hwp_invoker.H> + +// MVPD +#include <devicefw/userif.H> +#include <vpd/mvpdenums.H> + +#include <config.h> +#include "host_proc_pcie_scominit.H" +#include <p9_pcie_scominit.H> + +namespace ISTEP_10 +{ + +using namespace ISTEP; +using namespace ISTEP_ERROR; +using namespace ERRORLOG; +using namespace TARGETING; + +//***************************************************************************** +// wrapper function to call proc_pcie_scominit +//****************************************************************************** +void* call_proc_pcie_scominit( void *io_pArgs ) +{ + errlHndl_t l_errl = NULL; + IStepError l_StepError; + + // + // get a list of all the procs in the system + // + TARGETING::TargetHandleList l_cpuTargetList; + getAllChips(l_cpuTargetList, TYPE_PROC); + + for (const auto & l_cpu_target: l_cpuTargetList) + { + // Compute the PCIE attribute config on all systems + l_errl = computeProcPcieConfigAttrs(l_cpu_target); + if(l_errl != NULL) + { + // Any failure to configure PCIE that makes it to this handler + // implies a firmware bug that should be fixed, everything else + // is tolerated internally (usually as disabled PHBs) + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + ERR_MRK "call_proc_pcie_scominit> Failed in call to " + "computeProcPcieConfigAttrs for target with HUID = " + "0x%08X", + l_cpu_target->getAttr<TARGETING::ATTR_HUID>() ); + l_StepError.addErrorDetails(l_errl); + errlCommit( l_errl, ISTEP_COMP_ID ); + } + + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_fapi2_proc_target( + l_cpu_target); + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running p9_pcie_scominit HWP on " + "target HUID %.8X", TARGETING::get_huid(l_cpu_target) ); + + // call the HWP with each fapi2::Target + FAPI_INVOKE_HWP(l_errl, p9_pcie_scominit, l_fapi2_proc_target); + + if (l_errl) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X : p9_pcie_scominit HWP returned error", + l_errl->reasonCode() ); + + // capture the target data in the elog + ErrlUserDetailsTarget(l_cpu_target).addToLog( l_errl ); + + // Create IStep error log and cross reference to error that occurred + l_StepError.addErrorDetails( l_errl ); + + // Commit Error + errlCommit( l_errl, HWPF_COMP_ID ); + + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : proc_pcie_scominit HWP" ); + } + } // end of looping through all processors + + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_proc_pcie_scominit exit" ); + + // end task, returning any errorlogs to IStepDisp + return l_StepError.getErrorHandle(); +} +}; diff --git a/src/usr/isteps/istep10/call_proc_scomoverride_chiplets.C b/src/usr/isteps/istep10/call_proc_scomoverride_chiplets.C new file mode 100644 index 000000000..0d4c6d58f --- /dev/null +++ b/src/usr/isteps/istep10/call_proc_scomoverride_chiplets.C @@ -0,0 +1,129 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/istep10/call_proc_scomoverride_chiplets.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/** + @file call_proc_scomoverride_chiplets.C + * + * Support file for IStep: nest_chiplets + * Nest Chiplets + * + * HWP_IGNORE_VERSION_CHECK + * + */ +/******************************************************************************/ +// Includes +/******************************************************************************/ +#include <stdint.h> + +#include <trace/interface.H> +#include <initservice/taskargs.H> +#include <errl/errlentry.H> + +#include <isteps/hwpisteperror.H> +#include <errl/errludtarget.H> + +#include <initservice/isteps_trace.H> +#include <initservice/initserviceif.H> + +// targeting support +#include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> + +#include <fapi2/target.H> +#include <fapi2/plat_hwp_invoker.H> +#include <errl/errlmanager.H> + +// MVPD +#include <devicefw/userif.H> +#include <vpd/mvpdenums.H> + +#include <config.h> + +#include <p9_scomoverride_chiplets.H> + + +namespace ISTEP_10 +{ + +using namespace ISTEP; +using namespace ISTEP_ERROR; +using namespace ERRORLOG; +using namespace TARGETING; + +//***************************************************************************** +// wrapper function to call proc_scomoverride_chiplets +//***************************************************************************** +void* call_proc_scomoverride_chiplets( void *io_pArgs ) +{ + errlHndl_t l_errl = NULL; + IStepError l_StepError; + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_proc_scomoverride_chiplets entry" ); + + // + // get a list of all the procs in the system + // + TARGETING::TargetHandleList l_cpuTargetList; + getAllChips(l_cpuTargetList, TYPE_PROC); + + // Loop through all processors, including master + for (const auto & l_cpu_target: l_cpuTargetList) + { + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> + l_fapi2_proc_target (l_cpu_target); + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running p9_scomoverride_chiplets HWP on processor target %.8X", + TARGETING::get_huid(l_cpu_target) ); + + FAPI_INVOKE_HWP(l_errl, p9_scomoverride_chiplets, l_fapi2_proc_target); + + if (l_errl) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X : proc_scomoverride_chiplets " + "HWP returns error", + l_errl->reasonCode() ); + + // Create IStep error log and cross reference to error that occurred + l_StepError.addErrorDetails( l_errl ); + + // Commit Error + errlCommit( l_errl, HWPF_COMP_ID ); + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : proc_scomoverride_chiplets HWP" ); + } + } // end of going through all processors + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_proc_scomoverride_chiplets exit" ); + + // end task, returning any errorlogs to IStepDisp + return l_StepError.getErrorHandle(); +} +}; diff --git a/src/usr/isteps/istep10/host_proc_pcie_scominit.C b/src/usr/isteps/istep10/host_proc_pcie_scominit.C new file mode 100644 index 000000000..ff9075b4f --- /dev/null +++ b/src/usr/isteps/istep10/host_proc_pcie_scominit.C @@ -0,0 +1,816 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/istep10/host_proc_pcie_scominit.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/******************************************************************************/ +// Includes +/******************************************************************************/ +#include <stdint.h> + +#include <trace/interface.H> +#include <initservice/taskargs.H> +#include <errl/errlentry.H> +#include <isteps/hwpisteperror.H> +#include <errl/errludtarget.H> +#include <initservice/isteps_trace.H> +#include <initservice/initserviceif.H> + +// targeting support +#include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> + +#include <fapi2/target.H> +#include <fapi2/plat_hwp_invoker.H> +#include <devicefw/userif.H> +#include <config.h> +#include "host_proc_pcie_scominit.H" +#include <hwas/common/hwas.H> +#include <hwas/common/deconfigGard.H> + + +namespace ISTEP_10 +{ + +using namespace ISTEP; +using namespace ISTEP_ERROR; +using namespace ERRORLOG; +using namespace TARGETING; + +//****************************************************************************** +// Local logical equality operator for matching lane configuration rows +//****************************************************************************** + +inline bool operator==( + const laneConfigRow& i_lhs, + const laneConfigRow& i_rhs) + { + return ( memcmp(i_lhs.laneSet,i_rhs.laneSet, + sizeof(i_lhs.laneSet)) == 0); + } + +//****************************************************************************** +// _laneMaskToLaneWidth +//****************************************************************************** + +LaneWidth _laneMaskToLaneWidth(const uint16_t i_laneMask) +{ + LaneWidth laneWidth = LANE_WIDTH_NC; + if(i_laneMask == LANE_MASK_X16) + { + laneWidth = LANE_WIDTH_16X; + } + else if( (i_laneMask == LANE_MASK_X8_GRP0) + || (i_laneMask == LANE_MASK_X8_GRP1)) + { + laneWidth = LANE_WIDTH_8X; + } + else if( (i_laneMask == LANE_MASK_X4_GRP0) + || (i_laneMask == LANE_MASK_X4_GRP1)) + { + laneWidth = LANE_WIDTH_4X; + } + + return laneWidth; +} + +//****************************************************************************** +// _deconfigPhbsBasedOnPhbMask +//****************************************************************************** + +void _deconfigPhbsBasedOnPhbMask( + TARGETING::ConstTargetHandle_t const i_procTarget, + TARGETING::ATTR_PROC_PCIE_PHB_ACTIVE_type& i_phbActiveMask) +{ + uint8_t phbNum = 0; + errlHndl_t l_err = NULL; + + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + ENTER_MRK "_deconfigPhbsBasedOnPhbMask: Proc target HUID = " + "0x%08X, PHB active mask = 0x%02X.", i_procTarget ? + i_procTarget->getAttr<TARGETING::ATTR_HUID>() : 0, i_phbActiveMask); + + // PHB mask bits start at the left most bit - so we must shift the bits + // right in order to get the correct masks. This number below should + // always be 7. + const size_t bitsToRightShift = + ((sizeof(i_phbActiveMask)*BITS_PER_BYTE) - 1); + + // Get every functional PEC under the Proc + TARGETING::TargetHandleList funcPecList; + (void)TARGETING::getChildChiplets( + funcPecList,i_procTarget,TARGETING::TYPE_PEC); + + for (TARGETING::TargetHandleList::const_iterator pecItr + = funcPecList.begin(); pecItr != funcPecList.end(); ++pecItr) + { + TargetHandle_t l_pec = *pecItr; + + // Get pec chip's functional PHB units + TARGETING::TargetHandleList funcPhbList; + (void)TARGETING::getChildChiplets( + funcPhbList,l_pec,TARGETING::TYPE_PHB); + + // i_phbActiveMask is a bitmask whose leftmost bit corresponds to + // PHB0, followed by bits for PHB1, PHB2, PHB3, PHB4, and PBH5. The + // remaining bits are ignored. We need to compare each PHB mask to + // its respective PHB and deconfigure it if needed. + for (TARGETING::TargetHandleList::const_iterator phbItr + = funcPhbList.begin(); phbItr != funcPhbList.end(); ++phbItr) + { + TargetHandle_t l_phb = *phbItr; + + // Get the PHB unit number + phbNum = l_phb->getAttr<TARGETING::ATTR_CHIP_UNIT>(); + + // Subtract the PHB unit number from the constant bitsToRightShift + // in order to get the correct amount of bits to shift right. + // e.g. for PHB0, the unit number is 0, bitsToRightShift-0 = 7. + // We will shift i_phbActiveMask 7 bits right, which means we are + // examining bit 0 of the PHB mask. If it is not set - deconfigure + // the respective PHB + if (!((i_phbActiveMask >> (bitsToRightShift - phbNum)) & 1)) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "PHB %d on PEC %d has been found INACTIVE. Deconfiguring " + "PHB %d.", phbNum, + l_pec->getAttr<TARGETING::ATTR_CHIP_UNIT>(), phbNum); + + l_err = HWAS::theDeconfigGard().deconfigureTarget( + *l_phb, HWAS::DeconfigGard::DECONFIGURED_BY_PHB_DECONFIG); + + if (l_err) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, ERR_MRK + "_deconfigPhbsBasedOnPhbMask: Error deconfiguring PHB " + "%d on PEC %d.", phbNum, + l_pec->getAttr<TARGETING::ATTR_HUID>()); + + ERRORLOG::errlCommit(l_err, ISTEP_COMP_ID); + + // Try to deconfigure any other PHBs + delete l_err; + l_err = NULL; + } + } + }//PHB loop + }//PEC loop + + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + EXIT_MRK "_deconfigPhbsBasedOnPhbMask: i_phbActiveMask = 0x%02X", + i_phbActiveMask); + + return; +} + +//****************************************************************************** +// _queryIopsToBifurcateAndPhbsToDisable +//****************************************************************************** + +#ifdef DYNAMIC_BIFURCATION +// Normally a x16 PCIE adapter is driven by one PHB in the processor. +// Some x16 adapters have two logically different devices integrated +// onto the same adapter, each acting as a x8 PCIE endpoint driven by +// its own PHB. The ability to detect which type of PCIE adapter is +// present and dynamically reconfigure the PCIE langes / PHBs to support +// whatever is present is called 'dynamic bifurcation'. This feature is +// not officially supported however hooks remain in place to add that +// support easily. To enable it, define the DYNAMIC_BIFURCATION flag +// and implement the guts of the +// _queryIopsToBifurcateAndPhbsToDisable function. + +errlHndl_t _queryIopsToBifurcateAndPhbsToDisable( + TARGETING::ConstTargetHandle_t const i_pecTarget, + BifurcatedIopsContainer& o_iopList, + TARGETING::ATTR_PROC_PCIE_PHB_ACTIVE_type& o_disabledPhbsMask) +{ + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + ENTER_MRK "_queryIopsToBifurcateAndPhbsToDisable: PEC target " + "HUID = 0x%08X.", i_pecTarget ? + i_pecTarget->getAttr<TARGETING::ATTR_HUID>() : 0); + + errlHndl_t pError = NULL; + o_iopList.clear(); + o_disabledPhbsMask = 0; + + do { + + // Extension point to return bifurcated IOPs and PHBs to disable. + // Assuming no extensions are added, the function returns no IOPs to + // bifurcate and no PHBs to disable + + // If implemented, this function should only return error on software code + // bug. Any other condition should result in IOPs not being bifurcated and + // host taking care of that condition. + + } while(0); + + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + EXIT_MRK "_queryIopsToBifurcateAndPhbsToDisable: EID = 0x%08X, " + "PLID = 0x%08X, RC = 0x%08X.", + ERRL_GETEID_SAFE(pError),ERRL_GETPLID_SAFE(pError), + ERRL_GETRC_SAFE(pError)); + + return pError; +} + +#endif + +/****************************************************************** +* compareChipUnits +* +* Check if chip unit of l_t1 > l_t2 +* +*******************************************************************/ +bool compareChipUnits(TARGETING::Target *l_t1, + TARGETING::Target *l_t2) +{ + bool l_result = false; + assert((l_t1 != NULL) && (l_t2 != NULL)); + + l_result = l_t1->getAttr<TARGETING::ATTR_CHIP_UNIT>() > + l_t2->getAttr<TARGETING::ATTR_CHIP_UNIT>(); + + return l_result; +} + +/****************************************************************** +* setup_pcie_iovalid_enable +* +* Setup ATTR_PROC_PCIE_IOVALID_ENABLE on i_procTarget's PEC children +* +*******************************************************************/ +void setup_pcie_iovalid_enable(const TARGETING::Target * i_procTarget) +{ + // Get list of PEC chiplets downstream from the given proc chip + TARGETING::TargetHandleList l_pecList; + + getChildAffinityTargetsByState( l_pecList, + i_procTarget, + TARGETING::CLASS_NA, + TARGETING::TYPE_PEC, + TARGETING::UTIL_FILTER_ALL); + + for (auto l_pecTarget : l_pecList) + { + // Get list of PHB chiplets downstream from the given PEC chiplet + TARGETING::TargetHandleList l_phbList; + + getChildAffinityTargetsByState( l_phbList, + const_cast<TARGETING::Target*>(l_pecTarget), + TARGETING::CLASS_NA, + TARGETING::TYPE_PHB, + TARGETING::UTIL_FILTER_ALL); + + // default to all invalid + ATTR_PROC_PCIE_IOVALID_ENABLE_type l_iovalid = 0; + + // arrange phb targets from largest to smallest based on unit + // ex. PHB5, PHB4, PHB3 + std::sort(l_phbList.begin(),l_phbList.end(),compareChipUnits); + for(uint32_t k = 0; k<l_phbList.size(); ++k) + { + const fapi2::Target<fapi2::TARGET_TYPE_PHB> + l_fapi_phb_target(l_phbList[k]); + + if(l_fapi_phb_target.isFunctional()) + { + TRACDCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "PHB%d functional", + (l_phbList[k])->getAttr<TARGETING::ATTR_CHIP_UNIT>()); + + // filled in bitwise, largest PHB unit on the right to smallest + // leftword. ex. l_iovalid = 0b00000110 : PHB3, PHB4 functional + // PHB5 not + l_iovalid |= (1<<k); + } + else + { + TRACDCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "PHB%d not functional", + (l_phbList[k])->getAttr<TARGETING::ATTR_CHIP_UNIT>()); + } + } + + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "PROC %.8X PEC%d -> ATTR_PROC_PCIE_IOVALID_ENABLE: 0x%02X", + TARGETING::get_huid(i_procTarget), + l_pecTarget->getAttr<TARGETING::ATTR_CHIP_UNIT>(), + l_iovalid); + + l_pecTarget->setAttr + <TARGETING::ATTR_PROC_PCIE_IOVALID_ENABLE>(l_iovalid); + } +} + + +//***************************************************************************** +// computeProcPcieConfigAttrs +//****************************************************************************** +errlHndl_t computeProcPcieConfigAttrs(TARGETING::Target * i_pProcChipTarget) +{ + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + ENTER_MRK "computeProcPcieConfigAttrs: Proc chip target HUID = " + "0x%08X.", + i_pProcChipTarget ? + i_pProcChipTarget->getAttr<TARGETING::ATTR_HUID>() : 0); + + // Currently there are three PEC config tables for procs with 48 usable PCIE + // lanes. In general, the code accumulates the current configuration of + // the PECs from the MRW and other dynamic information(such as bifurcation) + // then matches that config to one of the rows in the table. Once a match + // is discovered, the PEC config value is pulled from the matching row and + // set in the attributes. + const laneConfigRow pec0_laneConfigTable[] = + {{{LANE_WIDTH_NC, + LANE_WIDTH_NC, + LANE_WIDTH_NC, + LANE_WIDTH_NC}, + 0x00,PHB_MASK_NA, + PHB_X16_MAC_MAP}, + + {{LANE_WIDTH_16X, + LANE_WIDTH_NC, + LANE_WIDTH_NC, + LANE_WIDTH_NC}, + 0x00,PHB0_MASK, + PHB_X16_MAC_MAP}, + }; + + const laneConfigRow pec1_laneConfigTable[] = + {{{LANE_WIDTH_NC, + LANE_WIDTH_NC, + LANE_WIDTH_NC, + LANE_WIDTH_NC}, + 0x00,PHB_MASK_NA, + PHB_X8_X8_MAC_MAP}, + + {{LANE_WIDTH_8X, + LANE_WIDTH_NC, + LANE_WIDTH_8X, + LANE_WIDTH_NC}, + 0x00,PHB1_MASK|PHB2_MASK, + PHB_X8_X8_MAC_MAP}, + + {{LANE_WIDTH_8X, + LANE_WIDTH_NC, + LANE_WIDTH_NC, + LANE_WIDTH_NC}, + 0x00,PHB1_MASK, + PHB_X8_X8_MAC_MAP}, + + {{LANE_WIDTH_NC, + LANE_WIDTH_NC, + LANE_WIDTH_8X, + LANE_WIDTH_NC}, + 0x00,PHB2_MASK, + PHB_X8_X8_MAC_MAP}, + }; + + const laneConfigRow pec2_laneConfigTable[] = + {{{LANE_WIDTH_NC, + LANE_WIDTH_NC, + LANE_WIDTH_NC, + LANE_WIDTH_NC}, + 0x00,PHB_MASK_NA, + PHB_X16_MAC_MAP}, + + {{LANE_WIDTH_16X, + LANE_WIDTH_NC, + LANE_WIDTH_NC, + LANE_WIDTH_NC}, + 0x00,PHB3_MASK, + PHB_X16_MAC_MAP}, + + {{LANE_WIDTH_8X, + LANE_WIDTH_NC, + LANE_WIDTH_8X, + LANE_WIDTH_NC}, + 0x10,PHB3_MASK|PHB4_MASK, + PHB_X8_X8_MAC_MAP}, + + {{LANE_WIDTH_8X, + LANE_WIDTH_NC, + LANE_WIDTH_4X, + LANE_WIDTH_4X}, + 0x20,PHB3_MASK|PHB4_MASK|PHB5_MASK, + PHB_X8_X4_X4_MAC_MAP}, + }; + + const laneConfigRow* pec0_end = pec0_laneConfigTable + + ( sizeof(pec0_laneConfigTable) + / sizeof(pec0_laneConfigTable[0])); + + const laneConfigRow* pec1_end = pec1_laneConfigTable + + ( sizeof(pec1_laneConfigTable) + / sizeof(pec1_laneConfigTable[0])); + + const laneConfigRow* pec2_end = pec2_laneConfigTable + + ( sizeof(pec2_laneConfigTable) + / sizeof(pec2_laneConfigTable[0])); + + errlHndl_t pError = NULL; + const laneConfigRow* pLaneConfigTableBegin = NULL; + const laneConfigRow* pLaneConfigTableEnd = NULL; + TARGETING::ATTR_PROC_PCIE_PHB_ACTIVE_type procPhbActiveMask = 0; + + do + { + assert((i_pProcChipTarget != NULL),"computeProcPcieConfigs was " + "passed in a NULL processor target"); + + const TARGETING::ATTR_CLASS_type targetClass + = i_pProcChipTarget->getAttr<TARGETING::ATTR_CLASS>(); + const TARGETING::ATTR_TYPE_type targetType + = i_pProcChipTarget->getAttr<TARGETING::ATTR_TYPE>(); + const bool targetPresent = + i_pProcChipTarget->getAttr<TARGETING::ATTR_HWAS_STATE>() + .present; + + assert(((targetClass == TARGETING::CLASS_CHIP) + || (targetType == TARGETING::TYPE_PROC) + || (targetPresent)),"computeProcPcieConfigs - input either not a " + "processor chip or not present"); + + // Set up vector of PECs under this processor + PredicateCTM predPec(CLASS_UNIT, TYPE_PEC); + TargetHandleList l_pecList; + targetService().getAssociated(l_pecList, + i_pProcChipTarget, + TargetService::CHILD, + TargetService::ALL, + &predPec); + + // Even if the list is empty we still want to go to the bottom of the + // fucntion and set PROC_PHB_ACTIVE_MASK + + // Iterate over every PEC to find its config, swap, reversal and + // bifurcation attributes + for(TargetHandleList::iterator l_pPecIt = l_pecList.begin(); + l_pPecIt != l_pecList.end(); ++l_pPecIt) + { + TargetHandle_t l_pec = *l_pPecIt; + // Get the PEC id + uint8_t l_pecID = l_pec->getAttr<TARGETING::ATTR_CHIP_UNIT>(); + + // Select the correct PEC config table + if(l_pecID == 0) + { + pLaneConfigTableBegin = pec0_laneConfigTable; + pLaneConfigTableEnd = pec0_end; + } + else if (l_pecID == 1) + { + pLaneConfigTableBegin = pec1_laneConfigTable; + pLaneConfigTableEnd = pec1_end; + } + else if (l_pecID == 2) + { + pLaneConfigTableBegin = pec2_laneConfigTable; + pLaneConfigTableEnd = pec2_end; + } + else + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + ERR_MRK "computeProcPcieConfigAttrs> " + "Code bug! Unsupported PEC ID attribute for " + "processor with HUID of 0x%08X. Expected 0,1 or 2, but " + "read a value of %d. PROC_PCIE_NUM_PEC is %d.", + i_pProcChipTarget->getAttr<TARGETING::ATTR_HUID>(),l_pecID, + i_pProcChipTarget->getAttr + <TARGETING::ATTR_PROC_PCIE_NUM_PEC>()); + + /*@ + * @errortype + * @moduleid MOD_COMPUTE_PCIE_CONFIG_ATTRS + * @reasoncode RC_INVALID_ATTR_VALUE + * @userdata1[0:15] Target's HUID + * @userdata1[16:31] PEC id number + * @userdata2[32:63] ATTR_PROC_PCIE_NUM_PEC attribute value + * @devdesc Illegal ATTR_PROC_PCIE_NUM_PEC attribute + * read from a processor chip target. + * @custdesc A problem isolated to firmware or firmware + * customization occurred during the IPL of + * the system. + */ + pError = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + MOD_COMPUTE_PCIE_CONFIG_ATTRS, + RC_INVALID_ATTR_VALUE, + TWO_UINT32_TO_UINT64(TWO_UINT16_TO_UINT32( + i_pProcChipTarget->getAttr<TARGETING::ATTR_HUID>(), + l_pecID), + i_pProcChipTarget->getAttr< + TARGETING::ATTR_PROC_PCIE_NUM_PEC>()), + 0, + true); + ERRORLOG::ErrlUserDetailsTarget(i_pProcChipTarget) + .addToLog(pError); + pError->collectTrace(ISTEP_COMP_NAME); + break; + } + + TARGETING::ATTR_PROC_PCIE_PHB_ACTIVE_type disabledPhbs = 0; + + TARGETING::ATTR_PROC_PCIE_LANE_MASK_type + effectiveLaneMask = {0}; + + TARGETING::ATTR_PEC_PCIE_IOP_REVERSAL_type + effectiveLaneReversal = {0}; + + TARGETING::ATTR_PROC_PCIE_IOP_SWAP_type + effectiveLaneSwap = 0; + + //Only attempt to determine the lane config on FSPless systems + //On FSP based systems it has already been determined + if (!INITSERVICE::spBaseServicesEnabled()) + { +#ifdef DYNAMIC_BIFURCATION + // Figure out which IOPs need bifurcation, and as a + // result, which PHBs to disable + BifurcatedIopsContainer iopList; + pError = _queryIopsToBifurcateAndPhbsToDisable( + l_pec, + iopList, + disabledPhbs); + if(pError!=NULL) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + ERR_MRK "computeProcPcieConfigAttrs> " + "Failed in call to" + "_queryIopsToBifurcateAndPhbsToDisable; " + "Proc HUID = 0x%08X.", + i_pProcChipTarget->getAttr + <TARGETING::ATTR_HUID>()); + break; + } +#endif + + TARGETING::ATTR_PEC_PCIE_LANE_MASK_NON_BIFURCATED_type + laneMaskNonBifurcated = {0}; + assert(l_pec->tryGetAttr< + TARGETING::ATTR_PEC_PCIE_LANE_MASK_NON_BIFURCATED>( + laneMaskNonBifurcated),"Failed to get " + "ATTR_PEC_PCIE_LANE_MASK_NON_BIFURCATED attribute"); + + + memcpy(effectiveLaneMask,laneMaskNonBifurcated, + sizeof(effectiveLaneMask)); + +#ifdef DYNAMIC_BIFURCATION + TARGETING::ATTR_PEC_PCIE_LANE_MASK_BIFURCATED_type + laneMaskBifurcated = {0}; + assert(l_pec->tryGetAttr< + TARGETING::ATTR_PEC_PCIE_LANE_MASK_BIFURCATED>( + laneMaskBifurcated),"Failed to get " + "ATTR_PEC_PCIE_LANE_MASK_BIFURCATED attribute"); + + TARGETING::ATTR_PEC_PCIE_IOP_REVERSAL_BIFURCATED_type + laneReversalBifurcated = {0}; + assert(l_pec->tryGetAttr< + TARGETING::ATTR_PEC_PCIE_IOP_REVERSAL_BIFURCATED>( + laneReversalBifurcated),"Failed to get " + "ATTR_PEC_PCIE_IOP_REVERSAL_BIFURCATED attribute"); + + TARGETING::ATTR_PEC_PCIE_IOP_SWAP_BIFURCATED_type + bifurcatedSwap = {0}; + assert(l_pec->tryGetAttr< + TARGETING::ATTR_PEC_PCIE_IOP_SWAP_BIFURCATED>( + bifurcatedSwap),"Failed to get " + "ATTR_PEC_PCIE_IOP_SWAP_BIFURCATED attribute"); + + // Apply any IOP bifurcation settings + for(BifurcatedIopsContainer::const_iterator iopItr = + iopList.begin(); iopItr != iopList.end(); + ++iopItr) + { + BifurcatedIopsContainer::const_reference iop = *iopItr; + memcpy( + &effectiveLaneReversal[0], + &laneReversalBifurcated[0], + sizeof(effectiveLaneReversal)/1); + + memcpy( + &effectiveLaneMask[0], + &laneMaskBifurcated[0], + sizeof(effectiveLaneMask)/1); + + // For every lane group of a PEC we need to see if + // the lane swap bit has been set. If the lane is + // used, and the bit is not set we set the lane swap + // bit. Lane swap attribute is a single attribute per + // PEC, so once the lane swap is set for one lane + // group it will be set for the whole PEC. + for(size_t laneGroup=0; + laneGroup < + (sizeof(bifurcatedSwap)/sizeof(effectiveLaneSwap)); + ++laneGroup) + { + // If lanes are used and swap not yet set, then set it + if((effectiveLaneMask[laneGroup]) && + (!effectiveLaneSwap)) + { + effectiveLaneSwap = bifurcatedSwap[laneGroup]; + break; + } + } + } + + // TODO: Dynamic Bifurcation - For future partner development + // Only set if dynamic bifurcation and we need to re-compute + // the swap and reversal setting + l_pec->setAttr< + TARGETING::ATTR_PEC_PCIE_IOP_SWAP>(effectiveLaneSwap); + + l_pec->setAttr< + TARGETING::ATTR_PEC_PCIE_IOP_REVERSAL>(effectiveLaneReversal); + +#endif + + l_pec->setAttr< + TARGETING::ATTR_PROC_PCIE_LANE_MASK>(effectiveLaneMask); + + } + else + { + assert(l_pec->tryGetAttr< + TARGETING::ATTR_PROC_PCIE_LANE_MASK>(effectiveLaneMask), + "Failed to get ATTR_PROC_PCIE_LANE_MASK attribute"); + + // While we aren't using the attribute in this function, we + // should still make sure swap and reversal are set + assert(l_pec->tryGetAttr< + TARGETING::ATTR_PROC_PCIE_IOP_SWAP>(effectiveLaneSwap), + "Failed to get ATTR_PROC_PCIE_IOP_SWAP attribute"); + + assert(l_pec->tryGetAttr< + TARGETING::ATTR_PEC_PCIE_IOP_REVERSAL> + (effectiveLaneReversal), + "Failed to get ATTR_PEC_PCIE_IOP_REVERSAL attribute"); + } + + TARGETING::ATTR_PROC_PCIE_PHB_ACTIVE_type pecPhbActiveMask = 0; + TARGETING::ATTR_PROC_PCIE_IOP_CONFIG_type iopConfig = 0; + TARGETING::ATTR_PROC_PCIE_REFCLOCK_ENABLE_type refEnable = 0; + TARGETING::ATTR_PROC_PCIE_PCS_SYSTEM_CNTL_type macCntl = 0; + + laneConfigRow effectiveConfig = + {{LANE_WIDTH_NC, + LANE_WIDTH_NC, + LANE_WIDTH_NC, + LANE_WIDTH_NC}, + 0x00,PHB_MASK_NA, + PHB_X16_MAC_MAP, + }; + + // Transform effective config to match lane config table format + for(size_t laneGroup = 0; + laneGroup < MAX_LANE_GROUPS_PER_PEC; + ++laneGroup) + { + effectiveConfig.laneSet[laneGroup].width + = _laneMaskToLaneWidth(effectiveLaneMask[laneGroup]); + } + + const laneConfigRow* laneConfigItr = + std::find( + pLaneConfigTableBegin, + pLaneConfigTableEnd, + effectiveConfig); + + if(laneConfigItr != pLaneConfigTableEnd) + { + iopConfig = laneConfigItr->laneConfig; + refEnable = 0x1; + macCntl = laneConfigItr->phb_to_pcieMAC; + pecPhbActiveMask = laneConfigItr->phbActive; + + // If we find a valid config, and the PHB_MASK is still NA + // that means all PHB's on this PEC will be disabled. Lets + // trace something out just so someone knows. + if(pecPhbActiveMask == PHB_MASK_NA) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,"Valid " + "configuration found for PEC 0x%08X, but no PHBs behind " + "it wil be functional", l_pecID); + } + + // Disable applicable PHBs + pecPhbActiveMask &= (~disabledPhbs); + // Add the PEC phb mask to the overall Proc PHB mask + procPhbActiveMask |= pecPhbActiveMask; + + } + else + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + ERR_MRK "computeProcPcieConfigAttrs> " + "Code bug! PEC PCIE IOP configuration not found. " + "Continuing with no PHBs active on PEC 0x%08X. " + "Lane set 0: Lane mask = 0x%04X " + "Lane set 1: Lane mask = 0x%04X " + "Lane set 2: Lane mask = 0x%04X " + "Lane set 3: Lane mask = 0x%04X ", + l_pecID, + effectiveLaneMask[0], + effectiveLaneMask[1], + effectiveLaneMask[2], + effectiveLaneMask[3]); + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "PEC chip target number 0x%08X, HUID = 0x%08X.", + l_pecID, l_pec->getAttr<TARGETING::ATTR_HUID>()); + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "Proc chip target HUID = 0x%08X.", + i_pProcChipTarget->getAttr<TARGETING::ATTR_HUID>()); + /*@ + * @errortype + * @moduleid MOD_COMPUTE_PCIE_CONFIG_ATTRS + * @reasoncode RC_INVALID_CONFIGURATION + * @userdata1[0:31] Target processor chip's HUID + * @userdata1[32:63] Target PEC HUID + * @userdata2[0:15] PEC lane set 0 lane mask + * @userdata2[16:31] PEC lane set 1 lane mask + * @userdata2[32:47] PEC lane set 2 lane mask + * @userdata2[48:63] PEC lane set 3 lane mask + * @devdesc No valid PCIE IOP configuration found. All + * PHBs on this PEC will be disabled. + * @custdesc A problem isolated to firmware or firmware + * customization occurred during the IPL of + * the system. + */ + pError = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + MOD_COMPUTE_PCIE_CONFIG_ATTRS, + RC_INVALID_CONFIGURATION, + TWO_UINT32_TO_UINT64( + i_pProcChipTarget->getAttr<TARGETING::ATTR_HUID>(), + l_pec->getAttr<TARGETING::ATTR_HUID>()), + TWO_UINT32_TO_UINT64( + TWO_UINT16_TO_UINT32( + effectiveLaneMask[0], + effectiveLaneMask[1]), + TWO_UINT16_TO_UINT32( + effectiveLaneMask[2], + effectiveLaneMask[3])), + true); + ERRORLOG::ErrlUserDetailsTarget(i_pProcChipTarget) + .addToLog(pError); + pError->collectTrace(ISTEP_COMP_NAME); + errlCommit(pError, ISTEP_COMP_ID); + } + + procPhbActiveMask |= pecPhbActiveMask; + l_pec->setAttr< + TARGETING::ATTR_PROC_PCIE_IOP_CONFIG>(iopConfig); + l_pec->setAttr< + TARGETING::ATTR_PROC_PCIE_REFCLOCK_ENABLE>(refEnable); + l_pec->setAttr< + TARGETING::ATTR_PROC_PCIE_PCS_SYSTEM_CNTL>(macCntl); + + }// PEC loop + + // Set the procPhbActiveMask + i_pProcChipTarget->setAttr< + TARGETING::ATTR_PROC_PCIE_PHB_ACTIVE>(procPhbActiveMask); + + // Only deconfigure the PHB's once we have the phbActiveMask attribute + // set up for the whole processor + (void)_deconfigPhbsBasedOnPhbMask( + i_pProcChipTarget, + procPhbActiveMask); + + // setup ATTR_PROC_PCIE_IOVALID_ENABLE for this processor + // This has to be done after the PHB's are disabled + setup_pcie_iovalid_enable(i_pProcChipTarget); + + } while(0); + + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + EXIT_MRK "computeProcPcieConfigAttrs: EID = 0x%08X, PLID = 0x%08X, " + "RC = 0x%08X.", + ERRL_GETEID_SAFE(pError),ERRL_GETPLID_SAFE(pError), + ERRL_GETRC_SAFE(pError)); + + return pError; +} + +}; diff --git a/src/usr/isteps/istep10/host_proc_pcie_scominit.H b/src/usr/isteps/istep10/host_proc_pcie_scominit.H new file mode 100644 index 000000000..96e7ca273 --- /dev/null +++ b/src/usr/isteps/istep10/host_proc_pcie_scominit.H @@ -0,0 +1,147 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/istep10/host_proc_pcie_scominit.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __ISTEPS_HOST_PROC_PCIE_SCOMINIT_H +#define __ISTEPS_HOST_PROC_PCIE_SCOMINIT_H + +/******************************************************************************/ +// Includes +/******************************************************************************/ +#include <stdint.h> + +namespace ISTEP_10 +{ + +/** + * @brief Computes PCIE configuration attributes based on MRW values + * + * @param i_pProcChipTarget: Proc chip to compute the PCIE Configuration + * attributes for. + */ +errlHndl_t computeProcPcieConfigAttrs(TARGETING::Target* i_pProcChipTarget); + +/** + * @brief # of bits in a byte for computation purposes + */ +static const size_t BITS_PER_BYTE = 8; + +/** + * @brief Container for holding IOPs to bifurcate + */ +typedef std::list<uint32_t> BifurcatedIopsContainer; + +/** + * @brief Enum indicating number of usable IOP lanes for a proc + */ +enum IopLanesPerProc +{ + IOP_LANES_PER_PROC_48X = 48,// 48 Lanes per proc +}; + +/** + * @brief Struct for PCIE lane properties within IOP configuration tables + */ +struct LaneSet +{ + uint8_t width; // Width of each PCIE lane set (0, 4, 8, or 16) +}; + +/** + * @brief Lane groups per PEC + */ +static const size_t MAX_LANE_GROUPS_PER_PEC = 4; + +/** + * @brief Struct for each row in PCIE IOP configuration table. + * Used by code to compute the IOP config and PHBs active mask. + */ +struct laneConfigRow +{ + // Grouping of lanes under one IOP + LaneSet laneSet[MAX_LANE_GROUPS_PER_PEC]; + + // IOP config value from PCIE IOP configuration table + uint8_t laneConfig; + + // PHB active mask (see PhbActiveMask enum) + // PHB0 = 0x80 + // PHB1 = 0x40 + // PHB2 = 0x20 + // PHB3 = 0x10 + // PHB4 = 0x08 + // PHB5 = 0x04 + uint8_t phbActive; + uint16_t phb_to_pcieMAC; +}; + +/** + * @brief Enum indicating lane width (units = "number of lanes") + */ +enum LaneWidth +{ + LANE_WIDTH_NC = 0, + LANE_WIDTH_4X = 4, + LANE_WIDTH_8X = 8, + LANE_WIDTH_16X = 16 +}; + +/** + * @brief Enumeration of lane mask values + */ +enum LaneMask +{ + LANE_MASK_X16 = 0xFFFF, + LANE_MASK_X8_GRP0 = 0xFF00, + LANE_MASK_X8_GRP1 = 0x00FF, + LANE_MASK_X4_GRP0 = 0x00F0, + LANE_MASK_X4_GRP1 = 0x000F, +}; + +/** + * @brief Enumeration of PHB to PCI MAC mappings + */ +enum PhbToMAC +{ + PHB_X16_MAC_MAP = 0x0000, + PHB_X8_X8_MAC_MAP = 0x0050, + PHB_X8_X4_X4_MAC_MAP = 0x0090, +}; + +/** + * @brief Enum giving bitmask values for enabled PHBs + */ +enum PhbActiveMask +{ + PHB_MASK_NA = 0x00, ///< Sentinel mask (loop terminations) + PHB0_MASK = 0x80, ///< PHB0 enabled + PHB1_MASK = 0x40, ///< PHB1 enabled + PHB2_MASK = 0x20, ///< PHB2 enabled + PHB3_MASK = 0x10, ///< PHB3 enabled + PHB4_MASK = 0x08, ///< PHB4 enabled + PHB5_MASK = 0x04, ///< PHB5 enabled +}; + +}; + +#endif diff --git a/src/usr/isteps/istep10/makefile b/src/usr/isteps/istep10/makefile index c5d4e88d1..f0101903d 100644 --- a/src/usr/isteps/istep10/makefile +++ b/src/usr/isteps/istep10/makefile @@ -28,7 +28,12 @@ MODULE = istep10 NEST_HWP_PATH += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/nest INITFILES_HWP_PATH += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/initfiles PERV_HWP_PATH += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/perv +PROCEDURES_PATH += ${ROOTPATH}/src/import/chips/p9/procedures +EXTRAINCDIR += ${PROCEDURES_PATH}/hwp/pm/ +EXTRAINCDIR += ${PROCEDURES_PATH}/hwp/io/ +EXTRAINCDIR += ${PROCEDURES_PATH}/hwp/lib/ +EXTRAINCDIR += ${PROCEDURES_PATH}/hwp/pm/include/registers EXTRAINCDIR += ${ROOTPATH}/src/usr/isteps/ EXTRAINCDIR += ${ROOTPATH}/src/include/usr/fapi2/ EXTRAINCDIR += ${ROOTPATH}/src/import/hwpf/fapi2/include/ @@ -40,11 +45,26 @@ EXTRAINCDIR += ${PERV_HWP_PATH} OBJS += call_proc_build_smp.o OBJS += call_host_slave_sbe_update.o +OBJS += call_host_set_voltages.o +OBJS += call_proc_cen_ref_clk_enable.o +OBJS += call_proc_enable_osclite.o +OBJS += call_proc_chiplet_scominit.o +OBJS += call_proc_abus_scominit.o +OBJS += call_proc_obus_scominit.o +OBJS += call_proc_npu_scominit.o +OBJS += call_proc_pcie_scominit.o +OBJS += call_proc_scomoverride_chiplets.o +OBJS += call_proc_chiplet_enable_ridi.o +OBJS += call_host_rng_bist.o OBJS += call_host_update_redundant_tpm.o +OBJS += host_proc_pcie_scominit.o VPATH += ${NEST_HWP_PATH} VPATH += ${INITFILES_HWP_PATH} VPATH += ${PERV_HWP_PATH} +VPATH += ${PROCEDURES_PATH}/hwp/io/ +VPATH += ${PROCEDURES_PATH}/hwp/pm/ +VPATH += ${PROCEDURES_PATH}/hwp/lib/ #Required include before all the procedure.mk are included include ${ROOTPATH}/procedure.rules.mk @@ -55,4 +75,52 @@ include ${INITFILES_HWP_PATH}/p9_fbc_ab_hp_scom.mk include ${INITFILES_HWP_PATH}/p9_fbc_cd_hp_scom.mk include ${PERV_HWP_PATH}/p9_update_security_ctrl.mk +# proc_chiplet_scominit : Scom inits to all chiplets (sans Quad) +include ${PROCEDURES_PATH}/hwp/nest/p9_chiplet_scominit.mk +include ${PROCEDURES_PATH}/hwp/nest/p9_psi_scominit.mk +include ${PROCEDURES_PATH}/hwp/initfiles/p9_psi_scom.mk +include ${PROCEDURES_PATH}/hwp/initfiles/p9_fbc_ioo_tl_scom.mk +include ${PROCEDURES_PATH}/hwp/initfiles/p9_fbc_ioo_dl_scom.mk +include ${PROCEDURES_PATH}/hwp/initfiles/p9_nx_scom.mk +include ${PROCEDURES_PATH}/hwp/initfiles/p9_cxa_scom.mk +include ${PROCEDURES_PATH}/hwp/initfiles/p9_mmu_scom.mk +include ${PROCEDURES_PATH}/hwp/initfiles/p9_int_scom.mk +include ${PROCEDURES_PATH}/hwp/initfiles/p9_vas_scom.mk + +# proc_obus_scominit : Apply scom inits to Obus +include ${PROCEDURES_PATH}/hwp/io/p9_io_obus_scominit.mk +include ${PROCEDURES_PATH}/hwp/initfiles/p9_obus_scom.mk + +# proc_npu_scominit : Apply scom inits to NPU bus +include ${PROCEDURES_PATH}/hwp/initfiles/p9_npu_scom.mk +include ${PROCEDURES_PATH}/hwp/nest/p9_npu_scominit.mk +include ${PROCEDURES_PATH}/hwp/perv/p9_nv_ref_clk_enable.mk + +# proc_pcie_scominit : Apply scom inits to PCIe chiplets +include ${PROCEDURES_PATH}/hwp/nest/p9_pcie_scominit.mk + +# p9_mcs_scom +include ${PROCEDURES_PATH}/hwp/initfiles/p9_mcs_scom.mk + +# proc_scomoverride_chiplets : Apply sequenced scom inits +include ${PROCEDURES_PATH}/hwp/nest/p9_scomoverride_chiplets.mk + +# proc_chiplet_enable_ridi : Apply RI/DI chip wide +include ${PROCEDURES_PATH}/hwp/perv/p9_chiplet_enable_ridi.mk + +# host_rng_bist : Trigger Built In Self Test +# HWP not ready - p9_trigger_rng_bist.mk +include ${PROCEDURES_PATH}/hwp/nest/p9_rng_init_phase1.mk + +# p9_setup_evid : apply voltage settings +include ${PROCEDURES_PATH}/hwp/pm/p9_setup_evid.mk +include ${PROCEDURES_PATH}/hwp/lib/p9_avsbus_lib.mk + +# p9_avsbus_lib.mk sets MODULE, reset here to istep10 +MODULE = istep10 + +# TODO RTC: 164237 +# Take another look at PM lib +include $(PROCEDURES_PATH)/hwp/pm/p9_pm_utils.mk + include ${ROOTPATH}/config.mk |