diff options
Diffstat (limited to 'src/usr/hwpf')
13 files changed, 1568 insertions, 949 deletions
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_bar_config.C b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_bar_config.C index 0ad332f02..b1fe68e9b 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_bar_config.C +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_bar_config.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_pba_bar_config.C,v 1.3 2012/10/23 16:09:37 stillgs Exp $ +// $Id: p8_pba_bar_config.C,v 1.4 2014/03/03 23:44:49 stillgs Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pba_bar_config.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -137,13 +137,14 @@ p8_pba_bar_config (const Target& i_target, uint64_t work_size; - FAPI_DBG("Called with index %x, address 0x%16llX, size 0x%llX scope 0x%llX", + FAPI_DBG("Called with index %x, address 0x%08llX, size 0x%04llX scope 0x%04llX", i_index, i_pba_bar_addr, i_pba_bar_size, i_pba_cmd_scope); // check if pba_bar scope in range if ( i_pba_cmd_scope > PBA_CMD_SCOPE_FOREIGN1 ) { - FAPI_ERR("ERROR: PB Command Scope out of Range"); + FAPI_ERR("ERROR: PB Command Scope out of Range: 0x%04llX > 0x%04X", i_pba_cmd_scope, PBA_CMD_SCOPE_FOREIGN1 ); + const uint64_t exp_PBA_CMD_SCOPE_FOREIGN1 = PBA_CMD_SCOPE_FOREIGN1; FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PBA_BAR_SCOPE_OUT_OF_RANGE); return l_rc; } @@ -152,7 +153,8 @@ p8_pba_bar_config (const Target& i_target, // High order bits checked to ensure a valid real address if ( (BAR_ADDR_RANGECHECK_HIGH & i_pba_bar_addr) != 0x0ull ) { - FAPI_ERR("ERROR: Address out of Range"); + FAPI_ERR("ERROR: Address out of Range : i_pba_bar_addr=0x%08llX", i_pba_bar_addr); + const uint64_t exp_BAR_ADDR_RANGECHECK_HIGH = BAR_ADDR_RANGECHECK_HIGH; FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PBA_ADDR_OUT_OF_RANGE); return l_rc; } @@ -160,7 +162,8 @@ p8_pba_bar_config (const Target& i_target, // Low order bits checked for alignment if ( (BAR_ADDR_RANGECHECK_LOW & i_pba_bar_addr) != 0x0ull ) { - FAPI_ERR("ERROR: Address must be on a 1MB boundary"); + FAPI_ERR("ERROR: Address must be on a 1MB boundary : i_pba_bar_addr=0x%08llX",i_pba_bar_addr); + const uint64_t exp_BAR_ADDR_RANGECHECK_LOW = BAR_ADDR_RANGECHECK_LOW; FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PBA_ADDR_ALIGNMENT_ERROR); return l_rc; } @@ -169,7 +172,7 @@ p8_pba_bar_config (const Target& i_target, // The combination of both the size and BAR being zero is legal. if ( (i_pba_bar_size == 0x0ull) && (i_pba_bar_size != 0x0ull) ) { - FAPI_ERR("ERROR: Size must be 1MB or greater"); + FAPI_ERR("ERROR: Size must be 1MB or greater : i_pba_bar_size=%08llX", i_pba_bar_size); FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PBA_BAR_SIZE_INVALID); return l_rc; } diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pba_bar_config_errors.xml b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pba_bar_config_errors.xml index 6e2991e0c..7a36ffb0f 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pba_bar_config_errors.xml +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pba_bar_config_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- COPYRIGHT International Business Machines Corp. 2013,2014 --> <!-- --> <!-- p1 --> <!-- --> @@ -20,43 +20,63 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: p8_pba_bar_config_errors.xml,v 1.3 2013/02/06 17:47:07 stillgs Exp $ --> +<!-- $Id: p8_pba_bar_config_errors.xml,v 1.4 2014/03/03 23:43:34 stillgs Exp $ --> <!-- Error definitions for proc_pba_bar_config procedure --> <hwpErrors> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_PBA_BAR_INDEX_OUT_OF_RANGE</rc> - <description>pba bar index out of range, allowed is 0 to 3</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> <rc>RC_PROC_PBA_BAR_SCOPE_OUT_OF_RANGE</rc> <description>pba bar scope out of range, allowed is 0 to 7</description> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <ffdc>i_index</ffdc> + <ffdc>i_pba_bar_addr</ffdc> + <ffdc>i_pba_bar_size</ffdc> + <ffdc>i_pba_cmd_scope</ffdc> + <ffdc>exp_PBA_CMD_SCOPE_FOREIGN1</ffdc> </hwpError> <!-- *********************************************************************** --> <hwpError> <rc>RC_PROC_PBA_ADDR_OUT_OF_RANGE</rc> <description>pba bar scope out of range, allowed is 0 to 7</description> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <ffdc>i_index</ffdc> + <ffdc>i_pba_bar_addr</ffdc> + <ffdc>i_pba_bar_size</ffdc> + <ffdc>i_pba_cmd_scope</ffdc> + <ffdc>exp_BAR_ADDR_RANGECHECK_HIGH</ffdc> </hwpError> <!-- *********************************************************************** --> <hwpError> <rc>RC_PROC_PBA_ADDR_ALIGNMENT_ERROR</rc> <description>pba BAR must be on a 1MB boundary</description> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <ffdc>i_index</ffdc> + <ffdc>i_pba_bar_addr</ffdc> + <ffdc>i_pba_bar_size</ffdc> + <ffdc>i_pba_cmd_scope</ffdc> + <ffdc>exp_BAR_ADDR_RANGECHECK_LOW</ffdc> </hwpError> <!-- *********************************************************************** --> <hwpError> <rc>RC_PROC_PBA_BAR_SIZE_INVALID</rc> <description>Non-zero PBA BAR defined with region size of 0. Size must be 1MB or greater</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROC_PBA_BAR_MODE_NOT_SUPPORTED</rc> - <description>pba bar procedure mode is not supported .</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROC_PBA_BAR_PUTSCOM_FAILED</rc> - <description>pba bar putscom failed .</description> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <ffdc>i_index</ffdc> + <ffdc>i_pba_bar_addr</ffdc> + <ffdc>i_pba_bar_size</ffdc> + <ffdc>i_pba_cmd_scope</ffdc> </hwpError> <!-- *********************************************************************** --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.H b/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.H index df8b03177..a09c7179e 100644 --- a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.H +++ b/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_mpipl_ex_cleanup.H,v 1.3 2012/11/27 23:11:35 belldi Exp $ +// $Id: proc_mpipl_ex_cleanup.H,v 1.4 2014/03/03 00:42:49 belldi Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_mpipl_ex_cleanup.H,v $ //------------------------------------------------------------------------------ // *| @@ -57,7 +57,7 @@ extern "C" /** * @brief Undo step that prepared fast-winkled cores for scanning and set up deep winkle mode * - * @param[in] (1) 'i_target' Reference to chip target + * @param[in] (1) 'i_target' Reference to processor chip target * * @return ReturnCode * diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup/mss_power_cleanup.C b/src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup/mss_power_cleanup.C index 1ba2a871c..d8fe64beb 100644 --- a/src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup/mss_power_cleanup.C +++ b/src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup/mss_power_cleanup.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_power_cleanup.C,v 1.10 2014/03/25 18:06:03 jdsloat Exp $ +// $Id: mss_power_cleanup.C,v 1.7 2014/02/19 13:41:33 bellows Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_power_cleanup.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -29,7 +29,7 @@ //------------------------------------------------------------------------------ // *! TITLE : mss_power_cleanup // *! DESCRIPTION : see additional comments below -// *! OWNER NAME : Jacob Sloat Email: jdsloat@us.ibm.com +// *! OWNER NAME : Mark Bellows Email: bellows@us.ibm.com // *! BACKUP NAME : Anuwat Saetow Email: asaetow@us.ibm.com // *! ADDITIONAL COMMENTS : @@ -49,9 +49,6 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- -// 1.10 | jdsloat |25-MAR-14| ENUM_ATTR_MSS_INIT_STATE_COLD became fapi::ENUM_ATTR_MSS_INIT_STATE_COLD -// 1.9 | jdsloat |25-MAR-14| Fixed 1.8 -// 1.8 | jdsloat |25-MAR-14| Added a check to break procedure if HW non-functional // 1.7 | bellows |19-FEB-14| RAS Review Updates Pass 2 // 1.6 |bellows |17-FEB-14| RAS review updates // 1.5 |bellows |05-FEB-14| Making this procedure work on really non-functional centaurs @@ -103,7 +100,6 @@ extern "C" { fapi::ReturnCode rc,rc0,rc1,rcf,rcc; uint8_t centaur_functional=1, mba0_functional=1, mba1_functional=1; - uint8_t cen_init_state = 0; FAPI_INF("Running mss_power_cleanupon %s\n", i_target_centaur.toEcmdString()); @@ -118,14 +114,6 @@ extern "C" rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &i_target_mba1, mba1_functional); if(rc) { FAPI_ERR("ERROR: Cannot get ATTR_FUNCTIONAL"); break; } - rc = FAPI_ATTR_GET(ATTR_MSS_INIT_STATE, &i_target_centaur, cen_init_state); - if(rc) { FAPI_ERR("ERROR: Cannot get ATTR_INIT_STATE"); break; } - - if (cen_init_state == fapi::ENUM_ATTR_MSS_INIT_STATE_COLD) - { - FAPI_ERR("Centaur clocks not on. Cannot execute mss_power_cleanup on this target: %s", i_target_centaur.toEcmdString()); break; - } - rc0 = mss_power_cleanup_mba_part1(i_target_centaur, i_target_mba0); rc1 = mss_power_cleanup_mba_part1(i_target_centaur, i_target_mba1); diff --git a/src/usr/hwpf/hwp/dram_training/memory_errors.xml b/src/usr/hwpf/hwp/dram_training/memory_errors.xml index 559711fe4..53efa9466 100644 --- a/src/usr/hwpf/hwp/dram_training/memory_errors.xml +++ b/src/usr/hwpf/hwp/dram_training/memory_errors.xml @@ -21,8 +21,7 @@ <!-- --> <!-- IBM_PROLOG_END_TAG --> <hwpErrors> -<!-- $Id: memory_errors.xml,v 1.00 2013/08/22 19:44:10 mjjones Exp $ --> -<!-- Mike Jones - modified version from 1.42 to 1.00 because it is a sandbox version --> +<!-- $Id: memory_errors.xml,v 1.43 2014/03/09 08:03:24 gpaulraj Exp $ --> <!-- EDIT THIS FILE DIRECTLY. THE ODS FILE METHOD IS NO LONGER VALID --> <!-- *********************************************************************** --> diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C index 965247244..de1a6befc 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit_training_advanced.C,v 1.42 2014/01/23 17:09:52 sasethur Exp $ +// $Id: mss_draminit_training_advanced.C,v 1.43 2014/03/10 16:30:18 jdsloat Exp $ /* File is created by SARAVANAN SETHURAMAN on Thur 29 Sept 2011. */ //------------------------------------------------------------------------------ @@ -82,11 +82,12 @@ // 1.40 | abhijsau |17-DEC-13| added creation and deletion of schmoo object // 1.41 | abhijsau |16-JAN-14| removed EFF_DIMM_TYPE attribute // 1.42 | mjjones |17-Jan-14| Fixed layout and error handling for RAS Review +// 1.43 | jdsloat |10-MAR-14| Edited comments // This procedure Schmoo's DRV_IMP, SLEW, VREF (DDR, CEN), RCV_IMP based on attribute from effective config procedure // DQ & DQS Driver impedance, Slew rate, WR_Vref shmoo would call only write_eye shmoo for margin calculation // DQ & DQS VREF (rd_vref), RCV_IMP shmoo would call rd_eye for margin calculation -// Internal Vref controlled by this function & external vref platform to provide function we return value +// Internal Vref controlled by this function & external vref // Not supported // DDR4, DIMM Types diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C index b87e3e1f7..9ab576cba 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_config_thermal.C,v 1.25 2014/01/21 17:39:47 pardeik Exp $ +// $Id: mss_eff_config_thermal.C,v 1.26 2014/03/10 16:32:09 jdsloat Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/ // centaur/working/procedures/ipl/fapi/mss_eff_config_thermal.C,v $ //------------------------------------------------------------------------------ @@ -53,6 +53,7 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.26 | jdsloat |10-MAR-14| Edited comments // 1.25 | pardeik |21-JAN-14| fixed default power curve values for CDIMM // | | | removed unneeded comments // 1.24 | pardeik |20-DEC-13| only get power curve attributes if custom dimm diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.C index 243eb12ae..41f19c9de 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_throttle_to_power.C,v 1.12 2014/01/06 19:49:21 pardeik Exp $ +// $Id: mss_throttle_to_power.C,v 1.13 2014/03/10 16:31:27 jdsloat Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/ // centaur/working/procedures/ipl/fapi/mss_throttle_to_power.C,v $ //------------------------------------------------------------------------------ @@ -47,6 +47,7 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.13 | jdsloat |10-MAR-14| Edited comments // 1.12 | pardeik |06-JAN-14| added dimm power curve uplift from MRW // | | | use max utiliation from MRW for MAX_UTIL // 1.11 | pardeik |13-NOV-13| changed MAX_UTIL from 75 to 56.25 diff --git a/src/usr/hwpf/hwp/mc_config/mss_volt/memory_mss_volt.xml b/src/usr/hwpf/hwp/mc_config/mss_volt/memory_mss_volt.xml index 5ba5b31f4..d1a4bc700 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_volt/memory_mss_volt.xml +++ b/src/usr/hwpf/hwp/mc_config/mss_volt/memory_mss_volt.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- COPYRIGHT International Business Machines Corp. 2013,2014 --> <!-- --> <!-- p1 --> <!-- --> @@ -21,9 +21,10 @@ <!-- --> <!-- IBM_PROLOG_END_TAG --> <hwpErrors> -<!-- $Id: memory_mss_volt.xml,v 1.1 2013/06/19 18:28:37 bellows Exp $ --> + +<!-- $Id: memory_mss_volt.xml,v 1.2 2014/03/06 00:11:14 jdsloat Exp $ --> <!-- For file ../../ipl/fapi/mss_volt.C --> -<!-- // *! OWNER NAME : Jeff Sabrowski (jsabrow@us.ibm.com) --> +<!-- // *! OWNER NAME : Jacob Sloat (jdsloat@us.ibm.com) --> <!-- // *! BACKUP NAME : --> <!-- Original Source for RC_MSS_VOLT_UNRECOGNIZED_DRAM_DEVICE_TYPE memory_errors.xml --> @@ -31,27 +32,53 @@ <rc>RC_MSS_VOLT_UNRECOGNIZED_DRAM_DEVICE_TYPE</rc> <description>Unsupported DIMM type found. All dimms must be DDR3 or DDR4</description> <ffdc>DEVICE_TYPE</ffdc> -</hwpError> + <callout> + <target>DIMM_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>DIMM_TARGET</target> + </deconfigure> + </hwpError> <!-- Original Source for RC_MSS_VOLT_DDR_TYPE_MIXING_UNSUPPORTED memory_errors.xml --> <hwpError> <rc>RC_MSS_VOLT_DDR_TYPE_MIXING_UNSUPPORTED</rc> <description>Mixing of DDR3 and DDR4 not supported.</description> -</hwpError> + <ffdc>DEVICE_TYPE</ffdc> + <callout> + <target>DIMM_DDR4_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>DIMM_DDR4_TARGET</target> + </deconfigure> + </hwpError> <!-- Original Source for RC_MSS_VOLT_DDR_TYPE_REQUIRED_VOLTAGE memory_errors.xml --> <hwpError> <rc>RC_MSS_VOLT_DDR_TYPE_REQUIRED_VOLTAGE</rc> <description>One or more DIMMs do not support required voltage for DDR type.</description> -</hwpError> + <ffdc>DIMM_VOLTAGE</ffdc> + <callout> + <target>DIMM_UV_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>DIMM_UV_TARGET</target> + </deconfigure> + </hwpError> <!-- Original Source for RC_MSS_VOLT_TOLERATED_VOLTAGE_VIOLATION memory_errors.xml --> <hwpError> <rc>RC_MSS_VOLT_TOLERATED_VOLTAGE_VIOLATION</rc> <description>One or more DIMMs classified non-functional has a tolerated voltage below selected voltage.</description> - <!-- Deconfigure MASTER_CHIP --> - <deconfigure><target>MASTER_CHIP</target></deconfigure> -</hwpError> - + <ffdc>DIMM_VOLTAGE</ffdc> + <!-- Deconfigure DIMM or Centaur --> + <deconfigure> + <target>CHIP_TARGET</target> + </deconfigure> + </hwpError> </hwpErrors> + diff --git a/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt.C b/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt.C index 3122a28a1..ea4d52b08 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt.C +++ b/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_volt.C,v 1.12 2012/10/18 14:46:36 jdsloat Exp $ +// $Id: mss_volt.C,v 1.13 2014/03/06 00:13:52 jdsloat Exp $ /* File mss_volt.C created by JEFF SABROWSKI on Fri 21 Oct 2011. */ //------------------------------------------------------------------------------ @@ -30,7 +30,7 @@ //------------------------------------------------------------------------------ // *! TITLE : mss_volt.C // *! DESCRIPTION : Tools for centaur procedures -// *! OWNER NAME : Jeff Sabrowski (jsabrow@us.ibm.com) +// *! OWNER NAME : Jacob Sloat (jdsloat@us.ibm.com) // *! BACKUP NAME : // #! ADDITIONAL COMMENTS : // @@ -53,6 +53,7 @@ // 1.10 | jdsloat | 05/09/12 | Fixed typo // 1.11 | bellows | 07/16/12 | added in Id tag // 1.11 | jdsloat | 10/18/12 | Added check for violation of tolerant voltages of non-functional dimms. +// 1.12 | jdsloat | 03/05/14 | RAS review Edits -- Error HW callouts // This procedure takes a vector of Centaurs behind a voltage domain, // reads in supported DIMM voltages from SPD and determines optimal @@ -76,161 +77,297 @@ const uint32_t MAX_TOLERATED_DDR4_VOLT = 1200; fapi::ReturnCode mss_volt(std::vector<fapi::Target> & i_targets_memb) { - fapi::ReturnCode l_rc; - uint8_t l_dimm_functionality=0; - uint8_t l_spd_dramtype=0; - uint8_t l_spd_volts=0; - uint8_t l_spd_volts_all_dimms=0x06; //start assuming all voltages supported - uint8_t l_dram_ddr3_found_flag=0; - uint8_t l_dram_ddr4_found_flag=0; + fapi::ReturnCode l_rc; + uint8_t l_dimm_functionality=0; + uint8_t l_spd_dramtype=0; + uint8_t l_spd_volts=0; + uint8_t l_spd_volts_all_dimms=0x06; //start assuming all voltages supported + uint8_t l_dram_ddr3_found_flag=0; + uint8_t l_dram_ddr4_found_flag=0; - uint32_t l_selected_dram_voltage=0; //this gets written into all centaurs when done. - uint32_t l_tolerated_dram_voltage = MAX_TOLERATED_VOLT; //initially set to the max tolerated voltage + uint32_t l_selected_dram_voltage=0; //this gets written into all centaurs when done. + uint32_t l_tolerated_dram_voltage = MAX_TOLERATED_VOLT; //initially set to the max tolerated voltage - // Iterate through the list of centaurs - for (uint32_t i=0; i < i_targets_memb.size(); i++) + do { - std::vector<fapi::Target> l_mbaChiplets; - // Get associated MBA's on this centaur - l_rc=fapiGetChildChiplets(i_targets_memb[i], fapi::TARGET_TYPE_MBA_CHIPLET, l_mbaChiplets); - if (l_rc) return l_rc; - // Loop through the 2 MBA's - for (uint32_t j=0; j < l_mbaChiplets.size(); j++) - { - std::vector<fapi::Target> l_dimm_targets; - // Get a vector of DIMM targets - l_rc = fapiGetAssociatedDimms(l_mbaChiplets[j], l_dimm_targets, fapi::TARGET_STATE_PRESENT); - if (l_rc) return l_rc; - for (uint32_t k=0; k < l_dimm_targets.size(); k++) - { - l_rc = FAPI_ATTR_GET(ATTR_SPD_DRAM_DEVICE_TYPE, &l_dimm_targets[k], l_spd_dramtype); - if (l_rc) return l_rc; - l_rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_NOMINAL_VOLTAGE, &l_dimm_targets[k], l_spd_volts); - if (l_rc) return l_rc; - l_rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_dimm_targets[k], l_dimm_functionality); - if (l_rc) return l_rc; - - // spd_volts: bit0= NOT 1.5V bit1=1.35V bit2=1.25V, assume a 1.20V in future for DDR4 - // check for supported voltage/dram type combo DDR3=12, DDR4=13 - if (l_spd_dramtype == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) - { - l_dram_ddr3_found_flag=1; - } - else if (l_spd_dramtype == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) - { - l_dram_ddr4_found_flag=1; - } - else - { - uint8_t &DEVICE_TYPE = l_spd_dramtype; - FAPI_ERR("Unknown DRAM Device Type 0x%x", l_spd_dramtype); - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_VOLT_UNRECOGNIZED_DRAM_DEVICE_TYPE); - return l_rc; - } - - if(l_dimm_functionality == fapi::ENUM_ATTR_FUNCTIONAL_FUNCTIONAL) - { - //AND dimm voltage capabilities together to find aggregate voltage support on all dimms - l_spd_volts_all_dimms = l_spd_volts_all_dimms & l_spd_volts; - } - - } - } - } - - // now we figure out if we have a supported ddr type and voltage - // note: only support DDR3=1.35V and DDR4=1.2xV - - if (l_dram_ddr3_found_flag && l_dram_ddr4_found_flag) - { - FAPI_ERR("mss_volt: DDR3 and DDR4 mixing not allowed"); - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_VOLT_DDR_TYPE_MIXING_UNSUPPORTED); - return l_rc; - } - if (l_dram_ddr3_found_flag && ((l_spd_volts_all_dimms & fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_OP1_35) == fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_OP1_35)) - { - l_selected_dram_voltage=1350; - } - else if (l_dram_ddr4_found_flag && ((l_spd_volts_all_dimms & fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_OP1_2X) == fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_OP1_2X)) - { - l_selected_dram_voltage=1200; - } - else if ((l_spd_volts_all_dimms & fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_NOTOP1_5) != fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_NOTOP1_5) - { - l_selected_dram_voltage=1500; - } - else - { - FAPI_ERR("One or more DIMMs do not support required voltage for DIMM type"); - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_VOLT_DDR_TYPE_REQUIRED_VOLTAGE); - return l_rc; - } - -/* if( l_selected_dram_voltage > l_supported_dram_voltage) - { - FAPI_INF( "Selected Voltage larger than highest supported voltage. Selected Voltage: %d Supported Voltage: %d ", l_selected_dram_voltage, l_supported_dram_voltage); - FAPI_INF( "Using supported Voltage."); - l_selected_dram_voltage = l_supported_dram_voltage; - } -*/ - - // Must check to see if we violate Tolerent voltages of Non-functional Dimms - // If so we must error/deconfigure on the centaur level. - // Iterate through the list of centaurs - for (uint32_t i=0; i < i_targets_memb.size(); i++) - { - l_tolerated_dram_voltage = MAX_TOLERATED_VOLT; // using 1.5 as this is the largest supported voltage - std::vector<fapi::Target> l_mbaChiplets; - // Get associated MBA's on this centaur - l_rc=fapiGetChildChiplets(i_targets_memb[i], fapi::TARGET_TYPE_MBA_CHIPLET, l_mbaChiplets); - if (l_rc) return l_rc; - for (uint32_t j=0; j < l_mbaChiplets.size(); j++) - { - std::vector<fapi::Target> l_dimm_targets; - // Get a vector of DIMM targets - l_rc = fapiGetAssociatedDimms(l_mbaChiplets[j], l_dimm_targets, fapi::TARGET_STATE_PRESENT); - if (l_rc) return l_rc; - for (uint32_t k=0; k < l_dimm_targets.size(); k++) - { - l_rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_dimm_targets[k], l_dimm_functionality); - if (l_rc) return l_rc; - - if(l_dimm_functionality == fapi::ENUM_ATTR_FUNCTIONAL_NON_FUNCTIONAL) - { - if ( (l_spd_dramtype == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) && (l_tolerated_dram_voltage > MAX_TOLERATED_DDR3_VOLT) ) - { - l_tolerated_dram_voltage = MAX_TOLERATED_DDR3_VOLT; - } - if ( (l_spd_dramtype == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) && (l_tolerated_dram_voltage > MAX_TOLERATED_DDR4_VOLT) ) - { - l_tolerated_dram_voltage = MAX_TOLERATED_DDR4_VOLT; - } - } - } - } - - if ( l_tolerated_dram_voltage < l_selected_dram_voltage ) - { - FAPI_ERR("One or more DIMMs classified non-functional has a tolerated voltage below selected voltage."); - FAPI_ERR("Deconfiguring the associated Centaur."); - const fapi::Target & MASTER_CHIP = i_targets_memb[i]; - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_VOLT_TOLERATED_VOLTAGE_VIOLATION); - return l_rc; - } - } - - - // Iterate through the list of centaurs again, to update ATTR - for (uint32_t i=0; i < i_targets_memb.size(); i++) - { - l_rc = FAPI_ATTR_SET(ATTR_MSS_VOLT, &i_targets_memb[i], l_selected_dram_voltage); - FAPI_INF( "mss_volt calculation complete. MSS_VOLT: %d", l_selected_dram_voltage); - if (l_rc) return l_rc; - } - - return l_rc; -} + // Iterate through the list of centaurs + for (uint32_t i=0; i < i_targets_memb.size(); i++) + { + std::vector<fapi::Target> l_mbaChiplets; + // Get associated MBA's on this centaur + l_rc=fapiGetChildChiplets(i_targets_memb[i], fapi::TARGET_TYPE_MBA_CHIPLET, l_mbaChiplets); + if (l_rc) break; + // Loop through the 2 MBA's + for (uint32_t j=0; j < l_mbaChiplets.size(); j++) + { + std::vector<fapi::Target> l_dimm_targets; + // Get a vector of DIMM targets + l_rc = fapiGetAssociatedDimms(l_mbaChiplets[j], l_dimm_targets, fapi::TARGET_STATE_PRESENT); + if (l_rc) break; + for (uint32_t k=0; k < l_dimm_targets.size(); k++) + { + l_rc = FAPI_ATTR_GET(ATTR_SPD_DRAM_DEVICE_TYPE, &l_dimm_targets[k], l_spd_dramtype); + if (l_rc) break; + l_rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_NOMINAL_VOLTAGE, &l_dimm_targets[k], l_spd_volts); + if (l_rc) break; + l_rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_dimm_targets[k], l_dimm_functionality); + if (l_rc) break; + + // spd_volts: bit0= NOT 1.5V bit1=1.35V bit2=1.25V, assume a 1.20V in future for DDR4 + // check for supported voltage/dram type combo DDR3=12, DDR4=13 + if (l_spd_dramtype == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) + { + l_dram_ddr3_found_flag=1; + } + else if (l_spd_dramtype == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) + { + l_dram_ddr4_found_flag=1; + } + else + { + // this just needs to be deconfiged at the dimm level + const uint8_t &DEVICE_TYPE = l_spd_dramtype; + const fapi::Target &DIMM_TARGET = l_dimm_targets[k]; + FAPI_ERR("Unknown DRAM Device Type 0x%x", l_spd_dramtype); + FAPI_SET_HWP_ERROR(l_rc, RC_MSS_VOLT_UNRECOGNIZED_DRAM_DEVICE_TYPE); + fapiLogError(l_rc); + } + + if(l_dimm_functionality == fapi::ENUM_ATTR_FUNCTIONAL_FUNCTIONAL) + { + //AND dimm voltage capabilities together to find aggregate voltage support on all dimms + l_spd_volts_all_dimms = l_spd_volts_all_dimms & l_spd_volts; + } + + }//end of dimms loop + if (l_rc) + { + break; + } + }//end of mba loop + if (l_rc) + { + break; + } + }//end of centaur (memb) loop + if (l_rc) + { + // Break out of do...while(0) + break; + } + + // now we figure out if we have a supported ddr type and voltage + // note: only support DDR3=1.35V and DDR4=1.2xV + + + // Mixed Dimms, Deconfig the DDR4. + if (l_dram_ddr3_found_flag && l_dram_ddr4_found_flag) + { + std::vector<fapi::Target> l_dimm_targets_deconfig; + // Iterate through the list of centaurs + for (uint32_t i=0; i < i_targets_memb.size(); i++) + { + std::vector<fapi::Target> l_mbaChiplets; + // Get associated MBA's on this centaur + l_rc=fapiGetChildChiplets(i_targets_memb[i], fapi::TARGET_TYPE_MBA_CHIPLET, l_mbaChiplets); + if (l_rc) break; + // Loop through the 2 MBA's + for (uint32_t j=0; j < l_mbaChiplets.size(); j++) + { + std::vector<fapi::Target> l_dimm_targets; + // Get a vector of DIMM targets + l_rc = fapiGetAssociatedDimms(l_mbaChiplets[j], l_dimm_targets, fapi::TARGET_STATE_PRESENT); + if (l_rc) break; + for (uint32_t k=0; k < l_dimm_targets.size(); k++) + { + + l_rc = FAPI_ATTR_GET(ATTR_SPD_DRAM_DEVICE_TYPE, &l_dimm_targets[k], l_spd_dramtype); + if (l_rc) break; + + if (l_spd_dramtype == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) + { + const fapi::Target &DIMM_DDR4_TARGET = l_dimm_targets[k]; + const uint8_t &DEVICE_TYPE = l_spd_dramtype; + FAPI_ERR("mss_volt: DDR3 and DDR4 mixing not allowed"); + FAPI_SET_HWP_ERROR(l_rc, RC_MSS_VOLT_DDR_TYPE_MIXING_UNSUPPORTED); + fapiLogError(l_rc); + } + + }//end of dimms loop + if (l_rc) + { + break; + } + }//end of mba loop + if (l_rc) + { + break; + } + }//end of centaur (memb) loop + } + if (l_rc) + { + // Break out of do...while(0) + break; + } + if (l_dram_ddr3_found_flag && ((l_spd_volts_all_dimms & fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_OP1_35) == fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_OP1_35)) + { + l_selected_dram_voltage=1350; + } + else if (l_dram_ddr4_found_flag && ((l_spd_volts_all_dimms & fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_OP1_2X) == fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_OP1_2X)) + { + l_selected_dram_voltage=1200; + } + else if ((l_spd_volts_all_dimms & fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_NOTOP1_5) != fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_NOTOP1_5) + { + l_selected_dram_voltage=1500; + } + else + { + std::vector<fapi::Target> l_dimm_targets_deconfig; + // Iterate through the list of centaurs + for (uint32_t i=0; i < i_targets_memb.size(); i++) + { + std::vector<fapi::Target> l_mbaChiplets; + // Get associated MBA's on this centaur + l_rc=fapiGetChildChiplets(i_targets_memb[i], fapi::TARGET_TYPE_MBA_CHIPLET, l_mbaChiplets); + if (l_rc) break; + // Loop through the 2 MBA's + for (uint32_t j=0; j < l_mbaChiplets.size(); j++) + { + std::vector<fapi::Target> l_dimm_targets; + // Get a vector of DIMM targets + l_rc = fapiGetAssociatedDimms(l_mbaChiplets[j], l_dimm_targets, fapi::TARGET_STATE_PRESENT); + if (l_rc) break; + for (uint32_t k=0; k < l_dimm_targets.size(); k++) + { + l_rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_NOMINAL_VOLTAGE, &l_dimm_targets[k], l_spd_volts); + if (l_rc) break; + if((l_spd_volts & fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_NOTOP1_5) == fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_NOTOP1_5) + { + const fapi::Target &DIMM_UV_TARGET = l_dimm_targets[k]; + const uint8_t &DIMM_VOLTAGE = l_spd_volts; + FAPI_ERR("One or more DIMMs do not support required voltage for DIMM type"); + FAPI_SET_HWP_ERROR(l_rc, RC_MSS_VOLT_DDR_TYPE_REQUIRED_VOLTAGE); + fapiLogError(l_rc); + } + + }//end of dimms loop + if (l_rc) + { + break; + } + }//end of mba loop + if (l_rc) + { + break; + } + }//end of centaur (memb) loop + } + if (l_rc) + { + // Break out of do...while(0) + break; + } + + // Must check to see if we violate Tolerent voltages of Non-functional Dimms + // If so we must error/deconfigure on the dimm level primarily then centaur level. + // Iterate through the list of centaurs + for (uint32_t i=0; i < i_targets_memb.size(); i++) + { + std::vector<fapi::Target> l_dimm_targets_deconfig; + + l_tolerated_dram_voltage = MAX_TOLERATED_VOLT; // using 1.5 as this is the largest supported voltage + std::vector<fapi::Target> l_mbaChiplets; + // Get associated MBA's on this centaur + l_rc=fapiGetChildChiplets(i_targets_memb[i], fapi::TARGET_TYPE_MBA_CHIPLET, l_mbaChiplets); + if (l_rc) break; + for (uint32_t j=0; j < l_mbaChiplets.size(); j++) + { + std::vector<fapi::Target> l_dimm_targets; + // Get a vector of DIMM targets + l_rc = fapiGetAssociatedDimms(l_mbaChiplets[j], l_dimm_targets, fapi::TARGET_STATE_PRESENT); + if (l_rc) break; + for (uint32_t k=0; k < l_dimm_targets.size(); k++) + { + l_rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_dimm_targets[k], l_dimm_functionality); + if (l_rc) break; + + if(l_dimm_functionality == fapi::ENUM_ATTR_FUNCTIONAL_NON_FUNCTIONAL) + { + if (l_spd_dramtype == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) + { + if (l_tolerated_dram_voltage > MAX_TOLERATED_DDR3_VOLT) + { + l_tolerated_dram_voltage = MAX_TOLERATED_DDR3_VOLT; + } + + if (MAX_TOLERATED_DDR3_VOLT < l_selected_dram_voltage) + { + FAPI_ERR("One or more DIMMs classified non-functional has a" + " tolerated voltage below selected voltage."); + const fapi::Target & CHIP_TARGET = l_dimm_targets[k]; + const uint8_t &DIMM_VOLTAGE = l_selected_dram_voltage; + FAPI_SET_HWP_ERROR(l_rc, RC_MSS_VOLT_TOLERATED_VOLTAGE_VIOLATION); + fapiLogError(l_rc); + } + } + if (l_spd_dramtype == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) + { + if (l_tolerated_dram_voltage > MAX_TOLERATED_DDR4_VOLT) + { + l_tolerated_dram_voltage = MAX_TOLERATED_DDR4_VOLT; + } + + if (MAX_TOLERATED_DDR4_VOLT < l_selected_dram_voltage) + { + FAPI_ERR("One or more DIMMs classified non-functional has a" + " tolerated voltage below selected voltage."); + const fapi::Target & CHIP_TARGET = l_dimm_targets[k]; + const uint8_t &DIMM_VOLTAGE = l_selected_dram_voltage; + FAPI_SET_HWP_ERROR(l_rc, RC_MSS_VOLT_TOLERATED_VOLTAGE_VIOLATION); + fapiLogError(l_rc); + } + } + + }//End of functional check + }//End of Dimm loop + if (l_rc) + { + break; + } + }// End of MBA loop + if (l_rc) + { + break; + } + if ( l_tolerated_dram_voltage < l_selected_dram_voltage ) + { + + FAPI_ERR("Deconfiguring the associated Centaur."); + const fapi::Target & CHIP_TARGET = i_targets_memb[i]; + const uint8_t &DIMM_VOLTAGE = l_selected_dram_voltage; + FAPI_SET_HWP_ERROR(l_rc, RC_MSS_VOLT_TOLERATED_VOLTAGE_VIOLATION); + break; + } + }//End of Centaur (MEMB) loop + if (l_rc) + { + // Break out of do...while(0) + break; + } + + // Iterate through the list of centaurs again, to update ATTR + for (uint32_t i=0; i < i_targets_memb.size(); i++) + { + l_rc = FAPI_ATTR_SET(ATTR_MSS_VOLT, &i_targets_memb[i], l_selected_dram_voltage); + FAPI_INF( "mss_volt calculation complete. MSS_VOLT: %d", l_selected_dram_voltage); + if (l_rc) break; + } + }while(0); + return l_rc; +} diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.C index 3a5a131f1..104cf720a 100755..100644 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.C @@ -20,9 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ - -// $Id: p8_pm_pmc_firinit.C,v 1.16 2014/01/14 17:13:31 stillgs Exp $ -// $Source: /archive/shadow/ekb/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pmc_firinit.C,v $ +// $Id: p8_pm_pmc_firinit.C,v 1.19 2014/03/06 19:03:25 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pmc_firinit.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -44,6 +43,7 @@ // *! Procedure Prereq: // *! o System clocks are running // *! +// *! buildfapiprcd p8_pm_pmc_firinit.C //------------------------------------------------------------------------------ @@ -101,6 +101,8 @@ p8_pm_pmc_firinit(const fapi::Target& i_target , uint32_t mode ) ecmdDataBufferBase action_0(64); ecmdDataBufferBase action_1(64); ecmdDataBufferBase mask(64); + ecmdDataBufferBase pmc_ocb_mask_hi(64); + ecmdDataBufferBase pmc_ocb_mask_lo(64); uint32_t e_rc = 0; @@ -124,9 +126,42 @@ p8_pm_pmc_firinit(const fapi::Target& i_target , uint32_t mode ) rc = fapiPutScom(i_target, PMC_LFIR_MASK_0x01010843, mask ); if (rc) { - FAPI_ERR("fapiPutScom(PMC_LFIR_MASK_0x01010843) failed."); + FAPI_ERR("fapiPutScom(PMC_LFIR_MASK_0x01010843) failed."); + break; + } + + + // Clear pmc_ocb_mask_[hi/lo] as these are really enables, not masks. + e_rc |= pmc_ocb_mask_hi.flushTo0(); + e_rc |= pmc_ocb_mask_lo.flushTo0(); + if (e_rc) + { + rc.setEcmdError(e_rc); + break; + } + + //#--****************************************************************************** + //#-- PMC OCB Mask Hi + //#--****************************************************************************** + + rc = fapiPutScom(i_target, PMC_ERROR_INT_MASK_HI_0x00062067, pmc_ocb_mask_hi ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_ERROR_INT_MASK_HI_0x00062067) failed."); + break; + } + + //#--****************************************************************************** + //#-- PMC OCB Mask Lo + //#--****************************************************************************** + + rc = fapiPutScom(i_target, PMC_ERROR_INT_MASK_LO_0x00062068, pmc_ocb_mask_lo ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_ERROR_INT_MASK_LO_0x00062068) failed."); break; } + } else if (mode == PM_RESET_SOFT) { @@ -135,7 +170,7 @@ p8_pm_pmc_firinit(const fapi::Target& i_target , uint32_t mode ) rc = fapiGetScom(i_target, PMC_LFIR_MASK_0x01010843, mask ); if (rc) { - FAPI_ERR("fapiGetScom(PMC_LFIR_MASK_0x01010843) failed."); + FAPI_ERR("fapiGetScom(PMC_LFIR_MASK_0x01010843) failed."); break; } @@ -157,9 +192,51 @@ p8_pm_pmc_firinit(const fapi::Target& i_target , uint32_t mode ) rc = fapiPutScom(i_target, PMC_LFIR_MASK_0x01010843, mask ); if (rc) { - FAPI_ERR("fapiPutScom(PMC_LFIR_MASK_0x01010843) failed."); + FAPI_ERR("fapiPutScom(PMC_LFIR_MASK_0x01010843) failed."); + break; + } + + //--****************************************************************************** + //-- PMC_FIR_MASK (W0_OR_45) (WR_43) (WO_AND_44) + //--****************************************************************************** + rc = fapiPutScom(i_target, PMC_LFIR_MASK_0x01010843, mask ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_LFIR_MASK_0x01010843) failed."); + break; + } + + // Clear pmc_ocb_mask_[hi/lo] as these are really enables, not masks. + e_rc |= pmc_ocb_mask_hi.flushTo0(); + e_rc |= pmc_ocb_mask_lo.flushTo0(); + if (e_rc) + { + rc.setEcmdError(e_rc); break; } + + //#--****************************************************************************** + //#-- PMC OCB Mask Hi + //#--****************************************************************************** + + rc = fapiPutScom(i_target, PMC_ERROR_INT_MASK_HI_0x00062067, pmc_ocb_mask_hi ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_ERROR_INT_MASK_HI_0x00062067) failed."); + break; + } + + //#--****************************************************************************** + //#-- PMC OCB Mask Lo + //#--****************************************************************************** + + rc = fapiPutScom(i_target, PMC_ERROR_INT_MASK_LO_0x00062068, pmc_ocb_mask_lo ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_ERROR_INT_MASK_LO_0x00062068) failed."); + break; + } + } else { @@ -196,8 +273,8 @@ p8_pm_pmc_firinit(const fapi::Target& i_target , uint32_t mode ) SET_FIR_MASKED(SPIVID_CRC_ERROR0 ); // 20 spivid_crc_error0 SET_FIR_MASKED(SPIVID_CRC_ERROR1 ); // 21 spivid_crc_error1 SET_FIR_MASKED(SPIVID_CRC_ERROR2 ); // 22 spivid_crc_error2 - SET_FIR_MASKED(SPIVID_RETRY_TIMEOUT ); // 23 spivid_retry_timeout - SET_FIR_MASKED(SPIVID_FSM_ERR ); // 24 spivid_fsm_err + SET_RECOV_ATTN(SPIVID_RETRY_TIMEOUT ); // 23 spivid_retry_timeout + SET_RECOV_ATTN(SPIVID_FSM_ERR ); // 24 spivid_fsm_err SET_FIR_MASKED(SPIVID_MAJORITY_DETECTED_A_MINORITY ); // 25 spivid_majority_detected_a_minority SET_FIR_MASKED(O2S_CRC_ERROR0 ); // 26 o2s_crc_error0 SET_FIR_MASKED(O2S_CRC_ERROR1 ); // 27 o2s_crc_error1 @@ -210,7 +287,7 @@ p8_pm_pmc_firinit(const fapi::Target& i_target , uint32_t mode ) SET_FIR_MASKED(O2P_FSM_ERR ); // 34 o2p_fsm_err SET_FIR_MASKED(OCI_SLAVE_ERR ); // 35 oci_slave_err SET_MALF_ALERT(IF_COMP_PARITY_ERR ); // 36 if_comp_parity_err - SET_RECOV_INTR(IDLE_RECOVERY_NOTIFY_PRD ); // 37 idle_recovery_notify_prd + SET_RECOV_ATTN(IDLE_RECOVERY_NOTIFY_PRD ); // 37 idle_recovery_notify_prd SET_FIR_MASKED(FIR_PARITY_ERR_DUP ); // 47 fir_parity_err_dup SET_FIR_MASKED(FIR_PARITY_ERR ); // 48 fir_parity_err @@ -220,9 +297,9 @@ p8_pm_pmc_firinit(const fapi::Target& i_target , uint32_t mode ) break; } - FAPI_DBG(" action_0 => 0x%16llx ", action_0.getDoubleWord(0)); - FAPI_DBG(" action_1 => 0x%16llx ", action_1.getDoubleWord(0)); - FAPI_DBG(" mask => 0x%16llx ", mask.getDoubleWord(0)); + FAPI_DBG(" action_0 => 0x%016llx ", action_0.getDoubleWord(0)); + FAPI_DBG(" action_1 => 0x%016llx ", action_1.getDoubleWord(0)); + FAPI_DBG(" mask => 0x%016llx ", mask.getDoubleWord(0)); //#--****************************************************************************** //#-- PMC_FIR - clear @@ -266,6 +343,90 @@ p8_pm_pmc_firinit(const fapi::Target& i_target , uint32_t mode ) FAPI_ERR("fapiPutScom(PMC_LFIR_MASK_0x01010843) failed."); break; } + + // Set the PMC OCB Masks to enable OCC interrupts on FIR bits + // Note: the descrption of the bit says "mask" but it takes a 1 + // to enable them. + + e_rc |= pmc_ocb_mask_hi.flushTo0(); + e_rc |= pmc_ocb_mask_lo.flushTo0(); + + // PMC OCB Mask Hi + e_rc |= pmc_ocb_mask_hi.setBit(PSTATE_OCI_MASTER_RDERR ); // 0 pstate_oci_master_rderr + e_rc |= pmc_ocb_mask_hi.setBit(PSTATE_OCI_MASTER_RDDATA_PARITY_ERR ); // 1 pstate_oci_master_rddata_parity_err + e_rc |= pmc_ocb_mask_hi.setBit(PSTATE_GPST_CHECKBYTE_ERR ); // 2 pstate_gpst_checkbyte_err + e_rc |= pmc_ocb_mask_hi.setBit(PSTATE_GACK_TO_ERR ); // 3 pstate_gack_to_err + e_rc |= pmc_ocb_mask_hi.setBit(PSTATE_PIB_MASTER_NONOFFLINE_ERR ); // 4 pstate_pib_master_nonoffline_err + e_rc |= pmc_ocb_mask_hi.setBit(PSTATE_PIB_MASTER_OFFLINE_ERR ); // 5 pstate_pib_master_offline_err + e_rc |= pmc_ocb_mask_hi.setBit(PSTATE_OCI_MASTER_TO_ERR ); // 6 pstate_oci_master_to_err + e_rc |= pmc_ocb_mask_hi.setBit(PSTATE_INTERCHIP_UE_ERR ); // 7 pstate_interchip_ue_err + e_rc |= pmc_ocb_mask_hi.setBit(PSTATE_INTERCHIP_ERRORFRAME_ERR ); // 8 pstate_interchip_errorframe_err + e_rc |= pmc_ocb_mask_hi.setBit(PSTATE_MS_FSM_ERR ); // 9 pstate_ms_fsm_err + e_rc |= pmc_ocb_mask_hi.setBit(MS_COMP_PARITY_ERR ); // 10 ms_comp_parity_err + e_rc |= pmc_ocb_mask_hi.setBit(IDLE_PORESW_FATAL_ERR ); // 11 idle_poresw_fatal_err + e_rc |= pmc_ocb_mask_hi.setBit(IDLE_PORESW_STATUS_RC_ERR ); // 12 idle_poresw_status_rc_err + e_rc |= pmc_ocb_mask_hi.setBit(IDLE_PORESW_STATUS_VALUE_ERR ); // 13 idle_poresw_status_value_err + e_rc |= pmc_ocb_mask_hi.setBit(IDLE_PORESW_WRITE_WHILE_INACTIVE_ERR ); // 14 idle_poresw_write_while_inactive_err + e_rc |= pmc_ocb_mask_hi.setBit(IDLE_PORESW_TIMEOUT_ERR ); // 15 idle_poresw_timeout_err +// Left 0 (IDLE_OCI_MASTER_WRITE_TIMEOUT_ERR ); // 16 idle_oci_master_write_timeout_err + e_rc |= pmc_ocb_mask_hi.setBit(IDLE_INTERNAL_ERR ); // 17 idle_internal_err + e_rc |= pmc_ocb_mask_hi.setBit(INT_COMP_PARITY_ERR ); // 18 int_comp_parity_err +// Left 0 (PMC_OCC_HEARTBEAT_TIMEOUT ); // 19 pmc_occ_heartbeat_timeout +// Left 0 (SPIVID_CRC_ERROR0 ); // 20 spivid_crc_error0 +// Left 0 (SPIVID_CRC_ERROR1 ); // 21 spivid_crc_error1 +// Left 0 (SPIVID_CRC_ERROR2 ); // 22 spivid_crc_error2 + e_rc |= pmc_ocb_mask_hi.setBit(SPIVID_RETRY_TIMEOUT ); // 23 spivid_retry_timeout + e_rc |= pmc_ocb_mask_hi.setBit(SPIVID_FSM_ERR ); // 24 spivid_fsm_err +// Left 0 (SPIVID_MAJORITY_DETECTED_A_MINORITY ); // 25 spivid_majority_detected_a_minority +// Left 0 (O2S_CRC_ERROR0 ); // 26 o2s_crc_error0 +// Left 0 (O2S_CRC_ERROR1 ); // 27 o2s_crc_error1 +// Left 0 (O2S_CRC_ERROR2 ); // 28 o2s_crc_error2 +// Left 0 (O2S_RETRY_TIMEOUT ); // 29 o2s_retry_timeout +// Left 0 (O2S_WRITE_WHILE_BRIDGE_BUSY_ERR ); // 30 o2s_write_while_bridge_busy_err +// Left 0 (O2S_FSM_ERR ); // 31 o2s_fsm_err + + // PMC OCB Mask Lo +// Left 0 (O2S_MAJORITY_DETECTED_A_MINORITY ); // 32 o2s_majority_detected_a_minority +// Left 0 (O2P_WRITE_WHILE_BRIDGE_BUSY_ERR ); // 33 o2p_write_while_bridge_busy_err + e_rc |= pmc_ocb_mask_lo.setBit(O2P_FSM_ERR - 32 ); // 34 o2p_fsm_err + e_rc |= pmc_ocb_mask_lo.setBit(OCI_SLAVE_ERR - 32 ); // 35 oci_slave_err +// (IF_COMP_PARITY_ERR ); // 36 if_comp_parity_err +// IDLE_RECOVERY_NOTIFY_PRD ); // 37 idle_recovery_notify_prd +// Left 0 (FIR_PARITY_ERR_DUP ); // 47 fir_parity_err_dup +// Left 0 (FIR_PARITY_ERR ); // 48 fir_parity_err + + + if (e_rc) + { + rc.setEcmdError(e_rc); + break; + } + + FAPI_DBG(" pmc_ocb_mask_hi => 0x%016llx ", pmc_ocb_mask_hi.getDoubleWord(0)); + FAPI_DBG(" pmc_ocb_mask_lo => 0x%016llx ", pmc_ocb_mask_lo.getDoubleWord(0)); + + //#--****************************************************************************** + //#-- PMC OCB Mask Hi + //#--****************************************************************************** + + rc = fapiPutScom(i_target, PMC_ERROR_INT_MASK_HI_0x00062067, pmc_ocb_mask_hi ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_ERROR_INT_MASK_HI_0x00062067) failed."); + break; + } + + //#--****************************************************************************** + //#-- PMC OCB Mask Lo + //#--****************************************************************************** + + rc = fapiPutScom(i_target, PMC_ERROR_INT_MASK_LO_0x00062068, pmc_ocb_mask_lo ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_ERROR_INT_MASK_LO_0x00062068) failed."); + break; + } + } } while(0); @@ -274,4 +435,4 @@ p8_pm_pmc_firinit(const fapi::Target& i_target , uint32_t mode ) } // Procedure -} //end extern C
\ No newline at end of file +} //end extern C diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C index 0fe39258c..29e0314eb 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013 */ +/* COPYRIGHT International Business Machines Corp. 2013,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_pmc_init.C,v 1.37 2013/11/07 14:00:09 stillgs Exp $ +// $Id: p8_pmc_init.C,v 1.41 2014/04/03 20:29:13 cmolsen Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pmc_init.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -28,22 +28,15 @@ // *! *** IBM Confidential *** //------------------------------------------------------------------------------ // *! OWNER NAME: Pradeep CN Email: pradeepcn@in.ibm.com +// *! OWNER NAME: Greg Still Email: stillgs@us.ibm.com // *! -// *! General Description: -// *! -// *! The purpose of this procedure is to ...... -// *! -// *! High-level procedure flow: -// *! o Do thing 1 -// *! o Do thing 2 -// *! o Do thing 3 -// *! o Check if all went well -// *! o If so celebrate -// *! o Else write logs, set bad return code -// *! -// *! Procedure Prereq: -// *! o System clocks are running -// *! +/// \verbatim +/// High-level procedure flow: +/// +/// T +/// +/// \endverbatim +/// buildfapiprcd -e "../../xml/error_info/p8_pmc_errors.xml,../../xml/error_info/p8_pstate_registers.xml" p8_pmc_init.C //------------------------------------------------------------------------------ @@ -60,6 +53,9 @@ #define PSTATE_HALT_POLL_COUNT 256 #define PORE_REQ_POLL_COUNT 256 +#define MASTER_SIDE 0 +#define SLAVE_SIDE 1 + extern "C" { using namespace fapi; @@ -68,6 +64,28 @@ using namespace fapi; // Function prototypes // ---------------------------------------------------------------------- +fapi::ReturnCode +p8_pmc_poll_pstate_halt( const fapi::Target & i_target, + const uint8_t i_side); + +fapi::ReturnCode +p8_pmc_poll_idle_halt( const fapi::Target & i_target, + const uint8_t i_side); + +fapi::ReturnCode +p8_pmc_poll_interchip_halt( const fapi::Target& i_target, + const uint8_t i_side, + bool i_is_MasterPMC, + const fapi::Target& i_dcm_target); + +fapi::ReturnCode +p8_pmc_poll_spivid_halt( const fapi::Target& i_target, + const uint8_t i_side); + +fapi::ReturnCode +p8_pmc_poll_o2p_halt( const fapi::Target& i_target, + const uint8_t i_side); + // ---------------------------------------------------------------------- /** * pmc_config_spivid_settings @@ -200,41 +218,39 @@ pmc_config_spivid_settings(const Target& l_pTarget) * @retval ERROR defined in xml */ fapi::ReturnCode -pmc_reset_function( const fapi::Target& i_target1 , - const fapi::Target& i_target2, +pmc_reset_function( const fapi::Target& i_target1 , + const fapi::Target& i_target2, uint32_t i_mode) { fapi::ReturnCode rc; ecmdDataBufferBase data(64); + ecmdDataBufferBase pmcstatus(64); + ecmdDataBufferBase porr(64); ecmdDataBufferBase pmcmode_master(64); ecmdDataBufferBase pmcmode_slave(64); - // ecmdDataBufferBase mask(64); - uint32_t e_rc = 0; - uint32_t count = 0 ; - bool is_stopped = false ; - bool is_spivid_stopped = false ; - bool is_not_ongoing = false ; - // bool fw_pstate_mode = false ; - bool is_pstate_error_stopped = false ; - bool is_intchp_error_stopped= false ; + uint32_t e_rc = 0; +// uint32_t count = 0 ; +// bool is_stopped = false ; +// bool is_pstate_error_stopped = false ; +// bool is_spivid_stopped = false ; +// bool is_intchp_error_stopped= false ; bool master_enable_pstate_voltage_changes = false ; bool master_is_MasterPMC= false ; - bool master_enable_fw_pstate_mode= false ; +// bool master_enable_fw_pstate_mode= false ; bool master_is_enable_interchip_interface= false ; - bool slave_enable_pstate_voltage_changes = false ; +// bool slave_enable_pstate_voltage_changes = false ; bool slave_is_MasterPMC= false ; - bool slave_enable_fw_pstate_mode= false ; +// bool slave_enable_fw_pstate_mode= false ; bool slave_is_enable_interchip_interface= false ; fapi::Target master_target; fapi::Target slave_target; uint8_t attr_pm_spivid_port_enable1 = 0; -// uint8_t attr_pm_spivid_port_enable2 = 0; uint8_t attr_dcm_installed_1 = 0; uint8_t attr_dcm_installed_2 = 0; uint64_t any_error = 0; @@ -263,8 +279,12 @@ pmc_reset_function( const fapi::Target& i_target1 , // if not NULL, exit with config error if (i_target2.getType() != TARGET_TYPE_NONE ) { - FAPI_ERR ("config error : target2 is not null for target1 dcm not installed case"); - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_DCM_INSTALL_ERROR); + FAPI_ERR ("Config error : target2 is not null for target1 SCM case"); + const fapi::Target& MASTER_TARGET = i_target1; + const fapi::Target& SLAVE_TARGET = i_target2; + const uint8_t & DCM_INSTALLED_1 = attr_dcm_installed_1; + const uint8_t & DCM_INSTALLED_2 = attr_dcm_installed_2; + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_SCM_INSTALL_ERROR); break; } } @@ -292,7 +312,14 @@ pmc_reset_function( const fapi::Target& i_target1 , if (attr_dcm_installed_2 != 1) { - FAPI_ERR ("config error: DCM_INSTALLED target2 does not match target1"); + FAPI_ERR ("Config error: DCM_INSTALLED target2 does not match target1\n" \ + " target1: %08x attr:%02x, target2:%08x attr:%02x", + i_target1.getType(), attr_dcm_installed_1, + i_target2.getType(), attr_dcm_installed_2); + const fapi::Target& MASTER_TARGET = i_target1; + const fapi::Target& SLAVE_TARGET = i_target2; + const uint8_t & DCM_INSTALLED_1 = attr_dcm_installed_1; + const uint8_t & DCM_INSTALLED_2 = attr_dcm_installed_2; FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_DCM_INSTALL_ERROR); break; } @@ -381,7 +408,7 @@ pmc_reset_function( const fapi::Target& i_target1 , if (any_error) { - FAPI_DBG(" PMC_FIR has error(s) active. Continuing though 0x%16llX ", data.getDoubleWord(0)); + FAPI_INF(" PMC_FIR has error(s) active. Continuing though 0x%16llX ", data.getDoubleWord(0)); } e_rc = data.flushTo0(); @@ -535,7 +562,6 @@ pmc_reset_function( const fapi::Target& i_target1 , } } - //////////////////////////////////////////////////////////////////////////// // Issue halt to Pstate Master FSM on master_chiptarget // Issue halt to Pstate Master FSM on slave_chiptarget @@ -576,11 +602,12 @@ pmc_reset_function( const fapi::Target& i_target1 , break; } - master_is_MasterPMC = data.isBitSet(6) & data.isBitSet(7) ; - master_enable_pstate_voltage_changes = data.isBitSet(3) ; - master_enable_fw_pstate_mode = data.isBitSet(2) ; - master_is_enable_interchip_interface = data.isBitSet(6) ; + master_is_MasterPMC = pmcmode_master.isBitSet(6) && pmcmode_master.isBitSet(7) ; + master_enable_pstate_voltage_changes = pmcmode_master.isBitSet(3) ; +// master_enable_fw_pstate_mode = pmcmode_master.isBitSet(2) ; + master_is_enable_interchip_interface = pmcmode_master.isBitSet(6) ; + // Resave the updated PMC Mode reg pmcmode_master = data; // ****************************************************** @@ -590,14 +617,13 @@ pmc_reset_function( const fapi::Target& i_target1 , if (dcm) { FAPI_INF("Halt Pstates and Idles on Slave"); - rc = fapiGetScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + rc = fapiGetScom(slave_target, PMC_MODE_REG_0x00062000 , pmcmode_master ); if (rc) { FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); break; } - e_rc |= data.setBit(05); e_rc |= data.setBit(14); if (e_rc) @@ -614,51 +640,14 @@ pmc_reset_function( const fapi::Target& i_target1 , break; } - slave_is_MasterPMC = data.isBitSet(6) & data.isBitSet(7) ; - slave_enable_pstate_voltage_changes = data.isBitSet(3) ; - slave_enable_fw_pstate_mode = data.isBitSet(2) ; - slave_is_enable_interchip_interface = data.isBitSet(6) ; + slave_is_MasterPMC = pmcmode_slave.isBitSet(6) && pmcmode_slave.isBitSet(7) ; +// slave_enable_pstate_voltage_changes = pmcmode_slave.isBitSet(3) ; +// slave_enable_fw_pstate_mode = pmcmode_slave.isBitSet(2) ; + slave_is_enable_interchip_interface = pmcmode_slave.isBitSet(6) ; + // Resave the updated PMC Mode reg pmcmode_slave = data; - // Check with Greg about return - // TODO : if ATTR_DCM_INSTALLED = 1 chip level attribute - /* - if (master_is_MasterPMC == 0) - { - FAPI_ERR(" MasterPMC bit of Master PMC is not set"); - const uint64_t& MASTERPMCMODE = pmcmode_master.getDoubleWord(0); - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMC_MASTER_CONFIG_ERROR); - break; - } - - if (slave_is_MasterPMC == 1) - { - FAPI_ERR(" MasterPMC bit of Slave PMC is set"); - const uint64_t& SLAVEPMCMODE = pmcmode_slave.getDoubleWord(0); - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMC_SLAVE_CONFIG_ERROR); - break; - } - - - if ((master_is_enable_interchip_interface ==1) && (slave_is_enable_interchip_interface == 0)) - { - FAPI_ERR (" Configuration Error : Master is enabled with interchip interface but slave is not "); - const uint64_t& MASTERPMCMODE = pmcmode_master.getDoubleWord(0); - const uint64_t& SLAVEPMCMODE = pmcmode_slave.getDoubleWord(0); - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMC_INTERCHIP_CONFIG_ERROR); - break; - } - - if ( (master_enable_fw_pstate_mode == 1) && (slave_enable_fw_pstate_mode == 0)) - { - FAPI_ERR (" Configuration Error : Master is enabled with FW pstate mode but slave is not "); - const uint64_t& MASTERPMCMODE = pmcmode_master.getDoubleWord(0); - const uint64_t& SLAVEPMCMODE = pmcmode_slave.getDoubleWord(0); - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMC_INTERCHIP_CONFIG_ERROR); - break; - } - */ } @@ -698,235 +687,31 @@ pmc_reset_function( const fapi::Target& i_target1 , FAPI_INF("Halt interchip interface on Master"); if (master_is_enable_interchip_interface == 1) { - - rc = fapiGetScom(master_target, PMC_INTCHP_COMMAND_REG_0x00062014 , data ); + rc = p8_pmc_poll_interchip_halt(master_target, MASTER_SIDE, master_is_MasterPMC, slave_target ); if (rc) { - FAPI_ERR("fapiGetScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); - break; - } - - e_rc = data.setBit(01); - if (e_rc) - { - FAPI_ERR("ecmdDataBufferBase error setting up PMC_INTCHP_COMMAND_REG_0x00062014 on Master during reset"); - rc.setEcmdError(e_rc); + FAPI_ERR("p8_pmc_poll_interchip_halt detected a failure."); break; } - - - rc = fapiPutScom(master_target, PMC_INTCHP_COMMAND_REG_0x00062014 , data ); - if (rc) - { - FAPI_ERR("fapiPutScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); - break; - } - - // Poll for interchip interface to stop - for (count = 0 , is_stopped = 0 ; count <= INTERCHIP_HALT_POLL_COUNT && is_stopped == 0; count++) - { - // Interchip_Wait1: Read PMC_STATUS_REG - // is_pstate_error_stopped = pstate_processing_is_suspended || - // gpsa_bdcst_error || - // gpsa_vchg_error || - // gpsa_timeout_error || - // pstate_interchip_error - - rc = fapiGetScom(master_target, PMC_STATUS_REG_0x00062009 , data ); - if (rc) - { - FAPI_ERR("fapiGetScom(PMC_STATUS_REG_0x00062009) failed."); - break; - } - - is_pstate_error_stopped = data.isBitSet(0) | - data.isBitSet(1) | - data.isBitSet(5) | - data.isBitSet(6) | - data.isBitSet(11); - - // Interchip_Wait2: Read PMC_INTCHP_STATUS_REG - // is_intchp_error_stopped = interchip_ecc_ue_err || - // interchip_fsm_err || - // (is_MasterPMC && interchip_slave_error_code != 0) is_MasterPMC - rc = fapiGetScom(master_target, PMC_INTCHP_STATUS_REG_0x00062013 , data ); - if (rc) - { - FAPI_ERR("fapiGetScom(PMC_INTCHP_STATUS_REG_0x00062013) failed."); - break; - } - is_intchp_error_stopped = data.isBitSet(1) | - data.isBitSet(7) | - (~( data.isBitClear(16,4) && master_is_MasterPMC)) ; - - // is_stopped = (interchip_ga_ongoing == 0) || - // is_pstate_error_stopped || - // is_intchp_error_stopped ; - is_stopped = data.isBitClear(0) || is_pstate_error_stopped || is_intchp_error_stopped; - FAPI_DBG("polling interchip ongoing : ... "); - - // If !is_stopped Then -->Interchip_Wait1 (Wait limit is parm TD_Interchip_HaltWait_max=260) - - } // end_for - // Error check - if (!rc.ok()) - { - break; - } - - if (count > INTERCHIP_HALT_POLL_COUNT) - { - FAPI_ERR("Timed out in polling interchip ongoing : Reset_suspicious ... "); - // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); - // break; - } - - // InterchipIf: PMC_MODE_REG.interchip_halt_if<-1 interchip_halt_if - - rc = fapiGetScom(master_target, PMC_MODE_REG_0x00062000 , data ); - if (rc) - { - FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); - break; - } - - e_rc = data.setBit(15); - if (e_rc) - { - FAPI_ERR("ecmdDataBufferBase error setting up PMC_MODE_REG_0x00062000 on Master during reset"); - rc.setEcmdError(e_rc); - break; - } - - rc = fapiPutScom(master_target, PMC_MODE_REG_0x00062000 , data ); - if (rc) { - FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); break; - } - - } // end if + } // ****************************************************** // Slave // ****************************************************** FAPI_INF("Halt interchip interface on Slave"); - if (slave_is_enable_interchip_interface ==1) { - - rc = fapiGetScom(slave_target, PMC_INTCHP_COMMAND_REG_0x00062014 , data ); + rc = p8_pmc_poll_interchip_halt(slave_target, SLAVE_SIDE, slave_is_MasterPMC, master_target); if (rc) { - FAPI_ERR("fapiGetScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); - break; - } - - e_rc = data.setBit(01); - if (e_rc) - { - FAPI_ERR("ecmdDataBufferBase error setting up PMC_INTCHP_COMMAND_REG_0x00062014 on Slave during reset"); - rc.setEcmdError(e_rc); - break; - } - - rc = fapiPutScom(slave_target, PMC_INTCHP_COMMAND_REG_0x00062014 , data ); - if (rc) - { - FAPI_ERR("fapiPutScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); - break; - } - - // Poll for interchip interface to stop - for (count = 0 , is_stopped = 0 ; count <= INTERCHIP_HALT_POLL_COUNT && is_stopped == 0; count++) - { - // Interchip_Wait1: Read PMC_STATUS_REG - // is_pstate_error_stopped = pstate_processing_is_suspended || - // gpsa_bdcst_error || - // gpsa_vchg_error || - // gpsa_timeout_error || - // pstate_interchip_error - - rc = fapiGetScom(slave_target, PMC_STATUS_REG_0x00062009 , data ); - if (rc) - { - FAPI_ERR("fapiGetScom(PMC_STATUS_REG_0x00062009) failed."); - break; - } - - is_pstate_error_stopped = data.isBitSet(0) | - data.isBitSet(1) | - data.isBitSet(5) | - data.isBitSet(6) | - data.isBitSet(11) ; - - - // Interchip_Wait2: Read PMC_INTCHP_STATUS_REG - // is_intchp_error_stopped = interchip_ecc_ue_err || - // interchip_fsm_err || - // (is_MasterPMC && interchip_slave_error_code != 0) is_MasterPMC - - rc = fapiGetScom(slave_target, PMC_INTCHP_STATUS_REG_0x00062013 , data ); - if (rc) - { - FAPI_ERR("fapiGetScom(PMC_INTCHP_STATUS_REG_0x00062013) failed."); - break; - } - is_intchp_error_stopped = data.isBitSet(1) | - data.isBitSet(7) | - (~( data.isBitClear(16,4) && slave_is_MasterPMC)); - - // is_stopped = (interchip_ga_ongoing == 0) || - // is_pstate_error_stopped || - // is_intchp_error_stopped ; - is_stopped = data.isBitClear(0) || - is_pstate_error_stopped || - is_intchp_error_stopped; - FAPI_DBG("polling interchip ongoing : ... "); - - } // end_for - - // Error check - if (!rc.ok()) - { - break; - } - - // Timeout check - if (count > INTERCHIP_HALT_POLL_COUNT) - { - FAPI_ERR("Timed out in polling interchip ongoing : Reset_suspicious ... "); - // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); - // break; - } - - - // InterchipIf: PMC_MODE_REG.interchip_halt_if<-1 interchip_halt_if - rc = fapiGetScom(slave_target, PMC_MODE_REG_0x00062000 , data ); - if (rc) - { - FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); - break; - } - - e_rc = data.setBit(15); - if (e_rc) - { - FAPI_ERR("ecmdDataBufferBase error setting up PMC_MODE_REG_0x00062000 on Slave during reset"); - rc.setEcmdError(e_rc); - break; - } - - rc = fapiPutScom(slave_target, PMC_MODE_REG_0x00062000 , data ); - if (rc) - { - FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); + FAPI_ERR("p8_pmc_poll_interchip_halt detected a failure."); break; } - - } // end if + } } // end dcm //////////////////////////////////////////////////////////////////////////// - // If voltage changes are enable, issue halt to SPIVID controller on FSM on master_chiptarget + // If voltage changes are enabled, issue halt to SPIVID controller on FSM on master_chiptarget // Poll for SPIVID FSM to halt on master_chiptarget // If poll not complete, flag "reset_suspicious" and save the poll point; continue // @@ -934,70 +719,20 @@ pmc_reset_function( const fapi::Target& i_target1 , // HaltSpivid: PMC_SPIV_COMMAND_REG.spivid_halt_fsm<-1 // Spivid_HaltWait: Read PMC_SPIV_STATUS_REG // is_spivid_error = spivid_retry_timeout || spivid_fsm_err - // if spivid_ongoing && !is_spivid_error Then -->Spivid_HaltWait (Wait limit is parm TD_Spivid_HaltWait_max=100) + // if spivid_ongoing && !is_spivid_error Then -->Spivid_HaltWait // else -->MPS_HaltWait //////////////////////////////////////////////////////////////////////////// if (master_enable_pstate_voltage_changes==1) { FAPI_INF("Halt SPIVID controller on Master"); - - // HaltSpivid: PMC_SPIV_COMMAND_REG.spivid_halt_fsm<-1 - rc = fapiGetScom(master_target, PMC_SPIV_COMMAND_REG_0x00062047 , data ); - if (rc) - { - FAPI_ERR("fapiGetScom(PMC_SPIV_COMMAND_REG_0x00062047) failed."); - break; - } - - e_rc = data.setBit(0); - if (e_rc) - { - FAPI_ERR("ecmdDataBufferBase error setting up PMC_SPIV_COMMAND_REG_0x00062047 on Master during reset"); - rc.setEcmdError(e_rc); - break; - } - - rc = fapiPutScom(master_target, PMC_SPIV_COMMAND_REG_0x00062047 , data ); + rc = p8_pmc_poll_spivid_halt(master_target, MASTER_SIDE); if (rc) { - FAPI_ERR("fapiPutScom(PMC_SPIV_COMMAND_REG_0x00062047) failed."); + FAPI_ERR("p8_pmc_poll_spivid_halt detected a failure."); break; } - - // Spivid_HaltWait: Read PMC_SPIV_STATUS_REG - for (count = 0 , is_spivid_stopped=0; count <= VOLTAGE_CHANGE_POLL_COUNT && is_spivid_stopped==0 ; count++) - { - rc = fapiGetScom(master_target, PMC_SPIV_STATUS_REG_0x00062046 , data ); - if (rc) - { - FAPI_ERR("fapiGetScom(PMC_SPIV_STATUS_REG_0x00062046) failed."); - break; - } - is_spivid_stopped = data.isBitClear(0) | - data.isBitSet(1) | - data.isBitSet(2) | - data.isBitSet(3) | - data.isBitSet(4) ; - FAPI_DBG("Polling spivid ongoing on Masster ... "); - } // end for - - // Error check - if (!rc.ok()) - { - break; - } - - // Timeout check - if (count > VOLTAGE_CHANGE_POLL_COUNT) - { - FAPI_ERR("Timed out in polling SPIVID ongoing : Reset_suspicious ... "); - // \todo - // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); - // break; - } - } // end if - + } //////////////////////////////////////////////////////////////////////////// // Poll for Pstate Master FSM being stopped on master_chiptarget @@ -1020,46 +755,12 @@ pmc_reset_function( const fapi::Target& i_target1 , FAPI_INF("Check for Pstate FSM being stopped on Master"); - // ****************************************************** - // Master - // ****************************************************** - for (count = 0, is_stopped = 0; count <= PSTATE_HALT_POLL_COUNT && is_stopped == 0 ; count++) - { - rc = fapiGetScom(master_target, PMC_STATUS_REG_0x00062009 , data ); - if (rc) - { - FAPI_ERR("fapiGetScom(PMC_STATUS_REG_0x00062009) failed."); - break; - } - - - if (master_enable_fw_pstate_mode) - { - is_not_ongoing = (master_enable_pstate_voltage_changes == 0 || - data.isBitClear(8) ) && - data.isBitClear(9); - } - else - { - is_not_ongoing = (master_enable_pstate_voltage_changes==0 || - data.isBitClear(7) ); - } - - is_stopped = ( data.isBitSet(11) | - data.isBitSet(12) | - data.isBitSet(1) | - data.isBitSet(5) | - data.isBitSet(6)) | - is_not_ongoing ; - FAPI_DBG("Polling voltage change ongoing on Master ... "); - } // end for - - if (count > PSTATE_HALT_POLL_COUNT ) - { - FAPI_ERR("Timed out in polling voltage change ongoing : Reset_suspicious ... "); - // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); - // break; - } + rc = p8_pmc_poll_pstate_halt(master_target, MASTER_SIDE); + if (rc) + { + FAPI_ERR("p8_pmc_poll_pstate_halt error detected for PMC Master"); + break; + } // ****************************************************** // Slave @@ -1068,50 +769,13 @@ pmc_reset_function( const fapi::Target& i_target1 , { FAPI_INF("Check for Pstate FSM being stopped on Slave"); - for (count = 0 , is_stopped = 0 ; count <= PSTATE_HALT_POLL_COUNT && is_stopped == 0 ; count++) - { - - rc = fapiGetScom(slave_target, PMC_STATUS_REG_0x00062009 , data ); - if (rc) - { - FAPI_ERR("fapiGetScom(PMC_STATUS_REG_0x00062009) failed."); - break; - } - - if (slave_enable_fw_pstate_mode) - { - is_not_ongoing = ( slave_enable_pstate_voltage_changes == 0 || - data.isBitClear(8) ) && - data.isBitClear(9); - } - else - { - is_not_ongoing = ( slave_enable_pstate_voltage_changes == 0 || - data.isBitClear(7) ); - } - - is_stopped = ( data.isBitSet(11) | - data.isBitSet(12) | - data.isBitSet(1) | - data.isBitSet(5) | - data.isBitSet(6)) | - is_not_ongoing ; - FAPI_DBG("polling voltage change ongoing on Slave ..."); - } // end for - - // Error check - if (!rc.ok()) + rc = p8_pmc_poll_pstate_halt(master_target, SLAVE_SIDE); + if (rc) { + FAPI_ERR("p8_pmc_poll_pstate_halt error detected for PMC Slave"); break; } - // Timeout check - if (count > PSTATE_HALT_POLL_COUNT ) - { - FAPI_ERR("Timed out in polling voltage change ongoing : Reset_suspicious ... "); - // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); - // break; - } } // dcm @@ -1146,85 +810,14 @@ pmc_reset_function( const fapi::Target& i_target1 , // ****************************************************** FAPI_INF("Poll for O2P bridge being complete on Master"); - rc = fapiGetScom(master_target, PMC_O2S_COMMAND_REG_0x00062057 , data ); - if (rc) - { - FAPI_ERR("fapiGetScom(PMC_O2S_COMMAND_REG__0x00062057) failed."); - break; - } - e_rc = data.setBit(00); if(e_rc){rc.setEcmdError(e_rc); break; } - - rc = fapiPutScom(master_target, PMC_O2S_COMMAND_REG_0x00062057 , data ); + rc = p8_pmc_poll_o2p_halt(master_target, MASTER_SIDE); if (rc) { - FAPI_ERR("fapiPutScom(PMC_O2S_COMMAND_REG__0x00062057) failed."); - break; - } - - // Poll for O2S to be stopped - for (count = 0 , is_stopped = 0 ; count <= O2S_POLL_COUNT && is_stopped == 0 ; count++) - { - rc = fapiGetScom(master_target, PMC_O2S_STATUS_REG_0x00062056 , data ); - if (rc) - { - FAPI_ERR("fapiGetScom(PMC_O2S_STATUS_REG__0x00062056) failed."); - break; - } - - is_stopped = ( data.isBitClear(0) | - data.isBitSet(4) | - data.isBitSet(5) | - data.isBitSet(7)); - FAPI_DBG("Polling O2S ongoing . : .. "); - } - - // Error check - if (!rc.ok()) - { - break; - } - - // Timeout check - if (count > O2S_POLL_COUNT) - { - FAPI_ERR("Timed out in polling O2S ongoing . : Reset_suspicious .. "); - // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); - // break; - } - - // Poll for O2P to be stopped - for (count = 0 , is_stopped = 0 ; count <= O2P_POLL_COUNT && is_stopped == 0 ; count++) - { - rc = fapiGetScom(master_target, PMC_O2P_CTRL_STATUS_REG_0x00062061 , data ); - if (rc) - { - FAPI_ERR("fapiGetScom(PMC_O2P_STATUS_REG__0x00062061) failed."); - break; - } - - is_stopped = ( data.isBitClear(0) | - data.isBitSet(4) | - data.isBitSet(5) | - data.isBitSet(6) | - data.isBitSet(7)); - FAPI_DBG("Polling O2P ongoing . : .. "); - } - - // Error check - if (!rc.ok()) - { + FAPI_ERR("p8_pmc_poll_o2p_halt error detected for PMC Master"); break; } - // Timeout check - if (count > O2P_POLL_COUNT) - { - FAPI_ERR("Timed out in polling O2P ongoing . : Reset_suspicious .. "); - // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); - // break; - } - // ****************************************************** // Slave // ****************************************************** @@ -1233,45 +826,20 @@ pmc_reset_function( const fapi::Target& i_target1 , { FAPI_INF("Poll for O2P bridge being complete on Slave"); - for (count = 0 , is_stopped = 0 ; count <= O2P_POLL_COUNT && is_stopped == 0 ; count++) - { - rc = fapiGetScom(slave_target, PMC_O2P_CTRL_STATUS_REG_0x00062061 , data ); - if (rc) - { - FAPI_ERR("fapiGetScom(PMC_O2P_STATUS_REG__0x00062061) failed."); - break; - } - - is_stopped = ( data.isBitClear(0) | - data.isBitSet(4) | - data.isBitSet(5) | - data.isBitSet(6) | - data.isBitSet(7)); - FAPI_DBG("Polling O2P ongoing . : .. "); - } - - // Error check - if (!rc.ok()) + rc = p8_pmc_poll_o2p_halt(slave_target, SLAVE_SIDE); + if (rc) { + FAPI_ERR("p8_pmc_poll_o2p_halt error detected for PMC Slave"); break; } - - // Timeout check - if (count > O2P_POLL_COUNT) - { - FAPI_ERR("Timed out in polling O2P ongoing . : Reset_suspicious .. "); - // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); - // break; - } - } // dcm + } /////////////////////////////////////////////////////////////////////////////////////////////////////////// - //GREG: Check with Greg whether this is needed for both master and slave? // 8) Poll for Idle FSM being quiesced (timeout: 500ms to cover the case of having all 4 types of Deep Idle // transitions in flight) // Note: Previously issued special wake-ups could have triggered PORE activity through the Idle FSM (and - // the related pending queues). if poll timeout, mark the error point + // the related pending queues). if poll timeout, FAIL THE OCC RESET AS SLW RECOVER IS COMPROMISED // // Note on Idle/PORE-SLW state (prior to reset) // Given that special wake-up occurred before this point, any errors that resulted from that special wake-up @@ -1282,83 +850,39 @@ pmc_reset_function( const fapi::Target& i_target1 , // ****************************************************** // Master // ****************************************************** - - FAPI_INF("Poll for Idle FSM being quiesced on Master"); - for (count = 0 , is_stopped = 0 ; count <= PORE_REQ_POLL_COUNT && is_stopped == 0 ; count++) - { - rc = fapiGetScom(master_target, PMC_PORE_REQ_REG0_0x0006208E , data ); - if (rc) - { - FAPI_ERR("fapiGetScom(PMC_O2P_STATUS_REG__0x00062061) failed."); - break; - } - is_stopped = (data.isBitClear(20)) ; - FAPI_DBG("Polling pore_busy bit ..."); - } + FAPI_INF("Poll for Idle FSM being quiesced on Master"); - // Error check - if (!rc.ok()) + rc = p8_pmc_poll_idle_halt(master_target, MASTER_SIDE); + if (rc) { + FAPI_ERR("p8_pmc_poll_idle_halt error detected for PMC Master"); break; } - // Timeout check - if (count > PORE_REQ_POLL_COUNT) - { - FAPI_ERR("Timed out in polling pore_busy bit . : Reset_suspicious .. "); - // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); - // break; - } // ****************************************************** // Slave // ****************************************************** - + if (dcm) { FAPI_INF("Poll for Idle FSM being quiesced on Slave"); - for (count = 0 , is_stopped = 0 ; count <= PORE_REQ_POLL_COUNT && is_stopped == 0 ; count++) - { - rc = fapiGetScom(slave_target, PMC_PORE_REQ_REG0_0x0006208E , data ); - if (rc) - { - FAPI_ERR("fapiGetScom(PMC_O2P_STATUS_REG__0x00062061) failed."); - break; - } - - is_stopped = (data.isBitClear(20)) ; - FAPI_DBG("Polling pore_busy bit ..."); - } - - // Error check - if (!rc.ok()) + rc = p8_pmc_poll_idle_halt(slave_target, SLAVE_SIDE); + if (rc) { + FAPI_ERR("p8_pmc_poll_idle_halt error detected for PMC Slave"); break; } - - // Timeout check - if (count > PORE_REQ_POLL_COUNT) - { - FAPI_ERR("Timed out in polling pore_busy bit . : Reset_suspicious .. "); - // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); - // break; - } } /////////////////////////////////////////////////////////////////////////////// - // GREG: // Issue interchip interface reset (if enabled) on master_chiptarget // PMC_INTCHP_COMMAND_REG.reset (0) = 1 // PMC_INTCHP_COMMAND_REG.reset (0) = 0 // Issue interchip interface reset (if enabled) on slave_chiptarget // PMC_INTCHP_COMMAND_REG.reset (0) = 1 // PMC_INTCHP_COMMAND_REG.reset (0) = 0 - - // SCOTT: - // 9. if enable_interchip_interface==1 and parm InterchipResetIf_AfterHalt - // InterchipResetIf_On: PMC_INTCHP_COMMAND_REG.interchip_reset_if<-1 - // InterchipResetIf_Off: PMC_INTCHP_COMMAND_REG.interchip_reset_if<-0 /////////////////////////////////////////////////////////////////////////////// // ****************************************************** @@ -1475,7 +999,7 @@ pmc_reset_function( const fapi::Target& i_target1 , // Master // ****************************************************** // RESET_ALL_PMC_REGISTERS - + if (i_mode == PM_RESET) { FAPI_INF("Hard reset detected"); @@ -1535,31 +1059,6 @@ pmc_reset_function( const fapi::Target& i_target1 , FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); break; } - - // \todo remove in deference to init path - // Restored only for slave - // SAFE_MODE_WITHOUT_SPIVID - rc = fapiGetScom(slave_target, PMC_MODE_REG_0x00062000 , data ); - if (rc) - { - FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); - break; - } - - e_rc = data.setBit(13); - if (e_rc) - { - FAPI_ERR("ecmdDataBufferBase error for PMC_MODE_REG_0x00062000 on Slave reset"); - rc.setEcmdError(e_rc); - break; - } - - rc = fapiPutScom(slave_target, PMC_MODE_REG_0x00062000 , data ); - if (rc) - { - FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); - break; - } } } else @@ -1577,12 +1076,13 @@ pmc_reset_function( const fapi::Target& i_target1 , /** * pmc_init_function * - * @param[in] i_target1 Primary Chip target: Murano - chip0; Venice - chip - + * @param[in] i_target Primary Chip target: Murano - chip0; Venice - chip + * @param[in] i_dcm Boolean to run in DCM or SCM mode + * * @retval ECMD_SUCCESS * @retval ERROR defined in xml */ -fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) +fapi::ReturnCode pmc_init_function(const fapi::Target& i_target, bool i_dcm ) { fapi::ReturnCode rc; uint32_t e_rc; @@ -1638,7 +1138,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) GETATTR_DEFAULT(rc, ATTR_PM_SPIVID_FRAME_SIZE, "ATTR_PM_SPIVID_FRAME_SIZE", - &i_target1, + &i_target, attr_pm_spivid_frame_size, default_spivid_frame_size ); @@ -1646,7 +1146,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) GETATTR_DEFAULT(rc, ATTR_PM_SPIVID_IN_DELAY_FRAME1, "ATTR_PM_SPIVID_IN_DELAY_FRAME1", - &i_target1, + &i_target, attr_pm_spivid_in_delay_frame1, default_spivid_in_delay_frame1 ); @@ -1654,7 +1154,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) GETATTR_DEFAULT(rc, ATTR_PM_SPIVID_IN_DELAY_FRAME1, "ATTR_PM_SPIVID_IN_DELAY_FRAME1", - &i_target1, + &i_target, attr_pm_spivid_in_delay_frame2, default_spivid_in_delay_frame2 ); @@ -1662,7 +1162,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) GETATTR_DEFAULT(rc, ATTR_PM_SPIVID_CLOCK_POLARITY, "ATTR_PM_SPIVID_CLOCK_POLARITY", - &i_target1, + &i_target, attr_pm_spivid_clock_polarity, default_spivid_clock_polarity ); @@ -1670,7 +1170,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) GETATTR_DEFAULT(rc, ATTR_PM_SPIVID_CLOCK_PHASE, "ATTR_PM_SPIVID_CLOCK_PHASE", - &i_target1, + &i_target, attr_pm_spivid_clock_phase, default_spivid_clock_phase ); @@ -1678,7 +1178,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) GETATTR_DEFAULT(rc, ATTR_PM_SPIVID_CRC_GEN_ENABLE, "ATTR_PM_SPIVID_CRC_GEN_ENABLE", - &i_target1, + &i_target, attr_pm_spivid_crc_gen_enable, default_spivid_crc_gen_enable ); @@ -1686,7 +1186,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) GETATTR_DEFAULT(rc, ATTR_PM_SPIVID_CRC_CHECK_ENABLE, "ATTR_PM_SPIVID_CRC_CHECK_ENABLE", - &i_target1, + &i_target, attr_pm_spivid_crc_check_enable, default_spivid_crc_check_enable ); @@ -1694,7 +1194,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) GETATTR_DEFAULT(rc, ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE, "ATTR_PM_SPIVID_CRC_CHECK_ENABLE", - &i_target1, + &i_target, attr_pm_spivid_majority_vote_enable, default_spivid_majority_vote_enable ); @@ -1702,7 +1202,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) GETATTR_DEFAULT(rc, ATTR_PM_SPIVID_MAX_RETRIES, "ATTR_PM_SPIVID_MAX_RETRIES", - &i_target1, + &i_target, attr_pm_spivid_max_retries, default_spivid_max_retries ); @@ -1710,7 +1210,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) GETATTR_DEFAULT(rc, ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES, "ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES", - &i_target1, + &i_target, attr_pm_spivid_crc_polynomial_enables, default_spivid_crc_polynomial_enables ); @@ -1718,7 +1218,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) GETATTR_DEFAULT(rc, ATTR_PM_SPIVID_PORT_ENABLE, "ATTR_PM_SPIVID_PORT_ENABLE", - &i_target1, + &i_target, attr_pm_spivid_port_enable, default_spivid_port_enable ); @@ -1726,56 +1226,54 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) GETATTR( rc, ATTR_PM_SPIVID_CLOCK_DIVIDER, "ATTR_PM_SPIVID_CLOCK_DIVIDER", - &i_target1, + &i_target, attr_pm_spivid_clock_divider); //---------------------------------------------------------- GETATTR( rc, ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, "ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE", - &i_target1, + &i_target, attr_pm_spivid_interframe_delay_write_status_value); //---------------------------------------------------------- GETATTR( rc, ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, "ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE", - &i_target1, + &i_target, attr_pm_spivid_inter_retry_delay_value); - FAPI_INF("PMC initialization..."); - - uint8_t o2s_frame_size = attr_pm_spivid_frame_size; - uint8_t o2s_in_delay1 = attr_pm_spivid_in_delay_frame1; - uint8_t o2s_in_delay2 = attr_pm_spivid_in_delay_frame2; - uint8_t o2s_clk_pol = attr_pm_spivid_clock_polarity; - uint8_t o2s_clk_pha = attr_pm_spivid_clock_phase; - uint8_t o2s_port_enable = attr_pm_spivid_port_enable; - uint32_t o2s_inter_frame_delay = attr_pm_spivid_interframe_delay_write_status_value; - uint8_t o2s_crc_gen_en = attr_pm_spivid_crc_gen_enable; - uint8_t o2s_crc_check_en = attr_pm_spivid_crc_check_enable; - uint8_t o2s_majority_vote_en = attr_pm_spivid_majority_vote_enable; - uint8_t o2s_max_retries = attr_pm_spivid_max_retries; - uint8_t o2s_crc_polynomial_enables = attr_pm_spivid_crc_polynomial_enables; - uint16_t o2s_clk_divider = attr_pm_spivid_clock_divider; + FAPI_INF("PMC initialization as %s ...", i_dcm ? "DCM" : "SCM"); + + uint8_t o2s_frame_size = attr_pm_spivid_frame_size; + uint8_t o2s_in_delay1 = attr_pm_spivid_in_delay_frame1; + uint8_t o2s_in_delay2 = attr_pm_spivid_in_delay_frame2; + uint8_t o2s_clk_pol = attr_pm_spivid_clock_polarity; + uint8_t o2s_clk_pha = attr_pm_spivid_clock_phase; + uint8_t o2s_port_enable = attr_pm_spivid_port_enable; + uint32_t o2s_inter_frame_delay = attr_pm_spivid_interframe_delay_write_status_value; + uint8_t o2s_crc_gen_en = attr_pm_spivid_crc_gen_enable; + uint8_t o2s_crc_check_en = attr_pm_spivid_crc_check_enable; + uint8_t o2s_majority_vote_en = attr_pm_spivid_majority_vote_enable; + uint8_t o2s_max_retries = attr_pm_spivid_max_retries; + uint8_t o2s_crc_polynomial_enables = attr_pm_spivid_crc_polynomial_enables; + uint16_t o2s_clk_divider = attr_pm_spivid_clock_divider; //spivid_freq = attr_pm_spivid_frequency; - uint8_t o2s_in_count2 = o2s_frame_size ; - uint8_t o2s_out_count2 = 0 ; - uint8_t o2s_bridge_enable = 0x1 ; - uint8_t o2s_nr_of_frames = 2 ; - uint8_t o2s_in_count1 = 0 ; - uint8_t o2s_out_count1 = o2s_frame_size ; - uint8_t hangpulse_predivider = 1; - uint8_t gpsa_timeout_value = 100; - uint8_t one=1; - uint8_t zero=0; - uint8_t dcm=0; - uint8_t is_master=0; - uint8_t is_slave=1; - - uint8_t is_simulation = 0; - uint8_t attr_dcm_installed_1 = 0; - uint64_t any_error = 0; + uint8_t o2s_in_count2 = o2s_frame_size ; + uint8_t o2s_out_count2 = 0 ; + uint8_t o2s_bridge_enable = 0x1 ; + uint8_t o2s_nr_of_frames = 2 ; + uint8_t o2s_in_count1 = 0 ; + uint8_t o2s_out_count1 = o2s_frame_size ; + uint8_t hangpulse_predivider = 1; + uint8_t gpsa_timeout_value = 100; + uint8_t one=1; + uint8_t zero=0; + uint8_t is_master=0; + uint8_t is_slave=1; + + uint8_t is_simulation = 0; + uint64_t any_error = 0; rc = FAPI_ATTR_GET( ATTR_IS_SIMULATION, NULL, is_simulation); if (rc) @@ -1806,7 +1304,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) break; } - rc = fapiGetScom(i_target1, PMC_LFIR_0x01010840 , data ); + rc = fapiGetScom(i_target, PMC_LFIR_0x01010840 , data ); if (rc) { FAPI_ERR("fapiGetScom(PMC_LFIR_0x01010840) failed."); @@ -1828,7 +1326,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) // - set PMC_o2s_CTRL_REG0A (24b) // ****************************************************************** - rc = fapiGetScom(i_target1, PMC_O2S_CTRL_REG0A_0x00062050, data ); + rc = fapiGetScom(i_target, PMC_O2S_CTRL_REG0A_0x00062050, data ); if (rc) { FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG0A) failed."); @@ -1852,14 +1350,14 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) FAPI_INF(" o2s_in_delay1 => %d ", o2s_in_delay1); FAPI_INF(" o2s_in_count1 => %d ", o2s_in_count1); - rc = fapiPutScom(i_target1, PMC_O2S_CTRL_REG0A_0x00062050, data ); + rc = fapiPutScom(i_target, PMC_O2S_CTRL_REG0A_0x00062050, data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG0A_0x00062050) failed."); break; } - rc = fapiPutScom(i_target1, PMC_SPIV_CTRL_REG0A_0x00062040, data ); + rc = fapiPutScom(i_target, PMC_SPIV_CTRL_REG0A_0x00062040, data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_SPIV_CTRL_REG0A_0x00062040) failed."); @@ -1870,7 +1368,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) // - set PMC_O2S_CTRL_REG0B (24b) // ****************************************************************** - rc = fapiGetScom(i_target1, PMC_O2S_CTRL_REG0B_0x00062051, data ); + rc = fapiGetScom(i_target, PMC_O2S_CTRL_REG0B_0x00062051, data ); if (rc) { FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG0B) failed."); @@ -1892,14 +1390,14 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) FAPI_INF(" o2s_in_delay2 => %d ", o2s_in_delay2 ); FAPI_INF(" o2s_in_count2 => %d ", o2s_in_count2 ); - rc = fapiPutScom(i_target1, PMC_O2S_CTRL_REG0B_0x00062051, data ); + rc = fapiPutScom(i_target, PMC_O2S_CTRL_REG0B_0x00062051, data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG0B_0x00062051) failed."); break; } - rc = fapiPutScom(i_target1, PMC_SPIV_CTRL_REG0B_0x00062041, data ); + rc = fapiPutScom(i_target, PMC_SPIV_CTRL_REG0B_0x00062041, data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_SPIV_CTRL_REG0B_0x00062041) failed."); @@ -1910,7 +1408,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) // - set PMC_O2S_CTRL_REG1 // ****************************************************************** - rc = fapiGetScom(i_target1, PMC_O2S_CTRL_REG1_0x00062052, data ); + rc = fapiGetScom(i_target, PMC_O2S_CTRL_REG1_0x00062052, data ); if (rc) { FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG1) failed."); @@ -1941,14 +1439,14 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) FAPI_INF(" o2s_port_enable => %d ", o2s_port_enable); - rc = fapiPutScom(i_target1, PMC_O2S_CTRL_REG1_0x00062052, data ); + rc = fapiPutScom(i_target, PMC_O2S_CTRL_REG1_0x00062052, data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG1_0x00062052) failed."); break; } - rc = fapiPutScom(i_target1, PMC_SPIV_CTRL_REG1_0x00062042, data ); + rc = fapiPutScom(i_target, PMC_SPIV_CTRL_REG1_0x00062042, data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_SPIV_CTRL_REG1_0x00062042) failed."); @@ -1959,7 +1457,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) // - set PMC_O2S_CTRL_REG2 // ****************************************************************** - rc = fapiGetScom(i_target1, PMC_O2S_CTRL_REG2_0x00062053, data ); + rc = fapiGetScom(i_target, PMC_O2S_CTRL_REG2_0x00062053, data ); if (rc) { FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG2) failed."); @@ -1978,14 +1476,14 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) FAPI_INF(" PMC_O2S_CTRL_REG2_ / PMC_SPIV_CTRL_REG2Configuration"); FAPI_INF(" o2s_inter_frame_delay => %d ", o2s_inter_frame_delay ); - rc = fapiPutScom(i_target1, PMC_O2S_CTRL_REG2_0x00062053, data ); + rc = fapiPutScom(i_target, PMC_O2S_CTRL_REG2_0x00062053, data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG2_0x00062053) failed."); break; } - rc = fapiPutScom(i_target1, PMC_SPIV_CTRL_REG2_0x00062043, data ); + rc = fapiPutScom(i_target, PMC_SPIV_CTRL_REG2_0x00062043, data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_SPIV_CTRL_REG2_0x00062043) failed."); @@ -1996,7 +1494,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) // - set PMC_SPIV_CTRL_REG3 // ****************************************************************** - rc = fapiGetScom(i_target1, PMC_SPIV_CTRL_REG3_0x00062044, data ); + rc = fapiGetScom(i_target, PMC_SPIV_CTRL_REG3_0x00062044, data ); if (rc) { FAPI_ERR("fapiGetScom(PMC_SPIV_CTRL_REG3) failed."); @@ -2016,7 +1514,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) FAPI_INF(" spivid_inter_retry_delay_value => %d ", attr_pm_spivid_inter_retry_delay_value ); FAPI_INF(" 100ns_div_value => %d ", var_100ns_div_value); - rc = fapiPutScom(i_target1, PMC_SPIV_CTRL_REG3_0x00062044, data ); + rc = fapiPutScom(i_target, PMC_SPIV_CTRL_REG3_0x00062044, data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_SPIV_CTRL_REG3_0x00062044) failed."); @@ -2027,7 +1525,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) // - set PMC_O2S_CTRL_REG4 // ****************************************************************** - rc = fapiGetScom(i_target1, PMC_O2S_CTRL_REG4_0x00062055, data ); + rc = fapiGetScom(i_target, PMC_O2S_CTRL_REG4_0x00062055, data ); if (rc) { FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG4) failed."); @@ -2054,7 +1552,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) FAPI_INF(" o2s_crc_polynomial_enab => 0x%x ", o2s_crc_polynomial_enables ); - rc = fapiPutScom(i_target1, PMC_O2S_CTRL_REG4_0x00062055, data ); + rc = fapiPutScom(i_target, PMC_O2S_CTRL_REG4_0x00062055, data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG4_0x00062055) failed."); @@ -2065,7 +1563,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) // Program crc polynomials // ****************************************************************** - rc = fapiGetScom(i_target1, PMC_SPIV_CTRL_REG4_0x00062045, data ); + rc = fapiGetScom(i_target, PMC_SPIV_CTRL_REG4_0x00062045, data ); if (rc) { FAPI_ERR("fapiGetScom(PMC_SPIV_CTRL_REG4) failed."); @@ -2091,7 +1589,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) FAPI_INF(" spiv_max_retries => %d ", o2s_max_retries ); FAPI_INF(" spiv_crc_polynomial_enab => 0x%x ", o2s_crc_polynomial_enables ); - rc = fapiPutScom(i_target1, PMC_SPIV_CTRL_REG4_0x00062045, data ); + rc = fapiPutScom(i_target, PMC_SPIV_CTRL_REG4_0x00062045, data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_SPIV_CTRL_REG4_0x00062045) failed."); @@ -2101,7 +1599,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) // ****************************************************************** // - write PMC_PARAMETER_REG0 // ****************************************************************** - rc = fapiGetScom(i_target1, PMC_PARAMETER_REG0_0x00062005, data ); + rc = fapiGetScom(i_target, PMC_PARAMETER_REG0_0x00062005, data ); if (rc) { FAPI_ERR("fapiGetScom(PMC_PARAMETER_REG0_0x00062005) failed."); @@ -2121,7 +1619,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) FAPI_INF(" hangpulse_predivider => 0x%x ", hangpulse_predivider); FAPI_INF(" gpsa_timeout_value => 0x%x ", gpsa_timeout_value ); - rc = fapiPutScom(i_target1, PMC_PARAMETER_REG0_0x00062005, data ); + rc = fapiPutScom(i_target, PMC_PARAMETER_REG0_0x00062005, data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_PARAMETER_REG0_0x00062005) failed."); @@ -2134,7 +1632,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) // 00 --- which may be a turbo frequency. // ****************************************************************** // Added for SW207759 - rc = fapiGetScom(i_target1, PMC_RAIL_BOUNDS_0x00062003, data ); + rc = fapiGetScom(i_target, PMC_RAIL_BOUNDS_0x00062003, data ); if (rc) { FAPI_ERR("fapiGetScom(PMC_RAIL_BOUNDS_0x00062003) failed."); @@ -2154,7 +1652,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) FAPI_INF(" pmin_rail => 0x%x ", data.getByte(0)); FAPI_INF(" pmax_rail => 0x%x ", data.getByte(1)); - rc = fapiPutScom(i_target1, PMC_RAIL_BOUNDS_0x00062003, data ); + rc = fapiPutScom(i_target, PMC_RAIL_BOUNDS_0x00062003, data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_RAIL_BOUNDS_0x00062003) failed."); @@ -2164,7 +1662,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) // ****************************************************************** // - write PMC_MODE_REG // ****************************************************************** - rc = fapiGetScom(i_target1, PMC_MODE_REG_0x00062000, data ); + rc = fapiGetScom(i_target, PMC_MODE_REG_0x00062000, data ); if (rc) { FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); @@ -2185,7 +1683,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) FAPI_INF(" PMC_MODE_REG Configuration"); FAPI_INF(" SAFE_MODE_WITHOUT_SPIVID => %d ", zero); - rc = fapiPutScom(i_target1, PMC_MODE_REG_0x00062000, data ); + rc = fapiPutScom(i_target, PMC_MODE_REG_0x00062000, data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); @@ -2196,19 +1694,9 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) // REGISTER WRITES FOR DCMS // ************************************************************* - rc = FAPI_ATTR_GET(ATTR_PROC_DCM_INSTALLED, &i_target1, attr_dcm_installed_1); - if (rc) + if (i_dcm) { - FAPI_ERR("fapiGetAttribute of ATTR_DCM_INSTALLED with rc = 0x%x", (uint32_t)rc); - break; - } - FAPI_INF (" value read from the attribute ATTR_DCM_INSTALLED in init function = 0x%x", attr_dcm_installed_1 ); - - if (attr_dcm_installed_1 == 1) - { - dcm = 1; - - rc = fapiGetScom(i_target1, DEVICE_ID_REG_0x000F000F, data ); + rc = fapiGetScom(i_target, DEVICE_ID_REG_0x000F000F, data ); if (rc) { FAPI_ERR("fapiGetScom(DEVICE_ID_REG_0x000F000F) failed."); @@ -2217,14 +1705,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) is_master = data.isBitClear(39) ; is_slave = not is_master ; - } - else - { - dcm = 0 ; - } - if (dcm == 1) - { if (is_master) { FAPI_INF ("**** Setting up DCM Master ****"); @@ -2236,7 +1717,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) // **************************************************************** // - write PMC_MODE_REG // **************************************************************** - rc = fapiGetScom(i_target1, PMC_MODE_REG_0x00062000, data ); + rc = fapiGetScom(i_target, PMC_MODE_REG_0x00062000, data ); if (rc) { FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); @@ -2260,7 +1741,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) FAPI_DBG(" ENABLE_INTERCHIP_PSTATE_IN_HAPS => %d ", is_master ); FAPI_DBG(" SAFE_MODE_WITHOUT_SPIVID => %d ", is_slave ); - rc = fapiPutScom(i_target1, PMC_MODE_REG_0x00062000, data ); + rc = fapiPutScom(i_target, PMC_MODE_REG_0x00062000, data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); @@ -2272,7 +1753,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) // - set PMC_O2S_CTRL_REG1 // ****************************************************************** - rc = fapiGetScom(i_target1, PMC_O2S_CTRL_REG1_0x00062052, data ); + rc = fapiGetScom(i_target, PMC_O2S_CTRL_REG1_0x00062052, data ); if (rc) { FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG1) failed."); @@ -2297,14 +1778,14 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) } // \todo this should be looked at for removal to avoid future problems - rc = fapiPutScom(i_target1, PMC_O2S_CTRL_REG1_0x00062052, data ); + rc = fapiPutScom(i_target, PMC_O2S_CTRL_REG1_0x00062052, data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG1_0x00062052) failed."); break; } - rc = fapiPutScom(i_target1, PMC_SPIV_CTRL_REG1_0x00062042, data ); + rc = fapiPutScom(i_target, PMC_SPIV_CTRL_REG1_0x00062042, data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_SPIV_CTRL_REG1_0x00062042) failed."); @@ -2314,7 +1795,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) // ****************************************************************** // - write PMC_INTCHP_CTRL_REG1 // ****************************************************************** - rc = fapiGetScom(i_target1, PMC_INTCHP_CTRL_REG1_0x00062010, data ); + rc = fapiGetScom(i_target, PMC_INTCHP_CTRL_REG1_0x00062010, data ); if (rc) { FAPI_ERR("fapiGetScom(PMC_INTCHP_CTRL_REG1_0x00062010) failed."); @@ -2336,7 +1817,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) FAPI_DBG(" INTERCHIP_CPHA => %d ", zero ); FAPI_DBG(" INTERCHIP_CLOCK_DIVIDER => 0x%x ", interchip_clock_divider ); - rc = fapiPutScom(i_target1, PMC_INTCHP_CTRL_REG1_0x00062010, data ); + rc = fapiPutScom(i_target, PMC_INTCHP_CTRL_REG1_0x00062010, data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_INTCHP_CTRL_REG1_0x00062010) failed."); @@ -2347,7 +1828,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) // ****************************************************************** // - write PMC_INTCHP_CTRL_REG4 // ****************************************************************** - rc = fapiGetScom(i_target1, PMC_INTCHP_CTRL_REG4_0x00062012, data ); + rc = fapiGetScom(i_target, PMC_INTCHP_CTRL_REG4_0x00062012, data ); if (rc) { FAPI_ERR("fapiGetScom(PMC_INTCHP_CTRL_REG4_0x00062012) failed."); @@ -2370,7 +1851,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) FAPI_DBG(" INTERCHIP_MSG_RCV_OVERFLOW_CHECK_EN => %d ", one ); FAPI_DBG(" INTERCHIP_ECC_UE_BLOCK_EN => %d ", one ); - rc = fapiPutScom(i_target1, PMC_INTCHP_CTRL_REG4_0x00062012, data ); + rc = fapiPutScom(i_target, PMC_INTCHP_CTRL_REG4_0x00062012, data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_INTCHP_CTRL_REG4_0x00062012) failed."); @@ -2404,6 +1885,10 @@ p8_pmc_init(const fapi::Target& i_target1, const fapi::Target& i_target2, uint32 { fapi::ReturnCode rc; + uint8_t attr_dcm_installed_1 = 0; + uint8_t attr_dcm_installed_2 = 0; + bool dcm = false; + do { @@ -2435,8 +1920,71 @@ p8_pmc_init(const fapi::Target& i_target1, const fapi::Target& i_target2, uint32 // ------------------------------------------------ else if (mode == PM_INIT) { - FAPI_INF("Executing p8_pmc_init for Target %s ...", i_target1.toEcmdString()); - rc = pmc_init_function(i_target1); + + // Per SW250226, determine if initialization should be as a real DCM + // or as a garded SCM + rc = FAPI_ATTR_GET(ATTR_PROC_DCM_INSTALLED, &i_target1, attr_dcm_installed_1); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_DCM_INSTALLED with rc = 0x%x", (uint32_t)rc); + break; + } + + FAPI_INF (" ATTR_DCM_INSTALLED value in init function = 0x%x", attr_dcm_installed_1 ); + + // Default is dcm = false + if (attr_dcm_installed_1 == 0) + { + + // target2 should be NULL + // if not NULL, exit with config error + if (i_target2.getType() != TARGET_TYPE_NONE ) + { + FAPI_ERR ("Config error : target2 is not null for target1 SCM case"); + const fapi::Target& MASTER_TARGET = i_target1; + const fapi::Target& SLAVE_TARGET = i_target2; + const uint8_t & DCM_INSTALLED_1 = attr_dcm_installed_1; + const uint8_t & DCM_INSTALLED_2 = attr_dcm_installed_2; + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_SCM_INSTALL_ERROR); + break; + } + } + // Target 1 indicates a physical DCM + else + { + // Check if Target 2 indicates a real DCM. If not, gard defaults to SCM + if (i_target2.getType() != TARGET_TYPE_NONE ) + { + rc = FAPI_ATTR_GET(ATTR_PROC_DCM_INSTALLED, &i_target2, attr_dcm_installed_2); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_DCM_INSTALLED with rc = 0x%x", (uint32_t)rc); + break; + } + FAPI_INF (" ATTR_DCM_INSTALLED value in INIT function = 0x%x", attr_dcm_installed_2 ); + + if (attr_dcm_installed_2 != 1) + { + FAPI_ERR ("Config error: DCM_INSTALLED target2 does not match target1\n" \ + " target1: %08x attr:%02x, target2:%08x attr:%02x", + i_target1.getType(), attr_dcm_installed_1, + i_target2.getType(), attr_dcm_installed_2); + const fapi::Target& MASTER_TARGET = i_target1; + const fapi::Target& SLAVE_TARGET = i_target2; + const uint8_t & DCM_INSTALLED_1 = attr_dcm_installed_1; + const uint8_t & DCM_INSTALLED_2 = attr_dcm_installed_2; + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_DCM_INSTALL_ERROR); + break; + } + dcm = true; + } + } + + + FAPI_INF("Executing p8_pmc_init for as %s for Target %s ...", + dcm ? "DCM" : "SCM", + i_target1.toEcmdString()); + rc = pmc_init_function(i_target1, dcm); if (rc) { FAPI_ERR("Error from pmc_init_function for target1"); @@ -2446,7 +1994,7 @@ p8_pmc_init(const fapi::Target& i_target1, const fapi::Target& i_target2, uint32 if ( i_target2.getType() != TARGET_TYPE_NONE ) { FAPI_INF("Executing p8_pmc_init for Target %s ...", i_target2.toEcmdString()); - rc = pmc_init_function(i_target2); + rc = pmc_init_function(i_target2, dcm); if (rc) { FAPI_ERR("Error from pmc_init_function for target2"); @@ -2460,7 +2008,7 @@ p8_pmc_init(const fapi::Target& i_target1, const fapi::Target& i_target2, uint32 /// ------------------------------- else if (mode == PM_RESET) { - FAPI_INF("Hard reset detected. Calling pmc_reset_function"); + FAPI_INF("Hard reset detected. Calling pmc_reset_function"); rc = pmc_reset_function(i_target1 , i_target2, mode); if (rc) { @@ -2468,7 +2016,7 @@ p8_pmc_init(const fapi::Target& i_target1, const fapi::Target& i_target2, uint32 break; } } - + // ------------------------------- /// Reset: perform soft reset of PMC /// ------------------------------- @@ -2500,6 +2048,597 @@ p8_pmc_init(const fapi::Target& i_target1, const fapi::Target& i_target2, uint32 } // end p8_pmc_init + +// ---------------------------------------------------------------------- +/** + * p8_pmc_poll_pstate_halt + * + * @param[in] i_target Chip target + * @param[in] i_side Master - 0; Slave - 1 + * + * @retval ECMD_SUCCESS + * @retval ERROR defined in xml + */ +fapi::ReturnCode +p8_pmc_poll_pstate_halt(const fapi::Target& i_target, uint8_t const i_side) +{ + fapi::ReturnCode rc; + ecmdDataBufferBase pmcstatus(64); + ecmdDataBufferBase porr(64); + + bool is_pstate_error_stopped = false ; + bool is_error_stopped = false; + + uint32_t count = 0 ; + bool is_stopped = false ; + + do + { + + // Confirm that Pstate hardware is quiesced before changing modes + rc = fapiGetScom(i_target, PMC_STATUS_REG_0x00062009 , pmcstatus ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_STATUS_REG_0x00062009) failed."); + break; + } + + // Poll for local Pstates being stopped + for (count = 0 , is_stopped = 0 ; count <= PSTATE_HALT_POLL_COUNT && is_stopped == 0; count++) + { + + // is_stopped = (GPSA_CHG_ONGOING == 0 || + // VOLT_CHG_ONGOING == 0 || + // BRD_CST_ONGOING == 0) ; + is_stopped = pmcstatus.isBitClear(7) || pmcstatus.isBitClear(8) || pmcstatus.isBitClear(9); + + // Leave if stopped + if (is_stopped) + continue; + + // wait for 1 millisecond/loop in hardware + rc = fapiDelay(1000*1000, 20000000); + if (rc) + { + FAPI_ERR("FAPI delay ends up with error"); + break; + } + + // Re-read + rc = fapiGetScom(i_target, PMC_STATUS_REG_0x00062009 , pmcstatus ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_STATUS_REG_0x00062009) failed."); + break; + } + + } // end_for + // Error check + if (!rc.ok()) + { + break; + } + + // check for Pstate errors + is_pstate_error_stopped = pmcstatus.isBitSet(0) || + pmcstatus.isBitSet(1) || + pmcstatus.isBitSet(5) || + pmcstatus.isBitSet(6) || + pmcstatus.isBitSet(11); + + if (is_pstate_error_stopped) + { + FAPI_ERR("Pstate errors exist. Reset may be suspicious but NOT failing as it could be cleared ... "); + } + + if (count > PSTATE_HALT_POLL_COUNT) + { + FAPI_ERR("Timed out in polling for Local Pstates to quiesce. Reset may be suspicious but NOT failing as it could be cleared ... "); + } + + + rc = fapiGetScom(i_target, PMC_PORRR0_REG_0x0006208E , porr ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_PORRR0_REG_0x0006208E) failed."); + break; + } + + // Poll for local Idle being stopped. As specical wake-up was to have + // occured prior to this, execution should be quick. If this times out, + // there is a significant problem. + for (count = 0 , is_stopped = 0 ; count <= PORE_REQ_POLL_COUNT && is_stopped == 0; count++) + { + // is_stopped = (PORRR_PORE_BUSY == 0) ; + is_stopped = porr.isBitClear(20); + + // Leave if stopped + if (is_stopped) + continue; + + // wait for 1 millisecond/loop in hardware + rc = fapiDelay(1000*1000, 20000000); + if (rc) + { + FAPI_ERR("FAPI delay ends up with error"); + break; + } + + // Re-read + rc = fapiGetScom(i_target, PMC_PORRR0_REG_0x0006208E , porr ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_PORRR0_REG_0x0006208E) failed."); + break; + } + + } // end_for + // Error check + if (!rc.ok()) + { + break; + } + + // check for Idle errors + is_error_stopped = porr.isBitSet(21) || pmcstatus.isBitSet(12); + + if (is_error_stopped) + { + FAPI_ERR("PMC Idle halt errors exist. OCC recovery cannot proceed ... "); + const fapi::Target& TARGET = i_target; + const uint64_t & PORR = porr.getDoubleWord(0); + const uint64_t & PMCSTATUS = pmcstatus.getDoubleWord(0); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_IDLE_ERROR); + break; + } + + if (count > PORE_REQ_POLL_COUNT) + { + FAPI_ERR("PMC Timed out in polling for Idle to Halt. OCC recovery cannot proceed ... "); + const fapi::Target& TARGET = i_target; + const uint64_t & PORR = porr.getDoubleWord(0); + const uint64_t & PMCSTATUS = pmcstatus.getDoubleWord(0); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_IDLE_TIMEOUT_ERROR); + break; + } + + } + while (0); + return rc; +} + +// ---------------------------------------------------------------------- +/** + * p8_pmc_poll_idle_halt + * + * @param[in] i_target Chip target + * @param[in] i_side Master - 0; Slave - 1 + * + * @retval ECMD_SUCCESS + * @retval ERROR defined in xml + */ +fapi::ReturnCode +p8_pmc_poll_idle_halt(const fapi::Target& i_target, const uint8_t i_side) +{ + fapi::ReturnCode rc; + ecmdDataBufferBase pmcstatus(64); + ecmdDataBufferBase porr(64); + + bool is_error_stopped = false; + + uint32_t count = 0 ; + bool is_stopped = false ; + + do + { + + // Poll for local Idle being stopped. As special wake-up was to have + // occured prior to this, execution should be quick. If this times out, + // there is a significant problem. + for (count = 0 , is_stopped = 0 ; count <= PORE_REQ_POLL_COUNT && is_stopped == 0; count++) + { + // is_stopped = (PORRR_PORE_BUSY == 0) ; + is_stopped = porr.isBitClear(20); + + // Leave if stopped + if (is_stopped) + continue; + + // wait for 1 millisecond/loop in hardware + rc = fapiDelay(1000*1000, 20000000); + if (rc) + { + FAPI_ERR("FAPI delay ends up with error"); + break; + } + + // Re-read + rc = fapiGetScom(i_target, PMC_PORRR0_REG_0x0006208E , porr ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_PORRR0_REG_0x0006208E) failed."); + break; + } + + } // end_for + // Error check + if (!rc.ok()) + { + break; + } + + // check for Idle errors + is_error_stopped = porr.isBitSet(21) || pmcstatus.isBitSet(12); + + if (is_error_stopped) + { + FAPI_ERR("PMC Idle halt errors exist. OCC recovery cannot proceed ... "); + const fapi::Target& TARGET = i_target; + const uint64_t & PORR = porr.getDoubleWord(0); + const uint64_t & PMCSTATUS = pmcstatus.getDoubleWord(0); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_IDLE_ERROR); + break; + } + + if (count > PORE_REQ_POLL_COUNT) + { + FAPI_ERR("PMC Timed out in polling for Idle to Halt. OCC recovery cannot proceed ... "); + const fapi::Target& TARGET = i_target; + const uint64_t & PORR = porr.getDoubleWord(0); + const uint64_t & PMCSTATUS = pmcstatus.getDoubleWord(0); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_IDLE_TIMEOUT_ERROR); + break; + } + + } + while (0); + return rc; +} + +// ---------------------------------------------------------------------- +/** + * p8_pmc_poll_interchip_halt + * + * @param[in] i_target Chip target + * @param[in] i_side Master - 0; Slave - 1 + * + * @retval ECMD_SUCCESS + * @retval ERROR defined in xml + */ +fapi::ReturnCode +p8_pmc_poll_interchip_halt( const fapi::Target& i_target, + const uint8_t i_side, + bool i_MasterPMC, + const fapi::Target& i_dcm_target) +{ + fapi::ReturnCode rc; + uint32_t e_rc; + ecmdDataBufferBase data(64); + + bool is_stopped = false ; + bool is_pstate_error_stopped = false; + bool is_intchp_error_stopped = false; + + uint32_t count = 0 ; + + + do + { + rc = fapiGetScom(i_target, PMC_INTCHP_COMMAND_REG_0x00062014 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); + break; + } + + e_rc = data.setBit(01); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_INTCHP_COMMAND_REG_0x00062014 on Master during reset"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(i_target, PMC_INTCHP_COMMAND_REG_0x00062014 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); + break; + } + + // Poll for interchip interface to stop + for (count = 0 , is_stopped = 0 ; count <= INTERCHIP_HALT_POLL_COUNT && is_stopped == 0; count++) + { + + rc = fapiGetScom(i_target, PMC_STATUS_REG_0x00062009 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_STATUS_REG_0x00062009) failed."); + break; + } + + // Interchip_Wait1: Read PMC_STATUS_REG + // is_pstate_error_stopped = pstate_processing_is_suspended || + // gpsa_bdcst_error || + // gpsa_vchg_error || + // gpsa_timeout_error || + // pstate_interchip_error; + is_pstate_error_stopped = data.isBitSet(0) || + data.isBitSet(1) || + data.isBitSet(5) || + data.isBitSet(6) || + data.isBitSet(11); + + // Interchip_Wait2: Read PMC_INTCHP_STATUS_REG + // is_intchp_error_stopped = interchip_ecc_ue_err || + // interchip_fsm_err || + // (is_MasterPMC && interchip_slave_error_code != 0) is_MasterPMC + rc = fapiGetScom(i_target, PMC_INTCHP_STATUS_REG_0x00062013 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_INTCHP_STATUS_REG_0x00062013) failed."); + break; + } + is_intchp_error_stopped = data.isBitSet(1) || + data.isBitSet(7) || + (~( data.isBitClear(16,4) && i_MasterPMC)) ; + + // is_stopped = (interchip_ga_ongoing == 0) || + // is_pstate_error_stopped || + // is_intchp_error_stopped ; + is_stopped = data.isBitClear(0) || is_pstate_error_stopped || is_intchp_error_stopped; + + if (is_stopped) + continue; + + FAPI_DBG("polling interchip ongoing : ... "); + + // If !is_stopped Then -->Interchip_Wait1 (Wait limit is parm TD_Interchip_HaltWait_max=260) + + // wait for 1 millisecond/loop in hardware + rc = fapiDelay(1000*1000, 20000000); + if (rc) + { + FAPI_ERR("fapi delay ends up with error"); + break; + } + + } // end_for + // Error check + if (!rc.ok()) + { + break; + } + + if (count > INTERCHIP_HALT_POLL_COUNT) + { + FAPI_INF("Timed out in polling interchip ongoing : Reset may be suspicious but NOT failing as it could be cleared ... "); + const fapi::Target& THISTARGET = i_target; + const fapi::Target& DCMTARGET = i_dcm_target; + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_INTCHP_TIMEOUT_ERROR); + fapiLogError(rc, fapi::FAPI_ERRL_SEV_RECOVERED); + } + + // InterchipIf: PMC_MODE_REG.interchip_halt_if<-1 interchip_halt_if + + rc = fapiGetScom(i_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + e_rc = data.setBit(15); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_MODE_REG_0x00062000 on Master during reset"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(i_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + } + while (0); + return rc; +} + +// ---------------------------------------------------------------------- +/** + * p8_pmc_poll_spivid_halt + * + * @param[in] i_target Chip target + * @param[in] i_side Master - 0; Slave - 1 + * + * @retval ECMD_SUCCESS + * @retval ERROR defined in xml + */ +fapi::ReturnCode +p8_pmc_poll_spivid_halt(const fapi::Target& i_target, + const uint8_t i_side) +{ + fapi::ReturnCode rc; + uint32_t e_rc; + ecmdDataBufferBase data(64); + + bool is_spivid_stopped = false ; + + uint32_t count = 0 ; + + + do + { + // HaltSpivid: PMC_SPIV_COMMAND_REG.spivid_halt_fsm<-1 + rc = fapiGetScom(i_target, PMC_SPIV_COMMAND_REG_0x00062047 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_SPIV_COMMAND_REG_0x00062047) failed."); + break; + } + + e_rc = data.setBit(0); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_SPIV_COMMAND_REG_0x00062047 on Side %d during reset", + i_side); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(i_target, PMC_SPIV_COMMAND_REG_0x00062047 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_SPIV_COMMAND_REG_0x00062047) failed."); + break; + } + + // Spivid_HaltWait: Read PMC_SPIV_STATUS_REG + for (count = 0 , is_spivid_stopped=0; count <= VOLTAGE_CHANGE_POLL_COUNT && is_spivid_stopped==0 ; count++) + { + + rc = fapiGetScom(i_target, PMC_SPIV_STATUS_REG_0x00062046 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_SPIV_STATUS_REG_0x00062046) failed."); + break; + } + is_spivid_stopped = data.isBitClear(0) || + data.isBitSet(1) || + data.isBitSet(2) || + data.isBitSet(3) || + data.isBitSet(4) ; + + if (is_spivid_stopped) + continue; + + FAPI_DBG("Polling spivid ongoing on Side %d", i_side); + + // wait for 1 millisecond/loop in hardware + rc = fapiDelay(1000*1000, 20000000); + if (rc) + { + FAPI_ERR("fapi delay ends up with error"); + break; + } + + } // end for + + // Error check + if (!rc.ok()) + { + break; + } + + // Timeout check + if (count > VOLTAGE_CHANGE_POLL_COUNT) + { + FAPI_ERR("Timed out in polling SPIVID ongoing : Reset_suspicious ... "); + const fapi::Target& TARGET = i_target; + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_SPIVID_TIMEOUT_ERROR); + fapiLogError(rc, fapi::FAPI_ERRL_SEV_RECOVERED); + } + + } + while (0); + return rc; +} + +// ---------------------------------------------------------------------- +/** + * p8_pmc_poll_o2p_halt + * + * @param[in] i_target Chip target + * @param[in] i_side Master - 0; Slave - 1 + * + * @retval ECMD_SUCCESS + * @retval ERROR defined in xml + */ +fapi::ReturnCode +p8_pmc_poll_o2p_halt(const fapi::Target& i_target, + const uint8_t i_side) +{ + fapi::ReturnCode rc; + uint32_t e_rc; + ecmdDataBufferBase data(64); + + bool is_stopped = false ; + + uint32_t count = 0 ; + + + do + { + rc = fapiGetScom(i_target, PMC_O2S_COMMAND_REG_0x00062057 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_O2S_COMMAND_REG__0x00062057) failed."); + break; + } + + e_rc = data.setBit(00); + if(e_rc) + { + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(i_target, PMC_O2S_COMMAND_REG_0x00062057 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_O2S_COMMAND_REG__0x00062057) failed."); + break; + } + + // Poll for O2S to be stopped + for (count = 0 , is_stopped = 0 ; count <= O2S_POLL_COUNT && is_stopped == 0 ; count++) + { + // wait for 1 millisecond/loop in hardware + rc = fapiDelay(1000*1000, 20000000); + if (rc) + { + FAPI_ERR("fapi delay ends up with error"); + break; + } + rc = fapiGetScom(i_target, PMC_O2S_STATUS_REG_0x00062056 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_O2S_STATUS_REG__0x00062056) failed."); + break; + } + + is_stopped = ( data.isBitClear(0) || + data.isBitSet(4) || + data.isBitSet(5) || + data.isBitSet(7)); + FAPI_DBG("Polling O2S ongoing . : .. "); + } + + // Error check + if (!rc.ok()) + { + break; + } + + // Timeout check + if (count > O2P_POLL_COUNT) + { + FAPI_ERR("Timed out in polling O2P ongoing . : Reset_suspicious .. "); + const fapi::Target& TARGET = i_target; + const uint64_t & O2PSTATUS = data.getDoubleWord(0); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_O2P_TIMEOUT_ERROR); + fapiLogError(rc, fapi::FAPI_ERRL_SEV_RECOVERED); + } + + } + while (0); + return rc; +} + } //end extern C /* @@ -2508,6 +2647,21 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: p8_pmc_init.C,v $ +Revision 1.41 2014/04/03 20:29:13 cmolsen +Removed three bool variables that were set only but not used. + +Revision 1.40 2014/03/12 21:03:15 stillgs +Per SW251617, updates for HostCompiler tool flagged logical errors (bitwise operators were scalar was intended + +Revision 1.39 2014/03/06 16:26:54 stillgs +SW250226 (deconfigured chip on DCM) + +Revision 1.38 2014/03/05 22:13:13 stillgs + +- Updates per RAS/callout reviews. In dealing with these comments, did some +restructuring of common code into subroutines. Runs through the Cronus +OCC reset shift cleanly. + Revision 1.37 2013/11/07 14:00:09 stillgs Per SW232699, updated SPIVID parameters diff --git a/src/usr/hwpf/hwp/runtime_errors/p8_pmc_errors.xml b/src/usr/hwpf/hwp/runtime_errors/p8_pmc_errors.xml index 31a38c305..03025a85f 100644 --- a/src/usr/hwpf/hwp/runtime_errors/p8_pmc_errors.xml +++ b/src/usr/hwpf/hwp/runtime_errors/p8_pmc_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2014 --> <!-- --> <!-- p1 --> <!-- --> @@ -20,19 +20,27 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: p8_pmc_errors.xml,v 1.6 2013/08/02 19:15:41 stillgs Exp $ --> -<!-- Error definitions for proc_pmc_init procedure --> +<!-- $Id: p8_pmc_errors.xml,v 1.10 2014/03/10 15:04:05 stillgs Exp $ --> +<!-- Error definitions for proc_pmc_init and proc_pm_init procedure --> <hwpErrors> <!-- *********************************************************************** --> <hwpError> <rc>RC_PROCPM_PMC_CODE_BAD_MODE</rc> <description>Unknown mode passed to proc_pmc_init.</description> - <ffdc>MODE</ffdc> + <ffdc>MODE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- *********************************************************************** --> <hwpError> <rc>RC_PROCPM_PMCINIT_TIMEOUT</rc> <description>time out in polling some register condition.</description> + <callout> + <procedure>CHIP_IN_ERROR</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- *********************************************************************** --> <hwpError> @@ -40,28 +48,56 @@ <description>Master target does not have SPIVID ports enabled: check the configuration setup.</description> <ffdc>MASTER_TARGET</ffdc> <ffdc>ATTR_SPIVID_PORT_ENABLE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROCPM_FIR_ERROR</rc> - <description>Either both targets are masters or slaves in reset mode.</description> + <rc>RC_PROCPM_PMCRESET_SCM_INSTALL_ERROR</rc> + <description>Error found in DCM installment attribute settings for the SCM case.</description> + <ffdc>MASTER_TARGET</ffdc> + <ffdc>SLAVE_TARGET</ffdc> + <ffdc>DCM_INSTALLED_1</ffdc> + <ffdc>DCM_INSTALLED_2</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- *********************************************************************** --> <hwpError> <rc>RC_PROCPM_PMCRESET_DCM_INSTALL_ERROR</rc> - <description>Error found in DCM installment..</description> + <description>Error found in DCM installment attribute settings.</description> + <ffdc>MASTER_TARGET</ffdc> + <ffdc>SLAVE_TARGET</ffdc> + <ffdc>DCM_INSTALLED_1</ffdc> + <ffdc>DCM_INSTALLED_2</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- *********************************************************************** --> <hwpError> <rc>RC_PROCPM_PMC_MASTER_CONFIG_ERROR</rc> <description>MasterPMC bit of Master PMC is not set.</description> <ffdc>MASTERPMCMODE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- *********************************************************************** --> <hwpError> <rc>RC_PROCPM_PMC_SLAVE_CONFIG_ERROR</rc> <description>MasterPMC bit of Slave PMC is not set.</description> <ffdc>SLAVEPMCMODE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- *********************************************************************** --> <hwpError> @@ -69,6 +105,10 @@ <description>Master is enabled with interchip interface but slave is not.</description> <ffdc>MASTERPMCMODE</ffdc> <ffdc>SLAVEPMCMODE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- *********************************************************************** --> <hwpError> @@ -76,6 +116,93 @@ <description>Master is enabled with FW pstate mode but slave is not </description> <ffdc>MASTERPMCMODE</ffdc> <ffdc>SLAVEPMCMODE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_PMCRESET_IDLE_ERROR</rc> + <description>PMC Idle halt errors exist. OCC recovery cannot proceed.</description> + <ffdc>TARGET</ffdc> + <ffdc>PORR</ffdc> + <ffdc>PMCSTATUS</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_PMCRESET_IDLE_TIMEOUT_ERROR</rc> + <description>Timed out in polling for Idle to Halt. OCC recovery cannot proceed </description> + <ffdc>TARGET</ffdc> + <ffdc>PORR</ffdc> + <ffdc>PMCSTATUS</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_PMCRESET_SPIVID_TIMEOUT_ERROR</rc> + <description>Timed out in polling for SPIVID controller to Halt. OCC reset is suspious but carried out</description> + <collectRegisterFfdc> + <id>REG_FFDC_SPIVID_REGISTERS</id> + <target>TARGET</target> + </collectRegisterFfdc> + <!-- No callout as this only logs data for use if the PMC reset (part of the OCC reset) actually fails --> </hwpError> <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_PMCRESET_INTCHP_TIMEOUT_ERROR</rc> + <description>Timed out in polling for InterChip Interface to Halt. OCC reset is suspious but carried out</description> + <collectRegisterFfdc> + <id>REG_FFDC_PSTATE_REGISTERS</id> + <id>REG_FFDC_SPIVID_REGISTERS</id> + <target>THISTARGET</target> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>REG_FFDC_PSTATE_REGISTERS</id> + <id>REG_FFDC_SPIVID_REGISTERS</id> + <target>DCMTARGET</target> + </collectRegisterFfdc> + <!-- No callout as this only logs data for use if the PMC reset (part of the OCC reset) actually fails --> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_PMCRESET_O2P_TIMEOUT_ERROR</rc> + <description>Timed out in polling for OCI to PIB Bridge to Halt. OCC reset is suspious but carried out</description> + <ffdc>TARGET</ffdc> + <ffdc>O2PSTATUS</ffdc> + <!-- No callout as this only logs data for use if the PMC reset (part of the OCC reset) actually fails --> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_PMCINIT_SCM_INSTALL_ERROR</rc> + <description>Error found in DCM installment attribute settings for the SCM case in the PMC INIT phase..</description> + <ffdc>MASTER_TARGET</ffdc> + <ffdc>SLAVE_TARGET</ffdc> + <ffdc>DCM_INSTALLED_1</ffdc> + <ffdc>DCM_INSTALLED_2</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_PMCINIT_DCM_INSTALL_ERROR</rc> + <description>Error found in DCM installment attribute settings in the PMC INIT phase.</description> + <ffdc>MASTER_TARGET</ffdc> + <ffdc>SLAVE_TARGET</ffdc> + <ffdc>DCM_INSTALLED_1</ffdc> + <ffdc>DCM_INSTALLED_2</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> </hwpErrors> |