diff options
Diffstat (limited to 'src/usr/hwpf/hwp')
35 files changed, 3086 insertions, 1482 deletions
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C index 99dbcf9c5..f108940f5 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp.C,v 1.4 2012/09/24 10:55:02 jmcgill Exp $ +// $Id: proc_build_smp.C,v 1.6 2013/01/21 03:11:23 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp.C,v $ //------------------------------------------------------------------------------ // *| @@ -368,7 +368,7 @@ fapi::ReturnCode proc_build_smp_process_system( } // retrieve safe mode attribute - // if user overrides is set, it will take presedence over write above + // if user overrides is set, it will take precedence over write above rc = FAPI_ATTR_GET(ATTR_PROC_FABRIC_ASYNC_SAFE_MODE, NULL, temp_attr); @@ -473,6 +473,10 @@ fapi::ReturnCode proc_build_smp_process_chip( { // return code fapi::ReturnCode rc; + uint8_t pcie_enabled; + uint8_t nx_enabled; + uint8_t x_enabled; + uint8_t a_enabled; // mark function entry FAPI_DBG("proc_build_smp_process_chip: Start"); @@ -515,6 +519,59 @@ fapi::ReturnCode proc_build_smp_process_chip( FAPI_ERR("proc_build_smp_process_chip: Error from proc_fab_smp_get_chip_id_attr"); break; } + + // query NX partial good attribute + rc = FAPI_ATTR_GET(ATTR_PROC_NX_ENABLE, + &(io_smp_chip.chip->this_chip), + nx_enabled); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_PROC_NX_ENABLE"); + break; + } + + // query X partial good attribute + rc = FAPI_ATTR_GET(ATTR_PROC_X_ENABLE, + &(io_smp_chip.chip->this_chip), + x_enabled); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_PROC_X_ENABLE"); + break; + } + + // query A partial good attribute + rc = FAPI_ATTR_GET(ATTR_PROC_A_ENABLE, + &(io_smp_chip.chip->this_chip), + a_enabled); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_PROC_A_ENABLE"); + break; + } + + // query PCIE partial good attribute + rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_ENABLE, + &(io_smp_chip.chip->this_chip), + pcie_enabled); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_PROC_PCIE_ENABLE"); + break; + } + + io_smp_chip.nx_enabled = + (nx_enabled == fapi::ENUM_ATTR_PROC_NX_ENABLE_ENABLE); + + io_smp_chip.x_enabled = + (x_enabled == fapi::ENUM_ATTR_PROC_X_ENABLE_ENABLE); + + io_smp_chip.a_enabled = + (a_enabled == fapi::ENUM_ATTR_PROC_A_ENABLE_ENABLE); + + io_smp_chip.pcie_enabled = + (pcie_enabled == fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE); + } while(0); // mark function exit diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H index 66ce8b5a2..8f2bc2489 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp.H,v 1.6 2012/09/24 04:59:17 jmcgill Exp $ +// $Id: proc_build_smp.H,v 1.8 2013/01/21 03:11:30 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp.H,v $ //------------------------------------------------------------------------------ // *| @@ -130,6 +130,11 @@ struct proc_build_smp_chip // fabric chip/node ID proc_fab_smp_chip_id chip_id; proc_fab_smp_node_id node_id; + // partial good attributes + bool nx_enabled; + bool x_enabled; + bool a_enabled; + bool pcie_enabled; // node/system master designation (curr) bool master_chip_node_curr; bool master_chip_sys_curr; diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml index 0157ffda3..f3d839bad 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> <!-- --> <!-- p1 --> <!-- --> @@ -109,4 +109,16 @@ <description>Status mismatch detected on ADU operation executed for SMP configuration.</description> <ffdc>STATUS_DATA</ffdc> </hwpError> + <hwpError> + <rc>RC_PROC_BUILD_SMP_X_PARTIAL_GOOD_ERR</rc> + <description>X bus partial good attribute state does not allow for action on target.</description> + </hwpError> + <hwpError> + <rc>RC_PROC_BUILD_SMP_A_PARTIAL_GOOD_ERR</rc> + <description>A bus partial good attribute state does not allow for action on target.</description> + </hwpError> + <hwpError> + <rc>RC_PROC_BUILD_SMP_PCIE_PARTIAL_GOOD_ERR</rc> + <description>PCIE partial good attribute state does not allow for action on target.</description> + </hwpError> </hwpErrors> diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C index 1f4051fa2..57204afa1 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_fbc_ab.C,v 1.3 2012/09/24 05:00:55 jmcgill Exp $ +// $Id: proc_build_smp_fbc_ab.C,v 1.5 2013/01/21 03:11:32 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_ab.C,v $ //------------------------------------------------------------------------------ // *| @@ -119,7 +119,7 @@ fapi::ReturnCode proc_build_smp_get_f_owpack_config( do { - // read PB A Link Framer Configuration register + // read PB F Link Framer Configuration register rc = fapiGetScom(i_smp_chip.chip->this_chip, PB_F_FMR_CFG_0x09010813, data); @@ -746,19 +746,19 @@ fapi::ReturnCode proc_build_smp_set_pb_hp_mode( uint8_t a_id[PROC_FAB_SMP_NUM_A_LINKS]; uint8_t f_id[PROC_FAB_SMP_NUM_F_LINKS]; // per-link address disable values - bool a_addr_dis[PROC_FAB_SMP_NUM_A_LINKS]; - bool f_addr_dis[PROC_FAB_SMP_NUM_F_LINKS]; + bool a_addr_dis[PROC_FAB_SMP_NUM_A_LINKS] = { false, false, false }; + bool f_addr_dis[PROC_FAB_SMP_NUM_F_LINKS] = { false, false }; // aggregate link settings - bool a_link_aggregate; - bool f_link_aggregate; + bool a_link_aggregate = false; + bool f_link_aggregate = false; // link ow pack settings - bool a_link_owpack; - bool a_link_owpack_priority; - bool f_link_owpack; - bool f_link_owpack_priority; + bool a_link_owpack = false; + bool a_link_owpack_priority = false; + bool f_link_owpack = false; + bool f_link_owpack_priority = false; // link command rates - uint8_t a_cmd_rate; - uint8_t f_cmd_rate; + uint8_t a_cmd_rate = 0x00; + uint8_t f_cmd_rate = 0x00; // mark function entry FAPI_DBG("proc_build_smp_set_pb_hp_mode: Start"); @@ -773,6 +773,13 @@ fapi::ReturnCode proc_build_smp_set_pb_hp_mode( { // determine link enable a_en[l] = (a_target[l]->getType() != fapi::TARGET_TYPE_NONE); + if (a_en[l] && !i_smp_chip.a_enabled) + { + FAPI_ERR("proc_build_smp_set_pb_hp_mode: Partial good attribute error (A)"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_A_PARTIAL_GOOD_ERR); + break; + } + // determine link ID proc_fab_smp_node_id dest_node_id = FBC_NODE_ID_0; if (a_en[l]) @@ -798,80 +805,102 @@ fapi::ReturnCode proc_build_smp_set_pb_hp_mode( f_en[1] = i_smp_chip.chip->enable_f1; f_id[1] = i_smp_chip.chip->f1_node_id; - // determine address/data assignents & aggregate mode programming - rc = proc_build_smp_calc_link_setup(i_smp_chip, - PROC_FAB_SMP_NUM_A_LINKS, - PROC_FAB_SMP_NUM_NODE_IDS, - PB_A_MODE_0x0801080A, - PB_A_MODE_LINK_DELAY_START_BIT, - PB_A_MODE_LINK_DELAY_END_BIT, - a_en, - a_id, - a_addr_dis, - a_link_aggregate); - if (rc) + for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_F_LINKS; l++) { - FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_calc_link_setup (A)"); - break; + if (f_en[l] && !i_smp_chip.pcie_enabled) + { + FAPI_ERR("proc_build_smp_set_pb_hp_mode: Partial good attribute error (PCIE)"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_PCIE_PARTIAL_GOOD_ERR); + break; + } } - - rc = proc_build_smp_calc_link_setup(i_smp_chip, - PROC_FAB_SMP_NUM_F_LINKS, - PROC_FAB_SMP_NUM_NODE_IDS, - PB_IOF_MODE_0x09011C0A, - PB_IOF_MODE_LINK_DELAY_START_BIT, - PB_IOF_MODE_LINK_DELAY_END_BIT, - f_en, - f_id, - f_addr_dis, - f_link_aggregate); if (rc) { - FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_calc_link_setup (F)"); break; } - // determine link command rates - rc = proc_build_smp_get_a_owpack_config(i_smp_chip, - a_link_owpack, - a_link_owpack_priority); - if (rc) + // determine address/data assignents, aggregate mode programming & + // link command rates (A) + if (i_smp_chip.a_enabled) { - FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_get_a_owpack_config"); - break; - } + rc = proc_build_smp_calc_link_setup(i_smp_chip, + PROC_FAB_SMP_NUM_A_LINKS, + PROC_FAB_SMP_NUM_NODE_IDS, + PB_A_MODE_0x0801080A, + PB_A_MODE_LINK_DELAY_START_BIT, + PB_A_MODE_LINK_DELAY_END_BIT, + a_en, + a_id, + a_addr_dis, + a_link_aggregate); + if (rc) + { + FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_calc_link_setup (A)"); + break; + } - rc = proc_build_smp_calc_a_cmd_rate(i_smp.freq_a, - i_smp.freq_pb, - a_link_owpack, - a_link_owpack_priority, - a_link_aggregate, - a_cmd_rate); - if (rc) - { - FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_calc_a_cmd_rate"); - break; - } + rc = proc_build_smp_get_a_owpack_config(i_smp_chip, + a_link_owpack, + a_link_owpack_priority); + if (rc) + { + FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_get_a_owpack_config"); + break; + } - rc = proc_build_smp_get_f_owpack_config(i_smp_chip, - f_link_owpack, - f_link_owpack_priority); - if (rc) - { - FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_get_f_owpack_config"); - break; + rc = proc_build_smp_calc_a_cmd_rate(i_smp.freq_a, + i_smp.freq_pb, + a_link_owpack, + a_link_owpack_priority, + a_link_aggregate, + a_cmd_rate); + if (rc) + { + FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_calc_a_cmd_rate"); + break; + } } - rc = proc_build_smp_calc_f_cmd_rate(i_smp.freq_pcie, - i_smp.freq_pb, - f_link_owpack, - f_link_owpack_priority, - f_link_aggregate, - f_cmd_rate); - if (rc) + if (i_smp_chip.pcie_enabled) { - FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_calc_a_cmd_rate"); - break; + // determine address/data assignents, aggregate mode programming & + // link command rates (F) + rc = proc_build_smp_calc_link_setup(i_smp_chip, + PROC_FAB_SMP_NUM_F_LINKS, + PROC_FAB_SMP_NUM_NODE_IDS, + PB_IOF_MODE_0x09011C0A, + PB_IOF_MODE_LINK_DELAY_START_BIT, + PB_IOF_MODE_LINK_DELAY_END_BIT, + f_en, + f_id, + f_addr_dis, + f_link_aggregate); + if (rc) + { + FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_calc_link_setup (F)"); + break; + } + + rc = proc_build_smp_get_f_owpack_config(i_smp_chip, + f_link_owpack, + f_link_owpack_priority); + if (rc) + { + FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_get_f_owpack_config"); + break; + } + + rc = proc_build_smp_calc_f_cmd_rate(i_smp.freq_pcie, + i_smp.freq_pb, + f_link_owpack, + f_link_owpack_priority, + f_link_aggregate, + f_cmd_rate); + if (rc) + { + FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_calc_f_cmd_rate"); + break; + } } // build data buffer with per-link values @@ -1105,11 +1134,11 @@ fapi::ReturnCode proc_build_smp_set_pb_hpx_mode( // per-link destination IDs uint8_t x_id[PROC_FAB_SMP_NUM_X_LINKS]; // per-link address disable values - bool x_addr_dis[PROC_FAB_SMP_NUM_X_LINKS]; + bool x_addr_dis[PROC_FAB_SMP_NUM_X_LINKS] = { false, false, false, false }; // aggregate link setting - bool x_link_aggregate; + bool x_link_aggregate = false; // link command rate - uint8_t x_cmd_rate; + uint8_t x_cmd_rate = 0x00; // mark function entry FAPI_DBG("proc_build_smp_set_pb_hpx_mode: Start"); @@ -1125,6 +1154,13 @@ fapi::ReturnCode proc_build_smp_set_pb_hpx_mode( { // determine link enable x_en[l] = (x_target[l]->getType() != fapi::TARGET_TYPE_NONE); + if (x_en[l] && !i_smp_chip.x_enabled) + { + FAPI_ERR("proc_build_smp_set_pb_hpx_mode: Partial good attribute error (X)"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_X_PARTIAL_GOOD_ERR); + break; + } + // determine link ID proc_fab_smp_chip_id dest_chip_id = FBC_CHIP_ID_0; if (x_en[l]) @@ -1143,33 +1179,36 @@ fapi::ReturnCode proc_build_smp_set_pb_hpx_mode( break; } - // determine address/data assignents & aggregate mode programming - rc = proc_build_smp_calc_link_setup(i_smp_chip, - PROC_FAB_SMP_NUM_X_LINKS, - PROC_FAB_SMP_NUM_CHIP_IDS, - PB_X_MODE_0x04010C0A, - PB_X_MODE_LINK_DELAY_START_BIT, - PB_X_MODE_LINK_DELAY_END_BIT, - x_en, - x_id, - x_addr_dis, - x_link_aggregate); - if (rc) + if (i_smp_chip.x_enabled) { - FAPI_ERR("proc_build_smp_set_pb_hpx_mode: Error from proc_build_smp_calc_link_setup (X)"); - break; - } + // determine address/data assignents & aggregate mode programming + rc = proc_build_smp_calc_link_setup(i_smp_chip, + PROC_FAB_SMP_NUM_X_LINKS, + PROC_FAB_SMP_NUM_CHIP_IDS, + PB_X_MODE_0x04010C0A, + PB_X_MODE_LINK_DELAY_START_BIT, + PB_X_MODE_LINK_DELAY_END_BIT, + x_en, + x_id, + x_addr_dis, + x_link_aggregate); + if (rc) + { + FAPI_ERR("proc_build_smp_set_pb_hpx_mode: Error from proc_build_smp_calc_link_setup (X)"); + break; + } - // determine link command rate - rc = proc_build_smp_calc_x_cmd_rate(i_smp.freq_x, - i_smp.freq_pb, - i_smp.x_bus_8B, - x_link_aggregate, - x_cmd_rate); - if (rc) - { - FAPI_ERR("proc_build_smp_set_pb_hpx_mode: Error from proc_build_smp_calc_x_cmd_rate"); - break; + // determine link command rate + rc = proc_build_smp_calc_x_cmd_rate(i_smp.freq_x, + i_smp.freq_pb, + i_smp.x_bus_8B, + x_link_aggregate, + x_cmd_rate); + if (rc) + { + FAPI_ERR("proc_build_smp_set_pb_hpx_mode: Error from proc_build_smp_calc_x_cmd_rate"); + break; + } } // build data buffer with per-link values diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.C index 798bd19b2..eb8c33392 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.C +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_fbc_nohp.C,v 1.3 2012/09/05 03:13:17 jmcgill Exp $ +// $Id: proc_build_smp_fbc_nohp.C,v 1.5 2013/01/21 03:11:34 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_nohp.C,v $ //------------------------------------------------------------------------------ // *| @@ -648,13 +648,13 @@ fapi::ReturnCode proc_build_smp_set_f_trace( if (!rc.ok()) { - FAPI_ERR("proc_build_smp_set_a_trace: fapiPutScom error (PB_F_TRACE_0x09010812)"); + FAPI_ERR("proc_build_smp_set_f_trace: fapiPutScom error (PB_F_TRACE_0x09010812)"); break; } } while(0); // mark function exit - FAPI_DBG("proc_build_smp_set_f_traec: End"); + FAPI_DBG("proc_build_smp_set_f_trace: End"); return rc; } @@ -679,6 +679,8 @@ fapi::ReturnCode proc_build_smp_set_fbc_nohp( (p_iter != n_iter->second.chips.end()) && (rc.ok()); p_iter++) { + fapi::Target target = p_iter->second.chip->this_chip; + // PB Mode register rc = proc_build_smp_set_pb_mode(p_iter->second, i_smp); @@ -698,27 +700,36 @@ fapi::ReturnCode proc_build_smp_set_fbc_nohp( } // X link trace setup - rc = proc_build_smp_set_x_trace(p_iter->second); - if (!rc.ok()) + if (p_iter->second.x_enabled) { - FAPI_ERR("proc_build_smp_set_fbc_nohp: Error from proc_build_smp_set_x_trace"); - break; + rc = proc_build_smp_set_x_trace(p_iter->second); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_set_fbc_nohp: Error from proc_build_smp_set_x_trace"); + break; + } } // A link trace setup - rc = proc_build_smp_set_a_trace(p_iter->second); - if (!rc.ok()) + if (p_iter->second.a_enabled) { - FAPI_ERR("proc_build_smp_set_fbc_nohp: Error from proc_build_smp_set_a_trace"); - break; + rc = proc_build_smp_set_a_trace(p_iter->second); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_set_fbc_nohp: Error from proc_build_smp_set_a_trace"); + break; + } } // F link trace setup - rc = proc_build_smp_set_f_trace(p_iter->second); - if (!rc.ok()) + if (p_iter->second.pcie_enabled) { - FAPI_ERR("proc_build_smp_set_fbc_nohp: Error from proc_build_smp_set_f_trace"); - break; + rc = proc_build_smp_set_f_trace(p_iter->second); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_set_fbc_nohp: Error from proc_build_smp_set_f_trace"); + break; + } } } } diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize_attributes.xml b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize_attributes.xml index a8d1c13ec..68e088c3f 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize_attributes.xml +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize_attributes.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> <!-- --> <!-- p1 --> <!-- --> @@ -64,6 +64,34 @@ <platInit/> <persistRuntime/> </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_A_ENABLE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>ABUS chiplet partial good control + creator: platform + firmware notes: + must track ATTR_CHIP_REGIONS_TO_ENABLE + </description> + <valueType>uint8</valueType> + <enum>DISABLE = 0x0, ENABLE = 0x1</enum> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_X_ENABLE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>XBUS chiplet partial good control + creator: platform + firmware notes: + must track ATTR_CHIP_REGIONS_TO_ENABLE + </description> + <valueType>uint8</valueType> + <enum>DISABLE = 0x0, ENABLE = 0x1</enum> + <platInit/> + <persistRuntime/> + </attribute> <!-- ********************************************************************* --> <attribute> <id>ATTR_PROC_ADU_UNTRUSTED_BAR_BASE_ADDR</id> diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C index f913aac70..7b1cd0ac4 100644 --- a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C +++ b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_pcie_config.C,v 1.3 2012/12/11 23:59:02 jmcgill Exp $ +// $Id: proc_pcie_config.C,v 1.4 2013/01/20 19:28:14 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_config.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -199,6 +199,10 @@ fapi::ReturnCode proc_pcie_config( break; } } + else + { + FAPI_DBG("proc_pcie_scominit: Skipping initialization (partial good)"); + } } while(0); diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.C b/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.C index 32bd122a1..7c2bd969d 100644 --- a/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.C +++ b/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.C @@ -1,27 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ -// $Id: proc_fab_iovalid.C,v 1.8 2012/07/23 14:15:51 jmcgill Exp $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_fab_iovalid.C,v 1.9 2013/01/21 01:42:45 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_fab_iovalid.C,v $ //------------------------------------------------------------------------------ // *| @@ -141,6 +140,9 @@ fapi::ReturnCode proc_fab_iovalid_manage_x_links( uint32_t rc_ecmd = 0; fapi::ReturnCode rc; + // partial good attribute + uint8_t xbus_enable_attr; + // mark function entry FAPI_DBG("proc_fab_iovalid_manage_x_links: Start"); @@ -152,6 +154,23 @@ fapi::ReturnCode proc_fab_iovalid_manage_x_links( i_proc_chip.x2 || i_proc_chip.x3) { + // query XBUS partial good attribute + rc = FAPI_ATTR_GET(ATTR_PROC_X_ENABLE, + &(i_proc_chip.this_chip), + xbus_enable_attr); + if (!rc.ok()) + { + FAPI_ERR("proc_fab_iovalid_manage_x_links: Error querying ATTR_PROC_X_ENABLE"); + break; + } + + if (xbus_enable_attr != fapi::ENUM_ATTR_PROC_X_ENABLE_ENABLE) + { + FAPI_ERR("proc_fab_iovalid_manage_x_links: Partial good attribute error"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_FAB_IOVALID_X_PARTIAL_GOOD_ERR); + break; + } + if (i_proc_chip.x0) { FAPI_DBG("proc_fab_iovalid_manage_x_links: Adding link X0 to active link mask"); @@ -222,6 +241,9 @@ fapi::ReturnCode proc_fab_iovalid_manage_a_links( uint32_t rc_ecmd = 0; fapi::ReturnCode rc; + // partial good attribute + uint8_t abus_enable_attr; + // mark function entry FAPI_DBG("proc_fab_iovalid_manage_a_links: Start"); @@ -232,6 +254,23 @@ fapi::ReturnCode proc_fab_iovalid_manage_a_links( i_proc_chip.a1 || i_proc_chip.a2) { + // query ABUS partial good attribute + rc = FAPI_ATTR_GET(ATTR_PROC_A_ENABLE, + &(i_proc_chip.this_chip), + abus_enable_attr); + if (!rc.ok()) + { + FAPI_ERR("proc_fab_iovalid_manage_a_links: Error querying ATTR_PROC_A_ENABLE"); + break; + } + + if (abus_enable_attr != fapi::ENUM_ATTR_PROC_A_ENABLE_ENABLE) + { + FAPI_ERR("proc_fab_iovalid_manage_a_links: Partial good attribute error"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_FAB_IOVALID_A_PARTIAL_GOOD_ERR); + break; + } + if (i_proc_chip.a0) { FAPI_DBG("proc_fab_iovalid_manage_a_links: Adding link A0 to active link mask"); diff --git a/src/usr/hwpf/hwp/initfiles/edi.io.define b/src/usr/hwpf/hwp/initfiles/edi.io.define index 05bfb2dd9..54e03ffea 100644 --- a/src/usr/hwpf/hwp/initfiles/edi.io.define +++ b/src/usr/hwpf/hwp/initfiles/edi.io.define @@ -1,233 +1,3 @@ -#-- $Id: edi.io.define,v 1.3 2012/07/09 22:31:54 ttnguyen Exp $ -#-- CHANGE HISTORY: -#-------------------------------------------------------------------------------- -#-- Version:|Author: | Date: | Comment: -#-- --------|--------|--------|-------------------------------------------------- -#-- 1.1 |thomsen |06/11/12|Created initial version -#-- --------|--------|--------|-------------------------------------------------- -#-------------------------------------------------------------------------------- -# End of revision history -#-------------------------------------------------------------------------------- -define tx_mode_pl=010000000; #080 -define tx_cntl_stat_pl=010000001; #081 -define tx_spare_mode_pl=010000010; #082 -#define #tx_id_pl=010000100; #084 -define tx_bist_stat_pl=010000101; #085 -define tx_prbs_mode_pl=010000110; #086 -define tx_data_cntl_gcrmsg_pl=010000111; #087 -define tx_sync_pattern_gcrmsg_pl=010001000; #088 -define tx_fir_pl=010001010; #08A -define tx_fir_mask_pl=010001011; #08B -define tx_fir_error_inject_pl=010001100; #08C -define tx_mode_fast_pl=010001101; #08D -define tx_tdr_stat_pl=010001110; #08E -define tx_cntl_gcrmsg_pl=010001111; #08F -define tx_clk_mode_pg=110000000; #180 -define tx_spare_mode_pg=110000001; #181 -define tx_cntl_stat_pg=110000010; #182 -define tx_mode_pg=110000011; #183 -define tx_reset_act_pg=110001000; #188 -define tx_bist_stat_pg=110001001; #189 -define tx_fir_pg=110001010; #18A -define tx_fir_mask_pg=110001011; #18B -define tx_fir_error_inject_pg=110001100; #18C -define tx_id1_pg=110010010; #192 -define tx_id2_pg=110010011; #193 -define tx_id3_pg=110010100; #194 -define tx_clk_cntl_gcrmsg_pg=110011000; #198 -define tx_ffe_mode_pg=110011001; #199 -define tx_ffe_main_pg=110011010; #19A -define tx_ffe_post_pg=110011011; #19B -define tx_ffe_margin_pg=110011100; #19C -define tx_bad_lane_enc_gcrmsg_pg=110011101; #19D -define tx_ber_cntl_pg=110011110; #19E -define tx_sls_lane_enc_gcrmsg_pg=110011111; #19F -define tx_wt_seg_enable_pg=110100000; #1A0 -define tx_lane_disabled_vec_0_15_pg=110100011; #1A3 -define tx_lane_disabled_vec_16_31_pg=110100100; #1A4 -define tx_sls_lane_mux_gcrmsg_pg=110100101; #1A5 -define tx_dyn_rpr_pg=110100110; #1A6 -define tx_slv_mv_sls_ln_req_gcrmsg_pg=110100111; #1A7 -define tx_wiretest_pp=111010000; #1D0 -define tx_mode_pp=111010001; #1D1 -define tx_sls_gcrmsg_pp=111010010; #1D2 -define tx_ber_cntl_a_pp=111010011; #1D3 -define tx_ber_cntl_b_pp=111010100; #1D4 -define tx_dyn_recal_timeouts_pp=111010101; #1D5 -define tx_bist_cntl_pp=111010110; #1D6 -define tx_ber_cntl_sls_pp=111010111; #1D7 -define tx_cntl_pp=111011000; #1D8 -define tx_reset_cfg_pp=111011001; #1D9 -define tx_tdr_cntl1_pp=111011010; #1DA -define tx_tdr_cntl2_pp=111011011; #1DB -define tx_tdr_cntl3_pp=111011100; #1DC -define tx_impcal_pb=111100000; #1E0 -define tx_impcal_nval_pb=111100001; #1E1 -define tx_impcal_pval_pb=111100010; #1E2 -define tx_impcal_p_4x_pb=111100011; #1E3 -define tx_impcal_swo1_pb=111100100; #1E4 -define tx_impcal_swo2_pb=111100101; #1E5 -define tx_analog_iref_pb=111100110; #1E6 -define tx_minikerf_pb=111100111; #1E7 -define tx_init_version_pb=111101000; #1E8 -define tx_scratch_reg_pb=111101001; #1E9 -define rx_mode_pl=000000000; #000 -define rx_cntl_pl=000000001; #001 -define rx_spare_mode_pl=000000010; #002 -define rx_prot_edge_status_pl=000000011; #003 -#define #rx_prot_gb_status_pl=000000100; #004 -define rx_bist_stat_pl=000000101; #005 -#define #rx_eyeopt_stat_pl=000000111; #007 -define rx_offset_even_pl=000001000; #008 -define rx_offset_odd_pl=000001001; #009 -define rx_amp_val_pl=000001010; #00A -define rx_amp_cntl_pl=000001011; #00B -define rx_prot_status_pl=000001100; #00C -define rx_prot_mode_pl=000001101; #00D -define rx_prot_cntl_pl=000001110; #00E -#define #rx_wiretest_stat_pl=000001110; #00E -define rx_fifo_stat_pl=000001111; #00F -define rx_ap_pl =000010000; #010 -define rx_an_pl =000010001; #011 -define rx_amin_pl=000010010; #012 -define rx_h1_even_pl=000010011; #013 -define rx_h1_odd_pl=000010100; #014 -define rx_prbs_mode_pl=000010110; #016 -define rx_stat_pl=000011000; #018 -define rx_deskew_stat_pl=000011001; #019 -define rx_fir_pl=000011010; #01A -define rx_fir_mask_pl=000011011; #01B -define rx_fir_error_inject_pl=000011100; #01C -define rx_sls_pl=000011101; #01D -define rx_wt_status_pl=000011110; #01E -define rx_fifo_cntl_pl=000011111; #01F -define rx_ber_status_pl=000100000; #020 -define rx_ber_timer_0_15_pl=000100001; #021 -define rx_ber_timer_16_31_pl=000100010; #022 -define rx_ber_timer_32_39_pl=000100011; #023 -define rx_servo_cntl_pl=000100100; #024 -define rx_fifo_diag_0_15_pl=000100101; #025 -define rx_fifo_diag_16_31_pl=000100110; #026 -define rx_fifo_diag_32_47_pl=000100111; #027 -define rx_eye_width_status_pl=000101000; #028 -define rx_eye_width_cntl_pl=000101001; #029 -define rx_dfe_clkadj_pl=000101010; #02A -define rx_trace_pl=000101011; #02B -define rx_servo_ber_count_pl=000101100; #02C -define rx_eye_opt_stat_pl=000101101; #02D -define rx_clk_mode_pg=100000000; #100 -define rx_spare_mode_pg=100000001; #101 -define rx_stop_cntl_stat_pg=100000010; #102 -define rx_mode_pg=100000011; #103 -define rx_stop_addr_lsb_pg=100000111; #107 -define rx_stop_mask_lsb_pg=100001000; #108 -define rx_reset_act_pg=100001001; #109 -define rx_id1_pg=100001010; #10A -define rx_id2_pg=100001011; #10B -define rx_id3_pg=100001100; #10C -define rx_minikerf_pg=100001101; #10D -define rx_dyn_rpr_debug2_pg=100001110; #10E -define rx_sls_mode_pg=100001111; #10F -define rx_training_start_pg=100010000; #110 -define rx_training_status_pg=100010001; #111 -define rx_recal_status_pg=100010010; #112 -define rx_timeout_sel_pg=100010011; #113 -define rx_fifo_mode_pg=100010100; #114 -#define #rx_state_debug_pg=100010101; #115 -#define #rx_state_val_pg=100010110; #116 -define rx_sls_status_pg=100010111; #117 -define rx_fir1_pg=100011010; #11A -define rx_fir2_pg=100011011; #11B -define rx_fir1_mask_pg=100011100; #11C -define rx_fir2_mask_pg=100011101; #11D -define rx_fir1_error_inject_pg=100011110; #11E -define rx_fir2_error_inject_pg=100011111; #11F -define rx_fir_training_pg=100100000; #120 -define rx_fir_training_mask_pg=100100001; #121 -define rx_timeout_sel1_pg=100100010; #122 -define rx_lane_bad_vec_0_15_pg=100100011; #123 -define rx_lane_bad_vec_16_31_pg=100100100; #124 -define rx_lane_disabled_vec_0_15_pg=100100101; #125 -define rx_lane_disabled_vec_16_31_pg=100100110; #126 -define rx_lane_swapped_vec_0_15_pg=100100111; #127 -define rx_lane_swapped_vec_16_31_pg=100101000; #128 -define rx_init_state_pg=100101001; #129 -define rx_wiretest_state_pg=100101010; #12A -define rx_wiretest_laneinfo_pg=100101011; #12B -define rx_wiretest_gcrmsgs_pg=100101100; #12C -define rx_deskew_gcrmsgs_pg=100101101; #12D -define rx_deskew_state_pg=100101110; #12E -define rx_deskew_mode_pg=100101111; #12F -define rx_deskew_status_pg=100110000; #130 -define rx_bad_lane_enc_gcrmsg_pg=100110001; #131 -define rx_static_repair_state_pg=100110010; #132 -define rx_tx_bus_info_pg=100110011; #133 -define rx_sls_lane_enc_gcrmsg_pg=100110100; #134 -define rx_fence_pg=100110101; #135 -define rx_timeout_sel2_pg=100110111; #137 -define rx_misc_analog_pg=100111000; #138 -define rx_dyn_rpr_pg=100111001; #139 -define rx_dyn_rpr_gcrmsg_pg=100111010; #13A -define rx_dyn_rpr_err_tallying1_pg=100111011; #13B -define rx_eo_final_l2u_gcrmsgs_pg=100111100; #13C -define rx_gcr_msg_debug_dest_ids_pg=100111101; #13D -define rx_gcr_msg_debug_src_ids_pg=100111110; #13E -define rx_gcr_msg_debug_dest_addr_pg=100111111; #13F -define rx_gcr_msg_debug_write_data_pg=101000000; #140 -define rx_dyn_recal_pg=101000001; #141 -define rx_wt_clk_status_pg=101000010; #142 -define rx_dyn_recal_config_pg=101000011; #143 -define rx_wt_config_pg=101000100; #144 -define rx_dyn_recal_gcrmsg_pg=101000101; #145 -define rx_wiretest_pll_cntl_pg=101000110; #146 -define rx_eo_step_cntl_pg=101000111; #147 -define rx_eo_step_stat_pg=101001000; #148 -define rx_eo_step_fail_pg=101001001; #149 -define rx_ap_pg =101001010; #14A -define rx_an_pg =101001011; #14B -define rx_amin_pg=101001100; #14C -define rx_amax_pg=101001101; #14D -define rx_amp_val_pg=101001110; #14E -define rx_amp_offset_pg=101001111; #14F -define rx_eo_convergence_pg=101010000; #150 -define rx_sls_rcvy_pg=101010001; #151 -define rx_sls_rcvy_gcrmsg_pg=101010010; #152 -define rx_tx_lane_info_gcrmsg_pg=101010011; #153 -define rx_err_tallying_gcrmsg_pg=101010100; #154 -define rx_trace_pg=101010101; #155 -define rx_rc_step_cntl_pg=101010111; #157 -define rx_eo_recal_pg=101011000; #158 -define rx_servo_ber_count_pg=101011001; #159 -define rx_func_state_pg=101011010; #15A -define rx_dyn_rpr_debug_pg=101011011; #15B -define rx_dyn_rpr_err_tallying2_pg=101011100; #15C -define rx_result_chk_pg=101011101; #15D -define rx_ber_chk_pg=101011110; #15E -define rx_sls_rcvy_fin_gcrmsg_pg=101011111; #15F -#define #rx_wiretest_pp=101100000; #160 -define rx_mode1_pp=101100001; #161 -define rx_cntl_fast_pp=101100010; #162 -define rx_dyn_recal_timeouts_pp=101101000; #168 -define rx_ber_cntl_pp=101101010; #16A -define rx_ber_mode_pp=101101011; #16B -define rx_servo_to1_pp=101101100; #16C -define rx_servo_to2_pp=101101101; #16D -define rx_servo_to3_pp=101101110; #16E -define rx_dfe_config_pp=101101111; #16F -define rx_dfe_timers_pp=101110000; #170 -define rx_reset_cfg_pp=101110001; #171 -define rx_recal_to1_pp=101110010; #172 -define rx_recal_to2_pp=101110011; #173 -define rx_recal_to3_pp=101110100; #174 -define rx_recal_cntl_pp=101110101; #175 -define rx_mode2_pp=101110110; #176 -define rx_bist_gcrmsg_pp=101110111; #177 -define rx_scope_cntl_pp=101111000; #178 -define rx_fir_reset_pb=111110000; #1F0 -define rx_fir_pb=111110001; #1F1 -define rx_fir_mask_pb=111110010; #1F2 -define rx_fir_error_inject_pb=111110011; #1F3 -define rx_fir_msg_pb=111111111; #1FF define tx_mode_pl_full_reg=48:63; #start_bit=48, number_of_bit=16 define tx_lane_pdwn=48:48; #start_bit=48, number_of_bit=1 define tx_lane_invert=49:49; #start_bit=49, number_of_bit=1 @@ -261,10 +31,8 @@ define tx_prbs_tap_id=48:50; #start_bit=48, number_of_bit=3 define tx_drv_data_pattern_gcrmsg=48:51; #start_bit=48, number_of_bit=4 define tx_drv_func_data_gcrmsg=52:52; #start_bit=52, number_of_bit=1 define tx_sls_lane_sel_gcrmsg=53:53; #start_bit=53, number_of_bit=1 -define tx_drv_sync_patt_gcrmsg=49:49; #start_bit=49, number_of_bit=1 -define tx_err_inject=48:51; #start_bit=48, number_of_bit=4 -define tx_err_inj_A_enable=52:52; #start_bit=52, number_of_bit=1 -define tx_err_inj_B_enable=53:53; #start_bit=53, number_of_bit=1 +define tx_err_inj_a_enable=52:52; #start_bit=52, number_of_bit=1 +define tx_err_inj_b_enable=53:53; #start_bit=53, number_of_bit=1 define tx_tdr_capt_val=48:48; #start_bit=48, number_of_bit=1 define tx_clk_pdwn=48:48; #start_bit=48, number_of_bit=1 define tx_clk_invert=49:49; #start_bit=49, number_of_bit=1 @@ -282,11 +50,9 @@ define tx_pg_spare_mode_7=55:55; #start_bit=55, number_of_bit=1 define tx_clk_bist_err=49:49; #start_bit=49, number_of_bit=1 define tx_clk_bist_done=51:51; #start_bit=51, number_of_bit=1 #define #tx_cntl_stat_pg_spare=48:48; #start_bit=48, number_of_bit=1 -define tx_fifo_init=49:49; #start_bit=49, number_of_bit=1 define tx_max_bad_lanes=48:52; #start_bit=48, number_of_bit=5 define tx_msbswap=53:53; #start_bit=53, number_of_bit=1 define tx_pdwn_lite_disable=54:54; #start_bit=54, number_of_bit=1 -define tx_reset_cfg_ena=48:48; #start_bit=48, number_of_bit=1 define tx_clr_par_errs=62:62; #start_bit=62, number_of_bit=1 define tx_fir_reset=63:63; #start_bit=63, number_of_bit=1 define tx_pg_fir_errs_full_reg=48:63; #start_bit=48, number_of_bit=16 @@ -376,15 +142,12 @@ define tx_enable_reduced_scramble=48:48; #start_bit=48, number_of_bit=1 define tx_reset_cfg_hld=48:63; #start_bit=48, number_of_bit=16 define tx_tdr_dac_cntl=48:55; #start_bit=48, number_of_bit=8 define tx_tdr_phase_sel=57:57; #start_bit=57, number_of_bit=1 -#define #tx_tdr_capt_val=63:63; #start_bit=63, number_of_bit=1 define tx_tdr_pulse_offset=48:59; #start_bit=48, number_of_bit=12 define tx_tdr_pulse_width=48:59; #start_bit=48, number_of_bit=12 #define #tx_zcal_spare=48:48; #start_bit=48, number_of_bit=1 -define tx_zcal_req=49:49; #start_bit=49, number_of_bit=1 define tx_zcal_done=50:50; #start_bit=50, number_of_bit=1 define tx_zcal_error=51:51; #start_bit=51, number_of_bit=1 define tx_zcal_busy=52:52; #start_bit=52, number_of_bit=1 -define tx_zcal_force_sample=53:53; #start_bit=53, number_of_bit=1 define tx_zcal_cmp_out=54:54; #start_bit=54, number_of_bit=1 define tx_zcal_sample_cnt=55:63; #start_bit=55, number_of_bit=9 define tx_zcal_n=48:56; #start_bit=48, number_of_bit=9 @@ -440,10 +203,6 @@ define rx_amp_adj_all_done_b=49:49; #start_bit=49, number_of_bit=1 #define #rx_lane_inverted=49:49; #start_bit=49, number_of_bit=1 #define #rx_lane_fault_details=52:54; #start_bit=52, number_of_bit=3 define rx_fifo_l2u_dly=48:51; #start_bit=48, number_of_bit=4 -define rx_fifo_init=52:52; #start_bit=52, number_of_bit=1 -define rx_fifo_inc_l2u_dly=48:48; #start_bit=48, number_of_bit=1 -define rx_fifo_dec_l2u_dly=49:49; #start_bit=49, number_of_bit=1 -define rx_clr_skew_valid=50:50; #start_bit=50, number_of_bit=1 #define #rx_fifo_cntl_spare=51:51; #start_bit=51, number_of_bit=1 define rx_bad_block_lock=48:48; #start_bit=48, number_of_bit=1 define rx_bad_skew=49:49; #start_bit=49, number_of_bit=1 @@ -493,8 +252,6 @@ define rx_bump_left_half_ui=48:48; #start_bit=48, number_of_bit=1 define rx_bump_right_half_ui=49:49; #start_bit=49, number_of_bit=1 define rx_bump_one_ui=50:50; #start_bit=50, number_of_bit=1 define rx_bump_two_ui=51:51; #start_bit=51, number_of_bit=1 -define rx_ext_sr=52:52; #start_bit=52, number_of_bit=1 -define rx_ext_sl=53:53; #start_bit=53, number_of_bit=1 define rx_phaserot_offset=50:55; #start_bit=50, number_of_bit=6 define rx_phaserot_val=50:55; #start_bit=50, number_of_bit=6 define rx_phaserot_ddc_complete=56:56; #start_bit=56, number_of_bit=1 @@ -506,7 +263,6 @@ define rx_phaserot_right_edge=56:61; #start_bit=56, number_of_bit=6 define rx_eye_width=50:55; #start_bit=50, number_of_bit=6 define rx_hist_min_eye_width_valid=56:56; #start_bit=56, number_of_bit=1 define rx_hist_min_eye_width=58:63; #start_bit=58, number_of_bit=6 -define rx_reset_hist_eye_width_min=48:48; #start_bit=48, number_of_bit=1 define rx_ber_count=48:55; #start_bit=48, number_of_bit=8 define rx_ber_count_saturated=56:56; #start_bit=56, number_of_bit=1 define rx_ber_count_frozen_by_lane=57:57; #start_bit=57, number_of_bit=1 @@ -531,14 +287,14 @@ define rx_pg_spare_mode_1=49:49; #start_bit=49, number_of_bit=1 define rx_pg_spare_mode_2=50:50; #start_bit=50, number_of_bit=1 define rx_pg_spare_mode_3=51:51; #start_bit=51, number_of_bit=1 define rx_pg_spare_mode_4=52:52; #start_bit=52, number_of_bit=1 -define rx_pg_spare_mode_5=53:53; #start_bit=53, number_of_bit=1 -define rx_pg_spare_mode_6=54:54; #start_bit=54, number_of_bit=1 -define rx_pg_spare_mode_7=55:55; #start_bit=55, number_of_bit=1 +#define #rx_pg_spare_mode_5=53:53; #start_bit=53, number_of_bit=1 +#define #rx_pg_spare_mode_6=54:54; #start_bit=54, number_of_bit=1 +#define #rx_pg_spare_mode_7=55:55; #start_bit=55, number_of_bit=1 +define rx_sls_extend_sel=53:55; #start_bit=53, number_of_bit=3 define rx_master_mode=48:48; #start_bit=48, number_of_bit=1 define rx_disable_fence_reset=49:49; #start_bit=49, number_of_bit=1 define rx_pdwn_lite_disable=50:50; #start_bit=50, number_of_bit=1 define rx_use_sls_as_spr=51:51; #start_bit=51, number_of_bit=1 -define rx_reset_cfg_ena=48:48; #start_bit=48, number_of_bit=1 define rx_clr_par_errs=62:62; #start_bit=62, number_of_bit=1 define rx_fir_reset=63:63; #start_bit=63, number_of_bit=1 define rx_bus_id=48:53; #start_bit=48, number_of_bit=6 @@ -771,6 +527,7 @@ define rx_gcr_msg_debug_write_data=48:63; #start_bit=48, number_of_bit=16 define rx_servo_recal_ip=48:48; #start_bit=48, number_of_bit=1 define rx_dyn_recal_main_state=50:55; #start_bit=50, number_of_bit=6 define rx_dyn_recal_hndshk_state=57:63; #start_bit=57, number_of_bit=7 +#define #rx_eye_opt_state=48:55; #start_bit=48, number_of_bit=8 define rx_eye_opt_state=48:55; #start_bit=48, number_of_bit=8 define rx_recal_state=56:63; #start_bit=56, number_of_bit=8 define rx_wt_clk_lane_inverted=49:49; #start_bit=49, number_of_bit=1 @@ -849,7 +606,6 @@ define rx_tx_bad_lane_cntr_gcrmsg=48:49; #start_bit=48, number_of_bit=2 define rx_dis_synd_tallying_gcrmsg=48:48; #start_bit=48, number_of_bit=1 define rx_trc_mode=48:51; #start_bit=48, number_of_bit=4 define rx_trc_grp=54:59; #start_bit=54, number_of_bit=6 -define rx_dyn_rpr_bad_lane_valid_debug=48:48; #start_bit=48, number_of_bit=1 define rx_dyn_rpr_enc_bad_data_lane_debug=49:55; #start_bit=49, number_of_bit=7 define rx_bad_bus_err_cntr=57:63; #start_bit=57, number_of_bit=7 define rx_bad_bus_lane_err_cntr_dis_clr=48:48; #start_bit=48, number_of_bit=1 @@ -863,7 +619,6 @@ define rx_min_eye_height=56:63; #start_bit=56, number_of_bit=8 define rx_max_ber_check_count=56:63; #start_bit=56, number_of_bit=8 define rx_stop_state_enable=48:48; #start_bit=48, number_of_bit=1 define rx_state_stopped=49:49; #start_bit=49, number_of_bit=1 -define rx_resume_from_stop=50:50; #start_bit=50, number_of_bit=1 define rx_stop_addr_msb=56:59; #start_bit=56, number_of_bit=4 define rx_stop_mask_msb=60:63; #start_bit=60, number_of_bit=4 define rx_stop_addr_lsb=48:63; #start_bit=48, number_of_bit=16 @@ -892,31 +647,29 @@ define rx_pp_trc_mode=48:50; #start_bit=48, number_of_bit=3 define rx_bist_jitter_pulse_sel=51:52; #start_bit=51, number_of_bit=2 define rx_bist_min_eye_width=54:59; #start_bit=54, number_of_bit=6 define rx_wt_pattern_length=61:62; #start_bit=61, number_of_bit=2 -define rx_servo_timeout_sel_A=48:51; #start_bit=48, number_of_bit=4 -define rx_servo_timeout_sel_B=52:55; #start_bit=52, number_of_bit=4 -define rx_servo_timeout_sel_C=56:59; #start_bit=56, number_of_bit=4 -define rx_servo_timeout_sel_D=60:63; #start_bit=60, number_of_bit=4 -define rx_servo_timeout_sel_E=48:51; #start_bit=48, number_of_bit=4 -define rx_servo_timeout_sel_F=52:55; #start_bit=52, number_of_bit=4 -define rx_servo_timeout_sel_G=56:59; #start_bit=56, number_of_bit=4 -define rx_servo_timeout_sel_H=60:63; #start_bit=60, number_of_bit=4 -define rx_servo_timeout_sel_I=48:51; #start_bit=48, number_of_bit=4 -define rx_servo_timeout_sel_J=52:55; #start_bit=52, number_of_bit=4 -define rx_servo_timeout_sel_K=56:59; #start_bit=56, number_of_bit=4 -define rx_servo_timeout_sel_L=60:63; #start_bit=60, number_of_bit=4 -define rx_recal_timeout_sel_A=48:51; #start_bit=48, number_of_bit=4 -define rx_recal_timeout_sel_B=52:55; #start_bit=52, number_of_bit=4 -define rx_recal_timeout_sel_G=56:59; #start_bit=56, number_of_bit=4 -define rx_recal_timeout_sel_H=60:63; #start_bit=60, number_of_bit=4 -define rx_recal_timeout_sel_I=48:51; #start_bit=48, number_of_bit=4 -define rx_recal_timeout_sel_J=52:55; #start_bit=52, number_of_bit=4 -define rx_recal_timeout_sel_K=56:59; #start_bit=56, number_of_bit=4 -define rx_recal_timeout_sel_L=60:63; #start_bit=60, number_of_bit=4 +define rx_servo_timeout_sel_a=48:51; #start_bit=48, number_of_bit=4 +define rx_servo_timeout_sel_b=52:55; #start_bit=52, number_of_bit=4 +define rx_servo_timeout_sel_c=56:59; #start_bit=56, number_of_bit=4 +define rx_servo_timeout_sel_d=60:63; #start_bit=60, number_of_bit=4 +define rx_servo_timeout_sel_e=48:51; #start_bit=48, number_of_bit=4 +define rx_servo_timeout_sel_f=52:55; #start_bit=52, number_of_bit=4 +define rx_servo_timeout_sel_g=56:59; #start_bit=56, number_of_bit=4 +define rx_servo_timeout_sel_h=60:63; #start_bit=60, number_of_bit=4 +define rx_servo_timeout_sel_i=48:51; #start_bit=48, number_of_bit=4 +define rx_servo_timeout_sel_j=52:55; #start_bit=52, number_of_bit=4 +define rx_servo_timeout_sel_k=56:59; #start_bit=56, number_of_bit=4 +define rx_servo_timeout_sel_l=60:63; #start_bit=60, number_of_bit=4 +define rx_recal_timeout_sel_a=48:51; #start_bit=48, number_of_bit=4 +define rx_recal_timeout_sel_b=52:55; #start_bit=52, number_of_bit=4 +define rx_recal_timeout_sel_g=56:59; #start_bit=56, number_of_bit=4 +define rx_recal_timeout_sel_h=60:63; #start_bit=60, number_of_bit=4 +define rx_recal_timeout_sel_i=48:51; #start_bit=48, number_of_bit=4 +define rx_recal_timeout_sel_j=52:55; #start_bit=52, number_of_bit=4 +define rx_recal_timeout_sel_k=56:59; #start_bit=56, number_of_bit=4 +define rx_recal_timeout_sel_l=60:63; #start_bit=60, number_of_bit=4 #define #rx_block_lock=48:48; #start_bit=48, number_of_bit=1 define rx_prbs_check_sync=49:49; #start_bit=49, number_of_bit=1 define rx_enable_reduced_scramble=50:50; #start_bit=50, number_of_bit=1 -define rx_prbs_inc=51:51; #start_bit=51, number_of_bit=1 -define rx_prbs_dec=52:52; #start_bit=52, number_of_bit=1 define rx_recal_in_progress=48:48; #start_bit=48, number_of_bit=1 define rx_dyn_recal_interval_timeout_sel=49:51; #start_bit=49, number_of_bit=3 define rx_dyn_recal_status_rpt_timeout_sel=52:53; #start_bit=52, number_of_bit=2 @@ -935,18 +688,14 @@ define rx_dac_bo_cfg=58:60; #start_bit=58, number_of_bit=3 define rx_prot_cfg=61:62; #start_bit=61, number_of_bit=2 define rx_reset_cfg_hld=48:63; #start_bit=48, number_of_bit=16 define rx_scope_control=48:49; #start_bit=48, number_of_bit=2 -define rx_bump_scope=50:50; #start_bit=50, number_of_bit=1 define rx_bist_en=48:48; #start_bit=48, number_of_bit=1 define rx_ber_en=48:48; #start_bit=48, number_of_bit=1 -define rx_ber_count_clr=49:49; #start_bit=49, number_of_bit=1 -define rx_ber_timer_clr=50:50; #start_bit=50, number_of_bit=1 define rx_ber_timer_freeze_en=48:48; #start_bit=48, number_of_bit=1 define rx_ber_count_freeze_en=49:49; #start_bit=49, number_of_bit=1 define rx_ber_count_sel=51:53; #start_bit=51, number_of_bit=3 define rx_ber_timer_sel=54:56; #start_bit=54, number_of_bit=3 define rx_ber_clr_count_on_read_en=57:57; #start_bit=57, number_of_bit=1 define rx_ber_clr_timer_on_read_en=58:58; #start_bit=58, number_of_bit=1 -define rx_fir_msg=48:55; #start_bit=48, number_of_bit=8 define rx_pb_clr_par_errs=62:62; #start_bit=62, number_of_bit=1 define rx_pb_fir_reset=63:63; #start_bit=63, number_of_bit=1 define rx_pb_fir_errs_full_reg=48:57; #start_bit=48, number_of_bit=10 @@ -985,6 +734,226 @@ define rx_pb_fir_err_inj_gcrs_ld_sm2=54:54; #start_bit=54, number_of_bit=1 define rx_pb_fir_err_inj_gcrs_unld_sm0=55:55; #start_bit=55, number_of_bit=1 define rx_pb_fir_err_inj_gcrs_unld_sm1=56:56; #start_bit=56, number_of_bit=1 define rx_pb_fir_err_inj_gcrs_unld_sm2=57:57; #start_bit=57, number_of_bit=1 +define tx_mode_pl=010000000; #080 +define tx_cntl_stat_pl=010000001; #081 +define tx_spare_mode_pl=010000010; #082 +#define #tx_id_pl=010000100; #084 +define tx_bist_stat_pl=010000101; #085 +define tx_prbs_mode_pl=010000110; #086 +define tx_data_cntl_gcrmsg_pl=010000111; #087 +define tx_sync_pattern_gcrmsg_pl=010001000; #088 +define tx_fir_pl=010001010; #08A +define tx_fir_mask_pl=010001011; #08B +define tx_fir_error_inject_pl=010001100; #08C +define tx_mode_fast_pl=010001101; #08D +define tx_tdr_stat_pl=010001110; #08E +define tx_cntl_gcrmsg_pl=010001111; #08F +define tx_clk_mode_pg=110000000; #180 +define tx_spare_mode_pg=110000001; #181 +define tx_cntl_stat_pg=110000010; #182 +define tx_mode_pg=110000011; #183 +define tx_reset_act_pg=110001000; #188 +define tx_bist_stat_pg=110001001; #189 +define tx_fir_pg=110001010; #18A +define tx_fir_mask_pg=110001011; #18B +define tx_fir_error_inject_pg=110001100; #18C +define tx_id1_pg=110010010; #192 +define tx_id2_pg=110010011; #193 +define tx_id3_pg=110010100; #194 +define tx_clk_cntl_gcrmsg_pg=110011000; #198 +define tx_ffe_mode_pg=110011001; #199 +define tx_ffe_main_pg=110011010; #19A +define tx_ffe_post_pg=110011011; #19B +define tx_ffe_margin_pg=110011100; #19C +define tx_bad_lane_enc_gcrmsg_pg=110011101; #19D +define tx_ber_cntl_pg=110011110; #19E +define tx_sls_lane_enc_gcrmsg_pg=110011111; #19F +define tx_wt_seg_enable_pg=110100000; #1A0 +define tx_lane_disabled_vec_0_15_pg=110100011; #1A3 +define tx_lane_disabled_vec_16_31_pg=110100100; #1A4 +define tx_sls_lane_mux_gcrmsg_pg=110100101; #1A5 +define tx_dyn_rpr_pg=110100110; #1A6 +define tx_slv_mv_sls_ln_req_gcrmsg_pg=110100111; #1A7 +define tx_wiretest_pp=111010000; #1D0 +define tx_mode_pp=111010001; #1D1 +define tx_sls_gcrmsg_pp=111010010; #1D2 +define tx_ber_cntl_a_pp=111010011; #1D3 +define tx_ber_cntl_b_pp=111010100; #1D4 +define tx_dyn_recal_timeouts_pp=111010101; #1D5 +define tx_bist_cntl_pp=111010110; #1D6 +define tx_ber_cntl_sls_pp=111010111; #1D7 +define tx_cntl_pp=111011000; #1D8 +define tx_reset_cfg_pp=111011001; #1D9 +define tx_tdr_cntl1_pp=111011010; #1DA +define tx_tdr_cntl2_pp=111011011; #1DB +define tx_tdr_cntl3_pp=111011100; #1DC +define tx_impcal_pb=111100000; #1E0 +define tx_impcal_nval_pb=111100001; #1E1 +define tx_impcal_pval_pb=111100010; #1E2 +define tx_impcal_p_4x_pb=111100011; #1E3 +define tx_impcal_swo1_pb=111100100; #1E4 +define tx_impcal_swo2_pb=111100101; #1E5 +define tx_analog_iref_pb=111100110; #1E6 +define tx_minikerf_pb=111100111; #1E7 +define tx_init_version_pb=111101000; #1E8 +define tx_scratch_reg_pb=111101001; #1E9 +define rx_mode_pl=000000000; #000 +define rx_cntl_pl=000000001; #001 +define rx_spare_mode_pl=000000010; #002 +define rx_prot_edge_status_pl=000000011; #003 +#define #rx_prot_gb_status_pl=000000100; #004 +define rx_bist_stat_pl=000000101; #005 +#define #rx_eyeopt_stat_pl=000000111; #007 +define rx_offset_even_pl=000001000; #008 +define rx_offset_odd_pl=000001001; #009 +define rx_amp_val_pl=000001010; #00A +define rx_amp_cntl_pl=000001011; #00B +define rx_prot_status_pl=000001100; #00C +define rx_prot_mode_pl=000001101; #00D +define rx_prot_cntl_pl=000001110; #00E +#define #rx_wiretest_stat_pl=000001110; #00E +define rx_fifo_stat_pl=000001111; #00F +define rx_ap_pl =000010000; #010 +define rx_an_pl =000010001; #011 +define rx_amin_pl=000010010; #012 +define rx_h1_even_pl=000010011; #013 +define rx_h1_odd_pl=000010100; #014 +define rx_prbs_mode_pl=000010110; #016 +define rx_stat_pl=000011000; #018 +define rx_deskew_stat_pl=000011001; #019 +define rx_fir_pl=000011010; #01A +define rx_fir_mask_pl=000011011; #01B +define rx_fir_error_inject_pl=000011100; #01C +define rx_sls_pl=000011101; #01D +define rx_wt_status_pl=000011110; #01E +define rx_fifo_cntl_pl=000011111; #01F +define rx_ber_status_pl=000100000; #020 +define rx_ber_timer_0_15_pl=000100001; #021 +define rx_ber_timer_16_31_pl=000100010; #022 +define rx_ber_timer_32_39_pl=000100011; #023 +define rx_servo_cntl_pl=000100100; #024 +define rx_fifo_diag_0_15_pl=000100101; #025 +define rx_fifo_diag_16_31_pl=000100110; #026 +define rx_fifo_diag_32_47_pl=000100111; #027 +define rx_eye_width_status_pl=000101000; #028 +define rx_eye_width_cntl_pl=000101001; #029 +define rx_dfe_clkadj_pl=000101010; #02A +define rx_trace_pl=000101011; #02B +define rx_servo_ber_count_pl=000101100; #02C +define rx_eye_opt_stat_pl=000101101; #02D +define rx_clk_mode_pg=100000000; #100 +define rx_spare_mode_pg=100000001; #101 +define rx_stop_cntl_stat_pg=100000010; #102 +define rx_mode_pg=100000011; #103 +define rx_stop_addr_lsb_pg=100000111; #107 +define rx_stop_mask_lsb_pg=100001000; #108 +define rx_reset_act_pg=100001001; #109 +define rx_id1_pg=100001010; #10A +define rx_id2_pg=100001011; #10B +define rx_id3_pg=100001100; #10C +define rx_minikerf_pg=100001101; #10D +define rx_dyn_rpr_debug2_pg=100001110; #10E +define rx_sls_mode_pg=100001111; #10F +define rx_training_start_pg=100010000; #110 +define rx_training_status_pg=100010001; #111 +define rx_recal_status_pg=100010010; #112 +define rx_timeout_sel_pg=100010011; #113 +define rx_fifo_mode_pg=100010100; #114 +#define #rx_state_debug_pg=100010101; #115 +#define #rx_state_val_pg=100010110; #116 +define rx_sls_status_pg=100010111; #117 +define rx_fir1_pg=100011010; #11A +define rx_fir2_pg=100011011; #11B +define rx_fir1_mask_pg=100011100; #11C +define rx_fir2_mask_pg=100011101; #11D +define rx_fir1_error_inject_pg=100011110; #11E +define rx_fir2_error_inject_pg=100011111; #11F +define rx_fir_training_pg=100100000; #120 +define rx_fir_training_mask_pg=100100001; #121 +define rx_timeout_sel1_pg=100100010; #122 +define rx_lane_bad_vec_0_15_pg=100100011; #123 +define rx_lane_bad_vec_16_31_pg=100100100; #124 +define rx_lane_disabled_vec_0_15_pg=100100101; #125 +define rx_lane_disabled_vec_16_31_pg=100100110; #126 +define rx_lane_swapped_vec_0_15_pg=100100111; #127 +define rx_lane_swapped_vec_16_31_pg=100101000; #128 +define rx_init_state_pg=100101001; #129 +define rx_wiretest_state_pg=100101010; #12A +define rx_wiretest_laneinfo_pg=100101011; #12B +define rx_wiretest_gcrmsgs_pg=100101100; #12C +define rx_deskew_gcrmsgs_pg=100101101; #12D +define rx_deskew_state_pg=100101110; #12E +define rx_deskew_mode_pg=100101111; #12F +define rx_deskew_status_pg=100110000; #130 +define rx_bad_lane_enc_gcrmsg_pg=100110001; #131 +define rx_static_repair_state_pg=100110010; #132 +define rx_tx_bus_info_pg=100110011; #133 +define rx_sls_lane_enc_gcrmsg_pg=100110100; #134 +define rx_fence_pg=100110101; #135 +define rx_timeout_sel2_pg=100110111; #137 +define rx_misc_analog_pg=100111000; #138 +define rx_dyn_rpr_pg=100111001; #139 +define rx_dyn_rpr_gcrmsg_pg=100111010; #13A +define rx_dyn_rpr_err_tallying1_pg=100111011; #13B +define rx_eo_final_l2u_gcrmsgs_pg=100111100; #13C +define rx_gcr_msg_debug_dest_ids_pg=100111101; #13D +define rx_gcr_msg_debug_src_ids_pg=100111110; #13E +define rx_gcr_msg_debug_dest_addr_pg=100111111; #13F +define rx_gcr_msg_debug_write_data_pg=101000000; #140 +define rx_dyn_recal_pg=101000001; #141 +define rx_wt_clk_status_pg=101000010; #142 +define rx_dyn_recal_config_pg=101000011; #143 +define rx_wt_config_pg=101000100; #144 +define rx_dyn_recal_gcrmsg_pg=101000101; #145 +define rx_wiretest_pll_cntl_pg=101000110; #146 +define rx_eo_step_cntl_pg=101000111; #147 +define rx_eo_step_stat_pg=101001000; #148 +define rx_eo_step_fail_pg=101001001; #149 +define rx_ap_pg =101001010; #14A +define rx_an_pg =101001011; #14B +define rx_amin_pg=101001100; #14C +define rx_amax_pg=101001101; #14D +define rx_amp_val_pg=101001110; #14E +define rx_amp_offset_pg=101001111; #14F +define rx_eo_convergence_pg=101010000; #150 +define rx_sls_rcvy_pg=101010001; #151 +define rx_sls_rcvy_gcrmsg_pg=101010010; #152 +define rx_tx_lane_info_gcrmsg_pg=101010011; #153 +define rx_err_tallying_gcrmsg_pg=101010100; #154 +define rx_trace_pg=101010101; #155 +define rx_rc_step_cntl_pg=101010111; #157 +define rx_eo_recal_pg=101011000; #158 +define rx_servo_ber_count_pg=101011001; #159 +define rx_func_state_pg=101011010; #15A +define rx_dyn_rpr_debug_pg=101011011; #15B +define rx_dyn_rpr_err_tallying2_pg=101011100; #15C +define rx_result_chk_pg=101011101; #15D +define rx_ber_chk_pg=101011110; #15E +define rx_sls_rcvy_fin_gcrmsg_pg=101011111; #15F +#define #rx_wiretest_pp=101100000; #160 +define rx_mode1_pp=101100001; #161 +define rx_cntl_fast_pp=101100010; #162 +define rx_dyn_recal_timeouts_pp=101101000; #168 +define rx_ber_cntl_pp=101101010; #16A +define rx_ber_mode_pp=101101011; #16B +define rx_servo_to1_pp=101101100; #16C +define rx_servo_to2_pp=101101101; #16D +define rx_servo_to3_pp=101101110; #16E +define rx_dfe_config_pp=101101111; #16F +define rx_dfe_timers_pp=101110000; #170 +define rx_reset_cfg_pp=101110001; #171 +define rx_recal_to1_pp=101110010; #172 +define rx_recal_to2_pp=101110011; #173 +define rx_recal_to3_pp=101110100; #174 +define rx_recal_cntl_pp=101110101; #175 +define rx_mode2_pp=101110110; #176 +define rx_bist_gcrmsg_pp=101110111; #177 +define rx_scope_cntl_pp=101111000; #178 +define rx_fir_reset_pb=111110000; #1F0 +define rx_fir_pb=111110001; #1F1 +define rx_fir_mask_pb=111110010; #1F2 +define rx_fir_error_inject_pb=111110011; #1F3 +define rx_fir_msg_pb=111111111; #1FF define abus_gcr_addr=08010C3F; define dmi0_gcr_addr=02011A3F; define dmi1_gcr_addr=02011E3F; @@ -997,7 +966,7 @@ define tx_grp0=100000; # 0x20 define tx_grp1=100001; # 0x21 define tx_grp2=100010; # 0x22 define tx_grp3=100011; # 0x23 -define lane_na=00000; # 0x00 +define lane_na=00000; # 0x00 define lane_0=00000; define lane_1=00001; define lane_2=00010; @@ -1038,4 +1007,3 @@ define tx_prbs_tap_id_pattern_e=0b100; define tx_prbs_tap_id_pattern_f=0b101; define tx_prbs_tap_id_pattern_g=0b110; define tx_prbs_tap_id_pattern_h=0b111; - diff --git a/src/usr/hwpf/hwp/initfiles/ei4.io.define b/src/usr/hwpf/hwp/initfiles/ei4.io.define index 1a74e4180..3a5e629cb 100644 --- a/src/usr/hwpf/hwp/initfiles/ei4.io.define +++ b/src/usr/hwpf/hwp/initfiles/ei4.io.define @@ -1,215 +1,3 @@ -#-- $Id: ei4.io.define,v 1.2 2012/08/01 05:31:17 thomsen Exp $ -#-- CHANGE HISTORY: -#-------------------------------------------------------------------------------- -#-- Version:|Author: | Date: | Comment: -#-- --------|--------|--------|-------------------------------------------------- -#-- 1.1 |pmegan |07/10/12|Created initial version -#-- --------|--------|--------|-------------------------------------------------- -#-------------------------------------------------------------------------------- -# End of revision history -#-------------------------------------------------------------------------------- -define tx_mode_pl=010000000; #080 -define tx_cntl_stat_pl=010000001; #081 -define tx_spare_mode_pl=010000010; #082 -#define #tx_id_pl=010000100; #084 -define tx_bist_stat_pl=010000101; #085 -define tx_prbs_mode_pl=010000110; #086 -define tx_data_cntl_gcrmsg_pl=010000111; #087 -define tx_sync_pattern_gcrmsg_pl=010001000; #088 -define tx_fir_pl=010001010; #08A -define tx_fir_mask_pl=010001011; #08B -define tx_fir_error_inject_pl=010001100; #08C -define tx_mode_fast_pl=010001101; #08D -define tx_clk_mode_pg=110000000; #180 -define tx_spare_mode_pg=110000001; #181 -define tx_cntl_stat_pg=110000010; #182 -define tx_mode_pg=110000011; #183 -define tx_reset_act_pg=110001000; #188 -define tx_bist_stat_pg=110001001; #189 -define tx_fir_pg=110001010; #18A -define tx_fir_mask_pg=110001011; #18B -define tx_fir_error_inject_pg=110001100; #18C -define tx_id1_pg=110010010; #192 -define tx_id2_pg=110010011; #193 -define tx_id3_pg=110010100; #194 -define tx_clk_cntl_gcrmsg_pg=110011000; #198 -define tx_bad_lane_enc_gcrmsg_pg=110011101; #19D -define tx_ber_cntl_pg=110011110; #19E -define tx_sls_lane_enc_gcrmsg_pg=110011111; #19F -define tx_wt_seg_enable_pg=110100000; #1A0 -#define #tx_term_pg=110100000; #1A0 -define tx_pc_ffe_pg=110100001; #1A1 -define tx_misc_analog_pg=110100010; #1A2 -define tx_lane_disabled_vec_0_15_pg=110100011; #1A3 -define tx_lane_disabled_vec_16_31_pg=110100100; #1A4 -define tx_sls_lane_mux_gcrmsg_pg=110100101; #1A5 -define tx_dyn_rpr_pg=110100110; #1A6 -define tx_slv_mv_sls_ln_req_gcrmsg_pg=110100111; #1A7 -define tx_rdt_cntl_pg=110101000; #1A8 -define rx_dll_cal_cntl_pg=111000111; #1C7 -define rx_dll1_setpoint1_pg=111001000; #1C8 -define rx_dll1_setpoint2_pg=111001001; #1C9 -define rx_dll1_setpoint3_pg=111001010; #1CA -define rx_dll2_setpoint1_pg=111001011; #1CB -define rx_dll2_setpoint2_pg=111001100; #1CC -define rx_dll2_setpoint3_pg=111001101; #1CD -define rx_dll_filter_mode_pg=111001110; #1CE -define rx_dll_analog_tweaks_pg=111001111; #1CF -define tx_wiretest_pp=111010000; #1D0 -define tx_mode_pp=111010001; #1D1 -define tx_sls_gcrmsg_pp=111010010; #1D2 -define tx_ber_cntl_a_pp=111010011; #1D3 -define tx_ber_cntl_b_pp=111010100; #1D4 -define tx_bist_cntl_pp=111010110; #1D6 -define tx_ber_cntl_sls_pp=111010111; #1D7 -define tx_cntl_pp=111011000; #1D8 -define tx_reset_cfg_pp=111011001; #1D9 -define tx_tdr_cntl2_pp=111011011; #1DB -define tx_tdr_cntl3_pp=111011100; #1DC -define tx_init_version_pb=111101000; #1E8 -define tx_scratch_reg_pb=111101001; #1E9 -define rx_mode_pl=000000000; #000 -define rx_cntl_pl=000000001; #001 -define rx_spare_mode_pl=000000010; #002 -define rx_prot_edge_status_pl=000000011; #003 -#define #rx_prot_gb_status_pl=000000100; #004 -define rx_bist_stat_pl=000000101; #005 -#define ##rx_eyeopt_mode_pl=000000110; #006 -#define #rx_eyeopt_stat_pl=000000111; #007 -define rx_offset_even_pl=000001000; #008 -define rx_offset_odd_pl=000001001; #009 -define rx_amp_val_pl=000001010; #00A -define rx_prot_status_pl=000001100; #00C -define rx_prot_mode_pl=000001101; #00D -define rx_prot_cntl_pl=000001110; #00E -#define #rx_wiretest_stat_pl=000001110; #00E -define rx_fifo_stat_pl=000001111; #00F -define rx_prbs_mode_pl=000010110; #016 -define rx_vref_pl=000010111; #017 -define rx_stat_pl=000011000; #018 -define rx_deskew_stat_pl=000011001; #019 -define rx_fir_pl=000011010; #01A -define rx_fir_mask_pl=000011011; #01B -define rx_fir_error_inject_pl=000011100; #01C -define rx_sls_pl=000011101; #01D -define rx_wt_status_pl=000011110; #01E -define rx_fifo_cntl_pl=000011111; #01F -define rx_ber_status_pl=000100000; #020 -define rx_ber_timer_0_15_pl=000100001; #021 -define rx_ber_timer_16_31_pl=000100010; #022 -define rx_ber_timer_32_39_pl=000100011; #023 -define rx_servo_cntl_pl=000100100; #024 -define rx_fifo_diag_0_15_pl=000100101; #025 -define rx_fifo_diag_16_31_pl=000100110; #026 -define rx_fifo_diag_32_47_pl=000100111; #027 -define rx_eye_width_status_pl=000101000; #028 -define rx_eye_width_cntl_pl=000101001; #029 -define rx_trace_pl=000101011; #02B -define rx_servo_ber_count_pl=000101100; #02C -define rx_eye_opt_stat_pl=000101101; #02D -define rx_clk_mode_pg=100000000; #100 -define rx_spare_mode_pg=100000001; #101 -define rx_stop_cntl_stat_pg=100000010; #102 -define rx_mode_pg=100000011; #103 -define rx_stop_addr_lsb_pg=100000111; #107 -define rx_stop_mask_lsb_pg=100001000; #108 -define rx_reset_act_pg=100001001; #109 -define rx_id1_pg=100001010; #10A -define rx_id2_pg=100001011; #10B -define rx_id3_pg=100001100; #10C -define rx_dyn_rpr_debug2_pg=100001110; #10E -define rx_sls_mode_pg=100001111; #10F -define rx_training_start_pg=100010000; #110 -define rx_training_status_pg=100010001; #111 -define rx_recal_status_pg=100010010; #112 -define rx_timeout_sel_pg=100010011; #113 -define rx_fifo_mode_pg=100010100; #114 -#define #rx_state_debug_pg=100010101; #115 -#define #rx_state_val_pg=100010110; #116 -define rx_sls_status_pg=100010111; #117 -define rx_fir1_pg=100011010; #11A -define rx_fir2_pg=100011011; #11B -define rx_fir1_mask_pg=100011100; #11C -define rx_fir2_mask_pg=100011101; #11D -define rx_fir1_error_inject_pg=100011110; #11E -define rx_fir2_error_inject_pg=100011111; #11F -define rx_fir_training_pg=100100000; #120 -define rx_fir_training_mask_pg=100100001; #121 -define rx_timeout_sel1_pg=100100010; #122 -define rx_lane_bad_vec_0_15_pg=100100011; #123 -define rx_lane_bad_vec_16_31_pg=100100100; #124 -define rx_lane_disabled_vec_0_15_pg=100100101; #125 -define rx_lane_disabled_vec_16_31_pg=100100110; #126 -define rx_lane_swapped_vec_0_15_pg=100100111; #127 -define rx_lane_swapped_vec_16_31_pg=100101000; #128 -define rx_init_state_pg=100101001; #129 -define rx_wiretest_state_pg=100101010; #12A -define rx_wiretest_laneinfo_pg=100101011; #12B -define rx_wiretest_gcrmsgs_pg=100101100; #12C -define rx_deskew_gcrmsgs_pg=100101101; #12D -define rx_deskew_state_pg=100101110; #12E -define rx_deskew_mode_pg=100101111; #12F -define rx_deskew_status_pg=100110000; #130 -define rx_bad_lane_enc_gcrmsg_pg=100110001; #131 -define rx_static_repair_state_pg=100110010; #132 -define rx_tx_bus_info_pg=100110011; #133 -define rx_sls_lane_enc_gcrmsg_pg=100110100; #134 -define rx_fence_pg=100110101; #135 -define rx_term_pg=100110110; #136 -define rx_timeout_sel2_pg=100110111; #137 -define rx_misc_analog_pg=100111000; #138 -define rx_dyn_rpr_pg=100111001; #139 -define rx_dyn_rpr_gcrmsg_pg=100111010; #13A -define rx_dyn_rpr_err_tallying1_pg=100111011; #13B -define rx_eo_final_l2u_gcrmsgs_pg=100111100; #13C -define rx_gcr_msg_debug_dest_ids_pg=100111101; #13D -define rx_gcr_msg_debug_src_ids_pg=100111110; #13E -define rx_gcr_msg_debug_dest_addr_pg=100111111; #13F -define rx_gcr_msg_debug_write_data_pg=101000000; #140 -define rx_wt_clk_status_pg=101000010; #142 -define rx_wt_config_pg=101000100; #144 -define rx_wiretest_pll_cntl_pg=101000110; #146 -define rx_eo_step_cntl_pg=101000111; #147 -define rx_eo_step_stat_pg=101001000; #148 -define rx_eo_step_fail_pg=101001001; #149 -define rx_amp_val_pg=101001110; #14E -define rx_sls_rcvy_pg=101010001; #151 -define rx_sls_rcvy_gcrmsg_pg=101010010; #152 -define rx_tx_lane_info_gcrmsg_pg=101010011; #153 -define rx_err_tallying_gcrmsg_pg=101010100; #154 -define rx_trace_pg=101010101; #155 -define rx_rdt_cntl_pg=101010110; #156 -define rx_rc_step_cntl_pg=101010111; #157 -define rx_eo_recal_pg=101011000; #158 -define rx_servo_ber_count_pg=101011001; #159 -define rx_func_state_pg=101011010; #15A -define rx_dyn_rpr_debug_pg=101011011; #15B -define rx_dyn_rpr_err_tallying2_pg=101011100; #15C -define rx_result_chk_pg=101011101; #15D -define rx_sls_rcvy_fin_gcrmsg_pg=101011111; #15F -#define #rx_wiretest_pp=101100000; #160 -define rx_mode1_pp=101100001; #161 -define rx_cntl_fast_pp=101100010; #162 -define rx_ei4_cal_cntl_pp=101100011; #163 -define rx_ei4_cal_inc_a_d_pp=101100100; #164 -define rx_ei4_cal_inc_e_h_pp=101100101; #165 -define rx_ei4_cal_dec_a_d_pp=101100110; #166 -define rx_ei4_cal_dec_e_h_pp=101100111; #167 -define rx_ber_cntl_pp=101101010; #16A -define rx_ber_mode_pp=101101011; #16B -define rx_servo_to1_pp=101101100; #16C -define rx_servo_to2_pp=101101101; #16D -define rx_reset_cfg_pp=101110001; #171 -define rx_recal_to1_pp=101110010; #172 -define rx_recal_to2_pp=101110011; #173 -define rx_recal_cntl_pp=101110101; #175 -define rx_mode2_pp=101110110; #176 -define rx_bist_gcrmsg_pp=101110111; #177 -define rx_fir_reset_pb=111110000; #1F0 -define rx_fir_pb=111110001; #1F1 -define rx_fir_mask_pb=111110010; #1F2 -define rx_fir_error_inject_pb=111110011; #1F3 -define rx_fir_msg_pb=111111111; #1FF define tx_mode_pl_full_reg=48:63; #start_bit=48, number_of_bit=16 define tx_lane_pdwn=48:48; #start_bit=48, number_of_bit=1 define tx_lane_invert=49:49; #start_bit=49, number_of_bit=1 @@ -241,10 +29,8 @@ define tx_prbs_tap_id=48:50; #start_bit=48, number_of_bit=3 define tx_drv_data_pattern_gcrmsg=48:51; #start_bit=48, number_of_bit=4 define tx_drv_func_data_gcrmsg=52:52; #start_bit=52, number_of_bit=1 define tx_sls_lane_sel_gcrmsg=53:53; #start_bit=53, number_of_bit=1 -define tx_drv_sync_patt_gcrmsg=49:49; #start_bit=49, number_of_bit=1 -define tx_err_inject=48:51; #start_bit=48, number_of_bit=4 -define tx_err_inj_A_enable=52:52; #start_bit=52, number_of_bit=1 -define tx_err_inj_B_enable=53:53; #start_bit=53, number_of_bit=1 +define tx_err_inj_a_enable=52:52; #start_bit=52, number_of_bit=1 +define tx_err_inj_b_enable=53:53; #start_bit=53, number_of_bit=1 define tx_clk_pdwn=48:48; #start_bit=48, number_of_bit=1 define tx_clk_invert=49:49; #start_bit=49, number_of_bit=1 define tx_clk_quiesce_p=50:51; #start_bit=50, number_of_bit=2 @@ -260,10 +46,8 @@ define tx_pg_spare_mode_7=55:55; #start_bit=55, number_of_bit=1 define tx_clk_bist_err=48:49; #start_bit=48, number_of_bit=2 define tx_clk_bist_done=50:51; #start_bit=50, number_of_bit=2 #define #tx_cntl_stat_pg_spare=48:48; #start_bit=48, number_of_bit=1 -define tx_fifo_init=49:49; #start_bit=49, number_of_bit=1 define tx_max_bad_lanes=48:52; #start_bit=48, number_of_bit=5 define tx_msbswap=53:53; #start_bit=53, number_of_bit=1 -define tx_reset_cfg_ena=48:48; #start_bit=48, number_of_bit=1 define tx_clr_par_errs=62:62; #start_bit=62, number_of_bit=1 define tx_fir_reset=63:63; #start_bit=63, number_of_bit=1 define tx_pg_fir_errs_full_reg=48:63; #start_bit=48, number_of_bit=16 @@ -393,10 +177,6 @@ define rx_amp_peak=48:53; #start_bit=48, number_of_bit=6 #define #rx_lane_inverted=49:49; #start_bit=49, number_of_bit=1 #define #rx_lane_fault_details=52:54; #start_bit=52, number_of_bit=3 define rx_fifo_l2u_dly=48:51; #start_bit=48, number_of_bit=4 -define rx_fifo_init=52:52; #start_bit=52, number_of_bit=1 -define rx_fifo_inc_l2u_dly=48:48; #start_bit=48, number_of_bit=1 -define rx_fifo_dec_l2u_dly=49:49; #start_bit=49, number_of_bit=1 -define rx_clr_skew_valid=50:50; #start_bit=50, number_of_bit=1 #define #rx_fifo_cntl_spare=51:51; #start_bit=51, number_of_bit=1 define rx_bad_block_lock=48:48; #start_bit=48, number_of_bit=1 define rx_bad_skew=49:49; #start_bit=49, number_of_bit=1 @@ -427,9 +207,6 @@ define rx_wt_lane_disabled=48:48; #start_bit=48, number_of_bit=1 define rx_wt_lane_inverted=49:49; #start_bit=49, number_of_bit=1 define rx_wt_lane_bad_code=50:52; #start_bit=50, number_of_bit=3 define rx_wt_lane_status_alias=49:52; #start_bit=49, number_of_bit=4 -#define #rx_prot_cntl_pl_dummy=48:48; #start_bit=48, number_of_bit=1 -define rx_ext_sr=52:52; #start_bit=52, number_of_bit=1 -define rx_ext_sl=53:53; #start_bit=53, number_of_bit=1 define rx_phaserot_offset=49:55; #start_bit=49, number_of_bit=7 define rx_phaserot_val=49:55; #start_bit=49, number_of_bit=7 #define #rx_phaserot_left_edge=49:55; #start_bit=49, number_of_bit=7 @@ -438,7 +215,6 @@ define rx_phaserot_val=49:55; #start_bit=49, number_of_bit=7 define rx_eye_width=50:55; #start_bit=50, number_of_bit=6 define rx_hist_min_eye_width_valid=56:56; #start_bit=56, number_of_bit=1 define rx_hist_min_eye_width=58:63; #start_bit=58, number_of_bit=6 -define rx_reset_hist_eye_width_min=48:48; #start_bit=48, number_of_bit=1 define rx_ber_count=48:55; #start_bit=48, number_of_bit=8 define rx_ber_count_saturated=56:56; #start_bit=56, number_of_bit=1 define rx_ber_count_frozen_by_lane=57:57; #start_bit=57, number_of_bit=1 @@ -455,19 +231,21 @@ define rx_fifo_out_16_31=48:63; #start_bit=48, number_of_bit=16 define rx_fifo_out_32_47=48:63; #start_bit=48, number_of_bit=16 define rx_ln_trc_en=48:48; #start_bit=48, number_of_bit=1 define rx_servo_ber_count=48:59; #start_bit=48, number_of_bit=12 +define rx_dcd_adjust=48:51; #start_bit=48, number_of_bit=4 define rx_clk_pdwn=48:48; #start_bit=48, number_of_bit=1 define rx_clk_invert=49:49; #start_bit=49, number_of_bit=1 +define rx_clk_amp_peak=58:63; #start_bit=58, number_of_bit=6 define rx_pg_spare_mode_0=48:48; #start_bit=48, number_of_bit=1 define rx_pg_spare_mode_1=49:49; #start_bit=49, number_of_bit=1 define rx_pg_spare_mode_2=50:50; #start_bit=50, number_of_bit=1 define rx_pg_spare_mode_3=51:51; #start_bit=51, number_of_bit=1 define rx_pg_spare_mode_4=52:52; #start_bit=52, number_of_bit=1 -define rx_pg_spare_mode_5=53:53; #start_bit=53, number_of_bit=1 -define rx_pg_spare_mode_6=54:54; #start_bit=54, number_of_bit=1 -define rx_pg_spare_mode_7=55:55; #start_bit=55, number_of_bit=1 +#define #rx_pg_spare_mode_5=53:53; #start_bit=53, number_of_bit=1 +#define #rx_pg_spare_mode_6=54:54; #start_bit=54, number_of_bit=1 +#define #rx_pg_spare_mode_7=55:55; #start_bit=55, number_of_bit=1 +define rx_sls_extend_sel=53:55; #start_bit=53, number_of_bit=3 define rx_master_mode=48:48; #start_bit=48, number_of_bit=1 define rx_disable_fence_reset=49:49; #start_bit=49, number_of_bit=1 -define rx_reset_cfg_ena=48:48; #start_bit=48, number_of_bit=1 define rx_clr_par_errs=62:62; #start_bit=62, number_of_bit=1 define rx_fir_reset=63:63; #start_bit=63, number_of_bit=1 define rx_bus_id=48:53; #start_bit=48, number_of_bit=6 @@ -732,6 +510,7 @@ define rx_gcr_msg_debug_src_group_id=54:59; #start_bit=54, number_of_bit=6 define rx_gcr_msg_debug_dest_addr=48:56; #start_bit=48, number_of_bit=9 define rx_gcr_msg_debug_send_msg=63:63; #start_bit=63, number_of_bit=1 define rx_gcr_msg_debug_write_data=48:63; #start_bit=48, number_of_bit=16 +#define #rx_eye_opt_state=48:55; #start_bit=48, number_of_bit=8 define rx_eye_opt_state=48:55; #start_bit=48, number_of_bit=8 define rx_recal_state=56:63; #start_bit=56, number_of_bit=8 define rx_wt_clk_lane_inverted=49:49; #start_bit=49, number_of_bit=1 @@ -744,6 +523,7 @@ define rx_eo_enable_measure_eye_width=55:55; #start_bit=55, number_of_bit=1 define rx_eo_enable_final_l2u_adj=56:56; #start_bit=56, number_of_bit=1 define rx_eo_enable_ber_test=57:57; #start_bit=57, number_of_bit=1 define rx_eo_enable_result_check=58:58; #start_bit=58, number_of_bit=1 +define rx_eo_enable_dcd_cal=60:60; #start_bit=60, number_of_bit=1 define rx_rc_enable_edge_track=51:51; #start_bit=51, number_of_bit=1 define rx_rc_enable_measure_eye_width=55:55; #start_bit=55, number_of_bit=1 define rx_rc_enable_result_check=57:57; #start_bit=57, number_of_bit=1 @@ -760,6 +540,7 @@ define rx_eo_vref_failed=51:51; #start_bit=51, number_of_bit=1 define rx_eo_measure_eye_width_failed=55:55; #start_bit=55, number_of_bit=1 define rx_eo_final_l2u_adj_failed=56:56; #start_bit=56, number_of_bit=1 define rx_eo_result_check_failed=57:57; #start_bit=57, number_of_bit=1 +define rx_eo_dcd_failed=58:58; #start_bit=58, number_of_bit=1 #define #rx_amp_peak_work=48:51; #start_bit=48, number_of_bit=4 #define #rx_amp_peak_work=48:53; #start_bit=48, number_of_bit=6 define rx_servo_ber_count_work=48:59; #start_bit=48, number_of_bit=12 @@ -778,7 +559,6 @@ define rx_rdt_check_mask=50:54; #start_bit=50, number_of_bit=5 define rx_rdt_failed=55:55; #start_bit=55, number_of_bit=1 define rx_trc_mode=48:51; #start_bit=48, number_of_bit=4 define rx_trc_grp=54:59; #start_bit=54, number_of_bit=6 -define rx_dyn_rpr_bad_lane_valid_debug=48:48; #start_bit=48, number_of_bit=1 define rx_dyn_rpr_enc_bad_data_lane_debug=49:55; #start_bit=49, number_of_bit=7 define rx_bad_bus_err_cntr=57:63; #start_bit=57, number_of_bit=7 define rx_bad_bus_lane_err_cntr_dis_clr=48:48; #start_bit=48, number_of_bit=1 @@ -788,9 +568,9 @@ define rx_dyn_rpr_bad_bus_max=48:54; #start_bit=48, number_of_bit=7 define rx_dyn_rpr_err_cntr2_duration=55:58; #start_bit=55, number_of_bit=4 define rx_dyn_rpr_clr_err_cntr2=59:59; #start_bit=59, number_of_bit=1 define rx_min_eye_width=50:55; #start_bit=50, number_of_bit=6 +define rx_max_ber_check_count=56:63; #start_bit=56, number_of_bit=8 define rx_stop_state_enable=48:48; #start_bit=48, number_of_bit=1 define rx_state_stopped=49:49; #start_bit=49, number_of_bit=1 -define rx_resume_from_stop=50:50; #start_bit=50, number_of_bit=1 define rx_stop_addr_msb=56:59; #start_bit=56, number_of_bit=4 define rx_stop_mask_msb=60:63; #start_bit=60, number_of_bit=4 define rx_stop_addr_lsb=48:63; #start_bit=48, number_of_bit=16 @@ -822,52 +602,50 @@ define rx_bist_jitter_pulse_sel=51:52; #start_bit=51, number_of_bit=2 define rx_bist_min_eye_width=53:59; #start_bit=53, number_of_bit=7 define rx_dis_block_lock_vref=60:60; #start_bit=60, number_of_bit=1 define rx_wt_pattern_length=61:62; #start_bit=61, number_of_bit=2 -define rx_servo_timeout_sel_A=48:51; #start_bit=48, number_of_bit=4 -define rx_servo_timeout_sel_B=52:55; #start_bit=52, number_of_bit=4 -define rx_servo_timeout_sel_C=56:59; #start_bit=56, number_of_bit=4 -define rx_servo_timeout_sel_D=60:63; #start_bit=60, number_of_bit=4 -define rx_servo_timeout_sel_E=48:51; #start_bit=48, number_of_bit=4 -define rx_servo_timeout_sel_F=52:55; #start_bit=52, number_of_bit=4 -define rx_servo_timeout_sel_G=56:59; #start_bit=56, number_of_bit=4 -define rx_servo_timeout_sel_H=60:63; #start_bit=60, number_of_bit=4 -define rx_recal_timeout_sel_A=48:51; #start_bit=48, number_of_bit=4 -define rx_recal_timeout_sel_E=48:51; #start_bit=48, number_of_bit=4 -define rx_recal_timeout_sel_F=52:55; #start_bit=52, number_of_bit=4 +define rx_servo_timeout_sel_a=48:51; #start_bit=48, number_of_bit=4 +define rx_servo_timeout_sel_b=52:55; #start_bit=52, number_of_bit=4 +define rx_servo_timeout_sel_c=56:59; #start_bit=56, number_of_bit=4 +define rx_servo_timeout_sel_d=60:63; #start_bit=60, number_of_bit=4 +define rx_servo_timeout_sel_e=48:51; #start_bit=48, number_of_bit=4 +define rx_servo_timeout_sel_f=52:55; #start_bit=52, number_of_bit=4 +define rx_servo_timeout_sel_g=56:59; #start_bit=56, number_of_bit=4 +define rx_servo_timeout_sel_h=60:63; #start_bit=60, number_of_bit=4 +define rx_recal_timeout_sel_a=48:51; #start_bit=48, number_of_bit=4 +define rx_recal_timeout_sel_e=48:51; #start_bit=48, number_of_bit=4 +define rx_recal_timeout_sel_f=52:55; #start_bit=52, number_of_bit=4 #define #rx_block_lock=48:48; #start_bit=48, number_of_bit=1 define rx_prbs_check_sync=49:49; #start_bit=49, number_of_bit=1 define rx_enable_reduced_scramble=50:50; #start_bit=50, number_of_bit=1 -define rx_prbs_inc=51:51; #start_bit=51, number_of_bit=1 -define rx_prbs_dec=52:52; #start_bit=52, number_of_bit=1 define rx_recal_in_progress=48:48; #start_bit=48, number_of_bit=1 define rx_ddc_use_cyc_block_lock=48:48; #start_bit=48, number_of_bit=1 -define rx_cal_inc_val_A=48:51; #start_bit=48, number_of_bit=4 -define rx_cal_inc_val_B=52:55; #start_bit=52, number_of_bit=4 -define rx_cal_inc_val_C=56:59; #start_bit=56, number_of_bit=4 -define rx_cal_inc_val_D=60:63; #start_bit=60, number_of_bit=4 -define rx_cal_inc_val_E=48:51; #start_bit=48, number_of_bit=4 -define rx_cal_inc_val_F=52:55; #start_bit=52, number_of_bit=4 -define rx_cal_inc_val_G=56:59; #start_bit=56, number_of_bit=4 -define rx_cal_inc_val_H=60:63; #start_bit=60, number_of_bit=4 -define rx_cal_dec_val_A=48:51; #start_bit=48, number_of_bit=4 -define rx_cal_dec_val_B=52:55; #start_bit=52, number_of_bit=4 -define rx_cal_dec_val_C=56:59; #start_bit=56, number_of_bit=4 -define rx_cal_dec_val_D=60:63; #start_bit=60, number_of_bit=4 -define rx_cal_dec_val_E=48:51; #start_bit=48, number_of_bit=4 -define rx_cal_dec_val_F=52:55; #start_bit=52, number_of_bit=4 -define rx_cal_dec_val_G=56:59; #start_bit=56, number_of_bit=4 -define rx_cal_dec_val_H=60:63; #start_bit=60, number_of_bit=4 +define rx_peak_baud_sel=49:50; #start_bit=49, number_of_bit=2 +define rx_peak_baud_toggle_sel=51:52; #start_bit=51, number_of_bit=2 +define rx_reverse_dcd=53:53; #start_bit=53, number_of_bit=1 +define rx_cal_inc_val_a=48:51; #start_bit=48, number_of_bit=4 +define rx_cal_inc_val_b=52:55; #start_bit=52, number_of_bit=4 +define rx_cal_inc_val_c=56:59; #start_bit=56, number_of_bit=4 +define rx_cal_inc_val_d=60:63; #start_bit=60, number_of_bit=4 +define rx_cal_inc_val_e=48:51; #start_bit=48, number_of_bit=4 +define rx_cal_inc_val_f=52:55; #start_bit=52, number_of_bit=4 +define rx_cal_inc_val_g=56:59; #start_bit=56, number_of_bit=4 +define rx_cal_inc_val_h=60:63; #start_bit=60, number_of_bit=4 +define rx_cal_dec_val_a=48:51; #start_bit=48, number_of_bit=4 +define rx_cal_dec_val_b=52:55; #start_bit=52, number_of_bit=4 +define rx_cal_dec_val_c=56:59; #start_bit=56, number_of_bit=4 +define rx_cal_dec_val_d=60:63; #start_bit=60, number_of_bit=4 +define rx_cal_dec_val_e=48:51; #start_bit=48, number_of_bit=4 +define rx_cal_dec_val_f=52:55; #start_bit=52, number_of_bit=4 +define rx_cal_dec_val_g=56:59; #start_bit=56, number_of_bit=4 +define rx_cal_dec_val_h=60:63; #start_bit=60, number_of_bit=4 define rx_reset_cfg_hld=48:63; #start_bit=48, number_of_bit=16 define rx_bist_en=48:48; #start_bit=48, number_of_bit=1 define rx_ber_en=48:48; #start_bit=48, number_of_bit=1 -define rx_ber_count_clr=49:49; #start_bit=49, number_of_bit=1 -define rx_ber_timer_clr=50:50; #start_bit=50, number_of_bit=1 define rx_ber_timer_freeze_en=48:48; #start_bit=48, number_of_bit=1 define rx_ber_count_freeze_en=49:49; #start_bit=49, number_of_bit=1 define rx_ber_count_sel=51:53; #start_bit=51, number_of_bit=3 define rx_ber_timer_sel=54:56; #start_bit=54, number_of_bit=3 define rx_ber_clr_count_on_read_en=57:57; #start_bit=57, number_of_bit=1 define rx_ber_clr_timer_on_read_en=58:58; #start_bit=58, number_of_bit=1 -define rx_fir_msg=48:55; #start_bit=48, number_of_bit=8 define rx_pb_clr_par_errs=62:62; #start_bit=62, number_of_bit=1 define rx_pb_fir_reset=63:63; #start_bit=63, number_of_bit=1 define rx_pb_fir_errs_full_reg=48:57; #start_bit=48, number_of_bit=10 @@ -906,19 +684,223 @@ define rx_pb_fir_err_inj_gcrs_ld_sm2=54:54; #start_bit=54, number_of_bit=1 define rx_pb_fir_err_inj_gcrs_unld_sm0=55:55; #start_bit=55, number_of_bit=1 define rx_pb_fir_err_inj_gcrs_unld_sm1=56:56; #start_bit=56, number_of_bit=1 define rx_pb_fir_err_inj_gcrs_unld_sm2=57:57; #start_bit=57, number_of_bit=1 +define tx_mode_pl=010000000; #080 +define tx_cntl_stat_pl=010000001; #081 +define tx_spare_mode_pl=010000010; #082 +#define #tx_id_pl=010000100; #084 +define tx_bist_stat_pl=010000101; #085 +define tx_prbs_mode_pl=010000110; #086 +define tx_data_cntl_gcrmsg_pl=010000111; #087 +define tx_sync_pattern_gcrmsg_pl=010001000; #088 +define tx_fir_pl=010001010; #08A +define tx_fir_mask_pl=010001011; #08B +define tx_fir_error_inject_pl=010001100; #08C +define tx_mode_fast_pl=010001101; #08D +define tx_clk_mode_pg=110000000; #180 +define tx_spare_mode_pg=110000001; #181 +define tx_cntl_stat_pg=110000010; #182 +define tx_mode_pg=110000011; #183 +define tx_reset_act_pg=110001000; #188 +define tx_bist_stat_pg=110001001; #189 +define tx_fir_pg=110001010; #18A +define tx_fir_mask_pg=110001011; #18B +define tx_fir_error_inject_pg=110001100; #18C +define tx_id1_pg=110010010; #192 +define tx_id2_pg=110010011; #193 +define tx_id3_pg=110010100; #194 +define tx_clk_cntl_gcrmsg_pg=110011000; #198 +define tx_bad_lane_enc_gcrmsg_pg=110011101; #19D +define tx_ber_cntl_pg=110011110; #19E +define tx_sls_lane_enc_gcrmsg_pg=110011111; #19F +define tx_wt_seg_enable_pg=110100000; #1A0 +#define #tx_term_pg=110100000; #1A0 +define tx_pc_ffe_pg=110100001; #1A1 +define tx_misc_analog_pg=110100010; #1A2 +define tx_lane_disabled_vec_0_15_pg=110100011; #1A3 +define tx_lane_disabled_vec_16_31_pg=110100100; #1A4 +define tx_sls_lane_mux_gcrmsg_pg=110100101; #1A5 +define tx_dyn_rpr_pg=110100110; #1A6 +define tx_slv_mv_sls_ln_req_gcrmsg_pg=110100111; #1A7 +define tx_rdt_cntl_pg=110101000; #1A8 +define rx_dll_cal_cntl_pg=111000111; #1C7 +define rx_dll1_setpoint1_pg=111001000; #1C8 +define rx_dll1_setpoint2_pg=111001001; #1C9 +define rx_dll1_setpoint3_pg=111001010; #1CA +define rx_dll2_setpoint1_pg=111001011; #1CB +define rx_dll2_setpoint2_pg=111001100; #1CC +define rx_dll2_setpoint3_pg=111001101; #1CD +define rx_dll_filter_mode_pg=111001110; #1CE +define rx_dll_analog_tweaks_pg=111001111; #1CF +define tx_wiretest_pp=111010000; #1D0 +define tx_mode_pp=111010001; #1D1 +define tx_sls_gcrmsg_pp=111010010; #1D2 +define tx_ber_cntl_a_pp=111010011; #1D3 +define tx_ber_cntl_b_pp=111010100; #1D4 +define tx_bist_cntl_pp=111010110; #1D6 +define tx_ber_cntl_sls_pp=111010111; #1D7 +define tx_cntl_pp=111011000; #1D8 +define tx_reset_cfg_pp=111011001; #1D9 +define tx_tdr_cntl2_pp=111011011; #1DB +define tx_tdr_cntl3_pp=111011100; #1DC +define tx_init_version_pb=111101000; #1E8 +define tx_scratch_reg_pb=111101001; #1E9 +define rx_mode_pl=000000000; #000 +define rx_cntl_pl=000000001; #001 +define rx_spare_mode_pl=000000010; #002 +define rx_prot_edge_status_pl=000000011; #003 +#define #rx_prot_gb_status_pl=000000100; #004 +define rx_bist_stat_pl=000000101; #005 +#define ##rx_eyeopt_mode_pl=000000110; #006 +#define #rx_eyeopt_stat_pl=000000111; #007 +define rx_offset_even_pl=000001000; #008 +define rx_offset_odd_pl=000001001; #009 +define rx_amp_val_pl=000001010; #00A +define rx_prot_status_pl=000001100; #00C +define rx_prot_mode_pl=000001101; #00D +define rx_prot_cntl_pl=000001110; #00E +#define #rx_wiretest_stat_pl=000001110; #00E +define rx_fifo_stat_pl=000001111; #00F +define rx_prbs_mode_pl=000010110; #016 +define rx_vref_pl=000010111; #017 +define rx_stat_pl=000011000; #018 +define rx_deskew_stat_pl=000011001; #019 +define rx_fir_pl=000011010; #01A +define rx_fir_mask_pl=000011011; #01B +define rx_fir_error_inject_pl=000011100; #01C +define rx_sls_pl=000011101; #01D +define rx_wt_status_pl=000011110; #01E +define rx_fifo_cntl_pl=000011111; #01F +define rx_ber_status_pl=000100000; #020 +define rx_ber_timer_0_15_pl=000100001; #021 +define rx_ber_timer_16_31_pl=000100010; #022 +define rx_ber_timer_32_39_pl=000100011; #023 +define rx_servo_cntl_pl=000100100; #024 +define rx_fifo_diag_0_15_pl=000100101; #025 +define rx_fifo_diag_16_31_pl=000100110; #026 +define rx_fifo_diag_32_47_pl=000100111; #027 +define rx_eye_width_status_pl=000101000; #028 +define rx_eye_width_cntl_pl=000101001; #029 +define rx_trace_pl=000101011; #02B +define rx_servo_ber_count_pl=000101100; #02C +define rx_eye_opt_stat_pl=000101101; #02D +define rx_dcd_adj_pl=000101110; #02E +define rx_clk_mode_pg=100000000; #100 +define rx_spare_mode_pg=100000001; #101 +define rx_stop_cntl_stat_pg=100000010; #102 +define rx_mode_pg=100000011; #103 +define rx_stop_addr_lsb_pg=100000111; #107 +define rx_stop_mask_lsb_pg=100001000; #108 +define rx_reset_act_pg=100001001; #109 +define rx_id1_pg=100001010; #10A +define rx_id2_pg=100001011; #10B +define rx_id3_pg=100001100; #10C +define rx_dyn_rpr_debug2_pg=100001110; #10E +define rx_sls_mode_pg=100001111; #10F +define rx_training_start_pg=100010000; #110 +define rx_training_status_pg=100010001; #111 +define rx_recal_status_pg=100010010; #112 +define rx_timeout_sel_pg=100010011; #113 +define rx_fifo_mode_pg=100010100; #114 +#define #rx_state_debug_pg=100010101; #115 +#define #rx_state_val_pg=100010110; #116 +define rx_sls_status_pg=100010111; #117 +define rx_fir1_pg=100011010; #11A +define rx_fir2_pg=100011011; #11B +define rx_fir1_mask_pg=100011100; #11C +define rx_fir2_mask_pg=100011101; #11D +define rx_fir1_error_inject_pg=100011110; #11E +define rx_fir2_error_inject_pg=100011111; #11F +define rx_fir_training_pg=100100000; #120 +define rx_fir_training_mask_pg=100100001; #121 +define rx_timeout_sel1_pg=100100010; #122 +define rx_lane_bad_vec_0_15_pg=100100011; #123 +define rx_lane_bad_vec_16_31_pg=100100100; #124 +define rx_lane_disabled_vec_0_15_pg=100100101; #125 +define rx_lane_disabled_vec_16_31_pg=100100110; #126 +define rx_lane_swapped_vec_0_15_pg=100100111; #127 +define rx_lane_swapped_vec_16_31_pg=100101000; #128 +define rx_init_state_pg=100101001; #129 +define rx_wiretest_state_pg=100101010; #12A +define rx_wiretest_laneinfo_pg=100101011; #12B +define rx_wiretest_gcrmsgs_pg=100101100; #12C +define rx_deskew_gcrmsgs_pg=100101101; #12D +define rx_deskew_state_pg=100101110; #12E +define rx_deskew_mode_pg=100101111; #12F +define rx_deskew_status_pg=100110000; #130 +define rx_bad_lane_enc_gcrmsg_pg=100110001; #131 +define rx_static_repair_state_pg=100110010; #132 +define rx_tx_bus_info_pg=100110011; #133 +define rx_sls_lane_enc_gcrmsg_pg=100110100; #134 +define rx_fence_pg=100110101; #135 +define rx_term_pg=100110110; #136 +define rx_timeout_sel2_pg=100110111; #137 +define rx_misc_analog_pg=100111000; #138 +define rx_dyn_rpr_pg=100111001; #139 +define rx_dyn_rpr_gcrmsg_pg=100111010; #13A +define rx_dyn_rpr_err_tallying1_pg=100111011; #13B +define rx_eo_final_l2u_gcrmsgs_pg=100111100; #13C +define rx_gcr_msg_debug_dest_ids_pg=100111101; #13D +define rx_gcr_msg_debug_src_ids_pg=100111110; #13E +define rx_gcr_msg_debug_dest_addr_pg=100111111; #13F +define rx_gcr_msg_debug_write_data_pg=101000000; #140 +define rx_wt_clk_status_pg=101000010; #142 +define rx_wt_config_pg=101000100; #144 +define rx_wiretest_pll_cntl_pg=101000110; #146 +define rx_eo_step_cntl_pg=101000111; #147 +define rx_eo_step_stat_pg=101001000; #148 +define rx_eo_step_fail_pg=101001001; #149 +define rx_amp_val_pg=101001110; #14E +define rx_sls_rcvy_pg=101010001; #151 +define rx_sls_rcvy_gcrmsg_pg=101010010; #152 +define rx_tx_lane_info_gcrmsg_pg=101010011; #153 +define rx_err_tallying_gcrmsg_pg=101010100; #154 +define rx_trace_pg=101010101; #155 +define rx_rdt_cntl_pg=101010110; #156 +define rx_rc_step_cntl_pg=101010111; #157 +define rx_eo_recal_pg=101011000; #158 +define rx_servo_ber_count_pg=101011001; #159 +define rx_func_state_pg=101011010; #15A +define rx_dyn_rpr_debug_pg=101011011; #15B +define rx_dyn_rpr_err_tallying2_pg=101011100; #15C +define rx_result_chk_pg=101011101; #15D +define rx_ber_chk_pg=101011110; #15E +define rx_sls_rcvy_fin_gcrmsg_pg=101011111; #15F +#define #rx_wiretest_pp=101100000; #160 +define rx_mode1_pp=101100001; #161 +define rx_cntl_fast_pp=101100010; #162 +define rx_ei4_cal_cntl_pp=101100011; #163 +define rx_ei4_cal_inc_a_d_pp=101100100; #164 +define rx_ei4_cal_inc_e_h_pp=101100101; #165 +define rx_ei4_cal_dec_a_d_pp=101100110; #166 +define rx_ei4_cal_dec_e_h_pp=101100111; #167 +define rx_ber_cntl_pp=101101010; #16A +define rx_ber_mode_pp=101101011; #16B +define rx_servo_to1_pp=101101100; #16C +define rx_servo_to2_pp=101101101; #16D +define rx_reset_cfg_pp=101110001; #171 +define rx_recal_to1_pp=101110010; #172 +define rx_recal_to2_pp=101110011; #173 +define rx_recal_cntl_pp=101110101; #175 +define rx_mode2_pp=101110110; #176 +define rx_bist_gcrmsg_pp=101110111; #177 +define rx_fir_reset_pb=111110000; #1F0 +define rx_fir_pb=111110001; #1F1 +define rx_fir_mask_pb=111110010; #1F2 +define rx_fir_error_inject_pb=111110011; #1F3 +define rx_fir_msg_pb=111111111; #1FF define xbus0_gcr_addr=0401103F; define xbus1_gcr_addr=0401143F; define xbus2_gcr_addr=04011C3F; define xbus3_gcr_addr=0401183F; -define rx_grp0=000000; # 0x00 -define rx_grp1=000001; # 0x01 -define rx_grp2=000010; # 0x02 -define rx_grp3=000011; # 0x03 -define tx_grp0=100000; # 0x20 -define tx_grp1=100001; # 0x21 -define tx_grp2=100010; # 0x22 -define tx_grp3=100011; # 0x23 -define lane_na=00000; # 0x00 +define rx_grp0=000000; # 0x00 +define rx_grp1=000001; # 0x01 +define rx_grp2=000010; # 0x02 +define rx_grp3=000011; # 0x03 +define tx_grp0=100000; # 0x20 +define tx_grp1=100001; # 0x21 +define tx_grp2=100010; # 0x22 +define tx_grp3=100011; # 0x23 +define lane_na=00000; # 0x00 define lane_0=00000; define lane_1=00001; define lane_2=00010; @@ -957,5 +939,3 @@ define tx_prbs_tap_id_pattern_c=0b0100000000000000; define tx_prbs_tap_id_pattern_d=0b0110000000000000; define tx_prbs_tap_id_pattern_e=0b1000000000000000; define tx_prbs_tap_id_pattern_f=0b1010000000000000; -define tx_prbs_tap_id_pattern_g=0b1100000000000000; -define tx_prbs_tap_id_pattern_h=0b1110000000000000; diff --git a/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile index b923afda4..3bd0800af 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile @@ -1,8 +1,12 @@ -#-- $Id: p8.abus.scom.initfile,v 1.4 2012/07/28 03:43:16 jmcgill Exp $ +#-- $Id: p8.abus.scom.initfile,v 1.6 2013/01/22 02:57:21 thomsen Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.6 |thomsen |01/21/13|Removed ATTR_EI_BUS_RX_MSB_LSB_SWAP & ATTR_EI_BUS_TX_MSB_LSB_SWAP as those are old now +#-- | | |Removed non-mirrored mode settings in PRBS tap id's +#-- 1.5 |pmegan |09/27/12|Set rx_sls_timeout_sel to 0b001 per defect HW220752 +#-- | | |Set rx_sls_extend_sel to 0b100 on slave chip per defect HW220806 #-- 1.4 |jmcgill |07/28/12|Simplify master/slave logic (node ID always unique) #-- 1.3 |jmcgill |07/27/12|Edits to match scan initfle #-- 1.2 |pmegan |07/11/12|Added ID in file header @@ -11,10 +15,9 @@ #-------------------------------------------------------------------------------- # End of revision history #-------------------------------------------------------------------------------- + #--Master list of variables that can be used in this file is at: #--<Attribute Definition Location> -#-- ATTR_EI_BUS_RX_MSB_LSB_SWAP is 0 for setting RX PRBS TapID's to Non-Mirrored Mode and 1 for setting to Mirrored Mode. It comes from the MRW. -#-- ATTR_EI_BUS_TX_MSB_LSB_SWAP is 0 for setting TX PRBS TapID's to Non-Mirrored Mode and 1 for setting to Mirrored Mode. It comes from the MRW. SyntaxVersion = 1 @@ -44,10 +47,6 @@ define def_bus_id2 = (ATTR_CHIP_UNIT_POS == 2); define def_is_master = (TGT1.ATTR_FABRIC_NODE_ID < TGT2.ATTR_FABRIC_NODE_ID); define def_is_slave = (TGT1.ATTR_FABRIC_NODE_ID > TGT2.ATTR_FABRIC_NODE_ID); -define def_rx_mirrored_mode = (ATTR_EI_BUS_RX_MSB_LSB_SWAP == 1); # Mirrored mode -define def_rx_non_mirrored_mode = (ATTR_EI_BUS_RX_MSB_LSB_SWAP == 0); # Non-Mirrored mode -define def_tx_mirrored_mode = (ATTR_EI_BUS_TX_MSB_LSB_SWAP == 1); # Mirrored mode -define def_tx_non_mirrored_mode = (ATTR_EI_BUS_TX_MSB_LSB_SWAP == 0); # Non-Mirrored mode # See p8.chipunit.scominfo file for details of how SCOM addresses are translated by Cronus and FW based on the target unit number define def_rx_base_grp = rx_grp0; # @@ -234,124 +233,100 @@ scom 0x800.0b(rx_mode_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ #-- rx_prbs_mode_pl: rx_prbs_tap_id #--********************************************************************************************* scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_0).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_1).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_2).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_3).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_4).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_e, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_e, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_e; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_5).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_f, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_f, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_f; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_6).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_g, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_g, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_g; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_7).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_h, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_h, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_h; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_8).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_9).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_10).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_11).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_12).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_13).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_14).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_15).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_h, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_16).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_h, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_g, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_h; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_17).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_g, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_f, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_g; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_18).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_f, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_e, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_f; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_19).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_e, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_e; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_20).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_21).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_22).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_23).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a; } #------------------------------------------------------------------------------------- # PER-LANE (TX) @@ -360,124 +335,100 @@ scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_23).0x(abus_gcr_addr){ #-- tx_prbs_mode_pl: tx_prbs_tap_id #--********************************************************************************************* scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_0).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_a; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_1).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_b; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_2).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_c; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_3).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_d, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_d, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_d; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_4).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_e, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_e, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_e; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_5).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_f, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_f, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_f; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_6).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_g, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_g, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_g; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_7).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_h, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_h, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_h; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_8).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_a; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_9).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_b; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_10).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_c; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_11).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_d, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_d, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_d; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_12).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_d, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_d; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_13).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_c; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_14).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_b; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_15).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_h, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_a; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_16).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_h, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_g, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_h; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_17).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_g, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_f, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_g; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_18).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_f, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_e, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_f; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_19).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_e, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_d, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_e; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_20).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_d, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_d; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_21).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_c; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_22).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_b; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_23).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_a; } #------------------------------------------------------------------------------------- @@ -509,6 +460,34 @@ scom 0x800.0b(tx_clk_cntl_gcrmsg_pg)(def_tx_base_grp)(lane_na).0x(abus_gcr_addr) bits, scom_data; tx_drv_clk_pattern_gcrmsg, 0b00; # Drive 0's to start out } +#------------------------------------------------------------------------------------- +# ____ _ __ _______ _____ __ +# / __ \ |/ / /_ __(_)___ ___ ___ _____ / ___/___ / / +# / /_/ / / / / / / __ `__ \/ _ \/ ___/ \__ \/ _ \/ / +# / _, _/ | / / / / / / / / / __/ / ___/ / __/ / +#/_/ |_/_/|_| /_/ /_/_/ /_/ /_/\___/_/ /____/\___/_/ +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +#-- rx_timeout_sel_pg: rx_sls_timeout_sel +#--********************************************************************************************* +scom 0x800.0b(rx_timeout_sel_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ + bits, scom_data; + rx_sls_timeout_sel, 0b001; # Set this entry to 0b001 per defect HW220752 +} +#------------------------------------------------------------------------------------- +# ____ _ __ _____ __ _____ ______ __ __ _____ __ +# / __ \ |/ / / ___// / / ___/ / ____/ __/ /____ ____ ____/ / / ___/___ / / +# / /_/ / / \__ \/ / \__ \ / __/ | |/_/ __/ _ \/ __ \/ __ / \__ \/ _ \/ / +# / _, _/ | ___/ / /______/ / / /____> </ /_/ __/ / / / /_/ / ___/ / __/ / +#/_/ |_/_/|_| /____/_____/____/ /_____/_/|_|\__/\___/_/ /_/\__,_/ /____/\___/_/ +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +#-- rx_spare_mode_pg: rx_sls_extend_sel +#--********************************************************************************************* +scom 0x800.0b(rx_spare_mode_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_sls_extend_sel, 0b100, (def_is_slave); #Set this entry to 0b100 per defect HW220806 +} ############################################################################################ # END OF FILE diff --git a/src/usr/hwpf/hwp/initfiles/p8.as.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.as.scom.initfile new file mode 100644 index 000000000..6ad2fb3f6 --- /dev/null +++ b/src/usr/hwpf/hwp/initfiles/p8.as.scom.initfile @@ -0,0 +1,130 @@ +#-- $Id: p8.as.scom.initfile,v 1.3 2013/01/16 20:26:34 irish Exp $ +#------------------------------------------------------------------------------- +#-- +#-- (C) Copyright International Business Machines Corp. 2013 +#-- All Rights Reserved -- Property of IBM +#-- *** IBM Confidential *** +#-- +#-- TITLE : p8.as.scom.initfile +#-- DESCRIPTION : Perform AS configuration +#-- +#-- OWNER NAME : John Irish Email: irish@us.ibm.com +#-- +#-------------------------------------------------------------------------------- + +SyntaxVersion = 1 + +#-------------------------------------------------------------------------------- +#-- Includes +#-------------------------------------------------------------------------------- + +#-------------------------------------------------------------------------------- +#-- Defines +#-------------------------------------------------------------------------------- + +#-------------------------------------------------------------------------------- +#-- SCOM initializations +#-------------------------------------------------------------------------------- + +#-- AS Config Register (0x020130FE) +scom 0x020130FE { + bits , scom_data ; + 0 , 0b1 ; #-- pbus in enable (ON) + 1 , 0b0 ; #-- dslc enable (OFF - set to 1 if DSLC link needed) + 2 , 0b0 ; #-- copreq wait for data (OFF) + 3 , 0b0 ; #-- copreq wait for cresp (OFF) + 4 , 0b0 ; #-- credwt wait for data (OFF) + 5 , 0b0 ; #-- dredwt wait for cresp (OFF) + 6 , 0b0 ; #-- dslc wait for data (OFF) + 7 , 0b0 ; #-- data hang check (ON) + 8 , 0b0 ; #-- sary ce rewrite (ON) + 9 , 0b0 ; #-- rcmd pchk (ON) + 10 , 0b0 ; #-- capture mal-formed mmio st (OFF) + 11 , 0b0 ; #-- capture data hang (OFF) + 12 , 0b0 ; #-- capture multiple cam hit (OFF) + 13 , 0b0 ; #-- capture phyp credit retry (OFF) + 14 , 0b0 ; #-- capture correctable errors (OFF) + 15 , 0b1 ; #-- capture unsupported conf (ON) + 16 , 0b0 ; #-- hypervisor PID chk ovrrd (OFF) + 17 , 0b0 ; #-- priveledged PID chk ovrrd (OFF) + 18 , 0b0 ; #-- spare 0 (OFF) + 19 , 0b0 ; #-- spare 1 (OFF) + 20 , 0b0 ; #-- spare 2 (OFF) + 21 , 0b0 ; #-- spare 3 (OFF) + 22 , 0b0 ; #-- spare 5 (OFF) + 23 , 0b0 ; #-- spare 6 (OFF) + 24 , 0b0 ; #-- spare 7 (OFF) + 25 , 0b0 ; #-- spare 8 (OFF) + 26 , 0b0 ; #-- spare 9 (OFF) + 27 , 0b0 ; #-- spare 10 (OFF) + 28 , 0b0 ; #-- spare 11 (OFF) + 29 , 0b0 ; #-- spare 12 (OFF) + 30 , 0b0 ; #-- spare 13 (OFF) + 31 , 0b0 ; #-- spare 14 (OFF) + 32 , 0b1 ; #-- FL wait for data sent (ON) +} + +#-- AS EG Config Register (0x020130F2) +scom 0x020130F2 { + bits , scom_data ; + 0 , 0b1 ; #-- EG enable (ON) + 1 , 0b0 ; #-- page migration mode (OFF) + 2:3 , 0b00 ; #-- credwt pref level (0) + 4 , 0b0 ; #-- relaxed DMA ordering (OFF) + 5 , 0b0 ; #-- dir cmd hang detect (OFF) + 6 , 0b1 ; #-- rary ce rewrite (ON) + 7 , 0b1 ; #-- cresp pchk (ON) + 8:9 , 0b00 ; #-- dma throttle (OFF) + 10:11 , 0b00 ; #-- notif throttle (OFF) + 12:13 , 0b00 ; #-- intr throttle (OFF) + 14:15 , 0b00 ; #-- credwt throttle (OFF) + 16:21 , 0b000000 ; #-- reserved (OFF) + 22 , 0b1 ; #-- force DMA to normal path (ON) + 23 , 0b0 ; #-- all notify to system scope (OFF) + 24 , 0b0 ; #-- grp notify to system scope (OFF) + 25 , 0b0 ; #-- rmt-grp notify to system scope (OFF) + 26 , 0b0 ; #-- all credwt to system scope (OFF) + 27 , 0b1 ; #-- grp credwt to system scope (ON) + 28 , 0b1 ; #-- rmt-grp credwt to system scope (ON) + 29 , 0b0 ; #-- hang on addr error (OFF) + 30:31 , 0b00 ; #-- dma worklist threshold (64) + 32:35 , 0b0000 ; #-- starve timer (OFF) + 36:39 , 0b0000 ; #-- stale timer (OFF) + 40 , 0b0 ; #-- force PM orig to normal path (OFF) + 41 , 0b0 ; #-- reserved (OFF) + 42:63 , 0x000 ; #-- reserved (OFF) +} + +#--****************************************************************************** +# FIR Action Register Decodes +#--****************************************************************************** +# (Action0, Action1, Mask) +# ------------------------ +# (0,0,0) = Checkstop +# (0,1,0) = Recoverable +# (1,0,0) = Reserved +# (1,1,0) = Local (Core) Checkstop / GX freeze' +# (x,x,1) = MASKED +#--****************************************************************************** +# -- description +#--****************************************************************************** +#-- Reset FIR +scom 0x020130C0 { + scom_data ; + 0x0000000000000000 ; + } +#-- Action 0 +scom 0x020130C6 { + scom_data ; + 0x0000000000000000 ; + } +#--- Action 1 +scom 0x020130C7 { + scom_data ; + 0x0040000010800000 ; + } +#--- Mask +scom 0x020130C3 { + scom_data ; + 0x60BD600DEF7FFFFF ; + } diff --git a/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile index 2fa3865f4..4d77cb378 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile @@ -1,9 +1,11 @@ -#-- $Id: p8.dmi.scom.initfile,v 1.10 2012/10/02 15:58:53 ttnguyen Exp $ +#-- $Id: p8.dmi.scom.initfile,v 1.11 2013/01/22 02:46:58 thomsen Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- -#-- 2.0 |pmegan |10/02/12|Removed rx_sls_extend_sel entry since its needed for slave chip only (Processor is always master on DMI) +#-- 1.11 |thomsen |01/21/13|Removed ATTR_EI_BUS_RX_MSB_LSB_SWAP & ATTR_EI_BUS_TX_MSB_LSB_SWAP as those are old now +#-- | | |Removed non-mirrored mode settings in PRBS tap id's +#-- 1.10 |pmegan |10/02/12|Removed rx_sls_extend_sel entry since its needed for slave chip only (Processor is always master on DMI) #-- 1.9 |pmegan |09/27/12|Set rx_sls_timeout_sel entry to 0b001 per defect HW220752 #-- |Set rx_sls_extend_sel entry to 0b100 per defect HW220806 #-- 1.8 |thomsen |07/13/12|Updated non-mirrored PRBS_TAP_ID's to have abcdefgabcdefgabc... pattern @@ -27,12 +29,10 @@ #-- the p8.chipunit.scominfo file. It is used to be able to select a specific clock group number. #-- Chip UNIT_POS DMI_UNIT CLOCKGRP #-- ---- -------- -------- -------- -#-- Venice: 0-3 DMI0 0-3 -#-- 4-7 DMI1 0-3 -#-- Murano: 4-7 DMI1 0-3 +#-- Venice: 0-3 DMI0 3-0 +#-- 4-7 DMI1 3-0 +#-- Murano: 4-7 DMI1 3-0 -#-- ATTR_EI_BUS_RX_MSB_LSB_SWAP is 0 for setting RX PRBS TapID's to Non-Mirrored Mode and 1 for setting to Mirrored Mode. It comes from the MRW. -#-- ATTR_EI_BUS_TX_MSB_LSB_SWAP is 0 for setting TX PRBS TapID's to Non-Mirrored Mode and 1 for setting to Mirrored Mode. It comes from the MRW. SyntaxVersion = 1 @@ -61,11 +61,6 @@ define def_bus_id2 = ((ATTR_CHIP_UNIT_POS == 1) || (ATTR_CHIP_UNIT_POS == 5)); define def_bus_id1 = ((ATTR_CHIP_UNIT_POS == 2) || (ATTR_CHIP_UNIT_POS == 6)); define def_bus_id0 = ((ATTR_CHIP_UNIT_POS == 3) || (ATTR_CHIP_UNIT_POS == 7)); -define def_rx_mirrored_mode = (ATTR_EI_BUS_RX_MSB_LSB_SWAP == 1); # Mirrored mode -define def_rx_non_mirrored_mode = (ATTR_EI_BUS_RX_MSB_LSB_SWAP == 0); # Non-Mirrored mode -define def_tx_mirrored_mode = (ATTR_EI_BUS_TX_MSB_LSB_SWAP == 1); # Mirrored mode -define def_tx_non_mirrored_mode = (ATTR_EI_BUS_TX_MSB_LSB_SWAP == 0); # Non-Mirrored mode - # See p8.chipunit.scominfo file for details of how SCOM addresses are translated by Cronus and FW based on the target unit number define def_rx_base_grp = rx_grp3; # Venice and Murano wire clkgrp3 to Cen0, clkgrp2 to Cen1, clkgrp1 to Cen2 and clkgrp0 to Cen3 define def_tx_base_grp = tx_grp3; # Venice and Murano wire clkgrp3 to Cen0, clkgrp2 to Cen1, clkgrp1 to Cen2 and clkgrp0 to Cen3 @@ -253,124 +248,100 @@ scom 0x800.0b(rx_mode_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){ #-- rx_prbs_mode_pl: rx_prbs_tap_id #--********************************************************************************************* scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_0).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_1).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_2).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_3).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_4).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_e, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_e, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_e; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_5).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_f, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_f, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_f; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_6).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_g, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_g, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_g; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_7).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_h, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_h, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_h; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_8).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_9).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_10).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_11).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_12).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_e, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_13).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_f, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_14).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_g, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_15).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_h, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_16).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_h, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_h; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_17).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_g, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_g; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_18).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_f, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_f; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_19).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_e, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_e; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_20).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_e, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_21).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_f, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_22).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_g, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b; } scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_23).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_mirrored_mode); - rx_prbs_tap_id, rx_prbs_tap_id_pattern_h, (def_rx_non_mirrored_mode); + bits, scom_data; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a; } #------------------------------------------------------------------------------------- # PER-LANE (TX: 17 lanes) @@ -379,89 +350,72 @@ scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_23).0x(dmi0_gcr_addr){ #-- tx_prbs_mode_pl: tx_prbs_tap_id #--********************************************************************************************* scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_0).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_a; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_1).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_b; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_2).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_c; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_3).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_d, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_d, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_d; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_4).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_e, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_e, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_e; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_5).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_f, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_f, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_f; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_6).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_g, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_g, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_g; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_7).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_h, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_h, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_h; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_8).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_a; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_9).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_h, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_h; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_10).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_g, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_g; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_11).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_f, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_d, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_f; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_12).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_e, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_e, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_e; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_13).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_d, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_f, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_d; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_14).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_g, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_c; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_15).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_h, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_b; } scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_16).0x(dmi0_gcr_addr){ - bits, scom_data, expr; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_mirrored_mode); - tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_non_mirrored_mode); + bits, scom_data; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_a; } #------------------------------------------------------------------------------------- # ____ __ __ diff --git a/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile index 3a7ce0d89..ba3b24b3e 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: p8.fbc.scom.initfile,v 1.3 2012/08/21 03:33:42 jmcgill Exp $ +#-- $Id: p8.fbc.scom.initfile,v 1.5 2013/01/20 19:12:33 jmcgill Exp $ #------------------------------------------------------------------------------- #-- #-- (C) Copyright International Business Machines Corp. 2011 @@ -23,8 +23,10 @@ include p8.fbc.define #-- Defines #-------------------------------------------------------------------------------- -#define def_x_is_4b = (SYS.ATTR_PROC_X_BUS_WIDTH == ENUM_ATTR_PROC_X_BUS_WIDTH_W4BYTE); -define def_x_is_4b = (0 == ENUM_ATTR_PROC_X_BUS_WIDTH_W4BYTE); +define def_x_is_4b = (SYS.ATTR_PROC_X_BUS_WIDTH == ENUM_ATTR_PROC_X_BUS_WIDTH_W4BYTE); +define xbus_enabled = (ATTR_PROC_X_ENABLE == ENUM_ATTR_PROC_X_ENABLE_ENABLE); +define abus_enabled = (ATTR_PROC_A_ENABLE == ENUM_ATTR_PROC_A_ENABLE_ENABLE); +define pcie_enabled = (ATTR_PROC_PCIE_ENABLE == ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE); #-------------------------------------------------------------------------------- @@ -34,74 +36,74 @@ define def_x_is_4b = (0 == ENUM_ATTR_PROC_X_BUS_WIDTH_W4BYTE); #-- PB Mode Register (PB_MODE / 0x02010C[048]A) scom 0x02010C(0,4,8)A { bits, scom_data; - chip_is_system, 0b1; #-- single chip - avp_mode, 0b0; #-- AVP mode (TODO: link to attribute) - sw_ab_wait, 0x0; #-- no delay - sp_hw_mark, 0x20; #-- 32 - gp_hw_mark, 0x20; #-- 32 - lcl_hw_mark, 0x20; #-- 32 - e2e_hw_mark, 0x40; #-- 64 - fp_hw_mark, 0x20; #-- 32 - switch_option_ab, 0b0; #-- no switch CD on switch AB - cpu_ratio_override, 0b000; #-- rcmd queue depth = 16 + chip_is_system, 0b1; #-- single chip + avp_mode, 0b0; #-- AVP mode (TODO: link to attribute) + sw_ab_wait, 0x0; #-- no delay + sp_hw_mark, 0x20; #-- 32 + gp_hw_mark, 0x20; #-- 32 + lcl_hw_mark, 0x20; #-- 32 + e2e_hw_mark, 0x40; #-- 64 + fp_hw_mark, 0x20; #-- 32 + switch_option_ab, 0b0; #-- no switch CD on switch AB + cpu_ratio_override, 0b000; #-- rcmd queue depth = 16 } #-- PB Trace Array Select Configuration Register (PB_EVENT_TRACE / 0x02010C4F) scom 0x02010C4F { bits, scom_data; - sn0_select, 0b10; #-- rcmd 0 - sn1_select, 0b10; #-- rcmd 1 - cr0_select, 0b10; #-- cresp 0 / presp 0 - cr1_select, 0b10; #-- cresp 1 / presp 1 - rt0_select, 0b10; #-- rtag NW - rt1_select, 0b001; #-- MCD - dat_select, 0b000000; #-- none + sn0_select, 0b10; #-- rcmd 0 + sn1_select, 0b10; #-- rcmd 1 + cr0_select, 0b10; #-- cresp 0 / presp 0 + cr1_select, 0b10; #-- cresp 1 / presp 1 + rt0_select, 0b10; #-- rtag NW + rt1_select, 0b001; #-- MCD + dat_select, 0b000000; #-- none } #-- PB Node Master Power Management Counter Register (PB_NMPM_COUNTER / 0x2010C50) scom 0x02010C50 { bits, scom_data; - apm_en, 0b0; #-- set shared counters to PMU mode - pmucnt_en, 0b1; #-- set shared counters to PMU mode - pmucnt_sel, 0b11; #-- PMU counter select = rcmd 0 OR rcmd 1 + apm_en, 0b0; #-- set shared counters to PMU mode + pmucnt_en, 0b1; #-- set shared counters to PMU mode + pmucnt_sel, 0b11; #-- PMU counter select = rcmd 0 OR rcmd 1 } #-- MCD Debug Configuration Register (MCD_DBG / 0x02013416) scom 0x02013416 { bits, scom_data; - mcd_debug_enable, 0b1; #-- enable debug clocks - mcd_debug_select, 0b1000; #-- default debug bus select + mcd_debug_enable, 0b1; #-- enable debug clocks + mcd_debug_select, 0b1000; #-- default debug bus select } #-- PB X Link Mode Register (PB_X_MODE / 0x04010C0A) scom 0x04010C0A { bits, scom_data, expr; - x_avp_mode, 0b0, any; #-- X AVP mode (TODO: link to attribute) - x_4b_mode, 0b1, (def_x_is_4b); #-- X bus 4/8B switch + x_avp_mode, 0b0, (xbus_enabled); #-- X AVP mode (TODO: link to attribute) + x_4b_mode, 0b1, (xbus_enabled) && (def_x_is_4b); #-- X bus 4/8B switch } #-- PB A Link Mode Register (PB_IOA_MODE / 0x0801080A) scom 0x0801080A { - bits, scom_data; - a_avp_mode, 0b0; #-- A AVP mode (TODO: link to attribute) + bits, scom_data, expr; + a_avp_mode, 0b0, (abus_enabled); #-- A AVP mode (TODO: link to attribute) } #-- PB A Link Framer Configuration Register (PB_IOA_FMR_CFG / 0x08010813) scom 0x08010813 { - bits, scom_data; - a_ow_pack, 0b0; #-- OW pack disabled - a_ow_pack_priority, 0b0; #-- low priority + bits, scom_data, expr; + a_ow_pack, 0b0, (abus_enabled); #-- OW pack disabled + a_ow_pack_priority, 0b0, (abus_enabled); #-- low priority } #-- PB F Link Mode Register (PB_IOF_MODE / 0x0901080A) scom 0x0901080A { - bits, scom_data; - f_avp_mode, 0b0; #-- F AVP mode (TODO: link to attribute) + bits, scom_data, expr; + f_avp_mode, 0b0, (pcie_enabled); #-- F AVP mode (TODO: link to attribute) } #-- PB F Link Framer Configuration Register (PB_IOF_FMR_CFG / 0x09010813) scom 0x09010813 { - bits, scom_data; - f_ow_pack, 0b0; #-- OW pack disabled - f_ow_pack_priority, 0b0; #-- low priority + bits, scom_data, expr; + f_ow_pack, 0b0, (pcie_enabled); #-- OW pack disabled + f_ow_pack_priority, 0b0, (pcie_enabled); #-- low priority } diff --git a/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile new file mode 100644 index 000000000..ef2c6b7b7 --- /dev/null +++ b/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile @@ -0,0 +1,107 @@ +#-- $Id: p8.mcs.scom.initfile,v 1.1 2012/10/08 03:24:14 jmcgill Exp $ +#-- CHANGE HISTORY: +#-------------------------------------------------------------------------------- +#-- Version:|Author: | Date: | Comment: +#-- --------|--------|--------|-------------------------------------------------- +#-- 1.00|baysah |08/12/12|Created MCS init file +#-- --------|--------|--------|-------------------------------------------------- +#-------------------------------------------------------------------------------- +# End of revision history +#-------------------------------------------------------------------------------- + +#--Master list of variables that can be used in this file is at: +#--<Attribute Definition Location> + +SyntaxVersion = 1 + + +#--****************************************************************************** +#-- MC Mode0 Register Ship Mode +#--****************************************************************************** + scom 0x0000000002011807 { + bits , scom_data ; + 0 , 0b1 ; # MCMODE0Q_ENABLE_CMD_BYP_STUTTER + 1 , 0b1 ; # MCMODE0Q_RESERVED Reserved + 2 , 0b1 ; # MCMODE0Q_ENABLE_NS_RD_AO_SFU_FOR_DCBZ + 3 , 0b1 ; # MCMODE0Q_ENABLE_CENTAUR_LOCAL_CHECKSTOP_COMMAND + 4:7 , 0xF ; # MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD + 8:11 , 0x0 ; # MCMODE0Q_Number_of_CL_Entries_Reserved_for_Read + 12:15, 0x1 ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_MIRRORED_OPS + 16:19, 0x0 ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_WRITES + 20:23, 0x1 ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_CP_WRITES + 24:27, 0x1 ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_CP_IG + 28:31, 0x0 ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_HTM_OPS + 32:35, 0x0 ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_HA_ASSIST + 36 , 0b1 ; # MCMODE0Q_MCFGRP_19_IS_HO_BIT + 37 , 0b1 ; # MCMODE0Q_CL_CHANNEL_TIMEOUT_FORCES_CHANNEL_FAIL + 38 , 0b1 ; # MCMODE0Q_ENABLE_FAULT_LINE_FOR_GLOBAL_CHECKSTOP + 39:43, 0b00000 ; # MCMODE0Q_RESERVED_39_43 Reserved + 44:52, 0b001100010 ; # MCMODE0Q_ADDRESS_COLLISION_MODES + 53 , 0b0 ; # MCMODE0Q_INCLUDE_CP_IG_IN_CP_WRITE_FULLNESS_GROUP + 54 , 0b1 ; # MCMODE0Q_ENABLE_DMAWR_CMD_BIT + 55 , 0b0 ; # MCMODE0Q_ENABLE_READ_LFSR_DATA + 56 , 0b0 ; # MCMODE0Q_FORCE_CHANNEL_FAIL + 57 , 0b0 ; # MCMODE0Q_DISABLE_READ_CRC_ECC_BYPASS_TAKEN + 58 , 0b0 ; # MCMODE0Q_DISABLE_CL_AO_QUEUES + 59:60, 0b00 ; # MCMODE0Q_ADDRESS_SELECT_LFSR_VALUE (4k) + 61 , 0b0 ; # MCMODE0Q_ENABLE_CENTAUR_SYNC + 62 , 0b0 ; # MCMODE0Q_WRITE_DATA_BUFFER_ECC_CHECK_DISABLE + 63 , 0b0 ; # MCMODE0Q_WRITE_DATA_BUFFER_ECC_CORRECT_DISABLE + + } + + +#--****************************************************************************** +#-- MC Mode2 Register Ship Mode +#--****************************************************************************** + scom 0x0000000002011809 { + bits , scom_data ; + 0 , 0b0 ; # MCMODE2Q_FORCE_SFSTAT_GLOBAL + 1:13 , 0b0000000000000 ; # MCMODE2Q_DISABLE_WRITE_MDI_TO_ZERO + 14 , 0b0 ; # MCMODE2Q_DISABLE_SFU_OPERATIONS + 15 , 0b0 ; # MCMODE2Q_DISABLE_FASTPATH_QOS + 16 , 0b0 ; # MCMODE2Q_ENABLE_2K_SPEC_READ_DISABLE_COUNTERS + 17 , 0b0 ; # MCMODE2Q_ENABLE_ZERO_SPEC_HASH_ADDR_48_TO_50 + 18 , 0b0 ; # MCMODE2Q_DISABLE_SPEC_DISABLE_HINT_BIT + 19 , 0b0 ; # MCMODE2Q_ENABLE_RESET_2K_COUNT_IF_HINT_BIT_SET + 20:23, 0x0 ; # MCMODE2Q_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT + 24:27, 0x0 ; # MCMODE2Q_D2K_SPEC_FILTER_COUNTER_LFSR_DEC__SELECT + 28 , 0b0 ; # MCMODE2Q_SPEC_READ_FILTER_NO_HASH_MODE + 29 , 0b1 ; # MCMODE2Q_ENABLE_CHANNEL_HANG + 30:35, 0b111111 ; # MCMODE2Q_READ_SPECULATION_DISABLE_THRESHOLD + 36:38, 0b010 ; # MCMODE2Q_CHANNEL_ARB_WRITE_HP_THRESHOLD + 39 , 0b0 ; # MCMODE2Q_DISABLE_BAD_CRESP_TO_CENTAUR + 40 , 0b1 ; # MCMODE2Q_ENABLE_CRC_BYPASS_ALWAYS + 41:43, 0b111 ; # MCMODE2Q_CHANNEL_HANG_VALUE + 44 , 0b1 ; # MCMODE2Q_ENABLE_RD_HANG + 45 , 0b1 ; # MCMODE2Q_ENABLE_WR_HANG + 46 , 0b1 ; # MCMODE2Q_ENABLE_MIRROR_RD_HANG + 47 , 0b1 ; # MCMODE2Q_ENABLE_MIRROR_WR_HANG + 48 , 0b1 ; # MCMODE2Q_ENABLE_AO_HANG + 49 , 0b1 ; # MCMODE2Q_ENABLE_INBAND_HANG + 50:52, 0b111 ; # MCMODE2Q_NONMIRROR_HANG_VALUE + 53:55, 0b111 ; # MCMODE2Q_MIRROR_HANG_VALUE + 56 , 0b1 ; # MCMODE2Q_ENABLE_EMER_THROTTLE + 57 , 0b0 ; # MCMODE2Q_DRIVE_SHARED_PRESP_WITH_LOST_CLAIM + 58 , 0b0 ; # MCMODE2Q_DISABLE_SHARED_PRESP_ABORT + 59 , 0b0 ; # MCMODE2Q_DISABLE_RTY_LOST_CLAIM_PRESP + 60 , 0b0 ; # MCMODE2Q_DRIVE_BC4_WRITE_COMMAND + 61 , 0b1 ; # MCMODE2Q_ENABLE_CENTAUR_CHECKSTOP_COMMAND + 62 , 0b1 ; # MCMODE2Q_ENABLE_CENTAUR_TRACESTOP_COMMAND + 63 , 0b0 ; # MCMODE2Q_ENABLE_EVENT_BUS_B + + } + + +#--****************************************************************************** +#-- MC Busy Control Register Ship Mode +#--****************************************************************************** + scom 0x0000000002011818 { + bits , scom_data ; + 0 , 0b0 ; # MCBUSYQ_ENABLE_BUSY_COUNTERS + 1:3 , 0b100 ; # MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT (256 Cycles) + 4:13 , 0b0000000000 ; # MCBUSYQ_BUSY_COUNTER_THRESHOLD0 + 14:23, 0b0000000000 ; # MCBUSYQ_BUSY_COUNTER_THRESHOLD1 + 24:33, 0b0000000000 ; # MCBUSYQ_BUSY_COUNTER_THRESHOLD2 + 34:43, 0b0000000000 ; # MCBUSYQ_BUSY_COUNTER_THRESHOLD3 +}
\ No newline at end of file diff --git a/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile new file mode 100644 index 000000000..379e3c945 --- /dev/null +++ b/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile @@ -0,0 +1,337 @@ +#-- $Id: p8.nx.scom.initfile,v 1.2 2013/01/10 21:31:50 johnre Exp $ +#------------------------------------------------------------------------------- +#-- +#-- (C) Copyright International Business Machines Corp. 2011 +#-- All Rights Reserved -- Property of IBM +#-- *** IBM Confidential *** +#-- +#-- TITLE : p8.nx.scom.initfile +#-- DESCRIPTION : Perform NX configuration +#-- +#-- OWNER NAME : John Reilly Email: johnre@us.ibm.com +#-- +#-------------------------------------------------------------------------------- + +SyntaxVersion = 1 + +#-------------------------------------------------------------------------------- +#-- Includes +#-------------------------------------------------------------------------------- + +#-------------------------------------------------------------------------------- +#-- Defines +#-------------------------------------------------------------------------------- +define eft_ci = ( ((8*ATTR_FABRIC_NODE_ID) + (ATTR_FABRIC_CHIP_ID) + 1) * 4) ; +define sym_ci = ( ((8*ATTR_FABRIC_NODE_ID) + (ATTR_FABRIC_CHIP_ID) + 1) * 4) ; +define asym_ci = ( ((8*ATTR_FABRIC_NODE_ID) + (ATTR_FABRIC_CHIP_ID) + 1) * 16); + + +#-------------------------------------------------------------------------------- +#-- SCOM initializations +#-------------------------------------------------------------------------------- + +#-- Engine Enable Register (0x02013041) +scom 0x02013041 { + bits , scom_data ; + 53 , 0b1 ; #-- ch7 ASYM enable + 54 , 0b1 ; #-- ch6 ASYM enable + 55 , 0b1 ; #-- ch5 ASYM enable + 56 , 0b1 ; #-- ch4 ASYM enable + 57 , 0b1 ; #-- ch3 SYM enable + 58 , 0b1 ; #-- ch2 SYM enable + 62 , 0b1 ; #-- ch1 842 enable + 63 , 0b1 ; #-- ch0 842 enable +} + + +#-- DMA Config Register (0x02013042) +scom 0x02013042 { + bits , scom_data ; + 23 , 0b1 ; #-- 842 comp prefetch hint enable + 24 , 0b1 ; #-- 842 decomp prefetch hint enable + 25:28 , 0b0011 ; #-- max sym reads + 29:32 , 0b0001 ; #-- max amf reads + 33:36 , 0b1101 ; #-- max comp reads + 37:40 , 0b0111 ; #-- max decomp reads + 41:42 , 0b01 ; #-- sym csb write type 01:128B cache inject + 43:44 , 0b01 ; #-- sym comp write type 01:128B cache inject + 45:46 , 0b10 ; #-- sym cpb write type 10:128B cache inject + 47 , 0b0 ; #-- sym data write type 0:DMA write + 49:50 , 0b01 ; #-- amf csb write type 01:128B cache inject + 51:52 , 0b01 ; #-- amf comp write type 01:128B cache inject + 55 , 0b0 ; #-- amf data write type 0:DMA write + 56 , 0b0 ; #-- 842 spbc write enable + 57:58 , 0b01 ; #-- 842 csb write type 01:128B cache inject + 59:60 , 0b01 ; #-- 842 comp write type 01:128B cache inject + 61:62 , 0b10 ; #-- 842 cpb write type 10:128B cache inject + 63 , 0b0 ; #-- 842 data write type 0:DMA write +} + + +#-- Symmetric Coprocessor Config Register (0x0201308A) +scom 0x0201308A { + bits , scom_data ; + 2:14 , sym_ci ; #-- sym CI. function of node, chip id + 18:23 , 0b000001 ; #-- sym CT + 32:39 , 0b10110010 ; #-- sym FC mask. enable 0,2,3,6 + 63 , 0b1 ; #-- sym enable +} + + +#-- Asymmetric Coprocessor Config Register (0x0201308B) +scom 0x0201308B { + bits , scom_data ; + 2:14 , asym_ci ; #-- asym CI. function of node, chip id + 18:23 , 0b000010 ; #-- asym CT + 32:55 , 0xfffff8 ; #-- asym FC mask. enable 0-20 + 63 , 0b1 ; #-- asym enable +} + + +#-- 842 Coprocessor Config Register (0x0201308C) +scom 0x0201308C { + bits , scom_data ; + 2:14 , eft_ci ; #-- 842 CI. function of node, chip id + 18:23 , 0b000000 ; #-- 842 CT + 32:36 , 0b11111 ; #-- 842 FC mask. enable 0-4 + 63 , 0b1 ; #-- 842 enable +} + + +#-- RNG Config Register (0x02013092) +scom 0x02013092 { + bits , scom_data ; + 46:61 , 0x07cf ; #-- RNG pacing. 0x07CF=1999. 2000 cycles between samples + 63 , 0b1 ; #-- RNG enable +} + + +#-- ICS Lite Config Register (0x02013093) +scom 0x02013093 { + bits , scom_data ; + 8:15 , 0x00 ; #-- trusted interrupt priority + 16:31 , 0x0000 ; #-- trusted interrupt server + 44:47 , 0b1100 ; #-- time to wait before resending returned interrupts. average 12*856ns + 54:63 , 0b0 ; #-- number of returns before issuing trusted interrupt. 0=never +} + + +#-- NX BUID Config Register (0x0201308E) +scom 0x0201308E { + bits , scom_data ; + 0 , 0b0 ; #-- BUID enable + 1:2 , ATTR_FABRIC_NODE_ID ; #-- BUID Base(0:1) Node Id ???? + 3:5 , ATTR_FABRIC_CHIP_ID ; #-- BUID Base(2:4) Chip Id ???? + 6:19 , 0x00000 ; #-- BUID Base(5:18) ???? + 20:32 , 0b0000 ; #-- BUID Mask(6:18). Mask(0:5)=0b111111 +} + + +#-- NX Cop_Req Input Queue Config Register (0x0201308F) +scom 0x0201308F { + bits , scom_data ; + 0:2 , 0b001 ; #-- SYM max extra queue entries. 2 total = 1 dedicated + 1 floating + 3:5 , 0b000 ; #-- ASYM max extra queue entries. 1 total = just 1 dedicated +} + + +#-- PowerBus Epsilon Config Register (0x0201309D) +scom 0x0201309D { + bits , scom_data ; + 0:5 , 0b000101 ; #-- epsilon count value. number * 7 clock cycles. + 6 , 0b0 ; #-- disable epsilon counter +} + + +#-- NX Miscellaneous Control Register (0x020130A8) +#scom 0x020130A8 { +# bits , scom_data ; +# 0 , 0b1 ; #-- enable NX interrupts to PowerBus. reset value = 0b1 +# 1 , 0b1 ; #-- enable AS interrupts to PowerBus. reset value = 0b1 +#} + + +#-- PBI FIR Mask Register (0x02013083) +scom 0x02013083 { + bits , scom_data ; + 0 , 0b0 ; #-- PBI internal parity error + 1 , 0b0 ; #-- PowerBus CE error + 2 , 0b0 ; #-- PowerBus UE error + 3 , 0b1 ; #-- mask PowerBus SUE error + 4 , 0b0 ; #-- Inbound array CE error + 5 , 0b0 ; #-- Inbound array UE error + 6 , 0b0 ; #-- PowerBus data hang error + 7 , 0b1 ; #-- mask PowerBus command hang error + 8 , 0b0 ; #-- PowerBus read address error + 9 , 0b0 ; #-- PowerBus write address error + 10 , 0b0 ; #-- PowerBus miscellaneous error + 11 , 0b0 ; #-- MMIO BAR parity error + 12 , 0b0 ; #-- CRB kill ISN received while holding ISN with UE error + 13 , 0b0 ; #-- ACK_DEAD cresp received by read command + 14 , 0b0 ; #-- ACK_DEAD cresp received by write command + 15 , 0b0 ; #-- Link check aborted while waiting on data + 16 , 0b0 ; #-- Hang poll time expired on internal transfer + 17 , 0b1 ; #-- mask FIR/SCOM satellite parity error + 18 , 0b1 ; #-- mask FIR/SCOM satellite parity error duplicate +} + + +#-- PBI FIR Action0,1 Register (0x02013086,7) +#-- action0,1 = 00 : checkstop +#-- 01 : recoverable +#-- 10 : unused +#-- 11 : local checkstop +scom 0x02013086 { + bits , scom_data ; #--Action + 0 , 0b0 ; #-- 0b00 PBI internal parity error + 1 , 0b0 ; #-- 0b01 PowerBus CE error + 2 , 0b0 ; #-- 0b01 PowerBus UE error + 3 , 0b0 ; #-- 0b00 mask PowerBus SUE error + 4 , 0b0 ; #-- 0b01 Inbound array CE error + 5 , 0b0 ; #-- 0b01 Inbound array UE error + 6 , 0b0 ; #-- 0b01 PowerBus data hang error + 7 , 0b0 ; #-- 0b00 mask PowerBus command hang error + 8 , 0b0 ; #-- 0b00 PowerBus read address error + 9 , 0b0 ; #-- 0b00 PowerBus write address error + 10 , 0b0 ; #-- 0b01 PowerBus miscellaneous error + 11 , 0b0 ; #-- 0b01 MMIO BAR parity error + 12 , 0b1 ; #-- 0b11 CRB kill ISN received while holding ISN with UE error + 13 , 0b0 ; #-- 0b01 ACK_DEAD cresp received by read command + 14 , 0b0 ; #-- 0b01 ACK_DEAD cresp received by write command + 15 , 0b0 ; #-- 0b01 Link check aborted while waiting on data + 16 , 0b0 ; #-- 0b01 Hang poll time expired on internal transfer + 17 , 0b0 ; #-- 0b00 mask FIR/SCOM satellite parity error + 18 , 0b0 ; #-- 0b00 mask FIR/SCOM satellite parity error duplicate +} +scom 0x02013087 { + bits , scom_data ; #--Action + 0 , 0b0 ; #-- 0b00 PBI internal parity error + 1 , 0b1 ; #-- 0b01 PowerBus CE error + 2 , 0b1 ; #-- 0b01 PowerBus UE error + 3 , 0b0 ; #-- 0b00 mask PowerBus SUE error + 4 , 0b1 ; #-- 0b01 Inbound array CE error + 5 , 0b1 ; #-- 0b01 Inbound array UE error + 6 , 0b1 ; #-- 0b01 PowerBus data hang error + 7 , 0b0 ; #-- 0b00 mask PowerBus command hang error + 8 , 0b0 ; #-- 0b00 PowerBus read address error + 9 , 0b0 ; #-- 0b00 PowerBus write address error + 10 , 0b1 ; #-- 0b01 PowerBus miscellaneous error + 11 , 0b1 ; #-- 0b01 MMIO BAR parity error + 12 , 0b1 ; #-- 0b11 CRB kill ISN received while holding ISN with UE error + 13 , 0b1 ; #-- 0b01 ACK_DEAD cresp received by read command + 14 , 0b1 ; #-- 0b01 ACK_DEAD cresp received by write command + 15 , 0b1 ; #-- 0b01 Link check aborted while waiting on data + 16 , 0b1 ; #-- 0b01 Hang poll time expired on internal transfer + 17 , 0b0 ; #-- 0b00 mask FIR/SCOM satellite parity error + 18 , 0b0 ; #-- 0b00 mask FIR/SCOM satellite parity error duplicate +} + + +#-- DMA/Engine FIR Mask Register (0x02013103) +scom 0x02013103 { + bits , scom_data ; + 0 , 0b1 ; #-- mask Reserved + 1 , 0b0 ; #-- ICS invalid state error FIR bit + 2:3 , 0b11 ; #-- mask Reserved + 4 , 0b0 ; #-- Channel 0 842 array corrected ECC error FIR bit" ; + 5 , 0b0 ; #-- Channel 0 842 array uncorrectable ECC error FIR bit" ; + 6 , 0b0 ; #-- Channel 1 842 array corrected ECC error FIR bit" ; + 7 , 0b0 ; #-- Channel 1 842 array uncorrectable ECC error FIR bit" ; + 8 , 0b1 ; #-- mask DMA non-zero CSB CC detected FIR bit. Programming error." ; + 9 , 0b0 ; #-- DMA array correctable ECC error FIR bit" ; + 10 , 0b0 ; #-- DMA outbound write/inbound read correctable ECC error FIR bit" ; + 11:13 , 0b000 ; #-- Channel 5,6,7 AMF array corrected ECC error FIR bit" ; + 14 , 0b1 ; #-- mask Error from other SCOM satellites FIR bit" ; + 15 , 0b0 ; #-- DMA invalid state error FIR bit. Unrecoverable despite name" ; + 16 , 0b0 ; #-- DMA invalid state error FIR bit" ; + 17 , 0b0 ; #-- DMA array uncorrectable ECC error FIR bit" ; + 18 , 0b0 ; #-- DMA outbound write/inbound read uncorrectable ECC error FIR bit" ; + 19 , 0b0 ; #-- DMA inbound read error FIR bit" ; + 20:27 , 0b00000000 ; #-- Channel 0-7 invalid state error FIR bit" ; + 28:30 , 0b000 ; #-- Channel 5,6,7 AMF array uncorrectable ECC error FIR bit" ; + 31 , 0b0 ; #-- UE error on CRB(CSB address, CCB) FIR bit" ; + 32 , 0b0 ; #-- SUE error on CRB(CSB address, CCB) FIR bit" ; + 33 , 0b1 ; #-- mask SUE error on something other than CRB(CSB address, CCB) FIR bit" ; + 34 , 0b1 ; #-- mask Reserved + 35 , 0b1 ; #-- mask Reserved + 36 , 0b0 ; #-- Channel 4 AMF array corrected ECC error FIR bit" ; + 37 , 0b0 ; #-- Channel 4 AMF array uncorrectable ECC error FIR bit" ; + 38:47 , 0b1111111111 ; #-- mask Reserved + 48 , 0b1 ; #-- mask FIR/SCOM satellite parity error FIR bit" ; + 49 , 0b1 ; #-- mask FIR/SCOM satellite parity error FIR bit duplicate" +} + + +#-- DMA/Engine Action0/1 Registers (0x02013106,07) +#-- action0,1 = 00 : checkstop +#-- 01 : recoverable +#-- 10 : unused +#-- 11 : local checkstop +scom 0x02013106 { + bits , scom_data ; #--Action + 0 , 0b0 ; #-- 0b00 mask Reserved + 1 , 0b1 ; #-- 0b11 ICS invalid state error FIR bit + 2:3 , 0b00 ; #-- 0b00 mask Reserved + 4 , 0b0 ; #-- 0b01 Channel 0 842 array corrected ECC error FIR bit" ; + 5 , 0b0 ; #-- 0b01 Channel 0 842 array uncorrectable ECC error FIR bit" ; + 6 , 0b0 ; #-- 0b01 Channel 1 842 array corrected ECC error FIR bit" ; + 7 , 0b0 ; #-- 0b01 Channel 1 842 array uncorrectable ECC error FIR bit" ; + 8 , 0b0 ; #-- 0b00 mask DMA non-zero CSB CC detected FIR bit. Programming error." ; + 9 , 0b0 ; #-- 0b01 DMA array correctable ECC error FIR bit" ; + 10 , 0b0 ; #-- 0b01 DMA outbound write/inbound read correctable ECC error FIR bit" ; + 11:13 , 0b000 ; #-- 0b01 Channel 5,6,7 AMF array corrected ECC error FIR bit" ; + 14 , 0b0 ; #-- 0b00 mask Error from other SCOM satellites FIR bit" ; + 15 , 0b1 ; #-- 0b11 DMA invalid state error FIR bit. Unrecoverable despite name" ; + 16 , 0b1 ; #-- 0b11 DMA invalid state error FIR bit" ; + 17 , 0b0 ; #-- 0b01 DMA array uncorrectable ECC error FIR bit" ; + 18 , 0b0 ; #-- 0b01 DMA outbound write/inbound read uncorrectable ECC error FIR bit" ; + 19 , 0b0 ; #-- 0b01 DMA inbound read error FIR bit" ; + 20:27 , 0b11111111 ; #-- 0b11 Channel 0-7 invalid state error FIR bit" ; + 28:30 , 0b000 ; #-- 0b01 Channel 5,6,7 AMF array uncorrectable ECC error FIR bit" ; + 31 , 0b1 ; #-- 0b11 UE error on CRB(CSB address, CCB) FIR bit" ; + 32 , 0b1 ; #-- 0b11 SUE error on CRB(CSB address, CCB) FIR bit" ; + 33 , 0b0 ; #-- 0b00 mask SUE error on something other than CRB(CSB address, CCB) FIR bit" ; + 34 , 0b0 ; #-- 0b00 mask Reserved + 35 , 0b0 ; #-- 0b00 mask Reserved + 36 , 0b0 ; #-- 0b01 Channel 4 AMF array corrected ECC error FIR bit" ; + 37 , 0b0 ; #-- 0b01 Channel 4 AMF array uncorrectable ECC error FIR bit" ; + 38:47 , 0b0000000000 ; #-- 0b00 mask Reserved + 48 , 0b0 ; #-- 0b00 mask FIR/SCOM satellite parity error FIR bit" ; + 49 , 0b0 ; #-- 0b00 mask FIR/SCOM satellite parity error FIR bit duplicate" +} +scom 0x02013107 { + bits , scom_data ; #--Action + 0 , 0b0 ; #-- 0b00 mask Reserved + 1 , 0b1 ; #-- 0b11 ICS invalid state error FIR bit + 2:3 , 0b00 ; #-- 0b00 mask Reserved + 4 , 0b1 ; #-- 0b01 Channel 0 842 array corrected ECC error FIR bit" ; + 5 , 0b1 ; #-- 0b01 Channel 0 842 array uncorrectable ECC error FIR bit" ; + 6 , 0b1 ; #-- 0b01 Channel 1 842 array corrected ECC error FIR bit" ; + 7 , 0b1 ; #-- 0b01 Channel 1 842 array uncorrectable ECC error FIR bit" ; + 8 , 0b0 ; #-- 0b00 mask DMA non-zero CSB CC detected FIR bit. Programming error." ; + 9 , 0b1 ; #-- 0b01 DMA array correctable ECC error FIR bit" ; + 10 , 0b1 ; #-- 0b01 DMA outbound write/inbound read correctable ECC error FIR bit" ; + 11:13 , 0b111 ; #-- 0b01 Channel 5,6,7 AMF array corrected ECC error FIR bit" ; + 14 , 0b0 ; #-- 0b00 mask Error from other SCOM satellites FIR bit" ; + 15 , 0b1 ; #-- 0b11 DMA invalid state error FIR bit. Unrecoverable despite name" ; + 16 , 0b1 ; #-- 0b11 DMA invalid state error FIR bit" ; + 17 , 0b1 ; #-- 0b01 DMA array uncorrectable ECC error FIR bit" ; + 18 , 0b1 ; #-- 0b01 DMA outbound write/inbound read uncorrectable ECC error FIR bit" ; + 19 , 0b1 ; #-- 0b01 DMA inbound read error FIR bit" ; + 20:27 , 0b11111111 ; #-- 0b11 Channel 0-7 invalid state error FIR bit" ; + 28:30 , 0b111 ; #-- 0b01 Channel 5,6,7 AMF array uncorrectable ECC error FIR bit" ; + 31 , 0b1 ; #-- 0b11 UE error on CRB(CSB address, CCB) FIR bit" ; + 32 , 0b1 ; #-- 0b11 SUE error on CRB(CSB address, CCB) FIR bit" ; + 33 , 0b0 ; #-- 0b00 mask SUE error on something other than CRB(CSB address, CCB) FIR bit" ; + 34 , 0b0 ; #-- 0b00 mask Reserved + 35 , 0b0 ; #-- 0b00 mask Reserved + 36 , 0b1 ; #-- 0b01 Channel 4 AMF array corrected ECC error FIR bit" ; + 37 , 0b1 ; #-- 0b01 Channel 4 AMF array uncorrectable ECC error FIR bit" ; + 38:47 , 0b0000000000 ; #-- 0b00 mask Reserved + 48 , 0b0 ; #-- 0b00 mask FIR/SCOM satellite parity error FIR bit" ; + 49 , 0b0 ; #-- 0b00 mask FIR/SCOM satellite parity error FIR bit duplicate" +} + + + + diff --git a/src/usr/hwpf/hwp/initfiles/p8.pe.phase1.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.pe.phase1.scom.initfile index 892b3c1f6..6b2d79725 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.pe.phase1.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.pe.phase1.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: p8.pe.phase1.scom.initfile,v 1.1 2012/11/05 21:39:30 jmcgill Exp $ +#-- $Id: p8.pe.phase1.scom.initfile,v 1.2 2013/01/02 03:18:01 jmcgill Exp $ #------------------------------------------------------------------------------- #-- #-- (C) Copyright International Business Machines Corp. 2011 @@ -67,6 +67,102 @@ scom 0x800008810901143F { 48:63, ATTR_PROC_PCIE_IOP_PCS_CONTROL1[0]; } +#-- TX FIFO Control Register (A0) +scom 0x800004000901143F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (A1) +scom 0x800004400901143F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (A2) +scom 0x800004800901143F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (A3) +scom 0x800004C00901143F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (A4) +scom 0x800005000901143F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (A5) +scom 0x800005400901143F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (A6) +scom 0x800005800901143F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (A7) +scom 0x800005C00901143F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (B0) +scom 0x800006000901143F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (B1) +scom 0x800006400901143F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (B2) +scom 0x800006800901143F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (B3) +scom 0x800006C00901143F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (B4) +scom 0x800007000901143F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (B5) +scom 0x800007400901143F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (B6) +scom 0x800007800901143F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (B7) +scom 0x800007C00901143F { + bits, scom_data; + 53:56, 0b1111; +} + #-- TX FIFO Offset Register (A0) scom 0x800004010901143F { bits, scom_data; @@ -696,6 +792,102 @@ scom 0x800008810901187F { 48:63, ATTR_PROC_PCIE_IOP_PCS_CONTROL1[1]; } +#-- TX FIFO Control Register (A0) +scom 0x800004000901187F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (A1) +scom 0x800004400901187F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (A2) +scom 0x800004800901187F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (A3) +scom 0x800004C00901187F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (A4) +scom 0x800005000901187F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (A5) +scom 0x800005400901187F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (A6) +scom 0x800005800901187F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (A7) +scom 0x800005C00901187F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (B0) +scom 0x800006000901187F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (B1) +scom 0x800006400901187F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (B2) +scom 0x800006800901187F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (B3) +scom 0x800006C00901187F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (B4) +scom 0x800007000901187F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (B5) +scom 0x800007400901187F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (B6) +scom 0x800007800901187F { + bits, scom_data; + 53:56, 0b1111; +} + +#-- TX FIFO Control Register (B7) +scom 0x800007C00901187F { + bits, scom_data; + 53:56, 0b1111; +} + #-- TX FIFO Offset Register (A0) scom 0x800004010901187F { bits, scom_data; diff --git a/src/usr/hwpf/hwp/initfiles/p8.xbus.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.xbus.scom.initfile index c6b4200e8..8c876c75d 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.xbus.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.xbus.scom.initfile @@ -1,8 +1,10 @@ -#-- $Id: p8.xbus.scom.initfile,v 1.3 2012/08/01 05:31:13 thomsen Exp $ +#-- $Id: p8.xbus.scom.initfile,v 1.4 2012/09/27 15:14:37 ttnguyen Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.4 |pmegan |09/27/12|Set rx_sls_timeout_sel to 0b001 per defect HW220752 +#-- | | |Set rx_sls_extend_sel to 0b100 on slave chip per defect HW220806 #-- 1.3 |thomsen |07/31/12|Removed mirrored PRBS tap entries since Xbus doesn't support end-for-end swapping #-- | | |Changed per-group writes with the same data being written into all groups into group broadcast writes to save scom's #-- 1.2 |jmcgill |07/27/12|Cleanup to run on VBU, edit to match scan initfile @@ -12,6 +14,7 @@ #-------------------------------------------------------------------------------- # End of revision history #-------------------------------------------------------------------------------- + #--Master list of variables that can be used in this file is at: #--<Attribute Definition Location> #-- ATTR_EI_BUS_RX_MSB_LSB_SWAP is 0 for setting RX PRBS TapID's to Non-Mirrored Mode and 1 for setting to Mirrored Mode. It comes from the MRW. @@ -822,6 +825,34 @@ scom 0x800.0b(rx_ei4_cal_cntl_pp)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(x rx_block_lock_lane, 0b1; } +#------------------------------------------------------------------------------------- +# ____ _ __ _______ _____ __ +# / __ \ |/ / /_ __(_)___ ___ ___ _____ / ___/___ / / +# / /_/ / / / / / / __ `__ \/ _ \/ ___/ \__ \/ _ \/ / +# / _, _/ | / / / / / / / / / __/ / ___/ / __/ / +#/_/ |_/_/|_| /_/ /_/_/ /_/ /_/\___/_/ /____/\___/_/ +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +#-- rx_timeout_sel_pg: rx_sls_timeout_sel +#--********************************************************************************************* +scom 0x800.0b(rx_timeout_sel_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data; + rx_sls_timeout_sel, 0b001; # Set this entry to 0b001 per defect HW220752 +} +#------------------------------------------------------------------------------------- +# ____ _ __ _____ __ _____ ______ __ __ _____ __ +# / __ \ |/ / / ___// / / ___/ / ____/ __/ /____ ____ ____/ / / ___/___ / / +# / /_/ / / \__ \/ / \__ \ / __/ | |/_/ __/ _ \/ __ \/ __ / \__ \/ _ \/ / +# / _, _/ | ___/ / /______/ / / /____> </ /_/ __/ / / / /_/ / ___/ / __/ / +#/_/ |_/_/|_| /____/_____/____/ /_____/_/|_|\__/\___/_/ /_/\__,_/ /____/\___/_/ +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +#-- rx_spare_mode_pg: rx_sls_extend_sel +#--********************************************************************************************* +scom 0x800.0b(rx_spare_mode_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + rx_sls_extend_sel, 0b100, (def_is_slave); #Set this entry to 0b100 per defect HW220806 +} ############################################################################################ # END OF FILE diff --git a/src/usr/hwpf/hwp/nest_chiplets/makefile b/src/usr/hwpf/hwp/nest_chiplets/makefile index b7c2982ac..b9b826bce 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/makefile +++ b/src/usr/hwpf/hwp/nest_chiplets/makefile @@ -1,25 +1,25 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. # -# $Source: src/usr/hwpf/hwp/nest_chiplets/makefile $ +# $Source: src/usr/hwpf/hwp/nest_chiplets/makefile $ # -# IBM CONFIDENTIAL +# IBM CONFIDENTIAL # -# COPYRIGHT International Business Machines Corp. 2012 +# COPYRIGHT International Business Machines Corp. 2012,2013 # -# p1 +# p1 # -# Object Code Only (OCO) source materials -# Licensed Internal Code Source Materials -# IBM HostBoot Licensed Internal Code +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code # -# The source code for this program is not published or other- -# wise divested of its trade secrets, irrespective of what has -# been deposited with the U.S. Copyright Office. +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. # -# Origin: 30 +# Origin: 30 # -# IBM_PROLOG_END_TAG +# IBM_PROLOG_END_TAG ROOTPATH = ../../../../.. MODULE = nest_chiplets @@ -49,7 +49,9 @@ OBJS = nest_chiplets.o \ proc_scomoverride_chiplets.o \ proc_a_x_pci_dmi_pll_initf.o \ proc_a_x_pci_dmi_pll_setup.o \ - proc_pcie_scominit.o + proc_pcie_scominit.o \ + proc_abus_scominit.o \ + proc_xbus_scominit.o ## NOTE: add a new directory onto the vpaths when you add a new HWP VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets diff --git a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C index 16a00927f..5c62d9cca 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C +++ b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C @@ -69,6 +69,8 @@ #include "nest_chiplets.H" #include "proc_start_clocks_chiplets/proc_start_clocks_chiplets.H" #include "proc_chiplet_scominit/proc_chiplet_scominit.H" +#include "proc_chiplet_scominit/proc_xbus_scominit.H" +#include "proc_chiplet_scominit/proc_abus_scominit.H" #include "proc_scomoverride_chiplets/proc_scomoverride_chiplets.H" #include "proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H" #include "proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.H" @@ -467,7 +469,6 @@ void* call_proc_chiplet_scominit( void *io_pArgs ) TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_chiplet_scominit entry" ); - uint8_t l_cpuNum = 0; TARGETING::TargetHandleList l_cpuTargetList; getAllChips(l_cpuTargetList, TYPE_PROC); @@ -523,14 +524,26 @@ void* call_proc_chiplet_scominit( void *io_pArgs ) } } - // ---------------------------------------------- - // Execute PROC_CHIPLET_ABUS/XBUS initfiles - // Note: the order is intentional to make - // HB and Cronus trace in the same order. - // Please do not change - // ---------------------------------------------- + } while (0); - // Do XBUS first, get all XBUS connections + return l_StepError.getErrorHandle(); +} +//***************************************************************************** +// wrapper function to call proc_xbus_scominit +//****************************************************************************** +void* call_proc_xbus_scominit( void *io_pArgs ) +{ + errlHndl_t l_err = NULL; + fapi::ReturnCode rc; + IStepError l_StepError; + + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_xbus_scominit entry" ); + + TARGETING::TargetHandleList l_cpuTargetList; + getAllChips(l_cpuTargetList, TYPE_PROC); + + do + { EDI_EI_INITIALIZATION::TargetPairs_t l_XbusConnections; l_err = EDI_EI_INITIALIZATION::PbusLinkSvc::getTheInstance().getPbusConnections( @@ -555,17 +568,14 @@ void* call_proc_chiplet_scominit( void *io_pArgs ) break; } - - // Loop thru the proc - for ( l_cpuNum=0; l_cpuNum < l_cpuTargetList.size(); l_cpuNum++ ) + for (TARGETING::TargetHandleList::iterator l_cpuIter = + l_cpuTargetList.begin(); l_cpuIter != l_cpuTargetList.end(); + ++l_cpuIter) { - const TARGETING::Target* l_cpuTarget = l_cpuTargetList[l_cpuNum]; + const TARGETING::Target* l_cpu_target = *l_cpuIter; - // ---------------------------------------------- - // Execute PROC_CHIPLET_XBUS initfiles - // ---------------------------------------------- TARGETING::TargetHandleList l_xbusList; - getChildChiplets( l_xbusList, l_cpuTarget, TYPE_XBUS ); + getChildChiplets( l_xbusList, l_cpu_target, TYPE_XBUS ); // For each XBUS unit in this proc for (size_t jj = 0; jj < l_xbusList.size(); jj++) @@ -595,7 +605,7 @@ void* call_proc_chiplet_scominit( void *io_pArgs ) TARGET_TYPE_PROC_CHIP, reinterpret_cast<void *> (const_cast<TARGETING::Target*>( - l_cpuTarget))); + l_cpu_target))); targets.push_back(l_fapi_this_cpu_target); const fapi::Target l_fapi_other_cpu_target( @@ -605,49 +615,75 @@ void* call_proc_chiplet_scominit( void *io_pArgs ) l_pParent))); targets.push_back(l_fapi_other_cpu_target); - // execute PROC_CHIPLET_XBUS_IF initfile - FAPI_INF("proc_chiplet_scominit: Executing %s on...", - PROC_CHIPLET_XBUS_IF); + // Call HW procedure + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "Running proc_xbus_scominit HWP on..." ); EntityPath l_path = l_xbusTarget->getAttr<ATTR_PHYS_PATH>(); l_path.dump(); - l_path = l_cpuTarget->getAttr<ATTR_PHYS_PATH>(); + l_path = l_cpu_target->getAttr<ATTR_PHYS_PATH>(); l_path.dump(); l_path = l_pParent->getAttr<ATTR_PHYS_PATH>(); l_path.dump(); - FAPI_EXEC_HWP(rc, - fapiHwpExecInitFile, - targets, - PROC_CHIPLET_XBUS_IF); - - l_err = fapi::fapiRcToErrl(rc); + FAPI_INVOKE_HWP(l_err, proc_xbus_scominit, + l_fapi_xbus_target, + l_fapi_this_cpu_target, + l_fapi_other_cpu_target); if (l_err) { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "proc_chiplet_scominit: Error from fapiHwpExecInitfile executing %s", - PROC_CHIPLET_XBUS_IF); - - l_StepError.addErrorDetails( - ISTEP_PROC_XBUS_IF_EXECUTION_FAILED, - ISTEP_PROC_CHIPLET_SCOMINIT, - l_err); - - // We want to continue to the next link instead of exiting, + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "ERROR 0x%.8X : " + "proc_xbus_scominit HWP returns error. XBUS target 0x%.8X, " + "This CPU target 0x%.8X, Other CPU target 0x%.8X", + l_err->reasonCode(), TARGETING::get_huid(l_xbusTarget), + TARGETING::get_huid(l_cpu_target), + TARGETING::get_huid(l_pParent)); + ErrlUserDetailsTarget myDetails(l_xbusTarget); + /*@ + * @errortype + * @reasoncode ISTEP_PROC_XBUS_SCOMINIT_FAILED + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid ISTEP_PROC_XBUS_SCOMINIT + * @userdata1 bytes 0-1: plid identifying first error + * bytes 2-3: reason code of first error + * @userdata2 bytes 0-1: total number of elogs included + * bytes 2-3: N/A + * @devdesc call to proc_xbus_scominit has failed + */ + l_StepError.addErrorDetails(ISTEP_PROC_XBUS_SCOMINIT_FAILED, + ISTEP_PROC_XBUS_SCOMINIT, + l_err ); + // We want to continue to the next target instead of exiting, // Commit the error log and move on - // Log should be deleted and set to NULL in errlCommit. + // Note: Error log should already be deleted and set to NULL + // after committing errlCommit(l_err, HWPF_COMP_ID); } } // End xbus loop + } // End cpu loop + + } while (0); + + return l_StepError.getErrorHandle(); +} + +//***************************************************************************** +// wrapper function to call proc_abus_scominit +//****************************************************************************** +void* call_proc_abus_scominit( void *io_pArgs ) +{ + + errlHndl_t l_err = NULL; + fapi::ReturnCode rc; + IStepError l_StepError; - } // End cpunum loop + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_abus_scominit entry" ); - // Note: all error logs exist above must have been committed. - // We want to move on to the ABUS training. The usage of l_err - // again below should not cause mem leakage. + TARGETING::TargetHandleList l_cpuTargetList; + getAllChips(l_cpuTargetList, TYPE_PROC); - // Now do ABUS, get all ABUS connections + do + { EDI_EI_INITIALIZATION::TargetPairs_t l_AbusConnections; l_err = EDI_EI_INITIALIZATION::PbusLinkSvc::getTheInstance().getPbusConnections( @@ -673,12 +709,15 @@ void* call_proc_chiplet_scominit( void *io_pArgs ) } // Loop thru the proc - for ( l_cpuNum=0; l_cpuNum < l_cpuTargetList.size(); l_cpuNum++ ) + for (TARGETING::TargetHandleList::iterator l_cpuIter = + l_cpuTargetList.begin(); l_cpuIter != l_cpuTargetList.end(); + ++l_cpuIter) { - const TARGETING::Target* l_cpuTarget = l_cpuTargetList[l_cpuNum]; + const TARGETING::Target* l_cpu_target = *l_cpuIter; + // Get the ABUS under this proc TARGETING::TargetHandleList l_abusList; - getChildChiplets( l_abusList, l_cpuTarget, TYPE_ABUS ); + getChildChiplets( l_abusList, l_cpu_target, TYPE_ABUS ); // For each ABUS unit in this proc for (size_t ii = 0; ii < l_abusList.size(); ii++) @@ -708,7 +747,7 @@ void* call_proc_chiplet_scominit( void *io_pArgs ) TARGET_TYPE_PROC_CHIP, reinterpret_cast<void *> (const_cast<TARGETING::Target*>( - l_cpuTarget))); + l_cpu_target))); targets.push_back(l_fapi_this_cpu_target); const fapi::Target l_fapi_other_cpu_target( @@ -718,76 +757,57 @@ void* call_proc_chiplet_scominit( void *io_pArgs ) l_pParent))); targets.push_back(l_fapi_other_cpu_target); - // execute PROC_CHIPLET_ABUS_IF initfile - FAPI_INF("proc_chiplet_scominit: Executing %s on...", - PROC_CHIPLET_ABUS_IF); + // Call HW procedure + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "Running proc_abus_scominit HWP on..." ); EntityPath l_path = l_abusTarget->getAttr<ATTR_PHYS_PATH>(); l_path.dump(); - l_path = l_cpuTarget->getAttr<ATTR_PHYS_PATH>(); + l_path = l_cpu_target->getAttr<ATTR_PHYS_PATH>(); l_path.dump(); l_path = l_pParent->getAttr<ATTR_PHYS_PATH>(); l_path.dump(); - FAPI_EXEC_HWP(rc, - fapiHwpExecInitFile, - targets, - PROC_CHIPLET_ABUS_IF); - l_err = fapi::fapiRcToErrl(rc); + FAPI_INVOKE_HWP(l_err, proc_abus_scominit, + l_fapi_abus_target, + l_fapi_this_cpu_target, + l_fapi_other_cpu_target); if (l_err) { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "proc_chiplet_scominit: Error from fapiHwpExecInitfile executing %s", - PROC_CHIPLET_ABUS_IF); - - l_StepError.addErrorDetails( - ISTEP_PROC_ABUS_IF_EXECUTION_FAILED, - ISTEP_PROC_CHIPLET_SCOMINIT, - l_err); - - // We want to continue to the next link instead of exiting, + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "ERROR 0x%.8X : " + "proc_abus_scominit HWP returns error. ABUS target 0x%.8X, " + "This CPU target 0x%.8X, Other CPU target 0x%.8X", + l_err->reasonCode(), TARGETING::get_huid(l_abusTarget), + TARGETING::get_huid(l_cpu_target), + TARGETING::get_huid(l_pParent)); + ErrlUserDetailsTarget myDetails(l_abusTarget); + /*@ + * @errortype + * @reasoncode ISTEP_PROC_ABUS_SCOMINIT_FAILED + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid ISTEP_PROC_ABUS_SCOMINIT + * @userdata1 bytes 0-1: plid identifying first error + * bytes 2-3: reason code of first error + * @userdata2 bytes 0-1: total number of elogs included + * bytes 2-3: N/A + * @devdesc call to proc_abus_scominit has failed + */ + l_StepError.addErrorDetails(ISTEP_PROC_ABUS_SCOMINIT_FAILED, + ISTEP_PROC_ABUS_SCOMINIT, + l_err ); + // We want to continue to the next target instead of exiting, // Commit the error log and move on - // Log should be deleted and set to NULL in errlCommit. + // Note: Error log should already be deleted and set to NULL + // after committing errlCommit(l_err, HWPF_COMP_ID); } - } // End abus list loop - } // End cpunum loop + } // End abus list loop + } // End cpu loop } while (0); return l_StepError.getErrorHandle(); -} -//***************************************************************************** -// wrapper function to call proc_xbus_scominit -//****************************************************************************** -void* call_proc_xbus_scominit( void *io_pArgs ) -{ - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "call_proc_xbus_scominit entry" ); - - // call proc_xbus_scominit.C - - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "call_proc_xbus_scominit exit" ); - - return NULL; -} - -//***************************************************************************** -// wrapper function to call proc_abus_scominit -//****************************************************************************** -void* call_proc_abus_scominit( void *io_pArgs ) -{ - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "call_proc_abus_scominit entry" ); - - // call proc_abus_scominit.C - // - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "call_proc_abus_scominit exit" ); - return NULL; } diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C index bf78cd3cf..a50fb1382 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -21,7 +21,7 @@ /* */ /* IBM_PROLOG_END_TAG */ // -*- mode: C++; c-file-style: "linux"; -*- -// $Id: proc_a_x_pci_dmi_pll_initf.C,v 1.4 2012/08/27 15:29:03 mfred Exp $ +// $Id: proc_a_x_pci_dmi_pll_initf.C,v 1.9 2013/01/20 19:21:03 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_initf.C,v $ //------------------------------------------------------------------------------ // *| @@ -51,10 +51,6 @@ #include "proc_a_x_pci_dmi_pll_initf.H" #include <fapi.H> -#define RING_LENGTH_AB_BNDY_PLL 536 -#define RING_LENGTH_PB_BNDY_DMIPLL 1234 -#define RING_LENGTH_PCI_BNDY_PLL 565 - using namespace fapi; @@ -68,43 +64,6 @@ const uint64_t OPCG_REG2_FOR_SETPULSE = 0x0000000000002000ull; const uint64_t OPCG_REG3_FOR_SETPULSE = 0x6000000000000000ull; const uint64_t CLK_REGION_FOR_SETPULSE = 0x0010040000000000ull; -// PLL Settings for simulation from Johannes Koesters 20 July 2012 -// TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF = x"13C54402001C000B 0008000000000000 00" -// TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF = x"13C54402001C000B 0008000000000000 00" -// TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF = x"174B1402001C0009 0008000000000000 00" -// TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF = x"10CB1402001C0009 0008000000000000 00" -// IOMC1.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF = x"10CB1402001C0009 0008000000000000 00" -// ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF = x"1F4CB402000C0009 0008000000000000 00" -// TPFLEX.PLLPCIE.PLLCTL.C_PLL_CNTRL_LEAF = x"128000000A0060DB B000000200000000 00" - - -// Settings for A Bus PLL // -// const uint64_t ABUS_PLL_CONFIG_RING_CNTRL0 = 0x0745D402001C000Bull; version 06/22/12 -const uint64_t ABUS_PLL_CONFIG_RING_CNTRL0 = 0x10C5D402000C0008ull; -const uint64_t ABUS_PLL_CONFIG_RING_CNTRL1 = 0x0008000000000000ull; -const uint8_t ABUS_PLL_CONFIG_RING_CNTRL2 = 0x00; -const uint64_t ABUS_PLL_CONFIG_RING_CNTRL0_FOR_SIM = 0x10C5D402001C0009ull; // TODO turn fastlock bit (63) OFF when new PLL model is available. -const uint64_t ABUS_PLL_CONFIG_RING_CNTRL1_FOR_SIM = 0x0008000000000000ull; -const uint8_t ABUS_PLL_CONFIG_RING_CNTRL2_FOR_SIM = 0x00; - -// Settings for DMI PLLs // -// const uint64_t DMI_PLL_CONFIG_RING_CNTRL0 = 0x074B1402001C000Bull; version 06/22/12 -const uint64_t DMI_PLL_CONFIG_RING_CNTRL0 = 0x10CB1402001C0008ull; -const uint64_t DMI_PLL_CONFIG_RING_CNTRL1 = 0x0008000000000000ull; -const uint8_t DMI_PLL_CONFIG_RING_CNTRL2 = 0x00; -const uint64_t DMI_PLL_CONFIG_RING_CNTRL0_FOR_SIM = 0x10CB1402000C0009ull; // TODO turn fastlock bit (63) OFF when new PLL model is available. -const uint64_t DMI_PLL_CONFIG_RING_CNTRL1_FOR_SIM = 0x0008000000000000ull; -const uint8_t DMI_PLL_CONFIG_RING_CNTRL2_FOR_SIM = 0x00; - -// Settings for PCIE PLL // -const uint64_t PCIE_PLL_CONFIG_RING_CNTRL0 = 0x128000000A00789Aull; -const uint64_t PCIE_PLL_CONFIG_RING_CNTRL1 = 0xA000000000000000ull; -const uint8_t PCIE_PLL_CONFIG_RING_CNTRL2 = 0x00; -const uint64_t PCIE_PLL_CONFIG_RING_CNTRL0_FOR_SIM = 0x128000000A0010DBull; -const uint64_t PCIE_PLL_CONFIG_RING_CNTRL1_FOR_SIM = 0xB000000200000000ull; -const uint8_t PCIE_PLL_CONFIG_RING_CNTRL2_FOR_SIM = 0x00; - - //------------------------------------------------------------------------------ @@ -133,16 +92,18 @@ extern "C" { // data buffer to hold register values ecmdDataBufferBase scom_data(64); - ecmdDataBufferBase rxpll_data(47); - ecmdDataBufferBase pll_data(136); ecmdDataBufferBase ring_data; + uint8_t pcie_enable_attr; + uint8_t abus_enable_attr; + uint32_t ring_length = 0; + uint8_t attrABRingData[80] ={0}; // Set to 80 bytes to match length in XML file, not actual scan ring length. + uint8_t attrDMIRingData[192]={0}; // Set to 192 bytes to match length in XML file, not actual scan ring length. + uint8_t attrPCIRingData[80] ={0}; // Set to 80 bytes to match length in XML file, not actual scan ring length. // return codes uint32_t rc_ecmd = 0; fapi::ReturnCode rc; - // locals - uint8_t is_simulation = 0; // mark function entry @@ -154,30 +115,17 @@ extern "C" do { - //---------------------------// - // Common code for all PLLs // - //---------------------------// - // Read the ATTR_IS_SIMULATION attribute - rc = FAPI_ATTR_GET( ATTR_IS_SIMULATION, NULL, is_simulation); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_IS_SIMULATION."); - break; - } - - - //------------// // X Bus PLL // //------------// if (!i_startX) { - FAPI_DBG("X BUS PLL not selected for setup in this routine.\n"); + FAPI_DBG("X BUS PLL not selected for setup in this routine."); } else { - FAPI_INF("This routine does not do X-BUS PLL setup at this time!.\n"); - FAPI_INF("It is assumed that the X-BUS PLL is already set up in synchronous mode for use with the NEST logic.\n"); + FAPI_INF("This routine does not do X-BUS PLL setup at this time!."); + FAPI_INF("It is assumed that the X-BUS PLL is already set up in synchronous mode for use with the NEST logic."); } // end X-bus PLL setup @@ -187,85 +135,67 @@ extern "C" //------------// // A Bus PLL // //------------// + + // query ABUS partial good attribute + rc = FAPI_ATTR_GET(ATTR_PROC_A_ENABLE, + &i_target, + abus_enable_attr); + if (!rc.ok()) + { + FAPI_ERR("Error querying ATTR_PROC_A_ENABLE"); + break; + } + if (!i_startA) { - FAPI_DBG("A BUS PLL not selected for setup in this routine.\n"); + FAPI_DBG("A BUS PLL not selected for setup in this routine."); + } + else if (abus_enable_attr != fapi::ENUM_ATTR_PROC_A_ENABLE_ENABLE) + { + FAPI_DBG("A BUS PLL setup skipped (partial good)."); } else { - FAPI_DBG("Loading the config bits into A BUS PLL\n"); - if (is_simulation) - { - rc_ecmd |= pll_data.setDoubleWord( 0, ABUS_PLL_CONFIG_RING_CNTRL0_FOR_SIM); - rc_ecmd |= pll_data.setDoubleWord( 1, ABUS_PLL_CONFIG_RING_CNTRL1_FOR_SIM); - rc_ecmd |= pll_data.setByte( 16, ABUS_PLL_CONFIG_RING_CNTRL2_FOR_SIM); - } - else - { - rc_ecmd |= pll_data.setDoubleWord( 0, ABUS_PLL_CONFIG_RING_CNTRL0); - rc_ecmd |= pll_data.setDoubleWord( 1, ABUS_PLL_CONFIG_RING_CNTRL1); - rc_ecmd |= pll_data.setByte( 16, ABUS_PLL_CONFIG_RING_CNTRL2); - } - if (rc_ecmd) - { - FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - // Set bit 17 of the controller for the ABus Cleanup PLLs - rc_ecmd |= rxpll_data.flushTo0(); - rc_ecmd |= rxpll_data.setBit(17); - if(rc_ecmd) - { - FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - + FAPI_DBG("Loading the config bits into A BUS PLL"); //--------------------------------------------------------------------------- - // Scan out the original contents from ring and modify it with new settings. + // Get ring data from cronus attribute and put it into eCmdDataBufferBase //--------------------------------------------------------------------------- - FAPI_DBG("Loading PLL settings into scan ring ab_bndy_pll for A-Bus PLL."); - - // The scan chain that we need to modify is: Name = ab_bndy_pll Address = {0x08030088} - // This chain is 536 bits long. - // RX2 clean up PLL control bits (47) go into positions 58 - 104 - // RX1 clean up PLL control bits (47) go into positions 105 - 151 - // RX0 clean up PLL control bits (47) go into positions 152 - 198 - // A-BUS PLL control bits (136) go into positions 200 - 335 - rc_ecmd |= ring_data.setBitLength(RING_LENGTH_AB_BNDY_PLL); // This length needs to match the length in the scandef file (Required for hostboot.) - if (rc_ecmd) + // Read the ring length attribute value. + rc = FAPI_ATTR_GET( ATTR_PROC_AB_BNDY_PLL_LENGTH, &i_target, ring_length); + if (rc) { - FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.", rc_ecmd); - rc.setEcmdError(rc_ecmd); + FAPI_ERR("Failed to get attribute: ATTR_PROC_AB_BNDY_PLL_LENGTH."); break; } - rc = fapiGetRing(i_target, 0x08030088, ring_data); + FAPI_DBG("ATTR_PROC_AB_BNDY_PLL_LENGTH attribute is set to : %d.", ring_length); + + + // Read the ring data attribute value. + rc = FAPI_ATTR_GET( ATTR_PROC_AB_BNDY_PLL_DATA, &i_target, attrABRingData); if (rc) { - FAPI_ERR("fapiGetRing failed with rc = 0x%x", (uint32_t)rc); + FAPI_ERR("Failed to get attribute: ATTR_PROC_AB_BNDY_PLL_DATA."); break; } - // Reverse the bits in the pll data buffers so they match the order of the bits in the scan chain - rc_ecmd |= pll_data.reverse( ); - rc_ecmd |= rxpll_data.reverse( ); + + + // Set the ring_data buffer to the right length for the ring data + rc_ecmd |= ring_data.setBitLength(ring_length); // This length needs to match the real scan length in the scandef file (Required for hostboot.) if (rc_ecmd) { - FAPI_ERR("Error (0x%x) reversing the bits in the pll data buffer", rc_ecmd); + FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.", rc_ecmd); rc.setEcmdError(rc_ecmd); break; } - // Insert the PLL settings in to the scan ring. - rc_ecmd |= ring_data.insert( rxpll_data, 58, 47); - rc_ecmd |= ring_data.insert( rxpll_data, 105, 47); - rc_ecmd |= ring_data.insert( rxpll_data, 152, 47); - rc_ecmd |= ring_data.insert( pll_data, 200, 136); + + + // Put the ring data from the attribute into the buffer + rc_ecmd |= ring_data.insert(attrABRingData, 0, ring_length, 0); if (rc_ecmd) { - FAPI_ERR("Error (0x%x) inserting config bits into ring_data buffer", rc_ecmd); + FAPI_ERR("Error 0x%x loading scan chain attribute data into buffer.", rc_ecmd); rc.setEcmdError(rc_ecmd); break; } @@ -342,7 +272,7 @@ extern "C" //----------------------------------------------------- - // Scan new ring data back into ab_bndy_pll scan ring. + // Scan new ring data into ab_bndy_pll scan ring. //----------------------------------------------------- rc = fapiPutRing(i_target, 0x08030088, ring_data, RING_MODE_SET_PULSE); if (rc) @@ -350,7 +280,7 @@ extern "C" FAPI_ERR("fapiPutRing failed with rc = 0x%x", (uint32_t)rc); break; } - FAPI_DBG("Loading of the config bits for A-BUS PLL is done.\n"); + FAPI_DBG("Loading of the config bits for A-BUS PLL is done."); @@ -390,8 +320,8 @@ extern "C" } - FAPI_DBG("Loading of the config bits for A BUS PLL is done.\n"); - FAPI_INF("Done setting up A-Bus PLL. \n"); + FAPI_DBG("Loading of the config bits for A BUS PLL is done."); + FAPI_INF("Done setting up A-Bus PLL. "); } // end A PLL @@ -401,85 +331,50 @@ extern "C" //----------// if (!i_startDMI) { - FAPI_DBG("DMI PLL not selected for setup in this routine.\n"); + FAPI_DBG("DMI PLL not selected for setup in this routine."); } else { - FAPI_DBG("Loading the config bits into DMI PLL\n"); - if (is_simulation) - { - rc_ecmd |= pll_data.setDoubleWord( 0, DMI_PLL_CONFIG_RING_CNTRL0_FOR_SIM); - rc_ecmd |= pll_data.setDoubleWord( 1, DMI_PLL_CONFIG_RING_CNTRL1_FOR_SIM); - rc_ecmd |= pll_data.setByte( 16, DMI_PLL_CONFIG_RING_CNTRL2_FOR_SIM); - } - else - { - rc_ecmd |= pll_data.setDoubleWord( 0, DMI_PLL_CONFIG_RING_CNTRL0); - rc_ecmd |= pll_data.setDoubleWord( 1, DMI_PLL_CONFIG_RING_CNTRL1); - rc_ecmd |= pll_data.setByte( 16, DMI_PLL_CONFIG_RING_CNTRL2); - } - if (rc_ecmd) - { - FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - // Set bit 17 of the controller for the DMI Cleanup PLLs - rc_ecmd |= rxpll_data.flushTo0(); - rc_ecmd |= rxpll_data.setBit(17); - if(rc_ecmd) - { - FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - + FAPI_DBG("Loading the config bits into DMI PLL"); //--------------------------------------------------------------------------- - // Scan out the original contents from ring and modify it with new settings. + // Get ring data from cronus attribute and put it into eCmdDataBufferBase //--------------------------------------------------------------------------- - FAPI_DBG("Loading PLL settings into scan ring pb_bndy_dmipll for DMI PLL."); - - // The scan chain that we need to modify is: Name = pb_bndy_dmipll Address = {0x02030088} - // This chain is 1234 bits long. - // RX3 clean up PLL control bits (47) go into positions 314 - 360 - // RX2 clean up PLL control bits (47) go into positions 361 - 407 - // RX1 clean up PLL control bits (47) go into positions 408 - 454 - // RX0 clean up PLL control bits (47) go into positions 455 - 501 - // DMI PLL control bits (136) go into positions 502 - 637 - rc_ecmd |= ring_data.setBitLength(RING_LENGTH_PB_BNDY_DMIPLL); // This length needs to match the length in the scandef file (Required for hostboot.) - if (rc_ecmd) + // Read the ring length attribute value. + rc = FAPI_ATTR_GET( ATTR_PROC_PB_BNDY_DMIPLL_LENGTH, &i_target, ring_length); + if (rc) { - FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.", rc_ecmd); - rc.setEcmdError(rc_ecmd); + FAPI_ERR("Failed to get attribute: ATTR_PROC_PB_BNDY_DMIPLL_LENGTH."); break; } - rc = fapiGetRing(i_target, 0x02030088, ring_data); + FAPI_DBG("ATTR_PROC_PB_BNDY_DMIPLL_LENGTH attribute is set to : %d.", ring_length); + + + // Read the ring data attribute value. + rc = FAPI_ATTR_GET( ATTR_PROC_PB_BNDY_DMIPLL_DATA, &i_target, attrDMIRingData); if (rc) { - FAPI_ERR("fapiGetRing failed with rc = 0x%x", (uint32_t)rc); + FAPI_ERR("Failed to get attribute: ATTR_PROC_PB_BNDY_DMIPLL_DATA."); break; } - // Reverse the bits in the pll data buffers so they match the order of the bits in the scan chain - rc_ecmd |= pll_data.reverse( ); - rc_ecmd |= rxpll_data.reverse( ); + + + // Set the ring_data buffer to the right length for the ring data + rc_ecmd |= ring_data.setBitLength(ring_length); // This length needs to match the real scan length in the scandef file (Required for hostboot.) if (rc_ecmd) { - FAPI_ERR("Error (0x%x) reversing the bits in the pll data buffer", rc_ecmd); + FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.", rc_ecmd); rc.setEcmdError(rc_ecmd); break; } - // Insert the PLL settings in to the scan ring. - rc_ecmd |= ring_data.insert( rxpll_data, 314, 47); - rc_ecmd |= ring_data.insert( rxpll_data, 361, 47); - rc_ecmd |= ring_data.insert( rxpll_data, 408, 47); - rc_ecmd |= ring_data.insert( rxpll_data, 455, 47); - rc_ecmd |= ring_data.insert( pll_data, 502, 136); + + + // Put the ring data from the attribute into the buffer + rc_ecmd |= ring_data.insert(attrDMIRingData, 0, ring_length, 0); if (rc_ecmd) { - FAPI_ERR("Error (0x%x) inserting config bits into ring_data buffer", rc_ecmd); + FAPI_ERR("Error 0x%x loading scan chain attribute data into buffer.", rc_ecmd); rc.setEcmdError(rc_ecmd); break; } @@ -556,7 +451,7 @@ extern "C" //----------------------------------------------------- - // Scan new ring data back into pb_bndy_dmipll scan ring. + // Scan new ring data into pb_bndy_dmipll scan ring. //----------------------------------------------------- rc = fapiPutRing(i_target, 0x02030088, ring_data, RING_MODE_SET_PULSE); if (rc) @@ -564,7 +459,7 @@ extern "C" FAPI_ERR("fapiPutRing failed with rc = 0x%x", (uint32_t)rc); break; } - FAPI_DBG("Loading of the config bits for DMI PLL is done.\n"); + FAPI_DBG("Loading of the config bits for DMI PLL is done."); @@ -603,7 +498,7 @@ extern "C" break; } - FAPI_INF("Done setting up DMI PLL. \n"); + FAPI_INF("Done setting up DMI PLL. "); } // end DMI PLL @@ -611,70 +506,67 @@ extern "C" //-----------// // PCIE PLL // //-----------// + + // query PCIE partial good attribute + rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_ENABLE, + &i_target, + pcie_enable_attr); + if (!rc.ok()) + { + FAPI_ERR("Error querying ATTR_PROC_PCIE_ENABLE"); + break; + } + if (!i_startPCIE) { - FAPI_DBG("PCIE PLL not selected for setup in this routine.\n"); + FAPI_DBG("PCIE PLL not selected for setup in this routine."); + } + else if (pcie_enable_attr != fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE) + { + FAPI_DBG("PCIE PLL setup skipped (partial good)."); } else { - FAPI_DBG("Starting PLL setup for PCIE PLL ...\n"); - FAPI_DBG("Loading the config bits into PCIE BUS PLL\n"); - if (is_simulation) - { - rc_ecmd |= pll_data.setDoubleWord( 0, PCIE_PLL_CONFIG_RING_CNTRL0_FOR_SIM); - rc_ecmd |= pll_data.setDoubleWord( 1, PCIE_PLL_CONFIG_RING_CNTRL1_FOR_SIM); - rc_ecmd |= pll_data.setByte( 16, PCIE_PLL_CONFIG_RING_CNTRL2_FOR_SIM); - } - else - { - rc_ecmd |= pll_data.setDoubleWord( 0, PCIE_PLL_CONFIG_RING_CNTRL0); - rc_ecmd |= pll_data.setDoubleWord( 1, PCIE_PLL_CONFIG_RING_CNTRL1); - rc_ecmd |= pll_data.setByte( 16, PCIE_PLL_CONFIG_RING_CNTRL2); - } - if (rc_ecmd) - { - FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - + FAPI_DBG("Loading the config bits into PCIE BUS PLL"); //--------------------------------------------------------------------------- - // Scan out the original contents from ring and modify it with new settings. + // Get ring data from cronus attribute and put it into eCmdDataBufferBase //--------------------------------------------------------------------------- - FAPI_DBG("Loading PLL settings into scan ring pci_bndy_pll for DMI PLL."); - // The scan chain that we need to modify is: Name = pci_bndy_pll Address = {0x09030088} - // This chain is 565 bits long. - // PCIE PLL control bits (136) go into positions 258 - 393 - - rc_ecmd |= ring_data.setBitLength(RING_LENGTH_PCI_BNDY_PLL); // This length needs to match the length in the scandef file (Required for hostboot.) - if (rc_ecmd) + // Read the ring length attribute value. + rc = FAPI_ATTR_GET( ATTR_PROC_PCI_BNDY_PLL_LENGTH, &i_target, ring_length); + if (rc) { - FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.", rc_ecmd); - rc.setEcmdError(rc_ecmd); + FAPI_ERR("Failed to get attribute: ATTR_PROC_PCI_BNDY_PLL_LENGTH."); break; } - rc = fapiGetRing(i_target, 0x09030088, ring_data); + FAPI_DBG("ATTR_PROC_PCI_BNDY_PLL_LENGTH attribute is set to : %d.", ring_length); + + + // Read the ring data attribute value. + rc = FAPI_ATTR_GET( ATTR_PROC_PCI_BNDY_PLL_DATA, &i_target, attrPCIRingData); if (rc) { - FAPI_ERR("fapiGetRing failed with rc = 0x%x", (uint32_t)rc); + FAPI_ERR("Failed to get attribute: ATTR_PROC_PCI_BNDY_PLL_DATA."); break; } - // Reverse the bits in the pll data buffers so they match the order of the bits in the scan chain - rc_ecmd |= pll_data.reverse( ); + + + // Set the ring_data buffer to the right length for the ring data + rc_ecmd |= ring_data.setBitLength(ring_length); // This length needs to match the real scan length in the scandef file (Required for hostboot.) if (rc_ecmd) { - FAPI_ERR("Error (0x%x) reversing the bits in the pll data buffer", rc_ecmd); + FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.", rc_ecmd); rc.setEcmdError(rc_ecmd); break; } - // Insert the PLL settings in to the scan ring. - rc_ecmd |= ring_data.insert( pll_data, 258, 136); + + + // Put the ring data from the attribute into the buffer + rc_ecmd |= ring_data.insert(attrPCIRingData, 0, ring_length, 0); if (rc_ecmd) { - FAPI_ERR("Error (0x%x) inserting config bits into ring_data buffer", rc_ecmd); + FAPI_ERR("Error 0x%x loading scan chain attribute data into buffer.", rc_ecmd); rc.setEcmdError(rc_ecmd); break; } @@ -751,7 +643,7 @@ extern "C" //----------------------------------------------------- - // Scan new ring data back into pci_bndy_pll scan ring. + // Scan new ring data into pci_bndy_pll scan ring. //----------------------------------------------------- rc = fapiPutRing(i_target, 0x09030088, ring_data, RING_MODE_SET_PULSE); if (rc) @@ -759,7 +651,7 @@ extern "C" FAPI_ERR("fapiPutRing failed with rc = 0x%x", (uint32_t)rc); break; } - FAPI_DBG("Loading of the config bits for PCIE PLL is done.\n"); + FAPI_DBG("Loading of the config bits for PCIE PLL is done."); @@ -799,7 +691,7 @@ extern "C" } - FAPI_INF("Done setting up PCIE PLL. \n"); + FAPI_INF("Done setting up PCIE PLL. "); } // end PCIE PLL @@ -818,6 +710,18 @@ extern "C" This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: proc_a_x_pci_dmi_pll_initf.C,v $ +Revision 1.9 2013/01/20 19:21:03 jmcgill +update for A chiplet partial good support + +Revision 1.8 2013/01/10 14:42:53 jmcgill +add partial good support + +Revision 1.6 2012/12/07 17:09:39 mfred +fix to add DMI PLL settings for MC1 for Venice. + +Revision 1.5 2012/12/06 22:59:18 mfred +adjust DMI PLL settings based on chip type. + Revision 1.4 2012/08/27 15:29:03 mfred Fixed some findings from the latest FW code review. diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C index d6b659e9b..97a75d9aa 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -21,7 +21,7 @@ /* */ /* IBM_PROLOG_END_TAG */ // -*- mode: C++; c-file-style: "linux"; -*- -// $Id: proc_a_x_pci_dmi_pll_setup.C,v 1.7 2012/08/14 18:32:45 mfred Exp $ +// $Id: proc_a_x_pci_dmi_pll_setup.C,v 1.9 2013/01/20 19:22:44 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_setup.C,v $ //------------------------------------------------------------------------------ // *| @@ -101,7 +101,8 @@ extern "C" const uint32_t max = 50; // Set to maximum number of times to poll for PLL each lock uint32_t timeout = 0; uint32_t num = 0; - + uint8_t pcie_enable_attr; + uint8_t abus_enable_attr; // mark function entry FAPI_INF("Entry1, start_XBUS=%s\n, Entry2, start_ABUS=%s\n, Entry3, start_PCIE=%s\n, Entry4, start_DMI=%s \n" , @@ -117,7 +118,7 @@ extern "C" // Common code for all PLLs // //---------------------------// - FAPI_INF("FSI GP4 bit 22: Clear pll_test_bypass1.\n"); + FAPI_INF("FSI GP4 bit 22: Clear pll_test_bypass1."); rc = fapiGetScom(i_target, MBOX_FSIGP4_0x00050013, gp_data); if (rc) { @@ -145,12 +146,12 @@ extern "C" //------------// if (!i_startX) { - FAPI_DBG("X BUS PLL not selected for setup in this routine.\n"); + FAPI_DBG("X BUS PLL not selected for setup in this routine."); } else { - FAPI_INF("This routine does not do X-BUS PLL setup at this time!.\n"); - FAPI_INF("It is assumed that the X-BUS PLL is already set up in synchronous mode for use with the NEST logic.\n"); + FAPI_INF("This routine does not do X-BUS PLL setup at this time!."); + FAPI_INF("It is assumed that the X-BUS PLL is already set up in synchronous mode for use with the NEST logic."); } // end X-bus PLL setup @@ -159,16 +160,30 @@ extern "C" //------------// // A Bus PLL // //------------// + + // query ABUS partial good attribute + rc = FAPI_ATTR_GET(ATTR_PROC_A_ENABLE, + &i_target, + abus_enable_attr); + if (!rc.ok()) + { + FAPI_ERR("Error querying ATTR_PROC_A_ENABLE"); + break; + } + if (!i_startA) { - FAPI_DBG("A BUS PLL not selected for setup in this routine.\n"); + FAPI_DBG("A BUS PLL not selected for setup in this routine."); + } + else if (abus_enable_attr != fapi::ENUM_ATTR_PROC_A_ENABLE_ENABLE) + { + FAPI_DBG("A BUS PLL setup skipped (partial good)."); } else { - FAPI_DBG("Starting PLL setup for A BUS PLL ...\n"); - + FAPI_DBG("Starting PLL setup for A BUS PLL ..."); - FAPI_INF("ABUS GP3: Release PLL test enable of ABUS chiplet. \n"); + FAPI_INF("ABUS GP3: Release PLL test enable of ABUS chiplet. "); rc_ecmd |= gp_data.flushTo1(); rc_ecmd |= gp_data.clearBit(GP3_PLL_TEST_ENABLE); if (rc_ecmd) @@ -186,7 +201,7 @@ extern "C" - FAPI_INF("ABUS GP3: Release PLL reset of ABUS chiplet \n"); + FAPI_INF("ABUS GP3: Release PLL reset of ABUS chiplet "); rc_ecmd |= gp_data.flushTo1(); rc_ecmd |= gp_data.clearBit(GP3_PLL_RESET); if (rc_ecmd) @@ -204,7 +219,7 @@ extern "C" - FAPI_INF("CHIPLET PLLLK: Check the PLL lock of A-BUS \n"); + FAPI_INF("CHIPLET PLLLK: Check the PLL lock of A-BUS "); num = 0; do { @@ -229,11 +244,11 @@ extern "C" FAPI_SET_HWP_ERROR(rc, RC_PROC_A_X_PCI_DMI_PLL_SETUP_ABUS_PLL_NO_LOCK); break; } - FAPI_INF("A-Bus PLL is locked.\n"); + FAPI_INF("A-Bus PLL is locked."); - FAPI_INF("ABUS GP3: Release PLL bypass of A-BUS \n"); + FAPI_INF("ABUS GP3: Release PLL bypass of A-BUS "); rc_ecmd |= gp_data.flushTo1(); rc_ecmd |= gp_data.clearBit(GP3_PLL_BYPASS); if (rc_ecmd) @@ -251,7 +266,7 @@ extern "C" - FAPI_INF("Done setting up A-Bus PLL. \n"); + FAPI_INF("Done setting up A-Bus PLL. "); } // end A PLL @@ -261,14 +276,14 @@ extern "C" //----------// if (!i_startDMI) { - FAPI_DBG("DMI PLL not selected for setup in this routine.\n"); + FAPI_DBG("DMI PLL not selected for setup in this routine."); } else { - FAPI_DBG("Starting PLL setup for DMI PLL ...\n"); + FAPI_DBG("Starting PLL setup for DMI PLL ..."); - FAPI_INF("NEST GP3: Release PLL test enable for DMI PLL.\n"); + FAPI_INF("NEST GP3: Release PLL test enable for DMI PLL."); rc_ecmd |= gp_data.flushTo1(); rc_ecmd |= gp_data.clearBit(GP3_PLL_TEST_ENABLE); if (rc_ecmd) @@ -286,7 +301,7 @@ extern "C" - FAPI_INF("NEST GP3: Release PLL reset for DMI PLL.\n"); + FAPI_INF("NEST GP3: Release PLL reset for DMI PLL."); rc_ecmd |= gp_data.flushTo1(); rc_ecmd |= gp_data.clearBit(GP3_PLL_RESET); if (rc_ecmd) @@ -304,7 +319,7 @@ extern "C" - FAPI_INF("CHIPLET PLLLK: Check the PLL lock of DMI PLL.\n"); + FAPI_INF("CHIPLET PLLLK: Check the PLL lock of DMI PLL."); num = 0; do { @@ -329,11 +344,11 @@ extern "C" FAPI_SET_HWP_ERROR(rc, RC_PROC_A_X_PCI_DMI_PLL_SETUP_DMI_PLL_NO_LOCK); break; } - FAPI_INF("DMI PLL is locked.\n"); + FAPI_INF("DMI PLL is locked."); - FAPI_INF("NEST GP3: Release PLL bypass of for DMI PLL.\n"); + FAPI_INF("NEST GP3: Release PLL bypass of for DMI PLL."); rc_ecmd |= gp_data.flushTo1(); rc_ecmd |= gp_data.clearBit(GP3_PLL_BYPASS); if (rc_ecmd) @@ -351,7 +366,7 @@ extern "C" - FAPI_INF("Done setting up DMI PLL. \n"); + FAPI_INF("Done setting up DMI PLL. "); } // end DMI PLL @@ -359,15 +374,30 @@ extern "C" //-----------// // PCIE PLL // //-----------// + + // query PCIE partial good attribute + rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_ENABLE, + &i_target, + pcie_enable_attr); + if (!rc.ok()) + { + FAPI_ERR("Error querying ATTR_PROC_PCIE_ENABLE"); + break; + } + if (!i_startPCIE) { - FAPI_DBG("PCIE PLL not selected for setup in this routine.\n"); + FAPI_DBG("PCIE PLL not selected for setup in this routine."); + } + else if (pcie_enable_attr != fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE) + { + FAPI_DBG("PCIE PLL setup skipped (partial good)."); } else { - FAPI_DBG("Starting PLL setup for PCIE PLL ...\n"); + FAPI_DBG("Starting PLL setup for PCIE PLL ..."); - FAPI_INF("PCIE GP3: Release PLL test enable of PCIE chiplet. \n"); + FAPI_INF("PCIE GP3: Release PLL test enable of PCIE chiplet. "); rc_ecmd |= gp_data.flushTo1(); rc_ecmd |= gp_data.clearBit(GP3_PLL_TEST_ENABLE); if (rc_ecmd) @@ -385,7 +415,7 @@ extern "C" - FAPI_INF("PCIE GP3: Release PLL reset of PCIE chiplet \n"); + FAPI_INF("PCIE GP3: Release PLL reset of PCIE chiplet "); rc_ecmd |= gp_data.flushTo1(); rc_ecmd |= gp_data.clearBit(GP3_PLL_RESET); if (rc_ecmd) @@ -403,7 +433,7 @@ extern "C" - FAPI_INF("PCIE GP3: Release PLL bypass of PCIE-BUS \n"); + FAPI_INF("PCIE GP3: Release PLL bypass of PCIE-BUS "); // 24july2012 mfred moved this before checking PLL lock as this is required for analog PLLs. rc_ecmd |= gp_data.flushTo1(); rc_ecmd |= gp_data.clearBit(GP3_PLL_BYPASS); @@ -422,7 +452,7 @@ extern "C" - FAPI_INF("CHIPLET PLLLK: Check the PLL lock of PCIE-BUS \n"); + FAPI_INF("CHIPLET PLLLK: Check the PLL lock of PCIE-BUS "); num = 0; do { @@ -447,11 +477,11 @@ extern "C" FAPI_SET_HWP_ERROR(rc, RC_PROC_A_X_PCI_DMI_PLL_SETUP_PCIE_PLL_NO_LOCK); break; } - FAPI_INF("PCIE PLL is locked.\n"); + FAPI_INF("PCIE PLL is locked."); - FAPI_INF("Done setting up PCIE PLL. \n"); + FAPI_INF("Done setting up PCIE PLL. "); } // end PCIE PLL @@ -470,6 +500,12 @@ extern "C" This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: proc_a_x_pci_dmi_pll_setup.C,v $ +Revision 1.9 2013/01/20 19:22:44 jmcgill +update for A chiplet partial good support + +Revision 1.8 2013/01/10 14:40:13 jmcgill +add partial good support + Revision 1.7 2012/08/14 18:32:45 mfred Changed input parms from bool & to const bool. diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit.C b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit.C new file mode 100644 index 000000000..72fc8f9b7 --- /dev/null +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit.C @@ -0,0 +1,119 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_abus_scominit.C,v 1.2 2013/01/20 19:23:46 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_abus_scominit.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2012 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : proc_abus_scominit.C +// *! DESCRIPTION : Invoke ABUS initfile (FAPI) +// *! +// *! OWNER NAME : Mike Jones Email: mjjones@us.ibm.com +// *! BACKUP NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! +// *! ADDITIONAL COMMENTS : +// *! +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapiHwpExecInitFile.H> +#include <proc_abus_scominit.H> + +extern "C" { + +//------------------------------------------------------------------------------ +// Function definitions +//------------------------------------------------------------------------------ + +// HWP entry point, comments in header +fapi::ReturnCode proc_abus_scominit( + const fapi::Target & i_abus_target, + const fapi::Target & i_this_pu_target, + const fapi::Target & i_other_pu_target) +{ + fapi::ReturnCode rc; + std::vector<fapi::Target> targets; + uint8_t abus_enable_attr; + + // mark HWP entry + FAPI_INF("proc_abus_scominit: Start"); + + do + { + // query ABUS partial good attribute + rc = FAPI_ATTR_GET(ATTR_PROC_A_ENABLE, + &i_this_pu_target, + abus_enable_attr); + if (!rc.ok()) + { + FAPI_ERR("proc_abus_scominit: Error querying ATTR_PROC_A_ENABLE"); + break; + } + + if (abus_enable_attr != fapi::ENUM_ATTR_PROC_A_ENABLE_ENABLE) + { + FAPI_ERR("proc_abus_scominit: Partial good attribute error"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_ABUS_SCOMINIT_PARTIAL_GOOD_ERR); + break; + } + + // obtain target type to determine which initfile(s) to execute + targets.push_back(i_abus_target); + targets.push_back(i_this_pu_target); + targets.push_back(i_other_pu_target); + + // processor ABUS chiplet target + if ((i_abus_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT) && + (i_this_pu_target.getType() == fapi::TARGET_TYPE_PROC_CHIP) && + (i_other_pu_target.getType() == fapi::TARGET_TYPE_PROC_CHIP)) + { + FAPI_INF("proc_abus_scominit: Executing %s on %s", + ABUS_IF, i_abus_target.toEcmdString()); + FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, targets, ABUS_IF); + if (!rc.ok()) + { + FAPI_ERR("proc_abus_scominit: Error from fapiHwpExecInitfile executing %s on %s", + ABUS_IF, i_abus_target.toEcmdString()); + break; + } + } + // unsupported target type + else + { + FAPI_ERR("proc_abus_scominit: Unsupported target type(s)"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_ABUS_SCOMINIT_INVALID_TARGET); + break; + } + } while (0); + + // mark HWP exit + FAPI_INF("proc_abus_scominit: End"); + return rc; +} + + +} // extern "C" diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit.H b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit.H new file mode 100644 index 000000000..928ab9c97 --- /dev/null +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit.H @@ -0,0 +1,93 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_abus_scominit.H,v 1.1 2012/08/11 18:24:25 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_abus_scominit.H,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2012 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : proc_abus_scominit.H +// *! DESCRIPTION : Invoke ABUS initfile (FAPI) +// *! +// *! OWNER NAME : Mike Jones Email: mjjones@us.ibm.com +// *! BACKUP NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! +// *! ADDITIONAL COMMENTS : +// *! +//------------------------------------------------------------------------------ + +#ifndef PROC_ABUS_SCOMINIT_H_ +#define PROC_ABUS_SCOMINIT_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi.H> + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ +const char * const ABUS_IF = "p8.abus.scom.if"; + +//------------------------------------------------------------------------------ +// Structure definitions +//------------------------------------------------------------------------------ + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode +(*proc_abus_scominit_FP_t)(const fapi::Target & i_abus_target, + const fapi::Target & i_this_pu_target, + const fapi::Target & i_other_pu_target); + +extern "C" { + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + +/** + * @brief HWP that calls the ABUS SCOM initfiles + * + * Should be called for all valid/connected ABUS endpoints + * + * @param[in] i_abus_target Reference to ABUS target + * i_this_pu_target Reference to enclosing chip target + * i_other_pu_target Reference to connected chip target + * If i_abus_target is TARGET_TYPE_ABUS_ENDPOINT, + * i_this_pu_target is TARGET_TYPE_PROC_CHIP, + * i_other_pu_target is TARGET_TYPE_PROC_CHIP, + * calls: + * - p8.abus.scom.initfile + * + * @return ReturnCode + */ +fapi::ReturnCode proc_abus_scominit( + const fapi::Target & i_abus_target, + const fapi::Target & i_this_pu_target, + const fapi::Target & i_other_pu_target); + + +} // extern "C" + +#endif // PROC_ABUS_SCOMINIT_H_ diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit_errors.xml b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit_errors.xml new file mode 100644 index 000000000..9e61fd5ae --- /dev/null +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit_errors.xml @@ -0,0 +1,34 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- Error definitions for proc_abus_scominit procedure --> +<hwpErrors> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_ABUS_SCOMINIT_INVALID_TARGET</rc> + <description>Invalid target type presented to proc_abus_scominit HWP (expects TARGET_TYPE_ABUS_ENDPOINT).</description> + </hwpError> + <hwpError> + <rc>RC_PROC_ABUS_SCOMINIT_PARTIAL_GOOD_ERR</rc> + <description>Partial good attribute state does not allow for action on chiplet target.</description> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C index 866b67b76..edfa740b2 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_chiplet_scominit.C,v 1.5 2012/08/11 03:43:10 jmcgill Exp $ +// $Id: proc_chiplet_scominit.C,v 1.9 2013/01/20 19:29:42 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_chiplet_scominit.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -54,7 +54,8 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target) { fapi::ReturnCode rc; fapi::TargetType target_type; - std::vector<fapi::Target> targets; + std::vector<fapi::Target> initfile_targets; + uint8_t nx_enabled; // mark HWP entry FAPI_INF("proc_chiplet_scominit: Start"); @@ -63,18 +64,18 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target) { // obtain target type to determine which initfile(s) to execute target_type = i_target.getType(); - targets.push_back(i_target); // chip level target if (target_type == fapi::TARGET_TYPE_PROC_CHIP) { - // execute FBC initfile + // execute FBC SCOM initfile + initfile_targets.push_back(i_target); FAPI_INF("proc_chiplet_scominit: Executing %s on %s", PROC_CHIPLET_SCOMINIT_FBC_IF, i_target.toEcmdString()); FAPI_EXEC_HWP( rc, fapiHwpExecInitFile, - targets, + initfile_targets, PROC_CHIPLET_SCOMINIT_FBC_IF); if (!rc.ok()) { @@ -83,6 +84,99 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target) i_target.toEcmdString()); break; } + + // query NX partial good attribute + rc = FAPI_ATTR_GET(ATTR_PROC_NX_ENABLE, + &i_target, + nx_enabled); + if (!rc.ok()) + { + FAPI_ERR("proc_chiplet_scominit: Error querying ATTR_PROC_NX_ENABLE"); + break; + } + + // apply NX/AS SCOM initfiles only if partial good attribute is set + if (nx_enabled == fapi::ENUM_ATTR_PROC_NX_ENABLE_ENABLE) + { + // execute NX SCOM initfile + initfile_targets.clear(); + initfile_targets.push_back(i_target); + FAPI_INF("proc_chiplet_scominit: Executing %s on %s", + PROC_CHIPLET_SCOMINIT_NX_IF, i_target.toEcmdString()); + FAPI_EXEC_HWP( + rc, + fapiHwpExecInitFile, + initfile_targets, + PROC_CHIPLET_SCOMINIT_NX_IF); + if (!rc.ok()) + { + FAPI_ERR("proc_chiplet_scominit: Error from fapiHwpExecInitfile executing %s on %s", + PROC_CHIPLET_SCOMINIT_NX_IF, + i_target.toEcmdString()); + break; + } + + // execute AS SCOM initfile + FAPI_INF("proc_chiplet_scominit: Executing %s on %s", + PROC_CHIPLET_SCOMINIT_AS_IF, i_target.toEcmdString()); + FAPI_EXEC_HWP( + rc, + fapiHwpExecInitFile, + initfile_targets, + PROC_CHIPLET_SCOMINIT_AS_IF); + if (!rc.ok()) + { + FAPI_ERR("proc_chiplet_scominit: Error from fapiHwpExecInitfile executing %s on %s", + PROC_CHIPLET_SCOMINIT_AS_IF, + i_target.toEcmdString()); + break; + } + } + else + { + FAPI_DBG("proc_chiplet_scominit: Skipping execution of %s/%s (partial good)", + PROC_CHIPLET_SCOMINIT_NX_IF, PROC_CHIPLET_SCOMINIT_AS_IF); + } + + // determine set of functional MCS chiplets + std::vector<fapi::Target> mcs_targets; + rc = fapiGetChildChiplets(i_target, + fapi::TARGET_TYPE_MCS_CHIPLET, + mcs_targets, + fapi::TARGET_STATE_FUNCTIONAL); + if (!rc.ok()) + { + FAPI_ERR("proc_chiplet_scominit: Error from fapiGetChildChiplets"); + break; + } + + // apply MCS SCOM initfile only for functional chiplets + for (std::vector<fapi::Target>::iterator i = mcs_targets.begin(); + (i != mcs_targets.end()) && rc.ok(); + i++) + { + // execute MCS SCOM initfile + initfile_targets.clear(); + initfile_targets.push_back(*i); + FAPI_INF("proc_chiplet_scominit: Executing %s on %s", + PROC_CHIPLET_SCOMINIT_MCS_IF, i->toEcmdString()); + FAPI_EXEC_HWP( + rc, + fapiHwpExecInitFile, + initfile_targets, + PROC_CHIPLET_SCOMINIT_MCS_IF); + if (!rc.ok()) + { + FAPI_ERR("proc_chiplet_scominit: Error from fapiHwpExecInitfile executing %s on %s", + PROC_CHIPLET_SCOMINIT_MCS_IF, + i->toEcmdString()); + break; + } + } + if (!rc.ok()) + { + break; + } } // unsupported target type else diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.H b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.H index c77eedf29..15da9670b 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.H +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_chiplet_scominit.H,v 1.6 2012/08/11 03:43:12 jmcgill Exp $ +// $Id: proc_chiplet_scominit.H,v 1.8 2013/01/20 19:30:37 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_chiplet_scominit.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -50,6 +50,9 @@ //------------------------------------------------------------------------------ const char * const PROC_CHIPLET_SCOMINIT_FBC_IF = "p8.fbc.scom.if"; +const char * const PROC_CHIPLET_SCOMINIT_NX_IF = "p8.nx.scom.if"; +const char * const PROC_CHIPLET_SCOMINIT_AS_IF = "p8.as.scom.if"; +const char * const PROC_CHIPLET_SCOMINIT_MCS_IF = "p8.mcs.scom.if"; //------------------------------------------------------------------------------ // Structure definitions @@ -74,6 +77,9 @@ extern "C" { * @param[in] i_target Reference to target * If TARGET_TYPE_PROC_CHIP, calls: * - p8.fbc.scom.initfile + * - p8.nx.scom.initfile + * - p8.as.scom.initfile + * - p8.mcs.scom.initfile for each functional MCS chiplet * * @return ReturnCode */ diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit.C b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit.C new file mode 100644 index 000000000..521a9b42c --- /dev/null +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit.C @@ -0,0 +1,119 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_xbus_scominit.C,v 1.2 2013/01/20 19:24:27 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_xbus_scominit.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2012 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : proc_xbus_scominit.C +// *! DESCRIPTION : Invoke XBUS initfile (FAPI) +// *! +// *! OWNER NAME : Mike Jones Email: mjjones@us.ibm.com +// *! BACKUP NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! +// *! ADDITIONAL COMMENTS : +// *! +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapiHwpExecInitFile.H> +#include <proc_xbus_scominit.H> + +extern "C" { + +//------------------------------------------------------------------------------ +// Function definitions +//------------------------------------------------------------------------------ + +// HWP entry point, comments in header +fapi::ReturnCode proc_xbus_scominit( + const fapi::Target & i_xbus_target, + const fapi::Target & i_this_pu_target, + const fapi::Target & i_other_pu_target) +{ + fapi::ReturnCode rc; + std::vector<fapi::Target> targets; + uint8_t xbus_enable_attr; + + // mark HWP entry + FAPI_INF("proc_xbus_scominit: Start"); + + do + { + // query XBUS partial good attribute + rc = FAPI_ATTR_GET(ATTR_PROC_X_ENABLE, + &i_this_pu_target, + xbus_enable_attr); + if (!rc.ok()) + { + FAPI_ERR("proc_xbus_scominit: Error querying ATTR_PROC_X_ENABLE"); + break; + } + + if (xbus_enable_attr != fapi::ENUM_ATTR_PROC_X_ENABLE_ENABLE) + { + FAPI_ERR("proc_xbus_scominit: Partial good attribute error"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_XBUS_SCOMINIT_PARTIAL_GOOD_ERR); + break; + } + + // obtain target type to determine which initfile(s) to execute + targets.push_back(i_xbus_target); + targets.push_back(i_this_pu_target); + targets.push_back(i_other_pu_target); + + // processor XBUS chiplet target + if ((i_xbus_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT) && + (i_this_pu_target.getType() == fapi::TARGET_TYPE_PROC_CHIP) && + (i_other_pu_target.getType() == fapi::TARGET_TYPE_PROC_CHIP)) + { + FAPI_INF("proc_xbus_scominit: Executing %s on %s", + XBUS_IF, i_xbus_target.toEcmdString()); + FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, targets, XBUS_IF); + if (!rc.ok()) + { + FAPI_ERR("proc_xbus_scominit: Error from fapiHwpExecInitfile executing %s on %s", + XBUS_IF, i_xbus_target.toEcmdString()); + break; + } + } + // unsupported target type + else + { + FAPI_ERR("proc_xbus_scominit: Unsupported target type(s)"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_XBUS_SCOMINIT_INVALID_TARGET); + break; + } + } while (0); + + // mark HWP exit + FAPI_INF("proc_xbus_scominit: End"); + return rc; +} + + +} // extern "C" diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit.H b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit.H new file mode 100644 index 000000000..0606a76e1 --- /dev/null +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit.H @@ -0,0 +1,93 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_xbus_scominit.H,v 1.1 2012/08/11 18:24:30 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_xbus_scominit.H,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2012 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : proc_xbus_scominit.H +// *! DESCRIPTION : Invoke XBUS initfile (FAPI) +// *! +// *! OWNER NAME : Mike Jones Email: mjjones@us.ibm.com +// *! BACKUP NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! +// *! ADDITIONAL COMMENTS : +// *! +//------------------------------------------------------------------------------ + +#ifndef PROC_XBUS_SCOMINIT_H_ +#define PROC_XBUS_SCOMINIT_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi.H> + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ +const char * const XBUS_IF = "p8.xbus.scom.if"; + +//------------------------------------------------------------------------------ +// Structure definitions +//------------------------------------------------------------------------------ + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode +(*proc_xbus_scominit_FP_t)(const fapi::Target & i_target, + const fapi::Target & i_this_pu_target, + const fapi::Target & i_other_pu_target); + +extern "C" { + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + +/** + * @brief HWP that calls the XBUS SCOM initfiles + * + * Should be called for all valid/connected XBUS endpoints + * + * @param[in] i_xbus_target Reference to XBUS target + * i_this_pu_target Reference to enclosing chip target + * i_other_pu_target Reference to connected chip target + * If i_xbus_target is TARGET_TYPE_XBUS_ENDPOINT, + * i_this_pu_target is TARGET_TYPE_PROC_CHIP, + * i_other_pu_target is TARGET_TYPE_PROC_CHIP, + * calls: + * - p8.xbus.scom.initfile + * + * @return ReturnCode + */ +fapi::ReturnCode proc_xbus_scominit( + const fapi::Target & i_xbus_target, + const fapi::Target & i_this_pu_target, + const fapi::Target & i_other_pu_target); + + +} // extern "C" + +#endif // PROC_XBUS_SCOMINIT_H_ diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit_errors.xml b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit_errors.xml new file mode 100644 index 000000000..bd2afb999 --- /dev/null +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit_errors.xml @@ -0,0 +1,34 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- Error definitions for proc_xbus_scominit procedure --> +<hwpErrors> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_XBUS_SCOMINIT_INVALID_TARGET</rc> + <description>Invalid target type presented to proc_xbus_scominit HWP (expects TARGET_TYPE_XBUS_ENDPOINT).</description> + </hwpError> + <hwpError> + <rc>RC_PROC_XBUS_SCOMINIT_PARTIAL_GOOD_ERR</rc> + <description>Partial good attribute state does not allow for action on chiplet target.</description> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C index 95ff319f4..f941f4e8f 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_pcie_scominit.C,v 1.1 2012/11/05 21:52:40 jmcgill Exp $ +// $Id: proc_pcie_scominit.C,v 1.3 2013/01/20 19:27:41 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_scominit.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -356,6 +356,7 @@ fapi::ReturnCode proc_pcie_scominit( const fapi::Target & i_target) { fapi::ReturnCode rc; + uint8_t pcie_enabled; // mark HWP entry FAPI_INF("proc_pcie_scominit: Start"); @@ -370,26 +371,44 @@ fapi::ReturnCode proc_pcie_scominit( break; } - // initialize/configure/finalize IOP programming - rc = proc_pcie_scominit_iop_init(i_target); + // query PCIE partial good attribute + rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_ENABLE, + &i_target, + pcie_enabled); if (!rc.ok()) { - FAPI_ERR("proc_pcie_scominit: Error from proc_pcie_scominit_iop_init"); + FAPI_ERR("proc_pcie_scominit: Error querying ATTR_PROC_PCIE_ENABLE"); break; } - rc = proc_pcie_scominit_iop_config(i_target); - if (!rc.ok()) + // initialize/configure/finalize IOP programming (only if partial good + // attribute is set) + if (pcie_enabled == fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE) { - FAPI_ERR("proc_pcie_scominit: Error from proc_pcie_scominit_iop_config"); - break; - } + rc = proc_pcie_scominit_iop_init(i_target); + if (!rc.ok()) + { + FAPI_ERR("proc_pcie_scominit: Error from proc_pcie_scominit_iop_init"); + break; + } - rc = proc_pcie_scominit_iop_complete(i_target); - if (!rc.ok()) + rc = proc_pcie_scominit_iop_config(i_target); + if (!rc.ok()) + { + FAPI_ERR("proc_pcie_scominit: Error from proc_pcie_scominit_iop_config"); + break; + } + + rc = proc_pcie_scominit_iop_complete(i_target); + if (!rc.ok()) + { + FAPI_ERR("proc_pcie_scominit: Error from proc_pcie_scominit_iop_complete"); + break; + } + } + else { - FAPI_ERR("proc_pcie_scominit: Error from proc_pcie_scominit_iop_complete"); - break; + FAPI_DBG("proc_pcie_scominit: Skipping initialization (partial good)"); } } while(0); diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C b/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C index c173a7bf8..d31a0d68f 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_start_clocks_chiplets.C,v 1.10 2012/12/12 10:43:10 rkoester Exp $ +// $Id: proc_start_clocks_chiplets.C,v 1.13 2013/01/20 19:26:07 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_start_clocks_chiplets.C,v $ //------------------------------------------------------------------------------ // *| @@ -298,8 +298,6 @@ fapi::ReturnCode proc_start_clocks_get_partial_good_vector( } - FAPI_DBG("proc_start_clocks_get_partial_good_vector: picked partial good regions vector is (%016llX)", *o_chiplet_reg_vec); - } while(0); @@ -438,8 +436,6 @@ fapi::ReturnCode proc_start_clocks_chiplet_check_clk_status_reg( break; } - // intialize reference databuffer - rc_ecmd |= vec_data.flushTo0(); // load it with reference data rc_ecmd |= vec_data.setDoubleWord(0, i_chiplet_clkreg_vec); // generate expected value databuffer @@ -717,7 +713,7 @@ fapi::ReturnCode proc_start_clocks_generic_chiplet( ); if (rc) { - FAPI_ERR("proc_start_clocks_partial_good_vector: Error getting partial good region vector"); + FAPI_ERR("proc_start_clocks_generic_chiplet: Error getting partial good region vector"); break; } @@ -793,6 +789,9 @@ fapi::ReturnCode proc_start_clocks_chiplets(const fapi::Target& i_target, bool xbus, bool abus, bool pcie) { fapi::ReturnCode rc; + uint8_t xbus_enable_attr; + uint8_t abus_enable_attr; + uint8_t pcie_enable_attr; // mark HWP entry FAPI_IMP("proc_start_clocks_chiplets: Entering ..."); @@ -801,38 +800,92 @@ fapi::ReturnCode proc_start_clocks_chiplets(const fapi::Target& i_target, { if (xbus) { - FAPI_DBG("Starting X bus chiplet clocks ..."); - rc = proc_start_clocks_generic_chiplet( - i_target, - X_BUS_CHIPLET_0x04000000); - if (rc) + // query XBUS partial good attribute + rc = FAPI_ATTR_GET(ATTR_PROC_X_ENABLE, + &i_target, + xbus_enable_attr); + if (!rc.ok()) { + FAPI_ERR("proc_start_clocks_chiplets: Error querying ATTR_PROC_X_ENABLE"); break; } + + if (xbus_enable_attr == fapi::ENUM_ATTR_PROC_X_ENABLE_ENABLE) + { + FAPI_DBG("Starting X bus chiplet clocks ..."); + rc = proc_start_clocks_generic_chiplet( + i_target, + X_BUS_CHIPLET_0x04000000); + if (rc) + { + FAPI_ERR("proc_start_clocks_chiplets: Error from proc_start_clocks_generic_chiplet (X)"); + break; + } + } + else + { + FAPI_DBG("Skipping XBUS chiplet clock start (partial good)."); + } } if (abus) { - FAPI_DBG("Starting A bus chiplet clocks ..."); - rc = proc_start_clocks_generic_chiplet( - i_target, - A_BUS_CHIPLET_0x08000000); - if (rc) + // query ABUS partial good attribute + rc = FAPI_ATTR_GET(ATTR_PROC_A_ENABLE, + &i_target, + abus_enable_attr); + if (!rc.ok()) { + FAPI_ERR("proc_start_clocks_chiplets: Error querying ATTR_PROC_A_ENABLE"); break; } + + if (abus_enable_attr == fapi::ENUM_ATTR_PROC_A_ENABLE_ENABLE) + { + FAPI_DBG("Starting A bus chiplet clocks ..."); + rc = proc_start_clocks_generic_chiplet( + i_target, + A_BUS_CHIPLET_0x08000000); + if (rc) + { + FAPI_ERR("proc_start_clocks_chiplets: Error from proc_start_clocks_generic_chiplet (A)"); + break; + } + } + else + { + FAPI_DBG("Skipping ABUS chiplet clock start (partial good)."); + } } if (pcie) { - FAPI_DBG("Starting PCIE chiplet clocks ..."); - rc = proc_start_clocks_generic_chiplet( - i_target, - PCIE_CHIPLET_0x09000000); - if (rc) + // query PCIE partial good attribute + rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_ENABLE, + &i_target, + pcie_enable_attr); + if (!rc.ok()) { + FAPI_ERR("proc_start_clocks_chiplets: Error querying ATTR_PROC_PCIE_ENABLE"); break; } + + if (pcie_enable_attr == fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE) + { + FAPI_DBG("Starting PCIE chiplet clocks ..."); + rc = proc_start_clocks_generic_chiplet( + i_target, + PCIE_CHIPLET_0x09000000); + if (rc) + { + FAPI_ERR("proc_start_clocks_chiplets: Error from proc_start_clocks_generic_chiplet (PCIE)"); + break; + } + } + else + { + FAPI_DBG("Skipping PCIE chiplet clock start (partial good)."); + } } } while (0); diff --git a/src/usr/hwpf/hwp/proc_fab_iovalid_errors.xml b/src/usr/hwpf/hwp/proc_fab_iovalid_errors.xml new file mode 100644 index 000000000..7d462067b --- /dev/null +++ b/src/usr/hwpf/hwp/proc_fab_iovalid_errors.xml @@ -0,0 +1,34 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_fab_iovalid_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- Error definitions for proc_fab_iovalid procedure --> +<hwpErrors> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_FAB_IOVALID_X_PARTIAL_GOOD_ERR</rc> + <description>X bus partial good attribute state does not allow for action on target.</description> + </hwpError> + <hwpError> + <rc>RC_PROC_FAB_IOVALID_A_PARTIAL_GOOD_ERR</rc> + <description>A bus partial good attribute state does not allow for action on target.</description> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.C b/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.C index 88ed00f97..a981d8c5a 100644 --- a/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.C +++ b/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_revert_sbe_mcs_setup.C,v 1.5 2012/11/16 04:48:35 jmcgill Exp $ +// $Id: proc_revert_sbe_mcs_setup.C,v 1.6 2013/01/20 15:55:42 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_revert_sbe_mcs_setup.C,v $ //------------------------------------------------------------------------------ // *| @@ -51,14 +51,32 @@ extern "C" //------------------------------------------------------------------------------ +// function: translate base SCOM address to chiplet specific offset +// parameters: i_input_addr => input SCOM address +// i_mcs_unit_num => chip unit number +// returns: translated SCOM address +//------------------------------------------------------------------------------ +uint64_t proc_revert_sbe_mcs_setup_xlate_address( + const uint64_t i_input_addr, + const uint8_t i_mcs_unit_num) +{ + return(i_input_addr + + (0x400 * (i_mcs_unit_num / 4)) + + (0x80 * (i_mcs_unit_num % 4))); +} + + +//------------------------------------------------------------------------------ // function: reset MCFGP BAR valid bit, base address and size fields to restore // register flush state -// parameters: i_target => MCS chiplet target +// parameters: i_target => chip target +// i_mcs_unit_num => chip unit number // returns: FAPI_RC_SUCCESS if register write is successful, // else failing return code //------------------------------------------------------------------------------ fapi::ReturnCode proc_revert_sbe_mcs_setup_reset_mcfgp( - const fapi::Target& i_target) + const fapi::Target& i_target, + const uint8_t i_mcs_unit_num) { fapi::ReturnCode rc; uint32_t rc_ecmd = 0x0; @@ -100,13 +118,17 @@ fapi::ReturnCode proc_revert_sbe_mcs_setup_reset_mcfgp( } // write register - rc = fapiPutScomUnderMask(i_target, - MCS_MCFGP_0x02011800, - mcfgp_data, - mcfgp_mask); + rc = fapiPutScomUnderMask( + i_target, + proc_revert_sbe_mcs_setup_xlate_address(MCS_MCFGP_0x02011800, + i_mcs_unit_num), + mcfgp_data, + mcfgp_mask); if (!rc.ok()) { - FAPI_ERR("proc_revert_sbe_mcs_setup_reset_mcfgp: fapiPutScomUnderMask error (MCS_MCFGP_0x02011800)"); + FAPI_ERR("proc_revert_sbe_mcs_setup_reset_mcfgp: fapiPutScomUnderMask error (MCS_MCFGP_0x%08llX)", + proc_revert_sbe_mcs_setup_xlate_address(MCS_MCFGP_0x02011800, + i_mcs_unit_num)); break; } } while(0); @@ -120,12 +142,14 @@ fapi::ReturnCode proc_revert_sbe_mcs_setup_reset_mcfgp( //------------------------------------------------------------------------------ // function: set MCI FIR Mask channel timeout bit, to restore register flush // state -// parameters: i_target => MCS chiplet target +// parameters: i_target => chip target +// i_mcs_unit_num => chip unit number // returns: FAPI_RC_SUCCESS if register write is successful, // else failing return code //------------------------------------------------------------------------------ fapi::ReturnCode proc_revert_sbe_mcs_setup_reset_mcifirmask( - const fapi::Target& i_target) + const fapi::Target& i_target, + const uint8_t i_mcs_unit_num) { fapi::ReturnCode rc; uint32_t rc_ecmd = 0x0; @@ -150,12 +174,16 @@ fapi::ReturnCode proc_revert_sbe_mcs_setup_reset_mcifirmask( } // write register - rc = fapiPutScom(i_target, - MCS_MCIFIRMASK_OR_0x02011845, - mcifirmask_or_data); + rc = fapiPutScom( + i_target, + proc_revert_sbe_mcs_setup_xlate_address(MCS_MCIFIRMASK_OR_0x02011845, + i_mcs_unit_num), + mcifirmask_or_data); if (!rc.ok()) { - FAPI_ERR("proc_revert_sbe_mcs_setup_reset_mcifirmask: fapiPutScom error (MCS_MCIFIRMASK_OR_0x02011845)"); + FAPI_ERR("proc_revert_sbe_mcs_setup_reset_mcifirmask: fapiPutScom error (MCS_MCIFIRMASK_OR_0x%08llX)", + proc_revert_sbe_mcs_setup_xlate_address(MCS_MCIFIRMASK_OR_0x02011845, + i_mcs_unit_num)); break; } } while(0); @@ -174,7 +202,10 @@ fapi::ReturnCode proc_revert_sbe_mcs_setup( const fapi::Target& i_target) { fapi::ReturnCode rc; + ecmdDataBufferBase gp0_data(64); ecmdDataBufferBase mcsmode1_reset_data(64); + bool mc_fenced[2] = { true, true }; + uint8_t mcs_unit_id = 0x0; // vector to hold MCS chiplet targets std::vector<fapi::Target> mcs_chiplets; @@ -184,12 +215,24 @@ fapi::ReturnCode proc_revert_sbe_mcs_setup( do { - // loop over all functional MCS chiplets, revert SBE configuration + // read GP0 to determine MCL/MCR partial good state + rc = fapiGetScom(i_target, NEST_GP0_0x02000000, gp0_data); + + if (!rc.ok()) + { + FAPI_ERR("proc_revert_sbe_mcs_setup: fapiGetScom error (NEST_GP0_0x02000000)"); + break; + } + + mc_fenced[0] = gp0_data.isBitClear(NEST_GP0_MCL_FENCE_B_BIT); + mc_fenced[1] = gp0_data.isBitClear(NEST_GP0_MCR_FENCE_B_BIT); + + // loop over all present MCS chiplets, revert SBE configuration // of BAR/FIR mask registers back to flush state rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_MCS_CHIPLET, mcs_chiplets, - fapi::TARGET_STATE_FUNCTIONAL); + fapi::TARGET_STATE_PRESENT); if (!rc.ok()) { FAPI_ERR("proc_revert_sbe_mcs_setup: Error from fapiGetChildChiplets"); @@ -200,28 +243,50 @@ fapi::ReturnCode proc_revert_sbe_mcs_setup( i != mcs_chiplets.end(); i++) { - rc = proc_revert_sbe_mcs_setup_reset_mcfgp(*i); - if (!rc.ok()) - { - FAPI_ERR("proc_revert_sbe_mcs_setup: Error from proc_revert_sbe_mcs_setup_reset_mcfgp"); - break; - } + // read chip unit number + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, + &(*i), + mcs_unit_id); - FAPI_DBG("proc_revert_sbe_mcs_setup: reset MCSMODE1"); - rc = fapiPutScom(*i, - MCS_MCSMODE1_0x02011808, - mcsmode1_reset_data); if (!rc.ok()) { - FAPI_ERR("proc_revert_sbe_mcs_setup: fapiPutScom error (MCS_MCSMODE1_0x02011808)"); + FAPI_ERR("proc_revert_sbe_mcs_setup: Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)"); break; } - rc = proc_revert_sbe_mcs_setup_reset_mcifirmask(*i); - if (!rc.ok()) + // reset all chiplets which are present (based on GP0 partial good data) + // this handles the case of reverting configuration which was written + // by SBE code for chiplets which are not considered functional by platform + if (!mc_fenced[mcs_unit_id / 4]) { - FAPI_ERR("proc_revert_sbe_mcs_setup: Error from proc_revert_sbe_mcs_setup_reset_mcfgp"); - break; + rc = proc_revert_sbe_mcs_setup_reset_mcfgp(i_target, + mcs_unit_id); + if (!rc.ok()) + { + FAPI_ERR("proc_revert_sbe_mcs_setup: Error from proc_revert_sbe_mcs_setup_reset_mcfgp"); + break; + } + + FAPI_DBG("proc_revert_sbe_mcs_setup: reset MCSMODE1"); + rc = fapiPutScom( + i_target, + proc_revert_sbe_mcs_setup_xlate_address(MCS_MCSMODE1_0x02011808, + mcs_unit_id), + mcsmode1_reset_data); + if (!rc.ok()) + { + FAPI_ERR("proc_revert_sbe_mcs_setup: fapiPutScom error (MCS_MCSMODE1_0x%08llX)", + proc_revert_sbe_mcs_setup_xlate_address(MCS_MCSMODE1_0x02011808, mcs_unit_id)); + break; + } + + rc = proc_revert_sbe_mcs_setup_reset_mcifirmask(i_target, + mcs_unit_id); + if (!rc.ok()) + { + FAPI_ERR("proc_revert_sbe_mcs_setup: Error from proc_revert_sbe_mcs_setup_reset_mcfgp"); + break; + } } } } while(0); diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.H b/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.H index f52ed6400..90719e5ba 100644 --- a/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.H +++ b/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_revert_sbe_mcs_setup.H,v 1.2 2012/07/23 14:16:07 jmcgill Exp $ +// $Id: proc_revert_sbe_mcs_setup.H,v 1.3 2013/01/20 15:55:45 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_revert_sbe_mcs_setup.H,v $ //------------------------------------------------------------------------------ // *| @@ -56,6 +56,10 @@ // Constant definitions //------------------------------------------------------------------------------ +// Nest GP0 register constants +const uint32_t NEST_GP0_MCL_FENCE_B_BIT = 51; +const uint32_t NEST_GP0_MCR_FENCE_B_BIT = 52; + // MCFGP register constants const uint32_t MCFGP_VALID_BIT = 0; const uint32_t MCFGP_UNITS_PER_GROUP_START_BIT = 1; |
