diff options
Diffstat (limited to 'src/usr/hwpf/hwp')
41 files changed, 5562 insertions, 4908 deletions
diff --git a/src/usr/hwpf/hwp/activate_powerbus/activate_powerbus.C b/src/usr/hwpf/hwp/activate_powerbus/activate_powerbus.C index 110cb065e..2cbfc4409 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/activate_powerbus.C +++ b/src/usr/hwpf/hwp/activate_powerbus/activate_powerbus.C @@ -39,6 +39,7 @@ #include <trace/interface.H> #include <initservice/taskargs.H> #include <errl/errlentry.H> +#include <errl/errludtarget.H> #include <initservice/isteps_trace.H> #include <hwpisteperror.H> @@ -55,6 +56,7 @@ #include <pbusLinkSvc.H> #include "proc_build_smp/proc_build_smp.H" +#include <intr/interrupt.H> namespace ACTIVATE_POWERBUS { @@ -64,6 +66,7 @@ using namespace ISTEP; using namespace TARGETING; using namespace EDI_EI_INITIALIZATION; using namespace fapi; +using namespace ERRORLOG; //****************************************************************************** // wrapper function to call proc_build_smp @@ -233,6 +236,52 @@ void* call_proc_build_smp( void *io_pArgs ) "SUCCESS : proc_build_smp" ); } + // At the point where we can now change the proc chips to use + // XSCOM rather than FSISCOM which is the default. + + TARGETING::TargetHandleList procChips; + getAllChips(procChips, TYPE_PROC); + + TARGETING::TargetHandleList::iterator curproc = procChips.begin(); + + // Loop through all proc chips + while(curproc != procChips.end()) + { + TARGETING::Target* l_proc_target = *curproc; + + // If the proc chip supports xscom.. + if (l_proc_target->getAttr<ATTR_PRIMARY_CAPABILITIES>() + .supportsXscom) + { + ScomSwitches l_switches = + l_proc_target->getAttr<ATTR_SCOM_SWITCHES>(); + + // If Xscom is not already enabled. + if ((l_switches.useXscom != 1) || (l_switches.useFsiScom != 0)) + { + l_switches.useFsiScom = 0; + l_switches.useXscom = 1; + + // Turn off FSI scom and turn on Xscom. + l_proc_target->setAttr<ATTR_SCOM_SWITCHES>(l_switches); + } + } + + // Enable PSI interrupts even if can't Xscom as + // Pbus is up and interrupts can flow + l_errl = INTR::enablePsiIntr(l_proc_target); + if(l_errl) + { + // capture the target data in the elog + ErrlUserDetailsTarget(l_proc_target).addToLog( l_errl ); + + break; + } + + ++curproc; + } + + } while (0); TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pcb_scom_errors.H b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pcb_scom_errors.H new file mode 100755 index 000000000..522960e67 --- /dev/null +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pcb_scom_errors.H @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pcb_scom_errors.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: p8_pcb_scom_errors.H,v 1.3 2013/02/16 20:26:51 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pcb_scom_errors.H,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Gebhard Weber Email: gweber@de.ibm.com +// *! +// *! General Description: Defines FFDC error codes for the procedures +// *! proc_timeout_error and proc_parity_error +//------------------------------------------------------------------------------ + +#ifndef P8_PCB_SCOM_ERRORS_H_ +#define P8_PCB_SCOM_ERRORS_H_ + +//------------------------------------------------------------------------------ +// Function definitions +//------------------------------------------------------------------------------ + +extern "C" { + + enum PCB_ERRORS { + PIB_NO_ERROR = 0x0, + PIB_XSCOM_ERROR = 0x1, + PIB_OFFLINE_ERROR = 0x2, + PIB_PARTIAL_ERROR = 0x3, + PIB_ADDRESS_ERROR = 0x4, + PIB_CLOCK_ERROR = 0x5, + PIB_PARITY_ERROR = 0x6, + PIB_TIMEOUT_ERROR = 0x7 + }; + +} // extern "C" + +#endif // P8_PCB_SCOM_ERRORS_H_ + diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_poreslw_init.C b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_poreslw_init.C index 67f945a36..806c7d475 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_poreslw_init.C +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_poreslw_init.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_poreslw_init.C,v 1.9 2012/12/20 05:21:05 stillgs Exp $ +// $Id: p8_poreslw_init.C,v 1.11 2013/02/19 15:37:34 stillgs Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_poreslw_init.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -65,6 +65,7 @@ #include "p8_poreslw_init.H" #include "p8_pfet_init.H" #include "p8_pmc_deconfig_setup.H" +#include "p8_pcb_scom_errors.H" extern "C" { @@ -331,6 +332,8 @@ poreslw_ex_setup(const Target& i_target) uint64_t address; bool core_flag = false; bool error_flag = false; + //@thi - fixed compiler error - Greg will fix this in next version + //uint32_t fsierror = 0; uint8_t pm_sleep_type; uint8_t pm_sleep_entry ; @@ -346,11 +349,11 @@ poreslw_ex_setup(const Target& i_target) const uint32_t PM_SLEEP_POWER_OFF_SEL_BIT = 2; const uint32_t PM_WINKLE_POWER_DOWN_EN_BIT = 3; const uint32_t PM_WINKLE_POWER_UP_EN_BIT = 4; - const uint32_t PM_WINKLE_POWER_OFF_SEL_BIT = 5; + const uint32_t PM_WINKLE_POWER_OFF_SEL_BIT = 5; - - const uint32_t IDLE_STATE_OVERRIDE_EN = 6; - const uint32_t PM_DISABLE = 0; + //@thi - fixed compiler error - Greg will fix this in next version + //const uint32_t IDLE_STATE_OVERRIDE_EN = 6; + const uint32_t PM_DISABLE = 0; do { @@ -475,12 +478,15 @@ poreslw_ex_setup(const Target& i_target) FAPI_INF("\tWARNING: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"); - pm_sleep_entry = 1; // 0=HW, 1=assisted - pm_sleep_exit = 1; // 0=HW, 1=assisted + pm_sleep_entry = 0; // 0=assisted, 1=HW + pm_sleep_exit = 0; // 0=assisted, 1=HW pm_sleep_type = 1; // 0=fast, 1=deep - pm_winkle_entry = 1; // 0=HW, 1=assisted - pm_winkle_exit = 1; // 0=HW, 1=assisted + // Due to L3 Hight Availability Write Pointers that must be + // saved upon a Deep Winkle Entry, this transition must be + // assisted. + pm_winkle_entry = 0; // 0=assisted, 1=HW + pm_winkle_exit = 0; // 0=assisted, 1=HW pm_winkle_type = 1; // 0=fast, 1=deep @@ -508,28 +514,26 @@ poreslw_ex_setup(const Target& i_target) e_rc |= clear_data.flushTo1(); // Set to 1s to be used for WAND e_rc |= set_data.flushTo0(); // Set to 0s to be used for WOR - // If sleep entry = 1 (assisted), sleep power down enable = 0 - // else sleep entry = 0 (hardware), sleep power down enable = 1 + // If sleep entry = 1 (hardware), sleep power down enable = 1 + // else sleep entry = 0 (assisted), sleep power down enable = 0 if (pm_sleep_entry) - { - e_rc |= clear_data.clearBit(PM_SLEEP_POWER_DOWN_EN_BIT); - + { + e_rc |= set_data.setBit(PM_SLEEP_POWER_DOWN_EN_BIT); } else { - e_rc |= set_data.setBit(PM_SLEEP_POWER_DOWN_EN_BIT); + e_rc |= clear_data.clearBit(PM_SLEEP_POWER_DOWN_EN_BIT); } - // If sleep exit = 1 (assisted), sleep power up enable = 0 - // else sleep exit = 0 (hardware), sleep power up enable = 1 + // If sleep exit = 1 (hardware), sleep power up enable = 1 + // else sleep exit = 0 (assisted), sleep power up enable = 0 if (pm_sleep_exit) { - e_rc |= clear_data.clearBit(PM_SLEEP_POWER_UP_EN_BIT); - + e_rc |= set_data.setBit(PM_SLEEP_POWER_UP_EN_BIT); } else { - e_rc |= set_data.setBit(PM_SLEEP_POWER_UP_EN_BIT); + e_rc |= clear_data.clearBit(PM_SLEEP_POWER_UP_EN_BIT); } // If sleep type = 1 (deep), sleep power up sel = 1 @@ -544,28 +548,26 @@ poreslw_ex_setup(const Target& i_target) e_rc |= clear_data.clearBit(PM_SLEEP_POWER_OFF_SEL_BIT); } - // If winkle entry = 1 (assisted), winkle power down enable = 0 - // else winkle entry = 0 (hardware), winkle power down enable = 1 + // If winkle entry = 1 (hardware), winkle power down enable = 1 + // else winkle entry = 0 (assisted), winkle power down enable = 0 if (pm_winkle_entry) { - e_rc |= clear_data.clearBit(PM_WINKLE_POWER_DOWN_EN_BIT); - + e_rc |= set_data.setBit(PM_WINKLE_POWER_DOWN_EN_BIT); } else { - e_rc |= set_data.setBit(PM_WINKLE_POWER_DOWN_EN_BIT); + e_rc |= clear_data.clearBit(PM_WINKLE_POWER_DOWN_EN_BIT); } - // If winkle exit = 1 (assisted), winkle power up enable = 0 - // else winkle exit = 0 (hardware), winkle power up enable = 1 + // If winkle exit = 1 (hardware), winkle power up enable = 1 + // else winkle exit = 0 (assisted), winkle power up enable = 0 if (pm_winkle_exit) { - e_rc |= clear_data.clearBit(PM_WINKLE_POWER_UP_EN_BIT); - + e_rc |= set_data.setBit(PM_WINKLE_POWER_UP_EN_BIT); } else { - e_rc |= set_data.setBit(PM_WINKLE_POWER_UP_EN_BIT); + e_rc |= clear_data.clearBit(PM_WINKLE_POWER_UP_EN_BIT); } // If winkle type = 1 (deep), winkle power up sel = 1 @@ -610,8 +612,6 @@ poreslw_ex_setup(const Target& i_target) FAPI_INF("\tDisable the PCBS Heartbeat EX %x", l_ex_number); address = EX_SLAVE_CONFIG_0x100F001E + (l_ex_number * 0x01000000); -//@thi - Temporary workaround. Greg Still agreed to fix this in his next version -// l_rc = fapiGetScom(l_exChiplets[j], address, data); l_rc = fapiGetScom(i_target, address, data); if(!l_rc.ok()) { @@ -635,13 +635,45 @@ poreslw_ex_setup(const Target& i_target) } // -------------------------------------- - // Check if SBE code has already cleard the OHA override. + // Check if SBE code has already cleared the OHA override. // As chiplets may be enabled but offline (eg in Winkle) // treat SCOM errors as off-line (eg skip it). If online - // and set, clear the override. + // and set, clear the override. + + /* GSS: removed as Cronus always puts a message out of (PCB_OFFLINE) + even though this code is meant to handle it. As this messge + can cause confusion in the lab, the check is being removed. + bool oha_accessible = true; l_rc = fapiGetScom(l_exChiplets[j], EX_OHA_MODE_REG_RWx1002000D, data); - if(l_rc.ok()) - { + if(!l_rc.ok()) + { + l_rc = fapiGetCfamRegister( i_target, CFAM_FSI_STATUS_0x00001007, data ); + if(!l_rc.ok()) + { + FAPI_ERR("Error reading CFAM FSI Status Register"); + break; + } + FAPI_INF( "CFAM_FSI_STATUS_0x00001007: 0x%X", data.getWord(0)); + e_rc |= data.extractToRight( &fsierror, 17, 3 ); + if ( e_rc ) + { + l_rc.setEcmdError(e_rc); + break; + } + if (fsierror == PIB_OFFLINE_ERROR) + { + FAPI_INF( "Chiplet offline error detected. Skipping OHA Override clearing"); + oha_accessible = false; + } + else + { + FAPI_ERR("Scom reading OHA_MODE"); + break; + } + } + // Process if OHA accessible. + if (oha_accessible) + { if (data.isBitSet(IDLE_STATE_OVERRIDE_EN)) { @@ -662,10 +694,13 @@ poreslw_ex_setup(const Target& i_target) } } } + End of check removal + */ // -------------------------------------- // Check that PM function is enabled (eg not disabled). // If not, remove the disable + address = EX_PMGP0_0x100F0100 + (l_ex_number * 0x01000000); l_rc=fapiGetScom(i_target, address, data); if(!l_rc.ok()) @@ -740,6 +775,5 @@ poreslw_ex_setup(const Target& i_target) return l_rc; } - } //end extern diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.H b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.H index e85bec40a..8163897af 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.H +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.H @@ -20,17 +20,23 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_image_help_base.H,v 1.12 2013/02/12 21:02:38 cmolsen Exp $ +// $Id: p8_image_help_base.H,v 1.15 2013/03/01 21:55:24 cmolsen Exp $ //------------------------------------------------------------------------------ // Title: p8_image_help_base.H // Description: Contains the most basic structures and defines needed for // image building and interpretation. //------------------------------------------------------------------------------ -const uint32_t MAX_REF_IMAGE_SIZE = 5000000; // Max reference image size. +// +// Various image/ring buffer sizes. Must be used by all users (VBU, FSP, HB, HBI, Cronus) +// +const uint32_t MAX_REF_IMAGE_SIZE = 5000000; // Max reference image size. +const uint32_t FIXED_SEEPROM_WORK_SPACE= 128*1024; // Max work space for Seeprom img. +const uint32_t MAX_SEEPROM_IMAGE_SIZE = 56*1024; // Max Seeprom image size. // Fixed SLW image size (Ensure 128-byte alignment.) -const uint32_t FIXED_SLW_IMAGE_SIZE = 1024*1024; // Fixed SLW image size assumed by HB, PHYP and slw_build(). -const uint32_t FIXED_RING_BUF_SIZE = 60000; // Fixed ring buffer size assumed by HB, PHYP and slw_build(). Only use when emulating FAPI calls and for command-line utilities. +const uint32_t FIXED_SLW_IMAGE_SIZE = 1024*1024; // Fixed SLW image size for _fixed. +const uint32_t FIXED_RING_BUF_SIZE = 60000; // Fixed ring buf size for _fixed. + const uint8_t MAX_VPD_TYPES = 2; // #G and #R, so far. #define CHIPLET_ID_MIN 0x00 #define CHIPLET_ID_MAX 0x1F @@ -38,8 +44,9 @@ const uint8_t MAX_CHIPLETS = CHIPLET_ID_MAX-CHIPLET_ID_MIN+1; const uint32_t ASM_RS4_LAUNCH_BUF_SIZE = 24; // Byte size of RS4 launch buffer. const uint32_t WF_ENCAP_SIZE = 400; // Byte size of WF encapsulation. // (Actually, only 304B but may change.) -const uint32_t WF_WORST_CASE_SIZE_FAC = 3; // WC WF size = 3x ring length. +const uint32_t WF_WORST_CASE_SIZE_FAC = 4; // WC WF size = 3x ring length. // (Assumes 12B per write.) + // (4x w/waits instructions.) const uint32_t LISTING_STRING_SIZE = 256; const uint64_t MAX_UINT64_T = (uint64_t)0xFFFFFFFF<<32 | (uint64_t)0xFFFFFFFF; diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize_errors.xml b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize_errors.xml index eaf1329d7..eac3d2f2c 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize_errors.xml +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize_errors.xml @@ -24,9 +24,16 @@ <hwpErrors> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_XIPC_INPUT_IMAGE_SIZE_MESS</rc> - <description>Supplied max image size is too small or image too large.</description> - <ffdc>DATA_IMG_SIZE_INP</ffdc> + <rc>RC_PROC_XIPC_IMAGE_WORK_SPACE_MESS</rc> + <description>Max work space for output image is not equal to FIXED_SEEPROM_WORK_SPACE.</description> + <ffdc>DATA_IMG_SIZE_MAX</ffdc> + <ffdc>DATA_IMG_SIZE_WORK_SPACE</ffdc> +</hwpError> +<!-- *********************************************************************** --> +<hwpError> + <rc>RC_PROC_XIPC_IMAGE_SIZE_MESS</rc> + <description>Supplied max image size is smaller than input image.</description> + <ffdc>DATA_IMG_SIZE</ffdc> <ffdc>DATA_IMG_SIZE_MAX</ffdc> </hwpError> <!-- *********************************************************************** --> @@ -69,6 +76,12 @@ </hwpError> <!-- *********************************************************************** --> <hwpError> + <rc>RC_PROC_XIPC_GEN_SCOM_ERROR</rc> + <description>Updating Scom NC table w/L2 or L3 data failed. Check rc code in p8_delta_scan_rw.h</description> + <ffdc>RC_LOCAL</ffdc> +</hwpError> +<!-- *********************************************************************** --> +<hwpError> <rc>RC_PROC_XIPC_PLL_RING_SIZE_TOO_LARGE</rc> <description>PLL ring size returned from attribute is too large.</description> <ffdc>DATA_ATTRIBUTE_RING_SIZE</ffdc> @@ -180,6 +193,30 @@ </hwpError> <!-- *********************************************************************** --> <hwpError> + <rc>RC_PROC_XIPC_CREATE_FIXED_IMAGE_ERROR</rc> + <description>Error associated with creating and initializing fixed image and fixed .slw and .ffdc sections.</description> + <ffdc>RC_LOCAL</ffdc> +</hwpError> +<!-- *********************************************************************** --> +<hwpError> + <rc>RC_PROC_XIPC_MAX_IMAGE_SIZE_EXCEEDED</rc> + <description>New image size exceeds max allowed size.</description> + <ffdc>DATA_IMG_SIZE_NEW</ffdc> + <ffdc>DATA_IMG_SIZE_MAX</ffdc> +</hwpError> +<!-- *********************************************************************** --> +<hwpError> + <rc>RC_PROC_XIPC_APPEND_SLW_SECTION_ERROR</rc> + <description>Error associated with adding empty SLW section for ram and scom tables.</description> + <ffdc>RC_LOCAL</ffdc> +</hwpError> +<!-- *********************************************************************** --> +<hwpError> + <rc>RC_PROC_XIPC_BAD_CODE_OR_PARM</rc> + <description>Shouldn't be in this code section or invalid parm.</description> +</hwpError> +<!-- *********************************************************************** --> +<hwpError> <rc>RC_PROC_XIPC_UNKNOWN_ERROR</rc> <description>Unknown error. (Shouldn't be in this code section.)</description> <ffdc>RC_LOCAL</ffdc> diff --git a/src/usr/hwpf/hwp/bus_training/io_clear_firs.C b/src/usr/hwpf/hwp/bus_training/io_clear_firs.C new file mode 100644 index 000000000..43694298c --- /dev/null +++ b/src/usr/hwpf/hwp/bus_training/io_clear_firs.C @@ -0,0 +1,241 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/bus_training/io_clear_firs.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: io_clear_firs.C,v 1.5 2013/02/20 09:40:22 jaswamin Exp $
+// *!***************************************************************************
+// *! (C) Copyright International Business Machines Corp. 2012, 2013
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *!***************************************************************************
+// *! FILENAME : io_clear_firs.C
+// *! TITLE :
+// *! DESCRIPTION : To clear summary fir registers
+// *! CONTEXT :
+// *!
+// *! OWNER NAME : Swaminathan, Janani Email: jaswamin@in.ibm.com
+// *! BACKUP NAME : Varghese, Varkey Email: varkey.kv@in.ibm.com
+// *!
+// *!***************************************************************************
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|Author: | Date: | Comment:
+// --------|--------|--------|--------------------------------------------------
+// 1.3 |varkeykv|02/18/13| Missing function check in
+// 1.2 |jaswamin|02/14/13| function for reading the fir scom register contents, enums and arrays for doing fir isolation
+// 1.1 |jaswamin|02/14/13| Additions for reading the fir register.
+// 1.0 |jaswamin|01/30/13| Initial check in .
+//------------------------------------------------------------------------------
+
+#include <fapi.H>
+#include "io_clear_firs.H"
+//#include "gcr_funcs.H"
+//#include "ei4_regs.h"
+
+extern "C" {
+
+
+using namespace fapi; + +// For clearing the FIR mask , used by io run training +ReturnCode clear_fir_mask_reg(const Target &i_target,fir_io_interface_t i_chip_interface){ + + ReturnCode rc; +//@thi - Fixed compiler error. Varkey will fix this in next version +// uint32_t rc_ecmd=0; + uint64_t scom_address64=0; + ecmdDataBufferBase putscom_data64(64),temp(64); + //rc_ecmd |=getscom_data64.flushTo0(); + //rc_ecmd |=putscom_data64.flushTo0(); + FAPI_INF("io_run_training:In the Clear FIR MASK register function "); + //get the 64 bit data + temp.setDoubleWord(0,fir_clear_mask_reg_addr[i_chip_interface]); + scom_address64=temp.getDoubleWord(0); + + //do the putscom + rc=fapiPutScom( i_target, scom_address64, putscom_data64); + + return(rc); + +}
+
+// for toggling the rx and tx fir reset.
+ReturnCode clear_fir_err_regs(const Target &i_target,io_interface_t i_chip_interface,uint32_t i_group){
+
+ ReturnCode rc;
+ uint32_t rc_ecmd=0;
+ uint16_t bits = 0;
+ ecmdDataBufferBase data_buffer;
+
+ ecmdDataBufferBase set_bits(16);
+ ecmdDataBufferBase clear_bits(16);
+
+ FAPI_DBG("In the Clear fir procedure");
+ //const Target *target_ptr=⌖
+
+ //set the rx_fir_reset bit
+ bits=rx_fir_reset;
+ rc_ecmd|=set_bits.insert(bits,0,16);
+ bits=rx_fir_reset_clear;
+ rc_ecmd|=clear_bits.insert(bits,0,16);
+ if(rc_ecmd)
+ {
+ rc.setEcmdError(rc_ecmd);
+ return(rc);
+ }
+ rc=GCR_write(i_target,i_chip_interface,rx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);}
+
+ //clear the rx_fir_reset bit
+ bits=0x0000;
+ rc_ecmd|=set_bits.insert(bits,0,16);
+ bits=rx_fir_reset_clear;
+ rc_ecmd|=clear_bits.insert(bits,0,16);
+ if(rc_ecmd)
+ {
+ rc.setEcmdError(rc_ecmd);
+ return(rc);
+ }
+ rc=GCR_write(i_target,i_chip_interface,rx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);}
+
+ //set the tx_fir_reset bit
+ bits=tx_fir_reset;
+ rc_ecmd|=set_bits.insert(bits,0,16);
+ bits=tx_fir_reset_clear;
+ rc_ecmd|=clear_bits.insert(bits,0,16);
+ if(rc_ecmd)
+ {
+ rc.setEcmdError(rc_ecmd);
+ return(rc);
+ }
+ rc=GCR_write(i_target,i_chip_interface,tx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);}
+
+ //clear the tx_fir_reset
+ bits=0x0000;
+ rc_ecmd|=set_bits.insert(bits,0,16);
+ bits=tx_fir_reset_clear;
+ rc_ecmd|=clear_bits.insert(bits,0,16);
+ if(rc_ecmd)
+ {
+ rc.setEcmdError(rc_ecmd);
+ return(rc);
+ }
+ rc=GCR_write(i_target,i_chip_interface,tx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);}
+
+ return(rc);
+
+
+}
+
+ReturnCode clear_fir_reg(const Target &i_target,fir_io_interface_t i_chip_interface){
+
+ ReturnCode rc;
+//@thi - Fixed compiler error. Varkey will fix this in next version +// uint32_t rc_ecmd=0;
+ uint64_t scom_address64=0;
+ ecmdDataBufferBase putscom_data64(64),temp(64);
+ //rc_ecmd |=getscom_data64.flushTo0();
+ //rc_ecmd |=putscom_data64.flushTo0();
+
+ //get the 64 bit data
+ temp.setDoubleWord(0,fir_clear_reg_addr[i_chip_interface]);
+ scom_address64=temp.getDoubleWord(0);
+
+ //do the putscom
+ rc=fapiPutScom( i_target, scom_address64, putscom_data64);
+
+ return(rc);
+
+}
+
+ReturnCode read_fir_reg(const Target &i_target,fir_io_interface_t i_chip_interface,ecmdDataBufferBase &o_databuf_64bit){
+
+ ReturnCode rc;
+ uint32_t rc_ecmd=0;
+ uint64_t scom_address64=0;
+ ecmdDataBufferBase temp(64);
+ rc_ecmd |=o_databuf_64bit.flushTo0();
+
+ //rc_ecmd |=putscom_data64.flushTo0();
+
+ //get the 64 bit scom address.
+ temp.setDoubleWord(0,fir_rw_reg_addr[i_chip_interface]);
+ scom_address64=temp.getDoubleWord(0);
+
+ //read the 64 bit fir register
+ rc=fapiGetScom(i_target,scom_address64,o_databuf_64bit);
+
+ return(rc);
+
+
+}
+
+ReturnCode io_clear_firs(const fapi::Target &i_target){
+
+ ReturnCode rc;
+ fir_io_interface_t interface;
+ io_interface_t gcr_interface; // requires different base address for gcr scoms
+ uint32_t group;
+
+ //on dmi
+ if( (i_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET )){
+ FAPI_DBG("This is a Processor DMI bus using base DMI scom address");
+ interface=FIR_CP_IOMC0_P0; // base scom for MC bus
+ gcr_interface=CP_IOMC0_P0;
+ group=3; // design requires us to swap
+
+ }
+ else if((i_target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP)){
+ FAPI_DBG("This is a Centaur DMI bus using base DMI scom address");
+ interface=FIR_CEN_DMI;
+ gcr_interface=CEN_DMI;
+ group=0;
+
+ }
+ else if((i_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT)){
+ FAPI_DBG("This is a X Bus invocation");
+ interface=FIR_CP_FABRIC_X0;
+ gcr_interface=CP_FABRIC_X0;
+ group=0;
+
+ }
+
+ else if((i_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT)){
+ FAPI_DBG("This is an A Bus invocation");
+ interface=FIR_CP_FABRIC_A0;
+ gcr_interface=CP_FABRIC_A0;
+ group=0;
+
+ }
+ else{
+ FAPI_ERR("Invalid io_clear_firs HWP invocation . Target doesnt belong to DMI/X/A instances");
+ FAPI_SET_HWP_ERROR(rc, IO_CLEAR_FIRS_INVALID_INVOCATION_RC);
+ return(rc);
+ }
+
+ rc=clear_fir_err_regs(i_target,gcr_interface,group);
+ if(rc){
+ return rc;
+ }
+ rc=clear_fir_reg(i_target,interface);
+ return(rc);
+}
+
+} //end extern C
diff --git a/src/usr/hwpf/hwp/bus_training/io_clear_firs.H b/src/usr/hwpf/hwp/bus_training/io_clear_firs.H new file mode 100644 index 000000000..d5bacf3a1 --- /dev/null +++ b/src/usr/hwpf/hwp/bus_training/io_clear_firs.H @@ -0,0 +1,176 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/bus_training/io_clear_firs.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: io_clear_firs.H,v 1.4 2013/02/20 09:40:22 jaswamin Exp $
+#ifndef IO_CLEAR_FIRS_H
+#define IO_CLEAR_FIRS_H
+
+#include <fapi.H>
+#include "gcr_funcs.H"
+
+using namespace fapi;
+
+/**
+ * io_clear_firs HWP func pointer typedef
+ *
+ */
+typedef fapi::ReturnCode (*io_clear_firs_FP_t)(const fapi::Target &target);
+
+// P8 chip interfaces
+const uint32_t FIR_INTERFACES=8;
+const uint32_t FIR_ISOLATION_REGS=42;
+
+enum fir_io_interface_t {FIR_CP_FABRIC_X0,
+ FIR_CP_FABRIC_X1,
+ FIR_CP_FABRIC_X2,
+ FIR_CP_FABRIC_X3,
+ FIR_CP_FABRIC_A0,
+ FIR_CP_IOMC0_P0,
+ FIR_CP_IOMC1_P0,
+ FIR_CEN_DMI };
+
+const char * const fir_interface_name[FIR_INTERFACES] = {"CP_FABRIC_X0",
+ "CP_FABRIC_X1",
+ "CP_FABRIC_X2",
+ "CP_FABRIC_X3",
+ "CP_FABRIC_A0",
+ "CP_IOMC0_P0",
+ "CP_IOMC1_P0",
+ "CEN_DMI" };
+
+// FIR register addresses for interfaces
+const uint32_t fir_clear_reg_addr[FIR_INTERFACES] = { 0x04011001,
+ 0x04011401,
+ 0x04011c01,
+ 0x04011801,
+ 0x08010c01,
+ 0x02011a01,
+ 0x02011e01,
+ 0x02010401 };
+
+const uint32_t fir_rw_reg_addr[FIR_INTERFACES]={0x04011000,
+ 0x04011400,
+ 0x04011c00,
+ 0x04011800,
+ 0x08010c00,
+ 0x02011a00,
+ 0x02011e00,
+ 0x02010400 }; + +const uint32_t fir_clear_mask_reg_addr[FIR_INTERFACES]={0x04011004, + 0x04011404, + 0x04011c04, + 0x04011804, + 0x08010c04, + 0x02011a04, + 0x02011e04, + 0x02010404 };
+enum fir_error_type{
+ RX_PARITY,
+ TX_PARITY,
+ GCR_HANG_ERROR,
+ BUS0_SPARE_DEPLOYED=9,
+ BUS0_MAX_SPARES_EXCEEDED=10,
+ BUS0_RECALIBRATION_ERROR=11,
+ BUS0_TOO_MANY_BUS_ERRORS=12,
+ BUS1_SPARE_DEPLOYED=17,
+ BUS1_MAX_SPARES_EXCEEDED=18,
+ BUS1_RECALIBRATION_ERROR=19,
+ BUS1_TOO_MANY_BUS_ERRORS=20,
+ BUS2_SPARE_DEPLOYED=25,
+ BUS2_MAX_SPARES_EXCEEDED=26,
+ BUS2_RECALIBRATION_ERROR=27,
+ BUS2_TOO_MANY_BUS_ERRORS=28,
+ BUS3_SPARE_DEPLOYED=33,
+ BUS3_MAX_SPARES_EXCEEDED=34,
+ BUS3_RECALIBRATION_ERROR=35,
+ BUS3_TOO_MANY_BUS_ERRORS=36,
+ BUS4_SPARE_DEPLOYED=41,
+ BUS4_MAX_SPARES_EXCEEDED=42,
+ BUS4_RECALIBRATION_ERROR=43,
+ BUS4_TOO_MANY_BUS_ERRORS=44,
+};
+const char * const fir1_reg[16] = {"RX_PG_FIR_ERR_PG_REGS",
+ "RX_PG_FIR_ERR_GCR_BUFF",
+ "RESERVED_FIR",
+ "RX_PG_FIR_ERR_GCRS_LD_SM",
+ "RX_PG_FIR_ERR_GCRS_UNLD_SM",
+ "RX_PG_FIR_ERR_GLB_INIT_SND_MSG_SM",
+ "RX_PG_FIR_ERR_MAIN_INIT_SM",
+ "RX_PG_FIR_ERR_WTM_SM",
+ "RX_PG_FIR_ERR_WTR_SM",
+ "RX_PG_FIR_ERR_WTL_SM",
+ "RX_PG_FIR_ERR_RPR_SM",
+ "RX_PG_FIR_ERR_EYEOPT_SM",
+ "RX_PG_FIR_ERR_DSM_SM",
+ "RX_PG_FIR_ERR_RXDSM_SM",
+ "RX_PG_CHAN_FAIL_RSVD",
+ "RX_PL_FIR_ERR"};
+
+
+const char * const fir2_reg[16] = {"RX_PG_FIR_ERR_DYN_RPR_SM",
+ "RX_PG_FIR_ERR_SLS_HNDSHK_SM",
+ "RX_PG_FIR_ERR_DYN_RPR_SND_MSG_SM",
+ "RX_PG_FIR_ERR_RECAL_SM",
+ "RX_PG_FIR_ERR_SLS_ENC_SND_MSG_SM",
+ "RX_PG_FIR_ERR_GLB_CAL_SND_MSG_SM",
+ "RX_PG_FIR_ERR_STAT_RPR_SND_MSG_SM",
+ "RESERVED_FIR",
+ "RESERVED_FIR",
+ "RESERVED_FIR",
+ "RESERVED_FIR",
+ "RESERVED_FIR",
+ "RESERVED_FIR",
+ "RESERVED_FIR",
+ "RESERVED_FIR",
+ "RESERVED_FIR"};
+
+extern "C"
+{
+
+/**
+ * io_clear_firs HWP
+ *
+ * target is any IO target P8 MCS,XBUS,Abus or centaur
+ *
+ *
+ *
+ *
+ */
+
+fapi::ReturnCode io_clear_firs(const fapi::Target &target);
+
+fapi::ReturnCode clear_fir_err_regs(const Target &target,io_interface_t chip_interface,uint32_t group);
+
+fapi::ReturnCode clear_fir_reg(const Target &target,fir_io_interface_t chip_interface); + +fapi::ReturnCode clear_fir_mask_reg(const Target &target,fir_io_interface_t chip_interface);
+
+fapi::ReturnCode read_fir_reg(const Target &target,fir_io_interface_t chip_interface,ecmdDataBufferBase &databuf_64bit); + +
+
+
+
+} // extern "C"
+#endif // CLEAR_IO_FIRS_H_
+
diff --git a/src/usr/hwpf/hwp/bus_training/io_errors.xml b/src/usr/hwpf/hwp/bus_training/io_errors.xml index ab074d0fa..7edc497e3 100644 --- a/src/usr/hwpf/hwp/bus_training/io_errors.xml +++ b/src/usr/hwpf/hwp/bus_training/io_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> <!-- --> <!-- p1 --> <!-- --> @@ -149,4 +149,80 @@ <rc>IO_DCCAL_ZCAL_M_LOW_RC</rc> <description>Margin Ratio is less than 50 percent</description> </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_CLEAR_FIRS_INVALID_INVOCATION_RC</rc> + <description>io clear firs hwp invoked with wrong pair of targets</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_FIR_LANE_RX_PARITY_ERROR_RC</rc> + <description>io lane level rx parity error set</description> + <ffdc>CHIP_TARGET</ffdc> + <ffdc>LANE_ID</ffdc> + <ffdc>RX_ERROR_REG</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_FIR_GROUP_RX_PARITY_ERROR_RC</rc> + <description>io group level rx parity error set</description> + <ffdc>CHIP_TARGET</ffdc> + <ffdc>RX_ERROR_REG</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_FIR_BUS_RX_PARITY_ERROR_RC</rc> + <description>io bus level rx parity error set</description> + <ffdc>CHIP_TARGET</ffdc> + <ffdc>RX_ERROR_REG</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_FIR_LANE_TX_PARITY_ERROR_RC</rc> + <description>io lane level tx parity error set</description> + <ffdc>CHIP_TARGET</ffdc> + <ffdc>LANE_ID</ffdc> + <ffdc>TX_ERROR_REG</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_FIR_GROUP_TX_PARITY_ERROR_RC</rc> + <description>io group level tx parity error set</description> + <ffdc>CHIP_TARGET</ffdc> + <ffdc>TX_ERROR_REG</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_FIR_SPARES_DEPLOYED_FIR_RC</rc> + <description>A spare has been deployed</description> + <ffdc>CHIP_TARGET</ffdc> + <ffdc>SPARE_ERROR_REG</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_FIR_MAX_SPARES_EXCEEDED_FIR_RC</rc> + <description>maximum spares possible to deploy exceeded</description> + <ffdc>CHIP_TARGET</ffdc> + <ffdc>SPARE_ERROR_REG</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_FIR_GCR_HANG_ERROR_RC</rc> + <description>gcr hang error detected</description> + <ffdc>CHIP_TARGET</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_FIR_RECALIBRATION_ERROR_RC</rc> + <description>recalibration or a repair error has been detected</description> + <ffdc>CHIP_TARGET</ffdc> + <ffdc>RECAL_ERROR_REG</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_FIR_TOO_MANY_BUS_ERROR_RC</rc> + <description>A bus has experienced too many random lane errors</description> + <ffdc>CHIP_TARGET</ffdc> + <ffdc>BUS_ERROR_REG</ffdc> + </hwpError> </hwpErrors> diff --git a/src/usr/hwpf/hwp/bus_training/io_funcs.C b/src/usr/hwpf/hwp/bus_training/io_funcs.C index 5131794f3..851ff4154 100644 --- a/src/usr/hwpf/hwp/bus_training/io_funcs.C +++ b/src/usr/hwpf/hwp/bus_training/io_funcs.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: io_funcs.C,v 1.15 2013/02/06 09:34:18 varkeykv Exp $ +// $Id: io_funcs.C,v 1.16 2013/02/07 10:07:28 varkeykv Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -53,6 +53,7 @@ extern "C" /* edi_training.C - functions of edi_training class */ /****************************************************************************************/ + //! Wrapper to Run W,D,E,R , F based on bus_status (selected on); ReturnCode edi_training::run_training(const Target& master_target, io_interface_t master_interface,uint32_t master_group, const Target& slave_target, io_interface_t slave_interface,uint32_t slave_group) { ReturnCode rc; @@ -242,7 +243,7 @@ ReturnCode edi_training::training_function_status(const Target& master_chip_ta { FAPI_ERR("io_run_training: the wiretest training state reported a fail \n"); FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_WIRETEST_RC); - fapiLogError(rc); + //fapiLogError(rc); wire_test_status = FAILED ; rx_wderf_failed[WIRE_TEST]=true; // Run First FAILED Data Capture for Wire Test for FAILED bus @@ -271,7 +272,7 @@ ReturnCode edi_training::training_function_status(const Target& master_chip_ta rx_wderf_failed[DESKEW]=true; FAPI_ERR("io_run_training : deskew training state reported a fail \n"); FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_DESKEW_RC); - fapiLogError(rc); + //fapiLogError(rc); desckew_status = FAILED ; break; } @@ -295,7 +296,7 @@ ReturnCode edi_training::training_function_status(const Target& master_chip_ta { FAPI_ERR("io_run_training : eye_opt_ training state reported a fail\n"); FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_EYE_OPT_RC); - fapiLogError(rc); + //fapiLogError(rc); rx_wderf_failed[EYE_OPT]=true; eye_opt_status = FAILED ; break; @@ -321,7 +322,7 @@ ReturnCode edi_training::training_function_status(const Target& master_chip_ta FAPI_DBG("io_run_training: static repair encountered an error \n"); rx_wderf_failed[REPAIR]=true; FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_REPAIR_RC); - fapiLogError(rc); + //fapiLogError(rc); repair_status = FAILED ; break; } @@ -348,7 +349,7 @@ ReturnCode edi_training::training_function_status(const Target& master_chip_ta FAPI_DBG("io_run_training: rx_func_mode_failed \n"); rx_wderf_failed[FUNCTIONAL]=true; FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_FUNC_MODE_RC); - fapiLogError(rc); + //fapiLogError(rc); functional_status = FAILED ; break; } @@ -391,31 +392,31 @@ ReturnCode edi_training::training_function_status(const Target& master_chip_ta { FAPI_ERR("io_run_training: wiretest timeout"); FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_WIRETEST_TIMEOUT_RC); - fapiLogError(rc); + //fapiLogError(rc); } else if (desckew_selected && desckew_status == RUNNING) { FAPI_ERR("io_run_training: deskew timeout"); FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_DESKEW_TIMEOUT_RC); - fapiLogError(rc); + // fapiLogError(rc); } else if (repair_selected && repair_status == RUNNING) { FAPI_ERR("io_run_training: repair timeout"); FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_REPAIR_TIMEOUT_RC); - fapiLogError(rc); + // fapiLogError(rc); } else if (eye_opt_selected && eye_opt_status == RUNNING) { FAPI_ERR("io_run_training: eyeopt timeout"); FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_EYE_OPT_TIMEOUT_RC); - fapiLogError(rc); + //fapiLogError(rc); } else { FAPI_ERR("io_run_training: func timeout"); FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FUNC_MODE_TIMEOUT_RC); - fapiLogError(rc); + //fapiLogError(rc); } break; } diff --git a/src/usr/hwpf/hwp/bus_training/io_funcs.H b/src/usr/hwpf/hwp/bus_training/io_funcs.H index 30f538ae0..7d6c78784 100644 --- a/src/usr/hwpf/hwp/bus_training/io_funcs.H +++ b/src/usr/hwpf/hwp/bus_training/io_funcs.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: io_funcs.H,v 1.13 2013/02/06 09:34:19 varkeykv Exp $ +// $Id: io_funcs.H,v 1.14 2013/02/12 06:25:32 varkeykv Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -76,7 +76,7 @@ public: bus_status repair_status; bus_status functional_status; //Updating max cycles to suit 100ms theoretical max timeout as per Mike Spear - static const uint32_t max_poll_cycles=100000; + static const uint32_t max_poll_cycles=100; static const uint32_t increment_poll_cycles=1; uint32_t endpoints_set; // How many end points have we accessed so far diff --git a/src/usr/hwpf/hwp/bus_training/makefile b/src/usr/hwpf/hwp/bus_training/makefile index 3bdb6b83d..16265745a 100644 --- a/src/usr/hwpf/hwp/bus_training/makefile +++ b/src/usr/hwpf/hwp/bus_training/makefile @@ -38,6 +38,7 @@ OBJS = gcr_funcs.o io_funcs.o io_run_training.o pbusLinkSvc.o proc_fab_smp.o \ io_dccal.o \ io_power_down_lanes.o \ io_read_erepair.o \ + io_clear_firs.o \ ## NOTE: add a new directory onto the vpaths when you add a new HWP diff --git a/src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.C b/src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.C index b5c1c12cd..5b7ff7c78 100644 --- a/src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.C +++ b/src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: cen_switch_rec_attn.C,v 1.2 2012/12/13 22:54:32 mfred Exp $ +// $Id: cen_switch_rec_attn.C,v 1.3 2013/01/18 17:18:31 mfred Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_switch_rec_attn.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -28,7 +28,7 @@ // *! *** IBM Confidential *** //------------------------------------------------------------------------------ // *! TITLE : cen_switch_rec_attn -// *! DESCRIPTION : The purpose of this procedure is to route Centaur recoverable attentions to the FSP instead of to the P8 host. +// *! DESCRIPTION : The purpose of this procedure is to route Centaur recoverable attns and special attns to the FSP. // *! OWNER NAME : Mark Fredrickson Email: mfred@us.ibm.com // #! ADDITIONAL COMMENTS : See inline comments below. // @@ -42,6 +42,7 @@ // Constants const uint8_t RECOV_ERR_IPOLL_MASK_BIT = 5; +const uint8_t SPEC_ATTN_IPOLL_MASK_BIT = 6; extern "C" { @@ -61,11 +62,12 @@ fapi::ReturnCode cen_switch_rec_attn(const fapi::Target & i_target) { // Clear bit 5 in the IPOLL Mask Register 0x01020013 to unmask the recoverable errors going to FSI and DMI. + // Clear bit 6 in the IPOLL Mask Register 0x01020013 to unmask the special attn interrupts going to FSI and DMI. // Note: In Centaur the outputs of the ITR Macro go to both the FSI and to the DMI. // The "HostBridge" mentioned in the P8 Pervasive Workbook is NOT the DMI path. // In Centaur the IPOLL Mask bits 0-3 to not do anything. // In Centaur the IPOLL Mask bits 4-7 controll signals going to BOTH FSI and DMI. - FAPI_DBG("Writing IPOLL Mask Register 0x01020013 to clear bit 5 (to unmask recoverable errors) ..."); + FAPI_DBG("Writing IPOLL Mask Register 0x01020013 to clear bit 5 and 6 (to unmask recov errs and spc attns) ..."); rc = fapiGetScom( i_target, TP_IPOLL_MSK_0x01020013, scom_data); if ( rc ) { @@ -73,6 +75,7 @@ fapi::ReturnCode cen_switch_rec_attn(const fapi::Target & i_target) break; } rc_ecmd |= scom_data.clearBit(RECOV_ERR_IPOLL_MASK_BIT); + rc_ecmd |= scom_data.clearBit(SPEC_ATTN_IPOLL_MASK_BIT); if (rc_ecmd) { FAPI_ERR("Error 0x%x setting up ecmd data buffer to write Interrupt IPOLL Mask Register.", rc_ecmd); @@ -103,6 +106,9 @@ fapi::ReturnCode cen_switch_rec_attn(const fapi::Target & i_target) This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: cen_switch_rec_attn.C,v $ +Revision 1.3 2013/01/18 17:18:31 mfred +Clear mask to allow special attentions to go to FSP, along with recoverables. + Revision 1.2 2012/12/13 22:54:32 mfred Update to remove unneeded commands and unmask recoverable path to FSI. diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_memdiag/mss_maint_cmds.C b/src/usr/hwpf/hwp/dram_initialization/mss_memdiag/mss_maint_cmds.C index 7246c796f..8950a11e9 100644 --- a/src/usr/hwpf/hwp/dram_initialization/mss_memdiag/mss_maint_cmds.C +++ b/src/usr/hwpf/hwp/dram_initialization/mss_memdiag/mss_maint_cmds.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_maint_cmds.C,v 1.18 2013/01/15 23:05:48 gollub Exp $ +// $Id: mss_maint_cmds.C,v 1.19 2013/01/31 22:27:22 gollub Exp $ //------------------------------------------------------------------------------ // Don't forget to create CVS comments when you check in your changes! //------------------------------------------------------------------------------ @@ -57,6 +57,13 @@ // 1.17 | 12/19/12 | gollub | Added UE isolation // 1.18 | 01/15/13 | gollub | Added check for valid dimm before calling // | | | dimmGetBadDqBitmap +// 1.19 | 01/31/13 | gollub | Updated MDI bits for random pattern so +// | | | don't get SUEs +// | | | Added mss_check_steering +// | | | Added mss_do_steering +// | | | Added mss_stopCmd +// | | | Removed cleanupCmd for cmds that didn't use it + //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ @@ -594,9 +601,9 @@ static const uint8_t mss_65thByte[MSS_MAX_PATTERNS][4]={ // PATTERN_8: random seed {0x20, // 1st 64B of cachline: tag0=0, tag1=1, MDI=0 - 0x70, // 1st 64B of cachline: tag2=1, tag3=1, MDI=1 + 0x60, // 1st 64B of cachline: tag2=1, tag3=1, MDI=0 0x30, // 2nd 64B of cachline: tag0=0, tag1=1, MDI=1 - 0x60}}; // 2nd 64B of cachline: tag2=1, tag3=1, MDI=0 + 0x70}}; // 2nd 64B of cachline: tag2=1, tag3=1, MDI=1 // TODO: Update with actual patterns from Luis Lastras when they are ready static const uint32_t mss_ECC[MSS_MAX_PATTERNS][4]={ @@ -682,6 +689,82 @@ mss_MaintCmd::mss_MaintCmd(const fapi::Target & i_target, iv_cmdType(i_cmdType){} +//--------------------------------------------------------- +// mss_stopCmd +//--------------------------------------------------------- +fapi::ReturnCode mss_MaintCmd::stopCmd() +{ + fapi::ReturnCode l_rc; + uint32_t l_ecmd_rc = 0; + ecmdDataBufferBase l_mbmsrq(64); + ecmdDataBufferBase l_mbmccq(64); + ecmdDataBufferBase l_mbmacaq(64); + + FAPI_INF("ENTER mss_MaintCmd::stopCmd()"); + + // Read MBMSRQ + l_rc = fapiGetScom(iv_target, MBA01_MBMSRQ_0x0301060C, l_mbmsrq); + if(l_rc) return l_rc; + + // If MBMSRQ[0], maint_cmd_in_progress, stop the cmd + if (l_mbmsrq.isBitSet(0)) + { + // Read MBMCCQ + l_rc = fapiGetScom(iv_target, MBA01_MBMCCQ_0x0301060B, l_mbmccq); + if(l_rc) return l_rc; + + // Set bit 1 to force the cmd to stop + l_ecmd_rc |= l_mbmccq.setBit(1); + if(l_ecmd_rc) + { + l_rc.setEcmdError(l_ecmd_rc); + return l_rc; + } + + // Write MBMCCQ + l_rc = fapiPutScom(iv_target, MBA01_MBMCCQ_0x0301060B, l_mbmccq); + if(l_rc) return l_rc; + + // Read MBMSRQ + l_rc = fapiGetScom(iv_target, MBA01_MBMSRQ_0x0301060C, l_mbmsrq); + if(l_rc) return l_rc; + + // If cmd didn't stop as expected + if (l_mbmsrq.isBitSet(0)) + { + FAPI_ERR("MBMSRQ[0] = 1, unsuccessful forced maint cmd stop."); + + // Calling out MBA target high, deconfig, gard + const fapi::Target & MBA = iv_target; + // FFDC: Capture register we used to stop cmd + ecmdDataBufferBase & MBMCC = l_mbmccq; + // FFDC: Capture register we are checking + ecmdDataBufferBase & MBMSR = l_mbmsrq; + // FFDC: Capture command type we are trying to run + const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; + + // Create new log + FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_UNSUCCESSFUL_FORCED_MAINT_CMD_STOP); + return l_rc; + } + } + + // Store the address we stopped at in iv_startAddr + l_rc = fapiGetScom(iv_target, MBA01_MBMACAQ_0x0301060D, iv_startAddr); + if(l_rc) return l_rc; + + // Only 0-36 are valid address bits so clear the rest, 37-63 + l_ecmd_rc |= iv_startAddr.clearBit(37,27); + if(l_ecmd_rc) + { + l_rc.setEcmdError(l_ecmd_rc); + return l_rc; + } + + + FAPI_INF("EXIT mss_MaintCmd::stopCmd()"); + return l_rc; +} //--------------------------------------------------------- @@ -692,7 +775,7 @@ fapi::ReturnCode mss_MaintCmd::cleanupCmd() fapi::ReturnCode l_rc; FAPI_INF("ENTER mss_MaintCmd::cleanupCmd()"); - // Clear maintenance command complete attention, scrub stats, etc... + FAPI_INF("EXIT mss_MaintCmd::cleanupCmd()"); return l_rc; @@ -1278,13 +1361,13 @@ fapi::ReturnCode mss_MaintCmd::collectFFDC() FAPI_DBG("MBMACAQ = 0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); // Print out error status bits from MBMACAQ - if (l_data.isBitSet(40)) FAPI_ERR("MBMACAQ error status: 40:NCE"); - if (l_data.isBitSet(41)) FAPI_ERR("MBMACAQ error status: 41:SCE"); - if (l_data.isBitSet(42)) FAPI_ERR("MBMACAQ error status: 42:MCE"); - if (l_data.isBitSet(43)) FAPI_ERR("MBMACAQ error status: 43:RCE"); - if (l_data.isBitSet(44)) FAPI_ERR("MBMACAQ error status: 44:MPE"); - if (l_data.isBitSet(45)) FAPI_ERR("MBMACAQ error status: 45:UE"); - if (l_data.isBitSet(46)) FAPI_ERR("MBMACAQ error status: 46:SUE"); + if (l_data.isBitSet(40)) FAPI_DBG("MBMACAQ error status: 40:NCE"); + if (l_data.isBitSet(41)) FAPI_DBG("MBMACAQ error status: 41:SCE"); + if (l_data.isBitSet(42)) FAPI_DBG("MBMACAQ error status: 42:MCE"); + if (l_data.isBitSet(43)) FAPI_DBG("MBMACAQ error status: 43:RCE"); + if (l_data.isBitSet(44)) FAPI_DBG("MBMACAQ error status: 44:MPE"); + if (l_data.isBitSet(45)) FAPI_DBG("MBMACAQ error status: 45:UE"); + if (l_data.isBitSet(46)) FAPI_DBG("MBMACAQ error status: 46:SUE"); l_rc = fapiGetScom(iv_target, MBA01_MBMEAQ_0x0301060E, l_data); if(l_rc) return l_rc; @@ -1319,20 +1402,20 @@ fapi::ReturnCode mss_MaintCmd::collectFFDC() FAPI_DBG("MBECCFIR = 0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); // Print out maint ECC FIR bits from MBECCFIR - if (l_data.isBitSet(20)) FAPI_ERR("20:Maint MPE, rank0"); - if (l_data.isBitSet(21)) FAPI_ERR("21:Maint MPE, rank1"); - if (l_data.isBitSet(22)) FAPI_ERR("22:Maint MPE, rank2"); - if (l_data.isBitSet(23)) FAPI_ERR("23:Maint MPE, rank3"); - if (l_data.isBitSet(24)) FAPI_ERR("24:Maint MPE, rank4"); - if (l_data.isBitSet(25)) FAPI_ERR("25:Maint MPE, rank5"); - if (l_data.isBitSet(26)) FAPI_ERR("26:Maint MPE, rank6"); - if (l_data.isBitSet(27)) FAPI_ERR("27:Maint MPE, rank7"); - if (l_data.isBitSet(36)) FAPI_ERR("36: Maint NCE"); - if (l_data.isBitSet(37)) FAPI_ERR("37: Maint SCE"); - if (l_data.isBitSet(38)) FAPI_ERR("38: Maint MCE"); - if (l_data.isBitSet(39)) FAPI_ERR("39: Maint RCE"); - if (l_data.isBitSet(40)) FAPI_ERR("40: Maint SUE"); - if (l_data.isBitSet(41)) FAPI_ERR("41: Maint UE"); + if (l_data.isBitSet(20)) FAPI_DBG("20:Maint MPE, rank0"); + if (l_data.isBitSet(21)) FAPI_DBG("21:Maint MPE, rank1"); + if (l_data.isBitSet(22)) FAPI_DBG("22:Maint MPE, rank2"); + if (l_data.isBitSet(23)) FAPI_DBG("23:Maint MPE, rank3"); + if (l_data.isBitSet(24)) FAPI_DBG("24:Maint MPE, rank4"); + if (l_data.isBitSet(25)) FAPI_DBG("25:Maint MPE, rank5"); + if (l_data.isBitSet(26)) FAPI_DBG("26:Maint MPE, rank6"); + if (l_data.isBitSet(27)) FAPI_DBG("27:Maint MPE, rank7"); + if (l_data.isBitSet(36)) FAPI_DBG("36: Maint NCE"); + if (l_data.isBitSet(37)) FAPI_DBG("37: Maint SCE"); + if (l_data.isBitSet(38)) FAPI_DBG("38: Maint MCE"); + if (l_data.isBitSet(39)) FAPI_DBG("39: Maint RCE"); + if (l_data.isBitSet(40)) FAPI_DBG("40: Maint SUE"); + if (l_data.isBitSet(41)) FAPI_DBG("41: Maint UE"); FAPI_DBG("Markstore"); for ( uint8_t i = 0; i < MSS_MAX_RANKS; i++ ) @@ -1355,9 +1438,8 @@ fapi::ReturnCode mss_MaintCmd::collectFFDC() FAPI_DBG("Steer MUXES"); for ( uint8_t i = 0; i < MSS_MAX_RANKS; i++ ) { - l_rc = mss_get_steer_mux(iv_target, + l_rc = mss_check_steering(iv_target, i, - mss_SteerMux::READ_MUX, l_dramSparePort0Symbol, l_dramSparePort1Symbol, l_eccSpareSymbol); @@ -1763,22 +1845,6 @@ fapi::ReturnCode mss_MaintCmd::loadSpeed(TimeBaseSpeed i_speed) } -//--------------------------------------------------------- -// mss_setupAndExecuteCmd -//--------------------------------------------------------- -fapi::ReturnCode mss_MaintCmd::setupAndExecuteCmd() -{ - - FAPI_INF("ENTER mss_MaintCmd::setupAndExecuteCmd()"); - fapi::ReturnCode l_rc; - FAPI_INF("EXIT mss_MaintCmd::setupAndExecuteCmd()"); - - return l_rc; -} - - - - @@ -1885,42 +1951,6 @@ fapi::ReturnCode mss_SuperFastInit::setupAndExecuteCmd() -fapi::ReturnCode mss_SuperFastInit::stopCmd() -{ - - FAPI_INF("ENTER mss_SuperFastInit::stopCmd()"); - - fapi::ReturnCode l_rc; - - // Stop the maintenace command if it is running. - - // Update the iv_startAddr to the addr the maintenenance command - // stopped on. For testing purposes we will just set an abitrary number. - //iv_startAddr = 0x0000dead0000beefll; - //printf( "addr stopped on: 0x%016llx\n", iv_startAddr ); - - FAPI_INF("EXIT mss_SuperFastInit::stopCmd()"); - - return l_rc; -} - -fapi::ReturnCode mss_SuperFastInit::cleanupCmd() -{ - - FAPI_INF("ENTER mss_SuperFastInit::cleanupCmd()"); - - fapi::ReturnCode l_rc; - - // Clear maintenance command complete attention, scrub stats, etc... - - // Restore the saved data. - - FAPI_INF("EXIT mss_SuperFastInit::cleanupCmd()"); - - return l_rc; -} - - //------------------------------------------------------------------------------ // mss_SuperFastRandomInit //------------------------------------------------------------------------------ @@ -2029,27 +2059,6 @@ fapi::ReturnCode mss_SuperFastRandomInit::setupAndExecuteCmd() } - - -fapi::ReturnCode mss_SuperFastRandomInit::stopCmd() -{ - - FAPI_INF("ENTER mss_SuperFastRandomInit::stopCmd()"); - - fapi::ReturnCode l_rc; - - // Stop the maintenace command if it is running. - - // Update the iv_startAddr to the addr the maintenenance command - // stopped on. For testing purposes we will just set an abitrary number. - //iv_startAddr = 0x0000dead0000beefll; - //printf( "addr stopped on: 0x%016llx\n", iv_startAddr ); - - FAPI_INF("EXIT mss_SuperFastRandomInit::stopCmd()"); - - return l_rc; -} - fapi::ReturnCode mss_SuperFastRandomInit::cleanupCmd() { @@ -2251,26 +2260,6 @@ fapi::ReturnCode mss_SuperFastRead::ueTrappingSetup() } - -fapi::ReturnCode mss_SuperFastRead::stopCmd() -{ - - FAPI_INF("ENTER mss_SuperFastRead::stopCmd()"); - - fapi::ReturnCode l_rc; - - // Stop the maintenace command if it is running. - - // Update the iv_startAddr to the addr the maintenenance command - // stopped on. For testing purposes we will just set an abitrary number. - //iv_startAddr = 0x0000dead0000beefll; - //printf( "addr stopped on: 0x%016llx\n", iv_startAddr ); - - FAPI_INF("EXIT mss_SuperFastRead::stopCmd()"); - - return l_rc; -} - fapi::ReturnCode mss_SuperFastRead::cleanupCmd() { @@ -2403,18 +2392,6 @@ fapi::ReturnCode mss_AtomicInject::setupAndExecuteCmd() } -fapi::ReturnCode mss_AtomicInject::stopCmd() -{ - - FAPI_INF("ENTER mss_AtomicInject::stopCmd()"); - fapi::ReturnCode l_rc; - FAPI_INF("EXIT mss_AtomicInject::stopCmd()"); - - return l_rc; -} - - - //------------------------------------------------------------------------------ // Display @@ -2545,17 +2522,6 @@ fapi::ReturnCode mss_Display::setupAndExecuteCmd() } -fapi::ReturnCode mss_Display::stopCmd() -{ - - FAPI_INF("ENTER mss_Display::stopCmd()"); - fapi::ReturnCode l_rc; - FAPI_INF("EXIT mss_Display::stopCmd()"); - - return l_rc; -} - - //------------------------------------------------------------------------------ // Increment MBMACA Address @@ -2624,17 +2590,6 @@ fapi::ReturnCode mss_IncrementAddress::setupAndExecuteCmd() } -fapi::ReturnCode mss_IncrementAddress::stopCmd() -{ - - FAPI_INF("ENTER mss_IncrementAddress::stopCmd()"); - fapi::ReturnCode l_rc; - FAPI_INF("EXIT mss_IncrementAddress::stopCmd()"); - - return l_rc; -} - - //------------------------------------------------------------------------------ // mss_TimeBaseScrub //------------------------------------------------------------------------------ @@ -2737,42 +2692,6 @@ fapi::ReturnCode mss_TimeBaseScrub::setupAndExecuteCmd() } -fapi::ReturnCode mss_TimeBaseScrub::stopCmd() -{ - - FAPI_INF("ENTER mss_TimeBaseScrub::stopCmd()"); - - fapi::ReturnCode l_rc; - - // Stop the maintenace command if it is running. - - // Update the iv_startAddr to the addr the maintenenance command - // stopped on. For testing purposes we will just set an abitrary number. - //iv_startAddr = 0x0000dead0000beefll; - //printf( "addr stopped on: 0x%016llx\n", iv_startAddr ); - - FAPI_INF("EXIT mss_TimeBaseScrub::stopCmd()"); - - return l_rc; -} - -fapi::ReturnCode mss_TimeBaseScrub::cleanupCmd() -{ - - FAPI_INF("ENTER mss_TimeBaseScrub::cleanupCmd()"); - - fapi::ReturnCode l_rc; - - // Clear maintenance command complete attention, scrub stats, etc... - - // Restore the saved data. - //printf( "Saved data: 0x%08x\n", getSavedData() ); - - FAPI_INF("EXIT mss_TimeBaseScrub::cleanupCmd()"); - - return l_rc; -} - //------------------------------------------------------------------------------ // mss_TimeBaseSteerCleanup @@ -2864,41 +2783,6 @@ fapi::ReturnCode mss_TimeBaseSteerCleanup::setupAndExecuteCmd() } -fapi::ReturnCode mss_TimeBaseSteerCleanup::stopCmd() -{ - - FAPI_INF("ENTER mss_TimeBaseSteerCleanup::stopCmd()"); - - fapi::ReturnCode l_rc; - - // Stop the maintenace command if it is running. - - // Update the iv_startAddr to the addr the maintenenance command - // stopped on. For testing purposes we will just set an abitrary number. - //iv_startAddr = 0x0000dead0000beefll; - //printf( "addr stopped on: 0x%016llx\n", iv_startAddr ); - - FAPI_INF("EXIT mss_TimeBaseSteerCleanup::stopCmd()"); - - return l_rc; -} - -fapi::ReturnCode mss_TimeBaseSteerCleanup::cleanupCmd() -{ - - FAPI_INF("ENTER mss_TimeBaseSteerCleanup::cleanupCmd()"); - - fapi::ReturnCode l_rc; - - // Clear maintenance command complete attention, scrub stats, etc... - - // Restore the saved data. - //printf( "Saved data: 0x%08x\n", getSavedData() ); - - FAPI_INF("EXIT mss_TimeBaseSteerCleanup::cleanupCmd()"); - - return l_rc; -} //------------------------------------------------------------------------------ @@ -3196,10 +3080,24 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, { FAPI_INF("Get address range for master rank = %d\n", i_rank ); + // Check for i_rank out of range + if (i_rank>=8) + { + FAPI_ERR("i_rank input to mss_get_address_range out of range"); + // TODO: Calling out FW high + // FFDC: MBA target + const fapi::Target & MBA = i_target; + // FFDC: Capture i_rank; + uint8_t RANK = i_rank; + + // Create new log. + FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_GET_ADDRESS_RANGE_BAD_INPUT); + return l_rc; + } + // NOTE: If this rank is not valid, we should see MBAFIR[1]: invalid // maint address, when cmd started - // DEBUG - run on last few address of the rank /* // Set end address to end of rank @@ -3337,6 +3235,21 @@ fapi::ReturnCode mss_get_mark_store( const fapi::Target & i_target, return l_rc; } + // Check for i_rank out of range + if (i_rank>=8) + { + FAPI_ERR("i_rank input to mss_get_mark_store out of range"); + // TODO: Calling out FW high + // FFDC: MBA target + const fapi::Target & MBA = i_target; + // FFDC: Capture i_rank; + uint8_t RANK = i_rank; + + // Create new log. + FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_GET_MARK_STORE_BAD_INPUT); + return l_rc; + } + // Read markstore register for the given rank l_rc = fapiGetScom(l_targetCentaur, mss_markStoreRegs[i_rank][l_mbaPosition], l_markstore); if(l_rc) return l_rc; @@ -3524,6 +3437,21 @@ fapi::ReturnCode mss_put_mark_store( const fapi::Target & i_target, FAPI_ERR("Error getting DRAM width"); return l_rc; } + + // Check for i_rank out of range + if (i_rank>=8) + { + FAPI_ERR("i_rank input to mss_put_mark_store out of range"); + // TODO: Calling out FW high + // FFDC: MBA target + const fapi::Target & MBA = i_target; + // FFDC: Capture i_rank; + uint8_t RANK = i_rank; + + // Create new log. + FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_PUT_MARK_STORE_BAD_INPUT); + return l_rc; + } // Get l_symbolMarkGalois if (i_symbolMark == MSS_INVALID_SYMBOL) // No symbol mark @@ -3694,6 +3622,7 @@ fapi::ReturnCode mss_put_mark_store( const fapi::Target & i_target, + //------------------------------------------------------------------------------ // mss_get_steer_mux //------------------------------------------------------------------------------ @@ -3746,6 +3675,26 @@ fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target, return l_rc; } + + // Check for i_rank or i_muxType out of range + if ((i_rank>=8) || + !((i_muxType==mss_SteerMux::READ_MUX) || (i_muxType==mss_SteerMux::WRITE_MUX))) + { + FAPI_ERR("i_rank or i_muxType input to mss_get_steer_mux out of range"); + // TODO: Calling out FW high + // FFDC: MBA target + const fapi::Target & MBA = i_target; + // FFDC: Capture i_rank; + uint8_t RANK = i_rank; + // FFDC: Capure i_muxType + uint8_t MUX_TYPE = i_muxType; + + // Create new log. + FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_GET_STEER_MUX_BAD_INPUT); + return l_rc; + } + + // Read steer mux register for the given rank and mux type (read or write). if (i_muxType == mss_SteerMux::READ_MUX) { @@ -3885,6 +3834,8 @@ fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target, + + //------------------------------------------------------------------------------ // mss_put_steer_mux //------------------------------------------------------------------------------ @@ -3938,6 +3889,31 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, } + // Check for i_rank or i_muxType or i_steerType or i_symbol out of range + if ((i_rank>=8) || + !((i_muxType==mss_SteerMux::READ_MUX) || (i_muxType==mss_SteerMux::WRITE_MUX)) || + !((i_steerType == mss_SteerMux::DRAM_SPARE_PORT0) || (i_steerType == mss_SteerMux::DRAM_SPARE_PORT1) || (i_steerType == mss_SteerMux::ECC_SPARE)) || + (i_symbol >= 72)) + { + FAPI_ERR("i_rank or i_muxType or i_steerType or i_symbol input to mss_get_steer_mux out of range"); + // TODO: Calling out FW high + // FFDC: MBA target + const fapi::Target & MBA = i_target; + // FFDC: Capture i_rank; + uint8_t RANK = i_rank; + // FFDC: Capure i_muxType + uint8_t MUX_TYPE = i_muxType; + // FFDC: Capure i_steerType + uint8_t STEER_TYPE = i_steerType; + // FFDC: Capure i_symbol + uint8_t SYMBOL = i_symbol; + + // Create new log. + FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_PUT_STEER_MUX_BAD_INPUT); + return l_rc; + } + + // Read steer mux register for the given rank and mux type (read or write). if (i_muxType == mss_SteerMux::READ_MUX) { @@ -3981,9 +3957,9 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, uint8_t RANK = i_rank; // FFDC: Capure i_muxType uint8_t MUX_TYPE = i_muxType; - // FFDC: Capure i_muxType + // FFDC: Capure i_steerType uint8_t STEER_TYPE = i_steerType; - // FFDC: Capure i_muxType + // FFDC: Capure i_symbol uint8_t SYMBOL = i_symbol; // Create new log. @@ -4017,9 +3993,9 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, uint8_t RANK = i_rank; // FFDC: Capure i_muxType uint8_t MUX_TYPE = i_muxType; - // FFDC: Capure i_muxType + // FFDC: Capure i_steerType uint8_t STEER_TYPE = i_steerType; - // FFDC: Capure i_muxType + // FFDC: Capure i_symbol uint8_t SYMBOL = i_symbol; // Create new log. @@ -4060,9 +4036,9 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, uint8_t RANK = i_rank; // FFDC: Capure i_muxType uint8_t MUX_TYPE = i_muxType; - // FFDC: Capure i_muxType + // FFDC: Capure i_steerType uint8_t STEER_TYPE = i_steerType; - // FFDC: Capure i_muxType + // FFDC: Capure i_symbol uint8_t SYMBOL = i_symbol; // Create new log. @@ -4096,9 +4072,9 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, uint8_t RANK = i_rank; // FFDC: Capure i_muxType uint8_t MUX_TYPE = i_muxType; - // FFDC: Capure i_muxType + // FFDC: Capure i_steerType uint8_t STEER_TYPE = i_steerType; - // FFDC: Capure i_muxType + // FFDC: Capure i_symbol uint8_t SYMBOL = i_symbol; // Create new log. @@ -4140,9 +4116,9 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, uint8_t RANK = i_rank; // FFDC: Capure i_muxType uint8_t MUX_TYPE = i_muxType; - // FFDC: Capure i_muxType + // FFDC: Capure i_steerType uint8_t STEER_TYPE = i_steerType; - // FFDC: Capure i_muxType + // FFDC: Capure i_symbol uint8_t SYMBOL = i_symbol; // Create new log. @@ -4163,9 +4139,9 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, uint8_t RANK = i_rank; // FFDC: Capure i_muxType uint8_t MUX_TYPE = i_muxType; - // FFDC: Capure i_muxType + // FFDC: Capure i_steerType uint8_t STEER_TYPE = i_steerType; - // FFDC: Capure i_muxType + // FFDC: Capure i_symbol uint8_t SYMBOL = i_symbol; // Create new log. @@ -4205,6 +4181,141 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, } +//------------------------------------------------------------------------------ +// mss_check_steering +//------------------------------------------------------------------------------ + +fapi::ReturnCode mss_check_steering(const fapi::Target & i_target, + uint8_t i_rank, + uint8_t & o_dramSparePort0Symbol, + uint8_t & o_dramSparePort1Symbol, + uint8_t & o_eccSpareSymbol ) +{ + + // Get the read steer mux, with the assuption + // that the write mux will be the same. + return mss_get_steer_mux(i_target, + i_rank, + mss_SteerMux::READ_MUX, + o_dramSparePort0Symbol, + o_dramSparePort1Symbol, + o_eccSpareSymbol); +} + + +//------------------------------------------------------------------------------ +// mss_do_steering +//------------------------------------------------------------------------------ + +fapi::ReturnCode mss_do_steering(const fapi::Target & i_target, + uint8_t i_rank, + uint8_t i_symbol, + bool i_x4EccSpare) +{ + FAPI_INF("ENTER mss_do_steering()"); + + + fapi::ReturnCode l_rc; + uint8_t l_steerType = 0; // 0 = DRAM_SPARE_PORT0, Spare DRAM on port0 + // 1 = DRAM_SPARE_PORT1, Spare DRAM on port1 + // 2 = ECC_SPARE, ECC spare (used in x4 mode only) + + + // Check for i_rank or i_symbol out of range + if ((i_rank>=8) || (i_symbol>=72)) + { + FAPI_ERR("i_rank or i_symbol input to mss_do_steer out of range"); + // TODO: Calling out FW high + // FFDC: MBA target + const fapi::Target & MBA = i_target; + // FFDC: Capture i_rank; + uint8_t RANK = i_rank; + // FFDC: Capture i_symbol; + uint8_t SYMBOL = i_symbol; + // FFDC: Capture i_x4EccSpare + uint8_t X4ECCSPARE = i_x4EccSpare; + + // Create new log. + FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_DO_STEER_INPUT_OUT_OF_RANGE); + return l_rc; + } + + //------------------------------------------------------ + // Determine l_steerType + //------------------------------------------------------ + if (i_x4EccSpare) + { + l_steerType = mss_SteerMux::ECC_SPARE; + } + else + { + // Symbols 71-40, 7-4 come from port0 + if (((i_symbol<=71)&&(i_symbol>=40)) || ((i_symbol<=7)&&(i_symbol>=4))) + { + l_steerType = mss_SteerMux::DRAM_SPARE_PORT0; + } + // Symbols 39-8, 3-0 come from port1 + else + { + l_steerType = mss_SteerMux::DRAM_SPARE_PORT1; + } + } + + //------------------------------------------------------ + // Update write mux + //------------------------------------------------------ + l_rc = mss_put_steer_mux( + + i_target, // MBA + i_rank, // Master rank: 0-7 + mss_SteerMux::WRITE_MUX,// write mux + l_steerType, // DRAM_SPARE_PORT0/DRAM_SPARE_PORT1/ECC_SPARE + i_symbol); // First symbol index of DRAM to steer around + + if (l_rc) + { + FAPI_ERR("Error updating write mux"); + return l_rc; + } + + //------------------------------------------------------ + // Wait for a periodic cal. + //------------------------------------------------------ + + // 250 ms delay for HW mode + const uint64_t HW_MODE_DELAY = 250000000; + + // 200000 sim cycle delay for SIM mode + const uint64_t SIM_MODE_DELAY = 200000; + + fapiDelay(HW_MODE_DELAY, SIM_MODE_DELAY); + + // TODO: Could be precise and find cal interval from: + // ATTR_EFF_ZQCAL_INTERVAL (in clocks... so still have to know freq) + // ATTR_EFF_MEMCAL_INTERVAL (in clocks... so still have to know freq) + + //------------------------------------------------------ + // Update read mux + //------------------------------------------------------ + l_rc = mss_put_steer_mux( + + i_target, // MBA + i_rank, // Master rank: 0-7 + mss_SteerMux::READ_MUX, // read mux + l_steerType, // DRAM_SPARE_PORT0/DRAM_SPARE_PORT1/ECC_SPARE + i_symbol); // First symbol index of DRAM to steer around + + if (l_rc) + { + FAPI_ERR("Error updating read mux"); + return l_rc; + + } + + FAPI_INF("EXIT mss_do_steering()"); + + return l_rc; +} //------------------------------------------------------------------------------ // mss_restore_DRAM_repairs @@ -4421,7 +4532,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, // If spare is bad but not used, not valid to try repair if ( l_spare_exists && (l_byte==9) && (l_bad_dq_pair_count > 0) && !l_spare_used) { - FAPI_INF("port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, Bad unused spare - no valid repair", + FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, Bad unused spare - no valid repair", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); break; @@ -4486,7 +4597,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, o_repairs_exceeded |= l_repairs_exceeded_translation[1][l_dimm]; } - FAPI_INF("port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, symbols %d-%d, FIXED CHIP WITH X8 STEER", + FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, symbols %d-%d, FIXED CHIP WITH X8 STEER", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte], 8*l_byte, 8*l_byte+7,l_bad_symbol, l_bad_symbol+3 ); @@ -4515,12 +4626,12 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, // Special case: - // If this is a bad spare byte we are analying + // If this is a bad spare byte we are analyzing // the chip mark goes on the byte being steered if (l_byte==9) { l_chip_mark = mss_centaurDQ_to_symbol(8*l_byte_being_steered,l_port) - 3; - FAPI_INF("Bad spare so chip mark goes on l_byte_being_steered = %d", l_byte_being_steered); + FAPI_ERR("WARNING: Bad spare so chip mark goes on l_byte_being_steered = %d", l_byte_being_steered); } else @@ -4556,7 +4667,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, o_repairs_exceeded |= l_repairs_exceeded_translation[1][l_dimm]; } - FAPI_INF("port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, symbols %d-%d, FIXED CHIP WITH X8 CHIP MARK", + FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, symbols %d-%d, FIXED CHIP WITH X8 CHIP MARK", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte], 8*l_byte, 8*l_byte+7,l_chip_mark, l_chip_mark+3 ); } @@ -4574,7 +4685,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, o_repairs_exceeded |= l_repairs_exceeded_translation[0][l_dimm]; } - FAPI_INF("port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, REPAIRS EXCEEDED", + FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, REPAIRS EXCEEDED", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte], 8*l_byte, 8*l_byte+7); @@ -4615,7 +4726,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, if (l_byte==9) { l_symbol_mark = mss_centaurDQ_to_symbol(8*l_byte_being_steered + 2*l_bad_dq_pair_index,l_port); - FAPI_INF("Bad spare so symbol mark goes on l_byte_being_steered = %d", l_byte_being_steered); + FAPI_ERR("WARNING: Bad spare so symbol mark goes on l_byte_being_steered = %d", l_byte_being_steered); } else @@ -4652,7 +4763,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, o_repairs_exceeded |= l_repairs_exceeded_translation[1][l_dimm]; } - FAPI_INF("port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, symbol %d, FIXED SYMBOL WITH X2 SYMBOL MARK", + FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, symbol %d, FIXED SYMBOL WITH X2 SYMBOL MARK", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte], 8*l_byte + 2*l_bad_dq_pair_index, 8*l_byte + 2*l_bad_dq_pair_index + 1, l_symbol_mark ); @@ -4716,7 +4827,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, o_repairs_exceeded |= l_repairs_exceeded_translation[1][l_dimm]; } - FAPI_INF("port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, symbols %d-%d, FIXED SYMBOL WITH X8 STEER", + FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, symbols %d-%d, FIXED SYMBOL WITH X8 STEER", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte], 8*l_byte + 2*l_bad_dq_pair_index, 8*l_byte + 2*l_bad_dq_pair_index + 1, l_bad_symbol, @@ -4753,7 +4864,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, if (l_byte==9) { l_chip_mark = mss_centaurDQ_to_symbol(8*l_byte_being_steered,l_port) - 3; - FAPI_INF("Bad spare so chip mark goes on l_byte_being_steered = %d", l_byte_being_steered); + FAPI_ERR("WARNING: Bad spare so chip mark goes on l_byte_being_steered = %d", l_byte_being_steered); } else @@ -4789,7 +4900,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, o_repairs_exceeded |= l_repairs_exceeded_translation[1][l_dimm]; } - FAPI_INF("port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, symbols %d-%d, FIXED SYMBOL WITH X8 CHIP MARK", + FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, symbols %d-%d, FIXED SYMBOL WITH X8 CHIP MARK", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte], 8*l_byte + 2*l_bad_dq_pair_index, 8*l_byte + 2*l_bad_dq_pair_index + 1, l_chip_mark, @@ -4812,7 +4923,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, o_repairs_exceeded |= l_repairs_exceeded_translation[0][l_dimm]; } - FAPI_INF("port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, REPAIRS EXCEEDED", + FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, REPAIRS EXCEEDED", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte], 8*l_byte + 2*l_bad_dq_pair_index, 8*l_byte + 2*l_bad_dq_pair_index + 1); @@ -5030,10 +5141,17 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, return l_rc; } - // No isolation if cmd is timebased steer cleanup, or pattern is random - if ((l_cmd_type == 2) || (l_initPattern == 8)) + // No isolation if cmd is timebased steer cleanup + if (l_cmd_type == 2) { - FAPI_ERR("No UE isolation for steer cleanup or random pattern"); + FAPI_ERR("WARNING: rank%d maint UE during steer cleanup - no bad bit isolation possible.", i_rank); + return l_rc; + } + + // No isolation if pattern is random + if (l_initPattern == 8) + { + FAPI_ERR("WARNING: rank%d maint UE with random pattern - no bad bit isolation possible.", i_rank); return l_rc; } @@ -5269,9 +5387,8 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, //---------------------------------------------------- // READ steer mux, which gets me a symbol for port0 and port1 - l_rc = mss_get_steer_mux(i_target, + l_rc = mss_check_steering(i_target, i_rank, - mss_SteerMux::READ_MUX, l_dramSparePort0Symbol, l_dramSparePort1Symbol, l_eccSpareSymbol); @@ -5313,11 +5430,13 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, // Show results //---------------------------------------------------- + FAPI_ERR("WARNING: IPL UE isolation results for rank = %d.", i_rank); + FAPI_ERR("WARNING: Expected pattern = 0x%.8X", mss_maintBufferData[l_initPattern][0][0]); for(l_port=0; l_port<2; l_port++ ) { for(l_byte=0; l_byte<10; l_byte++ ) { - FAPI_INF("o_bad_bits[%d][%d] = %02x", + FAPI_ERR("WARNING: o_bad_bits[port%d][byte%d] = %02x", l_port, l_byte, o_bad_bits[l_port][l_byte]); } } diff --git a/src/usr/hwpf/hwp/dram_training/makefile b/src/usr/hwpf/hwp/dram_training/makefile index e251b81e7..13f468553 100644 --- a/src/usr/hwpf/hwp/dram_training/makefile +++ b/src/usr/hwpf/hwp/dram_training/makefile @@ -48,6 +48,7 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mem_startclocks EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_scominit EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mem_pll_setup EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build ## NOTE: add new object files when you add a new HWP OBJS = dram_training.o \ diff --git a/src/usr/hwpf/hwp/dram_training/memory_errors.xml b/src/usr/hwpf/hwp/dram_training/memory_errors.xml index 3eb48ee4a..b12665f62 100644 --- a/src/usr/hwpf/hwp/dram_training/memory_errors.xml +++ b/src/usr/hwpf/hwp/dram_training/memory_errors.xml @@ -21,8 +21,7 @@ <!-- --> <!-- IBM_PROLOG_END_TAG --> <hwpErrors> -<!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB --> -<!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP --> +<!-- EDIT THIS FILE DIRECTLY. THE ODS FILE METHOD IS NO LONGER VALID --> <!-- *********************************************************************** --> <hwpError> @@ -613,6 +612,111 @@ </hwpError> <hwpError> + <rc>RC_MSS_MAINT_GET_ADDRESS_RANGE_BAD_INPUT</rc> + <description>i_rank input to mss_get_address_range out of range</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: RANK we are trying to get address range for --> + <ffdc>RANK</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + + <hwpError> + <rc>RC_MSS_MAINT_GET_MARK_STORE_BAD_INPUT</rc> + <description>i_rank input to mss_get_mark_store out of range</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: RANK we are trying read markstore for --> + <ffdc>RANK</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + + <hwpError> + <rc>RC_MSS_MAINT_PUT_MARK_STORE_BAD_INPUT</rc> + <description>i_rank input to mss_put_mark_store out of range</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: RANK we are trying write markstore for --> + <ffdc>RANK</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + + <hwpError> + <rc>RC_MSS_MAINT_GET_STEER_MUX_BAD_INPUT</rc> + <description>i_rank or i_muxType input to mss_get_steer_mux out of range</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: RANK we are reading steer mux for --> + <ffdc>RANK</ffdc> + <!-- FFDC: MUX_TYPE: read or write --> + <ffdc>MUX_TYPE</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + + <hwpError> + <rc>RC_MSS_MAINT_PUT_STEER_MUX_BAD_INPUT</rc> + <description>i_rank or i_muxType or i_steerType or i_symbol input to mss_get_steer_mux out of range</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: RANK we are writing steer mux for --> + <ffdc>RANK</ffdc> + <!-- FFDC: MUX_TYPE: read or write --> + <ffdc>MUX_TYPE</ffdc> + <!-- FFDC: STEER_TYPE: port0 spare, port1 spare or ecc spare --> + <ffdc>STEER_TYPE</ffdc> + <!-- FFDC: SYMBOL: 0-71 --> + <ffdc>SYMBOL</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + + <hwpError> + <rc>RC_MSS_MAINT_DO_STEER_INPUT_OUT_OF_RANGE</rc> + <description>i_rank or i_symbol input to mss_do_steer out of range</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: RANK we are writing steer mux for --> + <ffdc>RANK</ffdc> + <!-- FFDC: SYMBOL: 0-71 --> + <ffdc>SYMBOL</ffdc> + <!-- FFDC: X4ECCSPARE: true or false --> + <ffdc>X4ECCSPARE</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + + <hwpError> + <rc>RC_MSS_MAINT_UNSUCCESSFUL_FORCED_MAINT_CMD_STOP</rc> + <description>MBMSRQ[0] = 1, unsuccessful forced maint cmd stop.</description> + <!-- FFDC: Capture register we used to stop cmd --> + <ffdc>MBMCC</ffdc> + <!-- FFDC: Capture register we are checking --> + <ffdc>MBMSR</ffdc> + <!-- FFDC: Capture command type we are trying to run --> + <ffdc>CMD_TYPE</ffdc> + <!-- Callout MBA HIGH --> + <callout><target>MBA</target><priority>HIGH</priority></callout> + <!-- Deconfigure MBA --> + <deconfigure><target>MBA</target></deconfigure> + <!-- Create GARD record for MASTER_CHIP --> + <gard><target>MBA</target></gard> +</hwpError> + + + <hwpError> + <rc>RC_MSS_MEMDIAGS_RESTORE_REPAIRS_EXCEEDED</rc> + <description>FATAL: Memdiags exiting with error before running patterns, due to DRAM repairs exceeded.</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> +</hwpError> + + <hwpError> + <rc>RC_MSS_MEMDIAGS_UE_OR_SUE_IN_LAST_PATTERN</rc> + <description>FATAL: Memdiags exiting with error due to UE, or SUE(in last pattern).</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> +</hwpError> + + + <hwpError> <rc>RC_MSS_UNSUPPORTED_SPD_DATA</rc> <description>Invalid SPD data returned.</description> </hwpError> @@ -765,6 +869,32 @@ <description>Invalid input </description> </hwpError> -<!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB --> -<!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP --> +<hwpError> + <rc>RC_MSS_NON_CHECKER_BOARD_MODE_GROUPING_NOT_POSSIBLE</rc> + <description>FABRIC IS IN NON-CHECKER BOARD MODE. SET ATTRIBUTE 'ATTR_MSS_INTERLEAVE_ENABLE' TO SUPPORT '2MCS/GROUP, 4MCS/GROUP AND 8MCS/GROUP'. OR ENABLE CHECKER BOARD, TO SUPPORT '1MCS/GROUP'. MRW NEEDS TO BE UPDATED. </description> +</hwpError> + +<hwpError> + <rc>RC_MSS_CHECKER_BOARD_MODE_GROUPING_NOT_POSSIBLE</rc> + <description>FABRIC IS IN CHECKER BOARD MODE BUT IT DOES NOT SUPPORT 1MCS/GROUP. SET ATTRIBUTE 'ATTR_MSS_INTERLEAVE_ENABLE' TO SUPPORT '1MCS/GROUP'. OR DISABLE CHECKER BOARD, TO SUPPORT '2MCS/GROUP, 4MCS/GROUP AND 8MCS/GROUP'. MRW NEEDS TO BE UPDATED. </description> +</hwpError> + +<hwpError> + <rc>RC_MSS_UNABLE_TO_GROUP_MCS</rc> + <description>MCS COULD NOT BE GROUPED. EITHER SWITCH DIMMS SO GROUPING IS POSSIBLE OR CHANGE SYSTEM POLICY.</description> + <gard><target>TARGET_MCS</target></gard> + <deconfigure><target>TARGET_MCS</target></deconfigure> +</hwpError> + +<hwpError> + <rc>RC_MSS_UNABLE_TO_GROUP_SUMMARY</rc> + <description>MCS COULD NOT BE GROUPED. SEE PREVIOUS ERROR MESSAGES FOR WHICH MCS HAS BEEN RC_MSS_UNABLE_TO_GROUP_MCS</description> +</hwpError> + +<hwpError> + <rc>RC_MSS_BASE_ADDRESS_OVERLAPS_MIRROR_ADDRESS</rc> + <description>MIRROR BASE ADDRESS OVERLAPS WITH MEMORY BASE ADDRESS.</description> +</hwpError> + +<!-- EDIT THIS FILE DIRECTLY. THE ODS FILE METHOD IS NO LONGER VALID --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C index f5ab3267f..b8d6d9b2f 100755 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit.C,v 1.44 2013/01/25 15:16:21 jdsloat Exp $ +// $Id: mss_draminit.C,v 1.46 2013/02/12 17:24:16 jdsloat Exp $ //------------------------------------------------------------------------------ // Don't forget to create CVS comments when you check in your changes! //------------------------------------------------------------------------------ @@ -28,6 +28,8 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.46 | jdsloat | 02/12/13| Fixed RTT_WR in MR2 +// 1.45 | jdsloat | 01/28/13| is_sim check for address mirror mode // 1.44 | jdsloat | 01/25/13| Address Mirror Mode added for dual drop CDIMMs // 1.43 | bellows | 12/06/12| Fixed Review Comment // 1.42 | jdsloat | 12/02/12| SHADOW REG PRINT OUT FIX @@ -168,6 +170,7 @@ ReturnCode mss_draminit_cloned(Target& i_target) uint8_t secondary_ranks_array[4][2]; //secondary_ranks_array[group][port] uint8_t tertiary_ranks_array[4][2]; //tertiary_ranks_array[group][port] uint8_t quaternary_ranks_array[4][2]; //quaternary_ranks_array[group][port] + uint8_t is_sim = 0; //populate primary_ranks_arrays_array @@ -212,11 +215,14 @@ ReturnCode mss_draminit_cloned(Target& i_target) if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim); + if(rc) return rc; // Check to see if it's Dual drop and needs address mirror mode. Set the approriate flag. if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_CDIMM) && (num_drops_per_port == ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) - && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) ) + && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) + && (is_sim == 0) ) { FAPI_INF( "Setting Address Mirroring in the PHY"); @@ -1017,6 +1023,10 @@ ReturnCode mss_mrs_load( rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type); if(rc) return rc; + uint8_t is_sim = 0; + rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim); + if(rc) return rc; + //Lines commented out in the following section are waiting for xml attribute adds //MRS0 @@ -1427,7 +1437,7 @@ ReturnCode mss_mrs_load( rc_num = rc_num | mrs2.insert((uint8_t) sr_temp, 7, 1); rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 8, 1); rc_num = rc_num | mrs2.insert((uint8_t) dram_rtt_wr[i_port_number][dimm_number][rank_number], 9, 2); - rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 10, 6); + rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 11, 5); rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); @@ -1487,7 +1497,7 @@ ReturnCode mss_mrs_load( rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS0_BA, 2, 1, 5); } - if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_CDIMM) && (dimm_number == 1) ) + if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_CDIMM) && (dimm_number == 1) && (is_sim == 0)) { FAPI_INF( "ADDRESS MIRRORING ON PORT%d DIMM%d RANK%d", i_port_number, dimm_number, rank_number); diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C index 954849674..f1a1812f5 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit_mc.C,v 1.31 2013/01/21 16:47:20 lapietra Exp $ +// $Id: mss_draminit_mc.C,v 1.33 2013/02/04 20:04:51 lapietra Exp $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -44,6 +44,8 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.33 | dcadiga |04-FEB-13| For some reason the main procedure call was commented out in the last commit... commenting it back in +// 1.32 | gollub |31-JAN-13| Uncommenting mss_unmask_maint_errors and mss_unmask_inband_errors // 1.31 | dcadiga |21-JAN-13| Fixed variable name for memcal_interval (coded as memcal_iterval...) // 1.30 | dcadiga |21-JAN-13| Hardcoded memcal interval to 0 (disabled) until attribute for EC is available // 1.29 | jdsloat |14-JAN-13| Owner changed to Dave Cadigan. @@ -124,20 +126,20 @@ ReturnCode mss_draminit_mc(Target& i_target) // Target is centaur.mba fapi::ReturnCode l_rc; - + //Commented back in by dcadiga l_rc = mss_draminit_mc_cloned(i_target); // If mss_unmask_maint_errors gets it's own bad rc, // it will commit the passed in rc (if non-zero), and return it's own bad rc. // Else if mss_unmask_maint_errors runs clean, // it will just return the passed in rc. - //l_rc = mss_unmask_maint_errors(i_target, l_rc); // TODO: uncomment after this can be tested on hw + l_rc = mss_unmask_maint_errors(i_target, l_rc); // If mss_unmask_inband_errors gets it's own bad rc, // it will commit the passed in rc (if non-zero), and return it's own bad rc. // Else if mss_unmask_inband_errors runs clean, // it will just return the passed in rc. - //l_rc = mss_unmask_inband_errors(i_target, l_rc); // TODO: uncomment after this can be tested on hw + l_rc = mss_unmask_inband_errors(i_target, l_rc); return l_rc; } diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C index 3befd7465..2c317afc3 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit_training_advanced.C,v 1.24 2013/01/17 20:55:31 sasethur Exp $ +// $Id: mss_draminit_training_advanced.C,v 1.25 2013/01/31 15:54:58 sasethur Exp $ /* File is created by SARAVANAN SETHURAMAN on Thur 29 Sept 2011. */ //------------------------------------------------------------------------------ @@ -64,6 +64,8 @@ // 1.22 | sasethur |07-Dec-12| Updated for FW review comments - multiple changes // 1.23 | sasethur |14-Dec-12| Updated for FW review comments // 1.24 | sasethur |17-Jan-13| Updated for mss_mcbist_common.C include file +// 1.25 | abhijsau |31-Jan-13| removed mss_mcbist_common.C include file , needs to be included while compiling + // This procedure Schmoo's DRV_IMP, SLEW, VREF (DDR, CEN), RCV_IMP based on attribute from effective config procedure // DQ & DQS Driver impedance, Slew rate, WR_Vref shmoo would call only write_eye shmoo for margin calculation @@ -82,7 +84,7 @@ //Centaur functions //---------------------------------------------------------------------- #include <mss_termination_control.H> -#include <mss_mcbist.H> +#include "mss_mcbist.H" #include <mss_shmoo_common.H> #include <mss_generic_shmoo.H> #include <mss_draminit_training_advanced.H> @@ -272,7 +274,7 @@ fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_ta { if (( l_num_ranks_per_dimm_u8array[l_port][0] > 0 ) || (l_num_ranks_per_dimm_u8array[l_port][1] > 0)) { - if(l_shmoo_param_valid != PARAM_NONE) + if((l_shmoo_param_valid != PARAM_NONE) || (l_shmoo_type_valid != TEST_NONE)) { if((l_shmoo_param_valid & DRV_IMP) != 0) { @@ -319,7 +321,7 @@ fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_ta return rc; } } - if ((l_shmoo_param_valid & DELAY_REG) != 0) + if (((l_shmoo_param_valid & DELAY_REG) != 0) || (l_shmoo_type_valid != 0)) { rc = delay_shmoo(i_target_mba, l_port, l_shmoo_type_valid, &l_left_margin, &l_right_margin,i_pattern,i_test_type); if (rc) @@ -962,9 +964,10 @@ fapi::ReturnCode delay_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, uint8_t i_test_type) { fapi::ReturnCode rc; - // FAPI_INF(" Inside the delay shmoo "); + FAPI_INF(" Inside the delay shmoo " ); //Constructor CALL: generic_shmoo::generic_shmoo(uint8_t i_port, uint32_t shmoo_mask,shmoo_algorithm_t shmoo_algorithm) - generic_shmoo mss_shmoo=generic_shmoo(i_port,i_shmoo_type_valid,SEQ_LIN); + //generic_shmoo mss_shmoo=generic_shmoo(i_port,2,SEQ_LIN); + generic_shmoo mss_shmoo=generic_shmoo(i_port,i_shmoo_type_valid,SEQ_LIN); rc = mss_shmoo.run(i_target_mba, o_left_margin, o_right_margin,i_pattern,i_test_type); if(rc) { diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C index d8036a84e..1a2f3b8e6 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit_training.C,v 1.51 2013/01/31 22:33:54 gollub Exp $ +// $Id: mss_draminit_training.C,v 1.55 2013/02/25 19:05:31 jdsloat Exp $ //------------------------------------------------------------------------------ // Don't forget to create CVS comments when you check in your changes! //------------------------------------------------------------------------------ @@ -28,6 +28,13 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|------------------------------------------------ +// 1.55 | jdsloat |25-FEB-13| Added MBA/Port info to debug messages. +// 1.54 | jdsloat |22-FEB-13| Edited WRITE_READ workaround to also edit DQSCLK PHASE +// 1.53 | jdsloat |14-FEB-13| Fixed WRITE_READ workaround so it will execute in a partial substep case +// | | | Edited mss_rtt_nom_rtt_wr_swap to only write rtt_nom with rtt_wr or supplied rtt_nom +// | | | Moved location of mss_rtt_nom_rtt_wr_swap around wr_lvl substep +// | | | Added Address Mirror Mode. +// 1.52 | jdsloat |07-FEB-13| Fixed address typo for RP3 in WRITE_READ workaround. // 1.51 | gollub |31-JAN-13| Uncommenting mss_unmask_draminit_training_errors // 1.50 | jdsloat |16-JAN-13| Fixed rank group enable within PC_INIT_CAL reg // 1.49 | jdsloat |08-JAN-13| Added clearing RD PHASE SELECT values post Read Centering Workaround. @@ -150,7 +157,8 @@ ReturnCode mss_draminit_training(Target& i_target); ReturnCode mss_draminit_training_cloned(Target& i_target); ReturnCode mss_check_cal_status(Target& i_target, uint8_t i_port, uint8_t i_group, mss_draminit_training_result& io_status); ReturnCode mss_check_error_status(Target& i_target, uint8_t i_port, uint8_t i_group, mss_draminit_training_result& io_status); -ReturnCode mss_rtt_nom_rtt_wr_swap( Target& i_target, uint32_t i_port_number, uint8_t i_rank, uint32_t i_rank_pair_group, uint32_t& io_ccs_inst_cnt); +ReturnCode mss_rtt_nom_rtt_wr_swap( Target& i_target, uint32_t i_port_number, uint8_t i_rank, uint32_t i_rank_pair_group, uint32_t& io_ccs_inst_cnt, uint8_t& io_dram_rtt_nom_original); + ReturnCode getC4dq2reg(const Target &i_mba, const uint8_t i_port, const uint8_t i_dimm, const uint8_t i_rank, ecmdDataBufferBase &o_reg); ReturnCode setC4dq2reg(const Target &i_mba, const uint8_t i_port, const uint8_t i_dimm, const uint8_t i_rank, ecmdDataBufferBase &o_reg); ReturnCode mss_set_bbm_regs (const fapi::Target & mba_target); @@ -252,11 +260,16 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) uint8_t cal_steps = 0; uint8_t cur_cal_step = 0; ecmdDataBufferBase cal_steps_8(8); - uint64_t ADDR_0 = 0; - uint64_t ADDR_1 = 0; - uint64_t ADDR_2 = 0; - uint64_t ADDR_3 = 0; - uint64_t ADDR_4 = 0; + uint64_t DQSCLK_RD_PHASE_ADDR_0 = 0; + uint64_t DQSCLK_RD_PHASE_ADDR_1 = 0; + uint64_t DQSCLK_RD_PHASE_ADDR_2 = 0; + uint64_t DQSCLK_RD_PHASE_ADDR_3 = 0; + uint64_t DQSCLK_RD_PHASE_ADDR_4 = 0; + uint8_t l_value_u8 = 0; + uint8_t l_new_value_u8 = 0; + uint8_t l_nwell_misplacement = 0; + + uint8_t dram_rtt_nom_original = 0; enum mss_draminit_training_result cur_complete_status = MSS_INIT_CAL_COMPLETE; enum mss_draminit_training_result cur_error_status = MSS_INIT_CAL_PASS; @@ -264,6 +277,9 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) enum mss_draminit_training_result complete_status = MSS_INIT_CAL_COMPLETE; enum mss_draminit_training_result error_status = MSS_INIT_CAL_PASS; + fapi::Target l_target_centaur; + rc = fapiGetParentChip(i_target, l_target_centaur); if(rc) return rc; + //populate primary_ranks_arrays_array rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, primary_ranks_array[0]); if(rc) return rc; @@ -274,9 +290,22 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, primary_ranks_array[3]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_MSS_NWELL_MISPLACEMENT, &l_target_centaur, l_nwell_misplacement); + if(rc) return rc; + + uint8_t mbaPosition; + // Get MBA position: 0 = mba01, 1 = mba23 + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, mbaPosition); + if(rc) + { + FAPI_ERR("Error getting MBA position"); + return rc; + } + //Get which training steps we are to run rc = FAPI_ATTR_GET(ATTR_MSS_CAL_STEP_ENABLE, &i_target, cal_steps); if(rc) return rc; + rc_num = rc_num | cal_steps_8.insert(cal_steps, 0, 8, 0); //Set up CCS Mode Reg for Init cal @@ -310,7 +339,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) (cal_steps_8.isBitClear(4)) && (cal_steps_8.isBitClear(5)) && (cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitClear(7)) )) { - FAPI_INF( "Performing External ZQ Calibration."); + FAPI_INF( "Performing External ZQ Calibration on MBA %d.", mbaPosition); //Execute ZQ_CAL for(port = 0; port < MAX_NUM_PORT; port++) @@ -331,12 +360,6 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) if(primary_ranks_array[group][port] != INVALID) { - // Temporarily disable this function for HW debug - // Change the RTT_NOM to RTT_WR, RTT_WR to RTT_NOM - //rc = mss_rtt_nom_rtt_wr_swap(i_target, port, primary_ranks_array[group][port], group, instruction_number); - if(rc) return rc; - - //Set up for Init Cal - Done per port pair rc_num = rc_num | test_buffer_4.setBit(0, 2); //Init Cal test = 11XX rc_num = rc_num | wen_buffer_1.flushTo1(); //Init Cal ras/cas/we = 1/1/1 @@ -344,7 +367,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) rc_num = rc_num | rasn_buffer_1.flushTo1(); rc_num = rc_num | ddr_cal_enable_buffer_1.flushTo1(); //Init cal - FAPI_INF( "+++ Setting up Init Cal on rank group: %d cal_steps: 0x%02X +++", group, cal_steps); + FAPI_INF( "+++ Setting up Init Cal on MBA: %d Port: %d rank group: %d cal_steps: 0x%02X +++", mbaPosition, port, group, cal_steps); for(cur_cal_step = 1; cur_cal_step < MAX_CAL_STEPS; cur_cal_step++) //Cycle through all possible cal steps { @@ -466,7 +489,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) (cal_steps_8.isBitClear(4)) && (cal_steps_8.isBitClear(5)) && (cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitClear(7)) ) { - FAPI_INF( "+++ Executing ALL Cal Steps at the same time on rank group: %d +++", group); + FAPI_INF( "+++ Executing ALL Cal Steps at the same time on MBA: %d Port: %d rank group: %d +++", mbaPosition, port, group); rc_num = rc_num | data_buffer_64.setBit(48); rc_num = rc_num | data_buffer_64.setBit(50); rc_num = rc_num | data_buffer_64.setBit(51); @@ -477,42 +500,42 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) } else if ( (cur_cal_step == 1) && (cal_steps_8.isBitSet(1)) ) { - FAPI_INF( "+++ Write Leveling (WR_LVL) on rank group: %d +++", group); + FAPI_INF( "+++ Write Leveling (WR_LVL) on MBA: %d Port %d rank group: %d +++", mbaPosition, port, group); rc_num = rc_num | data_buffer_64.setBit(48); } else if ( (cur_cal_step == 2) && (cal_steps_8.isBitSet(2)) ) { - FAPI_INF( "+++ DQS Align (DQS_ALIGN) on rank group: %d +++", group); + FAPI_INF( "+++ DQS Align (DQS_ALIGN) on MBA: %d Port: %d rank group: %d +++", mbaPosition, port, group); rc_num = rc_num | data_buffer_64.setBit(50); } else if ( (cur_cal_step == 3) && (cal_steps_8.isBitSet(3)) ) { - FAPI_INF( "+++ RD CLK Align (RDCLK_ALIGN) on rank group: %d +++", group); + FAPI_INF( "+++ RD CLK Align (RDCLK_ALIGN) on MBA: %d Port: %d rank group: %d +++", mbaPosition, port, group); rc_num = rc_num | data_buffer_64.setBit(51); } else if ( (cur_cal_step == 4) && (cal_steps_8.isBitSet(4)) ) { - FAPI_INF( "+++ Read Centering (READ_CTR) on rank group: %d +++", group); + FAPI_INF( "+++ Read Centering (READ_CTR) on MBA: %d Port: %d rank group: %d +++", mbaPosition, port, group); rc_num = rc_num | data_buffer_64.setBit(52); } else if ( (cur_cal_step == 5) && (cal_steps_8.isBitSet(5)) ) { - FAPI_INF( "+++ Write Centering (WRITE_CTR) on rank group: %d +++", group); + FAPI_INF( "+++ Write Centering (WRITE_CTR) on MBA: %d Port: %d rank group: %d +++", mbaPosition, port, group); rc_num = rc_num | data_buffer_64.setBit(53); } else if ( (cur_cal_step == 6) && (cal_steps_8.isBitSet(6)) && (cal_steps_8.isBitClear(7)) ) { - FAPI_INF( "+++ Initial Course Write (COURSE_WR) on rank group: %d +++", group); + FAPI_INF( "+++ Initial Course Write (COURSE_WR) on MBA: %d Port: %d rank group: %d +++", mbaPosition, port, group); rc_num = rc_num | data_buffer_64.setBit(54); } else if ( (cur_cal_step == 6) && (cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitSet(7)) ) { - FAPI_INF( "+++ Course Read (COURSE_RD) on rank group: %d +++", group); + FAPI_INF( "+++ Course Read (COURSE_RD) on MBA: %d Port: %d rank group: %d +++", mbaPosition, port, group); rc_num = rc_num | data_buffer_64.setBit(55); } else if ( (cur_cal_step == 6) && (cal_steps_8.isBitSet(6)) && (cal_steps_8.isBitSet(7)) ) { - FAPI_INF( "+++ Initial Course Write (COURSE_WR) and Course Read (COURSE_RD) simultaneously on rank group: %d +++", group); + FAPI_INF( "+++ Initial Course Write (COURSE_WR) and Course Read (COURSE_RD) simultaneously on MBA: %d Port: %d rank group: %d +++", mbaPosition, port, group); rc_num = rc_num | data_buffer_64.setBit(54); rc_num = rc_num | data_buffer_64.setBit(55); } @@ -526,6 +549,20 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) if ( !( data_buffer_64.isBitClear(48, 8) ) ) // Only execute if we are doing a Cal Step { + // Before WR_LVL --- Change the RTT_NOM to RTT_WR pre-WR_LVL + if (cur_cal_step == 1) + { + dram_rtt_nom_original = 0; + rc = mss_rtt_nom_rtt_wr_swap(i_target, + port, + primary_ranks_array[group][port], + group, + instruction_number, + dram_rtt_nom_original); + if(rc) return rc; + } + + //Set the config register if(port == 0) { @@ -571,6 +608,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs + rc = mss_execute_ccs_inst_array( i_target, NUM_POLL, 60); if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs @@ -592,125 +630,196 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) error_status = cur_error_status; } - if ( (cur_cal_step == 4) && (cal_steps_8.isBitSet(5)) ) + // Following WR_LVL -- Restore RTT_NOM to orignal value post-wr_lvl + if (cur_cal_step == 1) + { + rc = mss_rtt_nom_rtt_wr_swap(i_target, + port, + primary_ranks_array[group][port], + group, + instruction_number, + dram_rtt_nom_original); + if(rc) return rc; + + } + + // Following Read Centering -- Enter into READ CENTERING WORKAROUND + // Adding a switch in anticipation of depending on the NWELL state. + // Currently will execute in either case + if ( (cur_cal_step == 4) && + ( ( l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_TRUE ) + ||( l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_FALSE ) ) ) { FAPI_INF( "+++ Read Centering Workaround on rank group: %d +++", group); FAPI_INF( "+++ Clearing values from RD PHASE SELECT regs. +++"); + FAPI_INF( "+++ Incrementing by 2 values from DQS CLK PHASE SELECT regs. +++"); if ( port == 0 ) { if ( group == 0 ) { - ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; - ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; - ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; - ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; - ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; + } else if ( group == 1 ) { - ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; - ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; - ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; - ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; - ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; + } else if ( group == 2 ) { - ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; - ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; - ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; - ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; - ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; + } else if ( group == 3 ) { - ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; - ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; - ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; - ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; - ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; + } } else if (port == 1 ) { if ( group == 0 ) { - ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; - ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; - ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; - ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; - ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; + } else if ( group == 1 ) { - ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; - ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; - ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; - ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; - ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; + + } else if ( group == 2 ) { - ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; - ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; - ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; - ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; - ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; + } else if ( group == 3 ) { - ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; - ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; - ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; - ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; - ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; + } } - rc = fapiGetScom(i_target, ADDR_0, data_buffer_64); + // Set Read Phase to 0. + //Increment dqs clk 2. 4 is the limit, wrap around (IE 5 = 1, 6 = 2) + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); + if (rc) return rc; rc_num = rc_num | data_buffer_64.clearBit(50, 2); rc_num = rc_num | data_buffer_64.clearBit(54, 2); rc_num = rc_num | data_buffer_64.clearBit(58, 2); rc_num = rc_num | data_buffer_64.clearBit(62, 2); - rc = fapiPutScom(i_target, ADDR_0, data_buffer_64); - rc = fapiGetScom(i_target, ADDR_1, data_buffer_64); + for ( uint8_t l_element_u8 = 0; l_element_u8 < 4; l_element_u8 += 1 ) { + l_value_u8 = 0; + data_buffer_64.extractToRight(&l_value_u8, (48 + (l_element_u8 * 4)), 2); + l_new_value_u8 = (l_value_u8 + 2) % 4; + data_buffer_64.insertFromRight(&l_new_value_u8, (48 + (l_element_u8 * 4)), 2); + } + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); + if (rc) return rc; + + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); + if (rc) return rc; rc_num = rc_num | data_buffer_64.clearBit(50, 2); rc_num = rc_num | data_buffer_64.clearBit(54, 2); rc_num = rc_num | data_buffer_64.clearBit(58, 2); rc_num = rc_num | data_buffer_64.clearBit(62, 2); - rc = fapiPutScom(i_target, ADDR_1, data_buffer_64); - rc = fapiGetScom(i_target, ADDR_2, data_buffer_64); + for ( uint8_t l_element_u8 = 0; l_element_u8 < 4; l_element_u8 += 1 ) { + l_value_u8 = 0; + data_buffer_64.extractToRight(&l_value_u8, (48 + (l_element_u8 * 4)), 2); + l_new_value_u8 = (l_value_u8 + 2) % 4; + data_buffer_64.insertFromRight(&l_new_value_u8, (48 + (l_element_u8 * 4)), 2); + } + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); + if (rc) return rc; + + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); + if (rc) return rc; rc_num = rc_num | data_buffer_64.clearBit(50, 2); rc_num = rc_num | data_buffer_64.clearBit(54, 2); rc_num = rc_num | data_buffer_64.clearBit(58, 2); rc_num = rc_num | data_buffer_64.clearBit(62, 2); - rc = fapiPutScom(i_target, ADDR_2, data_buffer_64); - rc = fapiGetScom(i_target, ADDR_3, data_buffer_64); + for ( uint8_t l_element_u8 = 0; l_element_u8 < 4; l_element_u8 += 1 ) { + l_value_u8 = 0; + data_buffer_64.extractToRight(&l_value_u8, (48 + (l_element_u8 * 4)), 2); + l_new_value_u8 = (l_value_u8 + 2) % 4; + data_buffer_64.insertFromRight(&l_new_value_u8, (48 + (l_element_u8 * 4)), 2); + } + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); + if (rc) return rc; + + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); + if (rc) return rc; rc_num = rc_num | data_buffer_64.clearBit(50, 2); rc_num = rc_num | data_buffer_64.clearBit(54, 2); rc_num = rc_num | data_buffer_64.clearBit(58, 2); rc_num = rc_num | data_buffer_64.clearBit(62, 2); - rc = fapiPutScom(i_target, ADDR_3, data_buffer_64); - rc = fapiGetScom(i_target, ADDR_4, data_buffer_64); + for ( uint8_t l_element_u8 = 0; l_element_u8 < 4; l_element_u8 += 1 ) { + l_value_u8 = 0; + data_buffer_64.extractToRight(&l_value_u8, (48 + (l_element_u8 * 4)), 2); + l_new_value_u8 = (l_value_u8 + 2) % 4; + data_buffer_64.insertFromRight(&l_new_value_u8, (48 + (l_element_u8 * 4)), 2); + } + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); + if (rc) return rc; + + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); + if (rc) return rc; rc_num = rc_num | data_buffer_64.clearBit(50, 2); rc_num = rc_num | data_buffer_64.clearBit(54, 2); rc_num = rc_num | data_buffer_64.clearBit(58, 2); rc_num = rc_num | data_buffer_64.clearBit(62, 2); - rc = fapiPutScom(i_target, ADDR_4, data_buffer_64); + + for ( uint8_t l_element_u8 = 0; l_element_u8 < 4; l_element_u8 += 1 ) { + l_value_u8 = 0; + data_buffer_64.extractToRight(&l_value_u8, (48 + (l_element_u8 * 4)), 2); + l_new_value_u8 = (l_value_u8 + 2) % 4; + data_buffer_64.insertFromRight(&l_new_value_u8, (48 + (l_element_u8 * 4)), 2); + } + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); + if (rc) return rc; } } }//end of step loop - - // Temporarily disable this function for HW debug - // Change the RTT_NOM to RTT_WR, RTT_WR to RTT_NOM - //rc = mss_rtt_nom_rtt_wr_swap(i_target, port, primary_ranks_array[group][port], group, instruction_number); } }//end of group loop }//end of port loop @@ -876,9 +985,17 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( uint32_t i_port_number, uint8_t i_rank, uint32_t i_rank_pair_group, - uint32_t& io_ccs_inst_cnt + uint32_t& io_ccs_inst_cnt, + uint8_t& io_dram_rtt_nom_original ) { + // Target MBA level + // This is a function written specifically for mss_draminit_training + // Meant for placing RTT_WR into RTT_NOM within MR1 before wr_lvl + // If the function argument dram_rtt_nom_original is 0 it will put the original rtt_nom there + // and write rtt_wr to the rtt_nom value + // If the function argument dram_rtt_nom_original has a value it will write that value to rtt_nom. + ReturnCode rc; ReturnCode rc_buff; @@ -886,6 +1003,8 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( ecmdDataBufferBase address_16(16); ecmdDataBufferBase bank_3(3); + ecmdDataBufferBase address_pre_AMM_16(16); + ecmdDataBufferBase bank_pre_AMM_3(3); ecmdDataBufferBase activate_1(1); ecmdDataBufferBase rasn_1(1); rc_num = rc_num | rasn_1.clearBit(0); @@ -916,6 +1035,16 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( uint16_t MRS1 = 0; uint16_t MRS2 = 0; + uint16_t mirror_mode_ba = 0; + uint16_t mirror_mode_ad = 0; + + uint8_t dimm_type; + rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type); + if(rc) return rc; + + uint8_t is_sim = 0; + rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim); + if(rc) return rc; // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles rc_num = rc_num | csn_8.setBit(0,8); @@ -964,11 +1093,27 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( { rc_num = rc_num | csn_8.clearBit(3); } + else if (i_rank == 4) + { + rc_num = rc_num | csn_8.clearBit(4); + } + else if (i_rank == 5) + { + rc_num = rc_num | csn_8.clearBit(5); + } + else if (i_rank == 6) + { + rc_num = rc_num | csn_8.clearBit(6); + } + else if (i_rank == 7) + { + rc_num = rc_num | csn_8.clearBit(7); + } // MRS CMD to CMD spacing = 12 cycles rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 12, 0, 16); - FAPI_INF( "SWAPPING RTT_NOM AND RTT_WR FOR PORT%d RP%d", i_port_number, i_rank_pair_group); + FAPI_INF( "Editing RTT_NOM during wr_lvl for PORT%d RP%d", i_port_number, i_rank_pair_group); //MRS1 // Get contents of MRS 1 Shadow Reg @@ -1013,7 +1158,7 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs1_16.insert(data_buffer_64, 0, 16, 0); rc_num = rc_num | mrs1_16.extractPreserve(&MRS1, 0, 16, 0); - FAPI_INF( "ORIGINAL MRS 1: 0x%04X", MRS1); + FAPI_INF( "CURRENT MRS 1: 0x%04X", MRS1); uint8_t dll_enable = 0x00; //DLL Enable if (mrs1_16.isBitSet(0)) @@ -1039,44 +1184,45 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( out_drv_imp_cntl = 0x80; } - uint8_t dram_rtt_wr = 0x00; + uint8_t dram_rtt_nom = 0x00; if ( (mrs1_16.isBitClear(2)) && (mrs1_16.isBitClear(6)) && (mrs1_16.isBitClear(9)) ) { // RTT_NOM set to disabled - //RTT WR Disabled - dram_rtt_wr = 0x00; + FAPI_INF( "DRAM_RTT_NOM orignally set to Disabled."); + dram_rtt_nom = 0x00; + } else if ( (mrs1_16.isBitClear(2)) && (mrs1_16.isBitClear(6)) && (mrs1_16.isBitSet(9)) ) { // RTT_NOM set to 20 - //RTT WR 60 OHM - dram_rtt_wr = 0x80; + FAPI_INF( "DRAM_RTT_NOM orignally set to 20 Ohm."); + dram_rtt_nom = 0x20; } else if ( (mrs1_16.isBitSet(2)) && (mrs1_16.isBitClear(6)) && (mrs1_16.isBitSet(9)) ) { // RTT_NOM set to 30 - //RTT WR 60 OHM - dram_rtt_wr = 0x80; + FAPI_INF( "DRAM_RTT_NOM orignally set to 30 Ohm."); + dram_rtt_nom = 0xA0; } else if ( (mrs1_16.isBitSet(2)) && (mrs1_16.isBitSet(6)) && (mrs1_16.isBitClear(9)) ) { // RTT_NOM set to 40 - //RTT WR 60 OHM - dram_rtt_wr = 0x80; + FAPI_INF( "DRAM_RTT_NOM orignally set to 40 Ohm."); + dram_rtt_nom = 0xC0; } else if ( (mrs1_16.isBitSet(2)) && (mrs1_16.isBitSet(6)) && (mrs1_16.isBitClear(9)) ) { // RTT_NOM set to 60 - //RTT WR 60 OHM - dram_rtt_wr = 0x80; + FAPI_INF( "DRAM_RTT_NOM orignally set to 60 Ohm."); + dram_rtt_nom = 0x80; } else if ( (mrs1_16.isBitClear(2)) && (mrs1_16.isBitSet(6)) && (mrs1_16.isBitClear(9)) ) { // RTT_NOM set to 120 - // RTT_WR set to 120 - dram_rtt_wr = 0x40; + FAPI_INF( "DRAM_RTT_NOM orignally set to 120 Ohm."); + dram_rtt_nom = 0x40; } - + uint8_t dram_al = 0x00; if ( (mrs1_16.isBitClear(3)) && (mrs1_16.isBitClear(4)) ) { @@ -1130,11 +1276,8 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( q_off = 0x00; } - //MRS2 - // MRS CMD to CMD spacing = 12 cycles - rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 12, 0, 16); - // Get contents of MRS 1 Shadow Reg + // Get contents of MRS 2 Shadow Reg if (i_port_number == 0){ if (i_rank_pair_group == 0) { @@ -1175,136 +1318,99 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs2_16.insert(data_buffer_64, 0, 16, 0); rc_num = rc_num | mrs2_16.extractPreserve(&MRS2, 0, 16, 0); - FAPI_INF( "ORIGINAL MRS 2: 0x%04X", MRS2); + FAPI_INF( "MRS 2: 0x%04X", MRS2); - uint8_t pt_arr_sr = 0x00; //Partial Array Self Refresh - if ( (mrs2_16.isBitClear(0)) && (mrs2_16.isBitClear(1)) && (mrs2_16.isBitClear(2)) ) - { - //PASR FULL - pt_arr_sr = 0x00; - } - else if ( (mrs2_16.isBitSet(0)) && (mrs2_16.isBitClear(1)) && (mrs2_16.isBitClear(2)) ) - { - //PASR FIRST HALF - pt_arr_sr = 0x80; - } - else if ( (mrs2_16.isBitClear(0)) && (mrs2_16.isBitSet(1)) && (mrs2_16.isBitClear(2)) ) - { - // PASR FIRST QUARTER - pt_arr_sr = 0x40; - } - else if ( (mrs2_16.isBitSet(0)) && (mrs2_16.isBitSet(1)) && (mrs2_16.isBitClear(2)) ) - { - // PASR FIRST EIGHTH - pt_arr_sr = 0xC0; - } - else if ( (mrs2_16.isBitClear(0)) && (mrs2_16.isBitClear(1)) && (mrs2_16.isBitSet(2)) ) - { - // PASR LAST FOURTH - pt_arr_sr = 0x20; - } - else if ( (mrs2_16.isBitSet(0)) && (mrs2_16.isBitClear(1)) && (mrs2_16.isBitSet(2)) ) - { - // PASR LAST HALF - pt_arr_sr = 0xA0; - } - else if ( (mrs2_16.isBitClear(0)) && (mrs2_16.isBitSet(1)) && (mrs2_16.isBitSet(2)) ) - { - // PASR LAST QUARTER - pt_arr_sr = 0x60; - } - else if ( (mrs2_16.isBitSet(0)) && (mrs2_16.isBitSet(1)) && (mrs2_16.isBitSet(2)) ) + uint8_t dram_rtt_wr = 0x00; + if ( (mrs2_16.isBitClear(9)) && (mrs2_16.isBitClear(10)) ) { - // PASR LAST EIGHTH - pt_arr_sr = 0xE0; - } + //RTT WR DISABLE + FAPI_INF( "DRAM_RTT_WR currently set to disable."); + dram_rtt_wr = 0x00; - uint8_t cwl = 0x00; // CAS Write Latency - if ( (mrs2_16.isBitClear(3)) && (mrs2_16.isBitClear(4)) && (mrs2_16.isBitClear(5)) ) - { - // CWL = 5 - cwl = 0x00; - } - else if ( (mrs2_16.isBitSet(3)) && (mrs2_16.isBitClear(4)) && (mrs2_16.isBitClear(5)) ) - { - // CWL = 6 - cwl = 0x80; - } - else if ( (mrs2_16.isBitClear(3)) && (mrs2_16.isBitSet(4)) && (mrs2_16.isBitClear(5)) ) - { - // CWL = 7 - cwl = 0x40; - } - else if ( (mrs2_16.isBitSet(3)) && (mrs2_16.isBitSet(4)) && (mrs2_16.isBitClear(5)) ) - { - // CWL = 8 - cwl = 0xC0; - } - else if ( (mrs2_16.isBitClear(3)) && (mrs2_16.isBitClear(4)) && (mrs2_16.isBitSet(5)) ) - { - // CWL = 9 - cwl = 0x20; - } - else if ( (mrs2_16.isBitSet(3)) && (mrs2_16.isBitClear(4)) && (mrs2_16.isBitSet(5)) ) - { - // CWL = 10 - cwl = 0xA0; - } - else if ( (mrs2_16.isBitClear(3)) && (mrs2_16.isBitSet(4)) && (mrs2_16.isBitSet(5)) ) - { - // CWL = 11 - cwl = 0x60; - } - else if ( (mrs2_16.isBitSet(3)) && (mrs2_16.isBitSet(4)) && (mrs2_16.isBitSet(5)) ) - { - // CWL = 12 - cwl = 0xE0; - } + //RTT NOM CODE FOR THIS VALUE IS + // dram_rtt_nom = 0x00 - uint8_t auto_sr = 0x00; // Auto Self-Refresh - if ( (mrs2_16.isBitClear(6)) ) - { - //AUTO SR = SRT - auto_sr = 0x00; } - else if ( (mrs2_16.isBitSet(6)) ) + else if ( (mrs2_16.isBitSet(9)) && (mrs2_16.isBitClear(10)) ) { - //AUTO SR = ASR ENABLE - auto_sr = 0xFF; - } + //RTT WR 60 OHM + FAPI_INF( "DRAM_RTT_WR currently set to 60 Ohm."); + dram_rtt_wr = 0x80; + + //RTT NOM CODE FOR THIS VALUE IS + // dram_rtt_nom = 0x80 - uint8_t sr_temp = 0x00; // Self-Refresh Temp Range - if ( (mrs2_16.isBitClear(7)) ) - { - //SRT NORMAL - sr_temp = 0x00; } - else if ( (mrs2_16.isBitSet(7)) ) + else if ( (mrs2_16.isBitClear(9)) && (mrs2_16.isBitSet(10)) ) { - //SRT EXTEND - sr_temp = 0xFF; - } + //RTT WR 120 OHM + FAPI_INF( "DRAM_RTT_WR currently set to 120 Ohm."); + dram_rtt_wr = 0x40; + + //RTT NOM CODE FOR THIS VALUE IS + // dram_rtt_nom = 0x40 - uint8_t dram_rtt_nom = 0x00; - if ( (mrs2_16.isBitClear(9)) && (mrs2_16.isBitClear(10)) ) - { - //RTT WR DISABLE - // RTT_NOM set to disabled - dram_rtt_nom = 0x00; } - else if ( (mrs2_16.isBitSet(9)) && (mrs2_16.isBitClear(10)) ) + + + // If you have a 0 value in dram_rtt_nom_orignal + // you will use dram_rtt_nom_original to save the original value + if (io_dram_rtt_nom_original == 0) { - //RTT WR 60 OHM - // RTT_NOM set to 60 - dram_rtt_nom = 0x80; + io_dram_rtt_nom_original = dram_rtt_nom; + dram_rtt_nom = dram_rtt_wr; + + if (dram_rtt_wr == 0x00) + { + FAPI_INF( "DRAM_RTT_NOM to be set to DRAM_RTT_WR which is disable."); + } + else if (dram_rtt_wr == 0x80) + { + FAPI_INF( "DRAM_RTT_NOM to be set to DRAM_RTT_WR which is 60 Ohm."); + } + else if (dram_rtt_wr == 0x40) + { + FAPI_INF( "DRAM_RTT_NOM to be set to DRAM_RTT_WR which is 120 Ohm."); + } } - else if ( (mrs2_16.isBitClear(9)) && (mrs2_16.isBitSet(10)) ) + else if (io_dram_rtt_nom_original != 0) { - //RTT WR 120 OHM - // RTT_NOM set to 120 - dram_rtt_nom = 0x40; + dram_rtt_nom = io_dram_rtt_nom_original; + + if ( dram_rtt_nom == 0x00 ) + { + // RTT_NOM set to disabled + FAPI_INF( "DRAM_RTT_NOM being set back to Disabled."); + + } + else if ( dram_rtt_nom == 0x20 ) + { + // RTT_NOM set to 20 + FAPI_INF( "DRAM_RTT_NOM being set back to 20 Ohm."); + } + else if ( dram_rtt_nom == 0xA0 ) + { + // RTT_NOM set to 30 + FAPI_INF( "DRAM_RTT_NOM being set back to 30 Ohm."); + } + else if ( dram_rtt_nom == 0xC0 ) + { + // RTT_NOM set to 40 + FAPI_INF( "DRAM_RTT_NOM being set back to 40 Ohm."); + } + else if ( dram_rtt_nom == 0x80 ) + { + // RTT_NOM set to 60 + FAPI_INF( "DRAM_RTT_NOM being set back to 60 Ohm."); + } + else if ( dram_rtt_nom == 0x40 ) + { + // RTT_NOM set to 120 + FAPI_INF( "DRAM_RTT_NOM being set back to 120 Ohm."); + } } + rc_num = rc_num | mrs1_16.insert((uint8_t) dll_enable, 0, 1, 0); rc_num = rc_num | mrs1_16.insert((uint8_t) out_drv_imp_cntl, 1, 1, 0); rc_num = rc_num | mrs1_16.insert((uint8_t) dram_rtt_nom, 2, 1, 0); @@ -1322,61 +1428,55 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( rc_num = rc_num | mrs1_16.extractPreserve(&MRS1, 0, 16, 0); FAPI_INF( "NEW MRS 1: 0x%04X", MRS1); - rc_num = rc_num | address_16.insert(mrs1_16, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 2, 1, 5); + // Copying the current MRS into address buffer matching the MRS_array order + // Setting the bank address - if (rc_num) + rc_num = rc_num | address_pre_AMM_16.insert(mrs1_16, 0, 16, 0); + rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS1_BA, 0, 1, 7); + rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS1_BA, 1, 1, 6); + rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS1_BA, 2, 1, 5); + + if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_CDIMM) && (i_rank > 3) && (is_sim == 0)) { - FAPI_ERR( "mss_mrs_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } + FAPI_INF( "MUST USE ADDRESS MIRRORING ON PORT%d RANK%d", i_port_number, i_rank); - // Send out to the CCS array - rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); - if(rc) return rc; - rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); - if(rc) return rc; - io_ccs_inst_cnt++; + rc_num = rc_num | address_pre_AMM_16.extractPreserve(&mirror_mode_ad, 0, 16, 0); + FAPI_INF( "PRE - MIRROR MODE ADDRESS: 0x%04X", mirror_mode_ad); + rc_num = rc_num | bank_pre_AMM_3.extractPreserve(&mirror_mode_ba, 0, 3, 0); + FAPI_INF( "PRE - MIRROR MODE BANK ADDRESS: 0x%04X", mirror_mode_ba); + //Initialize address and bank address as the same pre mirror mode swizzle + rc_num = rc_num | address_16.insert(address_pre_AMM_16, 0, 16, 0); + rc_num = rc_num | bank_3.insert(bank_pre_AMM_3, 0, 3, 0); - rc_num = rc_num | mrs2_16.insert((uint8_t) pt_arr_sr, 0, 3); - rc_num = rc_num | mrs2_16.insert((uint8_t) cwl, 3, 3); - rc_num = rc_num | mrs2_16.insert((uint8_t) auto_sr, 6, 1); - rc_num = rc_num | mrs2_16.insert((uint8_t) sr_temp, 7, 1); - rc_num = rc_num | mrs2_16.insert((uint8_t) 0x00, 8, 1); - rc_num = rc_num | mrs2_16.insert((uint8_t) dram_rtt_wr, 9, 2); - rc_num = rc_num | mrs2_16.insert((uint8_t) 0x00, 10, 6); + //Swap A3 and A4 + rc_num = rc_num | address_16.insert(address_pre_AMM_16, 4, 1, 3); + rc_num = rc_num | address_16.insert(address_pre_AMM_16, 3, 1, 4); - rc_num = rc_num | mrs2_16.extractPreserve(&MRS2, 0, 16, 0); - FAPI_INF( "NEW MRS 2: 0x%04X", MRS2); + //Swap A5 and A6 + rc_num = rc_num | address_16.insert(address_pre_AMM_16, 6, 1, 5); + rc_num = rc_num | address_16.insert(address_pre_AMM_16, 5, 1, 6); + + //Swap A7 and A8 + rc_num = rc_num | address_16.insert(address_pre_AMM_16, 8, 1, 7); + rc_num = rc_num | address_16.insert(address_pre_AMM_16, 7, 1, 8); - rc_num = rc_num | address_16.insert(mrs2_16, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 0, 1, 7); - rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 1, 1, 6); - rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 2, 1, 5); + //Swap BA0 and BA1 + rc_num = rc_num | bank_3.insert(bank_pre_AMM_3, 1, 1, 0); + rc_num = rc_num | bank_3.insert(bank_pre_AMM_3, 0, 1, 1); + + rc_num = rc_num | address_16.extractPreserve(&mirror_mode_ad, 0, 16, 0); + FAPI_INF( "POST - MIRROR MODE ADDRESS: 0x%04X", mirror_mode_ad); + rc_num = rc_num | bank_3.extractPreserve(&mirror_mode_ba, 0, 3, 0); + FAPI_INF( "POST - MIRROR MODE BANK ADDRESS: 0x%04X", mirror_mode_ba); + + } + else + { + // No need to worry about swizzle + rc_num = rc_num | address_16.insert(address_pre_AMM_16, 0, 16, 0); + rc_num = rc_num | bank_3.insert(bank_pre_AMM_3, 0, 3, 0); + } if (rc_num) { @@ -1385,6 +1485,8 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( return rc_buff; } + ccs_end_1.setBit(0); + // Send out to the CCS array rc = mss_ccs_inst_arry_0( i_target, io_ccs_inst_cnt, @@ -1410,7 +1512,12 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( ddr_cal_enable_1, ccs_end_1); if(rc) return rc; - io_ccs_inst_cnt++; + + uint32_t NUM_POLL = 100; + rc = mss_execute_ccs_inst_array( i_target, NUM_POLL, 60); + if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs + + io_ccs_inst_cnt = 0; return rc; diff --git a/src/usr/hwpf/hwp/dram_training/mss_unmask_errors.C b/src/usr/hwpf/hwp/dram_training/mss_unmask_errors.C deleted file mode 100644 index 5efa72815..000000000 --- a/src/usr/hwpf/hwp/dram_training/mss_unmask_errors.C +++ /dev/null @@ -1,2743 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_unmask_errors.C $ */ -/* */ -/* IBM CONFIDENTIAL */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ -/* */ -/* p1 */ -/* */ -/* Object Code Only (OCO) source materials */ -/* Licensed Internal Code Source Materials */ -/* IBM HostBoot Licensed Internal Code */ -/* */ -/* The source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* */ -/* Origin: 30 */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_unmask_errors.C,v 1.1 2012/09/05 21:04:52 gollub Exp $ -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Date: | Author: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.1 | 09/05/12 | gollub | Created - - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include <mss_unmask_errors.H> -#include <cen_scom_addresses.H> -using namespace fapi; - - -//------------------------------------------------------------------------------ -// Constants and enums -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// mss_unmask_inband_errors -//------------------------------------------------------------------------------ - -fapi::ReturnCode mss_unmask_inband_errors( const fapi::Target & i_target, - fapi::ReturnCode i_bad_rc ) - -{ - - FAPI_INF("ENTER mss_unmask_inband_errors()"); - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - - //************************* - //************************* - // MBS_FIR_REG - //************************* - //************************* - - ecmdDataBufferBase l_mbs_fir_mask(64); - ecmdDataBufferBase l_mbs_fir_mask_or(64); - ecmdDataBufferBase l_mbs_fir_mask_and(64); - ecmdDataBufferBase l_mbs_fir_action0(64); - ecmdDataBufferBase l_mbs_fir_action1(64); - - // Read mask - l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_MASK_REG_0x02011403, l_mbs_fir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_mbs_fir_action0.flushTo0(); - l_ecmd_rc |= l_mbs_fir_action1.flushTo0(); - l_ecmd_rc |= l_mbs_fir_mask_or.flushTo0(); - l_ecmd_rc |= l_mbs_fir_mask_and.flushTo1(); - - // 0 host_protocol_error channel checkstop unmask - l_ecmd_rc |= l_mbs_fir_action0.clearBit(0); - l_ecmd_rc |= l_mbs_fir_action1.clearBit(0); - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(0); - - // 1 int_protocol_error channel checkstop unmask - l_ecmd_rc |= l_mbs_fir_action0.clearBit(1); - l_ecmd_rc |= l_mbs_fir_action1.clearBit(1); - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(1); - - // 2 invalid_address_error channel checkstop mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(2); - l_ecmd_rc |= l_mbs_fir_action1.clearBit(2); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(2); - - // 3 external_timeout channel checkstop mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(3); - l_ecmd_rc |= l_mbs_fir_action1.clearBit(3); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(3); - - // 4 internal_timeout channel checkstop mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(4); - l_ecmd_rc |= l_mbs_fir_action1.clearBit(4); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(4); - - // 5 int_buffer_ce recoverable unmask - l_ecmd_rc |= l_mbs_fir_action0.clearBit(5); - l_ecmd_rc |= l_mbs_fir_action1.setBit(5); - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(5); - - // 6 int_buffer_ue recoverable unmask - l_ecmd_rc |= l_mbs_fir_action0.clearBit(6); - l_ecmd_rc |= l_mbs_fir_action1.setBit(6); - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(6); - - // 7 int_buffer_sue recoverable mask (forever) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(7); - l_ecmd_rc |= l_mbs_fir_action1.setBit(7); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(7); - - // 8 int_parity_error channel checkstop unmask - l_ecmd_rc |= l_mbs_fir_action0.clearBit(8); - l_ecmd_rc |= l_mbs_fir_action1.clearBit(8); - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(8); - - // 9 cache_srw_ce recoverable mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(9); - l_ecmd_rc |= l_mbs_fir_action1.setBit(9); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(9); - - // 10 cache_srw_ue recoverable mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(10); - l_ecmd_rc |= l_mbs_fir_action1.setBit(10); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(10); - - // 11 cache_srw_sue recoverable mask (forever) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(11); - l_ecmd_rc |= l_mbs_fir_action1.setBit(11); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(11); - - // 12 cache_co_ce recoverable mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(12); - l_ecmd_rc |= l_mbs_fir_action1.setBit(12); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(12); - - // 13 cache_co_ue recoverable mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(13); - l_ecmd_rc |= l_mbs_fir_action1.setBit(13); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(13); - - // 14 cache_co_sue recoverable mask (forever) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(14); - l_ecmd_rc |= l_mbs_fir_action1.setBit(14); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(14); - - // 15 dir_ce recoverable mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(15); - l_ecmd_rc |= l_mbs_fir_action1.setBit(15); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(15); - - // 16 dir_ue channel checkstop mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(16); - l_ecmd_rc |= l_mbs_fir_action1.clearBit(16); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(16); - - // 17 dir_member_deleted recoverable mask (forever) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(17); - l_ecmd_rc |= l_mbs_fir_action1.setBit(17); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(17); - - // 18 dir_all_members_deleted channel checkstop mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(18); - l_ecmd_rc |= l_mbs_fir_action1.clearBit(18); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(18); - - // 19 lru_error recoverable mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(19); - l_ecmd_rc |= l_mbs_fir_action1.setBit(19); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(19); - - // 20 eDRAM error channel checkstop mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(20); - l_ecmd_rc |= l_mbs_fir_action1.clearBit(20); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(20); - - // 21 emergency_throttle_set recoverable mask (forever) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(21); - l_ecmd_rc |= l_mbs_fir_action1.setBit(21); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(21); - - // 22 Host Inband Read Error recoverable mask (forever) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(22); - l_ecmd_rc |= l_mbs_fir_action1.setBit(22); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(22); - - // 23 Host Inband Write Error recoverable mask (forever) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(23); - l_ecmd_rc |= l_mbs_fir_action1.setBit(23); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(23); - - // 24 OCC Inband Read Error recoverable mask (forever) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(24); - l_ecmd_rc |= l_mbs_fir_action1.setBit(24); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(24); - - // 25 OCC Inband Write Error recoverable mask (forever) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(25); - l_ecmd_rc |= l_mbs_fir_action1.setBit(25); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(25); - - // 26 srb_buffer_ce recoverable mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(26); - l_ecmd_rc |= l_mbs_fir_action1.setBit(26); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(26); - - // 27 srb_buffer_ue recoverable mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(27); - l_ecmd_rc |= l_mbs_fir_action1.setBit(27); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(27); - - // 28 srb_buffer_sue recoverable mask (forever) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(28); - l_ecmd_rc |= l_mbs_fir_action1.setBit(28); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(28); - - // 29 internal_scom_error recoverable mask (tbd) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(29); - l_ecmd_rc |= l_mbs_fir_action1.setBit(29); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(29); - - // 30 internal_scom_error_copy recoverable mask (tbd) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(30); - l_ecmd_rc |= l_mbs_fir_action1.setBit(30); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(30); - - // 31:63 Reserved not implemented, so won't touch these - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write action0 - l_rc = fapiPutScom_w_retry(i_target, MBS_FIR_ACTION0_REG_0x02011406, l_mbs_fir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write action1 - l_rc = fapiPutScom_w_retry(i_target, MBS_FIR_ACTION1_REG_0x02011407, l_mbs_fir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - // Write mask OR - l_rc = fapiPutScom_w_retry(i_target, MBS_FIR_MASK_REG_OR_0x02011405, l_mbs_fir_mask_or); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, MBS_FIR_MASK_REG_AND_0x02011404, l_mbs_fir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_ACTION0_REG_0x02011406, l_mbs_fir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_ACTION1_REG_0x02011407, l_mbs_fir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_MASK_REG_0x02011403, l_mbs_fir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - - FAPI_INF("EXIT mss_unmask_inband_errors()"); - - return i_bad_rc; -} - - - -//------------------------------------------------------------------------------ -// mss_unmask_ddrphy_errors -//------------------------------------------------------------------------------ - -fapi::ReturnCode mss_unmask_ddrphy_errors( const fapi::Target & i_target, - fapi::ReturnCode i_bad_rc ) - -{ - - FAPI_INF("ENTER mss_unmask ddrphy_errors()"); - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - - //************************* - //************************* - // DDRPHY_FIR_REG - //************************* - //************************* - - ecmdDataBufferBase l_ddrphy_fir_mask(64); - ecmdDataBufferBase l_ddrphy_fir_mask_or(64); - ecmdDataBufferBase l_ddrphy_fir_mask_and(64); - ecmdDataBufferBase l_ddrphy_fir_action0(64); - ecmdDataBufferBase l_ddrphy_fir_action1(64); - - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_ddrphy_fir_action0.flushTo0(); - l_ecmd_rc |= l_ddrphy_fir_action1.flushTo0(); - l_ecmd_rc |= l_ddrphy_fir_mask_or.flushTo0(); - l_ecmd_rc |= l_ddrphy_fir_mask_and.flushTo0(); - l_ecmd_rc |= l_ddrphy_fir_mask_and.setBit(48,16); - - // 0:47 Reserved not implemented, so won't touch these - - // 48 ddr0_fsm_ckstp channel checkstop unmask - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(48); - l_ecmd_rc |= l_ddrphy_fir_action1.clearBit(48); - l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(48); - - // 49 ddr0_parity_ckstp channel checkstop unmask - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(49); - l_ecmd_rc |= l_ddrphy_fir_action1.clearBit(49); - l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(49); - - // 50 ddr0_calibration_error recoverable mask (forever) - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(50); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(50); - l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(50); - - // 51 ddr0_fsm_err recoverable unmask - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(51); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(51); - l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(51); - - // 52 ddr0_parity_err recoverable unmask - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(52); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(52); - l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(52); - - // 53 ddr01_fir_parity_err recoverable mask (forever) - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(53); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(53); - l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(53); - - // 54 Reserved recoverable mask (forever) - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(54); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(54); - l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(54); - - // 55 Reserved recoverable mask (forever) - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(55); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(55); - l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(55); - - // 56 ddr1_fsm_ckstp channel checkstop unmask - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(56); - l_ecmd_rc |= l_ddrphy_fir_action1.clearBit(56); - l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(56); - - // 57 ddr1_parity_ckstp channel checkstop unmask - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(57); - l_ecmd_rc |= l_ddrphy_fir_action1.clearBit(57); - l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(57); - - // 58 ddr1_calibration_error recoverable mask (forever) - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(58); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(58); - l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(58); - - // 59 ddr1_fsm_err recoverable unmask - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(59); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(59); - l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(59); - - // 60 ddr1_parity_err recoverable unmask - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(60); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(60); - l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(60); - - // 61 Reserved recoverable mask (forever) - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(61); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(61); - l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(61); - - // 62 Reserved recoverable mask (forever) - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(62); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(62); - l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(62); - - // 63 Reserved recoverable mask (forever) - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(63); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(63); - l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(63); - - - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write action0 - l_rc = fapiPutScom_w_retry(i_target, PHY01_DDRPHY_FIR_ACTION0_REG_0x800200960301143f, l_ddrphy_fir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write action1 - l_rc = fapiPutScom_w_retry(i_target, PHY01_DDRPHY_FIR_ACTION1_REG_0x800200970301143f, l_ddrphy_fir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - // Write mask OR - l_rc = fapiPutScom_w_retry(i_target, PHY01_DDRPHY_FIR_MASK_REG_OR_0x800200950301143f, l_ddrphy_fir_mask_or); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, PHY01_DDRPHY_FIR_MASK_REG_AND_0x800200940301143f, l_ddrphy_fir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(i_target, PHY01_DDRPHY_FIR_ACTION0_REG_0x800200960301143f, l_ddrphy_fir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - l_rc = fapiGetScom_w_retry(i_target, PHY01_DDRPHY_FIR_ACTION1_REG_0x800200970301143f, l_ddrphy_fir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - l_rc = fapiGetScom_w_retry(i_target, PHY01_DDRPHY_FIR_MASK_REG_0x800200930301143f, l_ddrphy_fir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - - //************************* - //************************* - // MBAFIR - //************************* - //************************* - - ecmdDataBufferBase l_mbafir_mask(64); - ecmdDataBufferBase l_mbafir_mask_or(64); - ecmdDataBufferBase l_mbafir_mask_and(64); - ecmdDataBufferBase l_mbafir_action0(64); - ecmdDataBufferBase l_mbafir_action1(64); - - - // Read mask - l_rc = fapiGetScom_w_retry(i_target, - MBA01_MBAFIRMASK_0x03010603, - l_mbafir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_mbafir_action0.flushTo0(); - l_ecmd_rc |= l_mbafir_action1.flushTo0(); - l_ecmd_rc |= l_mbafir_mask_or.flushTo0(); - l_ecmd_rc |= l_mbafir_mask_and.flushTo1(); - - - // 0 Invalid_Maint_Cmd recoverable masked (forever) - l_ecmd_rc |= l_mbafir_action0.clearBit(0); - l_ecmd_rc |= l_mbafir_action1.setBit(0); - l_ecmd_rc |= l_mbafir_mask_or.setBit(0); - - // 1 Invalid_Maint_Address recoverable masked (forever) - l_ecmd_rc |= l_mbafir_action0.clearBit(1); - l_ecmd_rc |= l_mbafir_action1.setBit(1); - l_ecmd_rc |= l_mbafir_mask_or.setBit(1); - - // 2 Multi_address_Maint_timeout recoverable masked (until mss_unmask_maint_errors) - l_ecmd_rc |= l_mbafir_action0.clearBit(2); - l_ecmd_rc |= l_mbafir_action1.setBit(2); - l_ecmd_rc |= l_mbafir_mask_or.setBit(2); - - // 3 Internal_fsm_error recoverable unmask - l_ecmd_rc |= l_mbafir_action0.clearBit(3); - l_ecmd_rc |= l_mbafir_action1.setBit(3); - l_ecmd_rc |= l_mbafir_mask_and.clearBit(3); - - // 4 MCBIST_Error recoverable mask (forever) - l_ecmd_rc |= l_mbafir_action0.clearBit(4); - l_ecmd_rc |= l_mbafir_action1.setBit(4); - l_ecmd_rc |= l_mbafir_mask_or.setBit(4); - - // 5 scom_cmd_reg_pe recoverable unmask - l_ecmd_rc |= l_mbafir_action0.clearBit(5); - l_ecmd_rc |= l_mbafir_action1.setBit(5); - l_ecmd_rc |= l_mbafir_mask_and.clearBit(5); - - // 6 channel_chkstp_err channel checkstop unmask - l_ecmd_rc |= l_mbafir_action0.clearBit(6); - l_ecmd_rc |= l_mbafir_action1.clearBit(6); - l_ecmd_rc |= l_mbafir_mask_and.clearBit(6); - - // 7 wrd_caw2_data_ce_ue_err recoverable masked (until mss_unmask_maint_errors) - l_ecmd_rc |= l_mbafir_action0.clearBit(7); - l_ecmd_rc |= l_mbafir_action1.setBit(7); - l_ecmd_rc |= l_mbafir_mask_or.setBit(7); - - // 8:14 RESERVED recoverable mask (forever) - l_ecmd_rc |= l_mbafir_action0.clearBit(8,7); - l_ecmd_rc |= l_mbafir_action1.setBit(8,7); - l_ecmd_rc |= l_mbafir_mask_or.setBit(8,7); - - // 15 internal scom error recoverable mask (tbd) - l_ecmd_rc |= l_mbafir_action0.clearBit(15); - l_ecmd_rc |= l_mbafir_action1.setBit(15); - l_ecmd_rc |= l_mbafir_mask_or.setBit(15); - - // 16 internal scom error clone recoverable mask (tbd) - l_ecmd_rc |= l_mbafir_action0.clearBit(16); - l_ecmd_rc |= l_mbafir_action1.setBit(16); - l_ecmd_rc |= l_mbafir_mask_or.setBit(16); - - - // 17:63 RESERVED not implemented, so won't touch these - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write action0 - l_rc = fapiPutScom_w_retry(i_target, - MBA01_MBAFIRACT0_0x03010606, - l_mbafir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write action1 - l_rc = fapiPutScom_w_retry(i_target, - MBA01_MBAFIRACT1_0x03010607, - l_mbafir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - // Write mask OR - l_rc = fapiPutScom_w_retry(i_target, - MBA01_MBAFIRMASK_OR_0x03010605, - l_mbafir_mask_or); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, - MBA01_MBAFIRMASK_AND_0x03010604, - l_mbafir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(i_target, - MBA01_MBAFIRACT0_0x03010606, - l_mbafir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - l_rc = fapiGetScom_w_retry(i_target, - MBA01_MBAFIRACT1_0x03010607, - l_mbafir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - l_rc = fapiGetScom_w_retry(i_target, - MBA01_MBAFIRMASK_0x03010603, - l_mbafir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - - FAPI_INF("EXIT mss_unmask_ddrphy_errors()"); - - return i_bad_rc; -} - - -//------------------------------------------------------------------------------ -// mss_unmask_draminit_errors -//------------------------------------------------------------------------------ - -fapi::ReturnCode mss_unmask_draminit_errors( const fapi::Target & i_target, - fapi::ReturnCode i_bad_rc ) - -{ - - FAPI_INF("ENTER mss_unmask_draminit_errors()"); - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - - //************************* - //************************* - // MBACALFIR - //************************* - //************************* - - ecmdDataBufferBase l_mbacalfir_mask(64); - ecmdDataBufferBase l_mbacalfir_mask_or(64); - ecmdDataBufferBase l_mbacalfir_mask_and(64); - ecmdDataBufferBase l_mbacalfir_action0(64); - ecmdDataBufferBase l_mbacalfir_action1(64); - - - // Read mask - l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_mbacalfir_action0.flushTo0(); - l_ecmd_rc |= l_mbacalfir_action1.flushTo0(); - l_ecmd_rc |= l_mbacalfir_mask_or.flushTo0(); - l_ecmd_rc |= l_mbacalfir_mask_and.flushTo1(); - - // 0 MBA Recoverable Error recoverable mask - l_ecmd_rc |= l_mbacalfir_action0.clearBit(0); - l_ecmd_rc |= l_mbacalfir_action1.setBit(0); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(0); - - // 1 MBA Nonrecoverable Error channel checkstop mask - l_ecmd_rc |= l_mbacalfir_action0.clearBit(1); - l_ecmd_rc |= l_mbacalfir_action1.clearBit(1); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(1); - - // 2 Refresh Overrun recoverable mask - l_ecmd_rc |= l_mbacalfir_action0.clearBit(2); - l_ecmd_rc |= l_mbacalfir_action1.setBit(2); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(2); - - // 3 WAT error recoverable mask (forever) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(3); - l_ecmd_rc |= l_mbacalfir_action1.setBit(3); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(3); - - // 4 RCD Parity Error 0 recoverable unmask (only if set) - // TODO: Unmask, only if set, only if ISD DIMM - l_ecmd_rc |= l_mbacalfir_action0.clearBit(4); - l_ecmd_rc |= l_mbacalfir_action1.setBit(4); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(4); - - // 5 ddr0_cal_timeout_err recoverable mask - l_ecmd_rc |= l_mbacalfir_action0.clearBit(5); - l_ecmd_rc |= l_mbacalfir_action1.setBit(5); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(5); - - // 6 ddr1_cal_timeout_err recoverable mask - l_ecmd_rc |= l_mbacalfir_action0.clearBit(6); - l_ecmd_rc |= l_mbacalfir_action1.setBit(6); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(6); - - // 7 RCD Parity Error 1 recoverable unmask (only if set) - // TODO: Unmask, only if set, only if ISD DIMM - l_ecmd_rc |= l_mbacalfir_action0.clearBit(7); - l_ecmd_rc |= l_mbacalfir_action1.setBit(7); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(7); - - - // 8 mbx to mba par error channel checkstop mask - l_ecmd_rc |= l_mbacalfir_action0.clearBit(8); - l_ecmd_rc |= l_mbacalfir_action1.clearBit(8); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(8); - - // 9 mba_wrd ue recoverable mask - l_ecmd_rc |= l_mbacalfir_action0.clearBit(9); - l_ecmd_rc |= l_mbacalfir_action1.setBit(9); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(9); - - // 10 mba_wrd ce recoverable mask - l_ecmd_rc |= l_mbacalfir_action0.clearBit(10); - l_ecmd_rc |= l_mbacalfir_action1.setBit(10); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(10); - - // 11 mba_maint ue recoverable mask - l_ecmd_rc |= l_mbacalfir_action0.clearBit(11); - l_ecmd_rc |= l_mbacalfir_action1.setBit(11); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(11); - - // 12 mba_maint ce recoverable mask - l_ecmd_rc |= l_mbacalfir_action0.clearBit(12); - l_ecmd_rc |= l_mbacalfir_action1.setBit(12); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(12); - - // 13 ddr_cal_reset_timeout channel checkstop mask - // TODO: Leaving masked until I find proper spot to unmask this - l_ecmd_rc |= l_mbacalfir_action0.clearBit(13); - l_ecmd_rc |= l_mbacalfir_action1.clearBit(13); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(13); - - // 14 wrq_data_ce recoverable mask - l_ecmd_rc |= l_mbacalfir_action0.clearBit(14); - l_ecmd_rc |= l_mbacalfir_action1.setBit(14); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(14); - - // 15 wrq_data_ue recoverable mask - l_ecmd_rc |= l_mbacalfir_action0.clearBit(15); - l_ecmd_rc |= l_mbacalfir_action1.setBit(15); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(15); - - // 16 wrq_data_sue recoverable mask - l_ecmd_rc |= l_mbacalfir_action0.clearBit(16); - l_ecmd_rc |= l_mbacalfir_action1.setBit(16); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(16); - - // 17 wrq_rrq_hang_err recoverable mask - l_ecmd_rc |= l_mbacalfir_action0.clearBit(17); - l_ecmd_rc |= l_mbacalfir_action1.setBit(17); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(17); - - // 18 sm_1hot_err recoverable unmask - l_ecmd_rc |= l_mbacalfir_action0.clearBit(18); - l_ecmd_rc |= l_mbacalfir_action1.setBit(18); - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(18); - - // 19 wrd_scom_error recoverable mask (tbd) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(19); - l_ecmd_rc |= l_mbacalfir_action1.setBit(19); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(19); - - // 20 internal_scom_error recoverable mask (tbd) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(20); - l_ecmd_rc |= l_mbacalfir_action1.setBit(20); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(20); - - // 21 internal_scom_error_copy recoverable mask (tbd) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(21); - l_ecmd_rc |= l_mbacalfir_action1.setBit(21); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(21); - - // 22-63 Reserved not implemented, so won't touch these - - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write action0 - l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_ACTION0_0x03010406, l_mbacalfir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write action1 - l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_ACTION1_0x03010407, l_mbacalfir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - // Write mask OR - l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_MASK_OR_0x03010405, l_mbacalfir_mask_or); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_MASK_AND_0x03010404, l_mbacalfir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_ACTION0_0x03010406, l_mbacalfir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_ACTION1_0x03010407, l_mbacalfir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - - FAPI_INF("EXIT mss_unmask_draminit_errors()"); - - return i_bad_rc; -} - - -//------------------------------------------------------------------------------ -// mss_unmask_draminit_training_errors -//------------------------------------------------------------------------------ - -fapi::ReturnCode mss_unmask_draminit_training_errors( - const fapi::Target & i_target, - fapi::ReturnCode i_bad_rc ) - -{ - - FAPI_INF("ENTER mss_unmask_draminit_training_errors()"); - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - - //************************* - //************************* - // MBACALFIR - //************************* - //************************* - - ecmdDataBufferBase l_mbacalfir_mask(64); - ecmdDataBufferBase l_mbacalfir_mask_and(64); - - // NOTE: In the IPL sequence, mss_unmask_draminit_errors has already been - // called, which has already set the MBACALFIR action regs to their runtime - // values, so no need to touch the action regs here. - - // NOTE: In the IPL sequence, mss_unmask_draminit_errors has already been - // called, which has already unmasked the approproiate MBACALFIR errors - // following mss_draminit. So all we will do here is unmask a few more - // errors that would be considered valid after the mss_draminit_training - // procedure. - - - // Read mask - l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_mbacalfir_mask_and.flushTo1(); - - // 0 MBA Recoverable Error recoverable umask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(0); - - // 4 RCD Parity Error 0 recoverable unmask (only if set) - // TODO: Unmask, only if set, only if ISD DIMM - - // 7 RCD Parity Error 1 recoverable unmask (only if set) - // TODO: Unmask, only if set, only if ISD DIMM - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_MASK_AND_0x03010404, l_mbacalfir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - - FAPI_INF("EXIT mss_unmask_draminit_training_errors()"); - - return i_bad_rc; -} - - -//------------------------------------------------------------------------------ -// mss_unmask_draminit_training_advanced_errors -//------------------------------------------------------------------------------ - -fapi::ReturnCode mss_unmask_draminit_training_advanced_errors( - const fapi::Target & i_target, - fapi::ReturnCode i_bad_rc ) - -{ - - FAPI_INF("ENTER mss_unmask_draminit_training_advanced_errors()"); - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - - //************************* - //************************* - // MBACALFIR - //************************* - //************************* - - ecmdDataBufferBase l_mbacalfir_mask(64); - ecmdDataBufferBase l_mbacalfir_mask_and(64); - - // NOTE: In the IPL sequence, mss_unmask_draminit_errors has already been - // called, which has already set the MBACALFIR action regs to their runtime - // values, so no need to touch the action regs here. - - // NOTE: In the IPL sequence, mss_unmask_draminit_errors and - // mss_unmask_draminit_training has already been - // called, which has already unmasked the approproiate MBACALFIR errors - // following mss_draminit and mss_draminit_training. So all we will do here - // is unmask a few more errors that would be considered valid after the - // mss_draminit_training_advanced procedure. - - - // Read mask - l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_mbacalfir_mask_and.flushTo1(); - - // 4 RCD Parity Error 0 recoverable unmask - // TODO: Unmask, only if ISD DIMM - - // 7 RCD Parity Error 1 recoverable unmask - // TODO: Unmask, only if ISD DIMM - - // 8 mbx to mba par error channel checkstop unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(8); - - // 11 mba_maint ue recoverable unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(11); - - // 12 mba_maint ce recoverable unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(12); - - // 17 wrq_rrq_hang_err recoverable unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(17); - - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_MASK_AND_0x03010404, l_mbacalfir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - - //************************* - //************************* - // MBSFIR - //************************* - //************************* - - fapi::Target l_targetCentaur; - uint8_t l_mbaPosition; // 0 = mba01, 1 = mba23 - - uint32_t l_mbsfir_mask_address[2]={ - // port0/1 port2/3 - MBS01_MBSFIRMASK_0x02011603, MBS23_MBSFIRMASK_0x02011703}; - - uint32_t l_mbsfir_mask_or_address[2]={ - // port0/1 port2/3 - MBS01_MBSFIRMASK_OR_0x02011605, MBS23_MBSFIRMASK_OR_0x02011705}; - - uint32_t l_mbsfir_mask_and_address[2]={ - // port0/1 port2/3 - MBS01_MBSFIRMASK_AND_0x02011604, MBS23_MBSFIRMASK_AND_0x02011704}; - - uint32_t l_mbsfir_action0_address[2]={ - // port0/1 port2/3 - MBS01_MBSFIRACT0_0x02011606, MBS23_MBSFIRACT0_0x02011706}; - - uint32_t l_mbsfir_action1_address[2]={ - // port0/1 port2/3 - MBS01_MBSFIRACT1_0x02011607, MBS23_MBSFIRACT1_0x02011707}; - - ecmdDataBufferBase l_mbsfir_mask(64); - ecmdDataBufferBase l_mbsfir_mask_or(64); - ecmdDataBufferBase l_mbsfir_mask_and(64); - ecmdDataBufferBase l_mbsfir_action0(64); - ecmdDataBufferBase l_mbsfir_action1(64); - - // Get Centaur target for the given MBA - l_rc = fapiGetParentChip(i_target, l_targetCentaur); - if(l_rc) - { - FAPI_ERR("Error getting Centaur parent target for the given MBA"); - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Get MBA position: 0 = mba01, 1 = mba23 - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbaPosition); - if(l_rc) - { - FAPI_ERR("Error getting MBA position"); - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Read mask - l_rc = fapiGetScom_w_retry(l_targetCentaur, - l_mbsfir_mask_address[l_mbaPosition], - l_mbsfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_mbsfir_action0.flushTo0(); - l_ecmd_rc |= l_mbsfir_action1.flushTo0(); - l_ecmd_rc |= l_mbsfir_mask_or.flushTo0(); - l_ecmd_rc |= l_mbsfir_mask_and.flushTo1(); - - // 0 scom_par_errors recoverable unmask - l_ecmd_rc |= l_mbsfir_action0.clearBit(0); - l_ecmd_rc |= l_mbsfir_action1.setBit(0); - l_ecmd_rc |= l_mbsfir_mask_and.clearBit(0); - - // 1 mbx_par_errors channel checkstop unmask - l_ecmd_rc |= l_mbsfir_action0.clearBit(1); - l_ecmd_rc |= l_mbsfir_action1.clearBit(1); - l_ecmd_rc |= l_mbsfir_mask_and.clearBit(1); - - // 2:14 RESERVED recoverable mask (forever) - l_ecmd_rc |= l_mbsfir_action0.clearBit(2,13); - l_ecmd_rc |= l_mbsfir_action1.setBit(2,13); - l_ecmd_rc |= l_mbsfir_mask_or.setBit(2,13); - - // 15 internal scom error recoverable mask (tbd) - l_ecmd_rc |= l_mbsfir_action0.clearBit(15); - l_ecmd_rc |= l_mbsfir_action1.setBit(15); - l_ecmd_rc |= l_mbsfir_mask_or.setBit(15); - - // 16 internal scom error clone recoverable mask (tbd) - l_ecmd_rc |= l_mbsfir_action0.clearBit(16); - l_ecmd_rc |= l_mbsfir_action1.setBit(16); - l_ecmd_rc |= l_mbsfir_mask_or.setBit(16); - - // 17:63 RESERVED not implemented, so won't touch these - - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write action0 - l_rc = fapiPutScom_w_retry(l_targetCentaur, - l_mbsfir_action0_address[l_mbaPosition], - l_mbsfir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write action1 - l_rc = fapiPutScom_w_retry(l_targetCentaur, - l_mbsfir_action1_address[l_mbaPosition], - l_mbsfir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - // Write mask OR - l_rc = fapiPutScom_w_retry(l_targetCentaur, - l_mbsfir_mask_or_address[l_mbaPosition], - l_mbsfir_mask_or); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - // Write mask AND - l_rc = fapiPutScom_w_retry(l_targetCentaur, - l_mbsfir_mask_and_address[l_mbaPosition], - l_mbsfir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(l_targetCentaur, - l_mbsfir_action0_address[l_mbaPosition], - l_mbsfir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - l_rc = fapiGetScom_w_retry(l_targetCentaur, - l_mbsfir_action1_address[l_mbaPosition], - l_mbsfir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - l_rc = fapiGetScom_w_retry(l_targetCentaur, - l_mbsfir_mask_address[l_mbaPosition], - l_mbsfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - - FAPI_INF("EXIT mss_unmask_draminit_training_advanced_errors()"); - - return i_bad_rc; -} - - - -//------------------------------------------------------------------------------ -// mss_unmask_maint_errors -//------------------------------------------------------------------------------ - -fapi::ReturnCode mss_unmask_maint_errors(const fapi::Target & i_target, - fapi::ReturnCode i_bad_rc ) - -{ - - // Target: Centaur - - FAPI_INF("ENTER mss_unmask_maint_errors()"); - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - std::vector<fapi::Target> l_mbaChiplets; - uint8_t l_mbaPosition; // 0 = mba01, 1 = mba23 - - ecmdDataBufferBase l_mbacalfir_mask(64); - ecmdDataBufferBase l_mbacalfir_mask_and(64); - - ecmdDataBufferBase l_mbafir_mask(64); - ecmdDataBufferBase l_mbafir_mask_and(64); - - ecmdDataBufferBase l_mbaspa_mask(64); - - uint32_t l_mbeccfir_mask_address[2]={ - // port0/1 port2/3 - MBS_ECC0_MBECCFIR_MASK_0x02011443, MBS_ECC1_MBECCFIR_MASK_0x02011483}; - - uint32_t l_mbeccfir_mask_or_address[2]={ - // port0/1 port2/3 - MBS_ECC0_MBECCFIR_MASK_OR_0x02011445, MBS_ECC1_MBECCFIR_MASK_OR_0x02011485}; - - uint32_t l_mbeccfir_mask_and_address[2]={ - // port0/1 port2/3 - MBS_ECC0_MBECCFIR_MASK_AND_0x02011444,MBS_ECC1_MBECCFIR_MASK_AND_0x02011484}; - - uint32_t l_mbeccfir_action0_address[2]={ - // port0/1 port2/3 - MBS_ECC0_MBECCFIR_ACTION0_0x02011446, MBS_ECC1_MBECCFIR_ACTION0_0x02011486}; - - uint32_t l_mbeccfir_action1_address[2]={ - // port0/1 port2/3 - MBS_ECC0_MBECCFIR_ACTION1_0x02011447, MBS_ECC1_MBECCFIR_ACTION1_0x02011487}; - - ecmdDataBufferBase l_mbeccfir_mask(64); - ecmdDataBufferBase l_mbeccfir_mask_or(64); - ecmdDataBufferBase l_mbeccfir_mask_and(64); - ecmdDataBufferBase l_mbeccfir_action0(64); - ecmdDataBufferBase l_mbeccfir_action1(64); - - - - // Get associated functional MBAs on this centaur - l_rc = fapiGetChildChiplets(i_target, - fapi::TARGET_TYPE_MBA_CHIPLET, - l_mbaChiplets); - if(l_rc) - { - FAPI_ERR("Error getting functional MBAs on this Centaur"); - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Loop through functional MBAs on this Centaur - for (uint32_t i=0; i < l_mbaChiplets.size(); i++) - { - - // Get MBA position: 0 = mba01, 1 = mba23 - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_mbaChiplets[i], l_mbaPosition); - if(l_rc) - { - FAPI_ERR("Error getting MBA position"); - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - - - //************************* - //************************* - // MBACALFIR - //************************* - //************************* - - - // NOTE: In the IPL sequence, mss_unmask_draminit_errors has already been - // called, which has already set the MBACALFIR action regs to their runtime - // values, so no need to touch the action regs here. - - // NOTE: In the IPL sequence, mss_unmask_draminit_errors, - // mss_unmask_draminit_training and mss_unmask_draminit_training_advanced - // have already been called, which have already unmasked the approproiate - // MBACALFIR errors following mss_draminit, mss_draminit_training, and - // mss_unmask_draminit_training_advanced. So all we will do here - // is unmask a few more errors that would be considered valid after the - // mss_draminit_mc procedure. - - // Read mask - l_rc = fapiGetScom_w_retry(l_mbaChiplets[i], - MBA01_MBACALFIR_MASK_0x03010403, - l_mbacalfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_mbacalfir_mask_and.flushTo1(); - - // 1 MBA Nonrecoverable Error channel checkstop unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(1); - - // 2 Refresh Overrun recoverable unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(2); - - // 5 ddr0_cal_timeout_err recoverable unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(5); - - // 6 ddr1_cal_timeout_err recoverable unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(6); - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(l_mbaChiplets[i], - MBA01_MBACALFIR_MASK_AND_0x03010404, - l_mbacalfir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(l_mbaChiplets[i], - MBA01_MBACALFIR_MASK_0x03010403, - l_mbacalfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - - //************************* - //************************* - // MBAFIR - //************************* - //************************* - - // NOTE: In the IPL sequence, mss_unmask_ddr_phy_errors has already been - // called, which has already set the MBAFIR action regs to their runtime - // values, so no need to touch the action regs here. - - // NOTE: In the IPL sequence, mss_unmask_ddr_phy_errors, - // has already been called, which has already unmasked the approproiate - // MBAFIR errors following mss_ddr_phy_reset. So all we will do here - // is unmask a few more errors that would be considered valid after the - // mss_draminit_mc procedure. - - // Read mask - l_rc = fapiGetScom_w_retry(l_mbaChiplets[i], - MBA01_MBAFIRMASK_0x03010603, - l_mbafir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_mbafir_mask_and.flushTo1(); - - // 2 Multi_address_Maint_timeout recoverable unmask - l_ecmd_rc |= l_mbafir_mask_and.clearBit(2); - - - // 7 wrd_caw2_data_ce_ue_err recoverable unmask - l_ecmd_rc |= l_mbafir_mask_and.clearBit(7); - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(l_mbaChiplets[i], - MBA01_MBAFIRMASK_AND_0x03010604, - l_mbafir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(l_mbaChiplets[i], - MBA01_MBAFIRMASK_0x03010603, - l_mbafir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - - //************************* - //************************* - // MBASPA - //************************* - //************************* - - - // Read mask - l_rc = fapiGetScom_w_retry(l_mbaChiplets[i], - MBA01_MBSPAMSKQ_0x03010614, - l_mbaspa_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - // 0 Command_Complete masked (DD1 broken) - l_ecmd_rc |= l_mbaspa_mask.setBit(0); - - // 1 Hard_CE_ETE_Attn unmask - // NOTE: FW memdiags may want to mask this if they want to wait till - // cmd gets to end of rank before getting any attention. - // NOTE: Hards counted during super fast read, but can't be called - // true hard CEs since super fast read doesn't write back and read again. - l_ecmd_rc |= l_mbaspa_mask.clearBit(1); - - // 2 Soft_CE_ETE_Attn unmask - // NOTE: FW memdiags may want to mask this if they want to wait till - // cmd gets to end of rank before getting any attention. - // NOTE: Softs not counted during super fast read. - l_ecmd_rc |= l_mbaspa_mask.clearBit(2); - - // 3 Intermittent_ETE_Attn unmask - // NOTE: FW memdiags may want to mask this if they want to wait till - // cmd gets to end of rank before getting any attention. - // NOTE: Intermittents not counted during super fast read. - l_ecmd_rc |= l_mbaspa_mask.clearBit(3); - - // 4 RCE_ETE_Attn unmask - // NOTE: FW memdiags may want to mask this if they want to wait till - // cmd gets to end of rank before getting any attention. - l_ecmd_rc |= l_mbaspa_mask.clearBit(4); - - // 5 Emergency_Throttle_Attn masked - l_ecmd_rc |= l_mbaspa_mask.setBit(5); - - // 6 Firmware_Attn0 masked - l_ecmd_rc |= l_mbaspa_mask.setBit(6); - - // 7 Firmware_Attn1 masked - l_ecmd_rc |= l_mbaspa_mask.setBit(7); - - // 8 wat_debug_attn unmask (DD1 workaround) - l_ecmd_rc |= l_mbaspa_mask.clearBit(8); - - // 9 Spare_Attn1 masked - l_ecmd_rc |= l_mbaspa_mask.setBit(9); - - // 10 MCBIST_Done masked - l_ecmd_rc |= l_mbaspa_mask.setBit(10); - - // 11:63 RESERVED not implemented, so won't touch these - - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write mask - l_rc = fapiPutScom_w_retry(l_mbaChiplets[i], - MBA01_MBSPAMSKQ_0x03010614, - l_mbaspa_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(l_mbaChiplets[i], - MBA01_MBSPAMSKQ_0x03010614, - l_mbaspa_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - //************************************************ - - - - //************************* - //************************* - // MBECCFIR - //************************* - //************************* - - // Get MBA position: 0 = mba01, 1 = mba23 - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_mbaChiplets[i], l_mbaPosition); - if(l_rc) - { - FAPI_ERR("Error getting MBA position"); - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Read mask - l_rc = fapiGetScom_w_retry(i_target, - l_mbeccfir_mask_address[l_mbaPosition], - l_mbeccfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_mbeccfir_action0.flushTo0(); - l_ecmd_rc |= l_mbeccfir_action1.flushTo0(); - l_ecmd_rc |= l_mbeccfir_mask_or.flushTo0(); - l_ecmd_rc |= l_mbeccfir_mask_and.flushTo1(); - - // 0:7 Memory MPE Rank 0:7 recoverable mask - l_ecmd_rc |= l_mbeccfir_action0.clearBit(0,8); - l_ecmd_rc |= l_mbeccfir_action1.setBit(0,8); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(0,8); - - // 8:15 Reserved recoverable mask (forever) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(8,8); - l_ecmd_rc |= l_mbeccfir_action1.setBit(8,8); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(8,8); - - // 16 Memory NCE recoverable mask - l_ecmd_rc |= l_mbeccfir_action0.clearBit(16); - l_ecmd_rc |= l_mbeccfir_action1.setBit(16); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(16); - - // 17 Memory RCE recoverable mask - l_ecmd_rc |= l_mbeccfir_action0.clearBit(17); - l_ecmd_rc |= l_mbeccfir_action1.setBit(17); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(17); - - // 18 Memory SUE recoverable mask (forever) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(18); - l_ecmd_rc |= l_mbeccfir_action1.setBit(18); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(18); - - // 19 Memory UE recoverable mask - l_ecmd_rc |= l_mbeccfir_action0.clearBit(19); - l_ecmd_rc |= l_mbeccfir_action1.setBit(19); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(19); - - // 20:27 Maint MPE Rank 0:7 recoverable unmask - // NOTE: FW memdiags may want to mask this if they want to wait till - // cmd gets to end of rank before getting any attention. - l_ecmd_rc |= l_mbeccfir_action0.clearBit(20,8); - l_ecmd_rc |= l_mbeccfir_action1.setBit(20,8); - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(20,8); - - // 28:35 Reserved recoverable mask (forever) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(28,8); - l_ecmd_rc |= l_mbeccfir_action1.setBit(28,8); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(28,8); - - // 36 Maintenance NCE recoverable mask (tbd) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(36); - l_ecmd_rc |= l_mbeccfir_action1.setBit(36); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(36); - - // 37 Maintenance SCE recoverable mask (tbd) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(37); - l_ecmd_rc |= l_mbeccfir_action1.setBit(37); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(37); - - // 38 Maintenance MCE recoverable mask (tbd) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(38); - l_ecmd_rc |= l_mbeccfir_action1.setBit(38); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(38); - - // 39 Maintenance RCE recoverable mask (tbd) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(39); - l_ecmd_rc |= l_mbeccfir_action1.setBit(39); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(39); - - // 40 Maintenance SUE recoverable mask (forever) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(40); - l_ecmd_rc |= l_mbeccfir_action1.setBit(40); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(40); - - // 41 Maintenance UE recoverable unmask (tbd) - // NOTE: FW memdiags may want to mask this if they want to wait till - // cmd gets to end of rank before getting any attention. - l_ecmd_rc |= l_mbeccfir_action0.clearBit(41); - l_ecmd_rc |= l_mbeccfir_action1.setBit(41); - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(41); - - // 42 MPE during maintenance mark mode recoverable mask (forever) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(42); - l_ecmd_rc |= l_mbeccfir_action1.setBit(42); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(42); - - // 43 Prefetch Memory UE recoverable mask - l_ecmd_rc |= l_mbeccfir_action0.clearBit(43); - l_ecmd_rc |= l_mbeccfir_action1.setBit(43); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(43); - - // 44 Memory RCD parity error recoverable mask (forever) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(44); - l_ecmd_rc |= l_mbeccfir_action1.setBit(44); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(44); - - // 45 Maint RCD parity error. recoverable mask (forever) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(45); - l_ecmd_rc |= l_mbeccfir_action1.setBit(45); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(45); - - // 46 Recoverable reg parity recoverable unmask - l_ecmd_rc |= l_mbeccfir_action0.clearBit(46); - l_ecmd_rc |= l_mbeccfir_action1.setBit(46); - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(46); - - - // 47 Unrecoverable reg parity channel checkstop unmask - l_ecmd_rc |= l_mbeccfir_action0.clearBit(47); - l_ecmd_rc |= l_mbeccfir_action1.clearBit(47); - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(47); - - // 48 Maskable reg parity error recoverable mask (forever) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(48); - l_ecmd_rc |= l_mbeccfir_action1.setBit(48); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(48); - - // 49 ecc datapath parity error channel checkstop unmask - l_ecmd_rc |= l_mbeccfir_action0.clearBit(49); - l_ecmd_rc |= l_mbeccfir_action1.clearBit(49); - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(49); - - // 50 internal scom error recovereble mask (tbd) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(50); - l_ecmd_rc |= l_mbeccfir_action1.setBit(50); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(50); - - // 51 internal scom error clone recovereble mask (tbd) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(51); - l_ecmd_rc |= l_mbeccfir_action1.setBit(51); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(51); - - // 52:63 Reserved not implemented, so won't touch these - - - - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write action0 - l_rc = fapiPutScom_w_retry(i_target, - l_mbeccfir_action0_address[l_mbaPosition], - l_mbeccfir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write action1 - l_rc = fapiPutScom_w_retry(i_target, - l_mbeccfir_action1_address[l_mbaPosition], - l_mbeccfir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - // Write mask OR - l_rc = fapiPutScom_w_retry(i_target, - l_mbeccfir_mask_or_address[l_mbaPosition], - l_mbeccfir_mask_or); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, - l_mbeccfir_mask_and_address[l_mbaPosition], - l_mbeccfir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(i_target, - l_mbeccfir_action0_address[l_mbaPosition], - l_mbeccfir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - l_rc = fapiGetScom_w_retry(i_target, - l_mbeccfir_action1_address[l_mbaPosition], - l_mbeccfir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - l_rc = fapiGetScom_w_retry(i_target, - l_mbeccfir_mask_address[l_mbaPosition], - l_mbeccfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - } // End for loop through functional MBAs on this Centaur - - FAPI_INF("EXIT mss_unmask_maint_errors()"); - - return i_bad_rc; -} - - - - -//------------------------------------------------------------------------------ -// mss_unmask_fetch_errors -//------------------------------------------------------------------------------ - -fapi::ReturnCode mss_unmask_fetch_errors(const fapi::Target & i_target, - fapi::ReturnCode i_bad_rc ) - -{ - - // Target: Centaur - - FAPI_INF("ENTER mss_unmask_fetch_errors()"); - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - - - //************************* - //************************* - // SCAC_LFIR - //************************* - //************************* - - ecmdDataBufferBase l_scac_lfir_mask(64); - ecmdDataBufferBase l_scac_lfir_mask_or(64); - ecmdDataBufferBase l_scac_lfir_mask_and(64); - ecmdDataBufferBase l_scac_lfir_action0(64); - ecmdDataBufferBase l_scac_lfir_action1(64); - - // Read mask - l_rc = fapiGetScom_w_retry(i_target, SCAC_FIRMASK_0x020115C3, l_scac_lfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_scac_lfir_action0.flushTo0(); - l_ecmd_rc |= l_scac_lfir_action1.flushTo0(); - l_ecmd_rc |= l_scac_lfir_mask_or.flushTo0(); - l_ecmd_rc |= l_scac_lfir_mask_and.flushTo1(); - - // 0 I2CMInvAddr recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(0); - l_ecmd_rc |= l_scac_lfir_action1.setBit(0); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(0); - - // 1 I2CMInvWrite recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(1); - l_ecmd_rc |= l_scac_lfir_action1.setBit(1); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(1); - - // 2 I2CMInvRead recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(2); - l_ecmd_rc |= l_scac_lfir_action1.setBit(2); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(2); - - // 3 I2CMApar recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(3); - l_ecmd_rc |= l_scac_lfir_action1.setBit(3); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(3); - - // 4 I2CMPar recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(4); - l_ecmd_rc |= l_scac_lfir_action1.setBit(4); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(4); - - // 5 I2CMLBPar recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(5); - l_ecmd_rc |= l_scac_lfir_action1.setBit(5); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(5); - - // 6:9 Expansion recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(6,4); - l_ecmd_rc |= l_scac_lfir_action1.setBit(6,4); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(6,4); - - // 10 I2CMInvCmd recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(10); - l_ecmd_rc |= l_scac_lfir_action1.setBit(10); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(10); - - // 11 I2CMPErr recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(11); - l_ecmd_rc |= l_scac_lfir_action1.setBit(11); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(11); - - // 12 I2CMOverrun recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(12); - l_ecmd_rc |= l_scac_lfir_action1.setBit(12); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(12); - - // 13 I2CMAccess recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(13); - l_ecmd_rc |= l_scac_lfir_action1.setBit(13); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(13); - - // 14 I2CMArb recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(14); - l_ecmd_rc |= l_scac_lfir_action1.setBit(14); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(14); - - // 15 I2CMNack recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(15); - l_ecmd_rc |= l_scac_lfir_action1.setBit(15); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(15); - - // 16 I2CMStop recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(16); - l_ecmd_rc |= l_scac_lfir_action1.setBit(16); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(16); - - // 17 LocalPib1 recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(17); - l_ecmd_rc |= l_scac_lfir_action1.setBit(17); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(17); - - // 18 LocalPib2 recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(18); - l_ecmd_rc |= l_scac_lfir_action1.setBit(18); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(18); - - // 19 LocalPib3 recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(19); - l_ecmd_rc |= l_scac_lfir_action1.setBit(19); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(19); - - // 20 LocalPib4 recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(20); - l_ecmd_rc |= l_scac_lfir_action1.setBit(20); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(20); - - // 21 LocalPib5 recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(21); - l_ecmd_rc |= l_scac_lfir_action1.setBit(21); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(21); - - // 22 LocalPib6 recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(22); - l_ecmd_rc |= l_scac_lfir_action1.setBit(22); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(22); - - // 23 LocalPib7 recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(23); - l_ecmd_rc |= l_scac_lfir_action1.setBit(23); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(23); - - // 24 StallError recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(24); - l_ecmd_rc |= l_scac_lfir_action1.setBit(24); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(24); - - // 25 RegParErr channel checkstop unmask - l_ecmd_rc |= l_scac_lfir_action0.clearBit(25); - l_ecmd_rc |= l_scac_lfir_action1.clearBit(25); - l_ecmd_rc |= l_scac_lfir_mask_and.clearBit(25); - - // 26 RegParErrX channel checkstop unmask - l_ecmd_rc |= l_scac_lfir_action0.clearBit(26); - l_ecmd_rc |= l_scac_lfir_action1.clearBit(26); - l_ecmd_rc |= l_scac_lfir_mask_and.clearBit(26); - - // 27:31 Reserved recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(27,5); - l_ecmd_rc |= l_scac_lfir_action1.setBit(27,5); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(27,5); - - // 32 SMErr recoverable unmask - l_ecmd_rc |= l_scac_lfir_action0.clearBit(32); - l_ecmd_rc |= l_scac_lfir_action1.setBit(32); - l_ecmd_rc |= l_scac_lfir_mask_and.clearBit(32); - - // 33 RegAccErr recoverable unmask - l_ecmd_rc |= l_scac_lfir_action0.clearBit(33); - l_ecmd_rc |= l_scac_lfir_action1.setBit(33); - l_ecmd_rc |= l_scac_lfir_mask_and.clearBit(33); - - // 34 ResetErr recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(34); - l_ecmd_rc |= l_scac_lfir_action1.setBit(34); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(34); - - // 35 internal_scom_error recoverable masked (tbd) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(35); - l_ecmd_rc |= l_scac_lfir_action1.setBit(35); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(35); - - // 36 internal_scom_error_clone recoverable masked (tbd) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(36); - l_ecmd_rc |= l_scac_lfir_action1.setBit(36); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(36); - - // 37:63 Reserved - // Can we write to these bits? - - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write action0 - l_rc = fapiPutScom_w_retry(i_target, SCAC_FIRACTION0_0x020115C6, l_scac_lfir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write action1 - l_rc = fapiPutScom_w_retry(i_target, SCAC_FIRACTION1_0x020115C7, l_scac_lfir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - // Write mask OR - l_rc = fapiPutScom_w_retry(i_target, SCAC_FIRMASK_OR_0x020115C5, l_scac_lfir_mask_or); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, SCAC_FIRMASK_AND_0x020115C4, l_scac_lfir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(i_target, SCAC_FIRACTION0_0x020115C6, l_scac_lfir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - l_rc = fapiGetScom_w_retry(i_target, SCAC_FIRACTION1_0x020115C7, l_scac_lfir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - l_rc = fapiGetScom_w_retry(i_target, SCAC_FIRMASK_0x020115C3, l_scac_lfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - - //************************* - //************************* - // MBS_FIR_REG - //************************* - //************************* - - - // NOTE: In the IPL sequence, mss_unmask_inband_errors has already been - // called, which has already set the MBS_FIR_REG action regs to their - // runtime values, so no need to touch the action regs here. - - // NOTE: In the IPL sequence, mss_unmask_inband_errors, - // has already been called, which has already unmasked the approproiate - // MBS_FIR_REG errors following mss_unmask_inband_errors. So all we will do - // here is unmask errors requiring mainline traffic which would be - // considered valid after the mss_thermal_init procedure. - - - ecmdDataBufferBase l_mbs_fir_mask(64); - ecmdDataBufferBase l_mbs_fir_mask_and(64); - - // Read mask - l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_MASK_REG_0x02011403, l_mbs_fir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - l_ecmd_rc |= l_mbs_fir_mask_and.flushTo1(); - - // 2 invalid_address_error channel checkstop unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(2); - - // 3 external_timeout channel checkstop unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(3); - - // 4 internal_timeout channel checkstop unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(4); - - // 9 cache_srw_ce recoverable unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(9); - - // 10 cache_srw_ue recoverable unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(10); - - // 12 cache_co_ce recoverable unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(12); - - // 13 cache_co_ue recoverable unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(13); - - // 15 dir_ce recoverable unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(15); - - // 16 dir_ue channel checkstop unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(16); - - // 18 dir_all_members_deleted channel checkstop unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(18); - - // 19 lru_error recoverable unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(19); - - // 20 eDRAM error channel checkstop unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(20); - - // 26 srb_buffer_ce recoverable unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(26); - - // 27 srb_buffer_ue recoverable unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(27); - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, MBS_FIR_MASK_REG_AND_0x02011404, l_mbs_fir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_MASK_REG_0x02011403, l_mbs_fir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - - //************************* - //************************* - // MBECCFIR - //************************* - //************************* - - std::vector<fapi::Target> l_mbaChiplets; - uint8_t l_mbaPosition; // 0 = mba01, 1 = mba23 - - - uint32_t l_mbeccfir_mask_address[2]={ - // port0/1 port2/3 - MBS_ECC0_MBECCFIR_MASK_0x02011443,MBS_ECC1_MBECCFIR_MASK_0x02011483}; - - uint32_t l_mbeccfir_mask_and_address[2]={ - // port0/1 port2/3 - MBS_ECC0_MBECCFIR_MASK_AND_0x02011444,MBS_ECC1_MBECCFIR_MASK_AND_0x02011484}; - - ecmdDataBufferBase l_mbeccfir_mask(64); - ecmdDataBufferBase l_mbeccfir_mask_and(64); - - - // Get associated functional MBAs on this centaur - l_rc = fapiGetChildChiplets(i_target, - fapi::TARGET_TYPE_MBA_CHIPLET, - l_mbaChiplets); - if(l_rc) - { - FAPI_ERR("Error getting functional MBAs on this Centaur"); - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Loop through functional MBAs on this Centaur - for (uint32_t i=0; i < l_mbaChiplets.size(); i++) - { - - // Get MBA position: 0 = mba01, 1 = mba23 - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_mbaChiplets[i], l_mbaPosition); - if(l_rc) - { - FAPI_ERR("Error getting MBA position"); - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Read mask - l_rc = fapiGetScom_w_retry(i_target, - l_mbeccfir_mask_address[l_mbaPosition], - l_mbeccfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - // NOTE: In the IPL sequence, mss_unmask_maint_errors has already been - // called, which has already set the MBECCFIR action regs to their runtime - // values, so no need to touch the action regs here. - - // NOTE: In the IPL sequence, mss_unmask_maint_errors, - // has already been called, which has already unmasked the approproiate - // MBECCFIR errors following mss_unmask_maint_errors. So all we will do - // here is unmask errors requiring mainline traffic which would be - // considered valid after the mss_thermal_init procedure. - - l_ecmd_rc |= l_mbeccfir_mask_and.flushTo1(); - - // 0:7 Memory MPE Rank 0:7 recoverable unmask - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(0,8); - - // 16 Memory NCE recoverable unmask - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(16); - - // 17 Memory RCE recoverable unmask - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(17); - - // 19 Memory UE recoverable unmask - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(19); - - // 43 Prefetch Memory UE recoverable unmask - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(43); - - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, - l_mbeccfir_mask_and_address[l_mbaPosition], - l_mbeccfir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(i_target, - l_mbeccfir_mask_address[l_mbaPosition], - l_mbeccfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - } - - - //************************* - //************************* - // MBACALFIR - //************************* - //************************* - - ecmdDataBufferBase l_mbacalfir_mask(64); - ecmdDataBufferBase l_mbacalfir_mask_and(64); - - // NOTE: In the IPL sequence, mss_unmask_draminit_errors has already been - // called, which has already set the MBACALFIR action regs to their runtime - // values, so no need to touch the action regs here. - - // NOTE: In the IPL sequence, various bits have already been unmasked - // after the approproiate procedures. So all we will do here is unmask - // errors requiring mainline traffic which would be considered valid after - // the mss_thermal_init procedure. - - // Loop through functional MBAs on this Centaur - for (uint32_t i=0; i < l_mbaChiplets.size(); i++) - { - - // Read mask - l_rc = fapiGetScom_w_retry(l_mbaChiplets[i], - MBA01_MBACALFIR_MASK_0x03010403, - l_mbacalfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - l_ecmd_rc |= l_mbacalfir_mask_and.flushTo1(); - - // 9 mba_wrd ue recoverable unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(9); - - // 10 mba_wrd ce recoverable unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(10); - - // 14 wrq_data_ce recoverable unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(14); - - // 15 wrq_data_ue recoverable unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(15); - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(l_mbaChiplets[i], - MBA01_MBACALFIR_MASK_AND_0x03010404, - l_mbacalfir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(l_mbaChiplets[i], - MBA01_MBACALFIR_MASK_0x03010403, - l_mbacalfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - } - - - - - FAPI_INF("EXIT mss_unmask_fetch_errors()"); - - return i_bad_rc; -} - -//------------------------------------------------------------------------------ -// fapiGetScom_w_retry -//------------------------------------------------------------------------------ -fapi::ReturnCode fapiGetScom_w_retry(const fapi::Target& i_target, - const uint64_t i_address, - ecmdDataBufferBase & o_data) -{ - fapi::ReturnCode l_rc; - - l_rc = fapiGetScom(i_target, i_address, o_data); - if(l_rc) - { - FAPI_ERR("1st Centaur fapiGetScom failed, so attempting retry."); - - // Log centaur scom error - fapiLogError(l_rc); - - // Retry centaur scom with assumption that retry is done via FSI, - // which may still work. - // NOTE: If scom fail was due to channel fail a retry via FSI may - // work. But if scom fail was due to PIB error, retry via FSI may - // also fail. - l_rc = fapiGetScom(i_target, i_address, o_data); - if(l_rc) - { - FAPI_ERR("fapiGetScom retry via FSI failed."); - // Retry didn't work either so give up and pass - // back centaur scom error - } - } - - return l_rc; -} - - -//------------------------------------------------------------------------------ -// fapiPutScom_w_retry -//------------------------------------------------------------------------------ -fapi::ReturnCode fapiPutScom_w_retry(const fapi::Target& i_target, - const uint64_t i_address, - ecmdDataBufferBase & i_data) -{ - fapi::ReturnCode l_rc; - - // NOTE: Inband scom device driver takes care of read to special reg after - // an inband scom write in order to detect SUE - l_rc = fapiPutScom(i_target, i_address, i_data); - if(l_rc) - { - FAPI_ERR("1st Centaur fapiPutScom failed, so attempting retry."); - - // Log centaur scom error - fapiLogError(l_rc); - - // Retry centaur scom with assumption that retry is done via FSI, - // which may still work. - // NOTE: If scom fail was due to channel fail a retry via FSI may - // work. But if scom fail was due to PIB error, retry via FSI may - // also fail. - l_rc = fapiPutScom(i_target, i_address, i_data); - if(l_rc) - { - FAPI_ERR("fapiPutScom retry via FSI failed."); - // Retry didn't work either so give up and pass - // back centaur scom error - } - } - - return l_rc; -} diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/edi_ei_initialization.C b/src/usr/hwpf/hwp/edi_ei_initialization/edi_ei_initialization.C index 4deca32bc..ccb463909 100644 --- a/src/usr/hwpf/hwp/edi_ei_initialization/edi_ei_initialization.C +++ b/src/usr/hwpf/hwp/edi_ei_initialization/edi_ei_initialization.C @@ -74,7 +74,6 @@ #include "proc_fab_iovalid/proc_fab_iovalid.H" #include <diag/prdf/prdfMain.H> #include "fabric_io_dccal/fabric_io_dccal.H" -#include <intr/interrupt.H> // eRepair Restore #include <erepairAccessorHwpFuncs.H> @@ -809,55 +808,6 @@ void* call_proc_fab_iovalid( void *io_pArgs ) (l_errl ? "ERROR" : "SUCCESS")); } - // no errors during the proc_fabric_iovalid so switch to XSCOM - if(!l_errl) - { - // At the point where we can now change the proc chips to use - // XSCOM rather than FSISCOM which is the default. - - TARGETING::TargetHandleList procChips; - getAllChips(procChips, TYPE_PROC); - - TARGETING::TargetHandleList::iterator curproc = procChips.begin(); - - // Loop through all proc chips - while(curproc != procChips.end()) - { - TARGETING::Target* l_proc_target = *curproc; - - // If the proc chip supports xscom.. - if (l_proc_target->getAttr<ATTR_PRIMARY_CAPABILITIES>() - .supportsXscom) - { - ScomSwitches l_switches = - l_proc_target->getAttr<ATTR_SCOM_SWITCHES>(); - - // If Xscom is not already enabled. - if ((l_switches.useXscom != 1) || (l_switches.useFsiScom != 0)) - { - l_switches.useFsiScom = 0; - l_switches.useXscom = 1; - - // Turn off FSI scom and turn on Xscom. - l_proc_target->setAttr<ATTR_SCOM_SWITCHES>(l_switches); - } - } - - // Enable PSI interrupts even if can't Xscom as - // Pbus is up and interrupts can flow - l_errl = INTR::enablePsiIntr(l_proc_target); - if(l_errl) - { - // capture the target data in the elog - ErrlUserDetailsTarget(l_proc_target).addToLog( l_errl ); - - break; - } - - ++curproc; - } - } - if (l_errl) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, diff --git a/src/usr/hwpf/hwp/include/p8_istep_num.H b/src/usr/hwpf/hwp/include/p8_istep_num.H index b80fc0df3..bc91d666c 100644 --- a/src/usr/hwpf/hwp/include/p8_istep_num.H +++ b/src/usr/hwpf/hwp/include/p8_istep_num.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -23,7 +23,7 @@ #ifndef __P8_ISTEP_NUM_H #define __P8_ISTEP_NUM_H -// $Id: p8_istep_num.H,v 1.19 2012/10/23 12:47:56 koenig Exp $ +// $Id: p8_istep_num.H,v 1.22 2013/02/06 04:15:38 jmcgill Exp $ /// Istep number encoding for all SEEPROM and PNOR procedures. Used to update /// the SBEVITAL register to record procedure progress and to create unique @@ -68,10 +68,11 @@ CONST_UINT64_T(proc_sbe_ex_core_initf_istep_num, ULL(0x040B)); CONST_UINT64_T(proc_sbe_ex_do_manual_inits_istep_num, ULL(0x040C)); CONST_UINT64_T(proc_sbe_ex_startclocks_istep_num, ULL(0x040D)); CONST_UINT64_T(proc_sbe_ex_scominit_istep_num, ULL(0x040E)); -CONST_UINT64_T(proc_sbe_ex_init_escape_istep_num, ULL(0x040F)); -CONST_UINT64_T(proc_sbe_ex_sp_runtime_scom_istep_num, ULL(0x0410)); -CONST_UINT64_T(proc_sbe_ex_occ_runtime_scom_istep_num, ULL(0x0411)); -CONST_UINT64_T(proc_sbe_ex_host_runtime_scom_istep_num, ULL(0x0412)); +CONST_UINT64_T(proc_sbe_ex_core_scominit_istep_num, ULL(0x040F)); +CONST_UINT64_T(proc_sbe_ex_init_escape_istep_num, ULL(0x0410)); +CONST_UINT64_T(proc_sbe_ex_sp_runtime_scom_istep_num, ULL(0x0411)); +CONST_UINT64_T(proc_sbe_ex_occ_runtime_scom_istep_num, ULL(0x0412)); +CONST_UINT64_T(proc_sbe_ex_host_runtime_scom_istep_num, ULL(0x0413)); CONST_UINT64_T(proc_sbe_enable_pnor_istep_num, ULL(0x0500)); CONST_UINT64_T(proc_sbe_lco_loader_istep_num, ULL(0x0501)); @@ -82,5 +83,6 @@ CONST_UINT64_T(proc_sbe_trigger_winkle_istep_num, ULL(0x0F01)); #define PROC_SBE_TRIGGER_WINKLE_ISTEP_NUM proc_sbe_trigger_winkle_istep_num #define PROC_SBE_CHECK_MASTER_ISTEP_NUM proc_sbe_check_master_istep_num #define PROC_SBE_ENABLE_PNOR_ISTEP_NUM proc_sbe_enable_pnor_istep_num +#define PROC_SBE_EX_HOST_RUNTIME_SCOM_ISTEP_NUM proc_sbe_ex_host_runtime_scom_istep_num #endif // __P8_ISTEP_NUM_H diff --git a/src/usr/hwpf/hwp/include/p8_scom_addresses.H b/src/usr/hwpf/hwp/include/p8_scom_addresses.H index 295ab48fd..6cfae2d6a 100644..100755 --- a/src/usr/hwpf/hwp/include/p8_scom_addresses.H +++ b/src/usr/hwpf/hwp/include/p8_scom_addresses.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_scom_addresses.H,v 1.129 2013/01/10 01:17:27 stillgs Exp $ +// $Id: p8_scom_addresses.H,v 1.135 2013/03/01 03:05:38 pchatnah Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/p8_scom_addresses.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -137,6 +137,9 @@ CONST_UINT64_T( ALL_CORES_COMP_0x62000000 , ULL(0x62000000) ); CONST_UINT64_T( ALL_CORES_WRITE_0x6A000000 , ULL(0x6A000000) ); +CONST_UINT64_T( DEVICE_ID_REG_0x000F000F , ULL(0x000F000F) ); + + /******************************************************************************/ /******************************** TP CHIPLET ********************************/ /******************************************************************************/ @@ -399,6 +402,14 @@ CONST_UINT64_T( PMC_PORRS_REG_0x00062090 , ULL(0x00062090) ); CONST_UINT64_T( PMC_DEEPEXIT_MASK_0x00062092 , ULL(0x00062092) ); CONST_UINT64_T( PMC_DEEPEXIT_MASK_WAND_0x000620A0 , ULL(0x000620A0) ); CONST_UINT64_T( PMC_DEEPEXIT_MASK_WOR_0x000620A1 , ULL(0x000620A1) ); +CONST_UINT64_T( PMC_INTCHP_COMMAND_REG_0x00062014 , ULL(0x00062014) ); +CONST_UINT64_T( PMC_INTCHP_STATUS_REG_0x00062013 , ULL(0x00062013) ); +CONST_UINT64_T( PMC_PORE_REQ_REG0_0x0006208E , ULL(0x0006208E) ); +CONST_UINT64_T( PMC_PARAMETER_REG0_0x00062005 , ULL(0x00062005) ); +CONST_UINT64_T( PMC_O2P_CTRL_STATUS_REG_0x00062061 , ULL (0x00062061)); + +CONST_UINT64_T( OCB_OCI_OIMR1_0x0006a014 , ULL(0x0006a014) ); +CONST_UINT64_T( OCB_OCI_OIMR0_0x0006a004 , ULL(0x0006a004) ); // SPIVID Controller CONST_UINT64_T( PMC_SPIV_CTRL_REG0A_0x00062040 , ULL(0x00062040) ); @@ -1020,6 +1031,8 @@ CONST_UINT64_T( X_GP0_0x04000000 , ULL(0x04000000) ); CONST_UINT64_T( X_GP1_0x04000001 , ULL(0x04000001) ); CONST_UINT64_T( X_GP2_0x04000002 , ULL(0x04000002) ); +CONST_UINT64_T( X_CLK_ADJ_SET_0x040F0016 , ULL(0x040F0016) ); + //------------------------------------------------------------------------------ // X-BUS SCOM // ring 1 = Trace 0 @@ -1408,6 +1421,8 @@ CONST_UINT64_T( EX_L3_FIR_MASK_REG_0x10010803 , ULL(0x10010803) ); CONST_UINT64_T( EX_L3_FIR_ACTION0_REG_0x10010806 , ULL(0x10010806) ); CONST_UINT64_T( EX_L3_FIR_ACTION1_REG_0x10010807 , ULL(0x10010807) ); CONST_UINT64_T( EX_L3_MODE_REG1_0x1001080A , ULL(0x1001080A) ); +CONST_UINT64_T( EX_L3_CERRS_RD_EPS_REG_0x10010829 , ULL(0x10010829) ); +CONST_UINT64_T( EX_L3_CERRS_WR_EPS_REG_0x1001082A , ULL(0x1001082A) ); CONST_UINT64_T( EX_L3_MODE_REG0_0x1001082B , ULL(0x1001082B) ); CONST_UINT64_T( EX_L3_PRD_PURGE_REG_0x1001080E , ULL(0x1001080E) ); CONST_UINT64_T( EX_L3_HA_DIRTY_ADDR_WR_PTR_0x10010832 , ULL(0x10010832) ); @@ -1427,6 +1442,7 @@ CONST_UINT64_T( EX_L2_FIR_OR_REG_0x10012802 , ULL(0x10012802) ); CONST_UINT64_T( EX_L2_FIR_MASK_REG_0x10012803 , ULL(0x10012803) ); CONST_UINT64_T( EX_L2_FIR_ACTION0_REG_0x10012806 , ULL(0x10012806) ); CONST_UINT64_T( EX_L2_FIR_ACTION1_REG_0x10012807 , ULL(0x10012807) ); +CONST_UINT64_T( EX_L2_CERRS_RD_EPS_REG_0x10012814 , ULL(0x10012814) ); CONST_UINT64_T( EX_L2_CERRS_REG0_0x10012815 , ULL(0x10012815) ); CONST_UINT64_T( EX_L2_CERRS_REG1_0x10012816 , ULL(0x10012816) ); CONST_UINT64_T( EX_L2_MODE_REG0_0x1001280A , ULL(0x1001280A) ); @@ -1590,7 +1606,7 @@ CONST_UINT64_T( EX_THERM_0x10050000 , ULL(0x10050000) ); //------------------------------------------------------------------------------ // EX Security //------------------------------------------------------------------------------ -CONST_UINT64_T( EX_TRUSTED_BOOT_EN_0x10050000 , ULL(0x10013C03) ); +CONST_UINT64_T( EX_TRUSTED_BOOT_EN_0x10013C03 , ULL(0x10013C03) ); //------------------------------------------------------------------------------ // EX PCB SLAVE @@ -1801,6 +1817,21 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: p8_scom_addresses.H,v $ +Revision 1.135 2013/03/01 03:05:38 pchatnah +adding device_id register + +Revision 1.134 2013/02/20 19:04:32 cmolsen +Added L2/L3 Epsilon registers. + +Revision 1.133 2013/02/05 14:33:50 koenig +Added XBus skew adjust register - AK + +Revision 1.132 2013/01/23 15:46:10 pchatnah +fixing address mistakes + +Revision 1.130 2013/01/17 11:39:08 pchatnah +updating the pmc_init registers + Revision 1.129 2013/01/10 01:17:27 stillgs Fix ID line typo diff --git a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile new file mode 100644 index 000000000..e1453741d --- /dev/null +++ b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile @@ -0,0 +1,294 @@ +#-- $Id: p8.abus.custom.scom.initfile,v 1.1 2013/02/11 04:26:41 jmcgill Exp $ +#-- CHANGE HISTORY: +#-------------------------------------------------------------------------------- +#-- Version:|Author: | Date: | Comment: +#-- --------|--------|--------|-------------------------------------------------- +#-- 1.1 |thomsen |01/29/13|Created initial version +#-- --------|--------|--------|-------------------------------------------------- +#-------------------------------------------------------------------------------- +# End of revision history +#-------------------------------------------------------------------------------- + +#--Master list of variables that can be used in this file is at: +#--<Attribute Definition Location> + +SyntaxVersion = 1 + + +#--****************************************************************************** +#-- ----------------------------------------------------------------------------- +#-- +#-- Includes +#-- Note: Must include the path to the .define file. +#-- +#-- ----------------------------------------------------------------------------- +#--****************************************************************************** + +include edi.io.define + + +#--****************************************************************************** +#-- ----------------------------------------------------------------------------- +#-- +#-- Defines +#-- +#-- ----------------------------------------------------------------------------- +#--****************************************************************************** + +define def_all_lanes=11111; + + +#--****************************************************************************** +#-------------------------------------------------------------------------------- +# __ ____ __ __ +# / / ____ _____ ___ / __ \____ _ _____ _____ / / / /___ +# / / / __ `/ __ \/ _ \ / /_/ / __ \ | /| / / _ \/ ___/ / / / / __ \ +# / /___/ /_/ / / / / __/ / ____/ /_/ / |/ |/ / __/ / / /_/ / /_/ / +# /_____/\__,_/_/ /_/\___/ /_/ \____/|__/|__/\___/_/ \____/ .___/ +# /_/ +#-------------------------------------------------------------------------------- +#--****************************************************************************** + +### # rx_lane_pdwn +### scom 0x800.0b(rx_mode_pl)(tx_grp0)(def_all_lanes).0x(abus_gcr_addr) { +### bits, scom_data; +### rx_lane_pdwn, 0b0; +### } + + +### # tx_lane_pdwn +### scom 0x800.0b(tx_mode_pl)(tx_grp0)(def_all_lanes).0x(abus_gcr_addr) { +### bits, scom_data; +### tx_lane_pdwn, 0b0; +### } + + +#--****************************************************************************** +#-------------------------------------------------------------------------------- +# _______ __ __ ___ _ ________ _____ ___ ____________ ______ +# /_ __/ |/ / / / / | / | / / ____/ / _/ | / / | / / ____/ __ \/_ __/ +# / / | / / / / /| | / |/ / __/ / // |/ /| | / / __/ / /_/ / / / +# / / / | / /___/ ___ |/ /| / /___ _/ // /| / | |/ / /___/ _, _/ / / +# /_/ /_/|_| /_____/_/ |_/_/ |_/_____/ /___/_/ |_/ |___/_____/_/ |_| /_/ +# figlet -fslant +#-------------------------------------------------------------------------------- +#--****************************************************************************** + +# These only do a scom if the invert attribute is set (saves scom's). +# The default scanflush value of tx_lane_invert for each lane is '0'. + +# Lane 0 +# 0x8004040008010C3F +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_0).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x80000000) > 0); +} + +# +# Lane 1 +# 0x8004040108010C3F +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_1).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x40000000) > 0); +} + +# +# Lane 2 +# 0x8004040208010C3F +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_2).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x20000000) > 0); +} + +# +# Lane 3 +# 0x8004040308010C3F +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_3).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x10000000) > 0); +} + +# +# Lane 4 +# 0x8004040408010C3F +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_4).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x08000000) > 0); +} + +# +# Lane 5 +# 0x8004040508010C3F +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_5).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x04000000) > 0); +} + +# +# Lane 6 +# 0x8004040608010C3F +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_6).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x02000000) > 0); +} + +# +# Lane 7 +# 0x8004040708010C3F +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_7).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x01000000) > 0); +} + +# +# Lane 8 +# 0x8004040808010C3F +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_8).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00800000) > 0); +} + +# +# Lane 9 +# 0x8004040908010C3F{ +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_9).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00400000) > 0); +} + +# +# Lane 10 +# 0x8004040A08010C3F +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_10).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00200000) > 0); +} + +# Lane 11 +# 0x8004040B08010C3F +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_11).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00100000) > 0); +} + +# +# Lane 12 +# 0x8004040C08010C3F +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_12).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00080000) > 0); +} + +# +# Lane 13 +# 0x8004040D08010C3F +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_13).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00040000) > 0); +} + +# +# Lane 14 +# 0x8004040E08010C3F +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_14).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00020000) > 0); +} + +# +# Lane 15 +# 0x8004040F08010C3F +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_15).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00010000) > 0); +} + +# +# Lane 16 +# 0x8004041008010C3F +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_16).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00008000) > 0); +} + +# Lane 17 +# 0x8004042008010C3F +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_17).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00004000) > 0); +} + +# Lane 18 +# 0x8004043008010C3F +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_18).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00002000) > 0); +} + +# Lane 19 +# 0x8004044008010C3F +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_19).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00001000) > 0); +} + +# Lane 20 +# 0x8004045008010C3F +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_20).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00000800) > 0); +} + +# Lane 21 +# 0x8004046008010C3F +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_21).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00000400) > 0); +} + +# Lane 22 +# 0x8004047008010C3F +scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_22).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00000200) > 0); +} + +#--****************************************************************************** +#-------------------------------------------------------------------------------- +# _____ _ _ _______ _ _ ___ _ +# /_ __/ |/ / / ____/ / / //_/ / _/___ _ _____ _____/ / +# / / | / / / / / / ,< / // __ \ | / / _ \/ ___/ __/ +# / / / | / /___/ /___/ /| | _/ // / / / |/ / __/ / / / +# /_/ /_/|_| \____/_____/_/ |_| /___/_/ /_/|___/\___/_/ \__/ +# figlet -fslant +#-------------------------------------------------------------------------------- +#--****************************************************************************** +# CLK Lane (assigned to bit 31 of TX Lane Invert Attribute) +# 0x800???7008010C3F +scom 0x800.0b(tx_clk_mode_pg)(tx_grp0)(lane_na).0x(abus_gcr_addr) { + bits, scom_data, expr; + tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00000001) > 0); +} + +#--****************************************************************************** +#-------------------------------------------------------------------------------- +# __ ________ ____ _____ +# / |/ / ___// __ ) / ___/ ______ _____ +# / /|_/ /\__ \/ __ | \__ \ | /| / / __ `/ __ \ +# / / / /___/ / /_/ / ___/ / |/ |/ / /_/ / /_/ / +# /_/ /_//____/_____/ /____/|__/|__/\__,_/ .___/ +# /_/ +# figlet -fslant +#-------------------------------------------------------------------------------- +#--****************************************************************************** + +# 0x800C1C0008010C3F +scom 0x800.0b(tx_mode_pg)(tx_grp0)(lane_na).0x(abus_gcr_addr) { + bits, scom_data; + tx_msbswap, (ATTR_EI_BUS_TX_MSBSWAP & 0x01); +} + + +############################################################################################ +# END OF FILE +############################################################################################ diff --git a/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile index 3bd0800af..51b0de94a 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile @@ -1,45 +1,46 @@ -#-- $Id: p8.abus.scom.initfile,v 1.6 2013/01/22 02:57:21 thomsen Exp $ -#-- CHANGE HISTORY: -#-------------------------------------------------------------------------------- -#-- Version:|Author: | Date: | Comment: -#-- --------|--------|--------|-------------------------------------------------- -#-- 1.6 |thomsen |01/21/13|Removed ATTR_EI_BUS_RX_MSB_LSB_SWAP & ATTR_EI_BUS_TX_MSB_LSB_SWAP as those are old now -#-- | | |Removed non-mirrored mode settings in PRBS tap id's -#-- 1.5 |pmegan |09/27/12|Set rx_sls_timeout_sel to 0b001 per defect HW220752 -#-- | | |Set rx_sls_extend_sel to 0b100 on slave chip per defect HW220806 -#-- 1.4 |jmcgill |07/28/12|Simplify master/slave logic (node ID always unique) -#-- 1.3 |jmcgill |07/27/12|Edits to match scan initfle -#-- 1.2 |pmegan |07/11/12|Added ID in file header -#-- 1.1 |pmegan |07/09/12|Created initial version -#-- --------|--------|--------|-------------------------------------------------- -#-------------------------------------------------------------------------------- -# End of revision history -#-------------------------------------------------------------------------------- - -#--Master list of variables that can be used in this file is at: -#--<Attribute Definition Location> +#-- $Id: p8.abus.scom.initfile,v 1.7 2013/02/11 04:26:41 jmcgill Exp $ + + +#################################################################### +## +## Auto-genrated by fig2scominit.pl +## Based on SETUP_ID_MODE A_BUS_TR_HW +## from ../../logic/mesa_sim/fusion/run/IODUV_ABUS_WRAP.IODUV_ABUS_WRAP.figdb +## +## Created on Thu Jan 24 14:48:09 EST 2013, by derrin +#################################################################### + +## -- CHANGE HISTORY: + ## -------------------------------------------------------------------------------- + ## -- VersionID: |Author: | Date: | Comment: + ## -- -----------|---------|--------|------------------------------------------------- + ## -- mbs13011802| mbs |01-18-13| Added rx_fence to run_mode dial (HW236326) + ## -- mbs12121100| mbs |12-11-12| Added rx_prot_speed_slct and rx_c4_sel + ## -- smr12112700| SMR |11-27-12| Added rx_dyn_recal_overall_timeout_sel init to 0b001 + ## -- jfg12112101| jfg |11-21-12| Added Zcal inits + ## -- jfg12112100| jfg |11-21-12| Added CU pll modes + ## -- 12111300| berger |11-13-12| Updated with HW eyeopt and recal settings + ## -- 12062500| SMR |06-25-12| HW210654: Added rx_sls_timeout_sel default of 1 + ## -- jfg12041600 |jfg |- HW193450,HW197325,HW196562,HW197324 clkdist Layout updates + ## -- 11012500| mbs |01-25-12| Swizzle and typo fixes for HW191494, HW191518, HW188304 + ## -- 12011900| RJR |01-18-12| Added RX_CTL2_REGS FILE REFERENCES Issue HW164277 + ## -- 12011800| berger |01-19-12| Added SETUP_ID_MODE dials + ## -- 11112900| mbs |11-29-11| Fixed RX scramble mirror taps (HW186689) + ## -- 11121600| mbs |12-16-11| Initial version (copied from version 11112900 of iodsh_abus_wrap.fig) + ## -------------------------------------------------------------------------------- + SyntaxVersion = 1 -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- -#-- -#-- Includes -#-- Note: Must include the path to the .define file. -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- + + +#################################################################### +# Define File +#################################################################### include edi.io.define -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- -#-- -#-- Defines -#-- -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- + +define def_IS_HW = SYS.ATTR_IS_SIMULATION == 0; +define def_IS_VBU = SYS.ATTR_IS_SIMULATION == 1; define def_bus_id0 = (ATTR_CHIP_UNIT_POS == 0); define def_bus_id1 = (ATTR_CHIP_UNIT_POS == 1); @@ -48,447 +49,556 @@ define def_bus_id2 = (ATTR_CHIP_UNIT_POS == 2); define def_is_master = (TGT1.ATTR_FABRIC_NODE_ID < TGT2.ATTR_FABRIC_NODE_ID); define def_is_slave = (TGT1.ATTR_FABRIC_NODE_ID > TGT2.ATTR_FABRIC_NODE_ID); -# See p8.chipunit.scominfo file for details of how SCOM addresses are translated by Cronus and FW based on the target unit number -define def_rx_base_grp = rx_grp0; # -define def_tx_base_grp = tx_grp0; # -#--****************************************************************************** + #------------------------------------------------------------------------------------- -# _____ __ ________ -# / ___/___ / /___ ______ / _/ __ \ -# \__ \/ _ \/ __/ / / / __ \ / // / / / -# ___/ / __/ /_/ /_/ / /_/ / _/ // /_/ / -# /____/\___/\__/\__,_/ .___/ /___/_____/ -# /_/ banner2 -fslant +# __ ___ __ __ ___ __ +# / |/ /___ ______/ /____ _____ / |/ /___ ____/ /__ +# / /|_/ / __ `/ ___/ __/ _ \/ ___/ / /|_/ / __ \/ __ / _ \ +# / / / / /_/ (__ ) /_/ __/ / / / / / /_/ / /_/ / __/ +# /_/ /_/\__,_/____/\__/\___/_/ /_/ /_/\____/\__,_/\___/ #------------------------------------------------------------------------------------- -#--****************************************************************************** -#### X bus -> 4 CG's, 20 lanes, A bus -> 3 CG's, 23 lanes , DMI bus -> 4 CG's, 24 lanes -# -# Target unit number based address translation method - fAPI translates group address and lower scom address based on target unit num passed in -# - So the scom address group number must be 000011 for RX and 100011 for TX and lower 32-bits of scom address needs to be DMI0 address -#--******************************************************************************************** -#-- rx_bus_id, tx_bus_id -#--******************************************************************************************** -scom 0x800.0b(rx_id1_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_bus_id , 0b000000, (def_bus_id0); # - rx_bus_id , 0b000001, (def_bus_id1); # - rx_bus_id , 0b000010, (def_bus_id2); # - rx_group_id, 0b000000, any; # GroupID is always 000000 on all RX Abus clk groups -} -scom 0x800.0b(tx_id1_pg)(def_tx_base_grp)(lane_na).0x(abus_gcr_addr){ - bits, scom_data, expr; - tx_bus_id , 0b000000, (def_bus_id0); # - tx_bus_id , 0b000001, (def_bus_id1); # - tx_bus_id , 0b000010, (def_bus_id2); # - tx_group_id, 0b100000, any; # GroupID is always 100000 on all TX Abus channels -} -#--******************************************************************************************** -#-- rx_last_group_id, tx_last_group_id -#--******************************************************************************************** -scom 0x800.0b(rx_id2_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ - bits, scom_data; - rx_last_group_id , 0b000000; # Every clk group is 000000 for RX -} -scom 0x800.0b(tx_id2_pg)(def_tx_base_grp)(lane_na).0x(abus_gcr_addr){ - bits, scom_data; - tx_last_group_id , 0b100000; # Every clk group is 100000 for TX -} #--********************************************************************************************* -#-- rx_start_lane_id, rx_end_lane_id +#-- rx_mode_pg: rx_master_mode #--********************************************************************************************* -# 23-bits -scom 0x800.0b(rx_id3_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ - bits, scom_data; - rx_start_lane_id , 0b0000000; # Each RX CG on Abus starts with lane 0 - rx_end_lane_id, 0b0010110; # Each RX CG on ABus ends with lane 22 +scom 0x800.0b(rx_mode_pg)(rx_grp0)(lane_na).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_master_mode, 0b1, (def_is_master); + rx_master_mode, 0b0, (def_is_slave); } -scom 0x800.0b(tx_id3_pg)(def_tx_base_grp)(lane_na).0x(abus_gcr_addr){ - bits, scom_data; - tx_start_lane_id , 0b0000000; # Each TX CG on Abus starts with lane 0 - tx_end_lane_id, 0b0010110; # Each TX CG on Abus ends with lane 22 + + +#RX0.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP +scom 0x800B780008010C3F { + bits, scom_data, expr; + rx_amin_cfg, 0b010, def_IS_HW; + rx_amin_cfg, 0b000, def_IS_VBU; + rx_anap_cfg, 0b10, def_IS_HW; + rx_anap_cfg, 0b00, def_IS_VBU; + rx_h1ap_cfg, 0b011, def_IS_HW; + rx_h1ap_cfg, 0b000, def_IS_VBU; + rx_peak_cfg, 0b10, def_IS_HW; + rx_peak_cfg, 0b00, def_IS_VBU; } -#--********************************************************************************************* -#-- rx_tx_bus_width, rx_rx_bus_width -#--********************************************************************************************* -# 23-bits -scom 0x800.0b(rx_tx_bus_info_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ - bits, scom_data; - rx_tx_bus_width, 0b0010111; # Each TX CG on Abus is 23-bits - rx_rx_bus_width, 0b0010111; # Each RX CG on Abus is 23-bits -} -#----------------------------------------------------------------------------------------------- -# ______ -# / ____/__ ____ ________ #### TODO: This needs to be set in the scaninit file and io_hard_reset factored into all reinit scenarios -# / /_ / _ \/ __ \/ ___/ _ \ -# / __/ / __/ / / / /__/ __/ -# /_/ \___/_/ /_/\___/\___/ banner2 -fslant -#---------------------------------------------------------------------------------------------- -scom 0x800.0b(rx_fence_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ - bits , scom_data; - rx_fence, 0b1; -} -#---------------------------------------------------------------------------------------------- -# __ ____ _ __ __ -# / / ____ _____ ___ / __ \(_)________ _/ /_ / /__ _____ -# / / / __ `/ __ \/ _ \ / / / / / ___/ __ `/ __ \/ / _ \/ ___/ -# / /___/ /_/ / / / / __/ / /_/ / (__ ) /_/ / /_/ / / __(__ ) -# /_____/\__,_/_/ /_/\___/ /_____/_/____/\__,_/_.___/_/\___/____/ banner2 -fslant -#---------------------------------------------------------------------------------------------- -#--********************************************************************************************* -#-- rx_lane_disabled_vec_0_15, rx_lane_disabled_vec_16_31 -#--********************************************************************************************* -# RX = 23-bits -scom 0x800.0b(rx_lane_disabled_vec_0_15_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ - bits, scom_data; - rx_lane_disabled_vec_0_15, 0b0000000000000000; # Each RX CG on Abus has lanes 0-15 enabled (ie. disabled=0) + +#RX0.RXCTL.RX_CTL_REGS.RX_DFE_TIMERS_PP +scom 0x800B800008010C3F { + bits, scom_data, expr; + rx_init_tmr_cfg, 0b100, def_IS_HW; + rx_init_tmr_cfg, 0b000, def_IS_VBU; } -scom 0x800.0b(rx_lane_disabled_vec_16_31_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ - bits, scom_data; - rx_lane_disabled_vec_16_31, 0b0000000111111111; # Each RX CG on Abus has lanes 16-22 enabled (ie. disabled=0) + +#RX0.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_CONFIG_PG +scom 0x800A180008010C3F { + bits, scom_data; + rx_dyn_recal_overall_timeout_sel, 0b001; } -#--********************************************************************************************* -#-- tx_lane_disabled_vec_0_15, tx_lane_disabled_vec_16_31 -#--********************************************************************************************* -# TX = 23-bits -scom 0x800.0b(tx_lane_disabled_vec_0_15_pg)(def_tx_base_grp)(lane_na).0x(abus_gcr_addr){ - bits, scom_data; - tx_lane_disabled_vec_0_15, 0b0000000000000000; # Each RX CG on Abus has lanes 0-15 enabled (ie. disabled=0) + +#RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG +scom 0x8009D80008010C3F { + bits, scom_data; + rx_dyn_rpr_bad_lane_max, 0b0001111; + rx_dyn_rpr_enc_bad_data_lane_width, 0b101; + rx_dyn_rpr_err_cntr1_duration, 0b1001; } -scom 0x800.0b(tx_lane_disabled_vec_16_31_pg)(def_tx_base_grp)(lane_na).0x(abus_gcr_addr){ - bits, scom_data; - tx_lane_disabled_vec_16_31, 0b0000000111111111; # Each RX CG on Abus has lanes 16-22 enabled (ie. disabled=0) + +#RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG +scom 0x800AE00008010C3F { + bits, scom_data; + rx_dyn_rpr_bad_bus_max, 0b0011111; + rx_dyn_rpr_err_cntr2_duration, 0b0110; } -#------------------------------------------------------------------------------------- -# __ ___ ____ __ __ -# / |/ /___ __ __ / __ )____ _____/ / / / ____ _____ ___ _____ -# / /|_/ / __ `/ |/_/ / __ / __ `/ __ / / / / __ `/ __ \/ _ \/ ___/ -# / / / / /_/ /> < / /_/ / /_/ / /_/ / / /___/ /_/ / / / / __(__ ) -# /_/ /_/\__,_/_/|_| /_____/\__,_/\__,_/ /_____/\__,_/_/ /_/\___/____/ banner2 -fslant -#------------------------------------------------------------------------------------- -#--********************************************************************************************* -#-- rx_wtr_max_bad_lanes, tx_max_bad_lanes -#--********************************************************************************************* -# RX = 1 spare -scom 0x800.0b(rx_wiretest_laneinfo_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ - bits, scom_data; - rx_wtr_max_bad_lanes, 0b00001; # Each RX CG on Abus has 1 spare lane + +#RX0.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG +scom 0x800A380008010C3F { + bits, scom_data, expr; + rx_eo_enable_ber_test, 0b1, def_IS_HW; + rx_eo_enable_ber_test, 0b0, def_IS_VBU; + rx_eo_enable_ctle_cal, 0b1, def_IS_HW; + rx_eo_enable_ctle_cal, 0b0, def_IS_VBU; + rx_eo_enable_ddc, 0b1, def_IS_HW; + rx_eo_enable_ddc, 0b0, def_IS_VBU; + rx_eo_enable_dfe_h1_cal, 0b0, any; + rx_eo_enable_final_l2u_adj, 0b1, any; + rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW; + rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU; + rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW; + rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU; + rx_eo_enable_result_check, 0b1, def_IS_HW; + rx_eo_enable_result_check, 0b0, def_IS_VBU; + rx_eo_enable_vga_cal, 0b1, def_IS_HW; + rx_eo_enable_vga_cal, 0b0, def_IS_VBU; } -# TX = 1 spare -scom 0x800.0b(tx_mode_pg)(def_tx_base_grp)(lane_na).0x(abus_gcr_addr){ - bits, scom_data; - tx_max_bad_lanes, 0b00001; # Each TX CG on Abus has 1 spare lane + +#RX0.RXCTL.RX_CTL_REGS.RX_FENCE_PG +scom 0x8009A80008010C3F { + bits, scom_data; + rx_fence, 0b1; } -#------------------------------------------------------------------------------------- -# ____ ____ _ ______ ____ _ -# / __ \__ ______ / __ \___ ____ ____ _(_)____ /_ __/___ _/ / /_ __(_)___ ____ _ -# / / / / / / / __ \ / /_/ / _ \/ __ \/ __ `/ / ___/ / / / __ `/ / / / / / / __ \/ __ `/ -# / /_/ / /_/ / / / / / _, _/ __/ /_/ / /_/ / / / / / / /_/ / / / /_/ / / / / / /_/ / -# /_____/\__, /_/ /_/ /_/ |_|\___/ .___/\__,_/_/_/ /_/ \__,_/_/_/\__, /_/_/ /_/\__, / -# /____/ /_/ /____/ /____/ banner2 -fslant -#------------------------------------------------------------------------------------- -#--********************************************************************************************* -#-- rx_dyn_rpr_err_tallying1_pg: rx_dyn_rpr_bad_lane_max, rx_dyn_rpr_err_cntr1_duration, rx_dyn_rpr_enc_bad_data_lane_width -#--********************************************************************************************* -scom 0x800.0b(rx_dyn_rpr_err_tallying1_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ - bits, scom_data; - rx_dyn_rpr_bad_lane_max, 0b0001111; # - rx_dyn_rpr_err_cntr1_duration, 0b1001; # tap 9 - rx_dyn_rpr_enc_bad_data_lane_width, 0b101; # + +#RX0.RXCTL.RX_CTL_REGS.RX_ID1_PG +scom 0x8008500008010C3F { + bits, scom_data, expr; + rx_bus_id, 0b000010, def_bus_id2; + rx_bus_id, 0b000001, def_bus_id1; + rx_bus_id, 0b000000, def_bus_id0; + rx_group_id, 0b000000, any; } -#--********************************************************************************************* -#-- rx_dyn_rpr_err_tallying2_pg: rx_dyn_rpr_bad_bus_max, rx_dyn_rpr_err_cntr2_duration -#--********************************************************************************************* -scom 0x800.0b(rx_dyn_rpr_err_tallying2_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ - bits, scom_data; - rx_dyn_rpr_bad_bus_max, 0b0011111; # - rx_dyn_rpr_err_cntr2_duration, 0b0110; # tap 6 + +#RX0.RXCTL.RX_CTL_REGS.RX_ID2_PG +scom 0x8008580008010C3F { + bits, scom_data; + rx_last_group_id, 0b000000; } -#------------------------------------------------------------------------------------- -# __ ___ __ __ ___ __ -# / |/ /___ ______/ /____ _____ / |/ /___ ____/ /__ -# / /|_/ / __ `/ ___/ __/ _ \/ ___/ / /|_/ / __ \/ __ / _ \ -# / / / / /_/ (__ ) /_/ __/ / / / / / /_/ / /_/ / __/ -# /_/ /_/\__,_/____/\__/\___/_/ /_/ /_/\____/\__,_/\___/ -#------------------------------------------------------------------------------------- -#--********************************************************************************************* -#-- rx_mode_pg: rx_master_mode -#--********************************************************************************************* -scom 0x800.0b(rx_mode_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_master_mode, 0b1, (def_is_master); - rx_master_mode, 0b0, (def_is_slave); + +#RX0.RXCTL.RX_CTL_REGS.RX_ID3_PG +scom 0x8008600008010C3F { + bits, scom_data; + rx_end_lane_id, 0b0010110; + rx_start_lane_id, 0b0000000; } -#------------------------------------------------------------------------------------- -# ____ ____ ____ _____ ______ _____ __ __ -# / __ \/ __ \/ __ ) ___/ /_ __/___ _____ / ___/___ / /__ _____/ /______ -# / /_/ / /_/ / __ \__ \ / / / __ `/ __ \ \__ \/ _ \/ / _ \/ ___/ __/ ___/ -# / ____/ _, _/ /_/ /__/ / / / / /_/ / /_/ / ___/ / __/ / __/ /__/ /_(__ ) -# /_/ /_/ |_/_____/____/ /_/ \__,_/ .___/ /____/\___/_/\___/\___/\__/____/ banner2 -fslant -# /_/ -#------------------------------------------------------------------------------------- -# PER-LANE (RX) -#------------------------------------------------------------------------------------- -#--********************************************************************************************* -#-- rx_prbs_mode_pl: rx_prbs_tap_id -#--********************************************************************************************* -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_0).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_a; + +#RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG +scom 0x8009280008010C3F { + bits, scom_data; + rx_lane_disabled_vec_0_15, 0b0000000000000000; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_1).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_b; + +#RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG +scom 0x8009300008010C3F { + bits, scom_data; + rx_lane_disabled_vec_16_31, 0b0000000111111111; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_2).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_c; + +#RX0.RXCTL.RX_CTL_REGS.RX_MISC_ANALOG_PG +scom 0x8009C00008010C3F { + bits, scom_data, expr; + rx_c4_sel, 0b00, def_IS_HW; + rx_c4_sel, 0b11, def_IS_VBU; + rx_prot_speed_slct, 0b0, def_IS_HW; + rx_prot_speed_slct, 0b1, def_IS_VBU; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_3).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_d; + +#RX0.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG +scom 0x800AB80008010C3F { + bits, scom_data, expr; + rx_rc_enable_ber_test, 0b1, def_IS_HW; + rx_rc_enable_ber_test, 0b0, def_IS_VBU; + rx_rc_enable_ctle_cal, 0b1, def_IS_HW; + rx_rc_enable_ctle_cal, 0b0, def_IS_VBU; + rx_rc_enable_ddc, 0b1, def_IS_HW; + rx_rc_enable_ddc, 0b0, def_IS_VBU; + rx_rc_enable_dfe_h1_cal, 0b0, any; + rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW; + rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU; + rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW; + rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU; + rx_rc_enable_result_check, 0b1, def_IS_HW; + rx_rc_enable_result_check, 0b0, def_IS_VBU; + rx_rc_enable_vga_cal, 0b1, def_IS_HW; + rx_rc_enable_vga_cal, 0b0, def_IS_VBU; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_4).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_e; + +#RX0.RXCTL.RX_CTL_REGS.RX_RECAL_TO2_PP +scom 0x800B980008010C3F { + bits, scom_data, expr; + rx_recal_timeout_sel_g, 0b0111, def_IS_HW; + rx_recal_timeout_sel_g, 0b0110, def_IS_VBU; + rx_recal_timeout_sel_h, 0b0110, def_IS_HW; + rx_recal_timeout_sel_h, 0b1000, def_IS_VBU; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_5).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_f; + +#RX0.RXCTL.RX_CTL_REGS.RX_RECAL_TO3_PP +scom 0x800BA00008010C3F { + bits, scom_data, expr; + rx_recal_timeout_sel_i, 0b0111, def_IS_HW; + rx_recal_timeout_sel_i, 0b1000, def_IS_VBU; + rx_recal_timeout_sel_l, 0b0100, def_IS_HW; + rx_recal_timeout_sel_l, 0b0110, def_IS_VBU; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_6).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_g; + +#RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP +scom 0x800B600008010C3F { + bits, scom_data, expr; + rx_servo_timeout_sel_d, 0b1010, def_IS_HW; + rx_servo_timeout_sel_d, 0b1000, def_IS_VBU; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_7).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_h; + +#RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP +scom 0x800B680008010C3F { + bits, scom_data, expr; + rx_servo_timeout_sel_f, 0b0001, def_IS_HW; + rx_servo_timeout_sel_f, 0b0110, def_IS_VBU; + rx_servo_timeout_sel_g, 0b0111, def_IS_HW; + rx_servo_timeout_sel_g, 0b0100, def_IS_VBU; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_8).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_a; + +#RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO3_PP +scom 0x800B700008010C3F { + bits, scom_data, expr; + rx_servo_timeout_sel_i, 0b0111, def_IS_HW; + rx_servo_timeout_sel_i, 0b1000, def_IS_VBU; + rx_servo_timeout_sel_k, 0b0111, def_IS_HW; + rx_servo_timeout_sel_k, 0b1000, def_IS_VBU; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_9).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_b; + +#RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG +scom 0x8008980008010C3F { + bits, scom_data; + rx_sls_timeout_sel, 0b001; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_10).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_c; + +#RX0.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG +scom 0x8009980008010C3F { + bits, scom_data; + rx_rx_bus_width, 0b0010111; + rx_tx_bus_width, 0b0010111; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_11).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_d; + +#RX0.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG +scom 0x8009580008010C3F { + bits, scom_data; + rx_wtr_max_bad_lanes, 0b00001; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_12).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_d; + +#RX0.RXCTL.RX_CTL_REGS.RX_WIRETEST_PLL_CNTL_PG +scom 0x800A300008010C3F { + bits, scom_data, expr; + rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW; + rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU; + rx_wt_cu_pll_reset, 0b0, def_IS_HW; + rx_wt_cu_pll_reset, 0b1, def_IS_VBU; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_13).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_c; + +#RX0.RXPACKS#0.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B01508010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b001; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_14).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_b; + +#RX0.RXPACKS#0.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B01408010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b010; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_15).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_a; + +#RX0.RXPACKS#0.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B01608010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b000; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_16).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_h; + +#RX0.RXPACKS#0.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B00A08010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b010; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_17).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_g; + +#RX0.RXPACKS#0.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B00B08010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b011; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_18).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_f; + +#RX0.RXPACKS#0.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B00908010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b001; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_19).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_e; + +#RX0.RXPACKS#1.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B01208010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b100; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_20).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_d; + +#RX0.RXPACKS#1.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B01708010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b000; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_21).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_c; + +#RX0.RXPACKS#1.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B00708010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b111; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_22).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_b; + +#RX0.RXPACKS#1.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B01308010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b011; } -scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_23).0x(abus_gcr_addr){ - bits, scom_data; - rx_prbs_tap_id, rx_prbs_tap_id_pattern_a; + +#RX0.RXPACKS#1.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B00608010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b110; } -#------------------------------------------------------------------------------------- -# PER-LANE (TX) -#------------------------------------------------------------------------------------- -#--********************************************************************************************* -#-- tx_prbs_mode_pl: tx_prbs_tap_id -#--********************************************************************************************* -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_0).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_a; + +#RX0.RXPACKS#1.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B00808010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b000; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_1).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_b; + +#RX0.RXPACKS#2.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B00508010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b101; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_2).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_c; + +#RX0.RXPACKS#2.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B00308010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b011; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_3).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_d; + +#RX0.RXPACKS#2.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B01108010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b101; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_4).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_e; + +#RX0.RXPACKS#2.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B00408010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b100; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_5).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_f; + +#RX0.RXPACKS#2.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B01008010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b110; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_6).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_g; + +#RX0.RXPACKS#2.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B00F08010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b111; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_7).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_h; + +#RX0.RXPACKS#3.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B00008010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b000; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_8).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_a; + +#RX0.RXPACKS#3.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B00208010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b010; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_9).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_b; + +#RX0.RXPACKS#3.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B00108010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b001; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_10).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_c; + +#RX0.RXPACKS#3.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B00E08010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b000; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_11).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_d; + +#RX0.RXPACKS#3.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B00C08010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b010; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_12).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_d; + +#RX0.RXPACKS#3.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B00D08010C3F { + bits, scom_data; + rx_prbs_tap_id, 0b001; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_13).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_c; + +#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG +scom 0x800CC40008010C3F { + bits, scom_data; + tx_drv_clk_pattern_gcrmsg, 0b00; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_14).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_b; + +#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID1_PG +scom 0x800C940008010C3F { + bits, scom_data, expr; + tx_bus_id, 0b000010, def_bus_id2; + tx_bus_id, 0b000001, def_bus_id1; + tx_bus_id, 0b000000, def_bus_id0; + tx_group_id, 0b100000, any; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_15).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_a; + +#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID2_PG +scom 0x800C9C0008010C3F { + bits, scom_data; + tx_last_group_id, 0b100000; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_16).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_h; + +#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID3_PG +scom 0x800CA40008010C3F { + bits, scom_data; + tx_end_lane_id, 0b0010110; + tx_start_lane_id, 0b0000000; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_17).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_g; + +#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG +scom 0x800D1C0008010C3F { + bits, scom_data; + tx_lane_disabled_vec_0_15, 0b0000000000000000; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_18).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_f; + +#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG +scom 0x800D240008010C3F { + bits, scom_data; + tx_lane_disabled_vec_16_31, 0b0000000111111111; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_19).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_e; + +#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_MODE_PG +scom 0x800C1C0008010C3F { + bits, scom_data; + tx_max_bad_lanes, 0b00001; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_20).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_d; + +#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004341108010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b101; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_21).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_c; + +#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004341208010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b100; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_22).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_b; + +#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004341608010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b000; } -scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_23).0x(abus_gcr_addr){ - bits, scom_data; - tx_prbs_tap_id, tx_prbs_tap_id_pattern_a; + +#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340008010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b000; } -#------------------------------------------------------------------------------------- -# ____ __ __ -# / __ \/ / / / -# / /_/ / / / / -# / ____/ /___/ /___ -# /_/ /_____/_____/ banner2 -fslant -#------------------------------------------------------------------------------------- -#--********************************************************************************************* -#-- rx_wiretest_pll_cntl_pg: rx_wt_cu_pll_reset, rx_wt_cu_pll_pgooddly -#--********************************************************************************************* -scom 0x800.0b(rx_wiretest_pll_cntl_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ - bits, scom_data; - rx_wt_cu_pll_reset, 0b0; # Put PLL in disabled state until Wiretest is started. - rx_wt_cu_pll_pgooddly, 0b001; # 50ns delay +#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004341008010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b110; } -#------------------------------------------------------------------------------------- -# ____ _ __________ ____ __ __ -# / __ \_____(_) _____ / ____/ / /__ / __ \____ _/ /_/ /____ _________ -# / / / / ___/ / | / / _ \ / / / / //_/ / /_/ / __ `/ __/ __/ _ \/ ___/ __ \ -# / /_/ / / / /| |/ / __/ / /___/ / ,< / ____/ /_/ / /_/ /_/ __/ / / / / / -# /_____/_/ /_/ |___/\___/ \____/_/_/|_| /_/ \__,_/\__/\__/\___/_/ /_/ /_/ -#------------------------------------------------------------------------------------- -#--********************************************************************************************* -#-- tx_clk_cntl_gcrmsg_pg: tx_drv_clk_pattern_gcrmsg -#--********************************************************************************************* -scom 0x800.0b(tx_clk_cntl_gcrmsg_pg)(def_tx_base_grp)(lane_na).0x(abus_gcr_addr){ - bits, scom_data; - tx_drv_clk_pattern_gcrmsg, 0b00; # Drive 0's to start out + +#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340108010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b001; } -#------------------------------------------------------------------------------------- -# ____ _ __ _______ _____ __ -# / __ \ |/ / /_ __(_)___ ___ ___ _____ / ___/___ / / -# / /_/ / / / / / / __ `__ \/ _ \/ ___/ \__ \/ _ \/ / -# / _, _/ | / / / / / / / / / __/ / ___/ / __/ / -#/_/ |_/_/|_| /_/ /_/_/ /_/ /_/\___/_/ /____/\___/_/ -#------------------------------------------------------------------------------------- -#--********************************************************************************************* -#-- rx_timeout_sel_pg: rx_sls_timeout_sel -#--********************************************************************************************* -scom 0x800.0b(rx_timeout_sel_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ - bits, scom_data; - rx_sls_timeout_sel, 0b001; # Set this entry to 0b001 per defect HW220752 + +#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004341408010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b010; } -#------------------------------------------------------------------------------------- -# ____ _ __ _____ __ _____ ______ __ __ _____ __ -# / __ \ |/ / / ___// / / ___/ / ____/ __/ /____ ____ ____/ / / ___/___ / / -# / /_/ / / \__ \/ / \__ \ / __/ | |/_/ __/ _ \/ __ \/ __ / \__ \/ _ \/ / -# / _, _/ | ___/ / /______/ / / /____> </ /_/ __/ / / / /_/ / ___/ / __/ / -#/_/ |_/_/|_| /____/_____/____/ /_____/_/|_|\__/\___/_/ /_/\__,_/ /____/\___/_/ -#------------------------------------------------------------------------------------- -#--********************************************************************************************* -#-- rx_spare_mode_pg: rx_sls_extend_sel -#--********************************************************************************************* -scom 0x800.0b(rx_spare_mode_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ - bits, scom_data, expr; - rx_sls_extend_sel, 0b100, (def_is_slave); #Set this entry to 0b100 per defect HW220806 + +#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004341508010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b001; } -############################################################################################ -# END OF FILE -############################################################################################ +#TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340E08010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b000; +} + +#TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340908010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b001; +} + +#TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340208010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b010; +} + +#TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004341308010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b011; +} + +#TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340308010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b011; +} + +#TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340508010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b101; +} + +#TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340408010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b100; +} + +#TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340D08010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b001; +} + +#TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340808010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b000; +} + +#TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340608010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b110; +} + +#TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340708010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b111; +} + +#TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340C08010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b010; +} + +#TX_WRAP.TX0.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340B08010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b011; +} + +#TX_WRAP.TX0.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340A08010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b010; +} + +#TX_WRAP.TX0.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340F08010C3F { + bits, scom_data; + tx_prbs_tap_id, 0b111; +} + + +###################################### +## END OF FILE +####################################### diff --git a/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile new file mode 100644 index 000000000..63759d6da --- /dev/null +++ b/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile @@ -0,0 +1,144 @@ +#-- $Id: p8.xbus.custom.scom.initfile,v 1.1 2013/02/04 19:52:00 thomsen Exp $ +#-- CHANGE HISTORY: +#-------------------------------------------------------------------------------- +#-- Version:|Author: | Date: | Comment: +#-- --------|--------|--------|-------------------------------------------------- +#-- 1.1 |thomsen |01/29/13|Created initial version +#-- --------|--------|--------|-------------------------------------------------- +#-------------------------------------------------------------------------------- +# End of revision history +#-------------------------------------------------------------------------------- + +#--Master list of variables that can be used in this file is at: +#--<Attribute Definition Location> + +SyntaxVersion = 1 + +#-- ----------------------------------------------------------------------------- +#--****************************************************************************** +#-- ----------------------------------------------------------------------------- +#-- +#-- Includes +#-- Note: Must include the path to the .define file. +#-- ----------------------------------------------------------------------------- +#--****************************************************************************** +#-- ----------------------------------------------------------------------------- +include ei4.io.define + +#-- ----------------------------------------------------------------------------- +#--****************************************************************************** +#-- ----------------------------------------------------------------------------- +#-- +#-- Defines +#-- +#-- ----------------------------------------------------------------------------- +#--****************************************************************************** +#-- ----------------------------------------------------------------------------- + +## ./iotk put rx_fence=1 +## 0x +#scom 0x800.0b(rx_fence_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr,xbus1_gcr_addr,xbus2_gcr_addr,xbus3_gcr_addr) { +#bits, scom_data; +#rx_fence, 0b1; +#} +# +## ./iotk put rx_c4_sel=00 +## ./iotk put rx_prot_speed_slct=1 +## 0x8009C00002011E3F +#scom 0x800.0b(rx_misc_analog_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr,xbus1_gcr_addr,xbus2_gcr_addr,xbus3_gcr_addr) { +#bits, scom_data; +#rx_c4_sel, 0b00; +#rx_prot_speed_slct, 0b1; +#} +## ./iotk put rx_servo_timeout_sel_D=1001 +## 0x800B600002011E3F +#scom 0x800.0b(rx_servo_to1_pp)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr,xbus1_gcr_addr,xbus2_gcr_addr,xbus3_gcr_addr) { +#bits, scom_data; +#rx_servo_timeout_sel_d, 0b1001; +#} +## ./iotk put rx_servo_timeout_sel_H=1110 +## 0x800B680002011E3F +#scom 0x800.0b(rx_servo_to2_pp)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr,xbus1_gcr_addr,xbus2_gcr_addr,xbus3_gcr_addr) { +#bits, scom_data; +#rx_servo_timeout_sel_h, 0b1110; +#} +## ./iotk put rx_servo_timeout_sel_I=1011 +## ./iotk put rx_servo_timeout_sel_J=1100 +## 0x800B700002011E3F +#scom 0x800.0b(rx_servo_to3_pp)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr,xbus1_gcr_addr,xbus2_gcr_addr,xbus3_gcr_addr) { +#bits, scom_data; +#rx_servo_timeout_sel_i, 0b1011; +#rx_servo_timeout_sel_j, 0b1100; +#rx_servo_timeout_sel_k, 0b1101; +#} +## ./iotk put rx_wt_timeout_sel=111 +## ./iotk put rx_ds_bl_timeout_sel=101 +## ./iotk put rx_ds_timeout_sel=110 +##./iotk put rx_sls_timeout_sel=111 +## 0x8008980002011E3F +#scom 0x800.0b(rx_timeout_sel_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr,xbus1_gcr_addr,xbus2_gcr_addr,xbus3_gcr_addr) { +#bits, scom_data; +#rx_wt_timeout_sel, 0b111; +#rx_ds_bl_timeout_sel, 0b101; +#rx_ds_timeout_sel, 0b110; +#rx_sls_timeout_sel, 0b001; +#} +# +## ./iotk put rx_bit_lock_timeout_sel=110 +## 0x800B080002011E3F +#scom 0x800.0b(rx_mode1_pp)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr,xbus1_gcr_addr,xbus2_gcr_addr,xbus3_gcr_addr) { +#bits, scom_data; +#rx_bit_lock_timeout_sel, 0b110; +#} +## ./iotk put rx_eo_offset_timeout_sel=111 +## ./iotk put rx_eo_amp_timeout_sel=111 +## ./iotk put rx_eo_ctle_timeout_sel=111 +## ./iotk put rx_eo_h1ap_timeout_sel=111 +## ./iotk put rx_eo_ddc_timeout_sel=111 +## 0x8009100002011E3F +#scom 0x800.0b(rx_timeout_sel1_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr,xbus1_gcr_addr,xbus2_gcr_addr,xbus3_gcr_addr) { +#bits, scom_data; +#rx_eo_offset_timeout_sel, 0b111; +#rx_eo_amp_timeout_sel, 0b111; +#rx_eo_ctle_timeout_sel, 0b111; +#rx_eo_h1ap_timeout_sel, 0b111; +#rx_eo_ddc_timeout_sel, 0b111; +#} +# +# +## 800A380002011E3F +#scom 0x800.0b(rx_eo_step_cntl_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr,xbus1_gcr_addr,xbus2_gcr_addr,xbus3_gcr_addr) { +#bits, scom_data; +#rx_eo_enable_latch_offset_cal, 0b1; +#rx_eo_enable_ctle_cal, 0b1; +#rx_eo_enable_vga_cal, 0b1; +#rx_eo_enable_dfe_h1_cal, 0b1; +#rx_eo_enable_h1ap_tweak, 0b1; +#rx_eo_enable_ddc, 0b1; +#rx_eo_enable_final_l2u_adj, 0b1; +#rx_eo_enable_ber_test, 0b1; +#rx_eo_enable_result_check, 0b1; +#} +# +#scom 0x800.0b(rx_eo_convergence_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr,xbus1_gcr_addr,xbus2_gcr_addr,xbus3_gcr_addr) { +#bits, scom_data; +#rx_eo_converged_end_count, 0b111; +#} +# +## 0x800AB80002011E3F +#scom 0x800.0b(rx_rc_step_cntl_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr,xbus1_gcr_addr,xbus2_gcr_addr,xbus3_gcr_addr) { +#bits, scom_data; +#rx_rc_enable_latch_offset_cal, 0b1; +#rx_rc_enable_ctle_cal, 0b1; +#rx_rc_enable_vga_cal, 0b1; +#rx_rc_enable_h1ap_tweak, 0b1; +#rx_rc_enable_ddc, 0b1; +#rx_rc_enable_ber_test, 0b1; +#rx_rc_enable_result_check, 0b1; +##rx_rc_enable_dfe_h1_cal, 0b0; # Leave DFE off during recal for now +#} + + +############################################################################################ +# END OF FILE +############################################################################################ diff --git a/src/usr/hwpf/hwp/initfiles/p8.xbus.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.xbus.scom.initfile index 8c876c75d..9b5a593d9 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.xbus.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.xbus.scom.initfile @@ -1,859 +1,1997 @@ -#-- $Id: p8.xbus.scom.initfile,v 1.4 2012/09/27 15:14:37 ttnguyen Exp $ -#-- CHANGE HISTORY: -#-------------------------------------------------------------------------------- -#-- Version:|Author: | Date: | Comment: -#-- --------|--------|--------|-------------------------------------------------- -#-- 1.4 |pmegan |09/27/12|Set rx_sls_timeout_sel to 0b001 per defect HW220752 -#-- | | |Set rx_sls_extend_sel to 0b100 on slave chip per defect HW220806 -#-- 1.3 |thomsen |07/31/12|Removed mirrored PRBS tap entries since Xbus doesn't support end-for-end swapping -#-- | | |Changed per-group writes with the same data being written into all groups into group broadcast writes to save scom's -#-- 1.2 |jmcgill |07/27/12|Cleanup to run on VBU, edit to match scan initfile -#-- | | |Simplify master/slave logic (chip ID always unique) -#-- 1.1 |pmegan |07/10/12|Created initial version -#-- --------|--------|--------|-------------------------------------------------- -#-------------------------------------------------------------------------------- -# End of revision history -#-------------------------------------------------------------------------------- - -#--Master list of variables that can be used in this file is at: -#--<Attribute Definition Location> -#-- ATTR_EI_BUS_RX_MSB_LSB_SWAP is 0 for setting RX PRBS TapID's to Non-Mirrored Mode and 1 for setting to Mirrored Mode. It comes from the MRW. -#-- ATTR_EI_BUS_TX_MSB_LSB_SWAP is 0 for setting TX PRBS TapID's to Non-Mirrored Mode and 1 for setting to Mirrored Mode. It comes from the MRW. +#-- $Id: p8.xbus.scom.initfile,v 1.6 2013/02/06 22:20:58 thomsen Exp $ + + +#################################################################### +## +## Auto-genrated by fig2scominit.pl +## Based on SETUP_ID_MODE X_BUS_8B_TR_HW RX_MASTER_MODE MASTER +## from ../../logic/mesa_sim/fusion/run/IOEPC_XBUS_WRAP.IOEPC_XBUS_WRAP.figdb +## +## Created on Wed Feb 6 11:20:13 EST 2013, by derrin +#################################################################### + +## -- CHANGE HISTORY: + ## -------------------------------------------------------------------------------- + ## -- Version:|Author: | Date: | Comment: + ## -- --------|---------|--------|------------------------------------------------- + ## -- 13011802| mbs |01-18-13| Added rx_fence to run_mode dial (HW236326) + ## -- 12112700| SMR |11-27-12| HW20806: Added rx_sls_extend_sel default of 0b101 (slave side only!) + ## -- 12111300| berger |11-13-12| Updated with HW eyeopt and recal settings + ## -- 12062500| SMR |06-25-12| HW210654: Added rx_sls_timeout_sel default of 1 + ## -- 12011800| RJR |01-18-12| Added RX_CTL2_REGS FILE REFERENCES Issue HW164277 + ## -- 12010300| berger |01-03-12| HW184227: Added SETUP_ID_MODE dials + ## -- 11122000| berger |12-20-11| HW186823: removed timer settings, set in regs + ## -- 11121500| thomsen |12-15-11| Added Per-Pack GCR SCOM Addresses for Regchk (HW188381,HW182867) + ## -- | | | Removed 0x0000040000000000 from TX address definitions since it is in the lower level figtree files (HW187781,HW187893) + ## -- 11122000| berger |12-20-11| HW186823: removed timer settings, set in regs + ## -- 11121500| thomsen |12-15-11| Added Per-Pack GCR SCOM Addresses for Regchk (HW188381,HW182867) + ## -- | | | Removed 0x0000040000000000 from TX address definitions since it is in the lower level figtree files (HW187781,HW187893) + ## -- 11102100| SMR |10-21-11| HW181193: Added rx_dyn_rpr_enc_bad_data_lane_width register + ## -- 11092900| SMR |09-29-11| HW171978: Added dyn rpr error tallying defaults + ## -- 11052300| berger |05-23-11| Added ds_timeout_sel and servo timeouts + ## -- 11050300| SMR |05-02-11| Added tx_max_bad_lanes + ## -- 11041900| smc |04-19-11| Per Mike, commented out BUSCTL.BUS_CTL_REGS.base_addr (SCOM) += 0x0000000000000000; + ## -- 11022400| thomsen |02-24-11| Fixed 4-byte mode settings + ## -- 11021600| thomsen |02-16-11| Added Per-Bus, Per-Lane and Per-Group GCR SCOM addresses so Regchk would pass + ## -- 11020200| thomsen |02-02-11| Added 4 Byte Mode settings (disable all RXTX0 lanes and parts of RXTX1) and simplified RX_TX_SCRAMBLER_TAP_ID + ## -- 11020200| thomsen |02-02-11| Added RX & TX scramble/descramble tap ID settings + ## -- 11012500| berger |01-25-11| added TX lane disable and rx_bus_width fields, added missing SETUP_ID fields + ## -- 11011800| mbs |01-18-11| Added "*_GEN." to group hierarchy + ## -- 11010700| berger |01-07-11| added lane disable and max bad lane + ## -- 10121600| thomsen |12-16-10| Added RX_FENCE + ## -- 10120800| thomsen |12-08-10| Added TX_BUS_WIDTH + ## -- 10120100| thomsen |12-01-10| Fixed typo + ## -- 10112900| thomsen |11-29-10| Fixed BUS_ID's and GROUP_ID's for TX + ## -- 10102600| thomsen |10-26-10| Initial version + ## -------------------------------------------------------------------------------- + ## -- TODO: These need to be modified for Z + SyntaxVersion = 1 -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- -#-- -#-- Includes -#-- Note: Must include the path to the .define file. -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- + + +#################################################################### +# Define File +#################################################################### include ei4.io.define -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- -#-- -#-- Defines -#-- -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- + + define HW_EXPRESS = SYS.ATTR_IS_SIMULATION == 0; + define VBU_EXPRESS = SYS.ATTR_IS_SIMULATION == 1; + define def_bus_id0 = (ATTR_CHIP_UNIT_POS == 0); define def_bus_id1 = (ATTR_CHIP_UNIT_POS == 1); define def_bus_id2 = (ATTR_CHIP_UNIT_POS == 2); define def_bus_id3 = (ATTR_CHIP_UNIT_POS == 3); -define def_is_master = (TGT1.ATTR_FABRIC_CHIP_ID < TGT2.ATTR_FABRIC_CHIP_ID); -define def_is_slave = (TGT1.ATTR_FABRIC_CHIP_ID > TGT2.ATTR_FABRIC_CHIP_ID); -define def_xbus_4byte_mode = (SYS.ATTR_PROC_X_BUS_WIDTH == ENUM_ATTR_PROC_X_BUS_WIDTH_W4BYTE); # xbus_4byte mode -define def_xbus_8byte_mode = (SYS.ATTR_PROC_X_BUS_WIDTH == ENUM_ATTR_PROC_X_BUS_WIDTH_W8BYTE); # xbus_8byte mode -# See p8.chipunit.scominfo file for details of how SCOM addresses are translated by Cronus and FW based on the target unit number -define rx_grp = rx_grp0; # -define tx_grp = tx_grp0; # -define rx_grp_broadcast = 001111; -define tx_grp_broadcast = 101111; - -#--****************************************************************************** -#------------------------------------------------------------------------------------- -# _____ __ ________ -# / ___/___ / /___ ______ / _/ __ \ -# \__ \/ _ \/ __/ / / / __ \ / // / / / -# ___/ / __/ /_/ /_/ / /_/ / _/ // /_/ / -# /____/\___/\__/\__,_/ .___/ /___/_____/ -# /_/ banner2 -fslant -#------------------------------------------------------------------------------------- -#--****************************************************************************** -#### X bus -> 4 CG's, 20 lanes, A bus -> 3 CG's, 23 lanes , DMI bus -> 4 CG's, 24 lanes -# -#--******************************************************************************************** -#-- rx_bus_id, tx_bus_id -#--******************************************************************************************** -scom 0x800.0b(rx_id1_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - rx_bus_id , 0b000000, (def_xbus_8byte_mode); # BusID is 0x00 on RX0 when in 8-byte mode - rx_bus_id , 0b110000, (def_xbus_4byte_mode); # BusID is 0x30 on RX0 when in 4-byte mode since it isn't used and we don't want it decoding any GCR commands - rx_group_id, 0b000000, (def_xbus_8byte_mode); # GroupID is 0x00 on RX0 when in 8-byte mode - rx_group_id, 0b110000, (def_xbus_4byte_mode); # GroupID is 0x30 on RX0 when 4-byte mode since it isn't used -} -scom 0x800.0b(rx_id1_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - rx_bus_id , 0b000000, any; # BusID is 0x00 for all clock groups in all X buses - rx_group_id, 0b000001, (def_xbus_8byte_mode); # GroupID is 0x01 on RX1 when in 8-byte mode - rx_group_id, 0b000000, (def_xbus_4byte_mode); # GroupID is 0x00 on RX1 when in 4-byte mode -} -scom 0x800.0b(rx_id1_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - rx_bus_id , 0b000000, any; # BusID is 0x00 for all clock groups in all X buses - rx_group_id, 0b000010, (def_xbus_8byte_mode); # GroupID is 0x02 on RX2 when in 8-byte mode - rx_group_id, 0b000001, (def_xbus_4byte_mode); # GroupID is 0x01 on RX2 when in 4-byte mode -} -scom 0x800.0b(rx_id1_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - rx_bus_id , 0b000000, any; # BusID is 0x00 for all clock groups in all X buses - rx_group_id, 0b000011, (def_xbus_8byte_mode); # GroupID is 0x03 on RX2 when in 8-byte mode - rx_group_id, 0b000001, (def_xbus_4byte_mode); # GroupID is 0x01 on RX2 when in 4-byte mode -} - -scom 0x800.0b(tx_id1_pg)(tx_grp0)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - tx_bus_id , 0b000000, (def_xbus_8byte_mode); # BusID is 0x00 on TX0 when in 8-byte mode - tx_bus_id , 0b110000, (def_xbus_4byte_mode); # BusID is 0x30 on TX0 when in 4-byte mode since it isn't used and we don't want it decoding any GCR commands - tx_group_id, 0b100000, (def_xbus_8byte_mode); # GroupID is 0x20 on TX0 when in 8-byte mode - tx_group_id, 0b110001, (def_xbus_4byte_mode); # GroupID is 0x31 on TX0 when in 4-byte mode since it isn't used -} -scom 0x800.0b(tx_id1_pg)(tx_grp1)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - tx_bus_id , 0b000000, any; # BusID is 0x00 for all clock groups in all X buses - tx_group_id, 0b100001, (def_xbus_8byte_mode); # GroupID is 0x21 on TX1 when in 8-byte mode - tx_group_id, 0b100000, (def_xbus_4byte_mode); # GroupID is 0x20 on TX1 when in 4-byte mode -} -scom 0x800.0b(tx_id1_pg)(tx_grp2)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - tx_bus_id , 0b000000, any; # BusID is 0x00 for all clock groups in all X buses - tx_group_id, 0b100010, (def_xbus_8byte_mode); # GroupID is 0x22 on TX2 when in 8-byte mode - tx_group_id, 0b100001, (def_xbus_4byte_mode); # GroupID is 0x21 on TX2 when in 4-byte mode -} -scom 0x800.0b(tx_id1_pg)(tx_grp3)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - tx_bus_id , 0b000000, any; # BusID is 0x00 for all clock groups in all X buses - tx_group_id, 0b100011, (def_xbus_8byte_mode); # GroupID is 0x23 on TX3 when in 8-byte mode - tx_group_id, 0b100010, (def_xbus_4byte_mode); # GroupID is 0x22 on TX3 when in 4-byte mode -} - -#--******************************************************************************************** -#-- rx_last_group_id, tx_last_group_id -#--******************************************************************************************** -scom 0x800.0b(rx_id2_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - rx_last_group_id , 0b000011, (def_xbus_8byte_mode); #Last group ID is 0x03 on RX0 when in 8-byte mode - rx_last_group_id , 0b110000, (def_xbus_4byte_mode); #Last group ID is 0x30 on RX0 when in 4-byte mode since it isn't used -} -scom 0x800.0b(rx_id2_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - rx_last_group_id , 0b000011, (def_xbus_8byte_mode); #Last group ID is 0x03 on RX1 when in 8-byte mode - rx_last_group_id , 0b100000, (def_xbus_4byte_mode); #Last group ID is 0x20 on RX1 when in 4-byte mode -} -scom 0x800.0b(rx_id2_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - rx_last_group_id , 0b000011, (def_xbus_8byte_mode); #Last group ID is 0x03 on RX2 when in 8-byte mode - rx_last_group_id , 0b100000, (def_xbus_4byte_mode); #Last group ID is 0x20 on RX2 when in 4-byte mode -} -scom 0x800.0b(rx_id2_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - rx_last_group_id , 0b000011, (def_xbus_8byte_mode); #Last group ID is 0x03 on RX3 when in 8-byte mode - rx_last_group_id , 0b100000, (def_xbus_4byte_mode); #Last group ID is 0x20 on RX2 when in 4-byte mode -} -scom 0x800.0b(tx_id2_pg)(tx_grp0)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - tx_last_group_id , 0b100011, (def_xbus_8byte_mode); #Last group ID is 0x23 on TX0 when in 8-byte mode - tx_last_group_id , 0b110001, (def_xbus_4byte_mode); #Last group ID is 0x31 on TX0 when in 4-byte mode since it isn't used -} -scom 0x800.0b(tx_id2_pg)(tx_grp1)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - tx_last_group_id , 0b100011, (def_xbus_8byte_mode); #Last group ID is 0x23 on TX1 when in 8-byte mode - tx_last_group_id , 0b100010, (def_xbus_4byte_mode); #Last group ID is 0x22 on TX1 when in 4-byte mode -} -scom 0x800.0b(tx_id2_pg)(tx_grp2)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - tx_last_group_id , 0b100011, (def_xbus_8byte_mode); #Last group ID is 0x23 on TX2 when in 8-byte mode - tx_last_group_id , 0b100010, (def_xbus_4byte_mode); #Last group ID is 0x22 on TX2 when in 4-byte mode -} -scom 0x800.0b(tx_id2_pg)(tx_grp3)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - tx_last_group_id , 0b100011, (def_xbus_8byte_mode); #Last group ID is 0x23 on TX3 when in 8-byte mode - tx_last_group_id , 0b100010, (def_xbus_4byte_mode); #Last group ID is 0x22 on TX3 when in 4-byte mode -} - -#--********************************************************************************************* -#-- rx_start_lane_id, rx_end_lane_id -#--********************************************************************************************* -#RX = 80-bits (8byte mode), 46-bits (4byte mode) -scom 0x800.0b(rx_id3_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - rx_start_lane_id , 0b0000000, any; #Start lane ID starts with lane 0 on RX0 when in 8/4 byte mode - rx_end_lane_id, 0b0010011, (def_xbus_8byte_mode); #End lane ID ends with lane 19 on RX0 when in 8-byte mode - rx_end_lane_id, 0b0000000, (def_xbus_4byte_mode); #End lane ID ends with lane 0 on RX0 when in 4-byte mode -} -scom 0x800.0b(rx_id3_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - rx_start_lane_id , 0b0010100, (def_xbus_8byte_mode); #Start lane ID starts with lane 20 on RX1 when in 8-byte mode - rx_start_lane_id , 0b0000000, (def_xbus_4byte_mode); #Start lane ID starts with lane 0 on RX1 when in 4-byte mode - rx_end_lane_id, 0b0100111, (def_xbus_8byte_mode); #End lane ID ends with lane 39 on RX1 when in 8-byte mode - rx_end_lane_id, 0b0000101, (def_xbus_4byte_mode); #End lane ID ends with lane 5 on RX1 when in 4-byte mode -} -scom 0x800.0b(rx_id3_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - rx_start_lane_id , 0b0101000, (def_xbus_8byte_mode); #Start lane ID starts with lane 40 on RX2 when in 8-byte mode - rx_start_lane_id , 0b0000110, (def_xbus_4byte_mode); #Start lane ID starts with lane 6 on RX2 when in 4-byte mode - rx_end_lane_id, 0b0111011, (def_xbus_8byte_mode); #End lane ID ends with lane 59 on RX2 when in 8-byte mode - rx_end_lane_id, 0b0011001, (def_xbus_4byte_mode); #End lane ID ends with lane 25 on RX2 when in 4-byte mode -} -scom 0x800.0b(rx_id3_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - rx_start_lane_id , 0b0111100, (def_xbus_8byte_mode); #Start lane ID starts with lane 60 on RX3 when in 8-byte mode - rx_start_lane_id , 0b0011010, (def_xbus_4byte_mode); #Start lane ID starts with lane 26 on RX3 when in 4-byte mode - rx_end_lane_id, 0b1001111, (def_xbus_8byte_mode); #End lane ID ends with lane 79 on RX3 when in 8-byte mode - rx_end_lane_id, 0b0101101, (def_xbus_4byte_mode); #End lane ID ends with lane 45 on RX3 when in 4-byte mode -} -# TX = 80-bits (8byte mode), 46-bits (4byte mode) -scom 0x800.0b(tx_id3_pg)(tx_grp0)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - tx_start_lane_id , 0b0000000, any; #Start lane ID starts with lane 0 on TX0 when in 8/4-byte mode - tx_end_lane_id, 0b0010011, (def_xbus_8byte_mode); #End lane ID ends with lane 19 on TX0 when in 8-byte mode - tx_end_lane_id, 0b0000000, (def_xbus_4byte_mode); #End lane ID ends with lane 0 on TX0 when in 4-byte mode - } -scom 0x800.0b(tx_id3_pg)(tx_grp1)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - tx_start_lane_id , 0b0010100, (def_xbus_8byte_mode); #Start lane ID starts with lane 20 on TX1 when in 8-byte mode - tx_start_lane_id , 0b0000000, (def_xbus_4byte_mode); #Start lane ID starts with lane 0 on TX1 when in 4-byte mode - tx_end_lane_id, 0b0100111, (def_xbus_8byte_mode); #End lane ID ends with lane 39 on TX1 when in 8-byte mode - tx_end_lane_id, 0b0000101, (def_xbus_4byte_mode); #End lane ID ends with lane 5 on TX1 when in 4-byte mode -} -scom 0x800.0b(tx_id3_pg)(tx_grp2)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - tx_start_lane_id , 0b0101000, (def_xbus_8byte_mode); #Start lane ID starts with lane 40 on TX2 when in 8-byte mode - tx_start_lane_id , 0b0000110, (def_xbus_4byte_mode); #Start lane ID start with lane 6 on TX2 when in 4-byte mode - tx_end_lane_id, 0b0111011, (def_xbus_8byte_mode); #End lane ID ends with lane 59 on TX2 when in 8-byte mode - tx_end_lane_id, 0b0011001, (def_xbus_4byte_mode); #End lane ID ends with lane 25 on TX2 when in 4-byte mode -} -scom 0x800.0b(tx_id3_pg)(tx_grp3)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - tx_start_lane_id , 0b0111100, (def_xbus_8byte_mode); #Start lane ID starts with lane 60 on TX3 when in 8-byte mode - tx_start_lane_id , 0b0011010, (def_xbus_4byte_mode); #Start lane ID start with lane 26 on TX3 when in 4-byte mode - tx_end_lane_id, 0b1001111, (def_xbus_8byte_mode); #End lane ID ends with lane 79 on TX3 when in 8-byte mode - tx_end_lane_id, 0b0101101, (def_xbus_4byte_mode); #End lane ID ends with lane 45 on TX3 when in 4-byte mode -} -#--********************************************************************************************* -# rx_tx_bus_width ediei4 0 99 rx_tx_bus_info_pg 0 7 RWX n 0000000 -# rx_rx_bus_width ediei4 0 99 rx_tx_bus_info_pg 7 7 RWX n 0000000 -#--********************************************************************************************* -# -# TX = 80-bits (8byte mode), 46-bits (4byte mode) -scom 0x800.0b(rx_tx_bus_info_pg)(rx_grp_broadcast)(lane_na).0x(xbus0_gcr_addr){ - scom_data, expr; -# 0d80 0d80 - 0b1010000101000000, (def_xbus_8byte_mode); #Bus width is 80 bits for all clock groups in all X buses when in 8-byte mode -# 0d46 0d46 - 0b0101110001011100, (def_xbus_4byte_mode); #Bus width is 46 bits for all clock groups in all X buses when in 4-byte mode -#scom 0x800.0b(rx_tx_bus_info_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr){ -# bits, scom_data, expr; -# rx_tx_bus_width, 0b1010000, (def_xbus_8byte_mode); #Bus width is 80 bits for all clock groups in all X buses when in 8-byte mode -# rx_tx_bus_width, 0b0101110, (def_xbus_4byte_mode); #Bus width is 46 bits for all clock groups in all X buses when in 4-byte mode -# rx_rx_bus_width, 0b1010000, (def_xbus_8byte_mode); #Bus width is 80 bits for all clock groups in all X buses when in 8-byte mode -# rx_rx_bus_width, 0b0101110, (def_xbus_4byte_mode); #Bus width is 46 bits for all clock groups in all X buses when in 4-byte mode -} -#----------------------------------------------------------------------------------------------- -# ______ -# / ____/__ ____ ________ #### TODO: This needs to be set in the scaninit file and io_hard_reset factored into all reinit scenarios -# / /_ / _ \/ __ \/ ___/ _ \ -# / __/ / __/ / / / /__/ __/ -# /_/ \___/_/ /_/\___/\___/ banner2 -fslant -#---------------------------------------------------------------------------------------------- -#--********************************************************************************************* -# rx_fence ediei4 0 99 rx_fence_pg 0 1 RWX n 0 -#--********************************************************************************************* -scom 0x800.0b(rx_fence_pg)(rx_grp_broadcast)(lane_na).0x(xbus0_gcr_addr){ - scom_data; - 0x8000; -#scom 0x800.0b(rx_fence_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr){ -# bits , scom_data; -# rx_fence, 0b1; -} -#---------------------------------------------------------------------------------------------- -# __ ____ _ __ __ -# / / ____ _____ ___ / __ \(_)________ _/ /_ / /__ _____ -# / / / __ `/ __ \/ _ \ / / / / / ___/ __ `/ __ \/ / _ \/ ___/ -# / /___/ /_/ / / / / __/ / /_/ / (__ ) /_/ / /_/ / / __(__ ) -# /_____/\__,_/_/ /_/\___/ /_____/_/____/\__,_/_.___/_/\___/____/ banner2 -fslant -#---------------------------------------------------------------------------------------------- -#--********************************************************************************************* -# rx_lane_disabled_vec_0_15 ediei4 0 99 rx_lane_disabled_vec_0_15_pg 0 16 RWX n 0000000000000000 -#--********************************************************************************************* -# RX = 80-bits (8byte mode), 46-bits (4byte mode) -scom 0x800.0b(rx_lane_disabled_vec_0_15_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - rx_lane_disabled_vec_0_15, 0b0000000000000000, (def_xbus_8byte_mode); # RX0 on X bus has all lanes (0x0000) enabled (ie. disabled=0)when in 8-byte mode - rx_lane_disabled_vec_0_15, 0b1111111111111111, (def_xbus_4byte_mode); # RX0 on X bus has lane 0:15 (0xFFFF) diabled when in 4-byte mode -} -scom 0x800.0b(rx_lane_disabled_vec_0_15_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - rx_lane_disabled_vec_0_15, 0b0000000000000000, (def_xbus_8byte_mode); # RX1 on X bus has all laness (0x0000) enabled (ie. disabled=0)when in 8-byte mode - rx_lane_disabled_vec_0_15, 0b1111111111111100, (def_xbus_4byte_mode); # RX1 on X bus has lane 0:13(0xFFFC) diabled when in 4-byte mode -} -scom 0x800.0b(rx_lane_disabled_vec_0_15_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - rx_lane_disabled_vec_0_15, 0b0000000000000000, any; # RX2 on X bus has all lanes (0x0000)enabled (ie. disabled=0) in 8/4-byte mode -} -scom 0x800.0b(rx_lane_disabled_vec_0_15_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - rx_lane_disabled_vec_0_15, 0b0000000000000000, any; # RX3 on X bus has all lanes (0x0000) enabled (ie. disabled=0) in 8/4-byte mode -} -#--********************************************************************************************* -# rx_lane_disabled_vec_16_31 ediei4 0 99 rx_lane_disabled_vec_16_31_pg 0 16 RWX n 0000000000000000 -#--********************************************************************************************* -scom 0x800.0b(rx_lane_disabled_vec_16_31_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - rx_lane_disabled_vec_16_31, 0b0000111111111111, (def_xbus_8byte_mode); # RX0 on X bus has lane 16:19 (0X0FFF) enabled (ie. disabled=0) when in 8-byte mode - rx_lane_disabled_vec_16_31, 0b1111111111111111, (def_xbus_4byte_mode); # RX0 on X bus has all lane 16:31(0xFFFF) diabled when in 4-byte mode -} -scom 0x800.0b(rx_lane_disabled_vec_16_31_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - rx_lane_disabled_vec_16_31, 0b0000111111111111, any; # RX1 on X bus has lane 16:19 (0X0FFF) enabled (ie. disabled=0) in 8/4-byte mode -} -scom 0x800.0b(rx_lane_disabled_vec_16_31_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - rx_lane_disabled_vec_16_31, 0b0000111111111111, any; # RX2 on X bus has lane 16:19 (0X0FFF) enabled (ie. disabled=0)when in 8/4-byte mode -} -scom 0x800.0b(rx_lane_disabled_vec_16_31_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - rx_lane_disabled_vec_16_31, 0b0000111111111111, any; # RX3 on X bus has lane 16:19 (0X0FFF) enabled (ie. disabled=0)when in 8/4-byte mode -} - -#--********************************************************************************************* -# tx_lane_disabled_vec_0_15 ediei4 0 99 tx_lane_disabled_vec_0_15_pg 0 16 RWX n 0000000000000000 -#--********************************************************************************************* -# TX = 80-bits (8byte mode), 46-bits (4byte mode) -scom 0x800.0b(tx_lane_disabled_vec_0_15_pg)(tx_grp0)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - tx_lane_disabled_vec_0_15, 0b0000000000000000, (def_xbus_8byte_mode); # TX0 on X bus has all lanes (0x0000)enabled(ie. disabled=0) when in 8-byte mode - tx_lane_disabled_vec_0_15, 0b1111111111111111, (def_xbus_4byte_mode); # TX0 on X bus has all lane 0:15 (0xFFFF)diabled when in 4-byte mode -} -scom 0x800.0b(tx_lane_disabled_vec_0_15_pg)(tx_grp1)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - tx_lane_disabled_vec_0_15, 0b0000000000000000, (def_xbus_8byte_mode); # TX1 on X bus has all lanes (0x0000) enabled (ie. disabled=0)when in 8-byte mode - tx_lane_disabled_vec_0_15, 0b1111111111111100, (def_xbus_4byte_mode); # TX1 on X bus has lane 0:13(0xFFFC) diabled when in 4-byte mode -} -scom 0x800.0b(tx_lane_disabled_vec_0_15_pg)(tx_grp2)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - tx_lane_disabled_vec_0_15, 0b0000000000000000, any; # TX2 on X bus has all lanes (0x0000) enabled (ie. disabled=0) in 8/4-byte mode -} -scom 0x800.0b(tx_lane_disabled_vec_0_15_pg)(tx_grp3)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - tx_lane_disabled_vec_0_15, 0b0000000000000000, any; # TX3 on X bus has all lanes enabled (0x0000) (ie. disabled=0) in 8/4-byte mode -} -#--********************************************************************************************* -# tx_lane_disabled_vec_16_31 ediei4 0 99 tx_lane_disabled_vec_16_31_pg 0 16 RWX n 0000000000000000 -#--********************************************************************************************* -scom 0x800.0b(tx_lane_disabled_vec_16_31_pg)(tx_grp0)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - tx_lane_disabled_vec_16_31, 0b0000111111111111, (def_xbus_8byte_mode); # TX0 on X bus has lane 16:19 (0X0FFF) enabled when in 8-byte mode(ie. disabled=0) - tx_lane_disabled_vec_16_31, 0b1111111111111111, (def_xbus_4byte_mode); # TX0 on X bus has all lane 16:31(0xFFFF) diabled when in 4-byte mode -} -scom 0x800.0b(tx_lane_disabled_vec_16_31_pg)(tx_grp1)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - tx_lane_disabled_vec_16_31, 0b0000111111111111, any; # TX1 on X bus has lane 16:19 (0X0FFF) enabled when in 8/4-byte mode(ie. disabled=0) -} -scom 0x800.0b(tx_lane_disabled_vec_16_31_pg)(tx_grp2)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - tx_lane_disabled_vec_16_31, 0b0000111111111111, any; # TX2 on X bus has lane 16:19 (0X0FFF)enabled in 8/4-byte mode(ie. disabled=0) -} -scom 0x800.0b(tx_lane_disabled_vec_16_31_pg)(tx_grp3)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - tx_lane_disabled_vec_16_31, 0b0000111111111111, any; # TX3 on X bus has lane 16:19 (0X0FFF) enabled in 8/4-byte mode(ie. disabled=0) -} -#------------------------------------------------------------------------------------- -# __ ___ ____ __ __ -# / |/ /___ __ __ / __ )____ _____/ / / / ____ _____ ___ _____ -# / /|_/ / __ `/ |/_/ / __ / __ `/ __ / / / / __ `/ __ \/ _ \/ ___/ -# / / / / /_/ /> < / /_/ / /_/ / /_/ / / /___/ /_/ / / / / __(__ ) -# /_/ /_/\__,_/_/|_| /_____/\__,_/\__,_/ /_____/\__,_/_/ /_/\___/____/ banner2 -fslant -#------------------------------------------------------------------------------------- -#--********************************************************************************************* -# rx_wtr_cur_lane ediei4 0 99 rx_wiretest_laneinfo_pg 0 5 ROX n 00000 -# rx_wtr_max_bad_lanes ediei4 0 99 rx_wiretest_laneinfo_pg 5 5 RWX n 00000 -# rx_wtr_bad_lane_count ediei4 0 99 rx_wiretest_laneinfo_pg 11 5 ROX n 00000 -#--********************************************************************************************* -# Register has more than one possible non-zero field so can't use group broadcast write -# RX = 2 spares -#scom 0x800.0b(rx_wiretest_laneinfo_pg)(rx_grp_broadcast)(lane_na).0x(xbus0_gcr_addr){ -scom 0x800.0b(rx_wiretest_laneinfo_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data; - rx_wtr_max_bad_lanes, 0b00010; # Only 2 spare lanes on all clock groups of XBUS RX in both 8/4byte mode -} - - -#--********************************************************************************************* -# tx_max_bad_lanes ediei4 0 99 tx_mode_pg 0 5 RWX n 00000 -# tx_msbswap ediei4 0 99 tx_mode_pg 5 1 RWX n 0 -# tx_pdwn_lite_disable edi 0 99 tx_mode_pg 6 1 RWX n 0 -#--********************************************************************************************* -# Register has more than one possible non-zero field so can't use group broadcast write -# TX = 2 spares -#scom 0x800.0b(tx_mode_pg)(tx_grp_broadcast)(lane_na).0x(xbus0_gcr_addr){ -scom 0x800.0b(tx_mode_pg)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data; - tx_max_bad_lanes, 0b00010; # Each TX CG on X bus has 2 spare lanes in 8/4byte mode -} -#------------------------------------------------------------------------------------- -# ____ ____ _ ______ ____ _ -# / __ \__ ______ / __ \___ ____ ____ _(_)____ /_ __/___ _/ / /_ __(_)___ ____ _ -# / / / / / / / __ \ / /_/ / _ \/ __ \/ __ `/ / ___/ / / / __ `/ / / / / / / __ \/ __ `/ -# / /_/ / /_/ / / / / / _, _/ __/ /_/ / /_/ / / / / / / /_/ / / / /_/ / / / / / /_/ / -# /_____/\__, /_/ /_/ /_/ |_|\___/ .___/\__,_/_/_/ /_/ \__,_/_/_/\__, /_/_/ /_/\__, / -# /____/ /_/ /____/ /____/ banner2 -fslant -#------------------------------------------------------------------------------------- -#--********************************************************************************************* -# rx_dyn_rpr_bad_lane_max ediei4 0 99 rx_dyn_rpr_err_tallying1_pg 0 7 RWX n 0001111 -# rx_dyn_rpr_err_cntr1_duration ediei4 0 99 rx_dyn_rpr_err_tallying1_pg 7 4 RWX n 1010 -# rx_dyn_rpr_clr_err_cntr1 ediei4 0 99 rx_dyn_rpr_err_tallying1_pg 11 1 RWX n 0 -# rx_dyn_rpr_disable ediei4 0 99 rx_dyn_rpr_err_tallying1_pg 12 1 RWX n 0 -# rx_dyn_rpr_enc_bad_data_lane_width ediei4 0 99 rx_dyn_rpr_err_tallying1_pg 13 3 RWX n 111 -#--********************************************************************************************* -# Register has more than one possible non-zero field so can't use group broadcast write -#scom 0x800.0b(rx_dyn_rpr_err_tallying1_pg)(rx_grp_broadcast)(lane_na).0x(xbus0_gcr_addr){ -# scom_data; -# 0b0001111101000111; -scom 0x800.0b(rx_dyn_rpr_err_tallying1_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data; - rx_dyn_rpr_bad_lane_max, 0b0001111; # - rx_dyn_rpr_err_cntr1_duration, 0b1010; # tap 10 - rx_dyn_rpr_enc_bad_data_lane_width, 0b111; # -} -#--********************************************************************************************* -# rx_dyn_rpr_bad_bus_max ediei4 0 99 rx_dyn_rpr_err_tallying2_pg 0 7 RWX n 0011111 -# rx_dyn_rpr_err_cntr2_duration ediei4 0 99 rx_dyn_rpr_err_tallying2_pg 7 4 RWX n 0111 -# rx_dyn_rpr_clr_err_cntr2 ediei4 0 99 rx_dyn_rpr_err_tallying2_pg 11 1 RWX n 0 -#--********************************************************************************************* -scom 0x800.0b(rx_dyn_rpr_err_tallying2_pg)(rx_grp_broadcast)(lane_na).0x(xbus0_gcr_addr){ - scom_data; - 0b0011111011100000; -#scom 0x800.0b(rx_dyn_rpr_err_tallying2_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr){ -# bits, scom_data; -# rx_dyn_rpr_bad_bus_max, 0b0011111; # -# rx_dyn_rpr_err_cntr2_duration, 0b0111; # tap 7 -} -#------------------------------------------------------------------------------------- -# __ ___ __ __ ___ __ -# / |/ /___ ______/ /____ _____ / |/ /___ ____/ /__ -# / /|_/ / __ `/ ___/ __/ _ \/ ___/ / /|_/ / __ \/ __ / _ \ -# / / / / /_/ (__ ) /_/ __/ / / / / / /_/ / /_/ / __/ -# /_/ /_/\__,_/____/\__/\___/_/ /_/ /_/\____/\__,_/\___/ -#------------------------------------------------------------------------------------- -#--********************************************************************************************* -# rx_master_mode ediei4 0 99 rx_mode_pg 0 1 RWX n 0 -# rx_disable_fence_reset ediei4 0 99 rx_mode_pg 1 1 RWX n 0 -# rx_pdwn_lite_disable edi 0 99 rx_mode_pg 2 1 RWX n 0 -# rx_use_sls_as_spr edi 0 99 rx_mode_pg 3 1 RWX n 0 -#--********************************************************************************************* -# Register has more than one possible non-zero field so can't use group broadcast write -#scom 0x800.0b(rx_mode_pg)(rx_grp_broadcast)(lane_na).0x(xbus0_gcr_addr){ -# scom_data, expr; -# 0x8000, (def_is_master); -# 0x0000, (def_is_slave); -scom 0x800.0b(rx_mode_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - rx_master_mode, 0b1, (def_is_master); # Node/chip currently running has - rx_master_mode, 0b0, (def_is_slave); # -} -#------------------------------------------------------------------------------------- -# ____ ____ ____ _____ ______ _____ __ __ -# / __ \/ __ \/ __ ) ___/ /_ __/___ _____ / ___/___ / /__ _____/ /______ -# / /_/ / /_/ / __ \__ \ / / / __ `/ __ \ \__ \/ _ \/ / _ \/ ___/ __/ ___/ -# / ____/ _, _/ /_/ /__/ / / / / /_/ / /_/ / ___/ / __/ / __/ /__/ /_(__ ) -# /_/ /_/ |_/_____/____/ /_/ \__,_/ .___/ /____/\___/_/\___/\___/\__/____/ banner2 -fslant -# /_/ -#------------------------------------------------------------------------------------- -# PER-LANE (RX) -#------------------------------------------------------------------------------------- -#--********************************************************************************************* -# rx_prbs_tap_id ediei4 0 99 rx_prbs_mode_pl 0 3 RWX n 000 -#--********************************************************************************************* -# *_grp_broadcast uses clock group broadcast addresses 0b001111 (RX) and 0b101111 (TX) to cut down the number of scom operations needed during scominit -# 0x8000B0000401103F, 0x8000B0200401103F, 0x8000B0400401103F, 0x8000B0600401103F -scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_0).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_a; -#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_0).0x(xbus0_gcr_addr){ -# bits, scom_data; -# rx_prbs_tap_id, rx_prbs_tap_id_pattern_a; -} -# 0x8000B0010401103F, 0x8000B0210401103F, 0x8000B0410401103F, 0x8000B0610401103F -scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_1).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_b; -#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_1).0x(xbus0_gcr_addr){ -# bits, scom_data; -# rx_prbs_tap_id, rx_prbs_tap_id_pattern_b; -} -# 0x8000B0020401103F, 0x8000B0220401103F, 0x8000B0420401103F, 0x8000B0620401103F -scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_2).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_c; -#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_2).0x(xbus0_gcr_addr){ -# bits, scom_data; -# rx_prbs_tap_id, rx_prbs_tap_id_pattern_c; -} -# 0x8000B0030401103F, 0x8000B0230401103F, 0x8000B0430401103F, 0x8000B0630401103F -scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_3).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_d; -#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_3).0x(xbus0_gcr_addr){ -# bits, scom_data; -# rx_prbs_tap_id, rx_prbs_tap_id_pattern_d; -} -# 0x8000B0040401103F, 0x8000B0240401103F, 0x8000B0440401103F, 0x8000B0640401103F -scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_4).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_e; -#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_4).0x(xbus0_gcr_addr){ -# bits, scom_data; -# rx_prbs_tap_id, rx_prbs_tap_id_pattern_e; -} -# 0x8000B0050401103F, 0x8000B0250401103F, 0x8000B0450401103F, 0x8000B0650401103F -scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_5).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_f; -#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_5).0x(xbus0_gcr_addr){ -# bits, scom_data; -# rx_prbs_tap_id, rx_prbs_tap_id_pattern_f; -} -# 0x8000B0060401103F, 0x8000B0260401103F, 0x8000B0460401103F, 0x8000B0660401103F -scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_6).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_g; -#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_6).0x(xbus0_gcr_addr){ -# bits, scom_data; -# rx_prbs_tap_id, rx_prbs_tap_id_pattern_g; -} -# 0x8000B0070401103F, 0x8000B0270401103F, 0x8000B0470401103F, 0x8000B0670401103F -scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_7).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_h; -#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_7).0x(xbus0_gcr_addr){ -# bits, scom_data; -# rx_prbs_tap_id, rx_prbs_tap_id_pattern_h; -} -# 0x8000B0080401103F, 0x8000B0280401103F, 0x8000B0480401103F, 0x8000B0680401103F -scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_8).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_a; -#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_8).0x(xbus0_gcr_addr){ -# bits, scom_data; -# rx_prbs_tap_id, rx_prbs_tap_id_pattern_a; -} -# 0x8000B0090401103F, 0x8000B0290401103F, 0x8000B0490401103F, 0x8000B0690401103F -scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_9).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_b; -#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_9).0x(xbus0_gcr_addr){ -# bits, scom_data; -# rx_prbs_tap_id, rx_prbs_tap_id_pattern_b; -} -# 0x8000B00A0401103F, 0x8000B02A0401103F, 0x8000B04A0401103F, 0x8000B06A0401103F -scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_10).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_c; -#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_10).0x(xbus0_gcr_addr){ -# bits, scom_data; -# rx_prbs_tap_id, rx_prbs_tap_id_pattern_c; -} -# 0x8000B00B0401103F, 0x8000B02B0401103F, 0x8000B04B0401103F, 0x8000B06B0401103F -scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_11).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_d; -#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_11).0x(xbus0_gcr_addr){ -# bits, scom_data; -# rx_prbs_tap_id, rx_prbs_tap_id_pattern_d; -} -# 0x8000B00C0401103F, 0x8000B02C0401103F, 0x8000B04C0401103F, 0x8000B06C0401103F -scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_12).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_e; -#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_12).0x(xbus0_gcr_addr){ -# bits, scom_data; -# rx_prbs_tap_id, rx_prbs_tap_id_pattern_e; -} -# 0x8000B00D0401103F, 0x8000B02D0401103F, 0x8000B04D0401103F, 0x8000B06D0401103F -scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_13).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_f; -#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_13).0x(xbus0_gcr_addr){ -# bits, scom_data; -# rx_prbs_tap_id, rx_prbs_tap_id_pattern_f; -} -# 0x8000B00E0401103F, 0x8000B02E0401103F, 0x8000B04E0401103F, 0x8000B06E0401103F -scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_14).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_g; -#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_14).0x(xbus0_gcr_addr){ -# bits, scom_data; -# rx_prbs_tap_id, rx_prbs_tap_id_pattern_g; -} -# 0x8000B00F0401103F, 0x8000B02F0401103F, 0x8000B04F0401103F, 0x8000B06F0401103F -scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_15).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_h; -#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_15).0x(xbus0_gcr_addr){ -# bits, scom_data; -# rx_prbs_tap_id, rx_prbs_tap_id_pattern_h; -} -# 0x8000B0100401103F, 0x8000B0300401103F, 0x8000B0500401103F, 0x8000B0700401103F -scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_16).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_a; -#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_16).0x(xbus0_gcr_addr){ -# bits, scom_data; -# rx_prbs_tap_id, rx_prbs_tap_id_pattern_a; -} -# 0x8000B0110401103F, 0x8000B0310401103F, 0x8000B0510401103F, 0x8000B0710401103F -scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_17).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_b; -#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_17).0x(xbus0_gcr_addr){ -# bits, scom_data; -# rx_prbs_tap_id, rx_prbs_tap_id_pattern_b; -} -# 0x8000B0120401103F, 0x8000B0320401103F, 0x8000B0520401103F, 0x8000B0720401103F -scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_18).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_c; -#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_18).0x(xbus0_gcr_addr){ -# bits, scom_data; -# rx_prbs_tap_id, rx_prbs_tap_id_pattern_c; -} -# 0x8000B0130401103F, 0x8000B0330401103F, 0x8000B0530401103F, 0x8000B0730401103F -scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_19).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_d; -#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_19).0x(xbus0_gcr_addr){ -# bits, scom_data; -# rx_prbs_tap_id, rx_prbs_tap_id_pattern_d; -} -#------------------------------------------------------------------------------------- -# PER-LANE (TX) -#------------------------------------------------------------------------------------- -#--********************************************************************************************* -# tx_prbs_tap_id ediei4 0 99 tx_prbs_mode_pl 0 3 RWX n 000 -#--********************************************************************************************* -scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_0).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_a; -#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_0).0x(xbus0_gcr_addr){ -# bits, scom_data; -# tx_prbs_tap_id, tx_prbs_tap_id_pattern_a; -} -scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_1).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_b; -#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_1).0x(xbus0_gcr_addr){ -# bits, scom_data; -# tx_prbs_tap_id, tx_prbs_tap_id_pattern_b; -} -scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_2).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_c; -#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_2).0x(xbus0_gcr_addr){ -# bits, scom_data; -# tx_prbs_tap_id, tx_prbs_tap_id_pattern_c; -} -scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_3).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_d; -#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_3).0x(xbus0_gcr_addr){ -# bits, scom_data; -# tx_prbs_tap_id, tx_prbs_tap_id_pattern_d; -} -scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_4).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_e; -#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_4).0x(xbus0_gcr_addr){ -# bits, scom_data; -# tx_prbs_tap_id, tx_prbs_tap_id_pattern_e; -} -scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_5).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_f; -#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_5).0x(xbus0_gcr_addr){ -# bits, scom_data; -# tx_prbs_tap_id, tx_prbs_tap_id_pattern_f; -} -scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_6).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_g; -#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_6).0x(xbus0_gcr_addr){ -# bits, scom_data; -# tx_prbs_tap_id, tx_prbs_tap_id_pattern_g; -} -scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_7).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_h; -#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_7).0x(xbus0_gcr_addr){ -# bits, scom_data; -# tx_prbs_tap_id, tx_prbs_tap_id_pattern_h; -} -scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_8).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_a; -#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_8).0x(xbus0_gcr_addr){ -# bits, scom_data; -# tx_prbs_tap_id, tx_prbs_tap_id_pattern_a; -} -scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_9).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_b; -#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_9).0x(xbus0_gcr_addr){ -# bits, scom_data; -# tx_prbs_tap_id, tx_prbs_tap_id_pattern_b; -} -scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_10).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_c; -#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_10).0x(xbus0_gcr_addr){ -# bits, scom_data; -# tx_prbs_tap_id, tx_prbs_tap_id_pattern_c; -} -scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_11).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_d; -#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_11).0x(xbus0_gcr_addr){ -# bits, scom_data; -# tx_prbs_tap_id, tx_prbs_tap_id_pattern_d; -} -scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_12).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_e; -#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_12).0x(xbus0_gcr_addr){ -# bits, scom_data; -# tx_prbs_tap_id, tx_prbs_tap_id_pattern_e; -} -scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_13).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_f; -#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_13).0x(xbus0_gcr_addr){ -# bits, scom_data; -# tx_prbs_tap_id, tx_prbs_tap_id_pattern_f; -} -scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_14).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_g; -#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_14).0x(xbus0_gcr_addr){ -# bits, scom_data; -# tx_prbs_tap_id, tx_prbs_tap_id_pattern_g; -} -scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_15).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_h; -#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_15).0x(xbus0_gcr_addr){ -# bits, scom_data; -# tx_prbs_tap_id, tx_prbs_tap_id_pattern_h; -} -scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_16).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_a; -#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_16).0x(xbus0_gcr_addr){ -# bits, scom_data; -# tx_prbs_tap_id, tx_prbs_tap_id_pattern_a; -} -scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_17).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_b; -#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_17).0x(xbus0_gcr_addr){ -# bits, scom_data; -# tx_prbs_tap_id, tx_prbs_tap_id_pattern_b; -} -scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_18).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_c; -#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_18).0x(xbus0_gcr_addr){ -# bits, scom_data; -# tx_prbs_tap_id, tx_prbs_tap_id_pattern_c; -} -scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_19).0x(xbus0_gcr_addr){ - scom_data; - rx_prbs_tap_id_pattern_d; -#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_19).0x(xbus0_gcr_addr){ -# bits, scom_data; -# tx_prbs_tap_id, tx_prbs_tap_id_pattern_d; - -} -#------------------------------------------------------------------------------------- -# ____ __ __ -# / __ \/ / / / -# / /_/ / / / / -# / ____/ /___/ /___ -# /_/ /_____/_____/ banner2 -fslant -#------------------------------------------------------------------------------------- -#--********************************************************************************************* -# rx_wt_cu_pll_pgood ediei4 0 99 rx_wiretest_pll_cntl_pg 0 1 RWX n 0 -# rx_wt_cu_pll_reset ediei4 0 99 rx_wiretest_pll_cntl_pg 1 1 RWX n 1 -# rx_wt_cu_pll_pgooddly ediei4 0 99 rx_wiretest_pll_cntl_pg 2 3 RWX n 000 -# rx_wt_cu_pll_lock ediei4 0 99 rx_wiretest_pll_cntl_pg 5 1 ROX n 0 -# rx_wt_pll_refclksel ediei4 0 99 rx_wiretest_pll_cntl_pg 6 1 RWX n 0 -# rx_pll_refclksel_scom_en edi 0 99 rx_wiretest_pll_cntl_pg 7 1 RWX n 0 -#--********************************************************************************************* -# TODO: Double check if this is needed here or not -# Register has more than one possible non-zero field so can't use group broadcast write -scom 0x800.0b(rx_wiretest_pll_cntl_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data; - rx_wt_cu_pll_reset, 0b0; # Put PLL in disabled state until Wiretest is started. - rx_wt_cu_pll_pgooddly, 0b000; # 16UI delay -} -#------------------------------------------------------------------------------------- -# ____ _ __________ ____ __ __ -# / __ \_____(_) _____ / ____/ / /__ / __ \____ _/ /_/ /____ _________ -# / / / / ___/ / | / / _ \ / / / / //_/ / /_/ / __ `/ __/ __/ _ \/ ___/ __ \ -# / /_/ / / / /| |/ / __/ / /___/ / ,< / ____/ /_/ / /_/ /_/ __/ / / / / / -# /_____/_/ /_/ |___/\___/ \____/_/_/|_| /_/ \__,_/\__/\__/\___/_/ /_/ /_/ -#------------------------------------------------------------------------------------- -#--********************************************************************************************* -# tx_drv_clk_pattern_gcrmsg ediei4 0 99 tx_clk_cntl_gcrmsg_pg 0 2 RWX n 10 -#--********************************************************************************************* -scom 0x800.0b(tx_clk_cntl_gcrmsg_pg)(tx_grp_broadcast)(lane_na).0x(xbus0_gcr_addr){ - scom_data; - 0x0000; -#scom 0x800.0b(tx_clk_cntl_gcrmsg_pg)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_na).0x(xbus0_gcr_addr){ -# bits, scom_data; -# tx_drv_clk_pattern_gcrmsg, 0b00; # Drive 0's to start out -} - -#--********************************************************************************************* -# rx_block_lock_lane ediei4 0 99 rx_cntl_pl 0 1 RWX n 0 -# rx_check_skew_lane ediei4 0 99 rx_cntl_pl 1 1 RWX n 0 -# rx_pdwn_lite edi 0 99 rx_cntl_pl 2 1 RWX n 0 -# rx_offcal_mode ediei4 0 99 rx_cntl_pl 3 1 RWX n 0 -#--********************************************************************************************* -# Register has more than one possible non-zero field so can't use group broadcast write -#scom 0x800.0b(rx_ei4_cal_cntl_pp)(rx_grp_broadcast)(lane_na).0x(xbus0_gcr_addr){ -# scom_data; -# 0x8000; -scom 0x800.0b(rx_ei4_cal_cntl_pp)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data; - rx_block_lock_lane, 0b1; -} - -#------------------------------------------------------------------------------------- -# ____ _ __ _______ _____ __ -# / __ \ |/ / /_ __(_)___ ___ ___ _____ / ___/___ / / -# / /_/ / / / / / / __ `__ \/ _ \/ ___/ \__ \/ _ \/ / -# / _, _/ | / / / / / / / / / __/ / ___/ / __/ / -#/_/ |_/_/|_| /_/ /_/_/ /_/ /_/\___/_/ /____/\___/_/ -#------------------------------------------------------------------------------------- -#--********************************************************************************************* -#-- rx_timeout_sel_pg: rx_sls_timeout_sel -#--********************************************************************************************* -scom 0x800.0b(rx_timeout_sel_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data; - rx_sls_timeout_sel, 0b001; # Set this entry to 0b001 per defect HW220752 -} -#------------------------------------------------------------------------------------- -# ____ _ __ _____ __ _____ ______ __ __ _____ __ -# / __ \ |/ / / ___// / / ___/ / ____/ __/ /____ ____ ____/ / / ___/___ / / -# / /_/ / / \__ \/ / \__ \ / __/ | |/_/ __/ _ \/ __ \/ __ / \__ \/ _ \/ / -# / _, _/ | ___/ / /______/ / / /____> </ /_/ __/ / / / /_/ / ___/ / __/ / -#/_/ |_/_/|_| /____/_____/____/ /_____/_/|_|\__/\___/_/ /_/\__,_/ /____/\___/_/ -#------------------------------------------------------------------------------------- -#--********************************************************************************************* -#-- rx_spare_mode_pg: rx_sls_extend_sel -#--********************************************************************************************* -scom 0x800.0b(rx_spare_mode_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr){ - bits, scom_data, expr; - rx_sls_extend_sel, 0b100, (def_is_slave); #Set this entry to 0b100 per defect HW220806 -} - -############################################################################################ -# END OF FILE -############################################################################################ +define def_is_master = (TGT1.ATTR_FABRIC_CHIP_ID < TGT3.ATTR_FABRIC_CHIP_ID); +define def_is_slave = (TGT1.ATTR_FABRIC_CHIP_ID > TGT3.ATTR_FABRIC_CHIP_ID); + +define xbus_base_addr = xbus0_gcr_addr; + + +#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG +scom 0x8009D800(xbus_base_addr) { + bits, scom_data, expr; + rx_dyn_rpr_bad_lane_max, 0b0001111, any; + rx_dyn_rpr_enc_bad_data_lane_width, 0b111, any; + rx_dyn_rpr_err_cntr1_duration, 0b1010, any; +} + +#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG +scom 0x800AE000(xbus_base_addr) { + bits, scom_data, expr; + rx_dyn_rpr_bad_bus_max, 0b0011111, any; + rx_dyn_rpr_err_cntr2_duration, 0b0111, any; +} + +#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_CNTL_PP +scom 0x800B1800(xbus_base_addr) { + bits, scom_data, expr; + rx_ddc_use_cyc_block_lock, 0b0 , HW_EXPRESS; + rx_ddc_use_cyc_block_lock, 0b1 , VBU_EXPRESS; +} + +#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_A_D_PP +scom 0x800B3000(xbus_base_addr) { + bits, scom_data, expr; + rx_cal_dec_val_a, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_a, 0b1000 , VBU_EXPRESS; + rx_cal_dec_val_b, 0b0001 , HW_EXPRESS; + rx_cal_dec_val_b, 0b0000 , VBU_EXPRESS; + rx_cal_dec_val_c, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_c, 0b0000 , VBU_EXPRESS; + rx_cal_dec_val_d, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_d, 0b1110 , VBU_EXPRESS; +} + +#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_E_H_PP +scom 0x800B3800(xbus_base_addr) { + bits, scom_data, expr; + rx_cal_dec_val_e, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_e, 0b1110 , VBU_EXPRESS; + rx_cal_dec_val_f, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_f, 0b0000 , VBU_EXPRESS; + rx_cal_dec_val_g, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_g, 0b0000 , VBU_EXPRESS; + rx_cal_dec_val_h, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_h, 0b0000 , VBU_EXPRESS; +} + +#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_A_D_PP +scom 0x800B2000(xbus_base_addr) { + bits, scom_data, expr; + rx_cal_inc_val_a, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_a, 0b1000 , VBU_EXPRESS; + rx_cal_inc_val_b, 0b0001 , HW_EXPRESS; + rx_cal_inc_val_b, 0b0000 , VBU_EXPRESS; + rx_cal_inc_val_c, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_c, 0b0000 , VBU_EXPRESS; + rx_cal_inc_val_d, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_d, 0b1110 , VBU_EXPRESS; +} + +#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_E_H_PP +scom 0x800B2800(xbus_base_addr) { + bits, scom_data, expr; + rx_cal_inc_val_e, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_e, 0b1110 , VBU_EXPRESS; + rx_cal_inc_val_f, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_f, 0b0000 , VBU_EXPRESS; + rx_cal_inc_val_g, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_g, 0b0000 , VBU_EXPRESS; + rx_cal_inc_val_h, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_h, 0b0000 , VBU_EXPRESS; +} + +#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG +scom 0x800A3800(xbus_base_addr) { + bits, scom_data, expr; + rx_eo_enable_ber_test, 0b1 , HW_EXPRESS; + rx_eo_enable_ber_test, 0b0 , VBU_EXPRESS; + rx_eo_enable_ctle_cal, 0b1 , HW_EXPRESS; + rx_eo_enable_ctle_cal, 0b0 , VBU_EXPRESS; + rx_eo_enable_dcd_cal, 0b1 , HW_EXPRESS; + rx_eo_enable_dcd_cal, 0b0 , VBU_EXPRESS; + rx_eo_enable_final_l2u_adj, 0b1, any; + rx_eo_enable_latch_offset_cal, 0b1 , HW_EXPRESS; + rx_eo_enable_latch_offset_cal, 0b0 , VBU_EXPRESS; + rx_eo_enable_measure_eye_width, 0b1 , HW_EXPRESS; + rx_eo_enable_measure_eye_width, 0b0 , VBU_EXPRESS; + rx_eo_enable_result_check, 0b1 , HW_EXPRESS; + rx_eo_enable_result_check, 0b0 , VBU_EXPRESS; + rx_eo_enable_vref_cal, 0b1 , HW_EXPRESS; + rx_eo_enable_vref_cal, 0b0 , VBU_EXPRESS; +} + +#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_FENCE_PG +scom 0x8009A800(xbus_base_addr) { + bits, scom_data, expr; + rx_fence, 0b1, any; +} + +#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_ID1_PG +scom 0x80085000(xbus_base_addr) { + bits, scom_data, expr; + rx_bus_id, 0b000000, any; + rx_group_id, 0b000000, any; +} + +#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_ID2_PG +scom 0x80085800(xbus_base_addr) { + bits, scom_data, expr; + rx_last_group_id, 0b000011, any; +} + +#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_ID3_PG +scom 0x80086000(xbus_base_addr) { + bits, scom_data, expr; + rx_end_lane_id, 0b0010011, any; + rx_start_lane_id, 0b0000000, any; +} + +#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG +scom 0x80092800(xbus_base_addr) { + bits, scom_data, expr; + rx_lane_disabled_vec_0_15, 0b0000000000000000, any; +} + +#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG +scom 0x80093000(xbus_base_addr) { + bits, scom_data, expr; + rx_lane_disabled_vec_16_31, 0b0000111111111111, any; +} + +#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_MODE_PG +scom 0x80081800(xbus_base_addr) { + bits, scom_data, expr; + rx_master_mode, 0b1, def_is_master; +} + +#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG +scom 0x800AB800(xbus_base_addr) { + bits, scom_data, expr; + rx_rc_enable_dll_update, 0b1 , HW_EXPRESS; + rx_rc_enable_dll_update, 0b0 , VBU_EXPRESS; + rx_rc_enable_edge_track, 0b1 , HW_EXPRESS; + rx_rc_enable_edge_track, 0b0 , VBU_EXPRESS; + rx_rc_enable_measure_eye_width, 0b1 , HW_EXPRESS; + rx_rc_enable_measure_eye_width, 0b0 , VBU_EXPRESS; + rx_rc_enable_result_check, 0b1 , HW_EXPRESS; + rx_rc_enable_result_check, 0b0 , VBU_EXPRESS; +} + +#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP +scom 0x800B6000(xbus_base_addr) { + bits, scom_data, expr; + rx_servo_timeout_sel_a, 0b0101 , HW_EXPRESS; + rx_servo_timeout_sel_a, 0b1000 , VBU_EXPRESS; + rx_servo_timeout_sel_b, 0b1010 , HW_EXPRESS; + rx_servo_timeout_sel_b, 0b1000 , VBU_EXPRESS; + rx_servo_timeout_sel_c, 0b0101 , HW_EXPRESS; + rx_servo_timeout_sel_c, 0b1000 , VBU_EXPRESS; +} + +#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP +scom 0x800B6800(xbus_base_addr) { + bits, scom_data, expr; + rx_servo_timeout_sel_f, 0b1000 , HW_EXPRESS; + rx_servo_timeout_sel_f, 0b0110 , VBU_EXPRESS; + rx_servo_timeout_sel_h, 0b0110 , HW_EXPRESS; + rx_servo_timeout_sel_h, 0b1000 , VBU_EXPRESS; +} + +#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_SPARE_MODE_PG +scom 0x80080800(xbus_base_addr) { + bits, scom_data, expr; + rx_sls_extend_sel, 0b101, def_is_slave; +} + +#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG +scom 0x80089800(xbus_base_addr) { + bits, scom_data, expr; + rx_sls_timeout_sel, 0b001, any; +} + +#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG +scom 0x80099800(xbus_base_addr) { + bits, scom_data, expr; + rx_rx_bus_width, 0b1010000, any; + rx_tx_bus_width, 0b1010000, any; +} + +#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG +scom 0x80095800(xbus_base_addr) { + bits, scom_data, expr; + rx_wtr_max_bad_lanes, 0b00010, any; +} + +#RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B000(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b000, any; +} + +#RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B001(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b001, any; +} + +#RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B002(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b010, any; +} + +#RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B003(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b011, any; +} + +#RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B004(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b100, any; +} + +#RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B005(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b101, any; +} + +#RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B006(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b110, any; +} + +#RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B007(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b111, any; +} + +#RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B008(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b000, any; +} + +#RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B009(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b001, any; +} + +#RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B00A(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b001, any; +} + +#RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B00B(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b000, any; +} + +#RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B00C(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b111, any; +} + +#RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B00D(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b110, any; +} + +#RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B00E(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b101, any; +} + +#RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B00F(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b100, any; +} + +#RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B010(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b011, any; +} + +#RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B011(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b010, any; +} + +#RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B012(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b001, any; +} + +#RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B013(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b000, any; +} + +#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG +scom 0x8009D820(xbus_base_addr) { + bits, scom_data, expr; + rx_dyn_rpr_bad_lane_max, 0b0001111, any; + rx_dyn_rpr_enc_bad_data_lane_width, 0b111, any; + rx_dyn_rpr_err_cntr1_duration, 0b1010, any; +} + +#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG +scom 0x800AE020(xbus_base_addr) { + bits, scom_data, expr; + rx_dyn_rpr_bad_bus_max, 0b0011111, any; + rx_dyn_rpr_err_cntr2_duration, 0b0111, any; +} + +#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_CNTL_PP +scom 0x800B1820(xbus_base_addr) { + bits, scom_data, expr; + rx_ddc_use_cyc_block_lock, 0b0 , HW_EXPRESS; + rx_ddc_use_cyc_block_lock, 0b1 , VBU_EXPRESS; +} + +#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_A_D_PP +scom 0x800B3020(xbus_base_addr) { + bits, scom_data, expr; + rx_cal_dec_val_a, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_a, 0b1000 , VBU_EXPRESS; + rx_cal_dec_val_b, 0b0001 , HW_EXPRESS; + rx_cal_dec_val_b, 0b0000 , VBU_EXPRESS; + rx_cal_dec_val_c, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_c, 0b0000 , VBU_EXPRESS; + rx_cal_dec_val_d, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_d, 0b1110 , VBU_EXPRESS; +} + +#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_E_H_PP +scom 0x800B3820(xbus_base_addr) { + bits, scom_data, expr; + rx_cal_dec_val_e, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_e, 0b1110 , VBU_EXPRESS; + rx_cal_dec_val_f, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_f, 0b0000 , VBU_EXPRESS; + rx_cal_dec_val_g, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_g, 0b0000 , VBU_EXPRESS; + rx_cal_dec_val_h, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_h, 0b0000 , VBU_EXPRESS; +} + +#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_A_D_PP +scom 0x800B2020(xbus_base_addr) { + bits, scom_data, expr; + rx_cal_inc_val_a, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_a, 0b1000 , VBU_EXPRESS; + rx_cal_inc_val_b, 0b0001 , HW_EXPRESS; + rx_cal_inc_val_b, 0b0000 , VBU_EXPRESS; + rx_cal_inc_val_c, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_c, 0b0000 , VBU_EXPRESS; + rx_cal_inc_val_d, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_d, 0b1110 , VBU_EXPRESS; +} + +#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_E_H_PP +scom 0x800B2820(xbus_base_addr) { + bits, scom_data, expr; + rx_cal_inc_val_e, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_e, 0b1110 , VBU_EXPRESS; + rx_cal_inc_val_f, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_f, 0b0000 , VBU_EXPRESS; + rx_cal_inc_val_g, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_g, 0b0000 , VBU_EXPRESS; + rx_cal_inc_val_h, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_h, 0b0000 , VBU_EXPRESS; +} + +#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG +scom 0x800A3820(xbus_base_addr) { + bits, scom_data, expr; + rx_eo_enable_ber_test, 0b1 , HW_EXPRESS; + rx_eo_enable_ber_test, 0b0 , VBU_EXPRESS; + rx_eo_enable_ctle_cal, 0b1 , HW_EXPRESS; + rx_eo_enable_ctle_cal, 0b0 , VBU_EXPRESS; + rx_eo_enable_dcd_cal, 0b1 , HW_EXPRESS; + rx_eo_enable_dcd_cal, 0b0 , VBU_EXPRESS; + rx_eo_enable_final_l2u_adj, 0b1, any; + rx_eo_enable_latch_offset_cal, 0b1 , HW_EXPRESS; + rx_eo_enable_latch_offset_cal, 0b0 , VBU_EXPRESS; + rx_eo_enable_measure_eye_width, 0b1 , HW_EXPRESS; + rx_eo_enable_measure_eye_width, 0b0 , VBU_EXPRESS; + rx_eo_enable_result_check, 0b1 , HW_EXPRESS; + rx_eo_enable_result_check, 0b0 , VBU_EXPRESS; + rx_eo_enable_vref_cal, 0b1 , HW_EXPRESS; + rx_eo_enable_vref_cal, 0b0 , VBU_EXPRESS; +} + +#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_FENCE_PG +scom 0x8009A820(xbus_base_addr) { + bits, scom_data, expr; + rx_fence, 0b1, any; +} + +#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_ID1_PG +scom 0x80085020(xbus_base_addr) { + bits, scom_data, expr; + rx_bus_id, 0b000000, any; + rx_group_id, 0b000001, any; +} + +#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_ID2_PG +scom 0x80085820(xbus_base_addr) { + bits, scom_data, expr; + rx_last_group_id, 0b000011, any; +} + +#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_ID3_PG +scom 0x80086020(xbus_base_addr) { + bits, scom_data, expr; + rx_end_lane_id, 0b0100111, any; + rx_start_lane_id, 0b0010100, any; +} + +#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG +scom 0x80092820(xbus_base_addr) { + bits, scom_data, expr; + rx_lane_disabled_vec_0_15, 0b0000000000000000, any; +} + +#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG +scom 0x80093020(xbus_base_addr) { + bits, scom_data, expr; + rx_lane_disabled_vec_16_31, 0b0000111111111111, any; +} + +#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_MODE_PG +scom 0x80081820(xbus_base_addr) { + bits, scom_data, expr; + rx_master_mode, 0b1, def_is_master; +} + +#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG +scom 0x800AB820(xbus_base_addr) { + bits, scom_data, expr; + rx_rc_enable_dll_update, 0b1 , HW_EXPRESS; + rx_rc_enable_dll_update, 0b0 , VBU_EXPRESS; + rx_rc_enable_edge_track, 0b1 , HW_EXPRESS; + rx_rc_enable_edge_track, 0b0 , VBU_EXPRESS; + rx_rc_enable_measure_eye_width, 0b1 , HW_EXPRESS; + rx_rc_enable_measure_eye_width, 0b0 , VBU_EXPRESS; + rx_rc_enable_result_check, 0b1 , HW_EXPRESS; + rx_rc_enable_result_check, 0b0 , VBU_EXPRESS; +} + +#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP +scom 0x800B6020(xbus_base_addr) { + bits, scom_data, expr; + rx_servo_timeout_sel_a, 0b0101 , HW_EXPRESS; + rx_servo_timeout_sel_a, 0b1000 , VBU_EXPRESS; + rx_servo_timeout_sel_b, 0b1010 , HW_EXPRESS; + rx_servo_timeout_sel_b, 0b1000 , VBU_EXPRESS; + rx_servo_timeout_sel_c, 0b0101 , HW_EXPRESS; + rx_servo_timeout_sel_c, 0b1000 , VBU_EXPRESS; +} + +#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP +scom 0x800B6820(xbus_base_addr) { + bits, scom_data, expr; + rx_servo_timeout_sel_f, 0b1000 , HW_EXPRESS; + rx_servo_timeout_sel_f, 0b0110 , VBU_EXPRESS; + rx_servo_timeout_sel_h, 0b0110 , HW_EXPRESS; + rx_servo_timeout_sel_h, 0b1000 , VBU_EXPRESS; +} + +#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_SPARE_MODE_PG +scom 0x80080820(xbus_base_addr) { + bits, scom_data, expr; + rx_sls_extend_sel, 0b101, def_is_slave; +} + +#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG +scom 0x80089820(xbus_base_addr) { + bits, scom_data, expr; + rx_sls_timeout_sel, 0b001, any; +} + +#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG +scom 0x80099820(xbus_base_addr) { + bits, scom_data, expr; + rx_rx_bus_width, 0b1010000, any; + rx_tx_bus_width, 0b1010000, any; +} + +#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG +scom 0x80095820(xbus_base_addr) { + bits, scom_data, expr; + rx_wtr_max_bad_lanes, 0b00010, any; +} + +#RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B020(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b000, any; +} + +#RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B021(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b001, any; +} + +#RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B022(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b010, any; +} + +#RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B023(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b011, any; +} + +#RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B024(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b100, any; +} + +#RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B025(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b101, any; +} + +#RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B026(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b110, any; +} + +#RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B027(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b111, any; +} + +#RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B028(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b000, any; +} + +#RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B029(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b001, any; +} + +#RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B02A(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b001, any; +} + +#RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B02B(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b000, any; +} + +#RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B02C(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b111, any; +} + +#RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B02D(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b110, any; +} + +#RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B02E(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b101, any; +} + +#RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B02F(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b100, any; +} + +#RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B030(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b011, any; +} + +#RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B031(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b010, any; +} + +#RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B032(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b001, any; +} + +#RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B033(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b000, any; +} + +#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG +scom 0x8009D840(xbus_base_addr) { + bits, scom_data, expr; + rx_dyn_rpr_bad_lane_max, 0b0001111, any; + rx_dyn_rpr_enc_bad_data_lane_width, 0b111, any; + rx_dyn_rpr_err_cntr1_duration, 0b1010, any; +} + +#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG +scom 0x800AE040(xbus_base_addr) { + bits, scom_data, expr; + rx_dyn_rpr_bad_bus_max, 0b0011111, any; + rx_dyn_rpr_err_cntr2_duration, 0b0111, any; +} + +#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_CNTL_PP +scom 0x800B1840(xbus_base_addr) { + bits, scom_data, expr; + rx_ddc_use_cyc_block_lock, 0b0 , HW_EXPRESS; + rx_ddc_use_cyc_block_lock, 0b1 , VBU_EXPRESS; +} + +#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_A_D_PP +scom 0x800B3040(xbus_base_addr) { + bits, scom_data, expr; + rx_cal_dec_val_a, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_a, 0b1000 , VBU_EXPRESS; + rx_cal_dec_val_b, 0b0001 , HW_EXPRESS; + rx_cal_dec_val_b, 0b0000 , VBU_EXPRESS; + rx_cal_dec_val_c, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_c, 0b0000 , VBU_EXPRESS; + rx_cal_dec_val_d, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_d, 0b1110 , VBU_EXPRESS; +} + +#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_E_H_PP +scom 0x800B3840(xbus_base_addr) { + bits, scom_data, expr; + rx_cal_dec_val_e, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_e, 0b1110 , VBU_EXPRESS; + rx_cal_dec_val_f, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_f, 0b0000 , VBU_EXPRESS; + rx_cal_dec_val_g, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_g, 0b0000 , VBU_EXPRESS; + rx_cal_dec_val_h, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_h, 0b0000 , VBU_EXPRESS; +} + +#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_A_D_PP +scom 0x800B2040(xbus_base_addr) { + bits, scom_data, expr; + rx_cal_inc_val_a, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_a, 0b1000 , VBU_EXPRESS; + rx_cal_inc_val_b, 0b0001 , HW_EXPRESS; + rx_cal_inc_val_b, 0b0000 , VBU_EXPRESS; + rx_cal_inc_val_c, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_c, 0b0000 , VBU_EXPRESS; + rx_cal_inc_val_d, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_d, 0b1110 , VBU_EXPRESS; +} + +#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_E_H_PP +scom 0x800B2840(xbus_base_addr) { + bits, scom_data, expr; + rx_cal_inc_val_e, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_e, 0b1110 , VBU_EXPRESS; + rx_cal_inc_val_f, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_f, 0b0000 , VBU_EXPRESS; + rx_cal_inc_val_g, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_g, 0b0000 , VBU_EXPRESS; + rx_cal_inc_val_h, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_h, 0b0000 , VBU_EXPRESS; +} + +#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG +scom 0x800A3840(xbus_base_addr) { + bits, scom_data, expr; + rx_eo_enable_ber_test, 0b1 , HW_EXPRESS; + rx_eo_enable_ber_test, 0b0 , VBU_EXPRESS; + rx_eo_enable_ctle_cal, 0b1 , HW_EXPRESS; + rx_eo_enable_ctle_cal, 0b0 , VBU_EXPRESS; + rx_eo_enable_dcd_cal, 0b1 , HW_EXPRESS; + rx_eo_enable_dcd_cal, 0b0 , VBU_EXPRESS; + rx_eo_enable_final_l2u_adj, 0b1, any; + rx_eo_enable_latch_offset_cal, 0b1 , HW_EXPRESS; + rx_eo_enable_latch_offset_cal, 0b0 , VBU_EXPRESS; + rx_eo_enable_measure_eye_width, 0b1 , HW_EXPRESS; + rx_eo_enable_measure_eye_width, 0b0 , VBU_EXPRESS; + rx_eo_enable_result_check, 0b1 , HW_EXPRESS; + rx_eo_enable_result_check, 0b0 , VBU_EXPRESS; + rx_eo_enable_vref_cal, 0b1 , HW_EXPRESS; + rx_eo_enable_vref_cal, 0b0 , VBU_EXPRESS; +} + +#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_FENCE_PG +scom 0x8009A840(xbus_base_addr) { + bits, scom_data, expr; + rx_fence, 0b1, any; +} + +#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_ID1_PG +scom 0x80085040(xbus_base_addr) { + bits, scom_data, expr; + rx_bus_id, 0b000000, any; + rx_group_id, 0b000010, any; +} + +#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_ID2_PG +scom 0x80085840(xbus_base_addr) { + bits, scom_data, expr; + rx_last_group_id, 0b000011, any; +} + +#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_ID3_PG +scom 0x80086040(xbus_base_addr) { + bits, scom_data, expr; + rx_end_lane_id, 0b0111011, any; + rx_start_lane_id, 0b0101000, any; +} + +#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG +scom 0x80092840(xbus_base_addr) { + bits, scom_data, expr; + rx_lane_disabled_vec_0_15, 0b0000000000000000, any; +} + +#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG +scom 0x80093040(xbus_base_addr) { + bits, scom_data, expr; + rx_lane_disabled_vec_16_31, 0b0000111111111111, any; +} + +#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_MODE_PG +scom 0x80081840(xbus_base_addr) { + bits, scom_data, expr; + rx_master_mode, 0b1, def_is_master; +} + +#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG +scom 0x800AB840(xbus_base_addr) { + bits, scom_data, expr; + rx_rc_enable_dll_update, 0b1 , HW_EXPRESS; + rx_rc_enable_dll_update, 0b0 , VBU_EXPRESS; + rx_rc_enable_edge_track, 0b1 , HW_EXPRESS; + rx_rc_enable_edge_track, 0b0 , VBU_EXPRESS; + rx_rc_enable_measure_eye_width, 0b1 , HW_EXPRESS; + rx_rc_enable_measure_eye_width, 0b0 , VBU_EXPRESS; + rx_rc_enable_result_check, 0b1 , HW_EXPRESS; + rx_rc_enable_result_check, 0b0 , VBU_EXPRESS; +} + +#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP +scom 0x800B6040(xbus_base_addr) { + bits, scom_data, expr; + rx_servo_timeout_sel_a, 0b0101 , HW_EXPRESS; + rx_servo_timeout_sel_a, 0b1000 , VBU_EXPRESS; + rx_servo_timeout_sel_b, 0b1010 , HW_EXPRESS; + rx_servo_timeout_sel_b, 0b1000 , VBU_EXPRESS; + rx_servo_timeout_sel_c, 0b0101 , HW_EXPRESS; + rx_servo_timeout_sel_c, 0b1000 , VBU_EXPRESS; +} + +#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP +scom 0x800B6840(xbus_base_addr) { + bits, scom_data, expr; + rx_servo_timeout_sel_f, 0b1000 , HW_EXPRESS; + rx_servo_timeout_sel_f, 0b0110 , VBU_EXPRESS; + rx_servo_timeout_sel_h, 0b0110 , HW_EXPRESS; + rx_servo_timeout_sel_h, 0b1000 , VBU_EXPRESS; +} + +#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_SPARE_MODE_PG +scom 0x80080840(xbus_base_addr) { + bits, scom_data, expr; + rx_sls_extend_sel, 0b101, def_is_slave; +} + +#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG +scom 0x80089840(xbus_base_addr) { + bits, scom_data, expr; + rx_sls_timeout_sel, 0b001, any; +} + +#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG +scom 0x80099840(xbus_base_addr) { + bits, scom_data, expr; + rx_rx_bus_width, 0b1010000, any; + rx_tx_bus_width, 0b1010000, any; +} + +#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG +scom 0x80095840(xbus_base_addr) { + bits, scom_data, expr; + rx_wtr_max_bad_lanes, 0b00010, any; +} + +#RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B040(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b000, any; +} + +#RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B041(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b001, any; +} + +#RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B042(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b010, any; +} + +#RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B043(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b011, any; +} + +#RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B044(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b100, any; +} + +#RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B045(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b101, any; +} + +#RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B046(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b110, any; +} + +#RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B047(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b111, any; +} + +#RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B048(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b000, any; +} + +#RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B049(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b001, any; +} + +#RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B04A(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b001, any; +} + +#RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B04B(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b000, any; +} + +#RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B04C(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b111, any; +} + +#RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B04D(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b110, any; +} + +#RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B04E(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b101, any; +} + +#RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B04F(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b100, any; +} + +#RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B050(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b011, any; +} + +#RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B051(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b010, any; +} + +#RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B052(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b001, any; +} + +#RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B053(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b000, any; +} + +#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG +scom 0x8009D860(xbus_base_addr) { + bits, scom_data, expr; + rx_dyn_rpr_bad_lane_max, 0b0001111, any; + rx_dyn_rpr_enc_bad_data_lane_width, 0b111, any; + rx_dyn_rpr_err_cntr1_duration, 0b1010, any; +} + +#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG +scom 0x800AE060(xbus_base_addr) { + bits, scom_data, expr; + rx_dyn_rpr_bad_bus_max, 0b0011111, any; + rx_dyn_rpr_err_cntr2_duration, 0b0111, any; +} + +#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_CNTL_PP +scom 0x800B1860(xbus_base_addr) { + bits, scom_data, expr; + rx_ddc_use_cyc_block_lock, 0b0 , HW_EXPRESS; + rx_ddc_use_cyc_block_lock, 0b1 , VBU_EXPRESS; +} + +#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_A_D_PP +scom 0x800B3060(xbus_base_addr) { + bits, scom_data, expr; + rx_cal_dec_val_a, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_a, 0b1000 , VBU_EXPRESS; + rx_cal_dec_val_b, 0b0001 , HW_EXPRESS; + rx_cal_dec_val_b, 0b0000 , VBU_EXPRESS; + rx_cal_dec_val_c, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_c, 0b0000 , VBU_EXPRESS; + rx_cal_dec_val_d, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_d, 0b1110 , VBU_EXPRESS; +} + +#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_E_H_PP +scom 0x800B3860(xbus_base_addr) { + bits, scom_data, expr; + rx_cal_dec_val_e, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_e, 0b1110 , VBU_EXPRESS; + rx_cal_dec_val_f, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_f, 0b0000 , VBU_EXPRESS; + rx_cal_dec_val_g, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_g, 0b0000 , VBU_EXPRESS; + rx_cal_dec_val_h, 0b1111 , HW_EXPRESS; + rx_cal_dec_val_h, 0b0000 , VBU_EXPRESS; +} + +#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_A_D_PP +scom 0x800B2060(xbus_base_addr) { + bits, scom_data, expr; + rx_cal_inc_val_a, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_a, 0b1000 , VBU_EXPRESS; + rx_cal_inc_val_b, 0b0001 , HW_EXPRESS; + rx_cal_inc_val_b, 0b0000 , VBU_EXPRESS; + rx_cal_inc_val_c, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_c, 0b0000 , VBU_EXPRESS; + rx_cal_inc_val_d, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_d, 0b1110 , VBU_EXPRESS; +} + +#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_E_H_PP +scom 0x800B2860(xbus_base_addr) { + bits, scom_data, expr; + rx_cal_inc_val_e, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_e, 0b1110 , VBU_EXPRESS; + rx_cal_inc_val_f, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_f, 0b0000 , VBU_EXPRESS; + rx_cal_inc_val_g, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_g, 0b0000 , VBU_EXPRESS; + rx_cal_inc_val_h, 0b1111 , HW_EXPRESS; + rx_cal_inc_val_h, 0b0000 , VBU_EXPRESS; +} + +#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG +scom 0x800A3860(xbus_base_addr) { + bits, scom_data, expr; + rx_eo_enable_ber_test, 0b1 , HW_EXPRESS; + rx_eo_enable_ber_test, 0b0 , VBU_EXPRESS; + rx_eo_enable_ctle_cal, 0b1 , HW_EXPRESS; + rx_eo_enable_ctle_cal, 0b0 , VBU_EXPRESS; + rx_eo_enable_dcd_cal, 0b1 , HW_EXPRESS; + rx_eo_enable_dcd_cal, 0b0 , VBU_EXPRESS; + rx_eo_enable_final_l2u_adj, 0b1, any; + rx_eo_enable_latch_offset_cal, 0b1 , HW_EXPRESS; + rx_eo_enable_latch_offset_cal, 0b0 , VBU_EXPRESS; + rx_eo_enable_measure_eye_width, 0b1 , HW_EXPRESS; + rx_eo_enable_measure_eye_width, 0b0 , VBU_EXPRESS; + rx_eo_enable_result_check, 0b1 , HW_EXPRESS; + rx_eo_enable_result_check, 0b0 , VBU_EXPRESS; + rx_eo_enable_vref_cal, 0b1 , HW_EXPRESS; + rx_eo_enable_vref_cal, 0b0 , VBU_EXPRESS; +} + +#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_FENCE_PG +scom 0x8009A860(xbus_base_addr) { + bits, scom_data, expr; + rx_fence, 0b1, any; +} + +#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_ID1_PG +scom 0x80085060(xbus_base_addr) { + bits, scom_data, expr; + rx_bus_id, 0b000000, any; + rx_group_id, 0b000011, any; +} + +#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_ID2_PG +scom 0x80085860(xbus_base_addr) { + bits, scom_data, expr; + rx_last_group_id, 0b000011, any; +} + +#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_ID3_PG +scom 0x80086060(xbus_base_addr) { + bits, scom_data, expr; + rx_end_lane_id, 0b1001111, any; + rx_start_lane_id, 0b0111100, any; +} + +#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG +scom 0x80092860(xbus_base_addr) { + bits, scom_data, expr; + rx_lane_disabled_vec_0_15, 0b0000000000000000, any; +} + +#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG +scom 0x80093060(xbus_base_addr) { + bits, scom_data, expr; + rx_lane_disabled_vec_16_31, 0b0000111111111111, any; +} + +#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_MODE_PG +scom 0x80081860(xbus_base_addr) { + bits, scom_data, expr; + rx_master_mode, 0b1, def_is_master; +} + +#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG +scom 0x800AB860(xbus_base_addr) { + bits, scom_data, expr; + rx_rc_enable_dll_update, 0b1 , HW_EXPRESS; + rx_rc_enable_dll_update, 0b0 , VBU_EXPRESS; + rx_rc_enable_edge_track, 0b1 , HW_EXPRESS; + rx_rc_enable_edge_track, 0b0 , VBU_EXPRESS; + rx_rc_enable_measure_eye_width, 0b1 , HW_EXPRESS; + rx_rc_enable_measure_eye_width, 0b0 , VBU_EXPRESS; + rx_rc_enable_result_check, 0b1 , HW_EXPRESS; + rx_rc_enable_result_check, 0b0 , VBU_EXPRESS; +} + +#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP +scom 0x800B6060(xbus_base_addr) { + bits, scom_data, expr; + rx_servo_timeout_sel_a, 0b0101 , HW_EXPRESS; + rx_servo_timeout_sel_a, 0b1000 , VBU_EXPRESS; + rx_servo_timeout_sel_b, 0b1010 , HW_EXPRESS; + rx_servo_timeout_sel_b, 0b1000 , VBU_EXPRESS; + rx_servo_timeout_sel_c, 0b0101 , HW_EXPRESS; + rx_servo_timeout_sel_c, 0b1000 , VBU_EXPRESS; +} + +#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP +scom 0x800B6860(xbus_base_addr) { + bits, scom_data, expr; + rx_servo_timeout_sel_f, 0b1000 , HW_EXPRESS; + rx_servo_timeout_sel_f, 0b0110 , VBU_EXPRESS; + rx_servo_timeout_sel_h, 0b0110 , HW_EXPRESS; + rx_servo_timeout_sel_h, 0b1000 , VBU_EXPRESS; +} + +#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_SPARE_MODE_PG +scom 0x80080860(xbus_base_addr) { + bits, scom_data, expr; + rx_sls_extend_sel, 0b101, def_is_slave; +} + +#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG +scom 0x80089860(xbus_base_addr) { + bits, scom_data, expr; + rx_sls_timeout_sel, 0b001, any; +} + +#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG +scom 0x80099860(xbus_base_addr) { + bits, scom_data, expr; + rx_rx_bus_width, 0b1010000, any; + rx_tx_bus_width, 0b1010000, any; +} + +#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG +scom 0x80095860(xbus_base_addr) { + bits, scom_data, expr; + rx_wtr_max_bad_lanes, 0b00010, any; +} + +#RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B060(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b000, any; +} + +#RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B061(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b001, any; +} + +#RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B062(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b010, any; +} + +#RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B063(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b011, any; +} + +#RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B064(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b100, any; +} + +#RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B065(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b101, any; +} + +#RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B066(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b110, any; +} + +#RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B067(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b111, any; +} + +#RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B068(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b000, any; +} + +#RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B069(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b001, any; +} + +#RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B06A(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b001, any; +} + +#RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B06B(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b000, any; +} + +#RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B06C(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b111, any; +} + +#RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B06D(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b110, any; +} + +#RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B06E(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b101, any; +} + +#RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B06F(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b100, any; +} + +#RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B070(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b011, any; +} + +#RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B071(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b010, any; +} + +#RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B072(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b001, any; +} + +#RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL +scom 0x8000B073(xbus_base_addr) { + bits, scom_data, expr; + rx_prbs_tap_id, 0b000, any; +} + +#TX01_GEN.TX01.TX0.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG +scom 0x800CC400(xbus_base_addr) { + bits, scom_data, expr; + tx_drv_clk_pattern_gcrmsg, 0b00, any; +} + +#TX01_GEN.TX01.TX0.TXCTL.TX_CTL_REGS.TX_ID1_PG +scom 0x800C9400(xbus_base_addr) { + bits, scom_data, expr; + tx_bus_id, 0b000000, any; + tx_group_id, 0b100000, any; +} + +#TX01_GEN.TX01.TX0.TXCTL.TX_CTL_REGS.TX_ID2_PG +scom 0x800C9C00(xbus_base_addr) { + bits, scom_data, expr; + tx_last_group_id, 0b100011, any; +} + +#TX01_GEN.TX01.TX0.TXCTL.TX_CTL_REGS.TX_ID3_PG +scom 0x800CA400(xbus_base_addr) { + bits, scom_data, expr; + tx_end_lane_id, 0b0010011, any; + tx_start_lane_id, 0b0000000, any; +} + +#TX01_GEN.TX01.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG +scom 0x800D1C00(xbus_base_addr) { + bits, scom_data, expr; + tx_lane_disabled_vec_0_15, 0b0000000000000000, any; +} + +#TX01_GEN.TX01.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG +scom 0x800D2400(xbus_base_addr) { + bits, scom_data, expr; + tx_lane_disabled_vec_16_31, 0b0000111111111111, any; +} + +#TX01_GEN.TX01.TX0.TXCTL.TX_CTL_REGS.TX_MODE_PG +scom 0x800C1C00(xbus_base_addr) { + bits, scom_data, expr; + tx_max_bad_lanes, 0b00010, any; +} + +#TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043400(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b000, any; +} + +#TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043401(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b001, any; +} + +#TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043402(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b010, any; +} + +#TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043403(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b011, any; +} + +#TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043404(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b100, any; +} + +#TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043405(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b101, any; +} + +#TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043406(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b110, any; +} + +#TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043407(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b111, any; +} + +#TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043408(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b000, any; +} + +#TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043409(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b001, any; +} + +#TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340A(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b001, any; +} + +#TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340B(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b000, any; +} + +#TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340C(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b111, any; +} + +#TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340D(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b110, any; +} + +#TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340E(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b101, any; +} + +#TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340F(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b100, any; +} + +#TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043410(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b011, any; +} + +#TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043411(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b010, any; +} + +#TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043412(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b001, any; +} + +#TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043413(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b000, any; +} + +#TX01_GEN.TX01.TX1.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG +scom 0x800CC420(xbus_base_addr) { + bits, scom_data, expr; + tx_drv_clk_pattern_gcrmsg, 0b00, any; +} + +#TX01_GEN.TX01.TX1.TXCTL.TX_CTL_REGS.TX_ID1_PG +scom 0x800C9420(xbus_base_addr) { + bits, scom_data, expr; + tx_bus_id, 0b000000, any; + tx_group_id, 0b100001, any; +} + +#TX01_GEN.TX01.TX1.TXCTL.TX_CTL_REGS.TX_ID2_PG +scom 0x800C9C20(xbus_base_addr) { + bits, scom_data, expr; + tx_last_group_id, 0b100011, any; +} + +#TX01_GEN.TX01.TX1.TXCTL.TX_CTL_REGS.TX_ID3_PG +scom 0x800CA420(xbus_base_addr) { + bits, scom_data, expr; + tx_end_lane_id, 0b0100111, any; + tx_start_lane_id, 0b0010100, any; +} + +#TX01_GEN.TX01.TX1.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG +scom 0x800D1C20(xbus_base_addr) { + bits, scom_data, expr; + tx_lane_disabled_vec_0_15, 0b0000000000000000, any; +} + +#TX01_GEN.TX01.TX1.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG +scom 0x800D2420(xbus_base_addr) { + bits, scom_data, expr; + tx_lane_disabled_vec_16_31, 0b0000111111111111, any; +} + +#TX01_GEN.TX01.TX1.TXCTL.TX_CTL_REGS.TX_MODE_PG +scom 0x800C1C20(xbus_base_addr) { + bits, scom_data, expr; + tx_max_bad_lanes, 0b00010, any; +} + +#TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043420(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b000, any; +} + +#TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043421(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b001, any; +} + +#TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043422(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b010, any; +} + +#TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043423(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b011, any; +} + +#TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043424(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b100, any; +} + +#TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043425(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b101, any; +} + +#TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043426(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b110, any; +} + +#TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043427(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b111, any; +} + +#TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043428(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b000, any; +} + +#TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043429(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b001, any; +} + +#TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004342A(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b001, any; +} + +#TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004342B(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b000, any; +} + +#TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004342C(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b111, any; +} + +#TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004342D(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b110, any; +} + +#TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004342E(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b101, any; +} + +#TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004342F(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b100, any; +} + +#TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043430(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b011, any; +} + +#TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043431(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b010, any; +} + +#TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043432(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b001, any; +} + +#TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043433(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b000, any; +} + +#TX23_GEN.TX23.TX0.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG +scom 0x800CC440(xbus_base_addr) { + bits, scom_data, expr; + tx_drv_clk_pattern_gcrmsg, 0b00, any; +} + +#TX23_GEN.TX23.TX0.TXCTL.TX_CTL_REGS.TX_ID1_PG +scom 0x800C9440(xbus_base_addr) { + bits, scom_data, expr; + tx_bus_id, 0b000000, any; + tx_group_id, 0b100010, any; +} + +#TX23_GEN.TX23.TX0.TXCTL.TX_CTL_REGS.TX_ID2_PG +scom 0x800C9C40(xbus_base_addr) { + bits, scom_data, expr; + tx_last_group_id, 0b100011, any; +} + +#TX23_GEN.TX23.TX0.TXCTL.TX_CTL_REGS.TX_ID3_PG +scom 0x800CA440(xbus_base_addr) { + bits, scom_data, expr; + tx_end_lane_id, 0b0111011, any; + tx_start_lane_id, 0b0101000, any; +} + +#TX23_GEN.TX23.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG +scom 0x800D1C40(xbus_base_addr) { + bits, scom_data, expr; + tx_lane_disabled_vec_0_15, 0b0000000000000000, any; +} + +#TX23_GEN.TX23.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG +scom 0x800D2440(xbus_base_addr) { + bits, scom_data, expr; + tx_lane_disabled_vec_16_31, 0b0000111111111111, any; +} + +#TX23_GEN.TX23.TX0.TXCTL.TX_CTL_REGS.TX_MODE_PG +scom 0x800C1C40(xbus_base_addr) { + bits, scom_data, expr; + tx_max_bad_lanes, 0b00010, any; +} + +#TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043440(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b000, any; +} + +#TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043441(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b001, any; +} + +#TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043442(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b010, any; +} + +#TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043443(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b011, any; +} + +#TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043444(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b100, any; +} + +#TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043445(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b101, any; +} + +#TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043446(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b110, any; +} + +#TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043447(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b111, any; +} + +#TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043448(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b000, any; +} + +#TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043449(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b001, any; +} + +#TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004344A(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b001, any; +} + +#TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004344B(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b000, any; +} + +#TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004344C(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b111, any; +} + +#TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004344D(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b110, any; +} + +#TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004344E(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b101, any; +} + +#TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004344F(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b100, any; +} + +#TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043450(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b011, any; +} + +#TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043451(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b010, any; +} + +#TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043452(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b001, any; +} + +#TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043453(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b000, any; +} + +#TX23_GEN.TX23.TX1.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG +scom 0x800CC460(xbus_base_addr) { + bits, scom_data, expr; + tx_drv_clk_pattern_gcrmsg, 0b00, any; +} + +#TX23_GEN.TX23.TX1.TXCTL.TX_CTL_REGS.TX_ID1_PG +scom 0x800C9460(xbus_base_addr) { + bits, scom_data, expr; + tx_bus_id, 0b000000, any; + tx_group_id, 0b100011, any; +} + +#TX23_GEN.TX23.TX1.TXCTL.TX_CTL_REGS.TX_ID2_PG +scom 0x800C9C60(xbus_base_addr) { + bits, scom_data, expr; + tx_last_group_id, 0b100011, any; +} + +#TX23_GEN.TX23.TX1.TXCTL.TX_CTL_REGS.TX_ID3_PG +scom 0x800CA460(xbus_base_addr) { + bits, scom_data, expr; + tx_end_lane_id, 0b1001111, any; + tx_start_lane_id, 0b0111100, any; +} + +#TX23_GEN.TX23.TX1.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG +scom 0x800D1C60(xbus_base_addr) { + bits, scom_data, expr; + tx_lane_disabled_vec_0_15, 0b0000000000000000, any; +} + +#TX23_GEN.TX23.TX1.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG +scom 0x800D2460(xbus_base_addr) { + bits, scom_data, expr; + tx_lane_disabled_vec_16_31, 0b0000111111111111, any; +} + +#TX23_GEN.TX23.TX1.TXCTL.TX_CTL_REGS.TX_MODE_PG +scom 0x800C1C60(xbus_base_addr) { + bits, scom_data, expr; + tx_max_bad_lanes, 0b00010, any; +} + +#TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043460(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b000, any; +} + +#TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043461(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b001, any; +} + +#TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043462(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b010, any; +} + +#TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043463(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b011, any; +} + +#TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043464(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b100, any; +} + +#TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043465(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b101, any; +} + +#TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043466(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b110, any; +} + +#TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043467(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b111, any; +} + +#TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043468(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b000, any; +} + +#TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043469(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b001, any; +} + +#TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004346A(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b001, any; +} + +#TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004346B(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b000, any; +} + +#TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004346C(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b111, any; +} + +#TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004346D(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b110, any; +} + +#TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004346E(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b101, any; +} + +#TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004346F(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b100, any; +} + +#TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043470(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b011, any; +} + +#TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043471(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b010, any; +} + +#TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043472(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b001, any; +} + +#TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x80043473(xbus_base_addr) { + bits, scom_data, expr; + tx_prbs_tap_id, 0b000, any; +} + + +###################################### +## END OF FILE +####################################### diff --git a/src/usr/hwpf/hwp/mc_config/makefile b/src/usr/hwpf/hwp/mc_config/makefile index 821bdfcb9..f0a7fc5eb 100644 --- a/src/usr/hwpf/hwp/mc_config/makefile +++ b/src/usr/hwpf/hwp/mc_config/makefile @@ -1,25 +1,25 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. # -# $Source: src/usr/hwpf/hwp/mc_config/makefile $ +# $Source: src/usr/hwpf/hwp/mc_config/makefile $ # -# IBM CONFIDENTIAL +# IBM CONFIDENTIAL # -# COPYRIGHT International Business Machines Corp. 2012 +# COPYRIGHT International Business Machines Corp. 2012,2013 # -# p1 +# p1 # -# Object Code Only (OCO) source materials -# Licensed Internal Code Source Materials -# IBM HostBoot Licensed Internal Code +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code # -# The source code for this program is not published or other- -# wise divested of its trade secrets, irrespective of what has -# been deposited with the U.S. Copyright Office. +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. # -# Origin: 30 +# Origin: 30 # -# IBM_PROLOG_END_TAG +# IBM_PROLOG_END_TAG ROOTPATH = ../../../../.. MODULE = mc_config @@ -51,8 +51,9 @@ OBJS = mc_config.o \ mss_eff_config_rank_group.o \ mss_eff_config_cke_map.o \ mss_bulk_pwr_throttles.o \ - mss_throttle_to_power.o - + mss_throttle_to_power.o \ + mss_eff_config_shmoo.o + ## NOTE: add a new directory onto the vpaths when you add a new HWP ##@ VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/??? VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_eff_config diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C index 2152d137e..6a2547e9e 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_config.C,v 1.16 2013/01/24 18:33:16 bellows Exp $ +// $Id: mss_eff_config.C,v 1.20 2013/02/28 21:36:08 asaetow Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/ // centaur/working/procedures/ipl/fapi/mss_eff_config.C,v $ //------------------------------------------------------------------------------ @@ -44,7 +44,12 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- -// 1.17 | | | +// 1.21 | | | +// 1.20 | asaetow |28-Feb-13| Changed temporary ATTR_EFF_ZQCAL_INTERVAL and ATTR_EFF_MEMCAL_INTERVAL to disable. +// | | | NOTE: Temporary until we get timeout error fixed. +// 1.19 | sauchadh |26-Feb-13| Added MCBIST related attributes +// 1.18 | asaetow |12-FEB-13| Changed eff_dram_tdqs from 1 to 0. +// 1.17 | asaetow |30-JAN-13| Changed "ATTR_SPD_MODULE_TYPE_CDIMM is obsolete..." message from error to warning. // 1.16 | bellows |24-JAN-13| Added in CUSTOM bit of SPD and CUSTOM Attr // | | | settings. // 1.15 | asaetow |15-NOV-12| Added call to mss_eff_config_cke_map(). @@ -128,6 +133,8 @@ #include <mss_eff_config_cke_map.H> #include <mss_eff_config_termination.H> #include <mss_eff_config_thermal.H> +#include <mss_eff_config_shmoo.H> + //------------------------------------------------------------------------------ // Includes @@ -1083,7 +1090,7 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( { case fapi::ENUM_ATTR_SPD_MODULE_TYPE_CDIMM: p_o_atts->eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM; - FAPI_ERR("ATTR_SPD_MODULE_TYPE_CDIMM is obsolete. Check your VPD for correct definition on %s!", i_target_mba.toEcmdString()); + FAPI_INF("WARNING: ATTR_SPD_MODULE_TYPE_CDIMM is obsolete. Check your VPD for correct definition on %s!", i_target_mba.toEcmdString()); break; case fapi::ENUM_ATTR_SPD_MODULE_TYPE_RDIMM: p_o_atts->eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM; @@ -1185,7 +1192,7 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( { p_o_atts->eff_dram_width = fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8; // NOTE: TDQS enable MR1(A11) is only avaliable for X8 in DDR3 - p_o_atts->eff_dram_tdqs = 1; + p_o_atts->eff_dram_tdqs = 0; } else if (p_i_data->dram_width[0][0] == fapi::ENUM_ATTR_SPD_DRAM_WIDTH_W16) @@ -1518,12 +1525,16 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( // 0.5 // ------------------------------ = 13.333ms // (1.5 * 10) + (0.15 * 150) - p_o_atts->eff_zqcal_interval = ( 13333 * - p_i_mss_eff_config_data->mss_freq) / 2; + + p_o_atts->eff_zqcal_interval = 0; + //p_o_atts->eff_zqcal_interval = ( 13333 * + // p_i_mss_eff_config_data->mss_freq) / 2; //------------------------------------------------------------------------------ // Calculate MEMCAL Interval based on 1sec interval across all bits per DP18 - p_o_atts->eff_memcal_interval = (62500 * - p_i_mss_eff_config_data->mss_freq) / 2; + + p_o_atts->eff_memcal_interval = 0; + //p_o_atts->eff_memcal_interval = (62500 * + // p_i_mss_eff_config_data->mss_freq) / 2; //------------------------------------------------------------------------------ // Calculate tRFI p_o_atts->eff_dram_trfi = (3900 * @@ -2075,6 +2086,7 @@ fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba) rc = mss_eff_config_cke_map(i_target_mba); if(rc) break; rc = mss_eff_config_termination(i_target_mba); if(rc) break; rc = mss_eff_config_thermal(i_target_mba); if(rc) break; + rc = mss_eff_config_shmoo(i_target_mba); if(rc) break; FAPI_INF("%s on %s COMPLETE\n", PROCEDURE_NAME, diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C new file mode 100644 index 000000000..ed3c8fb90 --- /dev/null +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C @@ -0,0 +1,117 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: mss_eff_config_shmoo.C,v 1.1 2013/02/26 12:38:20 lapietra Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_shmoo.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : mss_eff_config_shmoo +// *! DESCRIPTION : Additional attributes for MCBIST +// *! OWNER NAME : Saurabh Chadha Email: sauchadh@in.ibm.com +// *! BACKUP NAME : Email: +// *! ADDITIONAL COMMENTS : +// +//------------------------------------------------------------------------------ +// Don't forget to create CVS comments when you check in your changes! +//------------------------------------------------------------------------------ +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version:| Author: | Date: | Comment: +//---------|----------|---------|----------------------------------------------- +// 1.1 | sauchadh |26-Feb-13| Added MCBIST related attributes + + + +//---------------------------------------------------------------------- +// My Includes +//---------------------------------------------------------------------- + + + +//---------------------------------------------------------------------- +// Includes +//---------------------------------------------------------------------- +#include <fapi.H> + + +extern "C" { + + + +//****************************************************************************** +//* name=mss_eff_config_shmoo, param=i_target_mba, return=ReturnCode +//****************************************************************************** +fapi::ReturnCode mss_eff_config_shmoo(const fapi::Target i_target_mba) { + fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS; + const char * const PROCEDURE_NAME = "mss_eff_config_shmoo"; + FAPI_INF("*** Running %s on %s ... ***", PROCEDURE_NAME, i_target_mba.toEcmdString()); + + uint32_t datapattern=8; + uint32_t testtype=1; + uint8_t addr_modes=0; + uint8_t rank=0; + uint64_t start_addr=0; + uint64_t end_addr=0; + uint8_t error_capture=0; + uint64_t max_timeout=0; + uint8_t print_port=0; + uint8_t stop_on_error=0; + uint32_t data_seed=0; + uint8_t addr_inter=0; + uint8_t addr_num_rows=0; + uint8_t addr_num_cols=0; + uint8_t addr_rank=0; + uint8_t addr_bank=0; + uint8_t addr_slave_rank_on=0; + uint64_t adr_str_map=0; + uint8_t addr_rand=0; + + rc = FAPI_ATTR_SET(ATTR_MCBIST_PATTERN, &i_target_mba, datapattern); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_MCBIST_TEST_TYPE, &i_target_mba, testtype); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_MODES, &i_target_mba, addr_modes); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_MCBIST_RANK, &i_target_mba, rank); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_MCBIST_START_ADDR, &i_target_mba, start_addr); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_MCBIST_END_ADDR, &i_target_mba, end_addr); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_MCBIST_ERROR_CAPTURE, &i_target_mba, error_capture); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_MCBIST_MAX_TIMEOUT, &i_target_mba, max_timeout); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_MCBIST_PRINT_PORT, &i_target_mba, print_port); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_MCBIST_STOP_ON_ERROR, &i_target_mba, stop_on_error); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_MCBIST_DATA_SEED, &i_target_mba, data_seed); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_INTER, &i_target_mba, addr_inter); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_NUM_ROWS, &i_target_mba, addr_num_rows); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_NUM_COLS, &i_target_mba, addr_num_cols); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_RANK, &i_target_mba, addr_rank); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_BANK, &i_target_mba, addr_bank); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_SLAVE_RANK_ON, &i_target_mba, addr_slave_rank_on); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_STR_MAP, &i_target_mba, adr_str_map); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_RAND, &i_target_mba, addr_rand); if(rc) return rc; + + FAPI_INF("%s on %s COMPLETE", PROCEDURE_NAME, i_target_mba.toEcmdString()); + return rc; +} + + + +} // extern "C" diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.H new file mode 100644 index 000000000..7ea67d5e1 --- /dev/null +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.H @@ -0,0 +1,73 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: mss_eff_config_shmoo.H,v 1.1 2013/02/26 12:38:36 lapietra Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_shmoo.H,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : mss_eff_config_shmoo.H +// *! DESCRIPTION : Header file for mss_eff_config_shmoo.C +// *! OWNER NAME : Saurabh Chadha Email: sauchadh@in.ibm.com +// *! BACKUP NAME : Email: +// *! ADDITIONAL COMMENTS : +// +// +// +//------------------------------------------------------------------------------ +// Don't forget to create CVS comments when you check in your changes! +//------------------------------------------------------------------------------ +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version:| Author: | Date: | Comment: +//---------|----------|---------|----------------------------------------------- +// 1.1 | sauchadh |26-Feb-13| First Draft + + +#ifndef MSS_EFF_CONFIG_SHMOO_H_ +#define MSS_EFF_CONFIG_SHMOO_H_ + +//---------------------------------------------------------------------- +// My Includes +//---------------------------------------------------------------------- + + +//---------------------------------------------------------------------- +// Includes +//---------------------------------------------------------------------- +#include <fapi.H> + + +typedef fapi::ReturnCode (*mss_eff_config_shmoo_FP_t)(const fapi::Target i_target_mba); + +extern "C" { + +//****************************************************************************** +//* name=mss_eff_config_shmoo, param=i_target_mba, return=ReturnCode +//****************************************************************************** +fapi::ReturnCode mss_eff_config_shmoo(const fapi::Target i_target_mba); + +} // extern "C" + +#endif // MSS_EFF_CONFIG_SHMOO_H_ diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C index 48c356339..9a9d7e674 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_grouping.C,v 1.16 2012/12/14 08:41:20 gpaulraj Exp $ +// $Id: mss_eff_grouping.C,v 1.18 2013/02/01 23:38:22 asaetow Exp $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -38,7 +38,10 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- -// 1.16 | gpaulraj | 12-14-12| Modified "unable to group dimm size" as Error message +// 1.18 | asaetow | 02-01-13| Removed FAPI_ERR("Mirror Base address overlaps with memory base address. "); temporarily. +// | | | NOTE: Need Giri to check mirroring enable before checking for overlaps. +// 1.17 | gpaulraj | 01-31-13| Error place holders added +// 1.16 | gpaulraj | 12-14-12| Modified "nnable to group dimm size" as Error message // 1.15 | bellows | 12-11-12| Picked up latest updates from Girisankar // 1.14 | bellows | 12-11-12| added ; to DBG line // 1.13 | bellows | 12-07-12| fix for interleaving attr and array bounds @@ -230,8 +233,45 @@ extern "C" { rc = FAPI_ATTR_GET(ATTR_ALL_MCS_IN_INTERLEAVING_GROUP, NULL,check_board); // system level attribute if (!rc.ok()) { FAPI_ERR("Error reading ATTR_ALL_MCS_IN_INTERLEAVING_GROUP"); return rc; } + if(check_board) + { + if((groups_allowed & 0x02) || (groups_allowed & 0x04)||(groups_allowed & 0x08)) + { + FAPI_INF("FABRIC IS IN NON-CHECKER BOARD MODE."); + FAPI_INF("FABRIC SUPPORTS THE FOLLOWING "); +//@thi - Already asked Anuwat to fix this + if( (groups_allowed & 0x02)&& check_board){FAPI_INF("2MCS/GROUP");} + if( (groups_allowed & 0x04)&& check_board){FAPI_INF("4MCS/GROUP");} + if( (groups_allowed & 0x08)&& check_board){FAPI_INF("8MCS/GROUP");} + FAPI_INF("FABRIC DOES NOT SUPPORT THE FOLLOWING "); + if(! ((groups_allowed & 0x01)&& !check_board)){FAPI_INF("1MCS/GROUP");} + if(!((groups_allowed & 0x02)&& check_board)){FAPI_INF("2MCS/GROUP");} + if(!((groups_allowed & 0x04)&& check_board)){FAPI_INF("4MCS/GROUP");} + if(!((groups_allowed & 0x08)&& check_board)){FAPI_INF("8MCS/GROUP");} + } + else + { + FAPI_ERR("UNABLE TO GROUP"); + FAPI_ERR("FABRIC IS IN NON-CHECKER BOARD MODE. SET ATTRIBUTE 'ATTR_MSS_INTERLEAVE_ENABLE' TO SUPPORT '2MCS/GROUP, 4MCS/GROUP AND 8MCS/GROUP'. OR ENABLE CHECKER BOARD, TO SUPPORT '1MCS/GROUP'. "); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + return rc; + } + } + else + { + if(groups_allowed & 0x01) { + FAPI_INF("FABRIC IS IN CHECKER BOARD MODE AND IT SUPPORTS 1MCS/GROUP"); } + else { + FAPI_ERR("UNABLE TO GROUP"); + FAPI_ERR("FABRIC IS IN CHECKER BOARD MODE BUT IT DOES NOT SUPPORT 1MCS/GROUP. SET ATTRIBUTE 'ATTR_MSS_INTERLEAVE_ENABLE' TO SUPPORT '1MCS/GROUP'. OR DISABLE CHECKER BOARD, TO SUPPORT '2MCS/GROUP, 4MCS/GROUP AND 8MCS/GROUP'."); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + return rc; + } + + + } for(uint8_t i=0;i<16;i++) { grouped[i]=0; @@ -422,15 +462,21 @@ extern "C" { gp++; } } + } if(!done) - { + { uint8_t ungroup =0; for(uint8_t i=0;i<8;i++) { if(grouped[i] !=1 && eff_grouping_data.groupID[i][0] != 0 ) - FAPI_ERR ("UNABLE TO GROUP MCS%d size is %d", i,eff_grouping_data.groupID[i][0]); - } + { FAPI_ERR ("UNABLE TO GROUP MCS%d size is %d", i,eff_grouping_data.groupID[i][0]); ungroup++;} + } + if (ungroup) + { + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + return rc; + } for(uint8_t i=0;i<gp;i++) for(uint8_t j=0;j<16;j++) eff_grouping_data.groupID[i][j]=tempgpID.groupID[i][j]; @@ -464,6 +510,7 @@ extern "C" { uint8_t j=0; count=0; + uint64_t total_size_non_mirr =0; for(pos=0;pos<=gp_pos;pos++) { eff_grouping_data.groupID[pos][2] = eff_grouping_data.groupID[pos][0]*eff_grouping_data.groupID[pos][1]; @@ -484,6 +531,8 @@ extern "C" { //eff_grouping_data.groupID[pos+8][13] = eff_grouping_data.groupID[pos][13]/2; eff_grouping_data.groupID[pos][12] =1; } + + total_size_non_mirr += eff_grouping_data.groupID[pos][2]; } for(i=0;i<gp_pos;i++) { @@ -527,6 +576,8 @@ extern "C" { } } + + rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASE,&i_target,mss_base_address); mss_base_address = mss_base_address >> 30; if(!rc.ok()) return rc; @@ -536,32 +587,58 @@ extern "C" { if(!rc.ok()) return rc; - for(pos=0;pos<gp_pos;pos++) + if( mss_base_address > (mirror_base + total_size_non_mirr/2) || mirror_base > (mss_base_address + total_size_non_mirr)) { - if(pos==0) - { - eff_grouping_data.groupID[pos][3] =mss_base_address; - eff_grouping_data.groupID[pos+8][3]=mirror_base; //mirrored base address - if(eff_grouping_data.groupID[pos][12]) + for(pos=0;pos<gp_pos;pos++) { + if(pos==0) + { - eff_grouping_data.groupID[pos][14] = eff_grouping_data.groupID[pos][3]+ eff_grouping_data.groupID[pos][2]/2; - eff_grouping_data.groupID[pos+8][14] = eff_grouping_data.groupID[pos+8][3]+ eff_grouping_data.groupID[pos+8][2]/2; //mirrored base address with alternate bars - } - } - else - { - eff_grouping_data.groupID[pos][3] = eff_grouping_data.groupID[pos-1][3]+eff_grouping_data.groupID[pos-1][2]; - eff_grouping_data.groupID[pos+8][3]= eff_grouping_data.groupID[pos-1+8][3]+eff_grouping_data.groupID[pos-1+8][2]; + eff_grouping_data.groupID[pos][3] =mss_base_address; - if(eff_grouping_data.groupID[pos][12]) - { - eff_grouping_data.groupID[pos][14] = eff_grouping_data.groupID[pos][3]+ eff_grouping_data.groupID[pos][2]/2; - eff_grouping_data.groupID[pos+8][14] = eff_grouping_data.groupID[pos+8][3]+ eff_grouping_data.groupID[pos+8][2]/2; //mirrored base address with alternate bars + if(eff_grouping_data.groupID[pos][12]) + { + + eff_grouping_data.groupID[pos][14] = eff_grouping_data.groupID[pos][3]+ eff_grouping_data.groupID[pos][2]/2; + + } + } + else + { + eff_grouping_data.groupID[pos][3] = eff_grouping_data.groupID[pos-1][3]+eff_grouping_data.groupID[pos-1][2]; + + + if(eff_grouping_data.groupID[pos][12]) + { + eff_grouping_data.groupID[pos][14] = eff_grouping_data.groupID[pos][3]+ eff_grouping_data.groupID[pos][2]/2; + + } + } + + if(eff_grouping_data.groupID[pos][1]>1 ) + { + eff_grouping_data.groupID[pos+8][3]=mirror_base; + mirror_base= mirror_base + eff_grouping_data.groupID[pos+8][2]; + if(eff_grouping_data.groupID[pos][12]) + { + eff_grouping_data.groupID[pos+8][14] = eff_grouping_data.groupID[pos+8][3]+ eff_grouping_data.groupID[pos+8][2]/2; //mirrored base address with alternate bars + } + + } } - } - } + + } + + // AST HERE: NOTE: Need Giri to check mirroring enable before checking for overlaps. + //else + //{ + // FAPI_ERR("Mirror Base address overlaps with memory base address. "); + // FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + // return rc; + //} + + ecmdDataBufferBase MC_IN_GP(8); uint8_t mcs_in_group[8]; for(uint8_t i=0;i<8;i++) @@ -600,21 +677,21 @@ extern "C" { { if(eff_grouping_data.groupID[i][0]>0) { - FAPI_INF (" Group %d MCS Size %4d ",i,eff_grouping_data.groupID[i][0]); - FAPI_INF (" No of MCS %4d ",eff_grouping_data.groupID[i][1]); - FAPI_INF (" Group Size %4d ",eff_grouping_data.groupID[i][2]); - FAPI_INF (" Base Add. %4d ",eff_grouping_data.groupID[i][3]); - FAPI_INF (" Mirrored Group SIze %4d", eff_grouping_data.groupID[i+8][2]); - FAPI_INF (" Mirror Base Add %4d", eff_grouping_data.groupID[i+8][3]); + FAPI_INF (" Group %d MCS Size %4dGB",i,eff_grouping_data.groupID[i][0]); + FAPI_INF (" No of MCS %4d ",eff_grouping_data.groupID[i][1]); + FAPI_INF (" Group Size %4dGB",eff_grouping_data.groupID[i][2]); + FAPI_INF (" Base Add. %4dGB ",eff_grouping_data.groupID[i][3]); + FAPI_INF (" Mirrored Group SIze %4dGB", eff_grouping_data.groupID[i+8][2]); + FAPI_INF (" Mirror Base Add %4dGB" , eff_grouping_data.groupID[i+8][3]); for(uint8_t j=4;j<4+eff_grouping_data.groupID[i][1];j++) { FAPI_INF (" MCSID%d- Pos %4d",(j-4),eff_grouping_data.groupID[i][j]); } FAPI_INF (" Alter-bar %4d",eff_grouping_data.groupID[i][12]); - FAPI_INF("Alter-bar base add = %4d",eff_grouping_data.groupID[i][14]); - FAPI_INF("Alter-bar size = %4d",eff_grouping_data.groupID[i][13]); - FAPI_INF("Alter-bar Mirrored Base add = %4d", eff_grouping_data.groupID[i+8][14]); - FAPI_INF("Alter-bar Mirrored size = %4d", eff_grouping_data.groupID[i+8][13]); + FAPI_INF("Alter-bar base add = %4dGB ",eff_grouping_data.groupID[i][14]); + FAPI_INF("Alter-bar size = %4dGB",eff_grouping_data.groupID[i][13]); + FAPI_INF("Alter-bar Mirrored Base add = %4dGB ", eff_grouping_data.groupID[i+8][14]); + FAPI_INF("Alter-bar Mirrored size = %4dGB", eff_grouping_data.groupID[i+8][13]); } else { diff --git a/src/usr/hwpf/hwp/mc_config/mss_freq/mss_freq.C b/src/usr/hwpf/hwp/mc_config/mss_freq/mss_freq.C index cfaec3cc1..887428dff 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_freq/mss_freq.C +++ b/src/usr/hwpf/hwp/mc_config/mss_freq/mss_freq.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_freq.C,v 1.18 2012/09/07 22:22:08 jdsloat Exp $ +// $Id: mss_freq.C,v 1.20 2013/02/12 15:20:47 jdsloat Exp $ /* File mss_volt.C created by JEFF SABROWSKI on Fri 21 Oct 2011. */ //------------------------------------------------------------------------------ @@ -58,6 +58,8 @@ // 1.16 | jdsloat | 06/08/12 | Updates per Firware request // 1.17 | bellows | 07/16/12 | added in Id tag // 1.18 | jdsloat | 09/07/12 | Added FTB offset to TAA and TCK +// 1.19 | jdsloat | 01/30/13 | Added Check for l_spd_min_tck_max +// 1.20 | jdsloat | 02/12/13 | Added path for freq_override // // This procedure takes CENTAUR as argument. for each DIMM (under each MBA) // DIMM SPD attributes are read to determine optimal DRAM frequency @@ -122,6 +124,8 @@ fapi::ReturnCode mss_freq(const fapi::Target &i_target_memb) uint8_t module_type_all = 0; uint8_t num_ranks = 0; uint8_t num_ranks_total = 0; + uint32_t l_freq_override = 0; + uint8_t l_override_path = 0; // Get associated MBA's on this centaur l_rc=fapiGetChildChiplets(i_target_memb, fapi::TARGET_TYPE_MBA_CHIPLET, l_mbaChiplets); @@ -177,49 +181,49 @@ fapi::ReturnCode mss_freq(const fapi::Target &i_target_memb) break; } - l_rc = FAPI_ATTR_GET(ATTR_MBA_PORT, &l_dimm_targets[j], cur_mba_port); if(l_rc) return l_rc; + l_rc = FAPI_ATTR_GET(ATTR_MBA_PORT, &l_dimm_targets[j], cur_mba_port); if (l_rc) { FAPI_ERR("Unable to read the Port Info in order to determine configuration."); break; } - l_rc = FAPI_ATTR_GET(ATTR_MBA_DIMM, &l_dimm_targets[j], cur_mba_dimm); if(l_rc) return l_rc; + l_rc = FAPI_ATTR_GET(ATTR_MBA_DIMM, &l_dimm_targets[j], cur_mba_dimm); if (l_rc) { FAPI_ERR("Unable to read the DIMM Info in order to determine configuration."); break; } - l_rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_TYPE, &l_dimm_targets[j], module_type); if(l_rc) return l_rc; + l_rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_TYPE, &l_dimm_targets[j], module_type); if (l_rc) { FAPI_ERR("Unable to read the SPD module type."); break; } - l_rc = FAPI_ATTR_GET(ATTR_SPD_NUM_RANKS, &l_dimm_targets[j], num_ranks); if(l_rc) return l_rc; + l_rc = FAPI_ATTR_GET(ATTR_SPD_NUM_RANKS, &l_dimm_targets[j], num_ranks); if (l_rc) { FAPI_ERR("Unable to read the SPD number of ranks"); break; } - l_rc = FAPI_ATTR_GET(ATTR_SPD_FINE_OFFSET_TAAMIN, &l_dimm_targets[j], l_spd_taa_offset_FTB); if(l_rc) return l_rc; + l_rc = FAPI_ATTR_GET(ATTR_SPD_FINE_OFFSET_TAAMIN, &l_dimm_targets[j], l_spd_taa_offset_FTB); if (l_rc) { FAPI_ERR("Unable to read the SPD TAA offset (FTB)"); break; } - l_rc = FAPI_ATTR_GET(ATTR_SPD_FINE_OFFSET_TCKMIN, &l_dimm_targets[j], l_spd_tck_offset_FTB); if(l_rc) return l_rc; + l_rc = FAPI_ATTR_GET(ATTR_SPD_FINE_OFFSET_TCKMIN, &l_dimm_targets[j], l_spd_tck_offset_FTB); if (l_rc) { FAPI_ERR("Unable to read the SPD TCK offset (FTB)"); break; } - l_rc = FAPI_ATTR_GET(ATTR_SPD_FTB_DIVIDEND, &l_dimm_targets[j], l_spd_ftb_dividend); if(l_rc) return l_rc; + l_rc = FAPI_ATTR_GET(ATTR_SPD_FTB_DIVIDEND, &l_dimm_targets[j], l_spd_ftb_dividend); if (l_rc) { FAPI_ERR("Unable to read the SPD FTB dividend"); break; } - l_rc = FAPI_ATTR_GET(ATTR_SPD_FTB_DIVISOR, &l_dimm_targets[j], l_spd_ftb_divisor); if(l_rc) return l_rc; + l_rc = FAPI_ATTR_GET(ATTR_SPD_FTB_DIVISOR, &l_dimm_targets[j], l_spd_ftb_divisor); if (l_rc) { FAPI_ERR("Unable to read the SPD FTB divisor"); @@ -358,7 +362,46 @@ fapi::ReturnCode mss_freq(const fapi::Target &i_target_memb) l_spd_min_tck_max = 1500; } + if ( l_spd_min_tck_max == 0) + { + FAPI_ERR("l_spd_min_tck_max = 0 unable to calculate freq or cl. Possibly no centaurs configured. "); + FAPI_SET_HWP_ERROR(l_rc, RC_MSS_UNSUPPORTED_SPD_DATA); + } + FAPI_INF( "PLUG CONFIG: %d Type O' Dimm: 0x%02X Num Ranks: %d", plug_config, module_type, num_ranks); + + + l_rc = FAPI_ATTR_GET(ATTR_MSS_FREQ_OVERRIDE, &i_target_memb, l_freq_override); + if ( l_freq_override != 0) + { + // The relationship is as such + // l_dimm_freq_min = 2000000 / l_spd_min_tck_max + + if (l_freq_override == 1866) + { + l_dimm_freq_min = 1866; + l_spd_min_tck_max = 1072; + } + + if (l_freq_override == 1600) + { + l_dimm_freq_min = 1600; + l_spd_min_tck_max = 1250; + } + + if (l_freq_override == 1333) + { + l_dimm_freq_min = 1333; + l_spd_min_tck_max = 1500; + } + + if (l_freq_override == 1066) + { + l_dimm_freq_min = 1066; + l_spd_min_tck_max = 1875; + } + + } if ((l_spd_cas_lat_supported_all == 0) && (!l_rc)) { @@ -379,7 +422,10 @@ fapi::ReturnCode mss_freq(const fapi::Target &i_target_memb) // If the CL proposed is not supported or the TAA exceeds TAA max // Spec defines tAAmax as 20 ns for all DDR3 speed grades. - while ((!( l_spd_cas_lat_supported_all & (0x00000001<<(l_cas_latency-4)))) || (l_cl_mult_tck > 20000)) + // Break loop if we have an override condition without a solution. + + while ( ( (!( l_spd_cas_lat_supported_all & (0x00000001<<(l_cas_latency-4)))) || (l_cl_mult_tck > 20000) ) + && ( l_override_path = 0 ) ) { // If not supported, increment the CL up to 18 (highest supported CL) looking for Supported CL while ((!( l_spd_cas_lat_supported_all & (0x00000001<<(l_cas_latency-4))))&&(l_cas_latency < 18)) @@ -390,7 +436,9 @@ fapi::ReturnCode mss_freq(const fapi::Target &i_target_memb) // If still not supported CL or TAA is > 20 ns ... pick a slower TCK and start again l_cl_mult_tck = l_cas_latency * l_spd_min_tck_max; - if ((!( l_spd_cas_lat_supported_all & (0x00000001<<(l_cas_latency-4)))) || (l_cl_mult_tck > 20000)) + // Do not move freq if using an override freq. Just continue. Hence the overide in this if statement + if ( ( (!( l_spd_cas_lat_supported_all & (0x00000001<<(l_cas_latency-4)))) || (l_cl_mult_tck > 20000) ) + && ( l_freq_override == 0) ) { if (l_spd_min_tck_max < 1500) { @@ -426,6 +474,13 @@ fapi::ReturnCode mss_freq(const fapi::Target &i_target_memb) l_dimm_freq_min = 2000000 / l_spd_min_tck_max; } + // Need to break the loop in case we reach this condition because no longer modify freq and CL + // With an overrride + if ( ( (!( l_spd_cas_lat_supported_all & (0x00000001<<(l_cas_latency-4)))) || (l_cl_mult_tck > 20000) ) + && ( l_freq_override == 1) ) + { + l_override_path = 1; + } } } diff --git a/src/usr/hwpf/hwp/mcbist_attributes.xml b/src/usr/hwpf/hwp/mcbist_attributes.xml new file mode 100644 index 000000000..4ba2b6086 --- /dev/null +++ b/src/usr/hwpf/hwp/mcbist_attributes.xml @@ -0,0 +1,196 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/mcbist_attributes.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<attributes> + +<attribute> + <id>ATTR_MCBIST_PATTERN</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Enables mcbist data pattern selection.</description> + <valueType>uint32</valueType> + <writeable/> + <odmVisable/> +</attribute> + +<attribute> + <id>ATTR_MCBIST_TEST_TYPE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Enables mcbist test type selection.</description> + <valueType>uint32</valueType> + <writeable/> + <odmVisable/> +</attribute> + +<attribute> + <id>ATTR_MCBIST_ADDR_MODES</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Can choose mcbist address mode for full,half or quarter addressing mode.</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> +</attribute> + +<attribute> + <id>ATTR_MCBIST_RANK</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description></description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> +</attribute> + +<attribute> + <id>ATTR_MCBIST_START_ADDR</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Defines the start address for the Mcbist address range</description> + <valueType>uint64</valueType> + <writeable/> + <odmVisable/> +</attribute> + +<attribute> + <id>ATTR_MCBIST_END_ADDR</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Defines the end address for the Mcbist address range</description> + <valueType>uint64</valueType> + <writeable/> + <odmVisable/> +</attribute> + +<attribute> + <id>ATTR_MCBIST_ERROR_CAPTURE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Enables error capture; basically a flag.</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> +</attribute> + +<attribute> + <id>ATTR_MCBIST_MAX_TIMEOUT</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Define mcbist Max timeout</description> + <valueType>uint64</valueType> + <writeable/> + <odmVisable/> +</attribute> + +<attribute> + <id>ATTR_MCBIST_PRINT_PORT</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Enable which port prints are required.</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> +</attribute> + +<attribute> + <id>ATTR_MCBIST_STOP_ON_ERROR</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Flag to stop Mcbist on Error.</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> +</attribute> + +<attribute> + <id>ATTR_MCBIST_DATA_SEED</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Define data seed for the random data pattern or test</description> + <valueType>uint32</valueType> + <writeable/> + <odmVisable/> +</attribute> + +<attribute> + <id>ATTR_MCBIST_ADDR_INTER</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>The address interleave map with user cases or deafult cases of BANK_RANK,RANK_BANK,BANK_ONLY,RANK_ONLYRANKS_DIMM0,RANKS_DIMM1,USER_PATTERN.</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> +</attribute> + +<attribute> + <id>ATTR_MCBIST_ADDR_NUM_ROWS</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>User defined constraint for limiting number of rows for addressing.</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> +</attribute> + +<attribute> + <id>ATTR_MCBIST_ADDR_NUM_COLS</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>User defined constraint for limiting number of columns for addressing.</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> +</attribute> + +<attribute> + <id>ATTR_MCBIST_ADDR_RANK</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>User defined constraint for limiting number of ranks for addressing.</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> +</attribute> + +<attribute> + <id>ATTR_MCBIST_ADDR_BANK</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>User defined constraint for limiting number of banks for addressing.</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> +</attribute> + +<attribute> + <id>ATTR_MCBIST_ADDR_SLAVE_RANK_ON</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>If slave ranks exists;Restrict usage or enable addressing on them as well.</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> +</attribute> + +<attribute> + <id>ATTR_MCBIST_ADDR_STR_MAP</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>To Define custom addressing map ; Input by user.</description> + <valueType>uint64</valueType> + <writeable/> + <odmVisable/> +</attribute> + +<attribute> + <id>ATTR_MCBIST_ADDR_RAND</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Flag for Addressing to go sequential manner or random.</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> +</attribute> + +</attributes> diff --git a/src/usr/hwpf/hwp/memory_attributes.xml b/src/usr/hwpf/hwp/memory_attributes.xml index e6222ef5b..25b2d0f4f 100644 --- a/src/usr/hwpf/hwp/memory_attributes.xml +++ b/src/usr/hwpf/hwp/memory_attributes.xml @@ -37,6 +37,19 @@ firmware notes: none</description> <odmVisable/> </attribute> + <attribute> + <id>ATTR_MSS_FREQ_OVERRIDE</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>FOR LAB USE ONLY: Frequency override of this memory channel in MHz, comprising of up to three DIMMs. Set by config file or an attribute writing program. Consumed by mss_freq. The default of AUTO means mss_freq will find the best frequencies given the DIMMs plugged in and other rules. Otherwise, this is the system frequency. +firmware notes: Platforms should initialize this attribute to AUTO (0)</description> + <valueType>uint32</valueType> + <enum>AUTO = 0</enum> + <platInit/> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + <attribute> <id>ATTR_MSS_FREQ</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> diff --git a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C index 7714ca213..3da56e4d3 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C +++ b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C @@ -517,9 +517,6 @@ void* call_proc_xbus_scominit( void *io_pArgs ) TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_xbus_scominit entry" ); - TARGETING::TargetHandleList l_cpuTargetList; - getAllChips(l_cpuTargetList, TYPE_PROC); - do { EDI_EI_INITIALIZATION::TargetPairs_t l_XbusConnections; @@ -550,106 +547,66 @@ void* call_proc_xbus_scominit( void *io_pArgs ) break; } - // Loop thru the proc - for (TargetHandleList::const_iterator - l_cpuIter = l_cpuTargetList.begin(); - l_cpuIter != l_cpuTargetList.end(); - ++l_cpuIter) + for (EDI_EI_INITIALIZATION::TargetPairs_t::const_iterator + l_itr = l_XbusConnections.begin(); + l_itr != l_XbusConnections.end(); ++l_itr) { - const TARGETING::Target* l_cpuTarget = *l_cpuIter; - - // Get the XBUS under this proc - TARGETING::TargetHandleList l_xbusList; - getChildChiplets( l_xbusList, l_cpuTarget, TYPE_XBUS ); - - // For each XBUS unit in this proc - for (TargetHandleList::const_iterator - l_xbus_iter = l_xbusList.begin(); - l_xbus_iter != l_xbusList.end(); - ++l_xbus_iter) - { - // make a local copy of the target for ease of use - TARGETING::Target* l_xbusTarget = *l_xbus_iter; - EDI_EI_INITIALIZATION::TargetPairs_t::iterator l_itr = - l_XbusConnections.find(l_xbusTarget); - if ( l_itr == l_XbusConnections.end() ) - { - continue; - } - - const TARGETING::Target *l_pParent = - getParentChip( - (const_cast<TARGETING::Target*>(l_itr->second))); + const TARGETING::Target* l_thisXbusTarget = l_itr->first; + const TARGETING::Target* l_connectedXbusTarget = l_itr->second; - // Targets to pass in HW procedure - std::vector<fapi::Target> targets; + // Call HW procedure + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running proc_xbus_scominit HWP on " + "This XBUS target %.8X - Connected XBUS target %.8X", + TARGETING::get_huid(l_thisXbusTarget), + TARGETING::get_huid(l_connectedXbusTarget)); - const fapi::Target l_fapi_xbus_target( + const fapi::Target l_thisXbusFapiTarget( TARGET_TYPE_XBUS_ENDPOINT, - (const_cast<TARGETING::Target*>(l_xbusTarget))); - targets.push_back(l_fapi_xbus_target); + (const_cast<TARGETING::Target*>(l_thisXbusTarget))); - const fapi::Target l_fapi_this_cpu_target( - TARGET_TYPE_PROC_CHIP, - (const_cast<TARGETING::Target*>( - l_cpuTarget))); - targets.push_back(l_fapi_this_cpu_target); + const fapi::Target l_connectedXbusFapiTarget( + TARGET_TYPE_XBUS_ENDPOINT, + (const_cast<TARGETING::Target*>(l_connectedXbusTarget))); - const fapi::Target l_fapi_other_cpu_target( - TARGET_TYPE_PROC_CHIP, - (const_cast<TARGETING::Target*>( - l_pParent))); - targets.push_back(l_fapi_other_cpu_target); + FAPI_INVOKE_HWP(l_err, proc_xbus_scominit, + l_thisXbusFapiTarget, l_connectedXbusFapiTarget); + if (l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X : proc_xbus_scominit HWP returns error. " + "This XBUS target %.8X - Connected XBUS target %.8X", + l_err->reasonCode(), + TARGETING::get_huid(l_thisXbusTarget), + TARGETING::get_huid(l_connectedXbusTarget)); - // Call HW procedure - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Running proc_xbus_scominit HWP on " - "xbus HUID %.8X this cpu HUID %.8X other cpu HUID %.8X", - TARGETING::get_huid(l_xbusTarget), - TARGETING::get_huid(l_cpuTarget), - TARGETING::get_huid(l_pParent)); + // capture the target data in the elog + ErrlUserDetailsTarget(l_thisXbusTarget).addToLog( l_err ); + ErrlUserDetailsTarget(l_connectedXbusTarget).addToLog( l_err ); - FAPI_INVOKE_HWP(l_err, proc_xbus_scominit, - l_fapi_xbus_target, - l_fapi_this_cpu_target, - l_fapi_other_cpu_target); - if (l_err) - { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X : proc_xbus_scominit HWP returns error. " - "xbus HUID %.8X this cpu HUID %.8X other cpu HUID %.8X", - l_err->reasonCode(), - TARGETING::get_huid(l_xbusTarget), - TARGETING::get_huid(l_cpuTarget), - TARGETING::get_huid(l_pParent)); + /*@ + * @errortype + * @reasoncode ISTEP_PROC_XBUS_SCOMINIT_FAILED + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid ISTEP_PROC_XBUS_SCOMINIT + * @userdata1 bytes 0-1: plid identifying first error + * bytes 2-3: reason code of first error + * @userdata2 bytes 0-1: total number of elogs included + * bytes 2-3: N/A + * @devdesc call to proc_xbus_scominit has failed + */ + l_StepError.addErrorDetails(ISTEP_PROC_XBUS_SCOMINIT_FAILED, + ISTEP_PROC_XBUS_SCOMINIT, + l_err ); + // We want to continue to the next target instead of exiting, + // Commit the error log and move on + // Note: Error log should already be deleted and set to NULL + // after committing + errlCommit(l_err, HWPF_COMP_ID); + } - // capture the target data in the elog - ErrlUserDetailsTarget(l_pParent).addToLog( l_err ); - ErrlUserDetailsTarget(l_cpuTarget).addToLog( l_err ); - ErrlUserDetailsTarget(l_xbusTarget).addToLog( l_err ); + } - /*@ - * @errortype - * @reasoncode ISTEP_PROC_XBUS_SCOMINIT_FAILED - * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE - * @moduleid ISTEP_PROC_XBUS_SCOMINIT - * @userdata1 bytes 0-1: plid identifying first error - * bytes 2-3: reason code of first error - * @userdata2 bytes 0-1: total number of elogs included - * bytes 2-3: N/A - * @devdesc call to proc_xbus_scominit has failed - */ - l_StepError.addErrorDetails(ISTEP_PROC_XBUS_SCOMINIT_FAILED, - ISTEP_PROC_XBUS_SCOMINIT, - l_err ); - // We want to continue to the next target instead of exiting, - // Commit the error log and move on - // Note: Error log should already be deleted and set to NULL - // after committing - errlCommit(l_err, HWPF_COMP_ID); - } - } // End xbus loop - } // End cpu loop } while (0); return l_StepError.getErrorHandle(); diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit.C b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit.C index 521a9b42c..75f473da0 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit.C +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_xbus_scominit.C,v 1.2 2013/01/20 19:24:27 jmcgill Exp $ +// $Id: proc_xbus_scominit.C,v 1.4 2013/02/06 22:21:31 thomsen Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_xbus_scominit.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -36,6 +36,15 @@ // *! ADDITIONAL COMMENTS : // *! //------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +// Version Date Owner Description +//------------------------------------------------------------------------------ +// 1.3 01/31/13 thomsen Added separate calls to base & customized scominit files. Removed separate calls to SIM vs. HW scominit files +// 1.2 01/09/13 thomsen Added separate calls to SIM vs. HW scominit files +// Added parent chip and connected targets to vector of passed targets. This is to match scominit file updates. +// Added commented-out call to OVERRIDE initfile for system/bus/lane specific inits +// 1.1 8/11/12 jmcgill Initial release +//------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Includes @@ -50,13 +59,13 @@ extern "C" { //------------------------------------------------------------------------------ // HWP entry point, comments in header -fapi::ReturnCode proc_xbus_scominit( - const fapi::Target & i_xbus_target, - const fapi::Target & i_this_pu_target, - const fapi::Target & i_other_pu_target) +fapi::ReturnCode proc_xbus_scominit( const fapi::Target & i_xbus_target, + const fapi::Target & i_connected_xbus_target) { fapi::ReturnCode rc; std::vector<fapi::Target> targets; + fapi::Target i_this_pu_target; + fapi::Target i_connected_pu_target; uint8_t xbus_enable_attr; // mark HWP entry @@ -64,6 +73,17 @@ fapi::ReturnCode proc_xbus_scominit( do { + + // Get parent chip targets + rc = fapiGetParentChip(i_xbus_target, i_this_pu_target); if(rc) return rc; + rc = fapiGetParentChip(i_connected_xbus_target, i_connected_pu_target); if(rc) return rc; + + // populate targets vector + targets.push_back(i_xbus_target); + targets.push_back(i_this_pu_target); + targets.push_back(i_connected_xbus_target); + targets.push_back(i_connected_pu_target); + // query XBUS partial good attribute rc = FAPI_ATTR_GET(ATTR_PROC_X_ENABLE, &i_this_pu_target, @@ -81,25 +101,38 @@ fapi::ReturnCode proc_xbus_scominit( break; } - // obtain target type to determine which initfile(s) to execute - targets.push_back(i_xbus_target); - targets.push_back(i_this_pu_target); - targets.push_back(i_other_pu_target); - - // processor XBUS chiplet target - if ((i_xbus_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT) && - (i_this_pu_target.getType() == fapi::TARGET_TYPE_PROC_CHIP) && - (i_other_pu_target.getType() == fapi::TARGET_TYPE_PROC_CHIP)) + // processor target, processor MCS chiplet target + // test target types to confirm correct before calling initfile(s) to execute + if ((i_this_pu_target.getType() == fapi::TARGET_TYPE_PROC_CHIP) && + (i_xbus_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT) && + (i_connected_pu_target.getType() == fapi::TARGET_TYPE_PROC_CHIP) && + (i_connected_xbus_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT)) { - FAPI_INF("proc_xbus_scominit: Executing %s on %s", - XBUS_IF, i_xbus_target.toEcmdString()); - FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, targets, XBUS_IF); + // Call BASE DMI SCOMINIT + FAPI_INF("proc_xbus_scominit: fapiHwpExecInitfile executing %s on %s, %s, %s, %s", + XBUS_BASE_IF, i_this_pu_target.toEcmdString(), i_xbus_target.toEcmdString(), + i_connected_pu_target.toEcmdString(), i_connected_xbus_target.toEcmdString()); + FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, targets, XBUS_BASE_IF); if (!rc.ok()) { - FAPI_ERR("proc_xbus_scominit: Error from fapiHwpExecInitfile executing %s on %s", - XBUS_IF, i_xbus_target.toEcmdString()); + FAPI_ERR("proc_xbus_scominit: Error with fapiHwpExecInitfile executing %s on %s, %s, %s, %s", + XBUS_BASE_IF, i_this_pu_target.toEcmdString(), i_xbus_target.toEcmdString(), + i_connected_pu_target.toEcmdString(), i_connected_xbus_target.toEcmdString()); break; } + // Call CUSTOMIZED DMI SCOMINIT (system specific) + FAPI_INF("proc_xbus_scominit: fapiHwpExecInitfile executing %s on %s, %s, %s, %s", + XBUS_CUSTOM_IF, i_this_pu_target.toEcmdString(), i_xbus_target.toEcmdString(), + i_connected_pu_target.toEcmdString(), i_connected_xbus_target.toEcmdString()); + FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, targets, XBUS_CUSTOM_IF); + if (!rc.ok()) + { + FAPI_ERR("proc_xbus_scominit: Error with fapiHwpExecInitfile executing %s on %s, %s, %s, %s", + XBUS_CUSTOM_IF, i_this_pu_target.toEcmdString(), i_xbus_target.toEcmdString(), + i_connected_pu_target.toEcmdString(), i_connected_xbus_target.toEcmdString()); + break; + } + } // unsupported target type else @@ -110,6 +143,7 @@ fapi::ReturnCode proc_xbus_scominit( } } while (0); + // mark HWP exit FAPI_INF("proc_xbus_scominit: End"); return rc; diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit.H b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit.H index 0606a76e1..85b792639 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit.H +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_xbus_scominit.H,v 1.1 2012/08/11 18:24:30 jmcgill Exp $ +// $Id: proc_xbus_scominit.H,v 1.2 2013/02/04 23:08:13 thomsen Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_xbus_scominit.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -36,6 +36,15 @@ // *! ADDITIONAL COMMENTS : // *! //------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +// Version Date Owner Description +//------------------------------------------------------------------------------ +// 1.2 02/04/13 thomsen Added separate calls to base & customized scominit files. Removed separate calls to SIM vs. HW scominit files +// 01/09/13 thomsen Added SIM and HW scominit filename strings +// Added *_OVERRIDE_IF to allow DMI initfile overrides for specific bus instances +// Changed passed targets in order to match scominit file updates. +// 1.1 8/11/12 jmcgill Initial release +//------------------------------------------------------------------------------ #ifndef PROC_XBUS_SCOMINIT_H_ #define PROC_XBUS_SCOMINIT_H_ @@ -48,7 +57,8 @@ //------------------------------------------------------------------------------ // Constant definitions //------------------------------------------------------------------------------ -const char * const XBUS_IF = "p8.xbus.scom.if"; +const char * const XBUS_BASE_IF = "p8.xbus.scom.if"; +const char * const XBUS_CUSTOM_IF = "p8.xbus.custom.scom.if"; //------------------------------------------------------------------------------ // Structure definitions @@ -56,9 +66,8 @@ const char * const XBUS_IF = "p8.xbus.scom.if"; // function pointer typedef definition for HWP call support typedef fapi::ReturnCode -(*proc_xbus_scominit_FP_t)(const fapi::Target & i_target, - const fapi::Target & i_this_pu_target, - const fapi::Target & i_other_pu_target); +(*proc_xbus_scominit_FP_t)(const fapi::Target & i_xbus_target, + const fapi::Target & i_connected_xbus_target); extern "C" { @@ -71,12 +80,10 @@ extern "C" { * * Should be called for all valid/connected XBUS endpoints * - * @param[in] i_xbus_target Reference to XBUS target - * i_this_pu_target Reference to enclosing chip target - * i_other_pu_target Reference to connected chip target + * @param[in] i_xbus_target Reference to XBUS target + * i_connected_abus_target Reference to connected ABUS target * If i_xbus_target is TARGET_TYPE_XBUS_ENDPOINT, - * i_this_pu_target is TARGET_TYPE_PROC_CHIP, - * i_other_pu_target is TARGET_TYPE_PROC_CHIP, + * i_connected_abus_target is TARGET_TYPE_ABUS_ENDPOINT, * calls: * - p8.xbus.scom.initfile * @@ -84,8 +91,7 @@ extern "C" { */ fapi::ReturnCode proc_xbus_scominit( const fapi::Target & i_xbus_target, - const fapi::Target & i_this_pu_target, - const fapi::Target & i_other_pu_target); + const fapi::Target & i_connected_xbus_target); } // extern "C" diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C index ea0df2f1e..110e29a3d 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_pcie_scominit.C,v 1.4 2013/02/04 23:58:47 jmcgill Exp $ +// $Id: proc_pcie_scominit.C,v 1.5 2013/02/19 23:26:52 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_scominit.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -71,6 +71,8 @@ fapi::ReturnCode proc_pcie_scominit_iop_init( uint8_t iop_swap[PROC_PCIE_SCOMINIT_NUM_IOP]; uint8_t phb_active_mask; bool phb_active[PROC_PCIE_SCOMINIT_NUM_PHB]; + uint8_t refclock_active_mask; + bool refclock_active[PROC_PCIE_SCOMINIT_NUM_PHB]; // data buffers for GP4/GP0 accesses ecmdDataBufferBase gp4_data(64); @@ -164,7 +166,7 @@ fapi::ReturnCode proc_pcie_scominit_iop_init( break; } - // retrieve active PHB attribute and check value received + // retrieve active PHB/refclock enable attributes and check value received FAPI_DBG("proc_pcie_scominit_iop_init: Querying PHB active attribute"); rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_PHB_ACTIVE, &i_target, @@ -174,12 +176,24 @@ fapi::ReturnCode proc_pcie_scominit_iop_init( FAPI_ERR("proc_pcie_scominit_iop_init: Error from FAPI_ATTR_GET (ATTR_PROC_PCIE_PHB_ACTIVE)"); break; } + + FAPI_DBG("proc_pcie_scominit_iop_init: Querying refclock enable attribute"); + rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_REFCLOCK_ENABLE, + &i_target, + refclock_active_mask); + if (!rc.ok()) + { + FAPI_ERR("proc_pcie_scominit_iop_init: Error from FAPI_ATTR_GET (ATTR_PROC_PCIE_REFCLOCK_ENABLE)"); + break; + } + for (size_t i = 0; (i < PROC_PCIE_SCOMINIT_NUM_PHB); i++) { phb_active[i] = ((phb_active_mask >> (7-i)) & 0x1)?(true):(false); + refclock_active[i] = ((refclock_active_mask >> (7-i)) & 0x1)?(true):(false); } - // set PCIe GP0 mask for PHB iovalid + // set PCIe GP0 mask for PHB iovalid/refclock enable for (size_t i = 0; (i < PROC_PCIE_SCOMINIT_NUM_PHB) && !rc_ecmd; i++) { rc_ecmd |= gp0_data.writeBit( @@ -187,7 +201,7 @@ fapi::ReturnCode proc_pcie_scominit_iop_init( phb_active[i]); rc_ecmd |= gp0_data.writeBit( PCIE_GP0_PHB_REFCLOCK_DRIVE_EN_BIT[i], - phb_active[i]); + refclock_active[i]); } if (rc_ecmd) { @@ -198,7 +212,7 @@ fapi::ReturnCode proc_pcie_scominit_iop_init( } // write PCIe GP0 data via OR mask register - FAPI_DBG("proc_pcie_scominit_iop_init: Writing PCIe GP0 to set PHB iovalids"); + FAPI_DBG("proc_pcie_scominit_iop_init: Writing PCIe GP0 to set PHB iovalids and refclock drive enables"); rc = fapiPutScom(i_target, PCIE_GP0_OR_0x09000005, gp0_data); if (!rc.ok()) { diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml index 448658c9d..380675db3 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> <!-- --> <!-- p1 --> <!-- --> @@ -69,6 +69,21 @@ </attribute> <!-- ********************************************************************* --> <attribute> + <id>ATTR_PROC_PCIE_REFCLOCK_ENABLE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>PCIE refclock enable valid mask + creator: platform + consumer: proc_pcie_scominit + firmware notes: + Bit mask defining state of refclock drive enables + bit0=PCI0, bit1=PCI1, bit2=PCI2 + </description> + <valueType>uint8</valueType> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> <id>ATTR_PROC_PCIE_IOP_G3_PLL_CONTROL0</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> @@ -284,4 +299,4 @@ <platInit/> </attribute> <!-- ********************************************************************* --> -</attributes>
\ No newline at end of file +</attributes> diff --git a/src/usr/hwpf/hwp/utility_procedures/mss_unmask_errors.C b/src/usr/hwpf/hwp/utility_procedures/mss_unmask_errors.C index f91e37c77..2d0dfd2ff 100644 --- a/src/usr/hwpf/hwp/utility_procedures/mss_unmask_errors.C +++ b/src/usr/hwpf/hwp/utility_procedures/mss_unmask_errors.C @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_unmask_errors.C $ */ +/* $Source: src/usr/hwpf/hwp/utility_procedures/mss_unmask_errors.C $ */ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_unmask_errors.C,v 1.1 2012/09/05 21:04:52 gollub Exp $ +// $Id: mss_unmask_errors.C,v 1.2 2013/01/31 22:35:01 gollub Exp $ //------------------------------------------------------------------------------ // Don't forget to create CVS comments when you check in your changes! //------------------------------------------------------------------------------ @@ -29,7 +29,10 @@ // Version:| Date: | Author: | Comment: //---------|----------|---------|----------------------------------------------- // 1.1 | 09/05/12 | gollub | Created - +// 1.2 | 01/31/13 | gollub | Keeping maint UE/MPE, and MBSPA threshold +// | | | errors masked until mss_unmask_fetch_errors, +// | | | so they will be masked during memdiags, and +// | | | unmasked before scrub is started. //------------------------------------------------------------------------------ // Includes @@ -1697,49 +1700,58 @@ fapi::ReturnCode mss_unmask_maint_errors(const fapi::Target & i_target, // to be valid errors for PRD to log. - // 0 Command_Complete masked (DD1 broken) - l_ecmd_rc |= l_mbaspa_mask.setBit(0); + // 0 Command_Complete unmasked + // NOTE: This bit broken in DD1 + // It can be made to come on when cmd completes clean, or make to come + // on when cmd stops on error, but can't be set to do both. + // I am unmasking it since it should work for init commands which + // will always complete clean. This should at least allow FW to + // get cmd complete attention for sf init cmd. + l_ecmd_rc |= l_mbaspa_mask.clearBit(0); - // 1 Hard_CE_ETE_Attn unmask - // NOTE: FW memdiags may want to mask this if they want to wait till + // 1 Hard_CE_ETE_Attn mask (until after memdiags) + // NOTE: FW memdiags needs this masked because they want to wait till // cmd gets to end of rank before getting any attention. // NOTE: Hards counted during super fast read, but can't be called // true hard CEs since super fast read doesn't write back and read again. - l_ecmd_rc |= l_mbaspa_mask.clearBit(1); + l_ecmd_rc |= l_mbaspa_mask.setBit(1); - // 2 Soft_CE_ETE_Attn unmask - // NOTE: FW memdiags may want to mask this if they want to wait till + // 2 Soft_CE_ETE_Attn mask (until after memdiags) + // NOTE: FW memdiags needs this masked because they want to wait till // cmd gets to end of rank before getting any attention. // NOTE: Softs not counted during super fast read. - l_ecmd_rc |= l_mbaspa_mask.clearBit(2); + l_ecmd_rc |= l_mbaspa_mask.setBit(2); - // 3 Intermittent_ETE_Attn unmask - // NOTE: FW memdiags may want to mask this if they want to wait till + // 3 Intermittent_ETE_Attn mask (until after memdiags) + // NOTE: FW memdiags needs this masked because they want to wait till // cmd gets to end of rank before getting any attention. // NOTE: Intermittents not counted during super fast read. - l_ecmd_rc |= l_mbaspa_mask.clearBit(3); + l_ecmd_rc |= l_mbaspa_mask.setBit(3); - // 4 RCE_ETE_Attn unmask - // NOTE: FW memdiags may want to mask this if they want to wait till + // 4 RCE_ETE_Attn mask (until after memdiags) + // NOTE: FW memdiags needs this masked because they want to wait till // cmd gets to end of rank before getting any attention. - l_ecmd_rc |= l_mbaspa_mask.clearBit(4); + // NOTE: RCEs not counted during super fast read. + l_ecmd_rc |= l_mbaspa_mask.setBit(4); - // 5 Emergency_Throttle_Attn masked + // 5 Emergency_Throttle_Attn masked (forever) l_ecmd_rc |= l_mbaspa_mask.setBit(5); - // 6 Firmware_Attn0 masked + // 6 Firmware_Attn0 masked (forever) l_ecmd_rc |= l_mbaspa_mask.setBit(6); - // 7 Firmware_Attn1 masked + // 7 Firmware_Attn1 masked (forever) l_ecmd_rc |= l_mbaspa_mask.setBit(7); - // 8 wat_debug_attn unmask (DD1 workaround) + // 8 wat_debug_attn unmasked + // NOTE: DD1 workaround for broken bit 0. This bit will come on whenever + // cmd stops, either stop clean or stop on error. l_ecmd_rc |= l_mbaspa_mask.clearBit(8); - // 9 Spare_Attn1 masked + // 9 Spare_Attn1 masked (forever) l_ecmd_rc |= l_mbaspa_mask.setBit(9); - // 10 MCBIST_Done masked + // 10 MCBIST_Done masked (forever) l_ecmd_rc |= l_mbaspa_mask.setBit(10); // 11:63 RESERVED not implemented, so won't touch these @@ -1825,7 +1837,7 @@ fapi::ReturnCode mss_unmask_maint_errors(const fapi::Target & i_target, l_ecmd_rc |= l_mbeccfir_mask_or.flushTo0(); l_ecmd_rc |= l_mbeccfir_mask_and.flushTo1(); - // 0:7 Memory MPE Rank 0:7 recoverable mask + // 0:7 Memory MPE Rank 0:7 recoverable mask (until mainline traffic) l_ecmd_rc |= l_mbeccfir_action0.clearBit(0,8); l_ecmd_rc |= l_mbeccfir_action1.setBit(0,8); l_ecmd_rc |= l_mbeccfir_mask_or.setBit(0,8); @@ -1835,12 +1847,12 @@ fapi::ReturnCode mss_unmask_maint_errors(const fapi::Target & i_target, l_ecmd_rc |= l_mbeccfir_action1.setBit(8,8); l_ecmd_rc |= l_mbeccfir_mask_or.setBit(8,8); - // 16 Memory NCE recoverable mask + // 16 Memory NCE recoverable mask (until mainline traffic) l_ecmd_rc |= l_mbeccfir_action0.clearBit(16); l_ecmd_rc |= l_mbeccfir_action1.setBit(16); l_ecmd_rc |= l_mbeccfir_mask_or.setBit(16); - // 17 Memory RCE recoverable mask + // 17 Memory RCE recoverable mask (until mainline traffic) l_ecmd_rc |= l_mbeccfir_action0.clearBit(17); l_ecmd_rc |= l_mbeccfir_action1.setBit(17); l_ecmd_rc |= l_mbeccfir_mask_or.setBit(17); @@ -1850,39 +1862,43 @@ fapi::ReturnCode mss_unmask_maint_errors(const fapi::Target & i_target, l_ecmd_rc |= l_mbeccfir_action1.setBit(18); l_ecmd_rc |= l_mbeccfir_mask_or.setBit(18); - // 19 Memory UE recoverable mask + // 19 Memory UE recoverable mask (until mainline traffic) l_ecmd_rc |= l_mbeccfir_action0.clearBit(19); l_ecmd_rc |= l_mbeccfir_action1.setBit(19); l_ecmd_rc |= l_mbeccfir_mask_or.setBit(19); - // 20:27 Maint MPE Rank 0:7 recoverable unmask - // NOTE: FW memdiags may want to mask this if they want to wait till + // 20:27 Maint MPE Rank 0:7 recoverable mask (until after memdiags) + // NOTE: FW memdiags needs this masked because they want to wait till // cmd gets to end of rank before getting any attention. l_ecmd_rc |= l_mbeccfir_action0.clearBit(20,8); l_ecmd_rc |= l_mbeccfir_action1.setBit(20,8); - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(20,8); + l_ecmd_rc |= l_mbeccfir_mask_or.setBit(20,8); // 28:35 Reserved recoverable mask (forever) l_ecmd_rc |= l_mbeccfir_action0.clearBit(28,8); l_ecmd_rc |= l_mbeccfir_action1.setBit(28,8); l_ecmd_rc |= l_mbeccfir_mask_or.setBit(28,8); - // 36 Maintenance NCE recoverable mask (tbd) + // 36 Maintenance NCE recoverable mask (forever) + // NOTE: PRD planning to use maint CE thresholds instead. l_ecmd_rc |= l_mbeccfir_action0.clearBit(36); l_ecmd_rc |= l_mbeccfir_action1.setBit(36); l_ecmd_rc |= l_mbeccfir_mask_or.setBit(36); - // 37 Maintenance SCE recoverable mask (tbd) + // 37 Maintenance SCE recoverable mask (forever) + // NOTE: Don't care if symbol still bad after it's symbol marked. l_ecmd_rc |= l_mbeccfir_action0.clearBit(37); l_ecmd_rc |= l_mbeccfir_action1.setBit(37); l_ecmd_rc |= l_mbeccfir_mask_or.setBit(37); - // 38 Maintenance MCE recoverable mask (tbd) + // 38 Maintenance MCE recoverable mask (forever) + // NOTE: PRD plans to check manually as part of verify chip mark procedure. l_ecmd_rc |= l_mbeccfir_action0.clearBit(38); l_ecmd_rc |= l_mbeccfir_action1.setBit(38); l_ecmd_rc |= l_mbeccfir_mask_or.setBit(38); - // 39 Maintenance RCE recoverable mask (tbd) + // 39 Maintenance RCE recoverable mask (forever) + // NOTE: PRD planning to use maint RCE thresholds instead. l_ecmd_rc |= l_mbeccfir_action0.clearBit(39); l_ecmd_rc |= l_mbeccfir_action1.setBit(39); l_ecmd_rc |= l_mbeccfir_mask_or.setBit(39); @@ -1892,19 +1908,19 @@ fapi::ReturnCode mss_unmask_maint_errors(const fapi::Target & i_target, l_ecmd_rc |= l_mbeccfir_action1.setBit(40); l_ecmd_rc |= l_mbeccfir_mask_or.setBit(40); - // 41 Maintenance UE recoverable unmask (tbd) - // NOTE: FW memdiags may want to mask this if they want to wait till + // 41 Maintenance UE recoverable mask (until after memdiags) + // NOTE: FW memdiags needs this masked because they want to wait till // cmd gets to end of rank before getting any attention. l_ecmd_rc |= l_mbeccfir_action0.clearBit(41); l_ecmd_rc |= l_mbeccfir_action1.setBit(41); - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(41); + l_ecmd_rc |= l_mbeccfir_mask_or.setBit(41); // 42 MPE during maintenance mark mode recoverable mask (forever) l_ecmd_rc |= l_mbeccfir_action0.clearBit(42); l_ecmd_rc |= l_mbeccfir_action1.setBit(42); l_ecmd_rc |= l_mbeccfir_mask_or.setBit(42); - // 43 Prefetch Memory UE recoverable mask + // 43 Prefetch Memory UE recoverable mask (until mainline traffic) l_ecmd_rc |= l_mbeccfir_action0.clearBit(43); l_ecmd_rc |= l_mbeccfir_action1.setBit(43); l_ecmd_rc |= l_mbeccfir_mask_or.setBit(43); @@ -2449,11 +2465,6 @@ fapi::ReturnCode mss_unmask_fetch_errors(const fapi::Target & i_target, //************************************************ - //************************* - //************************* - // MBECCFIR - //************************* - //************************* std::vector<fapi::Target> l_mbaChiplets; uint8_t l_mbaPosition; // 0 = mba01, 1 = mba23 @@ -2470,6 +2481,7 @@ fapi::ReturnCode mss_unmask_fetch_errors(const fapi::Target & i_target, ecmdDataBufferBase l_mbeccfir_mask(64); ecmdDataBufferBase l_mbeccfir_mask_and(64); + ecmdDataBufferBase l_mbaspa_mask(64); // Get associated functional MBAs on this centaur l_rc = fapiGetChildChiplets(i_target, @@ -2497,6 +2509,87 @@ fapi::ReturnCode mss_unmask_fetch_errors(const fapi::Target & i_target, return l_rc; } + + //************************* + //************************* + // MBASPA + //************************* + //************************* + + // Read mask + l_rc = fapiGetScom_w_retry(l_mbaChiplets[i], + MBA01_MBSPAMSKQ_0x03010614, + l_mbaspa_mask); + if(l_rc) + { + // Log passed in error before returning with new error + if (i_bad_rc) fapiLogError(i_bad_rc); + return l_rc; + } + + // TODO: Here is where I could clear bits that were bogus, before I unmask + // them. But typically we are expecting the bit set at this point + // to be valid errors for PRD to log. + + + // 1 Hard_CE_ETE_Attn unmask + // NOTE: Unmasking, but PRD responsible for setting and enabling the threshold. + l_ecmd_rc |= l_mbaspa_mask.clearBit(1); + + // 2 Soft_CE_ETE_Attn unmask + // NOTE: Unmasking, but PRD responsible for setting and enabling the threshold. + l_ecmd_rc |= l_mbaspa_mask.clearBit(2); + + // 3 Intermittent_ETE_Attn unmask + // NOTE: Unmasking, but PRD responsible for setting and enabling the threshold. + l_ecmd_rc |= l_mbaspa_mask.clearBit(3); + + // 4 RCE_ETE_Attn unmask + // NOTE: Unmasking, but PRD responsible for setting and enabling the threshold. + l_ecmd_rc |= l_mbaspa_mask.clearBit(4); + + + if(l_ecmd_rc) + { + // Log passed in error before returning with new error + if (i_bad_rc) fapiLogError(i_bad_rc); + + l_rc.setEcmdError(l_ecmd_rc); + return l_rc; + } + + // Write mask + l_rc = fapiPutScom_w_retry(l_mbaChiplets[i], + MBA01_MBSPAMSKQ_0x03010614, + l_mbaspa_mask); + if(l_rc) + { + // Log passed in error before returning with new error + if (i_bad_rc) fapiLogError(i_bad_rc); + return l_rc; + } + + //************************************************ + // DEBUG: read them all back to verify + l_rc = fapiGetScom_w_retry(l_mbaChiplets[i], + MBA01_MBSPAMSKQ_0x03010614, + l_mbaspa_mask); + if(l_rc) + { + // Log passed in error before returning with new error + if (i_bad_rc) fapiLogError(i_bad_rc); + return l_rc; + } + //************************************************ + + + + //************************* + //************************* + // MBECCFIR + //************************* + //************************* + // Read mask l_rc = fapiGetScom_w_retry(i_target, l_mbeccfir_mask_address[l_mbaPosition], @@ -2536,6 +2629,12 @@ fapi::ReturnCode mss_unmask_fetch_errors(const fapi::Target & i_target, // 19 Memory UE recoverable unmask l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(19); + // 20:27 Maint MPE Rank 0:7 recoverable unmask + l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(20,8); + + // 41 Maintenance UE recoverable unmask + l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(41); + // 43 Prefetch Memory UE recoverable unmask l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(43); |
