diff options
Diffstat (limited to 'src/usr/hwpf/hwp/memory_attributes.xml')
| -rw-r--r-- | src/usr/hwpf/hwp/memory_attributes.xml | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/src/usr/hwpf/hwp/memory_attributes.xml b/src/usr/hwpf/hwp/memory_attributes.xml index af1fb78d3..a65b076d1 100644 --- a/src/usr/hwpf/hwp/memory_attributes.xml +++ b/src/usr/hwpf/hwp/memory_attributes.xml @@ -3642,6 +3642,76 @@ will originates from VPD for custom DIMMs in the MW keyword byte 5 (MSB is on th --> <attribute> + <id>ATTR_VPD_CKE_PRI_MAP</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>This value comes from the VPD keyword MT bytes 54 and 55 MT(54:55) for the Logical DIMM associated with port A. Bytes 118:119 for port B, 182:183 for port C and 246:247 for port D. In the end, the AB and CD portions form a 32 bit word for each mba to write into the corresponding ddrphy register</description> + <valueType>uint32</valueType> + <platInit/> + <odmVisable/> + <array>2</array> +</attribute> + +<attribute> + <id>ATTR_VPD_CKE_PWR_MAP</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>This value comes from the VPD keyword MT bytes 56 to 59 MT(56:59) for the Logical DIMM associated with port A. Bytes 120:123 for port B, 184:187 for port C and 248:251 for port D</description> + <valueType>uint32</valueType> + <platInit/> + <odmVisable/> + <array>2</array> +</attribute> + +<attribute> + <id>ATTR_VPD_GPO</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>This value comes from the VPD keyword MT bytes 61 MT(61) for the Logical DIMM associated with port A. Bytes 125 for port B, 189 for port C and 253 for port D</description> + <valueType>uint8</valueType> + <platInit/> + <odmVisable/> + <array>2</array> +</attribute> + +<attribute> + <id>ATTR_VPD_RLO</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>This value comes from the VPD keyword MT byte 60 bits 4:7 for the Logical DIMM associated with port A. Byte 124 bits 4:7 for port B, 188 bits 4:7 for port C and 252 bits 4:7 for port D</description> + <valueType>uint8</valueType> + <platInit/> + <odmVisable/> + <array>2</array> +</attribute> + +<attribute> + <id>ATTR_VPD_WLO</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>This value comes from the VPD keyword MT byte 60 bits 0:3 for the Logical DIMM associated with port A. Byte 124 bits 0:3 for port B, 188 bits 0:3 for port C and 252 bits 0:3 for port D</description> + <valueType>uint8</valueType> + <platInit/> + <odmVisable/> + <array>2</array> +</attribute> + +<attribute> + <id>ATTR_VPD_TSYS_ADR</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>This value comes from the VPD MR keyword byte 49 for ports A and B and byte 177 for port C and D. This means that all ADR blocks use this value on an mba level</description> + <valueType>uint8</valueType> + <platInit/> + <odmVisable/> + <array>2</array> +</attribute> + +<attribute> + <id>ATTR_VPD_TSYS_DP18</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>This value comes from the VPD MR keyword byte 113 for ports A and B and byte 241 for port C and D. This means all DP18 blocks use this value on a mba level</description> + <valueType>uint8</valueType> + <platInit/> + <odmVisable/> + <array>2</array> +</attribute> + +<attribute> <id>ATTR_LAB_USE_JTAG_MODE</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description>This attribute controls how the procedures operate in JTAG mode under an environment called cronus flex. For normal operation, this attribute should be set to FALSE. Platforms should initialize this attribute to FALSE.</description> |
