diff options
Diffstat (limited to 'src/usr/hwpf/hwp/memory_attributes.xml')
| -rw-r--r-- | src/usr/hwpf/hwp/memory_attributes.xml | 157 |
1 files changed, 151 insertions, 6 deletions
diff --git a/src/usr/hwpf/hwp/memory_attributes.xml b/src/usr/hwpf/hwp/memory_attributes.xml index 93b62644c..a4c172c6e 100644 --- a/src/usr/hwpf/hwp/memory_attributes.xml +++ b/src/usr/hwpf/hwp/memory_attributes.xml @@ -21,7 +21,7 @@ <!-- --> <!-- IBM_PROLOG_END_TAG --> <attributes> -<!-- $Id: memory_attributes.xml,v 1.71 2013/05/30 19:11:44 bellows Exp $ --> +<!-- $Id: memory_attributes.xml,v 1.76 2013/07/17 13:47:15 bellows Exp $ --> <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB --> <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP --> <!-- *********************************************************************** --> @@ -1930,7 +1930,8 @@ firmware notes: none</description> <attribute> <id>ATTR_MSS_CACHE_ENABLE</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> - <description>Reflects the functionality of the L4 Cache. Determines if the L4 is enabled or not. See chapter 6 of the Centaur Workbook. On means the full cache is enabled. HALF_A (EVEN) means only A is enabled and HALF_B (ODD) means only B is enabled. For DD1X, the values of UNK_OFF, UNK_ON, UNK_HALF_A and UNK_HALFB were added because early parts did not have the fuses blown correctly, so the cache repairs may not have worked. This value is set by the platform which can get the chips value by running the mss_cen_get_ecid function.</description> + <description>Reflects the functionality of the L4 Cache. Determines if the L4 is enabled or not. See chapter 6 of the Centaur Workbook. On means the full cache is enabled. HALF_A (EVEN) means only A is enabled and HALF_B (ODD) means only B is enabled. For DD1X, the values of UNK_OFF, UNK_ON, UNK_HALF_A and UNK_HALFB were added because early parts did not have the fuses blown correctly, so the cache repairs may not have worked. This value is set by the platform which can get the chips value by running the mss_cen_get_ecid function. +Note: Cronus and Firmware plus our initfiles do not really support any of the UNK values. It is the responsibility of the platform to map the UNK values to the appropriate value of OFF/ON/HALF_A/HALF_B</description> <valueType>uint8</valueType> <enum>OFF = 0, ON = 1, HALF_A = 3, HALF_B = 5, UNK_OFF = 8, UNK_ON = 9, UNK_HALF_A = 0xB, UNK_HALF_B = 0xD</enum> <platInit/> @@ -3218,7 +3219,6 @@ Comes from the VPD MW Keyword</description> <valueType>uint32</valueType> <platInit/> <odmVisable/> - <odmChangeable/> <persistRuntime/> </attribute> @@ -3229,7 +3229,6 @@ Comes from the VPD MW Keyword</description> <valueType>uint32</valueType> <platInit/> <odmVisable/> - <odmChangeable/> <persistRuntime/> </attribute> @@ -3240,7 +3239,6 @@ Comes from the VPD MW Keyword</description> <valueType>uint32</valueType> <platInit/> <odmVisable/> - <odmChangeable/> <persistRuntime/> </attribute> @@ -3251,7 +3249,6 @@ Comes from the VPD MW Keyword</description> <valueType>uint32</valueType> <platInit/> <odmVisable/> - <odmChangeable/> <persistRuntime/> </attribute> @@ -3347,6 +3344,154 @@ Comes from the VPD MW Keyword</description> <odmChangeable/> </attribute> +<attribute> + <id>ATTR_EFF_RLO</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Gives the RLO value to use for this port. This comes from the MR Keyword of the VPD gives and indication of the value. It will be writable until it comes from VPD. The value is a positive integer number.</description> + <valueType>uint8</valueType> + <platInit/> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_CKE_PRI_MAP</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Contains the CKE MAP for the DIMM being plugged in. It comes from the MT keyword but is not on a port basis --- meaning this Attribute may be split: with 16 bits associated with port A data and 16 bits with B. This value goes directly into the MBA01 Rank-to-primary-CKE mapping table register bits 0:31 (MBA01_MBAREF1Q) register. This attribute is writeable until it comes from the VPD</description> + <valueType>uint32</valueType> + <platInit/> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_CKE_PWR_MAP</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Contains the CKE Power Domain mapping tables for the DIMM being plugged in. It comes from the MT keyword but is not on a port basis --- meaning this Attribute may be split: with 32 bits associated with port A data and 32 bits with B. This value goes directly into the MBA01 Rank-to-CKE power domain mapping table bits 0:33 (MBA01_MBARPC1Q) register. This attribute is writeable until it comes from the VPD</description> + <valueType>uint64</valueType> + <platInit/> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_GPO</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Global Phy Offset value that is used in setting up the phy. This value comes from the MR keyword of the VPD</description> + <valueType>uint8</valueType> + <platInit/> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_RDTAG</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Read Tag value that is used in setting up the phy. It is expected that this value will come from the VPD</description> + <valueType>uint8</valueType> + <platInit/> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_WLO</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Read Latency Offset value that is used in the phy. This value comes from the MR keyword of the VPD</description> + <valueType>uint8</valueType> + <platInit/> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_TSYS_ADR</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>TSYS for all address blocks in the MBA pair. This value comes from the MR keyword of the VPD</description> + <valueType>uint8</valueType> + <platInit/> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_TSYS_DP18</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>TSYS for all DP18 blocks in the MBA pair. This value comes from the MR keyword of the VPD</description> + <valueType>uint8</valueType> + <platInit/> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DQ_WR_OFFSET</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>DQ write offset value that is used in setting up the phy's phase rotators before WR_LVL, 0x40 is HW Default. It is expected that this value will come from the VPD</description> + <valueType>uint8</valueType> + <platInit/> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_BUFFER_LATENCY</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Additional buffer latency in the case of RDIMMs and LRDIMMs. It is expected that this value will come from the VPD</description> + <valueType>uint8</valueType> + <platInit/> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_LRDIMM_MR12_REG</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>LRDIMM MR1,2 register. +DRAM Rtt_WR for all ranks, DRAM Rtt_Nom for ranks 0 and 1, DRAM driver impedance for all ranks. Eff config should set this up.</description> + <valueType>uint8</valueType> + <odmVisable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_LRDIMM_ADDITIONAL_CNTL_WORDS</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>LRDIMM additional RCD control words as set by DIMM SPD: +F[3,4]RC10, F[3,4]RC11, F[5,6]RC10, F[5,6]RC11, F[7,8]RC10, F[7,8]RC11, F[9,10]RC10, F[9,10]RC11, +F[1]RC8, F[3]RC9, F[3]RC8, F[1]RC11, F[1]RC12, F[1]RC13, F[1]RC14, F[1]RC15. +Eff config should set this up</description> + <valueType>uint64</valueType> + <odmVisable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_LRDIMM_RANK_MULT_MODE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>LRDIMM rank multiplication mode. +Will be set at an MBA level with one policy to be used</description> + <valueType>uint8</valueType> + <enum>NORMAL = 0, 2X_MULT = 2, 4X_MULT = 4</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB --> <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP --> </attributes> |
