diff options
Diffstat (limited to 'src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile')
| -rw-r--r-- | src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile | 494 |
1 files changed, 494 insertions, 0 deletions
diff --git a/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile new file mode 100644 index 000000000..92deef365 --- /dev/null +++ b/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile @@ -0,0 +1,494 @@ +#-- $Id: p8.dmi.scom.initfile,v 1.7 2012/06/21 15:56:28 jmcgill Exp $ +#-- CHANGE HISTORY: +#-------------------------------------------------------------------------------- +#-- Version:|Author: | Date: | Comment: +#-- --------|--------|--------|-------------------------------------------------- +#-- 1.7 |jmcgill |06/21/12|Update tx_clk_cntl_gcrmsg_pg to use def_tx_base_grp instead of def_rx_base_grp +#-- 1.6 |jmcgill |06/21/12|Updates to match dials +#-- 1.5 |thomsen |06/19/12|Changed name of rx_grp3 to be def_rx_base_grp in order to be more generic +#-- |Updated PRBS_TAP_ID's to match Centaur +#-- 1.4 |jmcgill |06/16/12|Update to generate MCS0 chipunit addresses required for translation +#-- 1.3 |thomsen |06/16/12|Added attribute comments +#-- 1.2 |thomsen |06/16/12|Rewrote to use target bus number in the expression fields to allow address translation for group # +#-- 1.1 |thomsen |06/15/12|Created initial version +#-- --------|--------|--------|-------------------------------------------------- +#-------------------------------------------------------------------------------- +# End of revision history +#-------------------------------------------------------------------------------- + +#--Master list of variables that can be used in this file is at: +#--<Attribute Definition Location> + +#-- ATTR_CHIP_UNIT_POS is the MCS unit number (0-7 on Venice, 4-7 on Murano) and corresponds to the scom address translation done in +#-- the p8.chipunit.scominfo file. It is used to be able to select a specific clock group number. +#-- Chip UNIT_POS DMI_UNIT CLOCKGRP +#-- ---- -------- -------- -------- +#-- Venice: 0-3 DMI0 0-3 +#-- 4-7 DMI1 0-3 +#-- Murano: 4-7 DMI1 0-3 + +#-- ATTR_EI_BUS_RX_MSB_LSB_SWAP is 0 for setting RX PRBS TapID's to Non-Mirrored Mode and 1 for setting to Mirrored Mode. It comes from the MRW. +#-- ATTR_EI_BUS_TX_MSB_LSB_SWAP is 0 for setting TX PRBS TapID's to Non-Mirrored Mode and 1 for setting to Mirrored Mode. It comes from the MRW. + +SyntaxVersion = 1 + +#-- ----------------------------------------------------------------------------- +#--****************************************************************************** +#-- ----------------------------------------------------------------------------- +#-- +#-- Includes +#-- Note: Must include the path to the .define file. +#-- ----------------------------------------------------------------------------- +#--****************************************************************************** +#-- ----------------------------------------------------------------------------- +include edi.io.define +#-- ----------------------------------------------------------------------------- +#--****************************************************************************** +#-- ----------------------------------------------------------------------------- +#-- +#-- Defines +#-- +#-- ----------------------------------------------------------------------------- +#--****************************************************************************** +#-- ----------------------------------------------------------------------------- + +define def_bus_id3 = ((ATTR_CHIP_UNIT_POS == 0) || (ATTR_CHIP_UNIT_POS == 4)); +define def_bus_id2 = ((ATTR_CHIP_UNIT_POS == 1) || (ATTR_CHIP_UNIT_POS == 5)); +define def_bus_id1 = ((ATTR_CHIP_UNIT_POS == 2) || (ATTR_CHIP_UNIT_POS == 6)); +define def_bus_id0 = ((ATTR_CHIP_UNIT_POS == 3) || (ATTR_CHIP_UNIT_POS == 7)); + +define def_rx_mirrored_mode = (ATTR_EI_BUS_RX_MSB_LSB_SWAP == 1); # Mirrored mode +define def_rx_non_mirrored_mode = (ATTR_EI_BUS_RX_MSB_LSB_SWAP == 0); # Non-Mirrored mode +define def_tx_mirrored_mode = (ATTR_EI_BUS_TX_MSB_LSB_SWAP == 1); # Mirrored mode +define def_tx_non_mirrored_mode = (ATTR_EI_BUS_TX_MSB_LSB_SWAP == 0); # Non-Mirrored mode + +# See p8.chipunit.scominfo file for details of how SCOM addresses are translated by Cronus and FW based on the target unit number +define def_rx_base_grp = rx_grp3; # Venice and Murano wire clkgrp3 to Cen0, clkgrp2 to Cen1, clkgrp1 to Cen2 and clkgrp0 to Cen3 +define def_tx_base_grp = tx_grp3; # Venice and Murano wire clkgrp3 to Cen0, clkgrp2 to Cen1, clkgrp1 to Cen2 and clkgrp0 to Cen3 + +#--****************************************************************************** +#------------------------------------------------------------------------------------- +# _____ __ ________ +# / ___/___ / /___ ______ / _/ __ \ +# \__ \/ _ \/ __/ / / / __ \ / // / / / +# ___/ / __/ /_/ /_/ / /_/ / _/ // /_/ / +# /____/\___/\__/\__,_/ .___/ /___/_____/ +# /_/ banner2 -fslant +#------------------------------------------------------------------------------------- +#--****************************************************************************** +#### X bus -> 4 CG's, 20 lanes, A bus -> 3 CG's, 23 lanes , DMI bus -> 4 CG's, 24 lanes +# +# Target unit number based address translation method - fAPI translates group address and lower scom address based on target unit num passed in +# - So the scom address group number must be 000011 for RX and 100011 for TX and lower 32-bits of scom address needs to be DMI0 address +#--******************************************************************************************** +#-- rx_bus_id, tx_bus_id +#--******************************************************************************************** +scom 0x800.0b(rx_id1_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_bus_id , 0b000000, (def_bus_id0); # BusId equals the channel number on DMI (or equivalently the MCS#) + rx_bus_id , 0b000001, (def_bus_id1); # DMI0 contains MCS0-3 and DMI1 MCS4-7. However, the relative bus_id is always 0-3 + rx_bus_id , 0b000010, (def_bus_id2); + rx_bus_id , 0b000011, (def_bus_id3); + rx_group_id, 0b000000, any; # GroupID is always 000000 on all RX DMI channels +} +scom 0x800.0b(tx_id1_pg)(def_tx_base_grp)(lane_na).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + tx_bus_id , 0b000000, (def_bus_id0); # BusId equals the channel number on DMI (or equivalently the MCS#) + tx_bus_id , 0b000001, (def_bus_id1); # DMI0 contains MCS0-3 and DMI1 MCS4-7. However, the relative bus_id is always 0-3 + tx_bus_id , 0b000010, (def_bus_id2); + tx_bus_id , 0b000011, (def_bus_id3); + tx_group_id, 0b100000, any; # GroupID is always 100000 on all TX DMI channels +} +#--******************************************************************************************** +#-- rx_last_group_id, tx_last_group_id +#--******************************************************************************************** +scom 0x800.0b(rx_id2_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){ + bits, scom_data; + rx_last_group_id , 0b000000; # Each "bus/channel" on DMI consists only of one clock group so the last group is 000000 for RX +} +scom 0x800.0b(tx_id2_pg)(def_tx_base_grp)(lane_na).0x(dmi0_gcr_addr){ + bits, scom_data; + tx_last_group_id , 0b100000; # Each "bus/channel" on DMI consists only of one clock group so the last group is 100000 for TX +} +#--********************************************************************************************* +#-- rx_start_lane_id, rx_end_lane_id +#--********************************************************************************************* +# Upstream = 24-bits +scom 0x800.0b(rx_id3_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){ + bits, scom_data; + rx_start_lane_id , 0b0000000; # Each RX CG or "bus/channel" on DMI starts with lane 0 + rx_end_lane_id, 0b0010111; # Each RX CG or "bus/channel" on DMI ends with lane 23 +} +# Downstream = 17-bits +scom 0x800.0b(tx_id3_pg)(def_tx_base_grp)(lane_na).0x(dmi0_gcr_addr){ + bits, scom_data; + tx_start_lane_id , 0b0000000; # Each TX CG or "bus/channel" on DMI starts with lane 0 + tx_end_lane_id, 0b0010000; # Each TX CG or "bus/channel" on DMI ends with lane 16 +} +#--********************************************************************************************* +#-- rx_tx_bus_width, rx_rx_bus_width +#--********************************************************************************************* +# Upstream = 24-bits +scom 0x800.0b(rx_tx_bus_info_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){ + bits, scom_data; + rx_tx_bus_width, 0b0010001; # Each TX CG or "bus/channel" on DMI is 17-bits + rx_rx_bus_width, 0b0011000; # Each RX CG or "bus/channel" on DMI is 24-bits +} +#----------------------------------------------------------------------------------------------- +# ______ +# / ____/__ ____ ________ #### TODO: This needs to be set in the scaninit file and io_hard_reset factored into all reinit scenarios +# / /_ / _ \/ __ \/ ___/ _ \ +# / __/ / __/ / / / /__/ __/ +# /_/ \___/_/ /_/\___/\___/ banner2 -fslant +#---------------------------------------------------------------------------------------------- +scom 0x800.0b(rx_fence_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr) { + bits , scom_data; + rx_fence, 0b1; +} +#---------------------------------------------------------------------------------------------- +# __ ____ _ __ __ +# / / ____ _____ ___ / __ \(_)________ _/ /_ / /__ _____ +# / / / __ `/ __ \/ _ \ / / / / / ___/ __ `/ __ \/ / _ \/ ___/ +# / /___/ /_/ / / / / __/ / /_/ / (__ ) /_/ / /_/ / / __(__ ) +# /_____/\__,_/_/ /_/\___/ /_____/_/____/\__,_/_.___/_/\___/____/ banner2 -fslant +#---------------------------------------------------------------------------------------------- +#--********************************************************************************************* +#-- rx_lane_disabled_vec_0_15, rx_lane_disabled_vec_16_31 +#--********************************************************************************************* +# Upstream = 24-bits +scom 0x800.0b(rx_lane_disabled_vec_0_15_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){ + bits, scom_data; + rx_lane_disabled_vec_0_15, 0b0000000000000000; # Each RX CG or "bus/channel" on DMI has lanes 0-15 enabled (ie. disabled=0) +} +scom 0x800.0b(rx_lane_disabled_vec_16_31_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){ + bits, scom_data; + rx_lane_disabled_vec_16_31, 0b0000000011111111; # Each RX CG or "bus/channel" on DMI has lanes 16-23 enabled (ie. disabled=0) +} +#--********************************************************************************************* +#-- tx_lane_disabled_vec_0_15, tx_lane_disabled_vec_16_31 +#--********************************************************************************************* +# Downstream = 17-bits +scom 0x800.0b(tx_lane_disabled_vec_0_15_pg)(def_tx_base_grp)(lane_na).0x(dmi0_gcr_addr){ + bits, scom_data; + tx_lane_disabled_vec_0_15, 0b0000000000000000; # Each RX CG or "bus/channel" on DMI has lanes 0-15 enabled (ie. disabled=0) +} +scom 0x800.0b(tx_lane_disabled_vec_16_31_pg)(def_tx_base_grp)(lane_na).0x(dmi0_gcr_addr){ + bits, scom_data; + tx_lane_disabled_vec_16_31, 0b0111111111111111; # Each RX CG or "bus/channel" on DMI has lane 16 enabled (ie. disabled=0) +} +#------------------------------------------------------------------------------------- +# __ ___ ____ __ __ +# / |/ /___ __ __ / __ )____ _____/ / / / ____ _____ ___ _____ +# / /|_/ / __ `/ |/_/ / __ / __ `/ __ / / / / __ `/ __ \/ _ \/ ___/ +# / / / / /_/ /> < / /_/ / /_/ / /_/ / / /___/ /_/ / / / / __(__ ) +# /_/ /_/\__,_/_/|_| /_____/\__,_/\__,_/ /_____/\__,_/_/ /_/\___/____/ banner2 -fslant +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +#-- rx_wtr_max_bad_lanes, tx_max_bad_lanes +#--********************************************************************************************* +# Upstream = 2 spares +scom 0x800.0b(rx_wiretest_laneinfo_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){ + bits, scom_data; + rx_wtr_max_bad_lanes, 0b00010; # Each RX CG or "bus/channel" on DMI has 2 spare lanes +} +# Downstream = 2 spares +scom 0x800.0b(tx_mode_pg)(def_tx_base_grp)(lane_na).0x(dmi0_gcr_addr){ + bits, scom_data; + tx_max_bad_lanes, 0b00010; # Each TX CG or "bus/channel" on DMI has 2 spare lanes +} +#------------------------------------------------------------------------------------- +# ____ ____ _ ______ ____ _ +# / __ \__ ______ / __ \___ ____ ____ _(_)____ /_ __/___ _/ / /_ __(_)___ ____ _ +# / / / / / / / __ \ / /_/ / _ \/ __ \/ __ `/ / ___/ / / / __ `/ / / / / / / __ \/ __ `/ +# / /_/ / /_/ / / / / / _, _/ __/ /_/ / /_/ / / / / / / /_/ / / / /_/ / / / / / /_/ / +# /_____/\__, /_/ /_/ /_/ |_|\___/ .___/\__,_/_/_/ /_/ \__,_/_/_/\__, /_/_/ /_/\__, / +# /____/ /_/ /____/ /____/ banner2 -fslant +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +#-- rx_dyn_rpr_err_tallying1_pg: rx_dyn_rpr_bad_lane_max, rx_dyn_rpr_err_cntr1_duration, rx_dyn_rpr_enc_bad_data_lane_width +#--********************************************************************************************* +scom 0x800.0b(rx_dyn_rpr_err_tallying1_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){ + bits, scom_data; + rx_dyn_rpr_bad_lane_max, 0b0001111; # + rx_dyn_rpr_err_cntr1_duration, 0b0111; # + rx_dyn_rpr_enc_bad_data_lane_width, 0b101; # +} +#--********************************************************************************************* +#-- rx_dyn_rpr_err_tallying2_pg: rx_dyn_rpr_bad_bus_max, rx_dyn_rpr_err_cntr2_duration +#--********************************************************************************************* +scom 0x800.0b(rx_dyn_rpr_err_tallying2_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){ + bits, scom_data; + rx_dyn_rpr_bad_bus_max, 0b0111111; # + rx_dyn_rpr_err_cntr2_duration, 0b0111; # +} +#------------------------------------------------------------------------------------- +# __ ___ __ __ ___ __ +# / |/ /___ ______/ /____ _____ / |/ /___ ____/ /__ +# / /|_/ / __ `/ ___/ __/ _ \/ ___/ / /|_/ / __ \/ __ / _ \ +# / / / / /_/ (__ ) /_/ __/ / / / / / /_/ / /_/ / __/ +# /_/ /_/\__,_/____/\__/\___/_/ /_/ /_/\____/\__,_/\___/ +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +#-- rx_mode_pg: rx_master_mode +#--********************************************************************************************* +scom 0x800.0b(rx_mode_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){ + bits, scom_data; + rx_master_mode, 0b1; # Processor is always master on DMI +} +#------------------------------------------------------------------------------------- +# ____ ____ ____ _____ ______ _____ __ __ +# / __ \/ __ \/ __ ) ___/ /_ __/___ _____ / ___/___ / /__ _____/ /______ +# / /_/ / /_/ / __ \__ \ / / / __ `/ __ \ \__ \/ _ \/ / _ \/ ___/ __/ ___/ +# / ____/ _, _/ /_/ /__/ / / / / /_/ / /_/ / ___/ / __/ / __/ /__/ /_(__ ) +# /_/ /_/ |_/_____/____/ /_/ \__,_/ .___/ /____/\___/_/\___/\___/\__/____/ banner2 -fslant +# /_/ +#------------------------------------------------------------------------------------- +# PER-LANE (RX) +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +#-- rx_prbs_mode_pl: rx_prbs_tap_id +#--********************************************************************************************* +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_0).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_1).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_2).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_3).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_4).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_e, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_e, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_5).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_f, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_f, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_6).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_g, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_g, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_7).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_h, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_h, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_8).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_9).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_10).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_11).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_12).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_13).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_14).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_15).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_16).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_h, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_h, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_17).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_g, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_g, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_18).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_f, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_f, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_19).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_e, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_e, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_20).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_21).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_22).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_23).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_non_mirrored_mode); +} +#------------------------------------------------------------------------------------- +# PER-LANE (TX) +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +#-- tx_prbs_mode_pl: tx_prbs_tap_id +#--********************************************************************************************* +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_0).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_1).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_2).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_3).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_d, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_d, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_4).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_e, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_e, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_5).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_f, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_f, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_6).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_g, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_g, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_7).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_h, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_h, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_8).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_9).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_h, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_h, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_10).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_g, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_g, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_11).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_f, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_f, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_12).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_e, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_e, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_13).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_d, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_d, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_14).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_15).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_16).0x(dmi0_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_non_mirrored_mode); +} +#------------------------------------------------------------------------------------- +# ____ __ __ +# / __ \/ / / / +# / /_/ / / / / +# / ____/ /___/ /___ +# /_/ /_____/_____/ banner2 -fslant +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +#-- rx_wiretest_pll_cntl_pg: rx_wt_cu_pll_reset, rx_wt_cu_pll_pgooddly +#--********************************************************************************************* +scom 0x800.0b(rx_wiretest_pll_cntl_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){ + bits, scom_data; + rx_wt_cu_pll_reset, 0b0; + rx_wt_cu_pll_pgooddly, 0b001; # 50ns delay +} +#------------------------------------------------------------------------------------- +# ____ _ __________ ____ __ __ +# / __ \_____(_) _____ / ____/ / /__ / __ \____ _/ /_/ /____ _________ +# / / / / ___/ / | / / _ \ / / / / //_/ / /_/ / __ `/ __/ __/ _ \/ ___/ __ \ +# / /_/ / / / /| |/ / __/ / /___/ / ,< / ____/ /_/ / /_/ /_/ __/ / / / / / +# /_____/_/ /_/ |___/\___/ \____/_/_/|_| /_/ \__,_/\__/\__/\___/_/ /_/ /_/ +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +#-- tx_clk_cntl_gcrmsg_pg: tx_drv_clk_pattern_gcrmsg +#--********************************************************************************************* +scom 0x800.0b(tx_clk_cntl_gcrmsg_pg)(def_tx_base_grp)(lane_na).0x(dmi0_gcr_addr){ + bits, scom_data; + tx_drv_clk_pattern_gcrmsg, 0b00; # Drive 0's to start out +} + +############################################################################################ +# END OF FILE +############################################################################################ |
