diff options
Diffstat (limited to 'src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml')
| -rw-r--r-- | src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml | 416 |
1 files changed, 0 insertions, 416 deletions
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml deleted file mode 100644 index 84d133591..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml +++ /dev/null @@ -1,416 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2012,2015 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_setup_bars_mmio_attributes.xml,v 1.6 2015/02/02 18:57:33 jmcgill Exp $ --> -<!-- proc_setup_bars_mmio_attributes.xml --> -<attributes> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_PSI_BRIDGE_BAR_ENABLE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>PSI Bridge BAR enable - creator: platform - consumer: proc_setup_bars - firmware notes: none - </description> - <valueType>uint8</valueType> - <enum>DISABLE = 0x0, ENABLE = 0x1</enum> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>PSI Bridge BAR base address value - creator: platform - consumer: proc_setup_bars - firmware notes: - 64-bit address representing BAR RA - NOTE: BAR register covers RA 14:43 - NOTE: Implied size of 1MB - </description> - <valueType>uint64</valueType> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_FSP_BAR_ENABLE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>FSP BAR enable - creator: platform - consumer: proc_setup_bars - firmware notes: none - </description> - <valueType>uint8</valueType> - <enum>DISABLE = 0x0, ENABLE = 0x1</enum> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_FSP_BAR_BASE_ADDR</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>FSP BAR base address value - creator: platform - consumer: proc_setup_bars - firmware notes: - 64-bit address representing BAR RA - NOTE: BAR register covers RA 14:43 - </description> - <valueType>uint64</valueType> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_FSP_BAR_SIZE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>FSP BAR size value - creator: platform - consumer: proc_setup_bars - firmware notes: none - </description> - <valueType>uint64</valueType> - <enum> - 4_GB = 0x0000000100000000, - 2_GB = 0x0000000080000000, - 1_GB = 0x0000000040000000, - 512_MB = 0x0000000020000000, - 256_MB = 0x0000000010000000, - 128_MB = 0x0000000008000000, - 64_MB = 0x0000000004000000, - 32_MB = 0x0000000002000000, - 16_MB = 0x0000000001000000, - 8_MB = 0x0000000000800000, - 4_MB = 0x0000000000400000, - 2_MB = 0x0000000000200000, - 1_MB = 0x0000000000100000 - </enum> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_FSP_MMIO_MASK_SIZE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>FSP MMIO mask size value - creator: platform - consumer: proc_setup_bars - firmware notes: - AND mask applied to RA 32:35 when transmitting address to FSP - NOTE: RA 14:31 are always replaced with zero - </description> - <valueType>uint64</valueType> - <enum> - 4_GB = 0x0000000100000000, - 2_GB = 0x0000000080000000, - 1_GB = 0x0000000040000000, - 512_MB = 0x0000000020000000, - 256_MB = 0x0000000010000000 - </enum> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_INTP_BAR_ENABLE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>INTP BAR enable - creator: platform - consumer: proc_setup_bars - firmware notes: none - </description> - <valueType>uint8</valueType> - <enum>DISABLE = 0x0, ENABLE = 0x1</enum> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_INTP_BAR_BASE_ADDR</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>INTP BAR base address value - creator: platform - consumer: proc_setup_bars - firmware notes: - 64-bit address representing BAR RA - NOTE: BAR register covers RA 14:43 - NOTE: Implied size of 1MB - </description> - <valueType>uint64</valueType> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_AS_MMIO_BAR_ENABLE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>AS MMIO BAR enable - creator: platform - consumer: proc_setup_bars - firmware notes: none - </description> - <valueType>uint8</valueType> - <enum>DISABLE = 0x0, ENABLE = 0x1</enum> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_AS_MMIO_BAR_BASE_ADDR</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>AS MMIO BAR base address value - creator: platform - consumer: proc_setup_bars - firmware notes: - 64-bit address representing BAR RA - NOTE: BAR register covers RA 14:51 - </description> - <valueType>uint64</valueType> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_AS_MMIO_BAR_SIZE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>AS MMIO BAR size value - creator: platform - consumer: proc_setup_bars - firmware notes: none - </description> - <valueType>uint64</valueType> - <enum> - 2_MB = 0x0000000000200000, - 1_MB = 0x0000000000100000, - 512_KB = 0x0000000000080000, - 256_KB = 0x0000000000040000 - </enum> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_NX_MMIO_BAR_ENABLE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>NX MMIO BAR enable - creator: platform - consumer: proc_setup_bars - firmware notes: none - </description> - <valueType>uint8</valueType> - <enum>DISABLE = 0x0, ENABLE = 0x1</enum> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_NX_MMIO_BAR_BASE_ADDR</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>NX MMIO BAR base address value - creator: platform - consumer: proc_setup_bars - firmware notes: - 64-bit address representing BAR RA - NOTE: BAR register covers RA 14:51 - </description> - <valueType>uint64</valueType> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_NX_MMIO_BAR_SIZE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>NX MMIO BAR size value - creator: platform - consumer: proc_setup_bars - firmware notes: none - </description> - <valueType>uint64</valueType> - <enum> - 16_GB = 0x0000000400000000, - 16_MB = 0x0000000001000000, - 1_MB = 0x0000000000100000, - 64_KB = 0x0000000000010000, - 4_KB = 0x0000000000001000 - </enum> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_NPU_MMIO_BAR_ENABLE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>NPU MMIO BAR enables - creator: platform - consumer: proc_setup_bars - firmware notes: - first dimension: unit number (0:3) - second dimension: BAR number (0:1) - </description> - <valueType>uint8</valueType> - <enum>DISABLE = 0x0, ENABLE = 0x1</enum> - <array>4,2</array> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>NPU MMIO BAR base address values - creator: platform - consumer: proc_setup_bars - firmware notes: - 64-bit address representing BAR RA - NOTE: BAR register covers RA 14:51 - first dimension: unit number (0:3) - second dimension: BAR number (0:1) - </description> - <valueType>uint64</valueType> - <array>4,2</array> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_NPU_MMIO_BAR_SIZE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>NPU MMIO BAR size values - creator: platform - consumer: proc_setup_bars - firmware notes: none - first dimension: unit number (0:3) - second dimension: BAR number (0:1) - </description> - <valueType>uint64</valueType> - <enum> - 2_MB = 0x0000000000200000, - 1_MB = 0x0000000000100000, - 512_KB = 0x0000000000080000, - 256_KB = 0x0000000000040000, - 128_KB = 0x0000000000020000, - 64_KB = 0x0000000000010000 - </enum> - <array>4,2</array> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_PCIE_BAR_ENABLE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>PCIE BAR enable - creator: platform - consumer: proc_setup_bars - firmware notes: - first dimension: PCIE unit number (0:3) - second dimension: BAR number (0:2) - </description> - <valueType>uint8</valueType> - <enum>DISABLE = 0x0, ENABLE = 0x1</enum> - <array>4 3</array> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_PCIE_BAR_BASE_ADDR</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>PCIE BAR base address value - creator: platform - consumer: proc_setup_bars - firmware notes: - 64-bit address representing BAR RA - first dimension: PCIE unit number (0:3) - second dimension: BAR number (0:2) - NOTE: BAR0/1 registers cover RA 14:47 - NOTE: BAR2 registers covers RA 14:51 - </description> - <valueType>uint64</valueType> - <array>4 3</array> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> - <attribute> - <id>ATTR_PROC_PCIE_BAR_SIZE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>PCIE BAR size value - creator: platform - consumer: proc_setup_bars - firmware notes: - first dimension: PCIE unit number (0:3) - second dimension: BAR number (0:2) - NOTE: supported BAR0/1 sizes are from 64KB-1PB - NOTE: only supported BAR2 size is 4KB - </description> - <valueType>uint64</valueType> - <enum> - 1_PB = 0x0004000000000000, - 512_TB = 0x0002000000000000, - 256_TB = 0x0001000000000000, - 128_TB = 0x0000800000000000, - 64_TB = 0x0000400000000000, - 32_TB = 0x0000200000000000, - 16_TB = 0x0000100000000000, - 8_TB = 0x0000080000000000, - 4_TB = 0x0000040000000000, - 2_TB = 0x0000020000000000, - 1_TB = 0x0000010000000000, - 512_GB = 0x0000008000000000, - 256_GB = 0x0000004000000000, - 128_GB = 0x0000002000000000, - 64_GB = 0x0000001000000000, - 32_GB = 0x0000000800000000, - 16_GB = 0x0000000400000000, - 8_GB = 0x0000000200000000, - 4_GB = 0x0000000100000000, - 2_GB = 0x0000000080000000, - 1_GB = 0x0000000040000000, - 512_MB = 0x0000000020000000, - 256_MB = 0x0000000010000000, - 128_MB = 0x0000000008000000, - 64_MB = 0x0000000004000000, - 32_MB = 0x0000000002000000, - 16_MB = 0x0000000001000000, - 8_MB = 0x0000000000800000, - 4_MB = 0x0000000000400000, - 2_MB = 0x0000000000200000, - 1_MB = 0x0000000000100000, - 512_KB = 0x0000000000080000, - 256_KB = 0x0000000000040000, - 128_KB = 0x0000000000020000, - 64_KB = 0x0000000000010000, - 4_KB = 0x0000000000001000 - </enum> - <array>4 3</array> - <platInit/> - <persistRuntime/> - </attribute> - <!-- ********************************************************************* --> -</attributes> |
