diff options
Diffstat (limited to 'src/import')
29 files changed, 1141 insertions, 409 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C index 1c20e96b9..53152f649 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C @@ -38,8 +38,8 @@ #include <lib/utils/fake_vpd.H> #include <lib/mss_vpd_decoder.H> #include <lib/spd/spd_factory.H> -#include <lib/spd/common/spd_decoder.H> -#include <lib/spd/common/rcw_settings.H> +#include <generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H> +#include <generic/memory/lib/spd/common/rcw_settings.H> #include <lib/eff_config/timing.H> #include <lib/dimm/rank.H> #include <lib/utils/conversions.H> @@ -47,7 +47,7 @@ #include <lib/dimm/eff_dimm.H> #include <lib/dimm/mrs_load.H> #include <lib/shared/mss_kind.H> -#include <lib/spd/common/dimm_module_decoder.H> +#include <generic/memory/lib/spd/common/dimm_module_decoder.H> namespace mss { @@ -717,19 +717,19 @@ fapi2::ReturnCode eff_dimm::dram_trfc() switch(iv_refresh_mode) { case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_NORMAL: - FAPI_TRY( iv_pDecoder->min_refresh_recovery_delay_time_1(l_trfc_mtb), + FAPI_TRY( iv_pDecoder->min_trfc1(l_trfc_mtb), "Failed to decode SPD for tRFC1" ); break; case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FIXED_2X: case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FLY_2X: - FAPI_TRY( iv_pDecoder->min_refresh_recovery_delay_time_2(l_trfc_mtb), + FAPI_TRY( iv_pDecoder->min_trfc2(l_trfc_mtb), "Failed to decode SPD for tRFC2" ); break; case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FIXED_4X: case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FLY_4X: - FAPI_TRY( iv_pDecoder->min_refresh_recovery_delay_time_4(l_trfc_mtb), + FAPI_TRY( iv_pDecoder->min_trfc4(l_trfc_mtb), "Failed to decode SPD for tRFC4" ); break; @@ -1828,8 +1828,8 @@ fapi2::ReturnCode eff_dimm::dram_twr() constexpr int64_t l_twr_ftb = 0; int64_t l_twr_mtb = 0; - FAPI_TRY( iv_pDecoder->min_write_recovery_time(l_twr_mtb), - "Failed min_write_recovery_time() for %s", mss::c_str(iv_dimm) ); + FAPI_TRY( iv_pDecoder->min_twr(l_twr_mtb), + "Failed min_twr() for %s", mss::c_str(iv_dimm) ); FAPI_INF("%s medium timebase (ps): %ld, fine timebase (ps): %ld, tWR (MTB): %ld, tWR(FTB): %ld", mss::c_str(iv_dimm), iv_mtb, iv_ftb, l_twr_mtb, l_twr_ftb); @@ -2845,8 +2845,9 @@ fapi2::ReturnCode eff_dimm::dram_trp() int64_t l_trp_mtb = 0; int64_t l_trp_ftb = 0; - FAPI_TRY( iv_pDecoder->min_row_precharge_delay_time(l_trp_mtb), - "Failed min_row_precharge_delay_time() for %s", mss::c_str(iv_dimm) ); + FAPI_TRY( iv_pDecoder->min_trp(l_trp_mtb), + "Failed min_trp() for %s", mss::c_str(iv_dimm) ); + FAPI_TRY( iv_pDecoder->fine_offset_min_trp(l_trp_ftb), "Failed fine_offset_min_trp() for %s", mss::c_str(iv_dimm) ); @@ -2906,8 +2907,9 @@ fapi2::ReturnCode eff_dimm::dram_trcd() int64_t l_trcd_mtb = 0; int64_t l_trcd_ftb = 0; - FAPI_TRY( iv_pDecoder->min_ras_to_cas_delay_time(l_trcd_mtb), - "Failed min_ras_to_cas_delay_time() for %s", mss::c_str(iv_dimm) ); + FAPI_TRY( iv_pDecoder->min_trcd(l_trcd_mtb), + "Failed min_trcd() for %s", mss::c_str(iv_dimm) ); + FAPI_TRY( iv_pDecoder->fine_offset_min_trcd(l_trcd_ftb), "Failed fine_offset_min_trcd() for %s", mss::c_str(iv_dimm) ); @@ -2955,8 +2957,9 @@ fapi2::ReturnCode eff_dimm::dram_trc() int64_t l_trc_mtb = 0; int64_t l_trc_ftb = 0; - FAPI_TRY( iv_pDecoder->min_active_to_active_refresh_delay_time(l_trc_mtb), - "Failed min_active_to_active_refresh_delay_time() for %s", mss::c_str(iv_dimm) ); + FAPI_TRY( iv_pDecoder->min_trc(l_trc_mtb), + "Failed min_trc() for %s", mss::c_str(iv_dimm) ); + FAPI_TRY( iv_pDecoder->fine_offset_min_trc(l_trc_ftb), "Failed fine_offset_min_trc() for %s", mss::c_str(iv_dimm) ); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H index 73bc39ecb..010e10b59 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H @@ -34,7 +34,7 @@ #include <fapi2.H> #include <lib/shared/mss_kind.H> -#include <lib/spd/common/spd_decoder.H> +#include <generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H> #include <lib/eff_config/timing.H> namespace mss { diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.C b/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.C index 168625717..490b0677b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.C @@ -41,7 +41,7 @@ #include <fapi2.H> // mss lib -#include <lib/spd/common/spd_decoder.H> +#include <generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H> #include <lib/freq/cas_latency.H> #include <lib/freq/cycle_time.H> #include <lib/freq/sync.H> @@ -272,8 +272,8 @@ fapi2::ReturnCode cas_latency::get_taamin( const std::shared_ptr<mss::spd::decod "%s. Failed medium_timebase()", mss::c_str(iv_target) ); FAPI_TRY( i_pDecoder->fine_timebase(l_fine_timebase), "%s. Failed fine_timebase()", mss::c_str(iv_target) ); - FAPI_TRY( i_pDecoder->min_cas_latency_time(l_timing_mtb), - "%s. Failed min_cas_latency_time()", mss::c_str(iv_target) ); + FAPI_TRY( i_pDecoder->min_taa(l_timing_mtb), + "%s. Failed min_taa()", mss::c_str(iv_target) ); FAPI_TRY( i_pDecoder->fine_offset_min_taa(l_timing_ftb), "%s. Failed fine_offset_min_taa()", mss::c_str(iv_target) ); @@ -321,8 +321,8 @@ fapi2::ReturnCode cas_latency::get_tckmin( const std::shared_ptr<mss::spd::decod "%s. Failed medium_timebase()", mss::c_str(iv_target) ); FAPI_TRY( i_pDecoder->fine_timebase(l_fine_timebase), "%s. Failed fine_timebase()", mss::c_str(iv_target) ); - FAPI_TRY( i_pDecoder->min_cycle_time(l_timing_mtb), - "%s. Failed min_cycle_time()", mss::c_str(iv_target) ); + FAPI_TRY( i_pDecoder->min_tck(l_timing_mtb), + "%s. Failed min_tck()", mss::c_str(iv_target) ); FAPI_TRY( i_pDecoder->fine_offset_min_tck(l_timing_ftb), "%s. Failed fine_offset_min_tck()", mss::c_str(iv_target) ); @@ -369,8 +369,8 @@ fapi2::ReturnCode cas_latency::get_tckmax( const std::shared_ptr<mss::spd::decod "%s. Failed medium_timebase()", mss::c_str(iv_target) ); FAPI_TRY( i_pDecoder->fine_timebase(l_fine_timebase), "%s. Failed fine_timebase()", mss::c_str(iv_target) ); - FAPI_TRY( i_pDecoder->max_cycle_time(l_timing_mtb), - "%s. Failed max_cycle_time()", mss::c_str(iv_target) ); + FAPI_TRY( i_pDecoder->max_tck(l_timing_mtb), + "%s. Failed max_tck()", mss::c_str(iv_target) ); FAPI_TRY( i_pDecoder->fine_offset_max_tck(l_timing_ftb), "%s. Failed fine_offset_max_tck()", mss::c_str(iv_target) ); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.H b/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.H index aa35274b7..6322bb40a 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.H @@ -45,7 +45,7 @@ #include <fapi2.H> // mss lib -#include <lib/spd/common/spd_decoder.H> +#include <generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H> namespace mss { diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C index 0d9bc1bcd..f236342bb 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C @@ -42,11 +42,13 @@ // mss lib #include <lib/spd/spd_factory.H> -#include <lib/spd/common/spd_decoder.H> -#include <lib/spd/common/rcw_settings.H> -#include <lib/spd/rdimm/rdimm_raw_cards.H> -#include <lib/spd/lrdimm/lrdimm_raw_cards.H> -#include <lib/utils/checker.H> +#include <generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H> +#include <generic/memory/lib/spd/rdimm/ddr4/rdimm_decoder_ddr4.H> +#include <generic/memory/lib/spd/lrdimm/ddr4/lrdimm_decoder_ddr4.H> +#include <generic/memory/lib/spd/common/rcw_settings.H> +#include <generic/memory/lib/spd/rdimm/ddr4/rdimm_raw_cards.H> +#include <generic/memory/lib/spd/lrdimm/ddr4/lrdimm_raw_cards.H> +#include <generic/memory/lib/spd/spd_checker.H> #include <generic/memory/lib/utils/c_str.H> #include <lib/utils/conversions.H> #include <generic/memory/lib/utils/find.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.H b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.H index 88728df10..29f6804ba 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.H @@ -44,7 +44,7 @@ #include <fapi2.H> // mss lib -#include <lib/spd/common/spd_decoder.H> +#include <generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H> namespace mss { diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.H index b8a59c91b..7d2b243ed 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.H @@ -171,130 +171,6 @@ fapi_try_exit: /// fapi2::ReturnCode temp_refresh_mode(); -namespace spd -{ - -/// -/// @brief Checks conditional passes and implements traces & exits if it fails -/// @tparam T input data of any size -/// @param[in] i_target fapi2 dimm target -/// @param[in] i_conditional conditional that we are testing against -/// @param[in] i_spd_byte_index current SPD byte -/// @param[in] i_spd_data debug data -/// @param[in] i_err_str error string to print out when conditional fails -/// @return ReturnCode -/// -template< typename T > -inline fapi2::ReturnCode fail_for_invalid_value(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const bool i_conditional, - const size_t i_spd_byte_index, - const T i_spd_data, - const char* i_err_str) -{ - FAPI_ASSERT(i_conditional, - fapi2::MSS_BAD_SPD(). - set_VALUE(i_spd_data). - set_BYTE(i_spd_byte_index). - set_DIMM_TARGET(i_target), - "%s %s Byte %d, Data returned: %d.", - c_str(i_target), - i_err_str, - i_spd_byte_index, - i_spd_data); - - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; - -} // fail_for_invalid_value() - -/// -/// @brief Checks conditional passes and implements traces if it fails. No FFDC collected. -/// @tparam T input data of any size -/// @param[in] i_target fapi2 dimm target -/// @param[in] i_conditional that we are testing against -/// @param[in] i_spd_byte_index -/// @param[in] i_spd_data debug data -/// @param[in] i_err_str string to print out when conditional fails -/// @return void -/// -template< typename T > -inline void warn_for_invalid_value(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const bool i_conditional, - const size_t i_spd_byte_index, - const T i_spd_data, - const char* i_err_str) -{ - // Don't print warning conditional if true - if(!i_conditional) - { - FAPI_IMP("%s. %s. Byte %d, Data returned: %d.", - c_str(i_target), - i_err_str, - i_spd_byte_index, - i_spd_data ); - } -}// warn_for_invalid_value - -/// -/// @brief Checks if valid factory parameters are given -/// @param[in] i_target fapi2 dimm target -/// @param[in] i_dimm_type DIMM type enumeration -/// @param[in] i_encoding_rev SPD encoding level rev number -/// @param[in] i_additions_rev SPD additions level rev number -/// @param[in] i_err_str string to print out when conditional fails -/// @return fapi2::ReturnCode -/// -inline fapi2::ReturnCode invalid_factory_sel(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint8_t i_dimm_type, - const uint8_t i_encoding_rev, - const uint8_t i_additions_rev, - const char* i_err_str) -{ - FAPI_ASSERT(false, - fapi2::MSS_INVALID_DIMM_REV_COMBO(). - set_DIMM_TYPE(i_dimm_type). - set_ENCODING_REV(i_encoding_rev). - set_ADDITIONS_REV(i_additions_rev). - set_DIMM_TARGET(i_target), - "%s. %s. Invalid combination for dimm type: %d, rev: %d.%d", - c_str(i_target), - i_err_str, - i_dimm_type, - i_encoding_rev, - i_additions_rev); - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -}// invalid_factory_sel - -/// -/// @brief Checks if valid factory parameters are given -/// @param[in] i_target fapi2 dimm target -/// @param[in] i_dimm_type DIMM type enumeration -/// @param[in] i_encoding_rev SPD encoding level rev number -/// @param[in] i_additions_rev SPD additions level rev number -/// @param[in] i_err_str string to print out when conditional fails -/// @return fapi2::ReturnCode -/// -inline fapi2::ReturnCode invalid_cache(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const bool i_conditional, - const uint8_t i_dimm_pos) -{ - FAPI_ASSERT(i_conditional, - fapi2::MSS_INVALID_CACHE(). - set_DIMM_POS(i_dimm_pos). - set_DIMM_TARGET(i_target), - "%s. Could not find SPD decoder cache for dimm pos: %d", - c_str(i_target), - i_dimm_pos); - - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -}// invalid_factory_sel - -}// spd }// check }// mss diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C index 93cf877b3..ae4e90374 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C @@ -42,7 +42,7 @@ #include <fapi2.H> // mss lib -#include <lib/spd/common/spd_decoder.H> +#include <generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H> #include <lib/spd/spd_factory.H> #include <generic/memory/lib/utils/pos.H> #include <lib/utils/checker.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.C index dfa6bec91..042f825de 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.C @@ -45,7 +45,7 @@ #include <fapi2.H> // mss lib -#include <lib/spd/common/spd_decoder.H> +#include <generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H> #include <lib/spd/spd_factory.H> #include <lib/freq/cas_latency.H> #include <generic/memory/lib/utils/c_str.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.C index ccd180c06..77c9afd6c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_volt.C @@ -44,7 +44,7 @@ // mss lib #include <lib/spd/spd_factory.H> -#include <lib/spd/common/spd_decoder.H> +#include <generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H> #include <lib/eff_config/attr_setters.H> #include <generic/memory/lib/utils/c_str.H> #include <generic/memory/lib/utils/pos.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.H b/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H index 187a43a71..65198a856 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.H +++ b/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.H $ */ +/* $Source: src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -45,11 +45,13 @@ #include <fapi2.H> // mss lib -#include <lib/spd/common/dimm_module_decoder.H> -#include <lib/spd/common/rcw_settings.H> -#include <lib/spd/rdimm/rdimm_decoder.H> -#include <lib/spd/lrdimm/lrdimm_decoder.H> +#include <generic/memory/lib/spd/common/dimm_module_decoder.H> +#include <generic/memory/lib/spd/common/rcw_settings.H> +#include <generic/memory/lib/spd/rdimm/ddr4/rdimm_decoder_ddr4.H> +#include <generic/memory/lib/spd/lrdimm/ddr4/lrdimm_decoder_ddr4.H> #include <generic/memory/lib/utils/c_str.H> +#include <generic/memory/lib/spd/common/spd_decoder_base.H> + namespace mss { @@ -173,10 +175,9 @@ inline uint8_t extract_spd_field(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i /// @class decoder /// @brief Base SPD DRAM decoder /// -class decoder +class decoder : public base_decoder { protected: - enum { // Byte 0 @@ -479,10 +480,6 @@ class decoder virtual fapi2::ReturnCode prim_sdram_logical_ranks( uint8_t& o_logical_ranks ); public: - const fapi2::Target<fapi2::TARGET_TYPE_DIMM> iv_target; - std::shared_ptr<dimm_module_decoder> iv_module_decoder; - std::vector<uint8_t> iv_spd_data; - rcw_settings iv_raw_card; // Default constructor deleted decoder() = delete; @@ -517,7 +514,7 @@ class decoder /// @note Page 14 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode number_of_used_bytes( uint16_t& o_value ); + virtual fapi2::ReturnCode number_of_used_bytes( uint16_t& o_value ) override; /// /// @brief Decodes total number of SPD bytes @@ -528,7 +525,7 @@ class decoder /// @note Page 14 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode number_of_total_bytes( uint16_t& o_value ); + virtual fapi2::ReturnCode number_of_total_bytes( uint16_t& o_value ) override; /// /// @brief Decodes hybrid media field from SPD @@ -539,7 +536,7 @@ class decoder /// @note Page 17 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode hybrid_media( uint8_t& o_value ); + virtual fapi2::ReturnCode hybrid_media( uint8_t& o_value ) override; /// /// @brief Decodes hybrid field from SPD @@ -550,7 +547,7 @@ class decoder /// @note Page 17 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode hybrid( uint8_t& o_value ); + virtual fapi2::ReturnCode hybrid( uint8_t& o_value ) override; /// /// @brief Decodes SDRAM density from SPD @@ -561,7 +558,7 @@ class decoder /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode sdram_density( uint8_t& o_value ); + virtual fapi2::ReturnCode sdram_density( uint8_t& o_value ) override; /// /// @brief Decodes number of SDRAM banks bits from SPD @@ -572,7 +569,7 @@ class decoder /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode bank_bits( uint8_t& o_value ); + virtual fapi2::ReturnCode bank_bits( uint8_t& o_value ) override; /// /// @brief Decodes number of SDRAM bank groups bits from SPD @@ -583,7 +580,7 @@ class decoder /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode bank_group_bits( uint8_t& o_value ); + virtual fapi2::ReturnCode bank_group_bits( uint8_t& o_value ) override; /// /// @brief Decodes number of SDRAM column address bits @@ -593,7 +590,7 @@ class decoder /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode column_address_bits( uint8_t& o_value ); + virtual fapi2::ReturnCode column_address_bits( uint8_t& o_value ) override; /// /// @brief Decodes number of SDRAM row address bits @@ -603,7 +600,7 @@ class decoder /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode row_address_bits( uint8_t& o_value ); + virtual fapi2::ReturnCode row_address_bits( uint8_t& o_value ) override; /// /// @brief Decodes Primary SDRAM signal loading @@ -613,7 +610,7 @@ class decoder /// @note Page 19 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode prim_sdram_signal_loading( uint8_t& o_value ); + virtual fapi2::ReturnCode prim_sdram_signal_loading( uint8_t& o_value ) override; /// /// @brief Decodes Primary SDRAM die count @@ -623,7 +620,7 @@ class decoder /// @note Page 19 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode prim_sdram_die_count( uint8_t& o_value ); + virtual fapi2::ReturnCode prim_sdram_die_count( uint8_t& o_value ) override; /// /// @brief Decodes Primary SDRAM package type @@ -633,7 +630,7 @@ class decoder /// @note Page 19 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode prim_sdram_package_type( uint8_t& o_value ); + virtual fapi2::ReturnCode prim_sdram_package_type( uint8_t& o_value ) override; /// /// @brief Decode SDRAM Maximum activate count @@ -643,7 +640,7 @@ class decoder /// @note Page 20 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode maximum_activate_count( uint32_t& o_value ); + virtual fapi2::ReturnCode maximum_activate_count( uint32_t& o_value ) override; /// /// @brief Decode SDRAM Maximum activate window (multiplier), tREFI uknown at this point @@ -653,7 +650,7 @@ class decoder /// @note Page 20 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode maximum_activate_window_multiplier( uint32_t& o_value ); + virtual fapi2::ReturnCode maximum_activate_window_multiplier( uint32_t& o_value ) override; /// /// @brief Decode Post package repair (PPR) @@ -663,7 +660,7 @@ class decoder /// @note Page 21 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode post_package_repair( uint8_t& o_value ); + virtual fapi2::ReturnCode post_package_repair( uint8_t& o_value ) override; /// /// @brief Decode Soft post package repair (soft PPR) @@ -673,7 +670,7 @@ class decoder /// @note Page 21 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode soft_post_package_repair( uint8_t& o_value ); + virtual fapi2::ReturnCode soft_post_package_repair( uint8_t& o_value ) override; /// /// @brief Decodes Secondary SDRAM signal loading @@ -683,7 +680,7 @@ class decoder /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode sec_sdram_signal_loading( uint8_t& o_value ); + virtual fapi2::ReturnCode sec_sdram_signal_loading( uint8_t& o_value ) override; /// /// @brief Decodes Secondary DRAM Density Ratio @@ -693,7 +690,7 @@ class decoder /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode sec_dram_density_ratio( uint8_t& o_value ); + virtual fapi2::ReturnCode sec_dram_density_ratio( uint8_t& o_value ) override; /// /// @brief Decodes Secondary SDRAM die count @@ -703,7 +700,7 @@ class decoder /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode sec_sdram_die_count( uint8_t& o_value ); + virtual fapi2::ReturnCode sec_sdram_die_count( uint8_t& o_value ) override; /// /// @brief Decodes Secondary SDRAM package type @@ -713,7 +710,7 @@ class decoder /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode sec_sdram_package_type( uint8_t& o_value ); + virtual fapi2::ReturnCode sec_sdram_package_type( uint8_t& o_value ) override; /// /// @brief Decode Module Nominal Voltage, VDD @@ -724,7 +721,7 @@ class decoder /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode operable_nominal_voltage( uint8_t& o_value ); + virtual fapi2::ReturnCode operable_nominal_voltage( uint8_t& o_value ) override; /// /// @brief Decode Module Nominal Voltage, VDD @@ -735,7 +732,7 @@ class decoder /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode endurant_nominal_voltage( uint8_t& o_value ); + virtual fapi2::ReturnCode endurant_nominal_voltage( uint8_t& o_value ) override; /// /// @brief Decodes SDRAM device width /// @param[out] o_value device width in bits @@ -745,7 +742,7 @@ class decoder /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode device_width( uint8_t& o_value ); + virtual fapi2::ReturnCode device_width( uint8_t& o_value ) override; /// /// @brief Decodes number of package ranks per DIMM @@ -756,7 +753,7 @@ class decoder /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode num_package_ranks_per_dimm( uint8_t& o_value ); + virtual fapi2::ReturnCode num_package_ranks_per_dimm( uint8_t& o_value ) override; /// /// @brief Decodes Rank Mix @@ -767,7 +764,7 @@ class decoder /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode rank_mix( uint8_t& o_value ); + virtual fapi2::ReturnCode rank_mix( uint8_t& o_value ) override; /// /// @brief Decodes primary bus width @@ -778,7 +775,7 @@ class decoder /// @note Page 27 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode prim_bus_width( uint8_t& o_value ); + virtual fapi2::ReturnCode prim_bus_width( uint8_t& o_value ) override; /// /// @brief Decodes bus width extension @@ -789,7 +786,7 @@ class decoder /// @note Page 27 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode bus_width_extension( uint8_t& o_value ); + virtual fapi2::ReturnCode bus_width_extension( uint8_t& o_value ) override; /// /// @brief Decode Module Thermal Sensor @@ -800,7 +797,7 @@ class decoder /// @note Page 28 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode thermal_sensor( uint8_t& o_value ); + virtual fapi2::ReturnCode thermal_sensor( uint8_t& o_value ) override; /// /// @brief Decode Extended Base Module Type @@ -811,7 +808,7 @@ class decoder /// @note Page 28 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode extended_base_module_type( uint8_t& o_value ); + virtual fapi2::ReturnCode extended_base_module_type( uint8_t& o_value ) override; /// /// @brief Decode Fine Timebase @@ -822,7 +819,7 @@ class decoder /// @note Page 29 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_timebase( int64_t& o_value ); + virtual fapi2::ReturnCode fine_timebase( int64_t& o_value ) override; /// /// @brief Decode Medium Timebase @@ -833,7 +830,7 @@ class decoder /// @note Page 29 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode medium_timebase( int64_t& o_value ); + virtual fapi2::ReturnCode medium_timebase( int64_t& o_value ) override; /// /// @@ -849,7 +846,7 @@ class decoder /// integer and the Fine Offset for tCKmin (SPD byte 125) /// used for correction to get the actual value. /// - virtual fapi2::ReturnCode min_cycle_time( int64_t& o_value ); + virtual fapi2::ReturnCode min_tck( int64_t& o_value ) override; /// /// @brief Decodes SDRAM Maximum Cycle Time in MTB @@ -864,7 +861,7 @@ class decoder /// integer and the Fine Offset for tCKmax (SPD byte 124) /// used for correction to get the actual value. /// - virtual fapi2::ReturnCode max_cycle_time( int64_t& o_value ); + virtual fapi2::ReturnCode max_tck( int64_t& o_value ) override; /// /// @brief Decode CAS Latencies Supported @@ -875,7 +872,7 @@ class decoder /// @note Page 33-34 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode supported_cas_latencies( uint64_t& o_value ); + virtual fapi2::ReturnCode supported_cas_latencies( uint64_t& o_value ) override; /// /// @brief Decodes SDRAM Minimum CAS Latency Time in MTB @@ -890,7 +887,7 @@ class decoder /// integer and the Fine Offset for tAAmin (SPD byte 123) /// used for correction to get the actual value. /// - virtual fapi2::ReturnCode min_cas_latency_time( int64_t& o_value ); + virtual fapi2::ReturnCode min_taa( int64_t& o_value ) override; /// /// @brief Decodes SDRAM Minimum RAS to CAS Delay Time in MTB @@ -905,7 +902,7 @@ class decoder /// integer and the Fine Offset for tRCDmin (SPD byte 122) /// used for correction to get the actual value /// - virtual fapi2::ReturnCode min_ras_to_cas_delay_time( int64_t& o_value ); + virtual fapi2::ReturnCode min_trcd( int64_t& o_value ) override; /// /// @brief Decodes SDRAM Minimum Row Precharge Delay Time in MTB @@ -920,7 +917,7 @@ class decoder /// integer and the Fine Offset for tRPmin (SPD byte 121) /// used for correction to get the actual value /// - virtual fapi2::ReturnCode min_row_precharge_delay_time( int64_t& o_value ); + virtual fapi2::ReturnCode min_trp( int64_t& o_value ) override; /// /// @brief Decodes SDRAM Minimum Active to Precharge Delay Time in MTB @@ -931,7 +928,7 @@ class decoder /// @note Page 38 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_active_to_precharge_delay_time( int64_t& o_value ); + virtual fapi2::ReturnCode min_tras( int64_t& o_value ) override; /// /// @brief Decodes SDRAM Minimum Active to Active/Refresh Delay Time in MTB @@ -946,8 +943,7 @@ class decoder /// integer and the Fine Offset for tRCmin (SPD byte 120) /// used for correction to get the actual value. /// - virtual - fapi2::ReturnCode min_active_to_active_refresh_delay_time( int64_t& o_value ); + virtual fapi2::ReturnCode min_trc( int64_t& o_value ) override; /// /// @brief Decodes SDRAM Minimum Refresh Recovery Delay Time 1 @@ -958,7 +954,7 @@ class decoder /// @note Page 39-40 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_refresh_recovery_delay_time_1( int64_t& o_value ); + virtual fapi2::ReturnCode min_trfc1( int64_t& o_value ) override; /// /// @brief Decodes SDRAM Minimum Refresh Recovery Delay Time 2 @@ -969,7 +965,7 @@ class decoder /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_refresh_recovery_delay_time_2( int64_t& o_value ); + virtual fapi2::ReturnCode min_trfc2( int64_t& o_value ) override; /// /// @brief Decodes SDRAM Minimum Refresh Recovery Delay Time 4 @@ -980,7 +976,7 @@ class decoder /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_refresh_recovery_delay_time_4( int64_t& o_value ); + virtual fapi2::ReturnCode min_trfc4( int64_t& o_value ) override; /// /// @brief Decodes SDRAM Minimum Four Activate Window Delay Time @@ -991,7 +987,7 @@ class decoder /// @note Page 42 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_tfaw( int64_t& o_value ); + virtual fapi2::ReturnCode min_tfaw( int64_t& o_value ) override; /// /// @brief Decodes Minimum Activate to Activate Delay Time - Different Bank Group @@ -1006,7 +1002,7 @@ class decoder /// integer and the Fine Offset for tRRD_Smin (SPD byte 119) /// used for correction to get the actual value. /// - virtual fapi2::ReturnCode min_trrd_s( int64_t& o_value ); + virtual fapi2::ReturnCode min_trrd_s( int64_t& o_value ) override; /// /// @brief Decodes Minimum Activate to Activate Delay Time - Same Bank Group @@ -1021,7 +1017,7 @@ class decoder /// integer and the Fine Offset for tRRD_Lmin (SPD byte 118) /// used for correction to get the actual value. /// - virtual fapi2::ReturnCode min_trrd_l( int64_t& o_value ); + virtual fapi2::ReturnCode min_trrd_l( int64_t& o_value ) override; /// /// @brief Decodes Minimum CAS to CAS Delay Time - Same Bank Group @@ -1036,7 +1032,7 @@ class decoder /// integer and the Fine Offset for tCCD_Lmin (SPD byte 117) /// used for correction to get the actual value. /// - virtual fapi2::ReturnCode min_tccd_l( int64_t& o_value ); + virtual fapi2::ReturnCode min_tccd_l( int64_t& o_value ) override; /// /// @brief Decodes Minimum Write Recovery Time @@ -1047,7 +1043,7 @@ class decoder /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_write_recovery_time( int64_t& o_value ); + virtual fapi2::ReturnCode min_twr( int64_t& o_value ) override; /// /// @brief Decodes Minimum Write to Read Time - Different Bank Group @@ -1058,7 +1054,7 @@ class decoder /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_twtr_s( int64_t& o_value ); + virtual fapi2::ReturnCode min_twtr_s( int64_t& o_value ) override; /// /// @brief Decodes Minimum Write to Read Time - Same Bank Group @@ -1069,7 +1065,7 @@ class decoder /// @note Page 46 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_twtr_l( int64_t& o_value ); + virtual fapi2::ReturnCode min_twtr_l( int64_t& o_value ) override; /// /// @brief Decodes Fine Offset for Minimum CAS to CAS Delay Time - Same Bank Group @@ -1080,7 +1076,7 @@ class decoder /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_min_tccd_l( int64_t& o_value ); + virtual fapi2::ReturnCode fine_offset_min_tccd_l( int64_t& o_value ) override; /// /// @brief Decodes Fine Offset for Minimum Activate to Activate Delay Time - Same Bank Group @@ -1091,7 +1087,7 @@ class decoder /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_min_trrd_l( int64_t& o_value ); + virtual fapi2::ReturnCode fine_offset_min_trrd_l( int64_t& o_value ) override; /// /// @brief Decodes Fine Offset for Minimum Activate to Activate Delay Time - Different Bank Group @@ -1102,7 +1098,7 @@ class decoder /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_min_trrd_s( int64_t& o_value ); + virtual fapi2::ReturnCode fine_offset_min_trrd_s( int64_t& o_value ) override; /// /// @brief Decodes Fine Offset for Minimum Active to Active/Refresh Delay Time @@ -1113,7 +1109,7 @@ class decoder /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_min_trc( int64_t& o_value ); + virtual fapi2::ReturnCode fine_offset_min_trc( int64_t& o_value ) override; /// /// @brief Decodes Fine Offset for Minimum Row Precharge Delay Time @@ -1124,7 +1120,7 @@ class decoder /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_min_trp( int64_t& o_value ); + virtual fapi2::ReturnCode fine_offset_min_trp( int64_t& o_value ) override; /// /// @brief Decodes Fine Offset for SDRAM Minimum RAS to CAS Delay Time @@ -1135,7 +1131,7 @@ class decoder /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_min_trcd( int64_t& o_value ); + virtual fapi2::ReturnCode fine_offset_min_trcd( int64_t& o_value ) override; /// /// @brief Decodes Fine Offset for SDRAM Minimum CAS Latency Time @@ -1146,7 +1142,7 @@ class decoder /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_min_taa( int64_t& o_value ); + virtual fapi2::ReturnCode fine_offset_min_taa( int64_t& o_value ) override; /// /// @brief Decodes Fine Offset for SDRAM Maximum Cycle Time @@ -1157,7 +1153,7 @@ class decoder /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_max_tck( int64_t& o_value ); + virtual fapi2::ReturnCode fine_offset_max_tck( int64_t& o_value ) override; /// /// @brief Decodes Fine Offset for SDRAM Minimum Cycle Time @@ -1168,7 +1164,7 @@ class decoder /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_min_tck( int64_t& o_value ); + virtual fapi2::ReturnCode fine_offset_min_tck( int64_t& o_value ) override; /// /// @brief Decodes Cyclical Redundancy Code (CRC) for Base Configuration Section @@ -1179,7 +1175,7 @@ class decoder /// @note Page 53 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode cyclical_redundancy_code( uint16_t& o_value ); + virtual fapi2::ReturnCode cyclical_redundancy_code( uint16_t& o_value ) override; /// /// @brief Decodes module manufacturer ID code @@ -1190,7 +1186,7 @@ class decoder /// @note DDR4 SPD Document Release 3 /// @note Page 4.1.2.12 - 54 /// - virtual fapi2::ReturnCode module_manufacturer_id_code( uint16_t& o_value ); + virtual fapi2::ReturnCode module_manufacturer_id_code( uint16_t& o_value ) override; /// /// @brief Decodes Module Manufacturing Location @@ -1201,7 +1197,7 @@ class decoder /// @note Page 55 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode module_manufacturing_location( uint8_t& o_value ); + virtual fapi2::ReturnCode module_manufacturing_location( uint8_t& o_value ) override; /// /// @brief Decodesmodule manufacturing date /// @param[out] o_output the 2 byte date of manufacturing in BCD format @@ -1213,7 +1209,7 @@ class decoder /// @note in Binary Coded Decimal (BCD) /// @note MSB = year, LSB = week /// - virtual fapi2::ReturnCode module_manufacturing_date( uint16_t& o_output ); + virtual fapi2::ReturnCode module_manufacturing_date( uint16_t& o_output ) override; /// /// @brief Decodes module's unique serial number @@ -1224,7 +1220,7 @@ class decoder /// @note DDR4 SPD Document Release 2 /// @note Page 4.1.2.12 - 54 /// - virtual fapi2::ReturnCode module_serial_number( uint32_t& o_output ); + virtual fapi2::ReturnCode module_serial_number( uint32_t& o_output ) override; /// /// @brief Decodes Module Revision Code @@ -1235,7 +1231,7 @@ class decoder /// @note Page 55 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode module_revision_code( uint8_t& o_value ); + virtual fapi2::ReturnCode module_revision_code( uint8_t& o_value ) override; /// /// @brief Decodes DRAM Manufacturer ID code @@ -1246,7 +1242,7 @@ class decoder /// @note DDR4 SPD Document Release 2 /// @note Page 4.1.2.12 - 54 /// - virtual fapi2::ReturnCode dram_manufacturer_id_code( uint16_t& o_output ); + virtual fapi2::ReturnCode dram_manufacturer_id_code( uint16_t& o_output ) override; /// /// @brief Decodes DRAM Stepping /// @param[out] o_value uint8_t DRAM Stepping val @@ -1257,14 +1253,14 @@ class decoder /// @note DDR4 SPD Document Release 3 /// @note also called die revision level /// - virtual fapi2::ReturnCode dram_stepping( uint8_t& o_value ); + virtual fapi2::ReturnCode dram_stepping( uint8_t& o_value ) override; /// /// @brief Returns Logical ranks per DIMM /// @param[out] o_logical_ranks number of logical ranks /// @return fapi2::FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode logical_ranks_per_dimm( uint8_t& o_logical_rank_per_dimm ); + virtual fapi2::ReturnCode logical_ranks_per_dimm( uint8_t& o_logical_rank_per_dimm ) override; };// decoder @@ -1435,7 +1431,7 @@ class decoder_v1_1 : public decoder /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_write_recovery_time( int64_t& o_value ) override; + virtual fapi2::ReturnCode min_twr( int64_t& o_value ) override; /// /// @brief Decodes Minimum Write to Read Time - Different Bank Group diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.C b/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4_v1_0.C index a1b15f8b1..ff265a585 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.C +++ b/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4_v1_0.C @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.C $ */ +/* $Source: src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4_v1_0.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -40,10 +40,10 @@ #include <fapi2.H> // mss lib -#include <lib/spd/common/spd_decoder.H> -#include <lib/spd/rdimm/rdimm_decoder.H> -#include <lib/spd/common/rcw_settings.H> -#include <lib/utils/checker.H> +#include <generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H> +#include <generic/memory/lib/spd/rdimm/ddr4/rdimm_decoder_ddr4.H> +#include <generic/memory/lib/spd/common/rcw_settings.H> +#include <generic/memory/lib/spd/spd_checker.H> #include <generic/memory/lib/utils/c_str.H> #include <generic/memory/lib/utils/find.H> @@ -71,10 +71,7 @@ decoder::decoder(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const std::vector<uint8_t>& i_spd_data, const std::shared_ptr<dimm_module_decoder>& i_module_decoder, const rcw_settings& i_raw_card) - : iv_target(i_target), - iv_module_decoder(i_module_decoder), - iv_spd_data(i_spd_data), - iv_raw_card(i_raw_card) + : base_decoder(i_target, i_spd_data, i_module_decoder, i_raw_card) {} /// @@ -1332,7 +1329,7 @@ fapi_try_exit: /// integer and the Fine Offset for tCKmin (SPD byte 125) /// used for correction to get the actual value. /// -fapi2::ReturnCode decoder::min_cycle_time( int64_t& o_value ) +fapi2::ReturnCode decoder::min_tck( int64_t& o_value ) { // Explicit conversion constexpr size_t BYTE_INDEX = 18; @@ -1379,7 +1376,7 @@ fapi_try_exit: /// integer and the Fine Offset for tCKmax (SPD byte 124) /// used for correction to get the actual value. /// -fapi2::ReturnCode decoder::max_cycle_time( int64_t& o_value ) +fapi2::ReturnCode decoder::max_tck( int64_t& o_value ) { // Explicit conversion constexpr size_t BYTE_INDEX = 19; @@ -1500,7 +1497,7 @@ fapi_try_exit: /// integer and the Fine Offset for tAAmin (SPD byte 123) /// used for correction to get the actual value. /// -fapi2::ReturnCode decoder::min_cas_latency_time( int64_t& o_value ) +fapi2::ReturnCode decoder::min_taa( int64_t& o_value ) { // Explicit conversion constexpr size_t BYTE_INDEX = 24; @@ -1547,7 +1544,7 @@ fapi_try_exit: /// integer and the Fine Offset for tRCDmin (SPD byte 122) /// used for correction to get the actual value /// -fapi2::ReturnCode decoder::min_ras_to_cas_delay_time( int64_t& o_value ) +fapi2::ReturnCode decoder::min_trcd( int64_t& o_value ) { // Explicit conversion constexpr size_t BYTE_INDEX = 25; @@ -1594,7 +1591,7 @@ fapi_try_exit: /// integer and the Fine Offset for tRPmin (SPD byte 121) /// used for correction to get the actual value /// -fapi2::ReturnCode decoder::min_row_precharge_delay_time( int64_t& o_value ) +fapi2::ReturnCode decoder::min_trp( int64_t& o_value ) { // Explicit conversion constexpr size_t BYTE_INDEX = 26; @@ -1638,7 +1635,7 @@ fapi_try_exit: /// @note Page 38 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder::min_active_to_precharge_delay_time( int64_t& o_value) +fapi2::ReturnCode decoder::min_tras( int64_t& o_value) { uint8_t tRASmin_MSN = extract_spd_field< TRASMIN_MSN >(iv_target, iv_spd_data); FAPI_INF("MSN Field Bits value: %lu", tRASmin_MSN); @@ -1701,7 +1698,7 @@ fapi_try_exit: /// integer and the Fine Offset for tRCmin (SPD byte 120) /// used for correction to get the actual value. /// -fapi2::ReturnCode decoder::min_active_to_active_refresh_delay_time( int64_t& o_value) +fapi2::ReturnCode decoder::min_trc( int64_t& o_value) { uint8_t tRCmin_MSN = extract_spd_field< TRCMIN_MSN >(iv_target, iv_spd_data); FAPI_INF("MSN Field Bits value: %lu", tRCmin_MSN); @@ -1759,7 +1756,7 @@ fapi_try_exit: /// @note Page 39-40 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder::min_refresh_recovery_delay_time_1( int64_t& o_value) +fapi2::ReturnCode decoder::min_trfc1( int64_t& o_value) { uint8_t tRFC1min_MSB = extract_spd_field< TRFC1MIN_MSB >(iv_target, iv_spd_data); FAPI_INF("MSB Field Bits value: %lu", tRFC1min_MSB); @@ -1817,7 +1814,7 @@ fapi_try_exit: /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder::min_refresh_recovery_delay_time_2( int64_t& o_value) +fapi2::ReturnCode decoder::min_trfc2( int64_t& o_value) { uint8_t tRFC2min_MSB = extract_spd_field< TRFC2MIN_MSB >(iv_target, iv_spd_data); FAPI_INF("MSB Field Bits value: %lu", tRFC2min_MSB); @@ -1875,7 +1872,7 @@ fapi_try_exit: /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder::min_refresh_recovery_delay_time_4( int64_t& o_value) +fapi2::ReturnCode decoder::min_trfc4( int64_t& o_value) { uint8_t tRFC4min_MSB = extract_spd_field< TRFC4MIN_MSB >(iv_target, iv_spd_data); FAPI_INF("MSB Field Bits value: %lu", tRFC4min_MSB); @@ -2138,7 +2135,7 @@ fapi_try_exit: /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder::min_write_recovery_time( int64_t& o_value) +fapi2::ReturnCode decoder::min_twr( int64_t& o_value) { // For General Section rev 1.0 of the SPD, // SPD Byte 41 (bits 3~0) & Byte 42 (bits 7~0) were reserved diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder_v1_1.C b/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4_v1_1.C index bac63b276..ea72b7615 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder_v1_1.C +++ b/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4_v1_1.C @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder_v1_1.C $ */ +/* $Source: src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4_v1_1.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ @@ -36,10 +36,9 @@ #include <fapi2.H> // mss lib -#include <lib/spd/common/spd_decoder.H> -#include <lib/utils/checker.H> +#include <generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H> +#include <generic/memory/lib/spd/spd_checker.H> #include <generic/memory/lib/utils/c_str.H> -#include <lib/utils/conversions.H> #include <generic/memory/lib/utils/find.H> using fapi2::TARGET_TYPE_MCA; @@ -609,7 +608,7 @@ fapi_try_exit: /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_1::min_write_recovery_time( int64_t& o_value ) +fapi2::ReturnCode decoder_v1_1::min_twr( int64_t& o_value ) { uint8_t tWRmin_MSN = extract_spd_field< TWRMIN_MSN >(iv_target, iv_spd_data); FAPI_INF("MSN Field Bits value: %lu", tWRmin_MSN); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/dimm_module_decoder.H b/src/import/generic/memory/lib/spd/common/dimm_module_decoder.H index f5d8660ae..67faa47a0 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/dimm_module_decoder.H +++ b/src/import/generic/memory/lib/spd/common/dimm_module_decoder.H @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/spd/common/dimm_module_decoder.H $ */ +/* $Source: src/import/generic/memory/lib/spd/common/dimm_module_decoder.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ @@ -68,8 +68,6 @@ class dimm_module_decoder /// @brief Decodes module nominal height max /// @param[out] o_output height range encoding from SPD /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 128 (Bits 4~0) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode max_module_nominal_height(uint8_t& o_output) { @@ -81,8 +79,6 @@ class dimm_module_decoder /// @brief Decodes raw card extension /// @param[out] o_output height range encoding from SPD /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 128 (Bits 7~5) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode raw_card_extension(uint8_t& o_output) { @@ -94,8 +90,6 @@ class dimm_module_decoder /// @brief Decodes front module maximum thickness max /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 129 (Bits 3~0) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode front_module_max_thickness(uint8_t& o_output) { @@ -107,8 +101,6 @@ class dimm_module_decoder /// @brief Decodes back module maximum thickness max /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 129 (Bits 7~4) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode back_module_max_thickness(uint8_t& o_output) { @@ -120,8 +112,6 @@ class dimm_module_decoder /// @brief Decodes number of registers used on RDIMM /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 131 (Bits 1~0) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode num_registers_used(uint8_t& o_output) { @@ -133,8 +123,6 @@ class dimm_module_decoder /// @brief Decodes number of rows of DRAMs on RDIMM /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 131 (Bits 3~2) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode num_rows_of_drams(uint8_t& o_output) { @@ -146,8 +134,6 @@ class dimm_module_decoder /// @brief Decodes register and buffer type for LRDIMMs /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 131 (Bits 7~4) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode register_and_buffer_type(uint8_t& o_output) { @@ -159,8 +145,6 @@ class dimm_module_decoder /// @brief Decodes heat spreader thermal characteristics /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCEawSS if okay - /// @note SPD Byte 132 (Bits 6~0) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode heat_spreader_thermal_char(uint8_t& o_output) { @@ -173,8 +157,6 @@ class dimm_module_decoder /// @brief Decodes heat spreader solution /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 132 (Bit 7) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode heat_spreader_solution(uint8_t& o_output) { @@ -186,8 +168,6 @@ class dimm_module_decoder /// @brief Decodes number of continuation codes /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 133 (Bits 6~0) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode num_continuation_codes(uint8_t& o_output) { @@ -199,8 +179,6 @@ class dimm_module_decoder /// @brief Decodes register manufacturer ID code /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 134 (Bits 7~0) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode reg_manufacturer_id_code(uint8_t& o_output) { @@ -212,8 +190,6 @@ class dimm_module_decoder /// @brief Decodes register revision number /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 135 (Bits 7~0) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode register_rev_num(uint8_t& o_output) { @@ -225,8 +201,6 @@ class dimm_module_decoder /// @brief Decodes address mapping from register to dram /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 136 (Bit 0) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode register_to_dram_addr_mapping(uint8_t& o_output) { @@ -238,8 +212,6 @@ class dimm_module_decoder /// @brief Decodes register output drive strength for CKE signal /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 137 (Bits 1~0) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode cke_signal_output_driver(uint8_t& o_output) { @@ -251,8 +223,6 @@ class dimm_module_decoder /// @brief Decodes register output drive strength for ODT signal /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 137 (Bits 3~2) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode odt_signal_output_driver(uint8_t& o_output) { @@ -264,8 +234,6 @@ class dimm_module_decoder /// @brief Decodes register output drive strength for command/address (CA) signal /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 137 (Bits 5~4) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode ca_signal_output_driver(uint8_t& o_output) { @@ -274,11 +242,9 @@ class dimm_module_decoder } /// - /// @brief Decodes register output drive strength for chip select (CS) signal + /// @brief Decodes register output drive strength for control signal (CS) signal /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 137 (Bits 6~7) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode cs_signal_output_driver(uint8_t& o_output) { @@ -290,8 +256,6 @@ class dimm_module_decoder /// @brief Decodes register output drive strength for clock (B side) /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 138 (Bits 1~0) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode b_side_clk_output_driver(uint8_t& o_output) { @@ -303,8 +267,6 @@ class dimm_module_decoder /// @brief Decodes register output drive strength for clock (A side) /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 138 (Bits 3~2) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode a_side_clk_output_driver(uint8_t& o_output) { @@ -316,8 +278,6 @@ class dimm_module_decoder /// @brief Decodes register output drive strength for data buffer control (BCOM, BODT, BKCE) /// @param[out] o_output encoded drive strength /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 138 (Bit 4) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode bcom_bcke_bodt_drive_strength(uint8_t& o_output) { @@ -330,8 +290,6 @@ class dimm_module_decoder /// @brief Decodes register output drive strength for data buffer control (BCK) /// @param[out] o_output encoded drive strength /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 138 (Bit 5) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode bck_output_drive_strength(uint8_t& o_output) { @@ -343,8 +301,6 @@ class dimm_module_decoder /// @brief Decodes RCD output slew rate control /// @param[out] o_output encoded drive strength /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 138 (Bit 6) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode slew_rate_control(uint8_t& o_output) { @@ -356,8 +312,6 @@ class dimm_module_decoder /// @brief Decodes data buffer revision number /// @param[out] o_output revision number /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 139 (Bits 7~0) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode data_buffer_rev(uint8_t& o_output) { @@ -369,8 +323,6 @@ class dimm_module_decoder /// @brief Decodes DRAM VrefDQ for Package Rank 0 /// @param[out] o_output encoding of MR6 A5:A0 in JESD790-4 spec /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 140 (Bits 5~0) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode dram_vref_dq_rank0(uint8_t& o_output) { @@ -382,8 +334,6 @@ class dimm_module_decoder /// @brief Decodes DRAM VrefDQ for Package Rank 1 /// @param[out] o_output encoding of MR6 A5:A0 in JESD790-4 spec /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 141 (Bits 5~0) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode dram_vref_dq_rank1(uint8_t& o_output) { @@ -395,8 +345,6 @@ class dimm_module_decoder /// @brief Decodes DRAM VrefDQ for Package Rank 2 /// @param[out] o_output encoding of MR6 A5:A0 in JESD790-4 spec /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 142 (Bits 5~0) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode dram_vref_dq_rank2(uint8_t& o_output) { @@ -408,8 +356,6 @@ class dimm_module_decoder /// @brief Decodes DRAM VrefDQ for Package Rank 3 /// @param[out] o_output encoding of MR6 A5:A0 in JESD790-4 spec /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 143 (Bits 5~0) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode dram_vref_dq_rank3(uint8_t& o_output) { @@ -421,8 +367,6 @@ class dimm_module_decoder /// @brief Decodes data buffer VrefDQ for DRAM interface /// @param[out] o_output encoding of F5BC6x in DDR4DB01 spec /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 144 (Bits 5~0) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode data_buffer_vref_dq(uint8_t& o_output) { @@ -436,8 +380,6 @@ class dimm_module_decoder /// @param[in] i_dimm_speed the dimm speed in MT/s /// @param[out] o_output encoding of F5BC6x in /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 145 - 147 (Bits 6~4) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode data_buffer_mdq_drive_strength(const uint64_t i_dimm_speed, uint8_t& o_output) { @@ -451,8 +393,6 @@ class dimm_module_decoder /// @param[in] i_dimm_speed the dimm speed in MT/s /// @param[out] o_output encoding of F5BC6x in /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 145 - 147 (Bits 2~0) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode data_buffer_mdq_rtt(const uint64_t i_dimm_speed, uint8_t& o_output) { @@ -466,8 +406,6 @@ class dimm_module_decoder /// @param[in] i_dimm_speed the dimm speed in MT/s /// @param[out] o_output DRAM drive strength (in ohms) /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 148 (Bits 5~0) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode dram_drive_strength(const uint64_t i_dimm_speed, uint8_t& o_output) { @@ -481,8 +419,6 @@ class dimm_module_decoder /// @param[in] i_dimm_speed the dimm speed in MT/s /// @param[out] o_output ODT termination strength (in ohms) /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 149 - 151 (Bits 2~0) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode dram_rtt_nom(const uint64_t i_dimm_speed, uint8_t& o_output) { @@ -496,8 +432,6 @@ class dimm_module_decoder /// @param[in] i_dimm_speed the dimm speed in MT/s /// @param[out] o_output ODT termination strength (in ohms) /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 149 - 151 (Bits 5~3) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode dram_rtt_wr(const uint64_t i_dimm_speed, uint8_t& o_output) { @@ -511,8 +445,6 @@ class dimm_module_decoder /// @param[in] i_dimm_speed the dimm speed in MT/s /// @param[out] o_output ODT termination strength (in ohms) /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 152 - 154 (Bits 2~0) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode dram_rtt_park_ranks0_1(const uint64_t i_dimm_speed, uint8_t& o_output) { @@ -526,8 +458,6 @@ class dimm_module_decoder /// @param[in] i_dimm_speed the dimm speed in MT/s /// @param[out] o_output ODT termination strength (in ohms) /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 152 - 154 (Bits 5~3) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode dram_rtt_park_ranks2_3(const uint64_t i_dimm_speed, uint8_t& o_output) { @@ -539,8 +469,6 @@ class dimm_module_decoder /// @brief Decodes VrefDQ range for DRAM interface range /// @param[out] o_output spd encoding /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 155 (Bits 3~0) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode dram_vref_dq_range(uint8_t& o_output) { @@ -552,8 +480,6 @@ class dimm_module_decoder /// @brief Decodes data buffer VrefDQ range for DRAM interface range /// @param[out] o_output spd encoding /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 155 (Bit 4) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode data_buffer_vref_dq_range(uint8_t& o_output) { @@ -565,8 +491,6 @@ class dimm_module_decoder /// @brief Decodes data buffer gain adjustment /// @param[out] o_output spd encoding /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 156 (Bit 0) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode data_buffer_gain_adjustment(uint8_t& o_output) { @@ -578,8 +502,6 @@ class dimm_module_decoder /// @brief Decodes data buffer Decision Feedback Equalization (DFE) /// @param[out] o_output spd encoding /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 156 (Bit 1) - /// @note Item JEDEC Standard No. 21-C /// virtual fapi2::ReturnCode data_buffer_dfe(uint8_t& o_output) { @@ -590,6 +512,7 @@ class dimm_module_decoder /// /// @brief data structure for byte fields +/// @note holds byte index, start bit and length of decoded field /// struct field_t { diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/rcw_settings.H b/src/import/generic/memory/lib/spd/common/rcw_settings.H index a95e485d0..57527dbe5 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/rcw_settings.H +++ b/src/import/generic/memory/lib/spd/common/rcw_settings.H @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/spd/common/rcw_settings.H $ */ +/* $Source: src/import/generic/memory/lib/spd/common/rcw_settings.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ diff --git a/src/import/generic/memory/lib/spd/common/spd_decoder_base.H b/src/import/generic/memory/lib/spd/common/spd_decoder_base.H new file mode 100644 index 000000000..a1aee784e --- /dev/null +++ b/src/import/generic/memory/lib/spd/common/spd_decoder_base.H @@ -0,0 +1,848 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/generic/memory/lib/spd/common/spd_decoder_base.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file spd_decoder.H +/// @brief SPD decoder declarations +/// +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: HB:FSP + +#ifndef _MSS_BASE_SPD_DECODER_H_ +#define _MSS_BASE_SPD_DECODER_H_ + +#include <cstdint> +#include <memory> +#include <fapi2.H> + +#include <generic/memory/lib/spd/common/dimm_module_decoder.H> +#include <generic/memory/lib/spd/common/rcw_settings.H> + +namespace mss +{ +namespace spd +{ + +/// +/// @class decoder +/// @brief Base SPD DRAM decoder +/// +class base_decoder +{ + protected: + + /// + /// @brief Helper function that turns Logical ranks in Primary SDRAM type + /// @param[out] o_logical_ranks number of logical ranks + /// @return fapi2::FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode prim_sdram_logical_ranks( uint8_t& o_logical_ranks ) + { + o_logical_ranks = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Helper functions that returns Logical ranks in Secondary SDRAM type + /// @param[out] o_logical_ranks number of logical ranks + /// @return fapi2::FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode sec_sdram_logical_ranks( uint8_t& o_logical_ranks ) + { + o_logical_ranks = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + public: + const fapi2::Target<fapi2::TARGET_TYPE_DIMM> iv_target; + std::shared_ptr<dimm_module_decoder> iv_module_decoder; + std::vector<uint8_t> iv_spd_data; + rcw_settings iv_raw_card; + + // Default constructor deleted + base_decoder() = delete; + + /// + /// @brief ctor + /// @param[in] i_target dimm target + /// @param[in] i_spd_data SPD data vector + /// @param[in] i_module_decoder shared_ptr to dimm module decoder + /// @param[in] i_raw_card raw pointer to rcd data + /// + base_decoder(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::vector<uint8_t>& i_spd_data, + const std::shared_ptr<dimm_module_decoder>& i_module_decoder, + const rcw_settings& i_raw_card) + : iv_target(i_target), + iv_module_decoder(i_module_decoder), + iv_spd_data(i_spd_data), + iv_raw_card(i_raw_card) + {} + + /// + /// @brief Default dtor + /// + virtual ~base_decoder() = default; + + ///////////////////////// + // Member Methods + ///////////////////////// + + /// + /// @brief Decodes number of used SPD bytes + /// @param[out] o_value number of SPD bytes used + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode number_of_used_bytes( uint16_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes total number of SPD bytes + /// @param[out] o_value number of total SPD bytes + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode number_of_total_bytes( uint16_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes hybrid media field from SPD + /// @param[out] o_value hybrid media decoding + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode hybrid_media( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes hybrid field from SPD + /// @param[out] o_value hybrid decoding + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode hybrid( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes SDRAM density from SPD + /// @param[out] o_value SDRAM density in GBs + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode sdram_density( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes number of SDRAM banks bits from SPD + /// @param[out] o_value Number of SDRAM bank bits + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode bank_bits( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes number of SDRAM bank groups bits from SPD + /// @param[out] o_value Number of SDRAM bank groups bits + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode bank_group_bits( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes number of SDRAM column address bits + /// @param[out] o_value Number of SDRAM bank bits + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode column_address_bits( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes number of SDRAM row address bits + /// @param[out] o_value Number of SDRAM bank bits + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode row_address_bits( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Primary SDRAM signal loading + /// @param[out] o_value Number of SDRAM bank bits + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode prim_sdram_signal_loading( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Primary SDRAM die count + /// @param[out] o_value Number of SDRAM bank bits + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode prim_sdram_die_count( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Primary SDRAM package type + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode prim_sdram_package_type( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decode SDRAM Maximum activate count + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode maximum_activate_count( uint32_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decode SDRAM Maximum activate window (multiplier), tREFI uknown at this point + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode maximum_activate_window_multiplier( uint32_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decode Post package repair (PPR) + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode post_package_repair( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decode Soft post package repair (soft PPR) + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode soft_post_package_repair( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Secondary SDRAM signal loading + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode sec_sdram_signal_loading( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Secondary DRAM Density Ratio + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode sec_dram_density_ratio( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Secondary SDRAM die count + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode sec_sdram_die_count( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Secondary SDRAM package type + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode sec_sdram_package_type( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decode Module Nominal Voltage, VDD + /// @param[out] o_value enum representing if 1.2V is operable + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode operable_nominal_voltage( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decode Module Nominal Voltage, VDD + /// @param[out] o_value enum representing if 1.2V is endurant + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode endurant_nominal_voltage( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + /// + /// @brief Decodes SDRAM device width + /// @param[out] o_value device width in bits + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode device_width( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes number of package ranks per DIMM + /// @param[out] o_value number of package ranks per DIMM + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode num_package_ranks_per_dimm( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Rank Mix + /// @param[out] o_value rank mix value from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode rank_mix( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes primary bus width + /// @param[out] o_value primary bus width in bits + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode prim_bus_width( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes bus width extension + /// @param[out] o_value bus width extension in bits + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode bus_width_extension( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decode Module Thermal Sensor + /// @param[out] o_value thermal sensor value from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode thermal_sensor( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decode Extended Base Module Type + /// @param[out] o_value extended base module type value from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode extended_base_module_type( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decode Fine Timebase + /// @param[out] o_value fine_timebase from SPD in picoseconds + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode fine_timebase( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decode Medium Timebase + /// @param[out] o_value fine_timebase from SPD in picoseconds + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode medium_timebase( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// + /// @brief Decodes SDRAM Minimum Cycle Time in MTB + /// @param[out] o_value tCKmin in MTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode min_tck( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes SDRAM Maximum Cycle Time in MTB + /// @param[out] o_value tCKmax in MTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode max_tck( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decode CAS Latencies Supported + /// @param[out] o_value bitmap of supported CAS latencies + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode supported_cas_latencies( uint64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes SDRAM Minimum CAS Latency Time in MTB + /// @param[out] o_value tAAmin in MTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode min_taa( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes SDRAM Minimum RAS to CAS Delay Time in MTB + /// @param[out] o_value tRCDmin in MTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode min_trcd( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes SDRAM Minimum Row Precharge Delay Time in MTB + /// @param[out] o_value tRPmin in MTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode min_trp( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes SDRAM Minimum Active to Precharge Delay Time in MTB + /// @param[out] o_value tRASmin in MTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode min_tras( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes SDRAM Minimum Active to Active/Refresh Delay Time in MTB + /// @param[out] o_value tRCmin in MTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode min_trc( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes SDRAM Minimum Refresh Recovery Delay Time 1 + /// @param[out] o_value tRFC1min in MTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode min_trfc1( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes SDRAM Minimum Refresh Recovery Delay Time 2 + /// @param[out] o_value tRFC2min in MTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode min_trfc2( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes SDRAM Minimum Refresh Recovery Delay Time 4 + /// @param[out] o_value tRFC4min in MTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode min_trfc4( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes SDRAM Minimum Four Activate Window Delay Time + /// @param[out] o_value tFAWmin in MTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode min_tfaw( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Minimum Activate to Activate Delay Time - Different Bank Group + /// @param[out] o_value tRRD_Smin MTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode min_trrd_s( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Minimum Activate to Activate Delay Time - Same Bank Group + /// @param[out] o_value tRRD_Lmin MTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode min_trrd_l( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Minimum CAS to CAS Delay Time - Same Bank Group + /// @param[out] o_value tCCD_Lmin MTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode min_tccd_l( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Minimum Write Recovery Time + /// @param[out] o_value tWRmin in MTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode min_twr( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Minimum Write to Read Time - Different Bank Group + /// @param[out] o_value tWRT_Smin in MTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode min_twtr_s( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Minimum Write to Read Time - Same Bank Group + /// @param[out] o_value tWRT_Lmin in MTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode min_twtr_l( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Fine Offset for Minimum CAS to CAS Delay Time - Same Bank Group + /// @param[out] o_value tCCD_Lmin offset in FTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode fine_offset_min_tccd_l( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Fine Offset for Minimum Activate to Activate Delay Time - Same Bank Group + /// @param[out] o_value tRRD_Lmin offset in FTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode fine_offset_min_trrd_l( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Fine Offset for Minimum Activate to Activate Delay Time - Different Bank Group + /// @param[out] o_value tRRD_Smin offset in FTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode fine_offset_min_trrd_s( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Fine Offset for Minimum Active to Active/Refresh Delay Time + /// @param[out] o_value tRCmin offset in FTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode fine_offset_min_trc( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Fine Offset for Minimum Row Precharge Delay Time + /// @param[out] o_value tRPmin offset in FTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode fine_offset_min_trp( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Fine Offset for SDRAM Minimum RAS to CAS Delay Time + /// @param[out] o_value tRCDmin offset in FTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode fine_offset_min_trcd( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Fine Offset for SDRAM Minimum CAS Latency Time + /// @param[out] o_value tAAmin offset in FTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode fine_offset_min_taa( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Fine Offset for SDRAM Maximum Cycle Time + /// @param[out] o_value tCKmax offset in FTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode fine_offset_max_tck( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Fine Offset for SDRAM Minimum Cycle Time + /// @param[out] o_value tCKmin offset in FTB units + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode fine_offset_min_tck( int64_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Cyclical Redundancy Code (CRC) for Base Configuration Section + /// @param[out] o_value crc value from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cyclical_redundancy_code( uint16_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes module manufacturer ID code + /// @param[out] o_output module manufacturing id code + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode module_manufacturer_id_code( uint16_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Module Manufacturing Location + /// @param[out] o_value uint8_t identifier for manufacturing location of memory module + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode module_manufacturing_location( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodesmodule manufacturing date + /// @param[out] o_value the 2 byte date of manufacturing in BCD format + /// @return FAPI2_RC_SUCCESS if okay + virtual fapi2::ReturnCode module_manufacturing_date( uint16_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes module's unique serial number + /// @param[out] o_value module's serial number + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode module_serial_number( uint32_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Module Revision Code + /// @param[out] o_value uint8_t identifier for revision code + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode module_revision_code( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes DRAM Manufacturer ID code + /// @param[out] o_value dram manufacturing id code + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode dram_manufacturer_id_code( uint16_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes DRAM Stepping + /// @param[out] o_value uint8_t DRAM Stepping val + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode dram_stepping( uint8_t& o_value ) + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Returns Logical ranks per DIMM + /// @param[out] o_logical_ranks number of logical ranks + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode logical_ranks_per_dimm( uint8_t& o_logical_rank_per_dimm ) + { + o_logical_rank_per_dimm = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + +};// decoder + +}// spd +}// mss + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/lrdimm/lrdimm_decoder.H b/src/import/generic/memory/lib/spd/lrdimm/ddr4/lrdimm_decoder_ddr4.H index 5db105e29..32d4c6245 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/lrdimm/lrdimm_decoder.H +++ b/src/import/generic/memory/lib/spd/lrdimm/ddr4/lrdimm_decoder_ddr4.H @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/spd/lrdimm/lrdimm_decoder.H $ */ +/* $Source: src/import/generic/memory/lib/spd/lrdimm/ddr4/lrdimm_decoder_ddr4.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ @@ -39,7 +39,7 @@ #include <fapi2.H> #include <vector> -#include <lib/spd/common/dimm_module_decoder.H> +#include <generic/memory/lib/spd/common/dimm_module_decoder.H> namespace mss { @@ -276,7 +276,7 @@ class decoder_v1_0 : public dimm_module_decoder virtual fapi2::ReturnCode ca_signal_output_driver(uint8_t& o_output) override; /// - /// @brief Decodes register output drive strength for chip select (CS) signal + /// @brief Decodes register output drive strength for control signal (CS) signal /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 137 (Bits 6~7) @@ -527,7 +527,7 @@ class decoder_v1_1 : public decoder_v1_0 virtual fapi2::ReturnCode odt_signal_output_driver(uint8_t& o_output) override; /// - /// @brief Decodes register output drive strength for chip select (CS) signal + /// @brief Decodes register output drive strength for control signal (CS) signal /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 137 (Bits 6~7) diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/lrdimm/lrdimm_decoder_v1_0.C b/src/import/generic/memory/lib/spd/lrdimm/ddr4/lrdimm_decoder_ddr4_v1_0.C index 6a143def5..00192a229 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/lrdimm/lrdimm_decoder_v1_0.C +++ b/src/import/generic/memory/lib/spd/lrdimm/ddr4/lrdimm_decoder_ddr4_v1_0.C @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/spd/lrdimm/lrdimm_decoder_v1_0.C $ */ +/* $Source: src/import/generic/memory/lib/spd/lrdimm/ddr4/lrdimm_decoder_ddr4_v1_0.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ @@ -40,9 +40,9 @@ #include <fapi2.H> // mss lib -#include <lib/spd/lrdimm/lrdimm_decoder.H> -#include <lib/spd/common/spd_decoder.H> -#include <lib/utils/checker.H> +#include <generic/memory/lib/spd/lrdimm/ddr4/lrdimm_decoder_ddr4.H> +#include <generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H> +#include <generic/memory/lib/spd/spd_checker.H> #include <generic/memory/lib/utils/c_str.H> #include <generic/memory/lib/utils/find.H> @@ -683,7 +683,7 @@ fapi_try_exit: } /// -/// @brief Decodes register output drive strength for chip select (CS) signal +/// @brief Decodes register output drive strength for control signal (CS) signal /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 137 (bit 6~7) diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/lrdimm/lrdimm_decoder_v1_1.C b/src/import/generic/memory/lib/spd/lrdimm/ddr4/lrdimm_decoder_ddr4_v1_1.C index 3f06d87d4..32bc97940 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/lrdimm/lrdimm_decoder_v1_1.C +++ b/src/import/generic/memory/lib/spd/lrdimm/ddr4/lrdimm_decoder_ddr4_v1_1.C @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/spd/lrdimm/lrdimm_decoder_v1_1.C $ */ +/* $Source: src/import/generic/memory/lib/spd/lrdimm/ddr4/lrdimm_decoder_ddr4_v1_1.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ @@ -40,9 +40,9 @@ #include <fapi2.H> // mss lib -#include <lib/spd/lrdimm/lrdimm_decoder.H> -#include <lib/spd/common/spd_decoder.H> -#include <lib/utils/checker.H> +#include <generic/memory/lib/spd/lrdimm/ddr4/lrdimm_decoder_ddr4.H> +#include <generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H> +#include <generic/memory/lib/spd/spd_checker.H> #include <generic/memory/lib/utils/c_str.H> #include <generic/memory/lib/utils/find.H> @@ -164,7 +164,7 @@ fapi_try_exit: } /// -/// @brief Decodes register output drive strength for chip select (CS) signal +/// @brief Decodes register output drive strength for control signal (CS) signal /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 137 (Bits 6~7) diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/lrdimm/lrdimm_decoder_v1_2.C b/src/import/generic/memory/lib/spd/lrdimm/ddr4/lrdimm_decoder_ddr4_v1_2.C index 692c0fca5..4e223cb19 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/lrdimm/lrdimm_decoder_v1_2.C +++ b/src/import/generic/memory/lib/spd/lrdimm/ddr4/lrdimm_decoder_ddr4_v1_2.C @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/spd/lrdimm/lrdimm_decoder_v1_2.C $ */ +/* $Source: src/import/generic/memory/lib/spd/lrdimm/ddr4/lrdimm_decoder_ddr4_v1_2.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ @@ -40,9 +40,9 @@ #include <fapi2.H> // mss lib -#include <lib/spd/lrdimm/lrdimm_decoder.H> -#include <lib/spd/common/spd_decoder.H> -#include <lib/utils/checker.H> +#include <generic/memory/lib/spd/lrdimm/ddr4/lrdimm_decoder_ddr4.H> +#include <generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H> +#include <generic/memory/lib/spd/spd_checker.H> #include <generic/memory/lib/utils/c_str.H> #include <generic/memory/lib/utils/find.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/lrdimm/lrdimm_raw_cards.C b/src/import/generic/memory/lib/spd/lrdimm/ddr4/lrdimm_raw_cards.C index 9794bb4d6..f4b943b2c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/lrdimm/lrdimm_raw_cards.C +++ b/src/import/generic/memory/lib/spd/lrdimm/ddr4/lrdimm_raw_cards.C @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/spd/lrdimm/lrdimm_raw_cards.C $ */ +/* $Source: src/import/generic/memory/lib/spd/lrdimm/ddr4/lrdimm_raw_cards.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ @@ -41,7 +41,7 @@ #include <fapi2.H> // mss lib -#include <lib/spd/lrdimm/lrdimm_raw_cards.H> +#include <generic/memory/lib/spd/lrdimm/ddr4/lrdimm_raw_cards.H> namespace mss { diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/lrdimm/lrdimm_raw_cards.H b/src/import/generic/memory/lib/spd/lrdimm/ddr4/lrdimm_raw_cards.H index e6f4cf8db..e3a99698d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/lrdimm/lrdimm_raw_cards.H +++ b/src/import/generic/memory/lib/spd/lrdimm/ddr4/lrdimm_raw_cards.H @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/spd/lrdimm/lrdimm_raw_cards.H $ */ +/* $Source: src/import/generic/memory/lib/spd/lrdimm/ddr4/lrdimm_raw_cards.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,7 +39,7 @@ #include <fapi2.H> #include <cstdint> #include <vector> -#include <lib/spd/common/rcw_settings.H> +#include <generic/memory/lib/spd/common/rcw_settings.H> namespace mss { diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/rdimm/rdimm_decoder.H b/src/import/generic/memory/lib/spd/rdimm/ddr4/rdimm_decoder_ddr4.H index ac208e53c..effc7f983 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/rdimm/rdimm_decoder.H +++ b/src/import/generic/memory/lib/spd/rdimm/ddr4/rdimm_decoder_ddr4.H @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/spd/rdimm/rdimm_decoder.H $ */ +/* $Source: src/import/generic/memory/lib/spd/rdimm/ddr4/rdimm_decoder_ddr4.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ @@ -37,7 +37,7 @@ #define _MSS_RDIMM_DECODER_H_ #include <fapi2.H> -#include <lib/spd/common/dimm_module_decoder.H> +#include <generic/memory/lib/spd/common/dimm_module_decoder.H> namespace mss { @@ -294,7 +294,7 @@ class rdimm_decoder_v1_0 : public dimm_module_decoder virtual fapi2::ReturnCode ca_signal_output_driver(uint8_t& o_output) override; /// - /// @brief Decodes register output drive strength for chip select (CS) signal + /// @brief Decodes register output drive strength for control signal (CS) signal /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 137 (bit 6~7) @@ -391,7 +391,7 @@ class rdimm_decoder_v1_1 : public rdimm_decoder_v1_0 virtual fapi2::ReturnCode odt_signal_output_driver(uint8_t& o_output) override; /// - /// @brief Decodes register output drive strength for chip select (CS) signal + /// @brief Decodes register output drive strength for control signal (CS) signal /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 137 (bit 6~7) diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/rdimm/rdimm_decoder_v1_0.C b/src/import/generic/memory/lib/spd/rdimm/ddr4/rdimm_decoder_ddr4_v1_0.C index 1ec73a5fd..43eb08c51 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/rdimm/rdimm_decoder_v1_0.C +++ b/src/import/generic/memory/lib/spd/rdimm/ddr4/rdimm_decoder_ddr4_v1_0.C @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/spd/rdimm/rdimm_decoder_v1_0.C $ */ +/* $Source: src/import/generic/memory/lib/spd/rdimm/ddr4/rdimm_decoder_ddr4_v1_0.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ @@ -39,9 +39,9 @@ #include <fapi2.H> // mss lib -#include <lib/spd/rdimm/rdimm_decoder.H> -#include <lib/spd/common/spd_decoder.H> -#include <lib/utils/checker.H> +#include <generic/memory/lib/spd/rdimm/ddr4/rdimm_decoder_ddr4.H> +#include <generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H> +#include <generic/memory/lib/spd/spd_checker.H> #include <generic/memory/lib/utils/c_str.H> #include <generic/memory/lib/utils/find.H> @@ -561,7 +561,7 @@ fapi_try_exit: } /// -/// @brief Decodes register output drive strength for chip select (CS) signal +/// @brief Decodes register output drive strength for control signal (CS) signal /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 137 (bit 6~7) diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/rdimm/rdimm_decoder_v1_1.C b/src/import/generic/memory/lib/spd/rdimm/ddr4/rdimm_decoder_ddr4_v1_1.C index 4eedc21ad..4517de0a7 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/rdimm/rdimm_decoder_v1_1.C +++ b/src/import/generic/memory/lib/spd/rdimm/ddr4/rdimm_decoder_ddr4_v1_1.C @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/spd/rdimm/rdimm_decoder_v1_1.C $ */ +/* $Source: src/import/generic/memory/lib/spd/rdimm/ddr4/rdimm_decoder_ddr4_v1_1.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ @@ -30,9 +30,9 @@ #include <fapi2.H> // mss lib -#include <lib/spd/rdimm/rdimm_decoder.H> -#include <lib/spd/common/spd_decoder.H> -#include <lib/utils/checker.H> +#include <generic/memory/lib/spd/rdimm/ddr4/rdimm_decoder_ddr4.H> +#include <generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H> +#include <generic/memory/lib/spd/spd_checker.H> #include <generic/memory/lib/utils/c_str.H> #include <generic/memory/lib/utils/find.H> @@ -162,7 +162,7 @@ fapi_try_exit: } /// -/// @brief Decodes register output drive strength for chip select (CS) signal +/// @brief Decodes register output drive strength for control signal (CS) signal /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 137 (bit 6~7) diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/rdimm/rdimm_raw_cards.C b/src/import/generic/memory/lib/spd/rdimm/ddr4/rdimm_raw_cards.C index bc49cab7e..0b4e50f02 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/rdimm/rdimm_raw_cards.C +++ b/src/import/generic/memory/lib/spd/rdimm/ddr4/rdimm_raw_cards.C @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/spd/rdimm/rdimm_raw_cards.C $ */ +/* $Source: src/import/generic/memory/lib/spd/rdimm/ddr4/rdimm_raw_cards.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ @@ -41,7 +41,7 @@ #include <fapi2.H> // mss lib -#include <lib/spd/rdimm/rdimm_raw_cards.H> +#include <generic/memory/lib/spd/rdimm/ddr4/rdimm_raw_cards.H> namespace mss { diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/rdimm/rdimm_raw_cards.H b/src/import/generic/memory/lib/spd/rdimm/ddr4/rdimm_raw_cards.H index c756c478d..02c30ba79 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/rdimm/rdimm_raw_cards.H +++ b/src/import/generic/memory/lib/spd/rdimm/ddr4/rdimm_raw_cards.H @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/spd/rdimm/rdimm_raw_cards.H $ */ +/* $Source: src/import/generic/memory/lib/spd/rdimm/ddr4/rdimm_raw_cards.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ @@ -39,7 +39,7 @@ #include <fapi2.H> #include <cstdint> #include <vector> -#include <lib/spd/common/rcw_settings.H> +#include <generic/memory/lib/spd/common/rcw_settings.H> namespace mss { diff --git a/src/import/generic/memory/lib/spd/spd_checker.H b/src/import/generic/memory/lib/spd/spd_checker.H index 77cc902f3..d3a85aaa4 100644 --- a/src/import/generic/memory/lib/spd/spd_checker.H +++ b/src/import/generic/memory/lib/spd/spd_checker.H @@ -22,3 +22,115 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +#ifndef _SPD_CHECKER_H_ +#define _SPD_CHECKER_H_ + +#include <fapi2.H> + +namespace mss +{ +namespace check +{ +namespace spd +{ + +/// +/// @brief Checks conditional passes and implements traces & exits if it fails +/// @tparam T input data of any size +/// @param[in] i_target fapi2 dimm target +/// @param[in] i_conditional conditional that we are testing against +/// @param[in] i_spd_byte_index current SPD byte +/// @param[in] i_spd_data debug data +/// @param[in] i_err_str error string to print out when conditional fails +/// @return ReturnCode +/// +template< typename T > +inline fapi2::ReturnCode fail_for_invalid_value(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const bool i_conditional, + const size_t i_spd_byte_index, + const T i_spd_data, + const char* i_err_str) +{ + FAPI_ASSERT(i_conditional, + fapi2::MSS_BAD_SPD(). + set_VALUE(i_spd_data). + set_BYTE(i_spd_byte_index). + set_DIMM_TARGET(i_target), + "%s %s Byte %d, Data returned: %d.", + c_str(i_target), + i_err_str, + i_spd_byte_index, + i_spd_data); + + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; + +} // fail_for_invalid_value() + +/// +/// @brief Checks conditional passes and implements traces if it fails. No FFDC collected. +/// @tparam T input data of any size +/// @param[in] i_target fapi2 dimm target +/// @param[in] i_conditional that we are testing against +/// @param[in] i_spd_byte_index +/// @param[in] i_spd_data debug data +/// @param[in] i_err_str string to print out when conditional fails +/// @return void +/// +template< typename T > +inline void warn_for_invalid_value(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const bool i_conditional, + const size_t i_spd_byte_index, + const T i_spd_data, + const char* i_err_str) +{ + // Don't print warning conditional if true + if(!i_conditional) + { + FAPI_IMP("%s. %s. Byte %d, Data returned: %d.", + c_str(i_target), + i_err_str, + i_spd_byte_index, + i_spd_data ); + } +}// warn_for_invalid_value + +/// +/// @brief Checks if valid factory parameters are given +/// @param[in] i_target fapi2 dimm target +/// @param[in] i_dimm_type DIMM type enumeration +/// @param[in] i_encoding_rev SPD encoding level rev number +/// @param[in] i_additions_rev SPD additions level rev number +/// @param[in] i_err_str string to print out when conditional fails +/// @return fapi2::ReturnCode +/// +inline fapi2::ReturnCode invalid_factory_sel(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint8_t i_dimm_type, + const uint8_t i_encoding_rev, + const uint8_t i_additions_rev, + const char* i_err_str) +{ + FAPI_ASSERT(false, + fapi2::MSS_INVALID_DIMM_REV_COMBO(). + set_DIMM_TYPE(i_dimm_type). + set_ENCODING_REV(i_encoding_rev). + set_ADDITIONS_REV(i_additions_rev). + set_DIMM_TARGET(i_target), + "%s. %s. Invalid combination for dimm type: %d, rev: %d.%d", + c_str(i_target), + i_err_str, + i_dimm_type, + i_encoding_rev, + i_additions_rev); + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; +}// invalid_factory_sel + +}// spd +}// check +}// mss + +#endif diff --git a/src/import/generic/memory/spd_decoder_base.H b/src/import/generic/memory/spd_decoder_base.H deleted file mode 100644 index d36bdb087..000000000 --- a/src/import/generic/memory/spd_decoder_base.H +++ /dev/null @@ -1,24 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/generic/memory/spd_decoder_base.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ |
