diff options
Diffstat (limited to 'src/import')
6 files changed, 210 insertions, 82 deletions
diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_clear_firs.C b/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_clear_firs.C index a7a5151dd..ab8927381 100644 --- a/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_clear_firs.C +++ b/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_clear_firs.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -48,9 +48,13 @@ // Includes //----------------------------------------------------------------------------- #include <p9_io_xbus_clear_firs.H> +#include <p9_io_xbus_read_erepair.H> #include <p9_io_scom.H> #include <p9_io_regs.H> +#include <p9_xbus_scom_addresses.H> +#include <p9_xbus_scom_addresses_fld.H> + //----------------------------------------------------------------------------- // Definitions //----------------------------------------------------------------------------- @@ -147,3 +151,134 @@ fapi2::ReturnCode io_tx_fir_reset( fapi_try_exit: return fapi2::current_err; } + +/** + * @brief This function reads the bad lane data of a EDI+ Xbus + * @param[in] i_target FAPI2 Target + * @param[in] i_clock_group Clock Group + * @param[out] o_bad_lane_data Bit representation of each lane in the clock group + * @retval ReturnCode + */ +fapi2::ReturnCode p9_io_xbus_get_bad_lane_data( + const fapi2::Target < fapi2::TARGET_TYPE_XBUS >& i_target, + const uint8_t& i_clock_group, + uint32_t& o_bad_lane_data) +{ + FAPI_IMP("I/O EDI+ Xbus Get Current Bad Lane Data :: Start"); + const uint8_t LN0 = 0; + uint64_t l_data = 0; + std::vector<uint8_t> l_bad_lanes; + + FAPI_DBG("Read Bad Lane Vector 0 15"); + FAPI_TRY(io::read(EDIP_RX_LANE_BAD_VEC_0_15, i_target, i_clock_group, LN0, l_data), + "rmw to edip_rx_lane_bad_vec_0_15 failed."); + + o_bad_lane_data = (io::get(EDIP_RX_LANE_BAD_VEC_0_15, l_data) << 8) & 0x00FFFF00; + + FAPI_DBG("Read Bad Lane Vector 16 23"); + FAPI_TRY(io::read(EDIP_RX_LANE_BAD_VEC_16_23, i_target, i_clock_group, LN0, l_data), + "rmw to edip_rx_lane_bad_vec_16_23 failed."); + + o_bad_lane_data |= (io::get(EDIP_RX_LANE_BAD_VEC_16_23, l_data) & 0x000000FF); + + + FAPI_DBG("Call xbus read erepair"); + FAPI_TRY(p9_io_xbus_read_erepair(i_target, i_clock_group, l_bad_lanes)); + + for(auto bad_lane : l_bad_lanes) + { + o_bad_lane_data |= (0x1 << (23 - bad_lane)); + } + +fapi_try_exit: + FAPI_IMP("I/O EDI+ Xbus Get Current Bad Lane Data :: Exit"); + return fapi2::current_err; +} + +/** + * @brief Clears PHY Rx/Tx FIRs on the XBUS(EDI+) specified target. The FIRs + * are cleared by toggling a rx & tx fir reset bit. + * @param[in] i_target FAPI2 Target + * @retval ReturnCode + */ +fapi2::ReturnCode p9_io_xbus_erepair_cleanup( + const fapi2::Target < fapi2::TARGET_TYPE_XBUS >& i_target) +{ + const uint8_t MAX_CLOCK_GROUPS = 2; + bool l_clear_pb_spare_deployed = true; + uint32_t l_grp0_pre_bad_lane_data = 0; + uint32_t l_grp1_pre_bad_lane_data = 0; + uint32_t l_pre_bad_lane_data = 0; + uint32_t l_post_bad_lane_data = 0; + FAPI_IMP("I/O Start Xbus Clear FIRs"); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_XBUS_GRP0_PRE_BAD_LANE_DATA, + i_target, l_grp0_pre_bad_lane_data)); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_XBUS_GRP1_PRE_BAD_LANE_DATA, + i_target, l_grp1_pre_bad_lane_data)); + + for (uint8_t l_group = 0; l_group < MAX_CLOCK_GROUPS; ++l_group) + { + // Get attribute of pre bad lane data + FAPI_IMP("Get Pre Bad Lane Data"); + + if (l_group == 0) + { + l_pre_bad_lane_data = l_grp0_pre_bad_lane_data; + } + else + { + l_pre_bad_lane_data = l_grp1_pre_bad_lane_data; + } + + + // Get current bad lane data + // - bad_lane_vector AND bad_lane_code + FAPI_IMP("Get Current Bad Lane Data"); + FAPI_TRY(p9_io_xbus_get_bad_lane_data(i_target, l_group, l_post_bad_lane_data)); + + FAPI_IMP("Compare Bad Lane Data"); + + if (l_pre_bad_lane_data == l_post_bad_lane_data) + { + FAPI_DBG("I/O EDI+ Xbus Pre/Post Bad Lane Data Match"); + + // If the entire bad lane vector equals 0, then we don't need to clear + // any firs. + if (l_pre_bad_lane_data != 0) + { + FAPI_DBG("I/O EDI+ Xbus Clearing PG Firs"); + + FAPI_TRY(io_tx_fir_reset(i_target, l_group), "Tx Reset Failed"); + FAPI_TRY(io_rx_fir_reset(i_target, l_group), "Rx Reset Failed"); + + } + } + else + { + FAPI_DBG("Bad lane data does NOT match."); + l_clear_pb_spare_deployed = false; + } + } + + // Clearing of the Spare Lane Deployed FIR when: + // - the pre/post bad lane data match on both groups. (l_clear_pb_spare_deployed) + // - AND if either groups have nonzero bad lane data + if (l_clear_pb_spare_deployed && + ((l_grp0_pre_bad_lane_data != 0x0) || (l_grp1_pre_bad_lane_data != 0x0)) ) + { + fapi2::buffer<uint64_t> l_data; + fapi2::buffer<uint64_t> l_mask; + + // Clear BUS0_SPARE_DEPLOYED (Bit 9). + l_data.clearBit<XBUS_1_FIR_REG_RX_BUS0_SPARE_DEPLOYED>(); + l_mask.setBit<XBUS_1_FIR_REG_RX_BUS0_SPARE_DEPLOYED>(); + FAPI_TRY(fapi2::putScomUnderMask(i_target, XBUS_FIR_REG, l_data, l_mask)); + + } + +fapi_try_exit: + FAPI_IMP("I/O End Xbus Clear FIRs"); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_clear_firs.H b/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_clear_firs.H index de6e1d807..1e1e18328 100644 --- a/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_clear_firs.H +++ b/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_clear_firs.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -48,6 +48,10 @@ typedef fapi2::ReturnCode (*p9_io_xbus_clear_firs_FP_t) (const fapi2::Target < fapi2::TARGET_TYPE_XBUS >&, const uint8_t&); +typedef fapi2::ReturnCode (*p9_io_xbus_erepair_cleanup_FP_t) +(const fapi2::Target < fapi2::TARGET_TYPE_XBUS >&); + + extern "C" { @@ -60,7 +64,17 @@ extern "C" */ fapi2::ReturnCode p9_io_xbus_clear_firs( const fapi2::Target < fapi2::TARGET_TYPE_XBUS >& i_target, - const uint8_t& i_clock_group ); + const uint8_t& i_clock_group); + + /** + * @brief Clears PHY Rx/Tx FIRs on the XBUS(EDI+) specified target. The FIRs + * are cleared by toggling a rx & tx fir reset bit. + * @param[in] i_target FAPI2 Target + * @retval ReturnCode + */ + fapi2::ReturnCode p9_io_xbus_erepair_cleanup ( + const fapi2::Target < fapi2::TARGET_TYPE_XBUS >& i_target); + } // extern "C" diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_clear_firs.mk b/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_clear_firs.mk index a6a212e16..e4d05594e 100644 --- a/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_clear_firs.mk +++ b/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_clear_firs.mk @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2015,2016 +# Contributors Listed Below - COPYRIGHT 2015,2018 # [+] International Business Machines Corp. # # @@ -23,4 +23,5 @@ # # IBM_PROLOG_END_TAG PROCEDURE=p9_io_xbus_clear_firs +OBJS+=p9_io_xbus_read_erepair.o $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_linktrain.C b/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_linktrain.C index bd866eed7..25084e2eb 100644 --- a/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_linktrain.C +++ b/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_linktrain.C @@ -791,77 +791,40 @@ fapi_try_exit: } /** - * @brief Reads bad lane vector data from the - * passed target and stores the data in the vector. + * @brief Reads and Sets bad lane vector data from the + * passed target and stores the data in an attribute. * @param[in] i_target Fapi2 Target * @param[in] i_group Clock Group - * @param[out] o_data Data of bad lane vector data * @retval ReturnCode */ -fapi2::ReturnCode get_bad_lane_data( +fapi2::ReturnCode set_bad_lane_data( const XBUS_TGT i_tgt, - const uint8_t i_grp, - uint32_t& o_data ) + const uint8_t i_grp) { FAPI_IMP( "P9 I/O EDI+ Xbus Entering" ); - const uint8_t LN0 = 0; - uint64_t l_data = 0; + const uint8_t LN0 = 0; + uint64_t l_data = 0; + uint32_t l_bad_lane_data = 0; FAPI_TRY( io::read( EDIP_RX_LANE_BAD_VEC_0_15, i_tgt, i_grp, LN0, l_data ), "rmw to edip_rx_lane_bad_vec_0_15 failed." ); - o_data = ( io::get( EDIP_RX_LANE_BAD_VEC_0_15, l_data ) << 8 ) & 0x00FFFF00; + l_bad_lane_data = ( io::get( EDIP_RX_LANE_BAD_VEC_0_15, l_data ) << 8 ) & 0x00FFFF00; FAPI_TRY( io::read( EDIP_RX_LANE_BAD_VEC_16_23, i_tgt, i_grp, LN0, l_data ), "rmw to edip_rx_lane_bad_vec_16_23 failed." ); - o_data |= ( io::get( EDIP_RX_LANE_BAD_VEC_16_23, l_data ) & 0x000000FF ); - -fapi_try_exit: - FAPI_IMP( "P9 I/O EDI+ Xbus Exiting" ); - return fapi2::current_err; -} + l_bad_lane_data |= ( io::get( EDIP_RX_LANE_BAD_VEC_16_23, l_data ) & 0x000000FF ); -/** - * @brief Copmares the bad lane vector pre and post training. If the data is - * the same, then we will want to clear the firs, since the firs have already - * been recorded. - * @param[in] i_tgt Fapi2 Target - * @param[in] i_grp Clock Group - * @param[out] o_data Data Vector of bad lane vector data - * @retval ReturnCode - */ -fapi2::ReturnCode check_bad_lane_data( - const XBUS_TGT i_tgt, - const uint8_t i_grp, - uint32_t i_pre_bad_lane_data, - uint32_t i_post_bad_lane_data ) -{ - FAPI_IMP( "P9 I/O EDI+ Xbus Entering" ); - const uint8_t LN0 = 0; - uint64_t l_data = 0; - - // If the bad lane vector matches pre to post training, then the same bad - // lanes that were previously found, were found again. These bad lanes have - // already been reported. So we will clear the first related to these bad - // lanes - if( i_pre_bad_lane_data == i_post_bad_lane_data ) + if (i_grp == 0) { - FAPI_DBG( "I/O EDI+ Xbus Pre/Post Bad Lane Data Match" ); - - // If the entire bad lane vector equals 0, then we don't need to clear - // any firs. - if( i_pre_bad_lane_data != 0 ) - { - FAPI_DBG( "I/O EDI+ Xbus Clearing Firs" ); - - FAPI_TRY( p9_io_xbus_clear_firs( i_tgt, i_grp ) ); - - // Clear BUS0_SPARE_DEPLOYED ( Bit 9 ). - FAPI_TRY( io::read( EDIP_SCOM_FIR_PB, i_tgt, i_grp, LN0, l_data ) ); - l_data &= 0xFF7FFFFFFFFFFFFFull; - FAPI_TRY( io::write( EDIP_SCOM_FIR_PB, i_tgt, i_grp, LN0, l_data ) ); - } + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_IO_XBUS_GRP0_PRE_BAD_LANE_DATA, + i_tgt, l_bad_lane_data)); + } + else + { + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_IO_XBUS_GRP1_PRE_BAD_LANE_DATA, + i_tgt, l_bad_lane_data)); } fapi_try_exit: @@ -869,7 +832,6 @@ fapi_try_exit: return fapi2::current_err; } - /** * @brief A HWP that runs on every link of the XBUS(EDI+) * @param[in] i_mode Linktraining Mode @@ -886,10 +848,6 @@ fapi2::ReturnCode p9_io_xbus_linktrain( FAPI_IMP( "p9_io_xbus_linktrain: P9 I/O EDI+ Xbus Entering" ); XBUS_TGT l_mtgt; XBUS_TGT l_stgt; - uint32_t l_m_pre_bad_data = 0; - uint32_t l_m_post_bad_data = 0; - uint32_t l_s_pre_bad_data = 0; - uint32_t l_s_post_bad_data = 0; char l_tgt_str[fapi2::MAX_ECMD_STRING_LEN]; char l_ctgt_str[fapi2::MAX_ECMD_STRING_LEN]; @@ -912,10 +870,12 @@ fapi2::ReturnCode p9_io_xbus_linktrain( // Record the Bad Lane Vectors Prior to link training. - FAPI_TRY( get_bad_lane_data( l_mtgt, i_grp, l_m_pre_bad_data ), - "Pre Training: Get Bad Lane Vector Failed on Master" ); - FAPI_TRY( get_bad_lane_data( l_stgt, i_grp, l_s_pre_bad_data ), - "Pre Training: Get Bad Lane Vector Failed on Slave" ); + FAPI_TRY(set_bad_lane_data(l_mtgt, i_grp), + "Pre Training: Get Bad Lane Vector Failed on Master"); + + + FAPI_TRY(set_bad_lane_data(l_stgt, i_grp), + "Pre Training: Get Bad Lane Vector Failed on Slave"); // Clock Serializer Init -- isn't strictly necessary but does line up the @@ -942,21 +902,6 @@ fapi2::ReturnCode p9_io_xbus_linktrain( // "tx_serializer_sync_power_off Failed."); // << HW390103 -- Leave Tx Unload Clock Disable Off - // Record the Bad Lane Vectors after link training. - FAPI_TRY( get_bad_lane_data( l_mtgt, i_grp, l_m_post_bad_data ), - "Post Training: Get Bad Lane Vector Failed on Master" ); - FAPI_TRY( get_bad_lane_data( l_stgt, i_grp, l_s_post_bad_data ), - "Post Training: Get Bad Lane Vector Failed on Master" ); - - - // Check to see if the bad lanes match the bad lanes prior to link training. - // If so, then that error has already been logged and we can clear the firs. - FAPI_TRY( check_bad_lane_data( l_mtgt, i_grp, l_m_pre_bad_data, l_m_post_bad_data ), - "Post Training: Evaluate Firs Failed on Master" ); - FAPI_TRY( check_bad_lane_data( l_stgt, i_grp, l_s_pre_bad_data, l_s_post_bad_data ), - "Post Training: Evaluate Firs Failed on Slave" ); - - fapi_try_exit: FAPI_IMP( "p9_io_xbus_linktrain: P9 I/O EDI+ Xbus Exiting" ); return fapi2::current_err; diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_io_xbus_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_io_xbus_attributes.xml index d219b2c62..27f9910a0 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/p9_io_xbus_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_io_xbus_attributes.xml @@ -139,6 +139,30 @@ <platInit/> </attribute> <!-- ********************************************************************** --> +<attribute> + <id>ATTR_IO_XBUS_GRP0_PRE_BAD_LANE_DATA</id> + <targetType>TARGET_TYPE_XBUS</targetType> + <description> + Pre-training bad lane data vector. This data is persistant from previous + IPLs so that the interface does not need to re-discover bad lanes. + </description> + <valueType>uint32</valueType> + <initToZero/> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_IO_XBUS_GRP1_PRE_BAD_LANE_DATA</id> + <targetType>TARGET_TYPE_XBUS</targetType> + <description> + Pre-training bad lane data vector. This data is persistant from previous + IPLs so that the interface does not need to re-discover bad lanes. + </description> + <valueType>uint32</valueType> + <initToZero/> + <writeable/> +</attribute> +<!-- ********************************************************************** --> </attributes> diff --git a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml index 3c0a7fcbf..1c63e8777 100644 --- a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml +++ b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml @@ -217,6 +217,15 @@ <attribute> <id>ATTR_VDM_ENABLED</id> </attribute> + + <attribute> + <id>ATTR_IO_XBUS_GRP0_PRE_BAD_LANE_DATA</id> + <default>0x00</default> + </attribute> + <attribute> + <id>ATTR_IO_XBUS_GRP1_PRE_BAD_LANE_DATA</id> + <default>0x00</default> + </attribute> <!-- set to 0 to allow automatic enablement when underlying support is available --> <attribute> |
