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Diffstat (limited to 'src/import/generic/memory/lib/data_engine/p9a/p9a_data_init_traits.H')
| -rw-r--r-- | src/import/generic/memory/lib/data_engine/p9a/p9a_data_init_traits.H | 444 |
1 files changed, 444 insertions, 0 deletions
diff --git a/src/import/generic/memory/lib/data_engine/p9a/p9a_data_init_traits.H b/src/import/generic/memory/lib/data_engine/p9a/p9a_data_init_traits.H index 66edc77d0..69234151e 100644 --- a/src/import/generic/memory/lib/data_engine/p9a/p9a_data_init_traits.H +++ b/src/import/generic/memory/lib/data_engine/p9a/p9a_data_init_traits.H @@ -22,3 +22,447 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ +/// +/// @file p9a_data_init_traits.H +/// @brief Trait class definitions for Axone pre_data_init +/// +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP FW Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: HB:CI + +#ifndef _MSS_P9A_PRE_DATA_INIT_TRAITS_H_ +#define _MSS_P9A_PRE_DATA_INIT_TRAITS_H_ + +#include <fapi2.H> +#include <generic/memory/lib/data_engine/data_engine_traits_def.H> +#include <generic/memory/lib/data_engine/data_engine_utils.H> +#include <generic/memory/lib/spd/spd_facade.H> + +namespace mss +{ + +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note AXONE, DIMM_TYPE specialization +/// +template<> +struct attrEngineTraits<pre_data_init_fields, DIMM_TYPE> +{ + using attr_type = fapi2::ATTR_MEM_EFF_DIMM_TYPE_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_DIMM_TYPE_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_DIMM_TYPE; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_DIMM_TYPE, i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return FAPI_ATTR_SET(fapi2::ATTR_MEM_EFF_DIMM_TYPE, i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[in] i_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + // ========================================================= + // DDR4 SPD Document Release 4 + // Byte 3 (0x003): Key Byte / Module Type + // ========================================================= + static const std::vector< std::pair<uint8_t, uint8_t> > BASE_MODULE_TYPE_MAP = + { + //{key byte, dimm type} + {1, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_RDIMM}, + {2, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_UDIMM}, + {10, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_DDIMM}, + // All others reserved or not supported + }; + + uint8_t l_base_module_type = 0; + FAPI_TRY(i_spd_data.base_module(l_base_module_type)); + FAPI_TRY(lookup_table_check(i_spd_data.get_dimm_target(), BASE_MODULE_TYPE_MAP, SET_ATTR_DIMM_TYPE, l_base_module_type, + o_setting)); + + fapi_try_exit: + return fapi2::current_err; + } +}; + +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note AXONE, DRAM_GEN specialization +/// +template<> +struct attrEngineTraits<pre_data_init_fields, DRAM_GEN> +{ + using attr_type = fapi2::ATTR_MEM_EFF_DRAM_GEN_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_DRAM_GEN_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_DRAM_GEN; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_DRAM_GEN, i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return FAPI_ATTR_SET(fapi2::ATTR_MEM_EFF_DRAM_GEN, i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[in] i_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + // ========================================================= + // DDR4 SPD Document Release 4 + // Byte 2 (0x002): Key Byte / DRAM Device Type + // ========================================================= + static const std::vector< std::pair<uint8_t, uint8_t> > DRAM_GEN_MAP = + { + //{key value, dram gen} + {0x0C, fapi2::ENUM_ATTR_MEM_EFF_DRAM_GEN_DDR4} + // Other key bytes reserved or not supported + }; + + uint8_t l_device_type = 0; + FAPI_TRY(i_spd_data.device_type(l_device_type)); + FAPI_TRY(lookup_table_check(i_spd_data.get_dimm_target(), DRAM_GEN_MAP, SET_ATTR_DRAM_GEN, l_device_type, o_setting)); + + fapi_try_exit: + return fapi2::current_err; + } +}; + +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note AXONE, HYBRID specialization +/// +template<> +struct attrEngineTraits<pre_data_init_fields, HYBRID> +{ + using attr_type = fapi2::ATTR_MEM_EFF_HYBRID_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_HYBRID_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_HYBRID; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_HYBRID, i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return FAPI_ATTR_SET(fapi2::ATTR_MEM_EFF_HYBRID, i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[in] i_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + // ========================================================= + // DDR4 SPD Document Release 4 + // Byte 3 (0x003): Key Byte / Module Type - Hybrid + // ========================================================= + static const std::vector< std::pair<uint8_t, uint8_t> > HYBRID_MAP = + { + //{key byte, dimm type} + {0, fapi2::ENUM_ATTR_MEM_EFF_HYBRID_NOT_HYBRID}, + {1, fapi2::ENUM_ATTR_MEM_EFF_HYBRID_IS_HYBRID}, + // All others reserved or not supported + }; + + uint8_t l_spd_hybrid_type = 0; + FAPI_TRY(i_spd_data.hybrid(l_spd_hybrid_type)); + FAPI_TRY(lookup_table_check(i_spd_data.get_dimm_target(), HYBRID_MAP, SET_ATTR_HYBRID, l_spd_hybrid_type, o_setting)); + + fapi_try_exit: + return fapi2::current_err; + } +}; + +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note AXONE, HYBRID_MEDIA specialization +/// +template<> +struct attrEngineTraits<pre_data_init_fields, HYBRID_MEDIA> +{ + using attr_type = fapi2::ATTR_MEM_EFF_HYBRID_MEMORY_TYPE_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_HYBRID_MEMORY_TYPE_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_HYBRID_MEDIA; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_HYBRID_MEMORY_TYPE, i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return FAPI_ATTR_SET(fapi2::ATTR_MEM_EFF_HYBRID_MEMORY_TYPE, i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[in] i_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + // ========================================================= + // DDR4 SPD Document Release 4 + // Byte 3 (0x003): Key Byte / Module Type - Hybrid + // ========================================================= + static const std::vector< std::pair<uint8_t, uint8_t> > HYBRID_MEMORY_TYPE_MAP = + { + + //{key byte, dimm type} + {0, fapi2::ENUM_ATTR_MEM_EFF_HYBRID_MEMORY_TYPE_NONE}, + {1, fapi2::ENUM_ATTR_MEM_EFF_HYBRID_MEMORY_TYPE_NVDIMM}, + // All others reserved or not supported + }; + + uint8_t l_spd_hybrid_media = 0; + FAPI_TRY(i_spd_data.hybrid_media(l_spd_hybrid_media)); + FAPI_TRY(lookup_table_check(i_spd_data.get_dimm_target(), HYBRID_MEMORY_TYPE_MAP, SET_ATTR_HYBRID_MEDIA, + l_spd_hybrid_media, o_setting)); + + fapi_try_exit: + return fapi2::current_err; + } +}; + +/// +/// @brief Gets master ranks from SPD +/// @param[out] o_output num package ranks per DIMM +/// @return FAPI2_RC_SUCCESS iff ok +/// +static fapi2::ReturnCode get_master_ranks(const spd::facade& i_spd_data, + const generic_ffdc_codes i_ffdc, + uint8_t& o_output) +{ + // ========================================================= + // DDR4 SPD Document Release 4 + // Byte 12 (0x00C): Module Organization + // ========================================================= + static const std::vector< std::pair<uint8_t, uint8_t> > NUM_PACKAGE_RANKS_MAP = + { + // {key byte, num of package ranks per DIMM (package ranks)} + {0, fapi2::ENUM_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM_1R}, + {1, fapi2::ENUM_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM_2R}, + {3, fapi2::ENUM_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM_4R}, + }; + + const auto l_dimm = i_spd_data.get_dimm_target(); + uint8_t l_master_ranks_spd = 0; + FAPI_TRY(i_spd_data.num_package_ranks_per_dimm(l_master_ranks_spd), + "%s failed to get number of package ranks from SPD", spd::c_str(l_dimm)); + + FAPI_TRY(lookup_table_check(l_dimm, NUM_PACKAGE_RANKS_MAP, i_ffdc, l_master_ranks_spd, + o_output), "%s failed MASTER_RANKS lookup check", spd::c_str(l_dimm)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note AXONE, MRANKS specialization +/// +template<> +struct attrEngineTraits<pre_data_init_fields, MRANKS> +{ + using attr_type = fapi2::ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_MRANKS; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM, i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return FAPI_ATTR_SET(fapi2::ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM, i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[in] i_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + FAPI_TRY( get_master_ranks(i_spd_data, SET_ATTR_MASTER_RANKS, o_setting) ); + + fapi_try_exit: + return fapi2::current_err; + } +}; + +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note AXONE, DIMM_RANKS_CNFG specialization +/// +template<> +struct attrEngineTraits<pre_data_init_fields, DIMM_RANKS_CNFG> +{ + using attr_type = fapi2::ATTR_MEM_EFF_DIMM_RANKS_CONFIGED_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_DIMM_RANKS_CONFIGED_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_DIMM_RANKS_CNFG; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_DIMM_RANKS_CONFIGED, i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return FAPI_ATTR_SET(fapi2::ATTR_MEM_EFF_DIMM_RANKS_CONFIGED, i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[in] i_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + // Set configed ranks. Set the bit representing the master rank configured (0 being left most.) So, + // a 4R DIMM would be 0b11110000 (0xF0). This is used by PRD. + fapi2::buffer<uint8_t> l_ranks_configed; + + uint8_t l_master_ranks = 0; + FAPI_TRY( get_master_ranks(i_spd_data, SET_ATTR_RANKS_CONFIGED, l_master_ranks) ); + + FAPI_TRY( l_ranks_configed.setBit(0, l_master_ranks), + "%s. Failed to setBit", spd::c_str(i_spd_data.get_dimm_target()) ); + + o_setting = l_ranks_configed; + + fapi_try_exit: + return fapi2::current_err; + } +}; + +}//mss + +#endif |
