diff options
Diffstat (limited to 'src/import/chips')
22 files changed, 1626 insertions, 444 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H index 6d24ec593..876f8a168 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H @@ -274,6 +274,13 @@ HCD_CONST(QUAD_SCOM_RESTORE_SIZE_PER_QUAD, (SCOM_RESTORE_ENTRY_SIZE* QUAD_SCOM_RESTORE_REGS_PER_QUAD)) HCD_CONST(QUAD_SCOM_RESTORE_SIZE_TOTAL, (6 * ONE_KB)) //rounded to 6KB +//FFDC Region +HCD_CONST(FFDC_REGION_QPMR_BASE_OFFSET, 0xE0000) //Offset wrt to QPMR base +HCD_CONST(FFDC_REGION_SIZE, (80 * ONE_KB)) +//end offset of FFDC region wrt to QPMR base +HCD_CONST(FFDC_REGION_QPMR_END_OFFSET, (FFDC_REGION_QPMR_BASE_OFFSET + + FFDC_REGION_SIZE )) +//--------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------- @@ -540,7 +547,8 @@ HCD_CONST(WOF_TABLE_RESERVE, HCD_CONST(PGPE_IMAGE_RESERVE_SIZE, (OCC_PSTATE_PARAM_BLOCK_PPMR_OFFSET - PGPE_IMAGE_PPMR_OFFSET - PGPE_IMAGE_SIZE - PGPE_AUX_TASK_SIZE)) -//FFDC Magic Words +// PM FFDC Magic Words +HCD_CONST(FFDC_MAGIC_NUM, (0x46464443)) //"FFDC" HCD_CONST(FFDC_CME_MAGIC_NUM, (0x434d455f)) //"CME_" HCD_CONST(FFDC_SGPE_MAGIC_NUM, (0x53475045)) //"SGPE" HCD_CONST(FFDC_PGPE_MAGIC_NUM, (0x50475045)) //"PGPE" @@ -548,33 +556,90 @@ HCD_CONST(FFDC_OCC_MAGIC_NUM, (0x4f43435f)) //"OCC_" HCD_CONST(FFDC_CPPM_MAGIC_NUM, (0x4350504d)) //"CPPM" HCD_CONST(FFDC_QPPM_MAGIC_NUM, (0x5150504d)) //"QPPM" HCD_CONST(FFDC_QUAD_MAGIC_NUM, (0x51554144)) //"QUAD" +HCD_CONST(FFDC_FIR_MAGIC_NUM, (0x46495200)) //"FIR" + +// PM FFDC Region Layout Sizes +HCD_CONST(FFDC_SCOM_REG_ID_VAL_SIZE, 12) + +// PPE FFDC Section +// section common to SGPE and PGPE FFDC -//FFDC Region Layout +// 27 CME internal regs, 10 CME regs, 1 buffer/pad +HCD_CONST(FFDC_PPE_INTL_REGISTERS_MAX, 38) + +HCD_CONST(FFDC_PPE_HDR_SIZE , 0x18) HCD_CONST(FFDC_PPE_SCORE_BOARD_SIZE, 0x200) HCD_CONST(FFDC_PPE_IMG_HDR_SIZE, 0x80) HCD_CONST(FFDC_PPE_XIR_SIZE, 0x28) HCD_CONST(FFDC_PPE_SPR_SIZE, 0x80) HCD_CONST(FFDC_PPE_GPR_SIZE, 0x80) -HCD_CONST(FFDC_PPE_INTERNAL_REG_SIZE, 0x78) +HCD_CONST(FFDC_PPE_INTERNAL_REG_SIZE, (FFDC_PPE_INTL_REGISTERS_MAX* + FFDC_SCOM_REG_ID_VAL_SIZE)) HCD_CONST(FFDC_PPE_TRACES_SIZE, 0x200) -HCD_CONST(FFDC_PPE_HDR_SIZE , 0x18) -HCD_CONST(FFDC_QUAD_HDR_SIZE , 0x18) -HCD_CONST(FFDC_CPPM_REGISTERS_SIZE, 0x160) -HCD_CONST(FFDC_PPE_BLOCK_SIZE, 0x6FC) -HCD_CONST(FFDC_QPPM_REGISTERS_SIZE, 0x154) -HCD_CONST(FFDC_HOMER_TOP_HEADER , 0x38) -HCD_CONST(FFDC_QUAD_REGION_SIZE, 0x14DC) +HCD_CONST(FFDC_PPE_BLOCK_SIZE, (FFDC_PPE_HDR_SIZE + + FFDC_PPE_SCORE_BOARD_SIZE + + FFDC_PPE_IMG_HDR_SIZE + + FFDC_PPE_XIR_SIZE + + FFDC_PPE_SPR_SIZE + + FFDC_PPE_GPR_SIZE + + FFDC_PPE_INTERNAL_REG_SIZE + + FFDC_PPE_TRACES_SIZE )) + +// FIR FFDC Section +HCD_CONST(FFDC_PM_CME_FIR_REGISTERS_MAX, 1) +HCD_CONST(FFDC_PM_FIR_REGISTERS_MAX, 2) + +HCD_CONST(FFDC_FIR_HDR_SIZE , 0x10) +HCD_CONST(FFDC_CME_FIR_REGISTERS_SIZE, (FFDC_PM_CME_FIR_REGISTERS_MAX* + FFDC_SCOM_REG_ID_VAL_SIZE)) +HCD_CONST(FFDC_FIR_REGISTER_SIZE, (FFDC_PM_FIR_REGISTERS_MAX* + FFDC_SCOM_REG_ID_VAL_SIZE)) +HCD_CONST(FFDC_FIR_REGION_SIZE, (FFDC_FIR_HDR_SIZE + + (FFDC_CME_FIR_REGISTERS_SIZE* MAX_CMES_PER_CHIP) + + FFDC_FIR_REGISTER_SIZE )) + +// PPM FFDC Sections +HCD_CONST(FFDC_PPM_HDR_SIZE, 0x10) + +// Core PPM +HCD_CONST(FFDC_CPPM_REGISTERS_MAX, 28) +HCD_CONST(FFDC_CPPM_REGISTERS_SIZE, (FFDC_CPPM_REGISTERS_MAX* + FFDC_SCOM_REG_ID_VAL_SIZE)) +HCD_CONST(FFDC_CPPM_REGION_SIZE, (FFDC_PPM_HDR_SIZE + + FFDC_CPPM_REGISTERS_SIZE)) + +// Quad PPM +HCD_CONST(FFDC_QPPM_REGISTERS_MAX, 28) // 1 extra for pad +HCD_CONST(FFDC_QPPM_REGISTERS_SIZE, (FFDC_QPPM_REGISTERS_MAX* + FFDC_SCOM_REG_ID_VAL_SIZE)) +HCD_CONST(FFDC_QPPM_REGION_SIZE, (FFDC_PPM_HDR_SIZE + + FFDC_QPPM_REGISTERS_SIZE)) + +// Quad FFDC Section +HCD_CONST(FFDC_QUAD_HDR_SIZE , 0x20) +HCD_CONST(FFDC_QUAD_REGION_SIZE, (FFDC_QUAD_HDR_SIZE + + (FFDC_CPPM_REGION_SIZE* MAX_CORES_PER_QUAD) + + (FFDC_PPE_BLOCK_SIZE* MAX_CMES_PER_QUAD) + + FFDC_QPPM_REGION_SIZE)) + +// SGPE FFDC Section HCD_CONST(FFDC_SGPE_REGION_SIZE, (FFDC_PPE_BLOCK_SIZE)) +// PGPE FFDC Section HCD_CONST(FFDC_PGPE_REGION_SIZE, (FFDC_PPE_BLOCK_SIZE)) -HCD_CONST(FFDC_OCC_REGION_HDR_SIZE, 0x18) + +// OCC FFDC Section +HCD_CONST(FFDC_OCC_REGISTERS_MAX, 202) // 1 extra for pad + +HCD_CONST(FFDC_OCC_REGION_HDR_SIZE, 0x20) HCD_CONST(FFDC_TRACE_ERR_SIZE, (8 * ONE_KB)) -HCD_CONST(FFDC_TRACE_IMP_SIZE, (FFDC_TRACE_ERR_SIZE)) -HCD_CONST(FFDC_TRACE_INF_SIZE, (FFDC_TRACE_ERR_SIZE)) -HCD_CONST(FFDC_TRACE_SSX_SIZE , (FFDC_TRACE_ERR_SIZE)) +HCD_CONST(FFDC_TRACE_IMP_SIZE, (8 * ONE_KB)) +HCD_CONST(FFDC_TRACE_INF_SIZE, (8 * ONE_KB)) +HCD_CONST(FFDC_TRACE_SSX_SIZE , (8 * ONE_KB)) HCD_CONST(FFDC_TRACE_GPE0_SIZE, 0x200) HCD_CONST(FFDC_TRACE_GPE1_SIZE, 0x200) HCD_CONST(FFDC_SHARED_SRAM_SIZE, 0x200) -HCD_CONST(FFDC_OCC_REGS_SIZE, 0x580) +HCD_CONST(FFDC_OCC_REGS_SIZE, (FFDC_OCC_REGISTERS_MAX* + FFDC_SCOM_REG_ID_VAL_SIZE)) HCD_CONST(FFDC_OCC_REGION_SIZE, (FFDC_OCC_REGION_HDR_SIZE + FFDC_TRACE_ERR_SIZE + FFDC_TRACE_IMP_SIZE + @@ -584,8 +649,17 @@ HCD_CONST(FFDC_OCC_REGION_SIZE, (FFDC_OCC_REGION_HDR_SIZE + FFDC_TRACE_GPE1_SIZE + FFDC_SHARED_SRAM_SIZE + FFDC_OCC_REGS_SIZE)) -HCD_CONST(FFDC_REGION_QPMR_BASE_OFFSET, 0xE0000) + +// Overall PM FFDC Section +HCD_CONST(FFDC_PM_HEADER_SIZE, 0x38) +HCD_CONST(FFDC_PM_REGION_SIZE, (FFDC_PM_HEADER_SIZE + + FFDC_FIR_REGION_SIZE + + (FFDC_QUAD_REGION_SIZE * 6) + + FFDC_SGPE_REGION_SIZE + + FFDC_PGPE_REGION_SIZE + + FFDC_OCC_REGION_SIZE)) + HCD_CONST(FFDC_REGION_HOMER_BASE_OFFSET, - (QPMR_HOMER_OFFSET + FFDC_REGION_QPMR_BASE_OFFSET)) + (FFDC_REGION_QPMR_BASE_OFFSET + QPMR_HOMER_OFFSET)) #endif /* __HCD_MEMMAP_BASE_H__ */ diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H index 4e5fcb4bb..ede7ce4a7 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H @@ -51,23 +51,20 @@ HCD_CONST(OCC_SRAM_BASE_ADDR, 0xFFF00000) HCD_CONST(GPE0_SRAM_BASE_ADDR, 0xFFF01000) HCD_CONST(GPE1_SRAM_BASE_ADDR, 0xFFF10000) -/// Base Addresses for various traces regions in OCC SRAM -HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_SSX_PTR, 0xFFF40824) +/// Base Addresses for various debug/trace regions in OCC SRAM HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_ERR, 0xFFFB4000) HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_INF, 0xFFFB6000) HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_IMP, 0xFFFB8000) -// @TODO: HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_SHARED, 0x0) -HCD_CONST(GPE0_SRAM_TRACE_BUF_PTR, GPE0_SRAM_BASE_ADDR + 0x184) -HCD_CONST(GPE1_SRAM_TRACE_BUF_PTR, GPE1_SRAM_BASE_ADDR + 0x184) +HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_SSX_PTR, 0xFFF40824) + +// Offset to trace buf ptr and trace buffer size from base +HCD_CONST(GPE_DEBUG_PTR_OFFSET, 0x180) // Size of various traces regions in OCC SRAM HCD_CONST(OCC_SRAM_TRACE_BUF_SSX_SIZE_PTR, 0xFFF40828) HCD_CONST(OCC_SRAM_TRACE_BUF_ERR_SIZE, (8 * ONE_KB)) HCD_CONST(OCC_SRAM_TRACE_BUF_INF_SIZE, (8 * ONE_KB)) HCD_CONST(OCC_SRAM_TRACE_BUF_IMP_SIZE, (8 * ONE_KB)) -// @TODO: HCD_CONST(OCC_SRAM_TRACE_BUF_SHARED_SIZE, ) -HCD_CONST(GPE0_SRAM_TRACE_BUF_SIZE_PTR, (GPE0_SRAM_BASE_ADDR + 0x188)) -HCD_CONST(GPE1_SRAM_TRACE_BUF_SIZE_PTR, (GPE1_SRAM_BASE_ADDR + 0x188)) HCD_CONST(OCC_SRAM_IPC_REGION_SIZE, (4 * ONE_KB)) HCD_CONST(OCC_SRAM_GPE0_REGION_SIZE, (60 * ONE_KB)) diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.C index 7ecb814f4..ac78cfe65 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.C @@ -26,15 +26,27 @@ #include <p9_pm_recovery_ffdc_base.H> #include <p9_pm_recovery_ffdc_defines.H> + +#include <p9_pm_recovery_ffdc_cme.H> +#include <p9_pm_recovery_ffdc_sgpe.H> +#include <p9_pm_recovery_ffdc_pgpe.H> +#include <p9_pm_recovery_ffdc_occ.H> +#include <p9_pm_recovery_ffdc_cppm.H> +#include <p9_pm_recovery_ffdc_qppm.H> + #include <p9_ppe_state.H> +#include <p9_pm_ocb_indir_access.H> +#include <p9_cme_sram_access.H> +#include <p9_pm_ocb_indir_setup_linear.H> + #include <endian.h> #include <stddef.h> - namespace p9_stop_recov_ffdc - { +namespace p9_stop_recov_ffdc +{ PlatPmComplex::PlatPmComplex( const fapi2::Target< fapi2::TARGET_TYPE_PROC_CHIP > i_procChipTgt, - uint32_t i_imageHdrBaseAddr, uint32_t i_traceBufBaseAddr, - uint32_t i_globalBaseAddr, PmComplexPlatId i_plat ) + PmComplexPlatId i_plat, uint32_t i_imageHdrBaseAddr, + uint32_t i_traceBufBaseAddr, uint32_t i_globalBaseAddr ) : iv_procChip( i_procChipTgt ), iv_imageHeaderBaseAddress( i_imageHdrBaseAddr ), iv_traceBufBaseAddress( i_traceBufBaseAddr ), @@ -44,12 +56,91 @@ //--------------------------------------------------------------------------------------------- - fapi2::ReturnCode PlatPmComplex::collectFfdc( void * i_pHomerBuf ) + fapi2::ReturnCode PlatPmComplex::init ( void* i_pHomerBuf ) { - FAPI_DBG(">> PlatPmComplex::collectFfdc"); + FAPI_DBG ( ">> PlatPmComplex::init" ); + + HomerFfdcRegion* l_pHomerFfdc = ( HomerFfdcRegion* ) + ((uint8_t*) i_pHomerBuf + FFDC_REGION_HOMER_BASE_OFFSET ); + + uint8_t* l_pFfdcLoc = (uint8_t*) (&l_pHomerFfdc->iv_pmFfdcHdrRegion); + PmFfdcHeader* l_pPmFfdcHdr = (PmFfdcHeader*) + ((PmFfdcHdrRegion*) l_pFfdcLoc); + uint32_t l_procPosition = 0xDEADC0DE; + if (FAPI_ATTR_GET (fapi2::ATTR_FAPI_POS, iv_procChip, l_procPosition) != + fapi2::FAPI2_RC_SUCCESS) + { + FAPI_ERR ("Could not read ATTR_FAPI_POS for the chip!"); + } + + l_pPmFfdcHdr->iv_magicNumber = htobe32 (FFDC_MAGIC_NUM); + l_pPmFfdcHdr->iv_versionMajor = 0x01; + l_pPmFfdcHdr->iv_versionMinor = 0x00; + l_pPmFfdcHdr->iv_headerSize = htobe16 (sizeof (PmFfdcHeader)); + l_pPmFfdcHdr->iv_sectionSize = htobe32 (sizeof (HomerFfdcRegion)); + l_pPmFfdcHdr->iv_procPosition = htobe32 (l_procPosition); + l_pPmFfdcHdr->iv_ffdcValid = 0x01; + l_pPmFfdcHdr->iv_phase = PM_RESET_FFDC_SEC_INIT; + l_pPmFfdcHdr->iv_errorMarker = htobe16 (0x0000); + l_pPmFfdcHdr->iv_sectionsValid = htobe16 (PM_FFDC_INVALID); + + uint16_t l_sectionOffset = sizeof (PmFfdcHeader); + l_pPmFfdcHdr->iv_firOffset = htobe16 (l_sectionOffset); + l_sectionOffset+= sizeof (FirFfdcRegion); + + for ( int i=0; i<MAX_QUADS_PER_CHIP; ++i ) + { + l_pPmFfdcHdr->iv_quadOffset[i] = htobe16 (l_sectionOffset); + l_sectionOffset += sizeof (HomerQuadFfdcRegion); + } + + l_pPmFfdcHdr->iv_sgpeOffset = htobe16 (l_sectionOffset); + l_sectionOffset += sizeof (PpeFfdcLayout); + l_pPmFfdcHdr->iv_pgpeOffset = htobe16 (l_sectionOffset); + l_sectionOffset += sizeof (PpeFfdcLayout); + l_pPmFfdcHdr->iv_occOffset = htobe16 (l_sectionOffset); + l_pPmFfdcHdr->iv_ccsr = 0; // @TODO via RTC 153978 + l_pPmFfdcHdr->iv_qcsr = 0; // @TODO via RTC 153978 + + FAPI_DBG( "================== PM FFDC Header ==========================" ); + FAPI_DBG( "Magic Number : 0x%08X", l_pPmFfdcHdr->iv_magicNumber ); + FAPI_DBG( "Version Major : 0x%02X", l_pPmFfdcHdr->iv_versionMajor ); + FAPI_DBG( "Version Minor : 0x%02X", l_pPmFfdcHdr->iv_versionMinor); + FAPI_DBG( "Header Size : 0x%02X", l_pPmFfdcHdr->iv_headerSize ); + FAPI_DBG(" FFDC Section Size : 0x%08X", l_pPmFfdcHdr->iv_sectionSize ); + FAPI_DBG(" Proc Position : 0x%08X", l_pPmFfdcHdr->iv_procPosition ); + FAPI_DBG(" PM FFDC Valid : 0x%02X", l_pPmFfdcHdr->iv_ffdcValid ); + FAPI_DBG(" PM RESET Phase : 0x%02X", l_pPmFfdcHdr->iv_phase ); + FAPI_DBG(" Error Marker : 0x%04X", l_pPmFfdcHdr->iv_errorMarker ); + FAPI_DBG(" Sub-section Validity Vector : 0x%04X", l_pPmFfdcHdr->iv_sectionsValid ); + FAPI_DBG(" FIR Sub-section Offset : 0x%04X", l_pPmFfdcHdr->iv_firOffset ); + FAPI_DBG(" Quad 0 Sub-section Offset : 0x%04X", l_pPmFfdcHdr->iv_quadOffset[0] ); + FAPI_DBG(" Quad 1 Sub-section Offset : 0x%04X", l_pPmFfdcHdr->iv_quadOffset[1] ); + FAPI_DBG(" Quad 2 Sub-section Offset : 0x%04X", l_pPmFfdcHdr->iv_quadOffset[2] ); + FAPI_DBG(" Quad 3 Sub-section Offset : 0x%04X", l_pPmFfdcHdr->iv_quadOffset[3] ); + FAPI_DBG(" Quad 4 Sub-section Offset : 0x%04X", l_pPmFfdcHdr->iv_quadOffset[4] ); + FAPI_DBG(" Quad 5 Sub-section Offset : 0x%04X", l_pPmFfdcHdr->iv_quadOffset[5] ); + FAPI_DBG(" SGPE Sub-section Offset : 0x%04X", l_pPmFfdcHdr->iv_sgpeOffset ); + FAPI_DBG(" PGPE Sub-section Offset : 0x%04X", l_pPmFfdcHdr->iv_pgpeOffset ); + FAPI_DBG(" OCC Sub-section Offset : 0x%04X", l_pPmFfdcHdr->iv_occOffset ); + FAPI_DBG( "================== PM FFDC Header End ====================" ); + + FAPI_DBG ("<< PlatPmComplex::init"); + return fapi2::FAPI2_RC_SUCCESS; + } + + //--------------------------------------------------------------------------------------------- + + fapi2::ReturnCode PlatPmComplex::collectFfdc( void* i_pHomerBuf, + uint8_t i_ffdcType ) + { + FAPI_DBG ( ">> PlatPmComplex::collectFfdc" ); + FAPI_INF ( "PlatPmComplex::collectFfdc No-Op. Plat Type 0x%02X", + iv_plat ); FAPI_DBG("<< PlatPmComplex::collectFfdc"); - return fapi2::FAPI2_RC_SUCCESS;; + + return fapi2::FAPI2_RC_SUCCESS; } //--------------------------------------------------------------------------------------------- @@ -77,23 +168,24 @@ #endif //--------------------------------------------------------------------------------------------- - fapi2::ReturnCode PlatPmComplex::updatePpeFfdcHeader( PpeFfdcHeader * i_pFfdcHdr, - uint8_t i_ffdcValid, uint8_t i_haltState ) + fapi2::ReturnCode PlatPmComplex::updatePpeFfdcHeader ( PpeFfdcHeader * i_pFfdcHdr, + uint16_t i_sectionsValid ) { FAPI_DBG(">> updatePpeFfdcHeader" ); - i_pFfdcHdr->iv_headerSize = sizeof( PpeFfdcHeader ); - i_pFfdcHdr->iv_sectionSize = htobe16( sizeof( PpeFfdcLayout ) ); - i_pFfdcHdr->iv_ffdcValid = i_ffdcValid; - i_pFfdcHdr->iv_ppeHaltCondition = i_haltState; - i_pFfdcHdr->iv_dashBoardOffset = htobe16( offsetof( struct PpeFfdcLayout, iv_ppeGlobals[0])); - i_pFfdcHdr->iv_sramHeaderOffset = htobe16( offsetof( struct PpeFfdcLayout, iv_ppeImageHeader[0])); - i_pFfdcHdr->iv_sprOffset = htobe16( offsetof( struct PpeFfdcLayout, iv_ppeXirReg[0])); - i_pFfdcHdr->iv_intRegOffset = htobe16( offsetof( struct PpeFfdcLayout, iv_ppeInternalReg[0])); - i_pFfdcHdr->iv_offsetTraces = htobe16( offsetof( struct PpeFfdcLayout, iv_ppeTraces[0] )); + i_pFfdcHdr->iv_versionMajor = 1; + i_pFfdcHdr->iv_versionMinor = 0; + i_pFfdcHdr->iv_headerSize = htobe16 (sizeof(PpeFfdcHeader)); + i_pFfdcHdr->iv_sectionSize = htobe16 (sizeof(PpeFfdcLayout )); + i_pFfdcHdr->iv_sectionsValid = htobe16 (i_sectionsValid); + i_pFfdcHdr->iv_dashBoardOffset = htobe16( offsetof( struct PpeFfdcLayout, iv_ppeGlobals[0])); + i_pFfdcHdr->iv_sramHeaderOffset = htobe16( offsetof( struct PpeFfdcLayout, iv_ppeImageHeader[0])); + i_pFfdcHdr->iv_sprOffset = htobe16( offsetof( struct PpeFfdcLayout, iv_ppeXirReg[0])); + i_pFfdcHdr->iv_intRegOffset = htobe16( offsetof( struct PpeFfdcLayout, iv_ppeInternalReg[0])); + i_pFfdcHdr->iv_offsetTraces = htobe16( offsetof( struct PpeFfdcLayout, iv_ppeTraces[0] )); FAPI_DBG( "================== PPE Header ==========================" ); - FAPI_DBG( "FFDC Validity Vector : 0x%02x", i_pFfdcHdr->iv_ffdcValid ); + FAPI_DBG( "FFDC Validity Vector : 0x%04x", i_pFfdcHdr->iv_sectionsValid ); FAPI_DBG( "PPE Header Size : 0x%02x", i_pFfdcHdr->iv_headerSize ); FAPI_DBG( "PPE FFDC Section Size : 0x%04x", REV_2_BYTE(i_pFfdcHdr->iv_sectionSize) ); FAPI_DBG( "PPE Halt State : 0x%02x", i_pFfdcHdr->iv_ppeHaltCondition ); @@ -109,18 +201,41 @@ } //------------------------------------------------------------------------------ - // @TODO May need to port this away, based on discussion + + void PlatPmComplex::setPmFfdcSectionValid ( void* i_pHomerBuf, + uint16_t i_pmFfdcSectionState, + bool i_valid ) + { + FAPI_DBG ( ">> PlatPmComplex::setPmFfdcSectionValid 0x%02X Valid %d", + i_pmFfdcSectionState, i_valid ); + HomerFfdcRegion* l_pHomerFfdc = ( HomerFfdcRegion* ) + ((uint8_t*) i_pHomerBuf + FFDC_REGION_HOMER_BASE_OFFSET ); + + uint16_t* l_pSectionsValid = &l_pHomerFfdc->iv_pmFfdcHdrRegion.iv_pmFfdcHdr.iv_sectionsValid; + + if (i_valid == true) + *l_pSectionsValid |= htobe16 (i_pmFfdcSectionState); + else + *l_pSectionsValid &= htobe16 (~i_pmFfdcSectionState); + + FAPI_DBG ( "<< PlatPmComplex::setPmFfdcSectionValid 0x%02X", + *l_pSectionsValid ); + } + +//------------------------------------------------------------------------------ + fapi2::ReturnCode PlatPmComplex::readPpeHaltState ( - const uint64_t i_xirBaseAddress, - uint8_t& o_ppeHaltState ) + const uint64_t i_xirBaseAddress, + const uint8_t* i_pHomerOffset ) { FAPI_DBG ( ">> PlatPmComplex::getPpeHaltState XIR Base: 0x%08llX", i_xirBaseAddress ); fapi2::ReturnCode l_rc; fapi2::buffer<uint64_t> l_data64; + uint8_t l_ppeHaltState = PPE_HALT_COND_UNKNOWN; - o_ppeHaltState = PPE_HALT_COND_UNKNOWN; + PpeFfdcHeader* l_pPpeFfdcHdr = (PpeFfdcHeader*) i_pHomerOffset; // Read the PPE XIR pair for XSR+SPRG0 l_rc = getScom ( iv_procChip, @@ -128,15 +243,15 @@ l_data64 ); if ( l_rc == fapi2::FAPI2_RC_SUCCESS ) - { // PU_PPE_XIRAMDBG_XSR_HS - if ( l_data64.getBit (0, 1) ) + { + if ( l_data64.getBit <PU_PPE_XIRAMDBG_XSR_HS>() ) { // Halt exists, get all bits 0:3 - l_data64.getBit (PU_PPE_XIRAMDBG_XSR_HS, 4); - o_ppeHaltState = static_cast<uint8_t> (l_data64()); + l_data64.getBit <PU_PPE_XIRAMDBG_XSR_HS, 4>(); + l_ppeHaltState = static_cast<uint8_t> (l_data64()); } else { // PPE is not halted - o_ppeHaltState = PPE_HALT_COND_NONE; + l_ppeHaltState = PPE_HALT_COND_NONE; } } else @@ -144,14 +259,14 @@ FAPI_ERR ("::readPpeHaltState: Error reading PPE XIRAMDBG"); } + l_pPpeFfdcHdr->iv_ppeHaltCondition = l_ppeHaltState; + FAPI_DBG ( "<< PlatPmComplex::getPpeHaltState: 0x%02X", - o_ppeHaltState ); + l_ppeHaltState ); return fapi2::FAPI2_RC_SUCCESS; } //------------------------------------------------------------------------------ - // @TODO Ideally, the reset flow should have already halted the PPE. - // Should the default mode here be FORCE_HALT? Is that safe? fapi2::ReturnCode PlatPmComplex::collectPpeState ( const uint64_t i_xirBaseAddress, const uint8_t* i_pHomerOffset, @@ -165,8 +280,6 @@ std::vector<PPERegValue_t> l_vGprs; std::vector<PPERegValue_t> l_vXirs; - // @TODO Update the ppe_halt HWP to avoid halting the PPE again - // if it is already halted. Can potentially change the XSR? FAPI_TRY ( p9_ppe_state ( iv_procChip, i_xirBaseAddress, @@ -175,7 +288,6 @@ l_vXirs, l_vGprs) ); - // @TODO any faster way, e.g. use data() method and memcpy? l_pPpeRegVal = (PPERegValue_t*) &l_pPpeFfdc->iv_ppeXirReg[0]; for ( auto& it : l_vXirs ) { @@ -322,4 +434,90 @@ FAPI_DBG("<< PlatPmComplex::collectSramInfo" ); return fapi2::current_err; } - }//namespace p9_stop_recov_ffdc ends + + //--------------------------------------------------------------------------------------------- + + fapi2::ReturnCode PlatPmComplex::updateFirFfdcHeader ( + uint8_t* i_pFfdcHdr, + uint8_t i_pos, + bool i_ffdcValid ) + { + FAPI_DBG(">> PlatPmComplex::updateFirFfdcHeader: Pos %d", i_pos ); + + FirFfdcHeader* l_FirFfdcHdr = (FirFfdcHeader*) i_pFfdcHdr; + l_FirFfdcHdr->iv_magicWord = htobe32 (FFDC_FIR_MAGIC_NUM); + l_FirFfdcHdr->iv_versionMajor = 1; + l_FirFfdcHdr->iv_versionMinor = 0; + l_FirFfdcHdr->iv_headerSize = htobe16 (sizeof(FirFfdcHeader)); + l_FirFfdcHdr->iv_sectionSize = htobe16 (sizeof(FirFfdcRegion)); + + if (i_pos < PM_FFDC_FIR_VALID_POS_MAX) + { + uint16_t l_validBit = PM_FFDC_FIR_VALID_POS_0 >> i_pos; + + if (i_ffdcValid) + { + l_FirFfdcHdr->iv_validityVector |= htobe16 (l_validBit); + } + else + { + l_FirFfdcHdr->iv_validityVector &= htobe16 (~l_validBit); + } + } + else + { + FAPI_ERR ( "Bad Pos %d for FIR FFDC Validity Vector", i_pos ); + } + + FAPI_DBG("<< PlatPmComplex::updateFirFfdcHeader" ); + return fapi2::FAPI2_RC_SUCCESS; + } + + //--------------------------------------------------------------------------------------------- + +extern "C" +{ + fapi2::ReturnCode p9_pm_recovery_ffdc_base ( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_procChipTarget, + void* i_pHomerImage ) + { + FAPI_IMP(">> p9_pm_recovery_ffdc_base" ); + std::vector<PlatPmComplex*> l_pPlatList; + + // init all the platform FFDC headers + l_pPlatList.push_back (new PlatPmComplex(i_procChipTarget)); + l_pPlatList.push_back (new PlatCme(i_procChipTarget)); + l_pPlatList.push_back (new PlatSgpe(i_procChipTarget)); + l_pPlatList.push_back (new PlatPgpe(i_procChipTarget)); + l_pPlatList.push_back (new PlatOcc(i_procChipTarget)); + l_pPlatList.push_back (new CppmRegs(i_procChipTarget)); + l_pPlatList.push_back (new QppmRegs(i_procChipTarget)); + + FAPI_INF ("p9_pm_recovery_ffdc_base: Initializing PM FFDC sections"); + for ( auto& it : l_pPlatList ) + { + FAPI_TRY ( it->init (i_pHomerImage), + "::init Failed to init plat %d", + it->getPlatId() ); + } + + // Grab FIRs and PPE Halt State in FFDC, before entering Reset Flow + FAPI_INF ("p9_pm_recovery_ffdc_base: Collecting FIR & PPE Halt States"); + for ( auto& it : l_pPlatList ) + { + FAPI_TRY ( it->collectFfdc (i_pHomerImage, (PPE_HALT_STATE | FIR_STATE)), + "p9_pm_recovery_ffdc_base: Failed to collect FOR & PPE Halt State. Plat %d", + it->getPlatId () ); + } + + fapi_try_exit: + for ( auto& it : l_pPlatList ) + delete it; + + FAPI_IMP("<< p9_pm_recovery_ffdc_base" ); + return fapi2::FAPI2_RC_SUCCESS; + } +} + + +} //namespace p9_stop_recov_ffdc ends diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.H index 7ac75e5e8..c8b56f6da 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.H @@ -22,12 +22,12 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -#ifndef __P9_PM_RECOVERY_BASE_ -#define __P9_PM_RECOVERY_BASE_ +#ifndef __P9_PM_RECOVERY_FFDC_BASE_ +#define __P9_PM_RECOVERY_FFDC_BASE_ /// -/// @file p9_stop_ffdc_base.H +/// @file p9_pm_recovery_ffdc_base.H /// @brief Models generic platform for the FFDC collection of PM complex /// /// *HWP HWP Owner: Greg Still <stillgs@us.ibm.com> @@ -41,39 +41,46 @@ // Includes //-------------------------------------------------------------------------- #include <fapi2.H> -#include <collect_reg_ffdc.H> #include <stdint.h> -#include <p9_hcd_memmap_cme_sram.H> -#include <p9_hcd_memmap_occ_sram.H> #include <p9_pm_recovery_ffdc_defines.H> -#include <p9_pm_ocb_indir_access.H> -#include <p9_cme_sram_access.H> -#include <p9_pm_ocb_indir_setup_linear.H> #include <p9_ppe_utils.H> namespace p9_stop_recov_ffdc { + class PlatPmComplex { public: /// @brief constructor /// @param[in] i_procChipTgt fapi2 target for P9 chip + /// @param[in] i_plat platform id /// @param[in] i_imageHdrBaseAddr sram address of start of image header /// @param[in] i_traceBufBaseAddr sram address of start of trace buffer /// @param[in] i_globalBaseAddr sram address of start of global variables - /// @param[in] i_plat platform id - PlatPmComplex( const fapi2::Target< fapi2::TARGET_TYPE_PROC_CHIP > i_procChipTgt, - uint32_t i_imageHdrBaseAddr, uint32_t i_traceBufBaseAddr, - uint32_t i_globalBaseAddr, - PmComplexPlatId i_plat ); + PlatPmComplex( const fapi2::Target< fapi2::TARGET_TYPE_PROC_CHIP > + i_procChipTgt, + PmComplexPlatId i_plat = PLAT_NONE, + uint32_t i_imageHdrBaseAddr = 0, + uint32_t i_traceBufBaseAddr = 0, + uint32_t i_globalBaseAddr = 0 ); /// @brief destructor virtual ~PlatPmComplex() { }; - /// @brief collects category of FFDC common for all platforms in PM complex. - /// @param[in] i_pHomerBuf points to base of P9 HOMER. + /// @brief Initializes the PM FFDC Section Header in HOMER + /// @param[in] i_pHomerBuf pointer to base of P9 HOMER. + // @return fapi2 return code + virtual fapi2::ReturnCode init ( void* i_pHomerBuf ); + + /// @brief Collects specified FFDC to PM FFDC section of HOMER + /// @param[in] i_pHomerBuf points to base of P9 HOMER. + /// @param[in] i_ffdcType indicates the content type to collect // @return fapi2 return code. - virtual fapi2::ReturnCode collectFfdc( void* i_pHomerBuf ); + virtual fapi2::ReturnCode collectFfdc( void* i_pHomerBuf, + uint8_t i_ffdcType = ALL ); + + /// @brief returns proc chip target associated with platform + fapi2::Target< fapi2::TARGET_TYPE_PROC_CHIP > getProcChip() const { return iv_procChip; } /// @brief sets start address of platform's trace buffer. void setTraceBufAddr (uint32_t i_addr) @@ -82,17 +89,25 @@ namespace p9_stop_recov_ffdc ///@brief returns instance id. PmComplexPlatId getPlatId() { return iv_plat ; } - /// @brief returns proc chip target associated with platform - fapi2::Target< fapi2::TARGET_TYPE_PROC_CHIP > getProcChip() const { return iv_procChip; } - protected: + + ///@brief sets the validity of a section in the PmFfdcHeader + ///@param[in] i_pHomerBuf Base address of PM FFDC in HOMER + ///@param[in] i_pmFfdcSectionState See PmFfdcSectionState + ///@param[in] i_valid true: sets the section valid + /// false: sets the section invalid + ///@return N.A. + void setPmFfdcSectionValid ( void* i_pHomerBuf, + uint16_t i_pmFfdcSectionState, + bool i_valid = true ); + ///@brief reads the PPE Halt State from XSR, w/o halting the PPE ///@param[in] i_xirBaseAddress XCR SCOM Address of the PPE - ///@param[out] o_haltCondition p9_stop_recov_ffdc::PpeHaltCondition + ///@param[in] i_pHomerOffset PPE section base address in HOMER ///@return fapi2 return code fapi2::ReturnCode readPpeHaltState ( const uint64_t i_xirBaseAddress, - uint8_t& o_haltCondition ); + const uint8_t* i_pHomerOffset ); ///@brief collects PPE State (XIRs, SPRs, GPRs) to a loc in HOMER ///@param[in] i_xirBaseAddress XCR SCOM Address of the PPE @@ -102,7 +117,7 @@ namespace p9_stop_recov_ffdc fapi2::ReturnCode collectPpeState ( const uint64_t i_xirBaseAddress, const uint8_t* i_pHomerOffset, - const PPE_DUMP_MODE i_mode = HALT ); + const PPE_DUMP_MODE i_mode = FORCE_HALT ); ///@brief collects FFDC from CME/OCC SRAM ///@param[in] i_chipletTarget fapi2 target for EX or Proc @@ -120,6 +135,23 @@ namespace p9_stop_recov_ffdc FfdcDataType i_dataType, uint32_t i_sramLength ); + + ///@brief updates parts of PPE FFDC Header common for all platforms. + ///param[in] i_pFfdcHdr points to the PPE FFDC header + ///param[in] i_sectionsValid bit vector summarizing FFDC validity + fapi2::ReturnCode updatePpeFfdcHeader( PpeFfdcHeader * i_pFfdcHdr, + uint16_t i_sectionsValid ); + + ///@brief update header for the FIR FFDC section + ///param[in] i_pFfdcHdr pointer to FIR FFDC header in HOMER + ///param[in] i_pos chiplet position + ///param[in] i_ffdcValid true if valid, false otherwise + ///@return fapi2 return code + fapi2::ReturnCode updateFirFfdcHeader( uint8_t* i_pFfdcHdr, + uint8_t i_pos, + bool i_ffdcValid); + + ///@brief Collects register data ///param[in] i_chipletTarget Chip/chilpet target ///param[out] o_pHomerBuf Homer base address to fill register @@ -131,15 +163,6 @@ namespace p9_stop_recov_ffdc fapi2::ReturnCode collectRegisterData( const fapi2::Target<T>& i_chipletTarget, uint8_t* o_pHomerBuf, fapi2::HwpFfdcId i_ffdcId); - - - ///@brief updates parts of PPE FFDC Header common for all platforms. - ///param[in] i_pFfdcHdr points to the PPE FFDC header - ///param[in] i_ffdcValid bit vector summarizing FFDC validity - ///param[in] i_haltState FFDC halt state - ///@note refer to PPE Spec for halt state description. - fapi2::ReturnCode updatePpeFfdcHeader( PpeFfdcHeader * i_pFfdcHdr, - uint8_t i_ffdcValid, uint8_t i_haltState ); #ifndef __HOSTBOOT_MODULE ///@brief to debug FFDC contents collected from SRAM. ///param[in] i_pSram points to location of SRAM info in HOMER. @@ -156,10 +179,13 @@ namespace p9_stop_recov_ffdc PmComplexPlatId iv_plat; }; + //--------------------------------------------------------------------------------------------- + template<fapi2::TargetType T> - fapi2::ReturnCode PlatPmComplex::collectRegisterData(const fapi2::Target<T>& i_chipletTarget, - uint8_t *o_pHomerBuf, - fapi2::HwpFfdcId i_ffdcId) + fapi2::ReturnCode PlatPmComplex::collectRegisterData ( + const fapi2::Target<T>& i_chipletTarget, + uint8_t *o_pHomerBuf, + fapi2::HwpFfdcId i_ffdcId ) { FAPI_DBG(">> collectRegisterData"); std::vector<uint32_t> l_cfamAddresses; @@ -172,14 +198,40 @@ namespace p9_stop_recov_ffdc FAPI_TRY((fapi2::collectRegisterAndAddressData<uint64_t, fapi2::ScomReader<T> >(l_scomAddresses, l_scomReader, - l_offset, o_pHomerBuf)), + l_offset, o_pHomerBuf)), "Failed in collectRegisterAndAddressData"); - fapi_try_exit: + fapi_try_exit: FAPI_DBG("<< collectRegisterData"); return fapi2::current_err; + }; + + //--------------------------------------------------------------------------------------------- + + // function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_pm_recovery_ffdc_base_FP_t) + ( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&, + const void* ); + + extern "C" + { + // ----------------------------------------------------------------------------- + // Function prototypes + // ----------------------------------------------------------------------------- + /// + /// @brief Initializes the PM FFDC section in HOMER with default headers and + /// other FFDC to be collection before the PM Reset Flow + /// + /// @param[in] i_procChipTarget Proc Chip target + /// @param[in] i_pHomerImage Pointer to the base of the chip HOMER region + /// + /// @return FAPI2_RC_SUCCESS on success or error return code + /// + fapi2::ReturnCode p9_pm_recovery_ffdc_base + ( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_procChipTarget, + void* i_pHomerImage ); } } //namespace p9_stop_recov_ffdc ends -#endif //__P9_PM_RECOVERY_BASE_ +#endif //__P9_PM_RECOVERY_FFDC_BASE_ diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.mk b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.mk index 5adde6809..967f69672 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.mk +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.mk @@ -25,7 +25,14 @@ PROCEDURE = p9_pm_recovery_ffdc_base FFDC_INC=$(ROOTPATH)/chips/p9/procedures/hwp/lib/ lib$(PROCEDURE)_DEPLIBS+=p9_pm_ocb_indir_setup_linear +lib$(PROCEDURE)_DEPLIBS+=p9_pm_recovery_ffdc_pgpe +lib$(PROCEDURE)_DEPLIBS+=p9_pm_recovery_ffdc_sgpe +lib$(PROCEDURE)_DEPLIBS+=p9_pm_recovery_ffdc_cme +lib$(PROCEDURE)_DEPLIBS+=p9_pm_recovery_ffdc_cppm +lib$(PROCEDURE)_DEPLIBS+=p9_pm_recovery_ffdc_occ +lib$(PROCEDURE)_DEPLIBS+=p9_pm_recovery_ffdc_qppm lib$(PROCEDURE)_DEPLIBS+=p9_cme_sram_access lib$(PROCEDURE)_DEPLIBS+=p9_ppe_state +lib$(PROCEDURE)_DEPLIBS+=p9_ppe_utils $(call ADD_MODULE_INCDIR,$(FFDC_INC)) $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.C index 2774f1539..5be51b1e9 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.C @@ -51,110 +51,176 @@ { PlatCme::PlatCme( const fapi2::Target< fapi2::TARGET_TYPE_PROC_CHIP > i_procChipTgt ) : PlatPmComplex( i_procChipTgt, + PLAT_CME, FFDC_PPE_IMG_HDR_START, FFDC_CME_TRACE_START, - FFDC_CME_DASH_BOARD_START, - PLAT_CME ) + FFDC_CME_DASH_BOARD_START ) { } //---------------------------------------------------------------------- - fapi2::ReturnCode PlatCme::collectFfdc( void * i_pHomerBuf ) + fapi2::ReturnCode PlatCme::init ( void* i_pHomerBuf ) { - FAPI_DBG(">> PlatCme::collectFfdc"); + FAPI_DBG (">> PlatCme::init" ); + FAPI_TRY ( collectFfdc( i_pHomerBuf, INIT), + "Failed To init CME FFDC" ); + + fapi_try_exit: + FAPI_DBG ("<< PlatCme::init" ); + return fapi2::current_err; + } + + //---------------------------------------------------------------------- + + fapi2::ReturnCode PlatCme::collectFfdc( void* i_pHomerBuf, + uint8_t i_ffdcType ) + { + FAPI_DBG ( ">> PlatCme::collectFfdc: i_ffdcType: 0x%02X", i_ffdcType ); fapi2::ReturnCode l_retCode = fapi2::FAPI2_RC_SUCCESS; auto l_exList = getProcChip().getChildren< fapi2::TARGET_TYPE_EX > ( fapi2::TARGET_STATE_PRESENT ); uint8_t l_quadPos = 0; uint8_t l_exPos = 0; uint8_t l_cmePos = 0; - uint8_t l_ffdcValdityVect = PPE_FFDC_ALL_VALID; - uint8_t l_haltState = PPE_HALT_COND_UNKNOWN; uint8_t *l_pFfdcLoc = NULL; + uint8_t* l_pFirFfdcLoc = NULL; HomerFfdcRegion * l_pHomerFfdc = ( HomerFfdcRegion *)( (uint8_t *)i_pHomerBuf + FFDC_REGION_HOMER_BASE_OFFSET ); for( auto ex : l_exList ) { - l_ffdcValdityVect = PPE_FFDC_ALL_VALID; - FAPI_TRY( FAPI_ATTR_GET( fapi2::ATTR_CHIP_UNIT_POS, ex, l_cmePos ), "FAPI_ATTR_GET Failed To Read EX Position" ); - if( !ex.isFunctional() ) + l_exPos = l_cmePos % 2; + l_quadPos = l_cmePos >> 1; + l_pFfdcLoc = &l_pHomerFfdc->iv_quadFfdc[l_quadPos].iv_quadCmeBlock[l_exPos][0]; + l_pFirFfdcLoc = &l_pHomerFfdc->iv_firFfdcRegion.iv_firCmeBlock[l_cmePos][0]; + + PpeFfdcHeader* l_pCmeFfdcHdr = (PpeFfdcHeader*) l_pFfdcLoc; + uint16_t l_ffdcValdityVect = l_pCmeFfdcHdr->iv_sectionsValid; + + if ( !ex.isFunctional() || (i_ffdcType & INIT)) { //Marking CME FFDC region as Invalid l_ffdcValdityVect = PPE_FFDC_INVALID; - FAPI_TRY( updateCmeFfdcHeader( l_pFfdcLoc, l_cmePos, l_ffdcValdityVect, l_haltState ), + FAPI_TRY( updateCmeFfdcHeader( l_pFfdcLoc, l_cmePos, l_ffdcValdityVect ), "Failed To Update CME FFDC Header for CME 0x%0d", l_cmePos ); + + // Mark CME FIR FFDC invalid + FAPI_TRY ( updateFirFfdcHeader ( + &l_pHomerFfdc->iv_firFfdcRegion.iv_firFfdcHeader[0], + l_cmePos, + false ) ); continue; } - l_exPos = l_cmePos % 2; - l_quadPos = l_cmePos >> 1; - l_pFfdcLoc = &l_pHomerFfdc->iv_quadFfdc[l_quadPos].iv_quadCmeBlock[l_exPos][0]; - FAPI_INF("CME FFDC Quad Pos %d Ex Pos %d ", l_quadPos, l_exPos ); //In case of error , invalidate FFDC in header. + // INIT case handled above where only header update is needed - // @TODO this is still after reset, which would have already - // halted the ppe. We need a wa to record this before reset - // and pass it down, or have a spl r-m-w update per member - // of the PPE Header? - // l_retCode = getPpeHaltState ( - // getCmeBaseAddress (l_cmePos), - // l_haltState); - - l_retCode = collectPpeState ( getCmeBaseAddress (l_cmePos), - l_pFfdcLoc ); - if ( l_retCode != fapi2::FAPI2_RC_SUCCESS ) + if ( i_ffdcType & FIR_STATE ) { - FAPI_ERR ( "Error collecting CME State, CME Pos 0x08x", - l_cmePos ); - l_ffdcValdityVect &= ~PPE_STATE_VALID; + bool l_firValid = true; + + l_retCode = collectRegisterData <fapi2::TARGET_TYPE_EX> ( + ex, l_pFirFfdcLoc, fapi2::PM_CME_FIR_REGISTERS ); + if (l_retCode) + { + FAPI_ERR ("CME %d FIR Data collection fail", l_cmePos); + l_firValid = false; + } + // Update CME FIR FFDC + FAPI_TRY ( updateFirFfdcHeader ( + &l_pHomerFfdc->iv_firFfdcRegion.iv_firFfdcHeader[0], + l_cmePos, + l_firValid ) ); + + // Since the top level header FIR Section validity is an aggregate + // of OCC FIR and multiple CME FIRs, it is updated only in OCC plat } - l_retCode = collectTrace( l_pFfdcLoc, ex ); - if( l_retCode ) + if ( i_ffdcType & PPE_HALT_STATE ) { - FAPI_ERR("Error in collecting CME Trace CME Pos 0x%08x", l_cmePos ); - l_ffdcValdityVect &= ~PPE_TRACE_VALID; + l_ffdcValdityVect |= PPE_HALT_STATE_VALID; + l_retCode = readPpeHaltState ( getCmeBaseAddress (l_cmePos), + l_pFfdcLoc ); + if ( l_retCode != fapi2::FAPI2_RC_SUCCESS ) + { + FAPI_ERR ( "Error reading CME Halt State, CME Pos 0x08x", + l_cmePos ); + l_ffdcValdityVect &= ~PPE_HALT_STATE_VALID; + } } - l_retCode = collectGlobals( l_pFfdcLoc, ex ); - - if( l_retCode ) + if ( i_ffdcType & PPE_STATE ) { - FAPI_ERR("Error in collecting CME Globals, CME Pos 0x%08x", l_cmePos ); - l_ffdcValdityVect &= ~PPE_DASHBOARD_VALID; - + l_ffdcValdityVect |= PPE_STATE_VALID; + l_retCode = collectPpeState ( getCmeBaseAddress (l_cmePos), + l_pFfdcLoc ); + if ( l_retCode != fapi2::FAPI2_RC_SUCCESS ) + { + FAPI_ERR ( "Error collecting CME State, CME Pos 0x08x", + l_cmePos ); + l_ffdcValdityVect &= ~PPE_STATE_VALID; + } } - l_retCode = collectImageHeader( l_pFfdcLoc, ex ); - - if( l_retCode ) + if ( i_ffdcType & TRACES ) { - FAPI_ERR("Error in collecting CME Image header, CME Pos 0x%08x", l_cmePos ); - l_ffdcValdityVect &= ~PPE_IMAGE_HEADER_VALID; + l_ffdcValdityVect |= PPE_TRACE_VALID; + l_retCode = collectTrace( l_pFfdcLoc, ex ); + + if( l_retCode ) + { + FAPI_ERR("Error in collecting CME Trace CME Pos 0x%08x", l_cmePos ); + l_ffdcValdityVect &= ~PPE_TRACE_VALID; + } } - l_retCode = collectInternalReg( l_pFfdcLoc, ex , l_cmePos); - - if( l_retCode ) + if ( i_ffdcType & DASH_BOARD_VAR ) { - FAPI_ERR("Error in collecting CME Internal Regs, CME Pos 0x%08x", l_cmePos ); - l_ffdcValdityVect &= ~PPE_INT_REG_VALID; + l_ffdcValdityVect |= PPE_DASHBOARD_VALID; + l_retCode = collectGlobals( l_pFfdcLoc, ex ); + + if( l_retCode ) + { + FAPI_ERR("Error in collecting CME Globals, CME Pos 0x%08x", l_cmePos ); + l_ffdcValdityVect &= ~PPE_DASHBOARD_VALID; + } } + if ( i_ffdcType & IMAGE_HEADER ) + { + l_ffdcValdityVect |= PPE_IMAGE_HEADER_VALID; + l_retCode = collectImageHeader( l_pFfdcLoc, ex ); + + if( l_retCode ) + { + FAPI_ERR("Error in collecting CME Image header, CME Pos 0x%08x", l_cmePos ); + l_ffdcValdityVect &= ~PPE_IMAGE_HEADER_VALID; + } + } + if ( i_ffdcType & INTERNAL_REG ) + { + l_ffdcValdityVect |= PPE_INT_REG_VALID; + l_retCode = collectInternalReg( l_pFfdcLoc, ex , l_cmePos); + + if( l_retCode ) + { + FAPI_ERR("Error in collecting CME Internal Regs, CME Pos 0x%08x", l_cmePos ); + l_ffdcValdityVect &= ~PPE_INT_REG_VALID; + } + } - FAPI_TRY( updateCmeFfdcHeader( l_pFfdcLoc, l_cmePos, l_ffdcValdityVect, l_haltState ), + FAPI_TRY( updateCmeFfdcHeader( l_pFfdcLoc, l_cmePos, l_ffdcValdityVect ), "Failed To Update CME FFDC Header for CME 0x%0d", l_cmePos ); } - fapi_try_exit: + fapi_try_exit: FAPI_DBG("<< PlatCme::collectFfdc"); return fapi2::current_err; } @@ -176,7 +242,7 @@ FFDC_PPE_TRACES_SIZE ), "Trace Collection Failed" ); - fapi_try_exit: + fapi_try_exit: FAPI_DBG("<< PlatCme::collectTrace" ); return fapi2::current_err; } @@ -197,7 +263,7 @@ FFDC_PPE_SCORE_BOARD_SIZE ), "Failed To Collect CME Global Variables" ); - fapi_try_exit: + fapi_try_exit: FAPI_DBG("<< PlatCme::collectGlobals" ); return fapi2::current_err; } @@ -221,7 +287,7 @@ "Failed to collect register data for CME instance %u",i_exPos); - fapi_try_exit: + fapi_try_exit: FAPI_DBG("<< PlatCme::collectInternalReg" ); return fapi2::FAPI2_RC_SUCCESS; } @@ -242,22 +308,22 @@ FFDC_PPE_IMG_HDR_SIZE ), "Failed To Collect CME Image Header" ); - fapi_try_exit: + fapi_try_exit: FAPI_DBG("<< PlatCme::collectImageHeader" ); return fapi2::current_err; } //----------------------------------------------------------------------- - fapi2::ReturnCode PlatCme::updateCmeFfdcHeader( uint8_t * i_pHomerBuf, uint8_t i_cmePos, - uint8_t l_ffdcValdityVect, uint8_t i_haltState ) + fapi2::ReturnCode PlatCme::updateCmeFfdcHeader( uint8_t* i_pHomerBuf, uint8_t i_cmePos, + uint16_t i_sectionsValid ) { FAPI_DBG(">> updateCmeFfdcHeader" ); PpeFfdcHeader * l_pCmeFfdcHdr = ( (PpeFfdcHeader *)(( PpeFfdcHdrRegion * ) i_pHomerBuf )); l_pCmeFfdcHdr->iv_ppeMagicNumber = htobe32(FFDC_CME_MAGIC_NUM); l_pCmeFfdcHdr->iv_ppeNumber = i_cmePos; - PlatPmComplex::updatePpeFfdcHeader( l_pCmeFfdcHdr, l_ffdcValdityVect, i_haltState ); + PlatPmComplex::updatePpeFfdcHeader( l_pCmeFfdcHdr, i_sectionsValid ); FAPI_DBG("<< updateCmeFfdcHeader" ); return fapi2::FAPI2_RC_SUCCESS; @@ -270,10 +336,11 @@ extern "C" { FAPI_IMP(">> p9_pm_recovery_ffdc_cme" ); PlatCme l_cmeFfdc( i_procChip ); - FAPI_TRY( l_cmeFfdc.collectFfdc( i_pFfdcBuf ), + FAPI_TRY( l_cmeFfdc.collectFfdc( i_pFfdcBuf, + (ALL & ~(PPE_HALT_STATE | FIR_STATE))), "Failed To Collect CME FFDC" ); - fapi_try_exit: + fapi_try_exit: FAPI_IMP("<< p9_pm_recovery_ffdc_cme" ); return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.H index 39be147af..f61f22dab 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.H @@ -55,10 +55,17 @@ namespace p9_stop_recov_ffdc /// @brief destructor virtual ~PlatCme() { }; + /// @brief Initializes the CME FFDC Sub-Sections in HOMER with default headers + /// @param[in] i_pHomerBuf points to base of P9 HOMER. + /// @return fapi2 return code + fapi2::ReturnCode init ( void* i_pHomerBuf ); + /// @brief collects FFDC pertaining to all functional CMEs in the chip. - /// @param[in] i_pHomerBuf points to base of P9 HOMER. + /// @param[in] i_pHomerBuf points to base of P9 HOMER. + /// @param[in] i_ffdcType indicates the content type to collect // @return fapi2 return code. - fapi2::ReturnCode collectFfdc( void* i_pHomerBuf ); + fapi2::ReturnCode collectFfdc( void* i_pHomerBuf, + uint8_t i_ffdcType = ALL ); private: /// @brief collects trace info from a given CME SRAM buffer. @@ -90,13 +97,10 @@ namespace p9_stop_recov_ffdc /// @brief updates the CME FFDC Header ///@param[in] i_pHomerBuf points to a location in HOMER meant for CME FFDC Header ///@param[in] i_cmePos position of CME instance - ///param[in] i_ffdcValid bit vector summarizing FFDC validity - ///@param[in] i_haltCondition hlat state of CME + ///param[in] i_sectionsValid bit vector summarizing FFDC validity ///@return fapi2 return code. - ///@note refer to PPE Spec for details on halt state. - - fapi2::ReturnCode updateCmeFfdcHeader( uint8_t * i_pHomerBuf, uint8_t i_cmePos, - uint8_t i_ffdcValid, uint8_t i_haltCondition ); + fapi2::ReturnCode updateCmeFfdcHeader( uint8_t* i_pHomerBuf, uint8_t i_cmePos, + uint16_t i_sectionsValid ); }; extern "C" diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.mk b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.mk index 7cc56b802..d2de53b3f 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.mk +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.mk @@ -25,8 +25,10 @@ PROCEDURE=p9_pm_recovery_ffdc_cme CME_FFDC_INC=$(ROOTPATH)/chips/p9/procedures/hwp/pm/ CME_FFDC_INC+=$(ROOTPATH)/chips/p9/procedures/hwp/lib -lib$(PROCEDURE)_DEPLIBS += p9_pm_recovery_ffdc_base +lib$(PROCEDURE)_DEPLIBS+=p9_pm_recovery_ffdc_base lib$(PROCEDURE)_DEPLIBS+=p9_pm_ocb_indir_setup_linear lib$(PROCEDURE)_DEPLIBS+=p9_cme_sram_access +lib$(PROCEDURE)_DEPLIBS+=p9_ppe_state +lib$(PROCEDURE)_DEPLIBS+=p9_ppe_utils $(call ADD_MODULE_INCDIR,$(CME_FFDC_INC)) $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cppm.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cppm.C index cfa2f5994..ba0d3727c 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cppm.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cppm.C @@ -48,108 +48,135 @@ namespace p9_stop_recov_ffdc { CppmRegs::CppmRegs( const fapi2::Target< fapi2::TARGET_TYPE_PROC_CHIP > i_procChipTgt ) - : PlatPmComplex( i_procChipTgt,0,0,0,PLAT_PPM) + : PlatPmComplex ( i_procChipTgt, PLAT_CPPM ) { } //---------------------------------------------------------------------- - fapi2::ReturnCode CppmRegs::collectRegFfdc( void * i_pHomerBuf ) + fapi2::ReturnCode CppmRegs::init ( void* i_pHomerBuf ) { - FAPI_DBG(">> CppmRegs::collectRegFfdc"); + FAPI_DBG (">> CppmRegs::init" ); + FAPI_TRY ( collectFfdc( i_pHomerBuf, INIT), + "Failed To Init CPPM REGS FFDC" ); + + fapi_try_exit: + FAPI_DBG ("<< CppmRegs::init" ); + return fapi2::current_err; + } + + //---------------------------------------------------------------------- + + fapi2::ReturnCode CppmRegs::collectFfdc( void* i_pHomerBuf, + uint8_t i_ffdcType ) + { + FAPI_DBG(">> CppmRegs::collectFfdc"); fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS; - auto l_quadList = - getProcChip().getChildren< fapi2::TARGET_TYPE_EQ > ( fapi2::TARGET_STATE_PRESENT ); + uint8_t l_quadPos = 0; uint8_t l_corePos = 0; - uint8_t *l_pFfdcLoc = NULL; - uint8_t l_cppmFfdcValid = 0; - uint8_t l_quadFfdcValid = 0; + uint8_t* l_pCppmFfdcLoc = NULL; + uint8_t* l_pQuadFfdcLoc = NULL; + uint16_t l_cppmFfdcValid = 0; + uint16_t l_quadFfdcValid = 0; + HomerFfdcRegion * l_pHomerFfdc = ( HomerFfdcRegion *)( (uint8_t *)i_pHomerBuf + FFDC_REGION_HOMER_BASE_OFFSET ); - for( auto quad : l_quadList ) + auto l_quadList = getProcChip().getChildren<fapi2::TARGET_TYPE_EQ> (fapi2::TARGET_STATE_PRESENT); + + for (auto& quad : l_quadList) { - l_cppmFfdcValid = 0; + // @TODO via RTC 153978: define bitsets for quad sub-section validity l_quadFfdcValid = 0; FAPI_TRY( FAPI_ATTR_GET( fapi2::ATTR_CHIP_UNIT_POS, quad, l_quadPos), "FAPI_ATTR_GET Failed To Read QUAD Position" ); - if( quad.isFunctional() ) + + l_pQuadFfdcLoc = &l_pHomerFfdc->iv_quadFfdc[l_quadPos].iv_quadFfdcHeader[0]; + + // @note: INIT applies to all present units, and is handled as default flow + // @note: CPPM headers for EQs that are not functionals will not be initialized + if (quad.isFunctional()) { l_quadFfdcValid = 1; - auto l_exList = - quad.getChildren< fapi2::TARGET_TYPE_EX > ( fapi2::TARGET_STATE_PRESENT ); + auto l_coreList = + quad.getChildren< fapi2::TARGET_TYPE_CORE > ( fapi2::TARGET_STATE_PRESENT ); - for( auto ex : l_exList ) + for (auto& core : l_coreList) { - auto l_coreList = - ex.getChildren< fapi2::TARGET_TYPE_CORE > ( fapi2::TARGET_STATE_PRESENT ); + FAPI_TRY( FAPI_ATTR_GET( fapi2::ATTR_CHIP_UNIT_POS, core, l_corePos ), + "FAPI_ATTR_GET Failed To Read CORE Position" ); + l_cppmFfdcValid = 0; - for ( auto core : l_coreList ) - { - FAPI_TRY( FAPI_ATTR_GET( fapi2::ATTR_CHIP_UNIT_POS, core, l_corePos ), - "FAPI_ATTR_GET Failed To Read CORE Position" ); + l_pCppmFfdcLoc = &l_pHomerFfdc->iv_quadFfdc[l_quadPos].iv_quadCppmRegion[l_corePos%MAX_CORES_PER_QUAD][0]; - l_pFfdcLoc = &l_pHomerFfdc->iv_quadFfdc[l_quadPos].iv_quadCppmRegion[l_corePos][0]; + // Note: ( i_ffdcType & INIT ) is the default case, for all present cores + if( core.isFunctional() ) + { + FAPI_INF("CPPM FFDC: Quad#%d Core#%d ", l_quadPos, (l_corePos%MAX_CORES_PER_QUAD)); - if( core.isFunctional() ) + if (i_ffdcType & SCOM_REG) { - l_cppmFfdcValid = 1; - - FAPI_INF("CPPM FFDC Pos %d ", l_corePos); - l_rc = collectRegisterData <fapi2::TARGET_TYPE_CORE> (core, - l_pFfdcLoc + sizeof (PpmFfdcHeader), + l_pCppmFfdcLoc + sizeof (PpmFfdcHeader), fapi2::CPPM_FFDC_REGISTERS); - if (l_rc) + if (l_rc == fapi2::FAPI2_RC_SUCCESS) { - l_cppmFfdcValid = 0; + l_cppmFfdcValid = 1; } } - - - FAPI_TRY( updateCppmFfdcHeader( l_pFfdcLoc, l_corePos, l_cppmFfdcValid), - "Failed To Update CPPM FFDC Header for CORE 0x%0d", l_corePos ); } + + FAPI_TRY( updateCppmFfdcHeader( l_pCppmFfdcLoc, l_corePos, l_cppmFfdcValid), + "Failed To Update CPPM FFDC Header for QUAD#%d CORE#%d", l_quadPos, (l_corePos%MAX_CORES_PER_QUAD)); } } - FAPI_TRY( updateQuadFfdcHeader( l_pFfdcLoc,l_quadPos, l_quadFfdcValid), - "Failed To Update CPPM FFDC Header for CORE 0x%0d", l_corePos ); + FAPI_TRY( updateQuadFfdcHeader( l_pQuadFfdcLoc,l_quadPos, l_quadFfdcValid), + "Failed To Update Quad FFDC Header for EQ 0x%0d", l_quadPos ); + + setPmFfdcSectionValid ( i_pHomerBuf, (PM_FFDC_QUAD0_VALID << l_quadPos), l_quadFfdcValid); } - fapi_try_exit: - FAPI_DBG("<< CppmRegs::collectRegFfdc"); + fapi_try_exit: + FAPI_DBG("<< CppmRegs::collectFfdc"); return fapi2::current_err; } - fapi2::ReturnCode CppmRegs::updateCppmFfdcHeader( uint8_t * i_pHomerBuf, - const uint8_t i_corePos, - const uint8_t i_ffdcValid) + //----------------------------------------------------------------------- + + fapi2::ReturnCode CppmRegs::updateCppmFfdcHeader( uint8_t* i_pHomerBuf, + const uint8_t i_corePos, + const uint16_t i_ffdcValid) { FAPI_DBG(">> updateCppmFfdcHeader" ); PpmFfdcHeader * l_CppmFfdcHdr = (PpmFfdcHeader *) i_pHomerBuf ; l_CppmFfdcHdr->iv_ppmMagicWord = htobe32(FFDC_CPPM_MAGIC_NUM); - l_CppmFfdcHdr->iv_Instance = i_corePos; - l_CppmFfdcHdr->iv_ppmHeaderSize = sizeof(PpmFfdcHeader); - l_CppmFfdcHdr->iv_sectionSize = FFDC_CPPM_REGISTERS_SIZE; - l_CppmFfdcHdr->iv_ffdcValid = i_ffdcValid; + l_CppmFfdcHdr->iv_versionMajor = 1; + l_CppmFfdcHdr->iv_versionMinor = 0; + l_CppmFfdcHdr->iv_Instance = i_corePos; // CHIP_UNIT_POS + l_CppmFfdcHdr->iv_ppmHeaderSize = htobe16 (sizeof(PpmFfdcHeader)); + l_CppmFfdcHdr->iv_sectionSize = htobe16 (FFDC_CPPM_REGION_SIZE); + l_CppmFfdcHdr->iv_ffdcValid = htobe16 (i_ffdcValid); FAPI_DBG("<< updateCppmFfdcHeader" ); return fapi2::FAPI2_RC_SUCCESS; } + //----------------------------------------------------------------------- - // - fapi2::ReturnCode CppmRegs::updateQuadFfdcHeader( uint8_t * i_pHomerBuf, - const uint8_t i_eqPos, - const uint8_t i_ffdcValid) + + fapi2::ReturnCode CppmRegs::updateQuadFfdcHeader( uint8_t* i_pHomerBuf, + const uint8_t i_eqPos, + const uint16_t i_ffdcValid) { FAPI_DBG(">> updateQuadFfdcHeader" ); QuadFfdcHeader* l_QuadFfdcHdr = (QuadFfdcHeader*) i_pHomerBuf ; l_QuadFfdcHdr->iv_quadMagicWord = htobe32(FFDC_QUAD_MAGIC_NUM); + l_QuadFfdcHdr->iv_versionMajor = 1; + l_QuadFfdcHdr->iv_versionMinor = 0; l_QuadFfdcHdr->iv_quadInstance = i_eqPos; - l_QuadFfdcHdr->iv_quadHeaderSize = sizeof(QuadFfdcHeader); - l_QuadFfdcHdr->iv_sectionSize = sizeof(HomerQuadFfdcRegion); + l_QuadFfdcHdr->iv_quadHeaderSize = htobe16 (sizeof(QuadFfdcHeader)); + l_QuadFfdcHdr->iv_sectionSize = htobe16 (sizeof(HomerQuadFfdcRegion)); l_QuadFfdcHdr->iv_offsetCppm0 = htobe16(offsetof (struct HomerQuadFfdcRegion, iv_quadCppmRegion[0][0])); l_QuadFfdcHdr->iv_offsetCppm1 = htobe16(offsetof (struct HomerQuadFfdcRegion, @@ -164,7 +191,7 @@ iv_quadCmeBlock[1][0])); l_QuadFfdcHdr->iv_offsetQppm = htobe16(offsetof(struct HomerQuadFfdcRegion, iv_quadQppmRegion[0])); - l_QuadFfdcHdr->iv_ffdcValid = i_ffdcValid; + l_QuadFfdcHdr->iv_sectionsValid = htobe16 (i_ffdcValid); FAPI_DBG("<< updateQuadFfdcHeader" ); return fapi2::FAPI2_RC_SUCCESS; @@ -177,7 +204,7 @@ extern "C" { FAPI_IMP(">> p9_pm_recovery_ffdc_cppm" ); CppmRegs l_cppmFfdc( i_procChip ); - FAPI_TRY( l_cppmFfdc.collectRegFfdc( i_pFfdcBuf ), + FAPI_TRY( l_cppmFfdc.collectFfdc( i_pFfdcBuf, SCOM_REG ), "Failed To Collect CPPM FFDC" ); fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cppm.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cppm.H index ffd72dca3..ec8db9455 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cppm.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cppm.H @@ -55,28 +55,37 @@ namespace p9_stop_recov_ffdc /// @brief destructor virtual ~CppmRegs () { }; - /// @brief collects Register FFDC pertaining to all functional cores in the chip. + /// @brief Initializes the Quad and CPPM FFDC Sub-Sections in HOMER with default headers + /// @param[in] i_pHomerBuf points to base of P9 HOMER. + /// @return fapi2 return code + fapi2::ReturnCode init ( void* i_pHomerBuf ); + + /// @brief collects FFDC pertaining to all functional cores in the chip. /// @param[in] i_pHomerBuf points to base of P9 HOMER. + /// @param[in] i_ffdcType indicates the content type to collect // @return fapi2 return code. - fapi2::ReturnCode collectRegFfdc( void* i_pHomerBuf ); + fapi2::ReturnCode collectFfdc ( void* i_pHomerBuf, + uint8_t i_ffdcType = ALL ); private: /// @brief updates the CPPM FFDC Header ///@param[in] i_pHomerBuf points to a location in HOMER meant for CPPM Header ///@param[in] i_CppmInstance CPPM instance + ///@param[in] i_ffdcValid non-zero indicates the CPPM FFDC is valid ///@return fapi2 return code. fapi2::ReturnCode updateCppmFfdcHeader( uint8_t * i_pHomerBuf, const uint8_t i_cppmInstance, - const uint8_t i_ffdcValid); + const uint16_t i_ffdcValid); /// @brief updates the QUAD FFDC Header - ///@param[in] i_pHomerBuf points to a location in HOMER meant for CPPM Header + ///@param[in] i_pHomerBuf points to a location in HOMER meant for Quad Header ///@param[in] i_quadInstance Quad instance + ///@param[in] i_ffdcValid non-zero indicates the Quad FFDC is valid ///@return fapi2 return code. fapi2::ReturnCode updateQuadFfdcHeader( uint8_t * i_pHomerBuf, const uint8_t i_quadInstance, - const uint8_t i_ffdcValid); + const uint16_t i_ffdcValid); }; extern "C" diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_defines.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_defines.H index 6a9e02852..502dbbac7 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_defines.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_defines.H @@ -39,15 +39,43 @@ namespace p9_stop_recov_ffdc { /** + * @brief enumerates all the sub-steps in a PM Reset Flow + */ +enum PmResetStep +{ + PM_RESET_UNKNOWN = 0, + PM_RESET_FFDC_SEC_INIT, + PM_RESET_FFDC_CHK_PPE_HALT, + PM_RESET_FFDC_GET_FIRS, + PM_RESET_FIR_OCC, + PM_RESET_OCC_CTRL, + PM_RESET_SPL_WKUP_EX_ALL, + PM_RESET_FIR_PBA, + PM_RESET_FIR_PPM, + PM_RESET_FIR_CME, + PM_RESET_OCC_GPE, + PM_RESET_PGPE, + PM_RESET_SGPE, + PM_RESET_EC_EQ, + PM_RESET_DISABLE_RES_CLKS, + PM_RESET_OCC_SRAM, + PM_RESET_OCB, + PM_RESET_PSS, + PM_RESET_MAX +}; + +/** * @brief enumerates all the platforms involved with STOP Recovery. */ enum PmComplexPlatId { + PLAT_NONE = 0x00, PLAT_CME = 0x01, PLAT_SGPE = 0x02, PLAT_PGPE = 0x03, PLAT_OCC = 0x04, - PLAT_PPM = 0x05, + PLAT_CPPM = 0x05, + PLAT_QPPM = 0x06, }; /** @@ -55,11 +83,51 @@ enum PmComplexPlatId */ enum FfdcDataType { - IMAGE_HEADER = 0x01, - DASH_BOARD_VAR = 0x02, - TRACES = 0x03, - INTERNAL_REG = 0x04, - SCOM_REG = 0x05, + INIT = 0x00, // initializes FFDC section headers + IMAGE_HEADER = 0x01, // collect PPE SRAM Image Header + DASH_BOARD_VAR = 0x02, // collect PPE GLobal Variables / Dash + TRACES = 0x04, // collect FW traces from SRAM + INTERNAL_REG = 0x08, // collect internal regsiters + SCOM_REG = 0x10, // collect SCOM registers + PPE_STATE = 0x20, // collect PPE SPRs, XIRs, and GPRs + PPE_HALT_STATE = 0x40, // collect the PPE Engine HALT State + FIR_STATE = 0x80, + ALL = ( IMAGE_HEADER | + DASH_BOARD_VAR | + TRACES | + INTERNAL_REG | + SCOM_REG | + PPE_STATE | + PPE_HALT_STATE | + FIR_STATE) +}; + +/** + * @brief enumerates bit positions used to mark sections in PM FFDC as valid + */ +enum PmFfdcSectionState +{ + PM_FFDC_INVALID = 0x0000, // none of the sections is valid + PM_FFDC_FIR_VALID = 0x0001, // fir section valid + PM_FFDC_QUAD0_VALID = 0x0002, // quad 0 section valid + PM_FFDC_QUAD1_VALID = 0x0004, // quad 1 section valid + PM_FFDC_QUAD2_VALID = 0x0008, // quad 2 section valid + PM_FFDC_QUAD3_VALID = 0x0010, // quad 3 section valid + PM_FFDC_QUAD4_VALID = 0x0020, // quad 4 section valid + PM_FFDC_QUAD5_VALID = 0x0040, // quad 5 section valid + PM_FFDC_SGPE_VALID = 0x0080, // sgpe section valid + PM_FFDC_PGPE_VALID = 0x0100, // pgpe section valid + PM_FFDC_OCC_VALID = 0x0200, // occ section valid + PM_FFDC_VALID_ALL = ( PM_FFDC_FIR_VALID | + PM_FFDC_QUAD0_VALID | + PM_FFDC_QUAD1_VALID | + PM_FFDC_QUAD2_VALID | + PM_FFDC_QUAD3_VALID | + PM_FFDC_QUAD4_VALID | + PM_FFDC_QUAD5_VALID | + PM_FFDC_SGPE_VALID | + PM_FFDC_PGPE_VALID | + PM_FFDC_OCC_VALID ) }; /** @@ -68,14 +136,14 @@ enum FfdcDataType enum PpeFfdcValidStatus { - PPE_FFDC_INVALID = 0x00, //entire PPE FFDC is not valid - PPE_DASHBOARD_VALID = 0x01, // PPE globals are valid - PPE_IMAGE_HEADER_VALID = 0x02, // PPE image header is valid - PPE_TRACE_VALID = 0x04, // PPE Traces are valid - PPE_STATE_VALID = 0x08, // PPE XIRS, GPES and SPRs are valid - PPE_INT_REG_VALID = 0x10, // PPE Int Regs are valid - PPE_HALT_STATE_VALID = 0x20, // PPE Halt State Info is valid - PPE_FFDC_ALL_VALID = 0x3F, // Entire PPE FFDC is valid + PPE_FFDC_INVALID = 0x0000, //entire PPE FFDC is not valid + PPE_DASHBOARD_VALID = 0x0001, // PPE globals are valid + PPE_IMAGE_HEADER_VALID = 0x0002, // PPE image header is valid + PPE_TRACE_VALID = 0x0004, // PPE Traces are valid + PPE_STATE_VALID = 0x0008, // PPE XIRS, GPES and SPRs are valid + PPE_INT_REG_VALID = 0x0010, // PPE Int Regs are valid + PPE_HALT_STATE_VALID = 0x0020, // PPE Halt State Info is valid + PPE_FFDC_ALL_VALID = 0x003F, // Entire PPE FFDC is valid }; /** @@ -95,23 +163,50 @@ enum PpeHaltCondition PPE_HALT_COND_UNKNOWN = 0xFF // Could not read or interpret XSR }; + +/** + * @brief Top level header of the PM Complex FFDC in HOMER + */ +struct __attribute__((packed)) PmFfdcHeader +{ + uint32_t iv_magicNumber; // Magic Word of Top Level PM FFDC + uint8_t iv_versionMajor; // Major Version of the Layout Header + uint8_t iv_versionMinor; // Minor Version of the Layout Header + uint16_t iv_headerSize; // Size of this Header + uint32_t iv_sectionSize; // Size of complete PM FFDC mapped by this + uint8_t iv_ffdcValid; // Validity of the complete PM FFDC + uint8_t iv_phase; // Last executed step in PM Reset + uint16_t iv_sectionsValid; // See PmFfdcSectionState + uint32_t iv_procPosition; // Logical position of Proc Chip in system + uint16_t iv_errorMarker; // High level error marker + uint16_t iv_firOffset; // Offset to FIR FFDC sub-section + uint16_t iv_quadOffset[MAX_QUADS_PER_CHIP]; // Offset to Quad subsections + uint16_t iv_sgpeOffset; // Offset to the SGPE FFDC sub-section + uint16_t iv_pgpeOffset; // Offset to the PGPE FFDC sub-section + uint16_t iv_occOffset; // Offset to the OCC FFDC sub-section + uint8_t iv_reserved[6]; // Reserved + uint32_t iv_ccsr; // CCSR on PM Reset entry + uint32_t iv_qcsr; // QCSR on PM Reset entry +}; + /** * @brief models header of FFDC region of HOMER associated with a CME. */ struct __attribute__((packed)) PpeFfdcHeader { uint32_t iv_ppeMagicNumber; - uint8_t iv_ppeNumber; - uint8_t iv_headerSize; + uint8_t iv_versionMajor; + uint8_t iv_versionMinor; + uint16_t iv_headerSize; uint16_t iv_sectionSize; - uint8_t iv_ffdcValid; + uint16_t iv_sectionsValid; + uint8_t iv_ppeNumber; uint8_t iv_ppeHaltCondition; uint16_t iv_dashBoardOffset; uint16_t iv_sramHeaderOffset; uint16_t iv_sprOffset; uint16_t iv_intRegOffset; uint16_t iv_offsetTraces; - uint8_t iv_reserve[4]; }; /** @@ -120,9 +215,13 @@ struct __attribute__((packed)) PpeFfdcHeader struct __attribute__((packed)) QuadFfdcHeader { uint32_t iv_quadMagicWord; - uint8_t iv_quadInstance; - uint8_t iv_quadHeaderSize; + uint8_t iv_versionMajor; + uint8_t iv_versionMinor; + uint16_t iv_quadHeaderSize; uint16_t iv_sectionSize; + uint16_t iv_sectionsValid; + uint8_t iv_reserve1; + uint8_t iv_quadInstance; uint16_t iv_offsetCppm0; uint16_t iv_offsetCppm1; uint16_t iv_offsetCppm2; @@ -130,8 +229,7 @@ struct __attribute__((packed)) QuadFfdcHeader uint16_t iv_offsetCme0; uint16_t iv_offsetCme1; uint16_t iv_offsetQppm; - uint8_t iv_ffdcValid; - uint8_t iv_reserve; + uint8_t iv_reserve2[4]; }; @@ -140,37 +238,60 @@ struct __attribute__((packed)) QuadFfdcHeader */ enum OccFfdcValidStatus { - OCC_FFDC_INVALID = 0x00, // None of the FFDC section is valid - OCC_FFDC_TRACE_ERR_VALID = 0x01, // OCC ERR traces section valid - OCC_FFDC_TRACE_IMP_VALID = 0x02, // OCC IMP traces section valid - OCC_FFDC_TRACE_INF_VALID = 0x04, // OCC INF traces section valid - OCC_FFDC_TRACE_SSX_VALID = 0x08, // OCC SSX trace section valid - OCC_FFDC_TRACE_GPE0_VALID = 0x10, // OCC GPE0 Trace Section valid - OCC_FFDC_TRACE_GPE1_VALID = 0x20, // OCC GPE1 Trace Section Valid - OCC_FFDC_SHARED_REGION_VALID = 0x40, // OCC Shared Region Section valid - OCC_FFDC_REGISTERS_VALID = 0x80, // OCC Register Section valid - OCC_FFDC_VALID_ALL = ( OCC_FFDC_TRACE_ERR_VALID | - OCC_FFDC_TRACE_IMP_VALID | - OCC_FFDC_TRACE_INF_VALID | - OCC_FFDC_TRACE_SSX_VALID | - OCC_FFDC_TRACE_GPE0_VALID | - OCC_FFDC_TRACE_GPE1_VALID | - OCC_FFDC_SHARED_REGION_VALID | - OCC_FFDC_REGISTERS_VALID ) + OCC_FFDC_INVALID = 0x0000, // None of the FFDC section is valid + OCC_FFDC_TRACE_ERR = 0x0001, // OCC ERR traces section valid + OCC_FFDC_TRACE_IMP = 0x0002, // OCC IMP traces section valid + OCC_FFDC_TRACE_INF = 0x0004, // OCC INF traces section valid + OCC_FFDC_TRACE_SSX = 0x0008, // OCC SSX trace section valid + OCC_FFDC_TRACE_GPE0 = 0x0010, // OCC GPE0 Trace Section valid + OCC_FFDC_TRACE_GPE1 = 0x0020, // OCC GPE1 Trace Section Valid + OCC_FFDC_SHARED_REGION = 0x0040, // OCC Shared Region Section valid + OCC_FFDC_REGISTERS = 0x0080, // OCC Register Section valid + OCC_FFDC_VALID_ALL = ( OCC_FFDC_TRACE_ERR | + OCC_FFDC_TRACE_IMP | + OCC_FFDC_TRACE_INF | + OCC_FFDC_TRACE_SSX | + OCC_FFDC_TRACE_GPE0 | + OCC_FFDC_TRACE_GPE1 | + OCC_FFDC_SHARED_REGION | + OCC_FFDC_REGISTERS) }; /** + * @brief models FIR FFDC header. + * @note iv_validityVector bits 0:11 => CME0:11 FIR valid + * bit 12 => OCC FIRs valid + * bits 13:15 => Reserved + */ +const uint16_t PM_FFDC_FIR_VALID_POS_0 = 0x8000; +const uint8_t PM_FFDC_FIR_VALID_POS_MAX = 13; +const uint8_t PM_FFDC_FIR_VALID_POS_OCC = 12; + +struct __attribute__((packed)) FirFfdcHeader +{ + uint32_t iv_magicWord; + uint8_t iv_versionMajor; + uint8_t iv_versionMinor; + uint16_t iv_headerSize; + uint16_t iv_sectionSize; + uint16_t iv_validityVector; // See note in doxygen above + uint8_t iv_reserved[4]; +}; + +/** * @brief models C_Q_PPM FFDC header. */ struct __attribute__((packed)) PpmFfdcHeader { uint32_t iv_ppmMagicWord; - uint8_t iv_Instance; - uint8_t iv_ppmHeaderSize; + uint8_t iv_versionMajor; + uint8_t iv_versionMinor; + uint16_t iv_ppmHeaderSize; uint16_t iv_sectionSize; - uint8_t iv_ffdcValid; - uint8_t iv_reserved[7]; + uint16_t iv_ffdcValid; + uint8_t iv_Instance; + uint8_t iv_reserved[3]; }; /** @@ -179,9 +300,11 @@ struct __attribute__((packed)) PpmFfdcHeader struct __attribute__((packed)) OccFfdcHeader { uint32_t iv_magicWord; - uint8_t iv_ffdcValid; - uint8_t iv_headerSize; + uint8_t iv_versionMajor; + uint8_t iv_versionMinor; + uint16_t iv_headerSize; uint16_t iv_sectionSize; + uint16_t iv_sectionsValid; uint16_t iv_offsetErrTrace; uint16_t iv_offsetImpTrace; uint16_t iv_offsetInfTrace; @@ -190,6 +313,16 @@ struct __attribute__((packed)) OccFfdcHeader uint16_t iv_offsetGpe1Trace; uint16_t iv_offsetSharedSram; uint16_t iv_offsetOccRegs; + uint8_t iv_reserved[4]; +}; + +/** + * @brief PM FFDC section header area + */ +union PmFfdcHdrRegion +{ + uint8_t iv_pmFfdcHdrArea[FFDC_PM_HEADER_SIZE]; + PmFfdcHeader iv_pmFfdcHdr; }; /** @@ -231,9 +364,9 @@ struct __attribute__((packed)) PpeFfdcLayout struct __attribute__((packed)) HomerQuadFfdcRegion { uint8_t iv_quadFfdcHeader[FFDC_QUAD_HDR_SIZE]; - uint8_t iv_quadCppmRegion[MAX_CORES_PER_QUAD][FFDC_CPPM_REGISTERS_SIZE]; + uint8_t iv_quadCppmRegion[MAX_CORES_PER_QUAD][FFDC_CPPM_REGION_SIZE]; uint8_t iv_quadCmeBlock[MAX_CMES_PER_QUAD][FFDC_PPE_BLOCK_SIZE]; - uint8_t iv_quadQppmRegion[FFDC_QPPM_REGISTERS_SIZE]; + uint8_t iv_quadQppmRegion[FFDC_QPPM_REGION_SIZE]; }; /** @@ -253,11 +386,22 @@ struct __attribute__((packed)) OccFfdcRegion }; /** + * @brief models Quad FFDC region of HOMER. + */ +struct __attribute__((packed)) FirFfdcRegion +{ + uint8_t iv_firFfdcHeader[FFDC_FIR_HDR_SIZE]; + uint8_t iv_firCmeBlock[MAX_CMES_PER_CHIP][FFDC_CME_FIR_REGISTERS_SIZE]; + uint8_t iv_OccPbaBlock[FFDC_FIR_REGISTER_SIZE]; +}; + +/** * @brief models full FFDC region of HOMER. */ struct __attribute__((packed)) HomerFfdcRegion { - uint8_t iv_homerFfdcHeader[FFDC_HOMER_TOP_HEADER]; + PmFfdcHdrRegion iv_pmFfdcHdrRegion; + FirFfdcRegion iv_firFfdcRegion; HomerQuadFfdcRegion iv_quadFfdc[MAX_QUADS_PER_CHIP]; PpeFfdcLayout iv_sgpeFfdcRegion; PpeFfdcLayout iv_pgpeFfdcRegion; diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.C index 2921efe67..a2dd3ab58 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.C @@ -46,99 +46,217 @@ #include <stddef.h> #include <endian.h> - namespace p9_stop_recov_ffdc - { +namespace p9_stop_recov_ffdc +{ PlatOcc::PlatOcc ( const fapi2::Target< fapi2::TARGET_TYPE_PROC_CHIP > i_procChipTgt ) : - PlatPmComplex(i_procChipTgt, 0, 0, 0, PLAT_OCC) + PlatPmComplex ( i_procChipTgt, PLAT_OCC ) { } //---------------------------------------------------------------------- - fapi2::ReturnCode PlatOcc::collectFfdc( void * i_pHomerBuf ) + fapi2::ReturnCode PlatOcc::init ( void* i_pHomerBuf ) + { + FAPI_DBG (">> PlatOcc::init" ); + FAPI_TRY ( collectFfdc( i_pHomerBuf, INIT), + "Failed To init OCC FFDC" ); + + fapi_try_exit: + FAPI_DBG ("<< PlatOcc::init" ); + return fapi2::current_err; + } + + //---------------------------------------------------------------------- + + fapi2::ReturnCode PlatOcc::collectFfdc( void* i_pHomerBuf, + uint8_t i_ffdcType ) { FAPI_DBG(">> PlatOcc::collectFfdc"); fapi2::ReturnCode l_retCode = fapi2::FAPI2_RC_SUCCESS; - uint8_t l_ffdcValid = OCC_FFDC_INVALID; uint8_t* l_pFfdcLoc = NULL; HomerFfdcRegion* l_pHomerFfdc = (HomerFfdcRegion*) ((uint8_t*) i_pHomerBuf + FFDC_REGION_HOMER_BASE_OFFSET ); l_pFfdcLoc = (uint8_t*) (&l_pHomerFfdc->iv_occFfdcRegion); + OccFfdcHeader* l_pOccFfdcHdr = ((OccFfdcHeader*) + ((OccFfdcHdrRegion*) l_pFfdcLoc)); + uint16_t l_ffdcValid = l_pOccFfdcHdr->iv_sectionsValid; + + if ( i_ffdcType & INIT ) + { // overwrite validity of OOC section header on init + l_ffdcValid = OCC_FFDC_INVALID; + // Mark OCC FIR FFDC bit as invalid on init + FAPI_TRY ( updateFirFfdcHeader ( + &l_pHomerFfdc->iv_firFfdcRegion.iv_firFfdcHeader[0], + PM_FFDC_FIR_VALID_POS_OCC, + false ) ); + // Update validity in top level header + setPmFfdcSectionValid (i_pHomerBuf, (PM_FFDC_OCC_VALID | PM_FFDC_FIR_VALID), false); + } - l_retCode = collectTrace (l_pFfdcLoc, OCC_SRAM_TRACE_BUF_BASE_ERR); - if( l_retCode ) + if ( i_ffdcType & FIR_STATE ) { - FAPI_ERR ("Error collecting OCC ERR Traces"); + bool l_firValid = true; + + l_retCode = collectRegisterData <fapi2::TARGET_TYPE_PROC_CHIP> ( + getProcChip(), + &l_pHomerFfdc->iv_firFfdcRegion.iv_OccPbaBlock[0], + fapi2::PM_FIR_REGISTERS ); + if (l_retCode) + { + FAPI_ERR ("OCC FIR Data collection fail"); + l_firValid = false; + } + // Update FIR FFDC header with the OCC FIR validity status + FAPI_TRY ( updateFirFfdcHeader ( + &l_pHomerFfdc->iv_firFfdcRegion.iv_firFfdcHeader[0], + PM_FFDC_FIR_VALID_POS_OCC, + l_firValid ) ); + + setPmFfdcSectionValid (i_pHomerBuf, PM_FFDC_FIR_VALID); } - l_ffdcValid |= OCC_FFDC_TRACE_ERR_VALID; - l_retCode = collectTrace (l_pFfdcLoc, OCC_SRAM_TRACE_BUF_BASE_IMP); - if( l_retCode ) + if ( i_ffdcType & TRACES ) { - FAPI_ERR ("Error collecting OCC IMP Traces"); + l_ffdcValid |= OCC_FFDC_TRACE_ERR; + l_retCode = collectTrace (l_pFfdcLoc, OCC_FFDC_TRACE_ERR); + if( l_retCode ) + { + FAPI_ERR ("Error collecting OCC ERR Traces"); + l_ffdcValid &= ~OCC_FFDC_TRACE_ERR; + } + + l_ffdcValid |= OCC_FFDC_TRACE_IMP; + l_retCode = collectTrace (l_pFfdcLoc, OCC_FFDC_TRACE_IMP); + if( l_retCode ) + { + FAPI_ERR ("Error collecting OCC IMP Traces"); + l_ffdcValid &= ~OCC_FFDC_TRACE_IMP; + } + + l_ffdcValid |= OCC_FFDC_TRACE_INF; + l_retCode = collectTrace (l_pFfdcLoc, OCC_FFDC_TRACE_INF); + if( l_retCode ) + { + FAPI_ERR ("Error collecting OCC INF Traces"); + l_ffdcValid &= ~OCC_FFDC_TRACE_INF; + } + + // OCC team has not yet enabled SSX tracing + // Avoid collecting unknown data from SRAM until it is enabled +#if 0 + l_ffdcValid |= OCC_FFDC_TRACE_SSX; + l_retCode = readSramRegion (l_pFfdcLoc, OCC_FFDC_TRACE_SSX); + if ( l_retCode ) + { + FAPI_ERR ("Error collecting OCC SSX Traces"); + l_ffdcValid &= ~OCC_FFDC_TRACE_SSX; + } +#endif + + l_ffdcValid |= OCC_FFDC_TRACE_GPE0; + l_retCode = readSramRegion (l_pFfdcLoc, OCC_FFDC_TRACE_GPE0); + if ( l_retCode ) + { + FAPI_ERR ("Error collecting GPE0 Traces"); + l_ffdcValid &= ~OCC_FFDC_TRACE_GPE0; + } + + l_ffdcValid |= OCC_FFDC_TRACE_GPE1; + l_retCode = readSramRegion (l_pFfdcLoc, OCC_FFDC_TRACE_GPE1); + if ( l_retCode ) + { + FAPI_ERR ("Error collecting GPE1 Traces"); + l_ffdcValid &= ~OCC_FFDC_TRACE_GPE1; + } + + l_ffdcValid |= OCC_FFDC_SHARED_REGION; + l_retCode = readSramRegion (l_pFfdcLoc, OCC_FFDC_SHARED_REGION); + if ( l_retCode ) + { + FAPI_ERR ("Error collecting OCC Shared Region"); + l_ffdcValid &= ~OCC_FFDC_SHARED_REGION; + } + setPmFfdcSectionValid (i_pHomerBuf, PM_FFDC_OCC_VALID); } - l_ffdcValid |= OCC_FFDC_TRACE_IMP_VALID; - l_retCode = collectTrace (l_pFfdcLoc, OCC_SRAM_TRACE_BUF_BASE_INF); - if( l_retCode ) + if ( i_ffdcType & SCOM_REG ) { - FAPI_ERR ("Error collecting OCC INF Traces"); + l_ffdcValid |= OCC_FFDC_REGISTERS; + l_retCode = collectOccReg( l_pFfdcLoc); + + if( l_retCode ) + { + FAPI_ERR("Error in collecting OCC scom Regs"); + l_ffdcValid &= ~OCC_FFDC_REGISTERS; + } + setPmFfdcSectionValid (i_pHomerBuf, PM_FFDC_OCC_VALID); } - l_ffdcValid |= OCC_FFDC_TRACE_INF_VALID; - - // @TODO Read SRAM for Base and Size of other undefined regions - // before collectTrace - - // @TODO Collect OCC Registers FAPI_TRY( updateOccFfdcHeader( l_pFfdcLoc, l_ffdcValid ), "Failed To Update OCC FFDC Header for OCC" ); fapi_try_exit: - FAPI_DBG("<< PlatSgpe::collectFfdc"); + FAPI_DBG("<< PlatOcc::collectFfdc"); + return fapi2::current_err; + } + + //----------------------------------------------------------------------- + + fapi2::ReturnCode PlatOcc::collectOccReg( uint8_t * i_pOccReg) + { + FAPI_DBG(">> PlatOcc::collectOccReg" ); + + OccFfdcRegion* l_pOccFfdc = ( OccFfdcRegion*) (i_pOccReg); + uint8_t * l_pRegs = &l_pOccFfdc->iv_occRegs[0]; + + FAPI_TRY(collectRegisterData<fapi2::TARGET_TYPE_PROC_CHIP> (getProcChip(), + l_pRegs, + static_cast<fapi2::HwpFfdcId>(fapi2::OCC_FFDC_REGISTERS)), + "Failed to collect register data for OCC "); + + + fapi_try_exit: + FAPI_DBG("<< PlatOcc::collectOccReg" ); return fapi2::current_err; } //----------------------------------------------------------------------- fapi2::ReturnCode PlatOcc::collectTrace ( uint8_t* i_pTraceBuf, - uint32_t i_sramAddr ) + uint8_t i_occSramRegion ) { - FAPI_DBG ( ">> PlatOcc::collectTrace: 0x%08X", - i_sramAddr ); + FAPI_DBG ( ">> PlatOcc::collectTrace: 0x%02X", i_occSramRegion ); OccFfdcRegion* l_pOccFfdc = ( OccFfdcRegion*) (i_pTraceBuf); uint8_t* l_pTraceLoc = NULL; uint32_t l_len = 0; + uint32_t l_sramAddr = 0; - switch (i_sramAddr) + switch ( i_occSramRegion ) { - case OCC_SRAM_TRACE_BUF_BASE_ERR: + case OCC_FFDC_TRACE_ERR: l_pTraceLoc = &l_pOccFfdc->iv_occTraceErr[0]; - setTraceBufAddr (OCC_SRAM_TRACE_BUF_BASE_ERR); + l_sramAddr = OCC_SRAM_TRACE_BUF_BASE_ERR; l_len = FFDC_TRACE_ERR_SIZE; break; - case OCC_SRAM_TRACE_BUF_BASE_INF: - l_pTraceLoc = &l_pOccFfdc->iv_occTraceInf[0]; - setTraceBufAddr (OCC_SRAM_TRACE_BUF_BASE_INF); + case OCC_FFDC_TRACE_INF: + l_pTraceLoc = &l_pOccFfdc->iv_occTraceInf[0]; + l_sramAddr = OCC_SRAM_TRACE_BUF_BASE_INF; l_len = FFDC_TRACE_INF_SIZE; break; - case OCC_SRAM_TRACE_BUF_BASE_IMP: + case OCC_FFDC_TRACE_IMP: l_pTraceLoc = &l_pOccFfdc->iv_occTraceImp[0]; - setTraceBufAddr (OCC_SRAM_TRACE_BUF_BASE_IMP); + l_sramAddr = OCC_SRAM_TRACE_BUF_BASE_IMP; l_len = FFDC_TRACE_IMP_SIZE; break; - // @TODO will have to collect other OCC SRAM regions once - // the util to read and get base + size is done - default: FAPI_ERR ( "PlatOcc::collectTrace Unknown Address! 0x%08X", - i_sramAddr ); + l_sramAddr ); // this is likely a code bug, but the overall ffdc flow // must carry on, so we do not break with an error break; @@ -146,12 +264,13 @@ if ( l_len != 0 ) { + setTraceBufAddr (l_sramAddr); FAPI_TRY ( collectSramInfo ( getProcChip(), l_pTraceLoc, TRACES, l_len ), "::collectTrace Failed Addr: 0x%08X Len: %lu bytes", - i_sramAddr, l_len ); + l_sramAddr, l_len ); } fapi_try_exit: @@ -161,17 +280,131 @@ //-------------------------------------------------------------------------- + fapi2::ReturnCode PlatOcc::readSramRegion ( uint8_t* i_pHomerBuf, + uint8_t i_occSramRegion ) + { + FAPI_DBG ( ">> PlatOcc::readSramRegion: 0x%02X", i_occSramRegion ); + + OccFfdcRegion* l_pOccFfdc = ( OccFfdcRegion*) (i_pHomerBuf); + uint8_t* l_pLoc = NULL; + uint32_t l_len = 0; + uint32_t l_sramAddr = 0; + + switch ( i_occSramRegion ) + { + case OCC_FFDC_TRACE_SSX: + l_pLoc = &l_pOccFfdc->iv_occTraceSsx[0]; + l_sramAddr = OCC_SRAM_TRACE_BUF_BASE_SSX_PTR; + break; + + case OCC_FFDC_TRACE_GPE0: + l_pLoc = &l_pOccFfdc->iv_occTraceGpe0[0]; + l_sramAddr = GPE0_SRAM_BASE_ADDR + GPE_DEBUG_PTR_OFFSET; + break; + + case OCC_FFDC_TRACE_GPE1: + l_pLoc = &l_pOccFfdc->iv_occTraceGpe1[0]; + l_sramAddr = GPE1_SRAM_BASE_ADDR + GPE_DEBUG_PTR_OFFSET; + break; + + case OCC_FFDC_SHARED_REGION: + l_pLoc = &l_pOccFfdc->iv_occSharedSram[0]; + l_sramAddr = OCC_SRAM_PGPE_HEADER_ADDR + + PGPE_SHARED_SRAM_ADDR_BYTE; + break; + + default: + FAPI_ERR ( "PlatOcc::readSramRegion Unknown Address! 0x%08X", + l_sramAddr ); + break; + } + + // For regions where the start and size are not pre-defined + // read the start address and size of the region from SRAM. + // The start address and size are expected to be 4 byte apart + fapi2::variable_buffer l_buf (128); + uint32_t l_sramSize = 0; + + // Read from an 8B aligned address and adjust data accordingly + uint32_t l_bytesToAlign = l_sramAddr & 0x7UL; + uint32_t l_bitStartPos = l_bytesToAlign * 8; + + FAPI_DBG ("SRAM Region Params: %d Addr: 0x%08X Aligned Addr: 0x%08X", + i_occSramRegion, l_sramAddr, (l_sramAddr-l_bytesToAlign)); + l_sramAddr -= l_bytesToAlign; + setTraceBufAddr (l_sramAddr); + + // Read 16 bytes from SRAM + FAPI_TRY ( collectSramInfo ( + getProcChip (), + reinterpret_cast<uint8_t*>(l_buf.pointer()), + TRACES, + 16 ) ); + + // Get the read data at an offset based on the aligned address + FAPI_TRY (l_buf.extract (l_sramAddr, l_bitStartPos, 32)); + FAPI_TRY (l_buf.extract (l_sramSize, (l_bitStartPos+64), 32)); + + FAPI_INF ("SRAM Region: 0x%08X Addr: 0x%08X Size: %d bytes", + i_occSramRegion, l_sramAddr, l_sramSize); + + // Ensure size of the region is not overshooting its budget in HOMER + switch (i_occSramRegion) + { + case OCC_FFDC_TRACE_SSX: + l_len = (l_sramSize > FFDC_TRACE_SSX_SIZE) ? + FFDC_TRACE_SSX_SIZE : l_sramSize; + break; + case OCC_FFDC_TRACE_GPE0: + l_len = (l_sramSize > FFDC_TRACE_GPE0_SIZE) ? + FFDC_TRACE_GPE0_SIZE : l_sramSize; + break; + case OCC_FFDC_TRACE_GPE1: + l_len = (l_sramSize > FFDC_TRACE_GPE1_SIZE) ? + FFDC_TRACE_GPE1_SIZE : l_sramSize; + break; + case OCC_FFDC_SHARED_REGION: + l_len = (l_sramSize > FFDC_SHARED_SRAM_SIZE) ? + FFDC_SHARED_SRAM_SIZE : l_sramSize; + break; + default: + FAPI_ERR ( "PlatOcc::readSramRegion bad region! 0x%08X", + i_occSramRegion); + l_len = 0; + break; + } + + if ( l_len != 0 ) + { + setTraceBufAddr (l_sramAddr); + FAPI_TRY ( collectSramInfo ( getProcChip(), + l_pLoc, + TRACES, + l_len ), + "::readSramRegion Failed Addr: 0x%08X Len: %lu bytes", + l_sramAddr, l_len ); + } + + fapi_try_exit: + FAPI_DBG("<< PlatOcc::readSramRegion" ); + return fapi2::current_err; + } + + //-------------------------------------------------------------------------- + fapi2::ReturnCode PlatOcc::updateOccFfdcHeader ( uint8_t * i_pHomerBuf, - uint8_t i_ffdcValid ) + uint16_t i_ffdcValid ) { FAPI_DBG(">> updateOccFfdcHeader" ); OccFfdcHeader* l_pOccFfdcHdr = ((OccFfdcHeader*) ((OccFfdcHdrRegion*) i_pHomerBuf)); l_pOccFfdcHdr->iv_magicWord = htobe32( FFDC_OCC_MAGIC_NUM ); - l_pOccFfdcHdr->iv_ffdcValid = i_ffdcValid; - l_pOccFfdcHdr->iv_headerSize = sizeof (OccFfdcHeader); + l_pOccFfdcHdr->iv_versionMajor = 1; + l_pOccFfdcHdr->iv_versionMinor = 0; + l_pOccFfdcHdr->iv_headerSize = htobe16 (sizeof (OccFfdcHeader)); l_pOccFfdcHdr->iv_sectionSize = htobe16 (sizeof (OccFfdcRegion)); + l_pOccFfdcHdr->iv_sectionsValid = htobe16 (i_ffdcValid); l_pOccFfdcHdr->iv_offsetErrTrace = htobe16 (offsetof (struct OccFfdcRegion, iv_occTraceErr[0])); l_pOccFfdcHdr->iv_offsetImpTrace = @@ -190,8 +423,8 @@ htobe16 (offsetof (struct OccFfdcRegion, iv_occRegs[0])); FAPI_DBG( "================== OCC Header ==========================" ); - FAPI_DBG( "FFDC Validity Vector : 0x%02x", l_pOccFfdcHdr->iv_ffdcValid ); - FAPI_DBG( "OCC Header Size : 0x%02x", l_pOccFfdcHdr->iv_headerSize ); + FAPI_DBG( "FFDC Validity Vector : 0x%04x", REV_2_BYTE(l_pOccFfdcHdr->iv_sectionsValid )); + FAPI_DBG( "OCC Header Size : 0x%04x", REV_2_BYTE(l_pOccFfdcHdr->iv_headerSize )); FAPI_DBG( "OCC FFDC Section Size : 0x%04x", REV_2_BYTE(l_pOccFfdcHdr->iv_sectionSize) ); FAPI_DBG( "OCC ERR Trace Offset : 0x%04x", REV_2_BYTE(l_pOccFfdcHdr->iv_offsetErrTrace)); FAPI_DBG( "OCC IMP Trace Offset : 0x%04x", REV_2_BYTE(l_pOccFfdcHdr->iv_offsetImpTrace)); @@ -217,7 +450,7 @@ extern "C" FAPI_DBG (">> p9_pm_recovery_occ" ); PlatOcc l_occFfdc( i_procChip ); - FAPI_TRY( l_occFfdc.collectFfdc( i_pFfdcBuf ), + FAPI_TRY( l_occFfdc.collectFfdc ( i_pFfdcBuf, (TRACES | SCOM_REG)), "Failed To Collect OCC FFDC" ); fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.H index 40ed156ad..24a87dee0 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.H @@ -56,18 +56,35 @@ namespace p9_stop_recov_ffdc /// @brief destructor virtual ~PlatOcc() { }; + /// @brief Initializes the OCC FFDC Sub-Sections in HOMER with default header + /// @param[in] i_pHomerBuf points to base of P9 HOMER. + /// @return fapi2 return code + fapi2::ReturnCode init ( void* i_pHomerBuf ); + /// @brief collects FFDC of the OCC 405, GPE0 and GPE1. - /// @param[in] i_pHomerBuf points to base of P9 HOMER. + /// @param[in] i_pHomerBuf points to base of P9 HOMER. + /// @param[in] i_ffdcType indicates the content type to collect /// @return fapi2 return code. - fapi2::ReturnCode collectFfdc( void* i_pHomerBuf ); + fapi2::ReturnCode collectFfdc ( void* i_pHomerBuf, + uint8_t i_ffdcType = ALL ); private: - /// @brief collects trace info from OCC SRAM buffer. + /// @brief collects trace info from a known region OCC SRAM + /// @param[in] i_pHomerBuf location in HOMER to write at + /// @param[in] i_occSramRegion See OccFfdcValidStatus, + /// Indicates OCC SRAM Region to read + /// @return fapi2 return code. + fapi2::ReturnCode collectTrace( uint8_t* i_pHomerBuf, + uint8_t i_occSramRegion ); + + /// @brief reads OCC SRAM to find out the region extent and + /// then collects info from that region /// @param[in] i_pHomerBuf location in HOMER to write at - /// @param[in] i_sramAddress location in OCC SRAM to read from + /// @param[in] i_occSramRegion See OccFfdcValidStatus. + /// Indicates OCC SRAM Region to read /// @return fapi2 return code. - fapi2::ReturnCode collectTrace( uint8_t * i_pHomerBuf, - uint32_t i_sramAddress ); + fapi2::ReturnCode readSramRegion ( uint8_t* i_pHomerBuf, + uint8_t i_occSramRegion ); /// @brief updates the OCC FFDC Header /// @param[in] i_pHomerBuf points to a location in HOMER meant for @@ -76,7 +93,14 @@ namespace p9_stop_recov_ffdc /// valid. See OccFfdcValidStatus ///@return fapi2 return code. fapi2::ReturnCode updateOccFfdcHeader ( uint8_t* i_pHomerBuf, - uint8_t i_ffdcValid ); + uint16_t i_ffdcValid ); + + /// @brief collects register info for a given OCC + /// @param[in] i_pHomerBuf points to location of HOMER meant for OCC internal register. + ///@return fapi2 return code. + fapi2::ReturnCode collectOccReg( uint8_t * i_pHomerBuf); + + }; extern "C" diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_pgpe.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_pgpe.C index daddc6191..6a8a775ab 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_pgpe.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_pgpe.C @@ -50,67 +50,116 @@ { PlatPgpe::PlatPgpe( const fapi2::Target< fapi2::TARGET_TYPE_PROC_CHIP > i_procChipTgt ) : PlatPmComplex( i_procChipTgt, + PLAT_PGPE, OCC_SRAM_PGPE_HEADER_ADDR, OCC_SRAM_PGPE_TRACE_START, - OCC_SRAM_PGPE_DASHBOARD_START, - PLAT_PGPE ) + OCC_SRAM_PGPE_DASHBOARD_START ) { } //---------------------------------------------------------------------- - fapi2::ReturnCode PlatPgpe::collectFfdc( void * i_pHomerBuf ) + fapi2::ReturnCode PlatPgpe::init ( void* i_pHomerBuf ) { - FAPI_DBG(">> PlatPgpe::collectFfdc"); - fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; + FAPI_DBG (">> PlatPgpe::init" ); + FAPI_TRY ( collectFfdc( i_pHomerBuf, INIT), + "Failed To init PGPE FFDC" ); + + fapi_try_exit: + FAPI_DBG ("<< PlatPgpe::init" ); + return fapi2::current_err; + } + + //---------------------------------------------------------------------- + + fapi2::ReturnCode PlatPgpe::collectFfdc( void * i_pHomerBuf, + uint8_t i_ffdcType ) + { + FAPI_DBG(">> PlatPgpe::collectFfdc: 0x%02X", i_ffdcType); + fapi2::ReturnCode l_retCode = fapi2::FAPI2_RC_SUCCESS; - uint8_t l_ffdcValdityVect = PPE_FFDC_ALL_VALID; - uint8_t l_haltState = PPE_HALT_COND_UNKNOWN; - uint8_t *l_pFfdcLoc = NULL; HomerFfdcRegion * l_pHomerFfdc = ( HomerFfdcRegion *)( (uint8_t *)i_pHomerBuf + FFDC_REGION_HOMER_BASE_OFFSET ); - l_pFfdcLoc = (uint8_t *)(&l_pHomerFfdc->iv_pgpeFfdcRegion); + uint8_t* l_pFfdcLoc = (uint8_t *)(&l_pHomerFfdc->iv_pgpeFfdcRegion); + PpeFfdcHeader* l_pPgpeFfdcHdr = (PpeFfdcHeader*) l_pFfdcLoc; + uint16_t l_ffdcValdityVect = l_pPgpeFfdcHdr->iv_sectionsValid; + + if ( i_ffdcType & INIT ) + { // overwrite on init + l_ffdcValdityVect = PPE_FFDC_INVALID; + } //In case of error , invalidate FFDC in header. - l_retCode = collectPpeState ( PGPE_BASE_ADDRESS, - l_pFfdcLoc ); - if ( l_retCode != fapi2::FAPI2_RC_SUCCESS ) + if ( i_ffdcType & PPE_HALT_STATE ) { - FAPI_ERR ( "Error collecting PGPE State" ); - l_ffdcValdityVect &= ~PPE_STATE_VALID; + l_ffdcValdityVect |= PPE_HALT_STATE_VALID; + l_retCode = readPpeHaltState ( PGPE_BASE_ADDRESS, l_pFfdcLoc); + if ( l_retCode != fapi2::FAPI2_RC_SUCCESS ) + { + FAPI_ERR ( "Error collecting PGPE Halt State" ); + l_ffdcValdityVect &= ~PPE_HALT_STATE_VALID; + } } - l_retCode = collectTrace( l_pFfdcLoc ); - - if( l_retCode ) + if (i_ffdcType & PPE_STATE ) { - FAPI_ERR("Error in collecting PGPE Trace " ); - l_ffdcValdityVect &= ~PPE_TRACE_VALID; + l_ffdcValdityVect |= PPE_STATE_VALID; + l_retCode = collectPpeState ( PGPE_BASE_ADDRESS, + l_pFfdcLoc ); + if ( l_retCode != fapi2::FAPI2_RC_SUCCESS ) + { + FAPI_ERR ( "Error collecting PGPE State" ); + l_ffdcValdityVect &= ~PPE_STATE_VALID; + } } - l_retCode = collectGlobals( l_pFfdcLoc ); - - if( l_retCode ) + if ( i_ffdcType & TRACES ) { - FAPI_ERR("Error in collecting PGPE Globals" ); - l_ffdcValdityVect &= ~PPE_DASHBOARD_VALID; + l_ffdcValdityVect |= PPE_TRACE_VALID; + l_retCode = collectTrace( l_pFfdcLoc ); + + if( l_retCode ) + { + FAPI_ERR("Error in collecting PGPE Trace " ); + l_ffdcValdityVect &= ~PPE_TRACE_VALID; + } } - l_retCode = collectImageHeader( l_pFfdcLoc ); - - if( l_retCode ) + if ( i_ffdcType & DASH_BOARD_VAR ) { - FAPI_ERR("Error in collecting PGPE Image header" ); - l_ffdcValdityVect &= ~PPE_IMAGE_HEADER_VALID; + l_ffdcValdityVect |= PPE_DASHBOARD_VALID; + l_retCode = collectGlobals( l_pFfdcLoc ); + + if( l_retCode ) + { + FAPI_ERR("Error in collecting PGPE Globals" ); + l_ffdcValdityVect &= ~PPE_DASHBOARD_VALID; + } } + if ( i_ffdcType & IMAGE_HEADER ) + { + l_ffdcValdityVect |= PPE_IMAGE_HEADER_VALID; + l_retCode = collectImageHeader( l_pFfdcLoc ); + + if( l_retCode ) + { + FAPI_ERR("Error in collecting PGPE Image header" ); + l_ffdcValdityVect &= ~PPE_IMAGE_HEADER_VALID; + } + } - FAPI_TRY( updatePgpeFfdcHeader( l_pFfdcLoc, l_ffdcValdityVect, l_haltState ), + FAPI_TRY( updatePgpeFfdcHeader( l_pFfdcLoc, l_ffdcValdityVect ), "Failed To Update PGPE FFDC Header for PGPE " ); - fapi_try_exit: + if (l_ffdcValdityVect == PPE_FFDC_INVALID) + setPmFfdcSectionValid ( i_pHomerBuf, PM_FFDC_PGPE_VALID, false ); + else + setPmFfdcSectionValid ( i_pHomerBuf, PM_FFDC_PGPE_VALID ); + + fapi_try_exit: FAPI_DBG("<< PlatPgpe::collectFfdc"); return fapi2::current_err; } @@ -131,7 +180,7 @@ FFDC_PPE_TRACES_SIZE ), "Trace Collection Failed" ); - fapi_try_exit: + fapi_try_exit: FAPI_DBG("<< PlatPgpe::collectTrace" ); return fapi2::current_err; } @@ -152,7 +201,7 @@ "Failed To Collect PGPE Global Variables" ); - fapi_try_exit: + fapi_try_exit: FAPI_DBG("<< PlatPgpe::collectGlobals" ); return fapi2::current_err; } @@ -179,22 +228,22 @@ FFDC_PPE_IMG_HDR_SIZE ), "Failed To Collect PGPE Image Header" ); - fapi_try_exit: + fapi_try_exit: FAPI_DBG("<< PlatPgpe::collectImageHeader" ); return fapi2::current_err; } //----------------------------------------------------------------------- - fapi2::ReturnCode PlatPgpe::updatePgpeFfdcHeader( uint8_t * i_pHomerBuf, - bool i_ffdcValid, uint8_t i_haltState ) + fapi2::ReturnCode PlatPgpe::updatePgpeFfdcHeader( uint8_t* i_pHomerBuf, + uint16_t i_sectionsValid ) { FAPI_DBG(">> updatePgpeFfdcHeader" ); PpeFfdcHeader * l_pPgpeFfdcHdr = ( (PpeFfdcHeader *)(( PpeFfdcHdrRegion * ) i_pHomerBuf )); l_pPgpeFfdcHdr->iv_ppeMagicNumber = htobe32( FFDC_PGPE_MAGIC_NUM ); l_pPgpeFfdcHdr->iv_ppeNumber = 0; - PlatPmComplex::updatePpeFfdcHeader( l_pPgpeFfdcHdr, i_ffdcValid, i_haltState ); + updatePpeFfdcHeader ( l_pPgpeFfdcHdr, i_sectionsValid ); FAPI_DBG("<< updatePgpeFfdcHeader" ); return fapi2::FAPI2_RC_SUCCESS; @@ -209,15 +258,14 @@ extern "C" FAPI_IMP(">> p9_pm_recovery_pgpe" ); PlatPgpe l_pgpeFfdc( i_procChip ); - FAPI_TRY( l_pgpeFfdc.collectFfdc( i_pFfdcBuf ), + FAPI_TRY( l_pgpeFfdc.collectFfdc( i_pFfdcBuf, (ALL & ~PPE_HALT_STATE) ), "Failed To Collect PGPE FFDC" ); - fapi_try_exit: + fapi_try_exit: FAPI_IMP("<< p9_pm_recovery_pgpe" ); return fapi2::current_err; } } - }//namespace p9_stop_recov_ffdc ends diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_pgpe.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_pgpe.H index 4c8222336..34ee09500 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_pgpe.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_pgpe.H @@ -55,10 +55,17 @@ namespace p9_stop_recov_ffdc /// @brief destructor virtual ~PlatPgpe() { }; + /// @brief Initializes the PGPE FFDC Sub-Section in HOMER with default header + /// @param[in] i_pHomerBuf points to base of P9 HOMER. + /// @return fapi2 return code + fapi2::ReturnCode init ( void* i_pHomerBuf ); + /// @brief collects FFDC pertaining to all functional PGPEs in the chip. - /// @param[in] i_pHomerBuf points to base of P9 HOMER. + /// @param[in] i_pHomerBuf points to base of P9 HOMER. + /// @param[in] i_ffdcType indicates the content type to collect /// @return fapi2 return code. - fapi2::ReturnCode collectFfdc( void* i_pHomerBuf ); + fapi2::ReturnCode collectFfdc( void* i_pHomerBuf, + uint8_t i_ffdcType = ALL ); private: /// @brief collects trace info from PGPE's SRAM buffer. @@ -88,13 +95,10 @@ namespace p9_stop_recov_ffdc /// @brief updates the PGPE FFDC Header ///@param[in] i_pHomerBuf points to a location in HOMER meant for PGPE FFDC Header - ///@param[in] i_ffdcValid true if FFDC is valid, false otherwise - ///@param[in] i_haltCondition hlat state of PGPE + ///@param[in] i_sectionsValid bit vector summarizing FFDC validity ///@return fapi2 return code. - ///@note refer to PPE Spec for details on halt state. - - fapi2::ReturnCode updatePgpeFfdcHeader( uint8_t * i_pHomerBuf, - bool i_ffdcValid, uint8_t i_haltCondition ); + fapi2::ReturnCode updatePgpeFfdcHeader( uint8_t* i_pHomerBuf, + uint16_t i_sectionsValid ); ///@brief returns type of platform PmComplexPlatId getPlatType() { return iv_plat; } diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_pgpe.mk b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_pgpe.mk index 4f3063553..3b0609be3 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_pgpe.mk +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_pgpe.mk @@ -29,5 +29,7 @@ lib$(PROCEDURE)_DEPLIBS +=p9_pm_recovery_ffdc_base lib$(PROCEDURE)_DEPLIBS+=p9_pm_ocb_indir_access lib$(PROCEDURE)_DEPLIBS+=p9_pm_ocb_indir_setup_linear lib$(PROCEDURE)_DEPLIBS+=p9_cme_sram_access +lib$(PROCEDURE)_DEPLIBS+=p9_ppe_state +lib$(PROCEDURE)_DEPLIBS+=p9_ppe_utils $(call ADD_MODULE_INCDIR,$(PGPE_FFDC_INC)) $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_qppm.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_qppm.C index 2dcc181c7..205240346 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_qppm.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_qppm.C @@ -48,66 +48,90 @@ namespace p9_stop_recov_ffdc { QppmRegs::QppmRegs( const fapi2::Target< fapi2::TARGET_TYPE_PROC_CHIP > i_procChipTgt ) - : PlatPmComplex( i_procChipTgt,0,0,0,PLAT_PPM) + : PlatPmComplex ( i_procChipTgt, PLAT_QPPM ) { } //---------------------------------------------------------------------- - fapi2::ReturnCode QppmRegs::collectRegFfdc( void * i_pHomerBuf ) + fapi2::ReturnCode QppmRegs::init ( void* i_pHomerBuf ) { - FAPI_DBG(">> QppmRegs::collectRegFfdc"); - fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; - fapi2::ReturnCode l_rc = fapi2::current_err; + FAPI_DBG (">> QppmRegs::init" ); + FAPI_TRY ( collectFfdc( i_pHomerBuf, INIT), + "Failed To init QPPM REGS FFDC" ); + + fapi_try_exit: + FAPI_DBG ("<< QppmRegs::init" ); + return fapi2::current_err; + } + + //---------------------------------------------------------------------- + + fapi2::ReturnCode QppmRegs::collectFfdc ( void* i_pHomerBuf, + uint8_t i_ffdcType ) + { + FAPI_DBG(">> QppmRegs::collectFfdc"); + + fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS; + auto l_quadList = getProcChip().getChildren< fapi2::TARGET_TYPE_EQ > ( fapi2::TARGET_STATE_PRESENT ); uint8_t l_quadPos = 0; - uint8_t *l_pFfdcLoc = NULL; - uint8_t l_ffdcValid = 0; + uint8_t* l_pFfdcLoc = NULL; + uint16_t l_ffdcValid = 0; HomerFfdcRegion * l_pHomerFfdc = ( HomerFfdcRegion *)( (uint8_t *)i_pHomerBuf + FFDC_REGION_HOMER_BASE_OFFSET ); for( auto quad : l_quadList ) { + FAPI_TRY( FAPI_ATTR_GET( fapi2::ATTR_CHIP_UNIT_POS, quad, l_quadPos ), "FAPI_ATTR_GET Failed To Read QUAD Position" ); l_pFfdcLoc = &l_pHomerFfdc->iv_quadFfdc[l_quadPos].iv_quadQppmRegion[0]; - if( quad.isFunctional() ) - { - l_ffdcValid = 1; - FAPI_INF("QPPM FFDC Pos %d ", l_quadPos); - l_rc = collectRegisterData<fapi2::TARGET_TYPE_EQ> (quad, - l_pFfdcLoc + sizeof(PpmFfdcHeader), - static_cast<fapi2::HwpFfdcId>(fapi2::QPPM_FFDC_REGISTERS)); - if (l_rc ) + // On INIT, update the headers just as in case of not functional + if (quad.isFunctional()) + { + // Note: ( i_ffdcType & INIT ) is the default case + if ( i_ffdcType & SCOM_REG ) { - l_ffdcValid = 0; + l_ffdcValid = 1; + FAPI_INF("QPPM FFDC Pos %d ", l_quadPos); + + l_rc = collectRegisterData <fapi2::TARGET_TYPE_EQ> ( + quad, + l_pFfdcLoc + sizeof(PpmFfdcHeader), + static_cast<fapi2::HwpFfdcId>(fapi2::QPPM_FFDC_REGISTERS)); + if (l_rc ) + { + l_ffdcValid = 0; + } } } - FAPI_TRY( updateQppmFfdcHeader( l_pFfdcLoc, l_quadPos, l_ffdcValid), "Failed To Update QPPM FFDC Header for quad 0x%0d", l_quadPos); } - fapi_try_exit: - FAPI_DBG("<< QppmRegs::collectRegFfdc"); + fapi_try_exit: + FAPI_DBG("<< QppmRegs::collectFfdc"); return fapi2::current_err; } fapi2::ReturnCode QppmRegs::updateQppmFfdcHeader( uint8_t * i_pHomerBuf, const uint8_t i_quadPos, - const uint8_t i_ffdcValid) + const uint16_t i_ffdcValid) { FAPI_DBG(">> updateQppmFfdcHeader" ); - PpmFfdcHeader * l_QppmFfdcHdr = (PpmFfdcHeader *) i_pHomerBuf ; - l_QppmFfdcHdr->iv_ppmMagicWord = htobe32(FFDC_QPPM_MAGIC_NUM); - l_QppmFfdcHdr->iv_Instance = i_quadPos; - l_QppmFfdcHdr->iv_ppmHeaderSize = sizeof(PpmFfdcHeader); - l_QppmFfdcHdr->iv_sectionSize = FFDC_QPPM_REGISTERS_SIZE; - l_QppmFfdcHdr->iv_ffdcValid = i_ffdcValid; + PpmFfdcHeader * l_QppmFfdcHdr = (PpmFfdcHeader *) i_pHomerBuf ; + l_QppmFfdcHdr->iv_ppmMagicWord = htobe32(FFDC_QPPM_MAGIC_NUM); + l_QppmFfdcHdr->iv_versionMajor = 1; + l_QppmFfdcHdr->iv_versionMinor = 0; + l_QppmFfdcHdr->iv_Instance = i_quadPos; + l_QppmFfdcHdr->iv_ppmHeaderSize = htobe16(sizeof(PpmFfdcHeader)); + l_QppmFfdcHdr->iv_sectionSize = htobe16(FFDC_QPPM_REGION_SIZE); + l_QppmFfdcHdr->iv_ffdcValid = htobe16 (i_ffdcValid); FAPI_DBG("<< updateQppmFfdcHeader" ); return fapi2::FAPI2_RC_SUCCESS; @@ -122,7 +146,7 @@ extern "C" { FAPI_IMP(">> p9_pm_recovery_ffdc_qppm" ); QppmRegs l_qppmFfdc( i_procChip ); - FAPI_TRY( l_qppmFfdc.collectRegFfdc( i_pFfdcBuf ), + FAPI_TRY( l_qppmFfdc.collectFfdc( i_pFfdcBuf, SCOM_REG ), "Failed To Collect QPPM FFDC" ); fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_qppm.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_qppm.H index 7b4aafbab..43b3ee50d 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_qppm.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_qppm.H @@ -55,10 +55,17 @@ namespace p9_stop_recov_ffdc /// @brief destructor virtual ~QppmRegs () { }; - /// @brief collects Register FFDC pertaining to all functional cores in the chip. + /// @brief Initializes the QPPM FFDC Sub-Sections in HOMER with default headers + /// @param[in] i_pHomerBuf points to base of P9 HOMER. + /// @return fapi2 return code + fapi2::ReturnCode init ( void* i_pHomerBuf ); + + /// @brief collects FFDC pertaining to QPMMs of all functional quads in the chip. /// @param[in] i_pHomerBuf points to base of P9 HOMER. + // @param[in] i_ffdcType indicates the content type to collect // @return fapi2 return code. - fapi2::ReturnCode collectRegFfdc( void* i_pHomerBuf ); + fapi2::ReturnCode collectFfdc ( void* i_pHomerBuf, + uint8_t i_ffdcType = ALL ); private: /// @brief updates the QPPM FFDC Header @@ -69,7 +76,7 @@ namespace p9_stop_recov_ffdc fapi2::ReturnCode updateQppmFfdcHeader( uint8_t * i_pHomerBuf, const uint8_t i_qppmInstance, - const uint8_t i_ffdcValid); + const uint16_t i_ffdcValid); }; diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.C index d79472f4a..512b8b91e 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.C @@ -50,67 +50,116 @@ { PlatSgpe::PlatSgpe( const fapi2::Target< fapi2::TARGET_TYPE_PROC_CHIP > i_procChipTgt ) : PlatPmComplex( i_procChipTgt, + PLAT_SGPE, OCC_SRAM_SGPE_HEADER_ADDR, OCC_SRAM_SGPE_TRACE_START, - OCC_SRAM_SGPE_DASHBOARD_START, - PLAT_SGPE ) + OCC_SRAM_SGPE_DASHBOARD_START ) { } +//---------------------------------------------------------------------- + + fapi2::ReturnCode PlatSgpe::init ( void* i_pHomerBuf ) + { + FAPI_DBG (">> PlatSgpe::init" ); + FAPI_TRY ( collectFfdc( i_pHomerBuf, INIT), + "Failed To init SGPE FFDC" ); + + fapi_try_exit: + FAPI_DBG ("<< PlatSgpe::init" ); + return fapi2::current_err; + } + //---------------------------------------------------------------------- - fapi2::ReturnCode PlatSgpe::collectFfdc( void * i_pHomerBuf ) + fapi2::ReturnCode PlatSgpe::collectFfdc( void * i_pHomerBuf, + uint8_t i_ffdcType ) { FAPI_DBG(">> PlatSgpe::collectFfdc"); - fapi2::ReturnCode l_retCode = fapi2::FAPI2_RC_SUCCESS; - uint8_t l_ffdcValdityVect = PPE_FFDC_ALL_VALID; - uint8_t l_haltState = PPE_HALT_COND_UNKNOWN; - uint8_t *l_pFfdcLoc = NULL; + fapi2::ReturnCode l_retCode = fapi2::FAPI2_RC_SUCCESS; HomerFfdcRegion * l_pHomerFfdc = ( HomerFfdcRegion *)( (uint8_t *)i_pHomerBuf + FFDC_REGION_HOMER_BASE_OFFSET ); - l_pFfdcLoc = (uint8_t *)(&l_pHomerFfdc->iv_sgpeFfdcRegion); + uint8_t* l_pFfdcLoc = (uint8_t *)(&l_pHomerFfdc->iv_sgpeFfdcRegion); + PpeFfdcHeader* l_pSgpeFfdcHdr = (PpeFfdcHeader*) l_pFfdcLoc; + + uint16_t l_ffdcValdityVect = l_pSgpeFfdcHdr->iv_sectionsValid; + + if ( i_ffdcType & INIT ) + { // overwrite on init + l_ffdcValdityVect = PPE_FFDC_INVALID; + } //In case of error , invalidate FFDC in header. - l_retCode = collectPpeState ( SGPE_BASE_ADDRESS, l_pFfdcLoc ); - if ( l_retCode != fapi2::FAPI2_RC_SUCCESS ) + if ( i_ffdcType & PPE_HALT_STATE ) { - FAPI_ERR ( "Error collecting SGPE State" ); - // PPE State Data is bad & continue SRAM FFDC collection - l_ffdcValdityVect &= ~PPE_STATE_VALID; + l_ffdcValdityVect |= PPE_HALT_STATE_VALID; + l_retCode = readPpeHaltState ( SGPE_BASE_ADDRESS, l_pFfdcLoc ); + if ( l_retCode != fapi2::FAPI2_RC_SUCCESS ) + { + FAPI_ERR ( "Error collecting SGPE Halt State" ); + l_ffdcValdityVect &= ~PPE_HALT_STATE_VALID; + } } - l_retCode = collectTrace( l_pFfdcLoc ); - - if( l_retCode ) + if ( i_ffdcType & PPE_STATE ) { - FAPI_ERR("Error in collecting SGPE Trace " ); - l_ffdcValdityVect &= ~PPE_TRACE_VALID; + l_ffdcValdityVect |= PPE_STATE_VALID; + l_retCode = collectPpeState ( SGPE_BASE_ADDRESS, l_pFfdcLoc ); + if ( l_retCode != fapi2::FAPI2_RC_SUCCESS ) + { + FAPI_ERR ( "Error collecting SGPE State" ); + // PPE State Data is bad & continue SRAM FFDC collection + l_ffdcValdityVect &= ~PPE_STATE_VALID; + } } - l_retCode = collectGlobals( l_pFfdcLoc ); - - if( l_retCode ) + if ( i_ffdcType & TRACES ) { - FAPI_ERR("Error in collecting SGPE Globals" ); - l_ffdcValdityVect &= ~PPE_DASHBOARD_VALID; + l_ffdcValdityVect |= PPE_TRACE_VALID; + l_retCode = collectTrace( l_pFfdcLoc ); + if( l_retCode ) + { + FAPI_ERR("Error in collecting SGPE Trace " ); + l_ffdcValdityVect &= ~PPE_TRACE_VALID; + } } + if ( i_ffdcType & DASH_BOARD_VAR ) + { + l_ffdcValdityVect |= PPE_DASHBOARD_VALID; + l_retCode = collectGlobals( l_pFfdcLoc ); + + if( l_retCode ) + { + FAPI_ERR("Error in collecting SGPE Globals" ); + l_ffdcValdityVect &= ~PPE_DASHBOARD_VALID; + } + } - l_retCode = collectImageHeader( l_pFfdcLoc ); - - if( l_retCode ) + if ( i_ffdcType & IMAGE_HEADER ) { - FAPI_ERR("Error in collecting SGPE Image header" ); - l_ffdcValdityVect &= ~PPE_IMAGE_HEADER_VALID; + l_ffdcValdityVect |= PPE_IMAGE_HEADER_VALID; + l_retCode = collectImageHeader( l_pFfdcLoc ); + + if( l_retCode ) + { + FAPI_ERR("Error in collecting SGPE Image header" ); + l_ffdcValdityVect &= ~PPE_IMAGE_HEADER_VALID; + } } - FAPI_TRY( updateSgpeFfdcHeader( l_pFfdcLoc, l_ffdcValdityVect, l_haltState ), + FAPI_TRY( updateSgpeFfdcHeader( l_pFfdcLoc, l_ffdcValdityVect), "Failed To Update SGPE FFDC Header for SGPE " ); - fapi_try_exit: - FAPI_DBG("<< PlatSgpe::collectFfdc"); + if (l_ffdcValdityVect == PPE_FFDC_INVALID) + setPmFfdcSectionValid ( i_pHomerBuf, PM_FFDC_SGPE_VALID, false ); + else + setPmFfdcSectionValid ( i_pHomerBuf, PM_FFDC_SGPE_VALID ); + + fapi_try_exit: + FAPI_DBG("<< PlatSgpe::collectFfdc: 0x%02X", l_ffdcValdityVect); return fapi2::current_err; } @@ -185,15 +234,15 @@ //----------------------------------------------------------------------- - fapi2::ReturnCode PlatSgpe::updateSgpeFfdcHeader( uint8_t * i_pHomerBuf, - uint8_t i_ffdcValid, uint8_t i_haltState ) + fapi2::ReturnCode PlatSgpe::updateSgpeFfdcHeader( uint8_t* i_pHomerBuf, + uint16_t i_sectionsValid ) { FAPI_DBG(">> updateSgpeFfdcHeader" ); PpeFfdcHeader * l_pSgpeFfdcHdr = ( (PpeFfdcHeader *)(( PpeFfdcHdrRegion * ) i_pHomerBuf )); l_pSgpeFfdcHdr->iv_ppeMagicNumber = htobe32( FFDC_SGPE_MAGIC_NUM ); l_pSgpeFfdcHdr->iv_ppeNumber = 0; - PlatPmComplex::updatePpeFfdcHeader( l_pSgpeFfdcHdr, i_ffdcValid, i_haltState ); + PlatPmComplex::updatePpeFfdcHeader( l_pSgpeFfdcHdr, i_sectionsValid ); FAPI_DBG("<< updateSgpeFfdcHeader" ); return fapi2::FAPI2_RC_SUCCESS; @@ -208,7 +257,7 @@ extern "C" FAPI_IMP(">> p9_pm_recovery_sgpe" ); PlatSgpe l_sgpeFfdc( i_procChip ); - FAPI_TRY( l_sgpeFfdc.collectFfdc( i_pFfdcBuf ), + FAPI_TRY( l_sgpeFfdc.collectFfdc( i_pFfdcBuf, (ALL & ~PPE_HALT_STATE) ), "Failed To Collect SGPE FFDC" ); fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.H index 227a1f188..640cc0651 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.H @@ -55,10 +55,17 @@ namespace p9_stop_recov_ffdc /// @brief destructor virtual ~PlatSgpe() { }; + /// @brief Initializes the SGPE FFDC Sub-Section in HOMER with default header + /// @param[in] i_pHomerBuf points to base of P9 HOMER. + /// @return fapi2 return code + fapi2::ReturnCode init ( void* i_pHomerBuf ); + /// @brief collects FFDC pertaining to all functional SGPEs in the chip. - /// @param[in] i_pHomerBuf points to base of P9 HOMER. + /// @param[in] i_pHomerBuf points to base of P9 HOMER. + /// @param[in] i_ffdcType indicates the content type to collect /// @return fapi2 return code. - fapi2::ReturnCode collectFfdc( void* i_pHomerBuf ); + fapi2::ReturnCode collectFfdc( void* i_pHomerBuf, + uint8_t i_ffdcType = ALL ); private: /// @brief collects trace info from SGPE's SRAM buffer. @@ -83,13 +90,10 @@ namespace p9_stop_recov_ffdc /// @brief updates the SGPE FFDC Header ///@param[in] i_pHomerBuf points to a location in HOMER meant for SGPE FFDC Header - ///param[in] i_ffdcValid bit vector summarizing FFDC validity - ///@param[in] i_haltCondition hlat state of SGPE + ///param[in] i_sectionsValid bit vector summarizing FFDC validity ///@return fapi2 return code. - ///@note refer to PPE Spec for details on halt state. - - fapi2::ReturnCode updateSgpeFfdcHeader( uint8_t * i_pHomerBuf, - uint8_t i_ffdcValid, uint8_t i_haltCondition ); + fapi2::ReturnCode updateSgpeFfdcHeader( uint8_t* i_pHomerBuf, + uint16_t i_sectionsValid ); ///@brief returns type of platform PmComplexPlatId getPlatType() { return iv_plat; } diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.mk b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.mk index 72b967dc7..cb7b28521 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.mk +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.mk @@ -29,5 +29,7 @@ lib$(PROCEDURE)_DEPLIBS +=p9_pm_recovery_ffdc_base lib$(PROCEDURE)_DEPLIBS+=p9_pm_ocb_indir_access lib$(PROCEDURE)_DEPLIBS+=p9_pm_ocb_indir_setup_linear lib$(PROCEDURE)_DEPLIBS+=p9_cme_sram_access +lib$(PROCEDURE)_DEPLIBS+=p9_ppe_state +lib$(PROCEDURE)_DEPLIBS+=p9_ppe_utils $(call ADD_MODULE_INCDIR,$(CME_FFDC_INC)) $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_registers.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_registers.xml index 939456ca0..98fbde7a4 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_registers.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_registers.xml @@ -381,4 +381,208 @@ <scomRegister>PU_PBAFIR</scomRegister> </registerFfdc> <!-- *********************************************************************** --> + <registerFfdc> + <id>OCC_FFDC_REGISTERS</id> + <scomRegister>PU_OCB_OCI_OISR0_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OISR1_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OIMR0_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OIMR1_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OITR0_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OITR1_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OIEPR0_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OIEPR1_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OCCFLG_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_CCSR_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_QCSR_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_QSSR_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OCBLWCR0_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OCBLWCR1_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OCBLWCR2_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OCBLWCR3_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OCBLWSBR0_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OCBLWSBR1_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OCBLWSBR2_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OCBLWSBR3_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OCBLWSR0_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OCBLWSR1_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OCBLWSR2_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OCBLWSR3_SCOM</scomRegister> + <scomRegister>PU_OCB_PIB_OCBAR0</scomRegister> + <scomRegister>PU_OCB_PIB_OCBAR1</scomRegister> + <scomRegister>PU_OCB_PIB_OCBAR2</scomRegister> + <scomRegister>PU_OCB_PIB_OCBAR3</scomRegister> + <scomRegister>PU_OCB_PIB_OCBCSR0_RO</scomRegister> + <scomRegister>PU_OCB_PIB_OCBCSR1_RO</scomRegister> + <scomRegister>PU_OCB_PIB_OCBCSR2_RO</scomRegister> + <scomRegister>PU_OCB_PIB_OCBCSR3_RO</scomRegister> + <scomRegister>PU_OCB_PIB_OCBESR0</scomRegister> + <scomRegister>PU_OCB_PIB_OCBESR1</scomRegister> + <scomRegister>PU_OCB_PIB_OCBESR2</scomRegister> + <scomRegister>PU_OCB_PIB_OCBESR3</scomRegister> + <scomRegister>PU_OCB_PIB_OCBDR0</scomRegister> + <scomRegister>PU_OCB_PIB_OCBDR1</scomRegister> + <scomRegister>PU_OCB_PIB_OCBDR2</scomRegister> + <scomRegister>PU_OCB_PIB_OCBDR3</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C0_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C1_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C2_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C3_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C4_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C5_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C6_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C7_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C8_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C9_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C10_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C11_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C12_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C13_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C14_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C15_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C16_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C17_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C18_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C19_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C20_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C21_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C22_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT0C23_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C0_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C1_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C2_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C3_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C4_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C5_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C6_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C7_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C8_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C9_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C10_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C11_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C12_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C13_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C14_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C15_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C16_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C17_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C18_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C19_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C20_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C21_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C22_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT1C23_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C0_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C1_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C2_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C3_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C4_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C5_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C6_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C7_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C8_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C9_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C10_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C11_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C12_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C13_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C14_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C15_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C16_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C17_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C18_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C19_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C20_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C21_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C22_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT2C23_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C0_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C1_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C2_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C3_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C4_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C5_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C6_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C7_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C8_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C9_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C10_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C11_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C12_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C13_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C14_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C15_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C16_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C17_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C18_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C19_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C20_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C21_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C22_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT3C23_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C0_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C1_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C2_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C3_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C4_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C5_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C6_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C7_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C8_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C9_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C10_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C11_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C12_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C13_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C14_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C15_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C16_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C17_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C18_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C19_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C20_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C21_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C22_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT4C23_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C0_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C1_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C2_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C3_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C4_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C5_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C6_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C7_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C8_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C9_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C10_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C11_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C12_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C13_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C14_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C15_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C16_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C17_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C18_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C19_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C20_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C21_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C22_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT5C23_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT6Q0_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT6Q1_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT6Q2_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT6Q3_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT6Q4_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT6Q5_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT7Q0_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT7Q1_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT7Q2_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT7Q3_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT7Q4_SCOM</scomRegister> + <scomRegister>PU_OCB_OCI_OPIT7Q5_SCOM</scomRegister> + <scomRegister>PU_PBAMODE_SCOM</scomRegister> + <scomRegister>PU_PBASLVCTL0_SCOM</scomRegister> + <scomRegister>PU_PBASLVCTL1_SCOM</scomRegister> + <scomRegister>PU_PBASLVCTL2_SCOM</scomRegister> + <scomRegister>PU_PBASLVCTL3_SCOM</scomRegister> + </registerFfdc> </hwpErrors> |
