diff options
Diffstat (limited to 'src/import/chips')
4 files changed, 95 insertions, 23 deletions
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioo_dl_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioo_dl_scom.C index 2e781d11a..43ecf2a6e 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioo_dl_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioo_dl_scom.C @@ -33,6 +33,7 @@ constexpr uint64_t literal_1 = 1; constexpr uint64_t literal_0x0F = 0x0F; constexpr uint64_t literal_0xF = 0xF; constexpr uint64_t literal_0x0 = 0x0; +constexpr uint64_t literal_0x00 = 0x00; constexpr uint64_t literal_0xE = 0xE; constexpr uint64_t literal_0x5 = 0x5; constexpr uint64_t literal_0b0001111 = 0b0001111; @@ -61,6 +62,9 @@ fapi2::ReturnCode p9_fbc_ioo_dl_scom(const fapi2::Target<fapi2::TARGET_TYPE_OBUS FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_LINK_ACTIVE, TGT0, l_TGT0_ATTR_PROC_FABRIC_LINK_ACTIVE)); uint64_t l_def_OBUS_FBC_ENABLED = ((l_TGT0_ATTR_OPTICS_CONFIG_MODE == fapi2::ENUM_ATTR_OPTICS_CONFIG_MODE_SMP) && l_TGT0_ATTR_PROC_FABRIC_LINK_ACTIVE); + fapi2::ATTR_CHIP_EC_FEATURE_HW419022_Type l_TGT1_ATTR_CHIP_EC_FEATURE_HW419022; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW419022, TGT1, l_TGT1_ATTR_CHIP_EC_FEATURE_HW419022)); + uint64_t l_def_DLL_DD10_TRAIN = (l_TGT1_ATTR_CHIP_EC_FEATURE_HW419022 != literal_0x00); fapi2::buffer<uint64_t> l_scom_buffer; { if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) @@ -153,14 +157,48 @@ fapi2::ReturnCode p9_fbc_ioo_dl_scom(const fapi2::Target<fapi2::TARGET_TYPE_OBUS } } - l_scom_buffer.insert<8, 4, 60, uint64_t>(literal_0xE ); - l_scom_buffer.insert<12, 4, 60, uint64_t>(literal_0xE ); + if (( ! l_def_DLL_DD10_TRAIN)) + { + constexpr auto l_PB_IOO_LL0_CONFIG_PHY_TRAIN_A_ADJ_USE4 = 0x2; + l_scom_buffer.insert<0, 2, 62, uint64_t>(l_PB_IOO_LL0_CONFIG_PHY_TRAIN_A_ADJ_USE4 ); + } + + if (( ! l_def_DLL_DD10_TRAIN)) + { + constexpr auto l_PB_IOO_LL0_CONFIG_PHY_TRAIN_B_ADJ_USE12 = 0x2; + l_scom_buffer.insert<2, 2, 62, uint64_t>(l_PB_IOO_LL0_CONFIG_PHY_TRAIN_B_ADJ_USE12 ); + } + + if (( ! l_def_DLL_DD10_TRAIN)) + { + l_scom_buffer.insert<8, 4, 60, uint64_t>(literal_0x0 ); + } + else if (l_def_DLL_DD10_TRAIN) + { + l_scom_buffer.insert<8, 4, 60, uint64_t>(literal_0xE ); + } + + if (( ! l_def_DLL_DD10_TRAIN)) + { + l_scom_buffer.insert<12, 4, 60, uint64_t>(literal_0x0 ); + } + else if (l_def_DLL_DD10_TRAIN) + { + l_scom_buffer.insert<12, 4, 60, uint64_t>(literal_0xE ); + } if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x12)) ) { - l_scom_buffer.insert<4, 4, 60, uint64_t>(literal_0x0 ); + if (( ! l_def_DLL_DD10_TRAIN)) + { + l_scom_buffer.insert<4, 4, 60, uint64_t>(literal_0xF ); + } + else if (l_def_DLL_DD10_TRAIN) + { + l_scom_buffer.insert<4, 4, 60, uint64_t>(literal_0x0 ); + } } FAPI_TRY(fapi2::putScom(TGT0, 0x901080cull, l_scom_buffer)); diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_obus_linktrain.C b/src/import/chips/p9/procedures/hwp/io/p9_io_obus_linktrain.C index 3808f50ed..bb15eaf01 100644 --- a/src/import/chips/p9/procedures/hwp/io/p9_io_obus_linktrain.C +++ b/src/import/chips/p9/procedures/hwp/io/p9_io_obus_linktrain.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -141,41 +141,71 @@ fapi2::ReturnCode p9_io_obus_linktrain(const OBUS_TGT& i_tgt) l_hw419022), "Error from FAPI_ATTR_GET (fapi2::ATTR_CHIP_EC_FEATURE_HW419022)"); - // perform DL training workaround - if (l_hw419022) + // Cable CDR lock + // determine link train capabilities (half/full) + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_LINK_TRAIN, + i_tgt, + l_link_train), + "Error from FAPI_ATTR_GET (ATTR_LINK_TRAIN)"); + + l_even = (l_link_train == fapi2::ENUM_ATTR_LINK_TRAIN_BOTH) || + (l_link_train == fapi2::ENUM_ATTR_LINK_TRAIN_EVEN_ONLY); + + l_odd = (l_link_train == fapi2::ENUM_ATTR_LINK_TRAIN_BOTH) || + (l_link_train == fapi2::ENUM_ATTR_LINK_TRAIN_ODD_ONLY); + + // set TX lane control to force send of TS1 pattern + if (l_even) + { + FAPI_TRY(fapi2::putScom(i_tgt, + OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL, + 0x1111111111100000ULL), + "Error from putScom (OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL)"); + } + + if (l_odd) { - // determine link train capabilities (half/full) - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_LINK_TRAIN, - i_tgt, - l_link_train), - "Error from FAPI_ATTR_GET (ATTR_LINK_TRAIN)"); + FAPI_TRY(fapi2::putScom(i_tgt, + OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL, + 0x1111111111100000ULL), + "Error from putScom (OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL)"); + } + + // Delay to compensate for active links + FAPI_TRY(fapi2::delay(100000000, 1000000), + "Error from A-link retimer delay"); - l_even = (l_link_train == fapi2::ENUM_ATTR_LINK_TRAIN_BOTH) || - (l_link_train == fapi2::ENUM_ATTR_LINK_TRAIN_EVEN_ONLY); + // DD1.1+ HW Start training sequence + if(!l_hw419022) + { - l_odd = (l_link_train == fapi2::ENUM_ATTR_LINK_TRAIN_BOTH) || - (l_link_train == fapi2::ENUM_ATTR_LINK_TRAIN_ODD_ONLY); + l_data.flush<0>(); - // set TX lane control to force send of TS1 pattern + // clear TX lane control overrides if (l_even) { + l_data.setBit<OBUS_LL0_IOOL_CONTROL_LINK0_PHY_TRAINING>(); + FAPI_TRY(fapi2::putScom(i_tgt, OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL, - 0x1111111111100000ULL), + 0x0000000000000000ULL), "Error from putScom (OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL)"); } if (l_odd) { + l_data.setBit<OBUS_LL0_IOOL_CONTROL_LINK1_PHY_TRAINING>(); + FAPI_TRY(fapi2::putScom(i_tgt, OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL, - 0x1111111111100000ULL), + 0x0000000000000000ULL), "Error from putScom (OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL)"); } - // Delay to compensate for active links - FAPI_TRY(fapi2::delay(100000000, 1000000), - "Error from A-link retimer delay"); + // Start phy training + FAPI_TRY(fapi2::putScom(i_tgt, OBUS_LL0_IOOL_CONTROL, l_data), + "Error writing DLL control register (0x%08X)!", + OBUS_LL0_IOOL_CONTROL); } fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fab_iovalid.C b/src/import/chips/p9/procedures/hwp/nest/p9_fab_iovalid.C index 5f57a1371..ab5df082b 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_fab_iovalid.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_fab_iovalid.C @@ -852,6 +852,10 @@ p9_fab_iovalid(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_A_LINK_DELAY, i_target, l_a_agg_link_delay), "Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_A_LINK_DELAY"); + // Add delay for dd1.1+ procedure to compensate for lack of lane lock polls + FAPI_TRY(fapi2::delay(100000000, 1000000), + "Error from delay"); + for (uint8_t l_link_id = 0; l_link_id < P9_FBC_UTILS_MAX_X_LINKS; l_link_id++) { if (l_x_en[l_link_id]) diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.C b/src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.C index 7a09d928e..42f647d60 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -201,7 +201,7 @@ p9_smp_link_layer_lock_lanes( { // set PHY TX lane address, start at: // - PHY lane 0 for even (work up) - // - PHY lane 23 for odd (work down) + // - PHY lane 23 for odd (work down) DD1.0 uint64_t l_phy_tx_mode1_pl_addr = OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL; if (i_even) |