diff options
Diffstat (limited to 'src/import/chips/p9')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H | 25 | ||||
-rwxr-xr-x | src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml | 16 |
2 files changed, 41 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H index 8d6458ed3..d41445265 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H @@ -14142,6 +14142,31 @@ fapi_try_exit: /// +/// @brief ATTR_MSS_MRW_NVDIMM_SLOT_POSITION getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (PROC_CHIP) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note The position of a dimm is based on which mca it is associated with and which +/// drop behind that mca, with 16 dimms possible per processor socket. The formula +/// is: [processor position with no gaps, i.e. 0,1,2,3]*16 + [mca position on this +/// processor * 2] + [dimm location behind this +/// mca] +/// +inline fapi2::ReturnCode mrw_nvdimm_slot_position(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_NVDIMM_SLOT_POSITION, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_MRW_NVDIMM_SLOT_POSITION: 0x%lx", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + +/// /// @brief ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> /// @param[out] ref to the value uint64_t diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml index 078f79284..ae6bbb47e 100755 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml @@ -24,6 +24,22 @@ <!-- IBM_PROLOG_END_TAG --> <attributes> + <attribute> + <id>ATTR_MSS_MRW_NVDIMM_SLOT_POSITION</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + The position of a dimm is based on which mca it is + associated with and which drop behind that mca, with + 16 dimms possible per processor socket. The formula is: + [processor position with no gaps, i.e. 0,1,2,3]*16 + + [mca position on this processor * 2] + [dimm location behind this mca] + </description> + <valueType>uint8</valueType> + <default>0xFF</default> + <platInit/> + <mrwHide/> + <mssAccessorName>mrw_nvdimm_slot_position</mssAccessorName> + </attribute> <attribute> <id>ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG</id> |