diff options
Diffstat (limited to 'src/import/chips/p9')
6 files changed, 165 insertions, 28 deletions
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.C index 648e04652..22e971187 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.C @@ -42,6 +42,8 @@ constexpr auto literal_0b00001 = 0b00001; constexpr auto literal_0b0010001 = 0b0010001; constexpr auto literal_0b0000000000000000 = 0b0000000000000000; constexpr auto literal_0b01111111 = 0b01111111; +constexpr auto literal_0b10 = 0b10; +constexpr auto literal_0b1100 = 0b1100; constexpr auto literal_0b00 = 0b00; constexpr auto literal_0b01 = 0b01; @@ -6458,6 +6460,52 @@ fapi2::ReturnCode p9_xbus_g0_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>& } } { + l_rc = fapi2::getScom( TGT0, 0x800ae80006010c3full, l_scom_buffer ); + + if (l_rc) + { + FAPI_ERR("ERROR executing: getScom (0x800ae80006010c3full)"); + break; + } + + { + l_scom_buffer.insert<uint64_t> (literal_0b10, 56, 2, 62 ); + } + + l_rc = fapi2::putScom(TGT0, 0x800ae80006010c3full, l_scom_buffer); + + if (l_rc) + { + FAPI_ERR("ERROR executing: putScom (0x800ae80006010c3full)"); + break; + } + } + { + l_rc = fapi2::getScom( TGT0, 0x800af80006010c3full, l_scom_buffer ); + + if (l_rc) + { + FAPI_ERR("ERROR executing: getScom (0x800af80006010c3full)"); + break; + } + + { + l_scom_buffer.insert<uint64_t> (literal_0b1100, 48, 4, 60 ); + } + + { + l_scom_buffer.insert<uint64_t> (literal_0b1100, 52, 4, 60 ); + } + + l_rc = fapi2::putScom(TGT0, 0x800af80006010c3full, l_scom_buffer); + + if (l_rc) + { + FAPI_ERR("ERROR executing: putScom (0x800af80006010c3full)"); + break; + } + } + { l_rc = fapi2::getScom( TGT0, 0x800b800006010c3full, l_scom_buffer ); if (l_rc) diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g1_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g1_scom.C index 86bb587e6..ca0b2929c 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g1_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g1_scom.C @@ -43,6 +43,8 @@ constexpr auto literal_0b00001 = 0b00001; constexpr auto literal_0b0010001 = 0b0010001; constexpr auto literal_0b0000000000000000 = 0b0000000000000000; constexpr auto literal_0b01111111 = 0b01111111; +constexpr auto literal_0b10 = 0b10; +constexpr auto literal_0b1100 = 0b1100; constexpr auto literal_0b00 = 0b00; constexpr auto literal_0b01 = 0b01; @@ -6459,6 +6461,52 @@ fapi2::ReturnCode p9_xbus_g1_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>& } } { + l_rc = fapi2::getScom( TGT0, 0x800ae82006010c3full, l_scom_buffer ); + + if (l_rc) + { + FAPI_ERR("ERROR executing: getScom (0x800ae82006010c3full)"); + break; + } + + { + l_scom_buffer.insert<uint64_t> (literal_0b10, 56, 2, 62 ); + } + + l_rc = fapi2::putScom(TGT0, 0x800ae82006010c3full, l_scom_buffer); + + if (l_rc) + { + FAPI_ERR("ERROR executing: putScom (0x800ae82006010c3full)"); + break; + } + } + { + l_rc = fapi2::getScom( TGT0, 0x800af82006010c3full, l_scom_buffer ); + + if (l_rc) + { + FAPI_ERR("ERROR executing: getScom (0x800af82006010c3full)"); + break; + } + + { + l_scom_buffer.insert<uint64_t> (literal_0b1100, 48, 4, 60 ); + } + + { + l_scom_buffer.insert<uint64_t> (literal_0b1100, 52, 4, 60 ); + } + + l_rc = fapi2::putScom(TGT0, 0x800af82006010c3full, l_scom_buffer); + + if (l_rc) + { + FAPI_ERR("ERROR executing: putScom (0x800af82006010c3full)"); + break; + } + } + { l_rc = fapi2::getScom( TGT0, 0x800b802006010c3full, l_scom_buffer ); if (l_rc) diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_scom.H b/src/import/chips/p9/procedures/hwp/io/p9_io_scom.H index ea33f70b9..bcc1d91fa 100644 --- a/src/import/chips/p9/procedures/hwp/io/p9_io_scom.H +++ b/src/import/chips/p9/procedures/hwp/io/p9_io_scom.H @@ -82,7 +82,7 @@ inline uint64_t get( { const uint8_t REGISTER_WIDTH = 64; const uint8_t SHIFT = REGISTER_WIDTH - i_start - i_width; - const uint64_t MASK = ( ( 0x1 << i_width ) - 1 ) << SHIFT; + const uint64_t MASK = ( ( (uint64_t)0x1 << i_width ) - 1 ) << SHIFT; return ( ( i_register_data & MASK ) >> SHIFT ); } @@ -105,7 +105,7 @@ inline void set( { const uint8_t REGISTER_WIDTH = 64; const uint8_t SHIFT = REGISTER_WIDTH - i_start - i_width; - const uint64_t MASK = ( ( 0x1 << i_width ) - 1 ) << SHIFT; + const uint64_t MASK = ( ( (uint64_t)0x1 << i_width ) - 1 ) << SHIFT; io_register_data = ( ( io_register_data & ~MASK ) | ( ( i_data << SHIFT ) & MASK ) ); return; } diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_dccal.C b/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_dccal.C index 1d77dfd9f..1e4dfb326 100644 --- a/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_dccal.C +++ b/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_dccal.C @@ -281,6 +281,7 @@ fapi2::ReturnCode tx_zcal_run_sm( } else { + FAPI_DBG( "tx_zcal_run_sm: Tx Impedance Calibration Successful." ); FAPI_DBG( "tx_zcal_run_sm: Using zCal Results." ); FAPI_TRY( io::read( EDIP_TX_ZCAL_P, i_target, GROUP_00, LANE_00, l_data ), @@ -639,6 +640,8 @@ fapi2::ReturnCode rx_dccal_poll( "rx_dc_cal_poll: Rx Dccal Timeout: Loops(%d) delay(%d ns, %d cycles)", l_poll_count, DLY_10MS, DLY_50MIL_CYCLES ); + FAPI_DBG( "rx_dc_cal_poll: I/O EDI+ Xbus Rx Dccal Successful." ); + fapi_try_exit: FAPI_IMP( "rx_dc_cal_poll: I/O EDI+ Xbus Exiting" ); return fapi2::current_err; diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_linktrain.C b/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_linktrain.C index 3bd360492..b234b50fe 100644 --- a/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_linktrain.C +++ b/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_linktrain.C @@ -587,7 +587,7 @@ fapi2::ReturnCode linktrain_poll( FAPI_IMP( "linktrain_poll: P9 I/O EDI+ Xbus Entering" ); const uint8_t MAXLOOPS = 100; - const uint64_t DELAY_NS = 200; + const uint64_t DELAY_1MS = 1000000; const uint64_t DELAY_SIM_CYCLES = 20000000; const uint8_t LANE_00 = 0; uint8_t l_loops = 0; @@ -598,6 +598,8 @@ fapi2::ReturnCode linktrain_poll( // In the P9 EDI+ Xbus unit model, polling finishes in // 17 loops @ 20 million cycles = 340 million cycles + // For hardware timeout, we used what was used in p8, 1ms @ 100 cycles for + // a max of 100ms to complete training. while( ++l_loops < MAXLOOPS ) { // Get Done/Failed WDERF Status @@ -617,7 +619,7 @@ fapi2::ReturnCode linktrain_poll( break; } - FAPI_TRY( fapi2::delay( DELAY_NS, DELAY_SIM_CYCLES ) ); + FAPI_TRY( fapi2::delay( DELAY_1MS, DELAY_SIM_CYCLES ) ); } // Check the error conditions. @@ -675,17 +677,27 @@ fapi2::ReturnCode add_linktrain_failed_ffdc( //////////////////////////////////////////////////////////////////////////// // Master /////////////////////////////////////////////////////////////////////////// - l_rc = io::read( EDIP_RX_CTL_STAT1_E_PG, i_mtarget, i_mgroup, LANE_00, l_data ); + l_rc = io::read( EDIP_RX_CTL_CNTL1_E_PG, i_mtarget, i_mgroup, LANE_00, l_data ); if( l_rc == fapi2::FAPI2_RC_SUCCESS ) { ffdc.set_M_WDERF_START ( io::get( EDIP_RX_START_WDERF_ALIAS, l_data ) ); + } + else + { + ffdc.set_M_WDERF_START ( INVALID_FFDC ); + l_rc = fapi2::FAPI2_RC_SUCCESS; + } + + l_rc = io::read( EDIP_RX_CTL_STAT1_E_PG, i_mtarget, i_mgroup, LANE_00, l_data ); + + if( l_rc == fapi2::FAPI2_RC_SUCCESS ) + { ffdc.set_M_WDERF_DONE ( io::get( EDIP_RX_WDERF_DONE_ALIAS, l_data ) ); ffdc.set_M_WDERF_FAILED( io::get( EDIP_RX_WDERF_FAILED_ALIAS, l_data ) ); } else { - ffdc.set_M_WDERF_START ( INVALID_FFDC ); ffdc.set_M_WDERF_DONE ( INVALID_FFDC ); ffdc.set_M_WDERF_FAILED( INVALID_FFDC ); l_rc = fapi2::FAPI2_RC_SUCCESS; @@ -872,23 +884,33 @@ fapi2::ReturnCode add_linktrain_failed_ffdc( /////////////////////////////////////////////////////////////////////////// // Slave /////////////////////////////////////////////////////////////////////////// - l_rc = io::read( EDIP_RX_CTL_STAT1_E_PG, i_mtarget, i_mgroup, LANE_00, l_data ); + l_rc = io::read( EDIP_RX_CTL_CNTL1_E_PG, i_starget, i_sgroup, LANE_00, l_data ); if( l_rc == fapi2::FAPI2_RC_SUCCESS ) { ffdc.set_S_WDERF_START ( io::get( EDIP_RX_START_WDERF_ALIAS, l_data ) ); + } + else + { + ffdc.set_S_WDERF_START ( INVALID_FFDC ); + l_rc = fapi2::FAPI2_RC_SUCCESS; + } + + l_rc = io::read( EDIP_RX_CTL_STAT1_E_PG, i_starget, i_sgroup, LANE_00, l_data ); + + if( l_rc == fapi2::FAPI2_RC_SUCCESS ) + { ffdc.set_S_WDERF_DONE ( io::get( EDIP_RX_WDERF_DONE_ALIAS, l_data ) ); ffdc.set_S_WDERF_FAILED( io::get( EDIP_RX_WDERF_FAILED_ALIAS, l_data ) ); } else { - ffdc.set_S_WDERF_START ( INVALID_FFDC ); ffdc.set_S_WDERF_DONE ( INVALID_FFDC ); ffdc.set_S_WDERF_FAILED( INVALID_FFDC ); l_rc = fapi2::FAPI2_RC_SUCCESS; } - l_rc = io::read( EDIP_RX_CTL_STAT2_E_PG, i_mtarget, i_mgroup, LANE_00, l_data ); + l_rc = io::read( EDIP_RX_CTL_STAT2_E_PG, i_starget, i_sgroup, LANE_00, l_data ); if( l_rc == fapi2::FAPI2_RC_SUCCESS ) { @@ -901,7 +923,7 @@ fapi2::ReturnCode add_linktrain_failed_ffdc( } - l_rc = io::read( EDIP_RX_CTL_STAT4_E_PG, i_mtarget, i_mgroup, LANE_00, l_data ); + l_rc = io::read( EDIP_RX_CTL_STAT4_E_PG, i_starget, i_sgroup, LANE_00, l_data ); if( l_rc == fapi2::FAPI2_RC_SUCCESS ) { @@ -913,7 +935,7 @@ fapi2::ReturnCode add_linktrain_failed_ffdc( l_rc = fapi2::FAPI2_RC_SUCCESS; } - l_rc = io::read( EDIP_RX_CTL_MODE11_E_PG, i_mtarget, i_mgroup, LANE_00, l_data ); + l_rc = io::read( EDIP_RX_CTL_MODE11_E_PG, i_starget, i_sgroup, LANE_00, l_data ); if( l_rc == fapi2::FAPI2_RC_SUCCESS ) { @@ -925,7 +947,7 @@ fapi2::ReturnCode add_linktrain_failed_ffdc( l_rc = fapi2::FAPI2_RC_SUCCESS; } - l_rc = io::read( EDIP_RX_CTL_MODE12_E_PG, i_mtarget, i_mgroup, LANE_00, l_data ); + l_rc = io::read( EDIP_RX_CTL_MODE12_E_PG, i_starget, i_sgroup, LANE_00, l_data ); if( l_rc == fapi2::FAPI2_RC_SUCCESS ) { @@ -937,7 +959,7 @@ fapi2::ReturnCode add_linktrain_failed_ffdc( l_rc = fapi2::FAPI2_RC_SUCCESS; } - l_rc = io::read( EDIP_RX_GLBSM_STAT1_E_PG, i_mtarget, i_mgroup, LANE_00, l_data ); + l_rc = io::read( EDIP_RX_GLBSM_STAT1_E_PG, i_starget, i_sgroup, LANE_00, l_data ); if( l_rc == fapi2::FAPI2_RC_SUCCESS ) { @@ -950,7 +972,7 @@ fapi2::ReturnCode add_linktrain_failed_ffdc( } // Wiretest - l_rc = io::read( EDIP_RX_GLBSM_STAT1_E_PG, i_mtarget, i_mgroup, LANE_00, l_data ); + l_rc = io::read( EDIP_RX_GLBSM_STAT1_E_PG, i_starget, i_sgroup, LANE_00, l_data ); if( l_rc == fapi2::FAPI2_RC_SUCCESS ) { @@ -964,7 +986,7 @@ fapi2::ReturnCode add_linktrain_failed_ffdc( l_rc = fapi2::FAPI2_RC_SUCCESS; } - l_rc = io::read( EDIP_RX_CTL_STAT3_EO_PG, i_mtarget, i_mgroup, LANE_00, l_data ); + l_rc = io::read( EDIP_RX_CTL_STAT3_EO_PG, i_starget, i_sgroup, LANE_00, l_data ); if( l_rc == fapi2::FAPI2_RC_SUCCESS ) { @@ -976,7 +998,7 @@ fapi2::ReturnCode add_linktrain_failed_ffdc( l_rc = fapi2::FAPI2_RC_SUCCESS; } - l_rc = io::read( EDIP_RX_GLBSM_STAT2_E_PG, i_mtarget, i_mgroup, LANE_00, l_data ); + l_rc = io::read( EDIP_RX_GLBSM_STAT2_E_PG, i_starget, i_sgroup, LANE_00, l_data ); if( l_rc == fapi2::FAPI2_RC_SUCCESS ) { @@ -988,7 +1010,7 @@ fapi2::ReturnCode add_linktrain_failed_ffdc( l_rc = fapi2::FAPI2_RC_SUCCESS; } - l_rc = io::read( EDIP_RX_CTL_STAT5_E_PG, i_mtarget, i_mgroup, LANE_00, l_data ); + l_rc = io::read( EDIP_RX_CTL_STAT5_E_PG, i_starget, i_sgroup, LANE_00, l_data ); if( l_rc == fapi2::FAPI2_RC_SUCCESS ) { @@ -1005,7 +1027,7 @@ fapi2::ReturnCode add_linktrain_failed_ffdc( // Deskew // Eye Opt - l_rc = io::read( EDIP_RX_GLBSM_STAT1_EO_PG, i_mtarget, i_mgroup, LANE_00, l_data ); + l_rc = io::read( EDIP_RX_GLBSM_STAT1_EO_PG, i_starget, i_sgroup, LANE_00, l_data ); if( l_rc == fapi2::FAPI2_RC_SUCCESS ) { @@ -1017,7 +1039,7 @@ fapi2::ReturnCode add_linktrain_failed_ffdc( l_rc = fapi2::FAPI2_RC_SUCCESS; } - l_rc = io::read( EDIP_RX_CTL_CNTL13_EO_PG, i_mtarget, i_mgroup, LANE_00, l_data ); + l_rc = io::read( EDIP_RX_CTL_CNTL13_EO_PG, i_starget, i_sgroup, LANE_00, l_data ); if( l_rc == fapi2::FAPI2_RC_SUCCESS ) { @@ -1034,7 +1056,7 @@ fapi2::ReturnCode add_linktrain_failed_ffdc( } // Repair - l_rc = io::read( EDIP_RX_GLBSM_STAT4_E_PG, i_mtarget, i_mgroup, LANE_00, l_data ); + l_rc = io::read( EDIP_RX_GLBSM_STAT4_E_PG, i_starget, i_sgroup, LANE_00, l_data ); if( l_rc == fapi2::FAPI2_RC_SUCCESS ) { @@ -1046,7 +1068,7 @@ fapi2::ReturnCode add_linktrain_failed_ffdc( l_rc = fapi2::FAPI2_RC_SUCCESS; } - l_rc = io::read( EDIP_RX_GLBSM_STAT9_E_PG, i_mtarget, i_mgroup, LANE_00, l_data ); + l_rc = io::read( EDIP_RX_GLBSM_STAT9_E_PG, i_starget, i_sgroup, LANE_00, l_data ); if( l_rc == fapi2::FAPI2_RC_SUCCESS ) { diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_scominit.C b/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_scominit.C index 8660508d9..2bcec33d2 100644 --- a/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_scominit.C +++ b/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_scominit.C @@ -108,7 +108,6 @@ fapi2::ReturnCode p9_io_xbus_scominit( { // mark HWP entry FAPI_INF("p9_io_xbus_scominit: Entering ..."); - const uint8_t GROUP_00 = 0; const uint8_t LANE_00 = 0; fapi2::ReturnCode rc = fapi2::FAPI2_RC_SUCCESS; @@ -119,10 +118,27 @@ fapi2::ReturnCode p9_io_xbus_scominit( // assert IO reset to power-up bus endpoint logic // read-modify-write, set single reset bit (HW auto-clears) // on writeback - FAPI_TRY( io::rmw( EDIP_IORESET_HARD_BUS0, i_target, GROUP_00, LANE_00, 1 ), + FAPI_TRY( io::rmw( EDIP_RX_IORESET, i_target, i_group, LANE_00, 1 ), "I/O Xbus Scominit: Primary Set Reset Hard Failed." ); - FAPI_TRY( io::rmw( EDIP_IORESET_HARD_BUS0, i_connected_target, GROUP_00, LANE_00, 1 ), + FAPI_TRY( io::rmw( EDIP_TX_IORESET, i_target, i_group, LANE_00, 1 ), + "I/O Xbus Scominit: Primary Set Reset Hard Failed." ); + FAPI_TRY( io::rmw( EDIP_RX_IORESET, i_connected_target, i_group, LANE_00, 1 ), "I/O Xbus Scominit: Connected Set Reset Hard Failed." ); + FAPI_TRY( io::rmw( EDIP_TX_IORESET, i_connected_target, i_group, LANE_00, 1 ), + "I/O Xbus Scominit: Primary Set Reset Hard Failed." ); + + // Delay 1ns, 1 Million cycles -- Needed in sim, may not be needed in hw. + FAPI_TRY( fapi2::delay( 1, 1000000 ) ); + + FAPI_TRY( io::rmw( EDIP_RX_IORESET, i_target, i_group, LANE_00, 0 ), + "I/O Xbus Scominit: Primary Set Reset Hard Failed." ); + FAPI_TRY( io::rmw( EDIP_TX_IORESET, i_target, i_group, LANE_00, 0 ), + "I/O Xbus Scominit: Primary Set Reset Hard Failed." ); + FAPI_TRY( io::rmw( EDIP_RX_IORESET, i_connected_target, i_group, LANE_00, 0 ), + "I/O Xbus Scominit: Connected Set Reset Hard Failed." ); + FAPI_TRY( io::rmw( EDIP_TX_IORESET, i_connected_target, i_group, LANE_00, 0 ), + "I/O Xbus Scominit: Primary Set Reset Hard Failed." ); + // Set rx master/slave attribute prior to calling the scominit procedures. // The scominit procedure will reference the attribute to set the register field. @@ -175,11 +191,11 @@ fapi2::ReturnCode set_rx_master_mode( uint32_t l_connected_id = 0; uint8_t l_connected_attr = 0; - FAPI_TRY( p9_get_proc_fabric_group_id( i_target, l_primary_group_id ) ); - FAPI_TRY( p9_get_proc_fabric_group_id( i_target, l_connected_group_id ) ); + FAPI_TRY( p9_get_proc_fabric_group_id( i_target, l_primary_group_id ) ); + FAPI_TRY( p9_get_proc_fabric_group_id( i_ctarget, l_connected_group_id ) ); - FAPI_TRY( p9_get_proc_fabric_chip_id( i_target, l_primary_chip_id ) ); - FAPI_TRY( p9_get_proc_fabric_chip_id( i_target, l_connected_chip_id ) ); + FAPI_TRY( p9_get_proc_fabric_chip_id( i_target, l_primary_chip_id ) ); + FAPI_TRY( p9_get_proc_fabric_chip_id( i_ctarget, l_connected_chip_id ) ); l_primary_id = ( (uint32_t)l_primary_group_id << 8 ) + (uint32_t)l_primary_chip_id; l_connected_id = ( (uint32_t)l_connected_group_id << 8 ) + (uint32_t)l_connected_chip_id; |
