diff options
Diffstat (limited to 'src/import/chips/p9/procedures')
6 files changed, 416 insertions, 39 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index 141fb4cb5..94dd95850 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -137,7 +137,10 @@ HCD_HDR_ATTN ( attnOpcodes, 2); HCD_HDR_UINT64( magic_number, CPMR_MAGIC_NUMBER); HCD_HDR_UINT32( cpmrbuildDate, 0); HCD_HDR_UINT32( cpmrVersion, 0); -HCD_HDR_UINT8_VEC (cpmrReserveFlags, 7, 0); +HCD_HDR_UINT8_VEC (cpmrReserveFlags, 4, 0); +HCD_HDR_UINT8 ( selfRestoreVer, 0); +HCD_HDR_UINT8 ( stopApiVer, 0); +HCD_HDR_UINT8 ( urmorFix, 0); HCD_HDR_UINT8 ( fusedModeStatus, 0); HCD_HDR_UINT32( cmeImgOffset, 0); HCD_HDR_UINT32( cmeImgLength, 0); @@ -596,11 +599,11 @@ typedef struct typedef union CPMRSelfRestoreLayout { - uint8_t region[SELF_RESTORE_CODE_SIZE]; + uint8_t region[SMF_SELF_RESTORE_CODE_SIZE]; struct { cpmrHeader_t CPMRHeader; - uint8_t exe[SELF_RESTORE_CODE_SIZE - sizeof(cpmrHeader_t)]; + uint8_t exe[SMF_SELF_RESTORE_CODE_SIZE - sizeof(cpmrHeader_t)]; } elements; } CPMRSelfRestoreLayout_t; @@ -610,8 +613,8 @@ typedef union CPMRSelfRestoreLayout typedef struct { CPMRSelfRestoreLayout_t CPMR_SR; - uint8_t coreSelfRestore[SELF_RESTORE_CORE_REGS_SIZE]; - uint8_t reserve[CORE_SCOM_RESTORE_CPMR_OFFSET - SELF_RESTORE_SIZE_TOTAL]; + uint8_t coreSelfRestore[SMF_SELF_RESTORE_CORE_REGS_SIZE]; + uint8_t reserve[CORE_SCOM_RESTORE_CPMR_OFFSET - SMF_SELF_RESTORE_SIZE_TOTAL]; uint8_t coreScom[CORE_SCOM_RESTORE_SIZE_TOTAL]; } SelfRestoreLayout_t; diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C index fa0340fac..433d83f59 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C @@ -138,9 +138,23 @@ enum MAX_PM_REGION_HEADER = 3, MAX_EQ_SCOM_RESTORES = 255, SGPE_IMGAE_VERSION = 0x003, //Keeping in HWP to avoid hcode-HWP coreq + SMF_SELF_REST_SIGN_OFFSET = 0x1300, + SMF_SELF_SIGNATURE = 0x5f534d46, + CORE_REST_WORDS_PER_THREAD = (CORE_RESTORE_SIZE_PER_THREAD >> 2), }; /** + * @brief models a CPU register restoration area in STOP section of homer image. + */ +typedef struct +{ + uint8_t iv_threadRestoreArea[MAX_THREADS_PER_CORE][SMF_CORE_RESTORE_THREAD_AREA_SIZE]; + uint8_t iv_threadSaveArea[MAX_THREADS_PER_CORE][SMF_SELF_SAVE_THREAD_AREA_SIZE]; + uint8_t iv_coreRestoreArea[SMF_CORE_RESTORE_CORE_AREA_SIZE]; + uint8_t iv_coreSaveArea[SMF_CORE_SAVE_CORE_AREA_SIZE]; +} SmfSprRestoreRegion_t; + +/** * @brief struct used to manipulate scan ring in HOMER. */ struct RingBufData @@ -274,7 +288,7 @@ ImgSizeBank::ImgSizeBank() //p9_xip_images.h. Inorder to identify a full SRAM Image, we introduced a new ID //xxx_SRAM_IMAGE. - iv_secSize[ImgSec(PLAT_SELF, P9_XIP_SECTION_RESTORE_SELF, (char*)"Self Restore")] = SELF_RESTORE_CODE_SIZE; + iv_secSize[ImgSec(PLAT_SELF, P9_XIP_SECTION_RESTORE_SELF, (char*)"Self Restore")] = SMF_SELF_RESTORE_CODE_SIZE; iv_secSize[ImgSec(PLAT_SELF, P9_XIP_SECTION_RESTORE_CPMR, (char*)"CPMR Header")] = CPMR_HEADER_SIZE; iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_QPMR, (char*)"QPMR Header")] = HALF_KB; iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_LVL1_BL, (char*)"SGPE Boot Copier")] = SGPE_BOOT_COPIER_SIZE; @@ -677,6 +691,94 @@ fapi_try_exit: //------------------------------------------------------------------------------ +fapi2::ReturnCode initSelfRestoreRegion( Homerlayout_t* i_pChipHomer ) +{ + FAPI_INF(">> initSelfRestoreRegion"); + uint32_t l_fillBlr = SWIZZLE_4_BYTE(SELF_RESTORE_BLR_INST); + uint32_t l_fillAttn = SWIZZLE_4_BYTE(CORE_RESTORE_PAD_OPCODE); + uint32_t l_byteCnt = 0; + uint32_t * l_pSelfRestLoc = + (uint32_t *)&i_pChipHomer->cpmrRegion.selfRestoreRegion.coreSelfRestore[0]; + + SmfSprRestoreRegion_t * l_pSaveRestore = + (SmfSprRestoreRegion_t *)&i_pChipHomer->cpmrRegion.selfRestoreRegion.coreSelfRestore[0]; + + while( l_byteCnt < SELF_RESTORE_CORE_REGS_SIZE ) + { + memcpy( l_pSelfRestLoc, &l_fillAttn, sizeof( uint32_t ) ); + l_byteCnt += 4; + l_pSelfRestLoc++; + } + + //Initialize Core SPR and Thread SPR start boundary with BLR instruction. + + FAPI_INF( " Size of SmfSprRestoreRegion_t 0x%08x", sizeof( SmfSprRestoreRegion_t ) ); + for( size_t l_coreId = 0; l_coreId < MAX_CORES_PER_CHIP; l_coreId++ ) + { + memcpy( (uint32_t *)&l_pSaveRestore->iv_coreRestoreArea[0], &l_fillBlr, sizeof(uint32_t) ); + + for( size_t l_threadId = 0; l_threadId < MAX_THREADS_PER_CORE; l_threadId++ ) + { + memcpy( &l_pSaveRestore->iv_threadRestoreArea[l_threadId][0], + &l_fillBlr, + sizeof(uint32_t) ); + } + + l_pSaveRestore++; + } + + FAPI_INF("<< initSelfRestoreRegion"); + + return fapi2::FAPI2_RC_SUCCESS; +} + +//------------------------------------------------------------------------------ + +fapi2::ReturnCode initSelfSaveRestoreEntries( Homerlayout_t* i_pChipHomer, + P9FuncModel & i_procFuncModel ) +{ + FAPI_DBG(">> initSelfSaveRestoreEntries" ); + StopReturnCode_t l_retCode; + uint32_t l_corePos = 0; + + for( l_corePos = 0; l_corePos < MAX_CORES_PER_CHIP; l_corePos++ ) + { + if( !i_procFuncModel.isCoreFunctional( l_corePos ) ) + { + continue; + } + + FAPI_INF( "Core Pos 0x%02d", l_corePos ); + l_retCode = p9_stop_init_cpureg( (void *)i_pChipHomer, l_corePos ); + + FAPI_ASSERT( ( STOP_SAVE_SUCCESS == l_retCode ), + fapi2::SELF_RESTORE_INIT_FAILED() + .set_HOMER_PTR( i_pChipHomer ) + .set_CORE_POS( l_corePos ) + .set_FAILURE_CODE( l_retCode ) + .set_EC_LEVEL( i_procFuncModel.getChipLevel() ) + .set_CHIP_TYPE( i_procFuncModel.getChipName() ), + "Failed To Initialize The Self-Restore Region 0x%08x", l_retCode ); + + l_retCode = p9_stop_init_self_save( (void *)i_pChipHomer, l_corePos ); + + FAPI_ASSERT( ( STOP_SAVE_SUCCESS == l_retCode ), + fapi2::SELF_SAVE_INIT_FAILED() + .set_HOMER_PTR( i_pChipHomer ) + .set_CORE_POS( l_corePos ) + .set_FAILURE_CODE( l_retCode ) + .set_EC_LEVEL( i_procFuncModel.getChipLevel() ) + .set_CHIP_TYPE( i_procFuncModel.getChipName() ), + "Failed To Initialize The Self-Save Region 0x%08x", (uint32_t)l_retCode ); + } + + fapi_try_exit: + FAPI_DBG("<< initSelfSaveRestoreEntries" ); + return fapi2::current_err; +} + +//------------------------------------------------------------------------------ + uint32_t getXipImageSectn( uint8_t * i_srcPtr, uint8_t i_secId, uint8_t i_ecLevel, P9XipSection& o_ppeSection ) { @@ -1277,8 +1379,9 @@ void updateCpmrCmeRegion( Homerlayout_t* i_pChipHomer ) * @brief updates various CPMR fields which are associated with self restore code. * @param[in] i_pChipHomer points to start of P9 HOMER. * @param[in] i_fuseState core fuse status + * @param[in] i_urmorFix true if URMOR correction is needed else false. */ -void updateCpmrHeaderSR( Homerlayout_t* i_pChipHomer, uint8_t i_fusedState ) +void updateCpmrHeaderSR( Homerlayout_t* i_pChipHomer, uint8_t i_fusedState, uint8_t i_urmorFix, uint32_t i_smfSign ) { FAPI_INF(">> updateCpmrHeaderSR"); cpmrHeader_t* pCpmrHdr = @@ -1288,6 +1391,18 @@ void updateCpmrHeaderSR( Homerlayout_t* i_pChipHomer, uint8_t i_fusedState ) //populate CPMR header pCpmrHdr->fusedModeStatus = i_fusedState ? uint32_t(FUSED_CORE_MODE) : uint32_t(NONFUSED_CORE_MODE); + + if( i_urmorFix ) + { + if( SMF_SELF_SIGNATURE == i_smfSign ) + { + pCpmrHdr->selfRestoreVer = 0x01; + pCpmrHdr->stopApiVer = 0x01; + } + + pCpmrHdr->urmorFix = 0x01; + } + pCmeHdr->g_cme_mode_flags = SWIZZLE_4_BYTE(i_fusedState ? 1 : 0); FAPI_INF("CPMR SR"); @@ -1297,6 +1412,9 @@ void updateCpmrHeaderSR( Homerlayout_t* i_pChipHomer, uint8_t i_fusedState ) SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset) * 32, SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset)); FAPI_DBG("CME Image Size : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgLength)); + FAPI_DBG("URMOR WorkAround Needed : %s", pCpmrHdr->urmorFix ? "Yes" : "No" ); + FAPI_DBG("Self Restore Ver : 0x%02d", pCpmrHdr->selfRestoreVer ); + FAPI_DBG("STOP API Ver : 0x%02d", pCpmrHdr->stopApiVer ); FAPI_INF("<< updateCpmrHeaderSR"); } @@ -1527,6 +1645,45 @@ fapi_try_exit: //------------------------------------------------------------------------------ +fapi2::ReturnCode initSmfDisabledSelfRestore( Homerlayout_t * i_pChipHomer ) +{ + FAPI_INF(">> initSmfDisabledSelfRestore") + uint32_t wordCnt = 0; + uint32_t l_fillPattern = 0; + uint32_t l_fillBlr = SWIZZLE_4_BYTE(SELF_RESTORE_BLR_INST); + uint32_t l_fillAttn = SWIZZLE_4_BYTE(CORE_RESTORE_PAD_OPCODE); + uint32_t * l_pSelfWord = (uint32_t *)&i_pChipHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.region[SELF_RESTORE_CODE_SIZE]; + uint32_t l_regionSize = SELF_RESTORE_CORE_REGS_SIZE >> 2; // Size in words + + while( wordCnt < l_regionSize ) + { + + if( ( 0 == wordCnt ) || ( 0 == ( wordCnt % CORE_REST_WORDS_PER_THREAD ) )) + { + l_fillPattern = l_fillBlr; + } + else + { + l_fillPattern = l_fillAttn; + } + + //Lab Need: First instruction in thread SPR restore region should be a blr instruction. + //This helps in a specific lab scenario. If Self Restore region is populated only for + //select number of threads, other threads will not hit attention during the self restore + //sequence. Instead, execution will hit a blr and control should return to thread launcher + //region. + + memcpy( l_pSelfWord, &l_fillPattern, sizeof( uint32_t )); + l_pSelfWord++; + wordCnt++; + } + + FAPI_INF("<< initSmfDisabledSelfRestore") + return fapi2::current_err; +} + +//------------------------------------------------------------------------------ + /** * @brief copies core self restore section from hardware image to HOMER. * @param[in] i_pImageIn points to start of hardware image. @@ -1546,10 +1703,9 @@ fapi2::ReturnCode buildCoreRestoreImage( void* const i_pImageIn, fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; //Let us find XIP Header for Core Self Restore Image P9XipSection ppeSection; - uint8_t* pSelfRestImg = NULL; - uint32_t wordCnt = 0; - uint32_t l_fillBlr = SWIZZLE_4_BYTE(SELF_RESTORE_BLR_INST); - uint32_t l_fillAttn = SWIZZLE_4_BYTE(CORE_RESTORE_PAD_OPCODE); + uint8_t* pSelfRestImg = NULL; + uint8_t * l_pTempByte = NULL; + uint32_t l_pSmfSignature = 0x00; rcTemp = p9_xip_get_section( i_pImageIn, P9_XIP_SECTION_HW_RESTORE, &ppeSection ); @@ -1603,38 +1759,34 @@ fapi2::ReturnCode buildCoreRestoreImage( void* const i_pImageIn, .set_ACTUAL_SIZE( ppeSection.iv_size ), "Failed to update CPMR Header in HOMER" ); + l_pTempByte = i_pChipHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.region; + l_pSmfSignature = SWIZZLE_4_BYTE( *(uint32_t *)( l_pTempByte + SMF_SELF_REST_SIGN_OFFSET ) ); + + FAPI_DBG(" SMF Signature 0x%08x" , l_pSmfSignature ); + if( i_imgType.coreSprBuild ) { //Pad undefined or runtime section with ATTN Opcode //Padding SPR restore area with ATTN Opcode FAPI_INF("Padding CPMR Core Restore portion with Attn opcodes"); - while( wordCnt < SELF_RESTORE_CORE_REGS_SIZE ) + if( i_procFuncModel.hasUrmorBug() && ( SMF_SELF_SIGNATURE == l_pSmfSignature ) ) // Nimbus >= DD22 and Cumulus >= DD13 { - uint32_t l_fillPattern = 0; + FAPI_TRY( initSelfRestoreRegion( i_pChipHomer ), + "Failed To Initialize The Self-Restore Region" ); - if( ( 0 == wordCnt ) || ( 0 == ( wordCnt % CORE_RESTORE_SIZE_PER_THREAD ) )) - { - l_fillPattern = l_fillBlr; - } - else - { - l_fillPattern = l_fillAttn; - } - - //Lab Need: First instruction in thread SPR restore region should be a blr instruction. - //This helps in a specific lab scenario. If Self Restore region is populated only for - //select number of threads, other threads will not hit attention during the self restore - //sequence. Instead, execution will hit a blr and control should return to thread launcher - //region. - - memcpy( (uint32_t*)&i_pChipHomer->cpmrRegion.selfRestoreRegion.coreSelfRestore[wordCnt], - &l_fillPattern, - sizeof( uint32_t )); - wordCnt += 4; + FAPI_TRY( initSelfSaveRestoreEntries( i_pChipHomer, i_procFuncModel ), + "Failed To Initialize The Self-Save Region" ); + } + else // for backward compatibility + { + FAPI_TRY( initSmfDisabledSelfRestore( i_pChipHomer ), + "Failed To Initialize Self-Restore Region In Non SMF Mode" ); } + } - updateCpmrHeaderSR( i_pChipHomer, i_fusedState ); + + updateCpmrHeaderSR( i_pChipHomer, i_fusedState, i_procFuncModel.hasUrmorBug(), l_pSmfSignature ); if( i_imgType.coreScomBuild ) { @@ -4378,6 +4530,145 @@ void customizeMagicWord( Homerlayout_t* i_pHomer ) //--------------------------------------------------------------------------- +/** + * @brief returns PIR value for a given core and thread. + * @param[in] i_corePos core position + * @param[in] i_threadPos thread position + * @param[in] i_fuseMode fuse status of core. + * @return PIR value + */ +uint64_t getPirValue( uint32_t i_corePos, uint32_t i_threadPos, uint8_t i_fuseMode ) +{ + uint64_t l_pir = 0; + uint8_t l_tempPir = 0; + l_tempPir = 0; + l_tempPir = (i_corePos / MAX_CORES_PER_QUAD ) << MAX_CORES_PER_QUAD; + i_corePos = i_corePos % MAX_CORES_PER_QUAD; + + switch( i_corePos ) + { + case 0: + break; + + case 1: + if( i_fuseMode ) + { + l_tempPir |= FUSED_CORE_BIT3; + } + else + { + l_tempPir |= FUSED_CORE_BIT1; + } + + break; + + case 2: + l_tempPir |= FUSED_CORE_BIT0; + break; + + case 3: + if( i_fuseMode ) + { + l_tempPir |= ( FUSED_CORE_BIT0 | FUSED_CORE_BIT3 ); + } + else + { + l_tempPir |= (FUSED_CORE_BIT0 | FUSED_CORE_BIT1 ); + } + + break; + } + + switch( i_threadPos ) + { + case 0: + break; + + case 1: + if( i_fuseMode ) + { + l_tempPir |= FUSED_CORE_BIT2; + } + else + { + l_tempPir |= FUSED_CORE_BIT3; + } + + break; + + case 2: + if( i_fuseMode ) + { + l_tempPir |= FUSED_CORE_BIT1; + } + else + { + l_tempPir |= FUSED_CORE_BIT2; + } + + break; + + case 3: + if( i_fuseMode ) + { + l_tempPir |= ( FUSED_CORE_BIT1 | FUSED_CORE_BIT2 ); + } + else + { + l_tempPir |= ( FUSED_CORE_BIT2 | FUSED_CORE_BIT3); + } + + break; + } + + l_pir = l_tempPir; + + return l_pir; +} + +//--------------------------------------------------------------------------- + +/** + * @brief creates URMOR restore value in HOMER. + * @param[in] i_pHomerImage points to P9 chip's HOMER. + * @param[in] i_fuseMode fuse status of core + * @param[in] i_chipFuncModel describes config details of the P9 chip + * @return PIR value + */ +fapi2::ReturnCode addUrmorRestore( void * const i_pHomerImage, + uint8_t i_fuseMode, + P9FuncModel & i_chipFuncModel ) +{ + #ifdef __URMOR_TEST + + // to verify UV and HV exit in Cronus environment. + uint64_t l_pir = 0; + StopReturnCode_t l_rc; + + for( uint8_t l_corePos = 0; l_corePos < MAX_CORES_PER_CHIP; l_corePos++ ) + { + if( i_chipFuncModel.isCoreFunctional( l_corePos ) ) + { + l_pir = getPirValue( l_corePos, 0, i_fuseMode ); + l_rc = stopImageSection::p9_stop_save_cpureg( i_pHomerImage, + P9_STOP_SPR_URMOR, + 0x00, + l_pir ); + FAPI_ASSERT( ( !l_rc ), + fapi2::URMOR_RESTORE_ENTRY_FAILED() + .set_PIR( l_pir ) + .set_STOP_API_RC( l_rc ), + "Failed To Create URMOR Restore Entry" ); + } + } + +fapi_try_exit: + #endif + return fapi2::current_err; +} + +//--------------------------------------------------------------------------- + fapi2::ReturnCode p9_hcode_image_build( CONST_FAPI2_PROC& i_procTgt, void* const i_pImageIn, void* i_pHomerImage, @@ -4602,6 +4893,9 @@ fapi2::ReturnCode p9_hcode_image_build( CONST_FAPI2_PROC& i_procTgt, //customize magic word based on endianess customizeMagicWord( pChipHomer ); + FAPI_TRY( addUrmorRestore( i_pHomerImage, fuseModeState, l_chipFuncModel ), + "Failed to create URMOR restore entry" ); + fapi_try_exit: FAPI_IMP("<< p9_hcode_image_build" ); return fapi2::current_err; diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C b/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C index def3c096b..62b1b9d3d 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C @@ -776,7 +776,8 @@ P9FuncModel::P9FuncModel( ): iv_funcExes(0), iv_funcQuads(0), iv_ddLevel(0), - iv_chipName(0) + iv_chipName(0), + iv_urmorBug(0) { } //------------------------------------------------------------------------- @@ -801,11 +802,12 @@ P9FuncModel::P9FuncModel( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP >& i_ FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, i_procTgt, iv_ddLevel); FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, i_procTgt, iv_chipName); + FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW403111, i_procTgt, iv_urmorBug); FAPI_DBG("functional core : 0x%08x Ex : 0x%08x quad 0x%08x" - "EC : 0x%02x ChipName : 0x%02x", + "EC : 0x%02x ChipName : 0x%02x URMOR Bug 0x%02x", iv_funcCores, iv_funcExes, iv_funcQuads, iv_ddLevel, - iv_chipName ); + iv_chipName, iv_urmorBug ); } //--------------------------------------------------------------------------- @@ -842,8 +844,18 @@ uint8_t P9FuncModel::getChipLevel() const return iv_ddLevel; } +//------------------------------------------------------------------------- uint8_t P9FuncModel::getChipName() const { return iv_chipName; } + +//------------------------------------------------------------------------- +bool P9FuncModel::hasUrmorBug() const +{ + return iv_urmorBug ? true : false; +} + +//------------------------------------------------------------------------- + } diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.H b/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.H index 98a23d1fb..21f252f2f 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.H @@ -321,6 +321,11 @@ class P9FuncModel uint8_t getChipName() const; /** + * returns true if URMOR has a hw bug else false. + */ + bool hasUrmorBug() const; + + /** * @brief constructor */ P9FuncModel( ); @@ -332,8 +337,9 @@ class P9FuncModel uint16_t iv_funcExes; uint8_t iv_funcQuads; uint8_t iv_ddLevel; - uint8_t iv_chipName; - uint8_t iv_reserve[3]; + uint8_t iv_chipName; + uint8_t iv_urmorBug; + uint8_t iv_reserve[2]; }; }// namesapce p9_hcodeImageBuild ends diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index d55877da8..5a0917648 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -7905,4 +7905,28 @@ </chipEcFeature> </attribute> <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW403111</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + mtspr URMOR, rX will add the PPC instruction text to the Rx value + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x22</value> + <test>LESS_THAN_OR_EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_CUMULUS</name> + <ec> + <value>0x13</value> + <test>LESS_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> </attributes> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml index 52f4d111a..e5dd8a3ab 100755 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml @@ -686,7 +686,6 @@ <priority>HIGH</priority> </callout> </hwpError> - <!-- *********************************************************************** --> <hwpError> <rc>RC_P9_PGPE_AUX_TASK_BIN_SIZE_ERROR</rc> @@ -702,4 +701,43 @@ </callout> </hwpError> <!-- *********************************************************************** --> + <hwpError> + <rc>RC_SELF_RESTORE_INIT_FAILED</rc> + <description>hcode image build procedure failed to initialize self-restore region.</description> + <ffdc>HOMER_PTR</ffdc> + <ffdc>CORE_POS</ffdc> + <ffdc>FAILURE_CODE</ffdc> + <ffdc>EC_LEVEL</ffdc> + <ffdc>CHIP_TYPE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_SELF_SAVE_INIT_FAILED</rc> + <description>hcode image build procedure failed to initialize self-save region.</description> + <ffdc>HOMER_PTR</ffdc> + <ffdc>CORE_POS</ffdc> + <ffdc>FAILURE_CODE</ffdc> + <ffdc>EC_LEVEL</ffdc> + <ffdc>CHIP_TYPE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_URMOR_RESTORE_ENTRY_FAILED</rc> + <description>hcode image build procedure failed to create URMOR restore entry</description> + <ffdc>PIR</ffdc> + <ffdc>STOP_API_RC</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> </hwpErrors> |
