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-rw-r--r--src/import/chips/p9/procedures/xml/error_info/p9_pm_pss_errors.xml40
1 files changed, 39 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_pss_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_pss_errors.xml
index 4e830f492..fe96bed21 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_pss_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_pss_errors.xml
@@ -5,7 +5,7 @@
<!-- -->
<!-- OpenPOWER HostBoot Project -->
<!-- -->
-<!-- Contributors Listed Below - COPYRIGHT 2015,2017 -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2018 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
@@ -55,6 +55,44 @@
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
+ <rc>RC_PM_PSS_ADC_WRITE_WHILE_BUSY</rc>
+ <description>SPI ADC was written while the bridge was busy. Cleared with
+ coming reset.
+ </description>
+ <ffdc>CHIP</ffdc>
+ <ffdc>POLLCOUNT</ffdc>
+ <collectRegisterFfdc>
+ <id>PSS_FFDC_REGISTERS</id>
+ <target>CHIP</target>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ </collectRegisterFfdc>
+ <callout>
+ <target>CODE</target>
+ <priority>HIGH</priority>
+ </callout>
+ </hwpError>
+ <!-- *********************************************************************** -->
+ <hwpError>
+ <rc>RC_PM_PSS_ADC_TIMEOUT</rc>
+ <description>SPIADC timed waiting to be quiesced. The SPIADC will be reset
+ anyway so as to attempt to recover the interface.
+ </description>
+ <ffdc>CHIP</ffdc>
+ <ffdc>POLLCOUNT</ffdc>
+ <ffdc>MAXPOLLS</ffdc>
+ <ffdc>TIMEOUTUS</ffdc>
+ <collectRegisterFfdc>
+ <id>PSS_FFDC_REGISTERS</id>
+ <target>CHIP</target>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ </collectRegisterFfdc>
+ <callout>
+ <target>CHIP</target>
+ <priority>HIGH</priority>
+ </callout>
+ </hwpError>
+ <!-- *********************************************************************** -->
+ <hwpError>
<rc>RC_PM_PSS_P2S_ERROR</rc>
<description>SPIP2S error bit asserted waiting for operation to complete.
</description>
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