diff options
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/pm')
3 files changed, 41 insertions, 9 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C index 8579f3df4..47f6f561d 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C @@ -50,6 +50,7 @@ /// Clear CME flags and scratch registers as these will be setup /// via CME booting during SGPE boot /// Clear PPM Errors +/// Clear Hcode Error Injection enable bits /// Restore PPM Error mask value from HWP attribute /// } /// } @@ -91,6 +92,7 @@ #include <p9_ppe_defs.H> #include <p9_resclk_defines.H> #include <p9_pstates_cmeqm.h> +#include <p9_pm_hcd_flags.h> #include <p9_pm_utils.H> // ----------------------------------------------------------------------------- @@ -339,6 +341,20 @@ fapi2::ReturnCode pm_corequad_init( FAPI_TRY(fapi2::putScom(l_core_chplt, l_address, l_data64), "ERROR: Failed to clear CORE PPM ERROR"); + FAPI_INF("Clearing Hcode Error Injection and other CSAR settings ..."); + // *INDENT-OFF* + l_data64.flush<0>() + .setBit<p9hcd::CPPM_CSAR_FIT_HCODE_ERROR_INJECT>() + .setBit<p9hcd::CPPM_CSAR_ENABLE_PSTATE_REGISTRATION_INTERLOCK>() + .setBit<p9hcd::CPPM_CSAR_PSTATE_HCODE_ERROR_INJECT>() + .setBit<p9hcd::CPPM_CSAR_STOP_HCODE_ERROR_INJECT>(); + // Note: CPPM_CSAR_DISABLE_CME_NACK_ON_PROLONGED_DROOP is NOT + // cleared as this is a persistent, characterization setting + // *INDENT-ON* + l_address = C_CPPM_CSAR_CLEAR; + FAPI_TRY(fapi2::putScom(l_core_chplt, l_address, l_data64), + "ERROR: Failed to clear the CSAR register"); + // Restore CORE PPM Error Mask FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CORE_PPM_ERRMASK, l_core_chplt, diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C index 59904d7c3..8483b9308 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C @@ -48,7 +48,13 @@ // ----------------------------------------------------------------------------- // Constants // ----------------------------------------------------------------------------- -// @todo RTC 148540 Refine this values for the lab + +// Map the auto generated names to clearer ones +static const uint64_t PU_OCB_OCI_OCCFLG_CLEAR = PU_OCB_OCI_OCCFLG_SCOM1; +static const uint64_t PU_OCB_OCI_OCCFLG_SET = PU_OCB_OCI_OCCFLG_SCOM2; +static const uint64_t PU_OCB_OCI_OCCFLG2_CLEAR = P9N2_PU_OCB_OCI_OCCFLG2_SCOM1; +static const uint64_t PU_OCB_OCI_OCCFLG2_SET = P9N2_PU_OCB_OCI_OCCFLG2_SCOM2; + // Following constants hold an approximate value. static const uint32_t PGPE_TIMEOUT_MS = 500; static const uint32_t PGPE_TIMEOUT_MCYCLES = 20; @@ -157,6 +163,12 @@ fapi2::ReturnCode pstate_gpe_init( .insertFromRight<4, 4>(0xA); // FIT FAPI_TRY(fapi2::putScom(i_target, PU_GPE2_GPETSEL_SCOM, l_data64)); + // Clear error injection bits + l_data64.flush<0>() + .setBit<p9hcd::OCCFLG2_PGPE_HCODE_FIT_ERR_INJ>() + .setBit<p9hcd::OCCFLG2_PGPE_HCODE_PSTATE_REQ_ERR_INJ>(); + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCFLG2_CLEAR, l_data64)); + // Program XCR to ACTIVATE PGPE FAPI_INF(" Starting the PGPE..."); l_xcr.flush<0>().insertFromRight(p9hcd::HARD_RESET, 1, 3); diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C index 02ee7c5b9..8c3d84409 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C @@ -43,6 +43,7 @@ /// - call p9_pm_pba_init in PM_RESET mode to get the PBA in "boot" mode /// - Read the SGPE IVPR value that is in HOMER from Attribute written /// by p9_hcode_image_build +/// - Clear error injection bits /// - Sreset the SGPE to start the boot copier from . /// - Polls OCC Flag bit for HCode init completion /// - Starting the SGPE will cause a "reboot" of functional CMEs @@ -72,16 +73,15 @@ #include <p9_misc_scom_addresses_fld.H> #include <p9n2_misc_scom_addresses.H> -//#include <p9_ppe_state.H> @todo RTC 147996 to incorporate PPE state removing strings. - - // ---------------------------------------------------------------------- // Constants // ---------------------------------------------------------------------- // Map the auto generated names to clearer ones -static const uint64_t PU_OCB_OCI_OCCFLG_CLEAR = PU_OCB_OCI_OCCFLG_SCOM1; -static const uint64_t PU_OCB_OCI_OCCFLG_SET = PU_OCB_OCI_OCCFLG_SCOM2; +static const uint64_t PU_OCB_OCI_OCCFLG_CLEAR = PU_OCB_OCI_OCCFLG_SCOM1; +static const uint64_t PU_OCB_OCI_OCCFLG_SET = PU_OCB_OCI_OCCFLG_SCOM2; +static const uint64_t PU_OCB_OCI_OCCFLG2_CLEAR = P9N2_PU_OCB_OCI_OCCFLG2_SCOM1; +static const uint64_t PU_OCB_OCI_OCCFLG2_SET = P9N2_PU_OCB_OCI_OCCFLG2_SCOM2; static const uint32_t SGPE_TIMEOUT_MS = 2500; // Guess at this time static const uint32_t SGPE_TIMEOUT_MCYCLES = 20; // Guess at this time @@ -317,6 +317,10 @@ fapi2::ReturnCode p9_pm_stop_gpe_init( .insertFromRight<4, 4>(0xA); // FIT FAPI_TRY(fapi2::putScom(i_target, PU_GPE3_GPETSEL_SCOM, l_data64)); + // Clear error injection bits + l_data64.flush<0>().setBit<p9hcd::OCCFLG2_SGPE_HCODE_STOP_REQ_ERR_INJ>(); + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCFLG2_CLEAR, l_data64)); + // Set the Malf Alert Enabled policy to OCCFLG2 reg bit 29 FAPI_IMP ("Malf Alert Policy Enabled: %d", malfAlertEnable); @@ -324,11 +328,11 @@ fapi2::ReturnCode p9_pm_stop_gpe_init( if (malfAlertEnable == fapi2::ENUM_ATTR_PM_MALF_ALERT_ENABLE_TRUE) { - FAPI_TRY(fapi2::putScom(i_target, P9N2_PU_OCB_OCI_OCCFLG2_SCOM2, l_data64)); + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCFLG2_SET, l_data64)); } else { - FAPI_TRY(fapi2::putScom(i_target, P9N2_PU_OCB_OCI_OCCFLG2_SCOM1, l_data64)); + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCFLG2_CLEAR, l_data64)); } FAPI_IMP ("Malf Alert Policy Set to OCC FLAG2 .. now init SGPE"); @@ -540,7 +544,7 @@ fapi2::ReturnCode stop_gpe_reset( FAPI_INF(" Clear SGPE_ACTIVE in OCC Flag Register..."); l_data64.flush<0>().setBit<p9hcd::SGPE_ACTIVE>(); - FAPI_TRY(putScom(i_target, PU_OCB_OCI_OCCFLG_SCOM1, l_data64)); + FAPI_TRY(putScom(i_target, PU_OCB_OCI_OCCFLG_CLEAR, l_data64)); fapi_try_exit: FAPI_IMP("<< stop_gpe_reset..."); |
