diff options
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib')
15 files changed, 85 insertions, 141 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C index a9196951b..43694ac2d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C @@ -30,7 +30,7 @@ // *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -211,7 +211,7 @@ fapi2::ReturnCode rtt_wr_to_rtt_nom_helper(const fapi2::Target<TARGET_TYPE_DIMM> FAPI_ASSERT( false, fapi2::MSS_INVALID_RTT_WR_ENCODING(). set_RTT_WR(i_rtt_wr). - set_TARGET(i_target), + set_DIMM_TARGET(i_target), "Received invalid RTT_WR value: 0x%02x for %s.", i_rtt_wr, mss::c_str(i_target) ); break; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C index 7926425a6..9df9a63a9 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C @@ -2013,7 +2013,7 @@ fapi2::ReturnCode eff_dimm::dimm_rcbx() break; default: - FAPI_ERR("%s Error with C++ enum in eff_dimm.C. %d recieved", mss::c_str(iv_dimm), l_qs_enabled); + FAPI_ERR("%s Error with C++ enum in eff_dimm.C. %d received", mss::c_str(iv_dimm), l_qs_enabled); fapi2::Assert(false); } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H index 7daa12437..2bbcdc44d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H @@ -25,7 +25,7 @@ // *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Aandre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB @@ -100,15 +100,16 @@ class eff_dimm iv_port_index = mss::index(iv_mca); iv_dimm_index = mss::index(iv_dimm); - FAPI_TRY( iv_pDecoder->medium_timebase(iv_mtb) ); - FAPI_TRY( iv_pDecoder->fine_timebase(iv_ftb) ); + FAPI_TRY( iv_pDecoder->medium_timebase(iv_mtb), "Failed medium timebase in eff_dimm()" ); + FAPI_TRY( iv_pDecoder->fine_timebase(iv_ftb), "Failed medium timebase in eff_dimm()" ); FAPI_TRY( clock_period(iv_dimm, iv_tCK_in_ps), "Failed to calculate clock period (tCK)" ); FAPI_TRY( mss::mrw_refresh_rate_request(iv_refresh_rate_request), "Failed mrw_temp_refresh_rate_request()" ); FAPI_TRY( mss::mrw_fine_refresh_mode(iv_refresh_mode), "Failed mrw_fine_refresh_mode()" ); - FAPI_TRY( mss::freq(find_target<fapi2::TARGET_TYPE_MCBIST>(iv_dimm), iv_freq)); + FAPI_TRY( mss::freq(find_target<fapi2::TARGET_TYPE_MCBIST>(iv_dimm), iv_freq), + "Failed accessing mss::freq in eff_dimm"); FAPI_INF("Calculated clock period - tCK (ps): %d for %s", iv_tCK_in_ps, mss::c_str(iv_dimm)); FAPI_INF("Calculated frequency (ps): %d for %s", iv_freq, mss::c_str(iv_dimm)); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.C index 3c458c5f7..26b391976 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.C @@ -223,7 +223,6 @@ fapi2::ReturnCode check_dead_load( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& l_live_dimm = ( l_found == l_functional_dimms.end() ) ? l_live_dimm : l_plugged_dimms[0]; FAPI_ASSERT( false, fapi2::MSS_DEAD_LOAD_ON_PORT() - .set_DEAD_DIMM(l_dead_dimm) .set_FUNCTIONAL_DIMM(l_live_dimm), "%s has two DIMMs installed, but one is deconfigured (%d), so deconfiguring the other (%d) because of dead load", mss::c_str(i_target), mss::index(l_dead_dimm), mss::index(l_live_dimm)); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C index 5755589ac..3d19b1764 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C @@ -261,7 +261,7 @@ fapi2::ReturnCode setup_phase_rotator_control_registers( const fapi2::Target<TAR // From the DDR PHY workbook constexpr uint64_t CONTINUOUS_UPDATE = 0x8024; - FAPI_INF("continuous update: 0x%x", CONTINUOUS_UPDATE); + FAPI_INF("%s continuous update: 0x%x", mss::c_str(i_target), CONTINUOUS_UPDATE); constexpr uint64_t SIM_OVERRIDE = 0x8080; constexpr uint64_t PHASE_CNTL_EN = 0x8020; @@ -302,7 +302,7 @@ fapi2::ReturnCode setup_phase_rotator_control_registers( const fapi2::Target<TAR // All the MCA (and both registers) will be in the same state, so we can get the first and use it to create the // values for the others. - FAPI_INF("Write 0x%lx into the ADR SysClk Phase Rotator Control Regs", l_update); + FAPI_INF("%s Write 0x%lx into the ADR SysClk Phase Rotator Control Regs", mss::c_str(i_target), l_update); // WRCLK Phase rotators are taken care of in the phy initfile. BRS 6/16. @@ -1482,7 +1482,7 @@ fapi2::ReturnCode setup_wr_level_terminations( const fapi2::Target<fapi2::TARGET FAPI_TRY( mss::rank::get_ranks_in_pair(i_target, i_rp, l_ranks) ); FAPI_ASSERT( !l_ranks.empty(), fapi2::MSS_NO_RANKS_IN_RANK_PAIR() - .set_TARGET(i_target) + .set_MCA_TARGET(i_target) .set_RANK_PAIR(i_rp), "No ranks configured in MCA %s, rank pair %d", mss::c_str(i_target), @@ -1541,7 +1541,7 @@ fapi2::ReturnCode restore_mainline_terminations( const fapi2::Target<fapi2::TARG FAPI_TRY( mss::rank::get_ranks_in_pair(i_target, i_rp, l_ranks) ); FAPI_ASSERT( !l_ranks.empty(), fapi2::MSS_NO_RANKS_IN_RANK_PAIR() - .set_TARGET(i_target) + .set_MCA_TARGET(i_target) .set_RANK_PAIR(i_rp), "No ranks configured in MCA %s, rank pair %d", mss::c_str(i_target), i_rp ); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C index c20cac543..d9a7fb8e4 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C @@ -2774,7 +2774,7 @@ fapi2::ReturnCode process_rdvref_cal_errors( const fapi2::Target<fapi2::TARGET_T // the errors and the disables there. FAPI_ASSERT_NOEXIT(v == 0, fapi2::MSS_FAILED_RDVREF_CAL() - .set_DIMM_TARGET(i_target) + .set_MCA_TARGET(i_target) .set_REGISTER(TT::RD_VREF_CAL_ERROR_REG[l_index]) .set_VALUE(v), "DP16 failed read vref calibration on %s. register 0x%016lx value 0x%016lx", @@ -2836,7 +2836,7 @@ fapi2::ReturnCode process_wrvref_cal_errors( const fapi2::Target<fapi2::TARGET_T // Now does bitwise anding to determine what's an actual error w/ the masking FAPI_ASSERT_NOEXIT(0 == (l_mask_compare & l_data_it->first), fapi2::MSS_FAILED_WRVREF_CAL() - .set_DIMM_TARGET(i_target) + .set_MCA_TARGET(i_target) .set_REGISTER(TT::WR_VREF_ERROR_REG[l_index].first) .set_VALUE(l_data_it->first) .set_MASK(l_mask_it->first), @@ -2849,7 +2849,7 @@ fapi2::ReturnCode process_wrvref_cal_errors( const fapi2::Target<fapi2::TARGET_T FAPI_ASSERT_NOEXIT(0 == (l_mask_compare & l_data_it->second), fapi2::MSS_FAILED_WRVREF_CAL() - .set_DIMM_TARGET(i_target) + .set_MCA_TARGET(i_target) .set_REGISTER(TT::WR_VREF_ERROR_REG[l_index].second) .set_VALUE(l_data_it->second) .set_MASK(l_mask_it->second), diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C index d97e6cc4b..8674997fd 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C @@ -154,18 +154,17 @@ fapi2::ReturnCode reset_config1(const fapi2::Target<TARGET_TYPE_MCA>& i_target) l_type_index = l_dimm_type[0] | l_dimm_type[1]; l_gen_index = l_dram_gen[0] | l_dram_gen[1]; - // These two checks should never be called, but better safe than seg fault - FAPI_ASSERT( l_type_index < NUM_DIMM_TYPES, - fapi2::MSS_INVALID_DIMM_TYPE() - .set_DIMM_TYPE(l_type_index) - .set_TARGET(i_target), - "Invalid DIMM configuration or DIMM type on %s", - mss::c_str(i_target)); - FAPI_ASSERT( l_gen_index < NUM_DIMM_GEN, - fapi2::MSS_PLUG_RULES_INVALID_DRAM_GEN() - .set_DRAM_GEN(l_gen_index) - .set_DIMM_TARGET(i_target), - "Invalid DIMM configuration or DRAM gen on %s", + // This check should never be called, but better safe than seg fault + FAPI_ASSERT( (l_type_index < NUM_DIMM_TYPES) && (l_gen_index < NUM_DIMM_GEN), + fapi2::MSS_PLUG_RULES_ERROR_IN_PHY() + .set_DIMM_TYPE_DIMM_0(l_dimm_type[0]) + .set_DIMM_TYPE_DIMM_1(l_dimm_type[1]) + .set_DRAM_GEN_DIMM_0(l_dram_gen[0]) + .set_DRAM_GEN_DIMM_1(l_dram_gen[1]) + .set_MCA_TARGET(i_target), + "Invalid DIMM configuration or DIMM type (%d) or DRAM_GEN (%d) on %s", + l_type_index, + l_gen_index, mss::c_str(i_target)); // FOR NIMBUS PHY (as the protocol choice above is) BRS diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.C b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.C index 5a08c49f0..c25cfb35a 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.C @@ -27,9 +27,9 @@ /// @brief Decode MSS_MRW_PWR_CURVE_SLOPE, PWR_CURVE_INTERCEPT, and THERMAL_POWER_LIMIT /// // *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB // fapi2 @@ -290,44 +290,45 @@ fapi2::ReturnCode get_power_attrs (const fapi2::Target<fapi2::TARGET_TYPE_MCS>& mss::dimm::kind l_kind (l_dimm); mss::power_thermal::decoder l_decoder(l_kind); - FAPI_TRY( l_decoder.generate_encoding() ); + FAPI_TRY( l_decoder.generate_encoding(), "%s Error in get_power_attrs", mss::c_str(i_mcs) ); // The first entry into these arrays must be valid // If we don't find any values, the attributes aren't found so go with some defaults if (i_slope.empty() || i_slope[0] == 0) { - FAPI_INF("ATTR_MSS_MRW_PWR_SLOPE not found!!"); + FAPI_INF("%s ATTR_MSS_MRW_PWR_SLOPE not found!!", mss::c_str(i_mcs)); o_vddr_slope [l_mca_pos][l_dimm_pos] = default_power::VDDR_SLOPE; o_total_slope [l_mca_pos][l_dimm_pos] = default_power::TOTAL_SLOPE; } else { - FAPI_TRY( l_decoder.find_slope(i_slope) ); + FAPI_TRY( l_decoder.find_slope(i_slope), "%s Error in get_power_attrs", mss::c_str(i_mcs) ); o_vddr_slope [l_mca_pos][l_dimm_pos] = l_decoder.iv_vddr_slope; o_total_slope [l_mca_pos][l_dimm_pos] = l_decoder.iv_total_slope; } if (i_intercept.empty() || i_intercept[0] == 0) { - FAPI_INF("ATTR_MSS_MRW_PWR_INTERCEPT not found!!"); + FAPI_INF("%s ATTR_MSS_MRW_PWR_INTERCEPT not found!!", mss::c_str(i_mcs)); o_total_int [l_mca_pos][l_dimm_pos] = default_power::TOTAL_INT; o_vddr_int [l_mca_pos][l_dimm_pos] = default_power::VDDR_INT; } else { - FAPI_TRY( l_decoder.find_intercept(i_intercept) ); + FAPI_TRY( l_decoder.find_intercept(i_intercept), "%s Error in get_power_attrs", mss::c_str(i_mcs) ); o_vddr_int [l_mca_pos][l_dimm_pos] = l_decoder.iv_vddr_intercept; o_total_int [l_mca_pos][l_dimm_pos] = l_decoder.iv_total_intercept; } if (i_thermal_power_limit.empty() || i_thermal_power_limit[0] == 0) { - FAPI_INF("ATTR_MSS_MRW_THERMAL_MEMORY_POWER_LIMIT not found!!"); + FAPI_INF("%s ATTR_MSS_MRW_THERMAL_MEMORY_POWER_LIMIT not found!!", mss::c_str(i_mcs)); o_thermal_power [l_mca_pos][l_dimm_pos] = default_power::THERMAL_LIMIT; } else { - FAPI_TRY( l_decoder.find_thermal_power_limit(i_thermal_power_limit) ); + FAPI_TRY( l_decoder.find_thermal_power_limit(i_thermal_power_limit), + "%s Error in get_power_attrs", mss::c_str(i_mcs) ); o_thermal_power [l_mca_pos][l_dimm_pos] = l_decoder.iv_thermal_power_limit; } } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.C b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.C index 3e7c51500..ee15073e5 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.C @@ -67,16 +67,19 @@ throttle::throttle( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_mca, fapi2::R //holder for watt_target to add up for port uint32_t l_dimm_power_limits [MAX_DIMM_PER_PORT] = {}; - FAPI_TRY( mrw_max_dram_databus_util(iv_databus_port_max) ); - FAPI_TRY( mrw_dimm_power_curve_percent_uplift(iv_power_uplift) ); - FAPI_TRY( mrw_dimm_power_curve_percent_uplift_idle(iv_power_uplift_idle) ); - FAPI_TRY( dimm_thermal_limit( iv_target, iv_dimm_thermal_limit) ); - FAPI_TRY( total_pwr_intercept( iv_target, iv_pwr_int)); - FAPI_TRY( total_pwr_slope( iv_target, iv_pwr_slope)); - FAPI_TRY( runtime_mem_throttled_n_commands_per_slot(iv_target, iv_runtime_n_slot ) ); - FAPI_TRY( runtime_mem_throttled_n_commands_per_port(iv_target, iv_runtime_n_port ) ); - FAPI_TRY( mem_watt_target( iv_target, l_dimm_power_limits) ); - FAPI_TRY( mrw_mem_m_dram_clocks(iv_m_clocks) ); + FAPI_TRY( mrw_max_dram_databus_util(iv_databus_port_max), "%s Error in throttle ctor", mss::c_str(i_mca) ); + FAPI_TRY( mrw_dimm_power_curve_percent_uplift(iv_power_uplift), "%s Error in throttle ctor", mss::c_str(i_mca) ); + FAPI_TRY( mrw_dimm_power_curve_percent_uplift_idle(iv_power_uplift_idle), "%s Error in throttle ctor", + mss::c_str(i_mca) ); + FAPI_TRY( dimm_thermal_limit( iv_target, iv_dimm_thermal_limit), "%s Error in throttle ctor", mss::c_str(i_mca) ); + FAPI_TRY( total_pwr_intercept( iv_target, iv_pwr_int), "%s Error in throttle ctor", mss::c_str(i_mca) ); + FAPI_TRY( total_pwr_slope( iv_target, iv_pwr_slope), "%s Error in throttle ctor", mss::c_str(i_mca) ); + FAPI_TRY( runtime_mem_throttled_n_commands_per_slot(iv_target, iv_runtime_n_slot ), "%s Error in throttle ctor", + mss::c_str(i_mca) ); + FAPI_TRY( runtime_mem_throttled_n_commands_per_port(iv_target, iv_runtime_n_port ), "%s Error in throttle ctor", + mss::c_str(i_mca) ); + FAPI_TRY( mem_watt_target( iv_target, l_dimm_power_limits), "%s Error in throttle ctor", mss::c_str(i_mca) ); + FAPI_TRY( mrw_mem_m_dram_clocks(iv_m_clocks), "%s Error in throttle ctor", mss::c_str(i_mca) ); //Port power limit = sum of dimm power limits for ( const auto& l_dimm : mss::find_targets<TARGET_TYPE_DIMM>(iv_target) ) diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.H b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.H index acb3df555..70156eb04 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.H @@ -28,7 +28,7 @@ /// // *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 3 // *HWP Consumed by: FSP:HB @@ -42,19 +42,30 @@ namespace mss { namespace power_thermal { +/// +/// @brief throttle constants used in the power_thermal functions +/// enum throttle_const : size_t { - // Dram data bus utilization is bus utilization / 4 + /// Dram data bus utilization is bus utilization / 4 DRAM_BUS_UTILS = 4, - //10000 to convert to and from c% + + /// 10000 to convert to and from c% UTIL_CONVERSION = 10000, + + /// Conversion to percentage PERCENT_CONVERSION = 100, - //MIN_UTIL and IDLE_UTIL are in c% + /// MIN_UTIL is in c% MIN_UTIL = 100, + + /// IDLE_UTIL is in c% IDLE_UTIL = 0, + + /// Minimum throttle allowed for the port and or slot. If we set to 0, we brick the port MIN_THROTTLE = 1, }; + /// /// @class throttle /// @brief Determine power_thermal throttles for memory diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C index f61ba52b0..fd032e167 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C @@ -27,9 +27,9 @@ /// @brief SPD factory and functions /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP // std lib @@ -122,7 +122,7 @@ fapi_try_exit: /// /// @brief Decodes SPD Revision additions level /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD data +/// @param[in] i_spd_data SPD data /// @param[out] o_value additions revision num /// @return FAPI2_RC_SUCCESS if okay /// @note Decodes SPD Byte 1 (bits 7~4). @@ -637,7 +637,7 @@ fapi2::ReturnCode raw_card_factory(const fapi2::Target<TARGET_TYPE_DIMM>& i_targ .set_DIMM_TYPE(l_dimm_type) .set_RAW_CARD_REV(l_ref_raw_card_rev) .set_DIMM_TARGET(i_target), - "Invalid reference raw card recieved for RDIMM: %d for %s", + "Invalid reference raw card received for RDIMM: %d for %s", l_ref_raw_card_rev, mss::c_str(i_target) ); break; @@ -649,17 +649,16 @@ fapi2::ReturnCode raw_card_factory(const fapi2::Target<TARGET_TYPE_DIMM>& i_targ .set_DIMM_TYPE(l_dimm_type) .set_RAW_CARD_REV(l_ref_raw_card_rev) .set_DIMM_TARGET(i_target), - "Invalid reference raw card recieved for LRDIMM: %d for %s", + "Invalid reference raw card received for LRDIMM: %d for %s", l_ref_raw_card_rev, mss::c_str(i_target)); break; default: - FAPI_ASSERT( false, fapi2::MSS_INVALID_DIMM_TYPE() .set_DIMM_TYPE(l_dimm_type) - .set_TARGET(i_target), + .set_DIMM_TARGET(i_target), "Recieved invalid dimm type: %d for %s", l_dimm_type, mss::c_str(i_target) ); break; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.C b/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.C index 1aa042f58..c55657845 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.C @@ -28,9 +28,9 @@ /// @brief Contains common functions that perform checks /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP FW Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -72,5 +72,5 @@ fapi_try_exit: return fapi2::current_err; }; -} -} +} // ns check +} // ns mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.H index a5cbd8012..0b9a46f3f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.H @@ -28,9 +28,9 @@ /// @brief Contains common functions that perform checks /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP FW Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _CHECKER_H_ @@ -93,78 +93,6 @@ fapi_try_exit: } /// -/// @brief Checks homogenous DDR4 dimm configuration (e.g. DDR4) -/// @param[in] i_target the controller target -/// @return fapi2::FAPI2_RC_SUCCESS iff ok -/// -inline fapi2::ReturnCode dram_type(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target) -{ - uint8_t l_dram_gen[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {0}; - - // Retrieve DDR4 dimm attributes - FAPI_TRY(eff_dram_gen(i_target, &(l_dram_gen[0][0]))); - - // Make sure all DRAMs are DDR4 or throw an error - for (const auto& l_mca : i_target.getChildren<fapi2::TARGET_TYPE_MCA>()) - { - const auto l_port_num = mss::index(l_mca); - - for (const auto& l_dimm : l_mca.getChildren<fapi2::TARGET_TYPE_DIMM>()) - { - const auto l_dimm_num = mss::index(l_dimm); - - FAPI_INF("%s DRAM device type is %llX", - mss::c_str(l_dimm), - l_dram_gen[l_port_num][l_dimm_num]); - - // Nimbus supports only DDR4 - FAPI_ASSERT(l_dram_gen[l_port_num][l_dimm_num] == fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, - fapi2::MSS_UNSUPPORTED_DEV_TYPE(). - set_DEV_TYPE(l_dram_gen[l_port_num][l_dimm_num]), - "%s Incorrect DRAM device generation, DRAM generation is %llx", - mss::c_str(l_dimm), - l_dram_gen[l_port_num][l_dimm_num]); - }// dimm - }// mca - -fapi_try_exit: - return fapi2::current_err; - -}// dram_type - -/// -/// @brief Checks conditional and implements traces & exits if it fails -/// @param[in] i_target the dimm target -/// @param[in] i_conditional conditional that we are testing against -/// @param[in] i_key map key -/// @param[in] i_data additional returned data -/// @param[in] i_err_str error string to print out when conditional fails -/// @return ReturnCode -/// -inline fapi2::ReturnCode fail_for_invalid_map(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const bool i_conditional, - const uint64_t i_key, - const uint64_t i_data = 0, - const char* i_err_str = "") -{ - // Invalid keys won't return useful or valid data so we allow optional data - FAPI_ASSERT(i_conditional, - fapi2::MSS_INVALID_KEY(). - set_KEY(i_key). - set_DATA(i_data). - set_DIMM_TARGET(i_target), - "%s. %s Could not find value from key %d. Returned data: %d.", - c_str(i_target), - i_err_str, - i_key, - i_data); - - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -} - -/// /// @brief Checks to make sure ATTR_MSS_MRW_TEMP_REFRESH_MODE and ATTR_MSS_MRW_FINE_REFRESH_MODE are set correctly /// @return fapi2::FAPI2_RC_SUCCESS if okay /// @note from DDR4 DRAM Spec (79-4B) 4.9.4 page 48 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.C b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.C index ad8baffff..41bc0b0c6 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.C @@ -27,10 +27,10 @@ /// @file fake_spd.H /// @brief A tool to return fake (fixed) DIMM SPD for testing, development /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> -// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP // This shouldn't be callable by HB diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.H index 151e0f5b4..1084494b7 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.H @@ -27,10 +27,10 @@ /// @file fake_spd.H /// @brief A tool to return fake (fixed) DIMM SPD for testing, development /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> -// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP // This shouldn't be callable by HB @@ -43,6 +43,9 @@ #include <fapi2.H> #include <cstdint> +/// +/// @brief SPD_TYPE class for our "fake" SPD for testing purposes +/// enum class spd_type { VBU_16GB_2RX4_2400_DDR4_RDIMM, |
