2 files changed, 26 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C
index 06131bd61..6f0ba4e72 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C
@@ -48,6 +48,7 @@
 #include <lib/dimm/ddr4/latch_wr_vref.H>
 #include <lib/workarounds/seq_workarounds.H>
 #include <lib/workarounds/dqs_align_workarounds.H>
+#include <lib/workarounds/ccs_workarounds.H>
 
 #include <generic/memory/lib/utils/scom.H>
 #include <lib/utils/count_dimm.H>
@@ -201,6 +202,13 @@ fapi2::ReturnCode wr_lvl::pre_workaround( const fapi2::Target<fapi2::TARGET_TYPE
         l_program.iv_instructions.clear();
     }
 
+    FAPI_INF("%s RP%lu %s WR_LVL workaround setup", mss::c_str(i_target), i_rp, iv_sim ? "skipping" : "running");
+
+    if(!iv_sim)
+    {
+        FAPI_TRY( mss::ccs::workarounds::wr_lvl::configure_non_calibrating_ranks(i_target, i_rp, mss::states::OFF_N) );
+    }
+
 fapi_try_exit:
     return fapi2::current_err;
 }
@@ -256,6 +264,13 @@ fapi2::ReturnCode wr_lvl::post_workaround( const fapi2::Target<fapi2::TARGET_TYP
         FAPI_TRY( mss::ccs::execute(l_mcbist, l_program, i_target) );
     }
 
+    FAPI_INF("%s RP%lu %s WR_LVL workaround cleanup", mss::c_str(i_target), i_rp, iv_sim ? "skipping" : "running");
+
+    if(!iv_sim)
+    {
+        FAPI_TRY( mss::ccs::workarounds::wr_lvl::configure_non_calibrating_ranks(i_target, i_rp, mss::states::ON_N) );
+    }
+
 fapi_try_exit:
     return fapi2::current_err;
 }
@@ -893,7 +908,7 @@ std::vector<std::shared_ptr<step>> steps_factory(const fapi2::buffer<uint32_t>&
     if(i_cal_steps.getBit<mss::cal_steps::WR_LEVEL>())
     {
         FAPI_INF("Write leveling is enabled");
-        l_steps.push_back(std::make_shared<wr_lvl>());
+        l_steps.push_back(std::make_shared<wr_lvl>(i_sim));
     }
 
     // INITIAL_PAT_WR
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.H
index 69372ef85..3ae5e3365 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.H
@@ -301,11 +301,16 @@ class wr_lvl : public phy_step
     public:
         ///
         /// @brief Base constructor
+        /// @param[in] i_sim - true if in simulation mode
         ///
-        wr_lvl() :
-            phy_step( fapi2::buffer<uint64_t>().setBit<MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_WR_LEVEL>(), "WR_LVL")
+        wr_lvl(const bool i_sim) :
+            phy_step( fapi2::buffer<uint64_t>().setBit<MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_WR_LEVEL>(), "WR_LVL"),
+            iv_sim(i_sim)
         {}
 
+        // Delete the default constructor
+        wr_lvl() = delete;
+
         ///
         /// @brief Default destructor
         ///
@@ -339,6 +344,9 @@ class wr_lvl : public phy_step
         /// @return l_cycles - the number of cycles a given calibration step wil take
         ///
         uint64_t calculate_cycles( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ) const;
+
+    private:
+        bool iv_sim;
 };
 
 ///