diff options
Diffstat (limited to 'src/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H')
| -rw-r--r-- | src/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H | 8711 |
1 files changed, 8143 insertions, 568 deletions
diff --git a/src/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H index 0399cfd29..f8bc0478a 100644 --- a/src/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H +++ b/src/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H @@ -41,6 +41,264 @@ #include <p9_scom_template_consts.H> #include <p9_misc_scom_addresses_fld_fixes.H> +REG64_FLD( PHB_ACT0_REG_AIB_COMMAND_INVALID , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_COMMAND_INVALID ); +REG64_FLD( PHB_ACT0_REG_AIB_ADDRESSING_ERROR , 1 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_ADDRESSING_ERROR ); +REG64_FLD( PHB_ACT0_REG_AIB_ACCESS_ERROR , 2 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_ACCESS_ERROR ); +REG64_FLD( PHB_ACT0_REG_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED , 3 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED ); +REG64_FLD( PHB_ACT0_REG_AIB_FATAL_CLASS_ERROR , 4 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_FATAL_CLASS_ERROR ); +REG64_FLD( PHB_ACT0_REG_AIB_INF_CLASS_ERROR , 5 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_INF_CLASS_ERROR ); +REG64_FLD( PHB_ACT0_REG_PE_STOP_STATE_ERROR , 6 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PE_STOP_STATE_ERROR ); +REG64_FLD( PHB_ACT0_REG_AIB_DAT_ERR_SIGNALED , 7 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_DAT_ERR_SIGNALED ); +REG64_FLD( PHB_ACT0_REG_OUT_COMMON_ARRAY_FATAL_ERROR , 8 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_OUT_COMMON_ARRAY_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_OUT_COMMON_LATCH_FATAL_ERROR , 9 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_OUT_COMMON_LATCH_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_OUT_COMMON_LOGIC_FATAL_ERROR , 10 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_OUT_COMMON_LOGIC_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_BLIF_OUT_INTERFACE_PARITY_ERROR , 11 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_BLIF_OUT_INTERFACE_PARITY_ERROR ); +REG64_FLD( PHB_ACT0_REG_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE , 12 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE ); +REG64_FLD( PHB_ACT0_REG_MMIO_REQUEST_TIMEOUT , 13 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MMIO_REQUEST_TIMEOUT ); +REG64_FLD( PHB_ACT0_REG_OUT_RRB_SOURCED_ERROR , 14 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_OUT_RRB_SOURCED_ERROR ); +REG64_FLD( PHB_ACT0_REG_CFG_LOGIC_SIGNALED_ERROR , 15 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_CFG_LOGIC_SIGNALED_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_REG_REQUEST_ADDRESS_ERROR , 16 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_REG_REQUEST_ADDRESS_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_FDA_FATAL_ERROR , 17 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_FDA_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_FDA_INF_ERROR , 18 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_FDA_INF_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_FDB_FATAL_ERROR , 19 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_FDB_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_FDB_INF_ERROR , 20 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_FDB_INF_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_ERR_FATAL_ERROR , 21 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_ERR_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_ERR_INF_ERROR , 22 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_ERR_INF_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_DBG_FATAL_ERROR , 23 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_DBG_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_DBG_INF_ERROR , 24 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_DBG_INF_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_PCIE_REQUEST_ACCESS_ERROR , 25 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_PCIE_REQUEST_ACCESS_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_BUS_LOGIC_ERROR , 26 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_BUS_LOGIC_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_UVI_FATAL_ERROR , 27 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_UVI_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_UVI_INF_ERROR , 28 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_UVI_INF_ERROR ); +REG64_FLD( PHB_ACT0_REG_SCOM_FATAL_ERROR , 29 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_SCOM_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_SCOM_INF_ERROR , 30 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_SCOM_INF_ERROR ); +REG64_FLD( PHB_ACT0_REG_PCIE_MACRO_ERROR_ACTIVE_STATUS , 31 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PCIE_MACRO_ERROR_ACTIVE_STATUS ); +REG64_FLD( PHB_ACT0_REG_ARB_IODA_FATAL_ERROR , 32 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_IODA_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_ARB_MSI_PE_MATCH_ERROR , 33 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_MSI_PE_MATCH_ERROR ); +REG64_FLD( PHB_ACT0_REG_ARB_MSI_ADDRESS_ERROR , 34 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_MSI_ADDRESS_ERROR ); +REG64_FLD( PHB_ACT0_REG_ARB_TVT_ERROR , 35 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_TVT_ERROR ); +REG64_FLD( PHB_ACT0_REG_ARB_RCVD_FATAL_ERROR_MSG , 36 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_RCVD_FATAL_ERROR_MSG ); +REG64_FLD( PHB_ACT0_REG_ARB_RCVD_NONFATAL_ERROR_MSG , 37 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_RCVD_NONFATAL_ERROR_MSG ); +REG64_FLD( PHB_ACT0_REG_ARB_RCVD_CORRECTIBLE_ERROR_MSG , 38 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_RCVD_CORRECTIBLE_ERROR_MSG ); +REG64_FLD( PHB_ACT0_REG_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED , 39 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED ); +REG64_FLD( PHB_ACT0_REG_ARB_COMMON_FATAL_ERROR , 40 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_COMMON_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_ARB_TABLE_BAR_DISABLED_ERROR , 41 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_TABLE_BAR_DISABLED_ERROR ); +REG64_FLD( PHB_ACT0_REG_ARB_BLIF_COMPLETION_ERROR , 42 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_BLIF_COMPLETION_ERROR ); +REG64_FLD( PHB_ACT0_REG_ARB_PCT_TIMEOUT_ERROR , 43 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_PCT_TIMEOUT_ERROR ); +REG64_FLD( PHB_ACT0_REG_ARB_ECC_CORRECTABLE_ERROR , 44 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_ACT0_REG_ARB_ECC_UNCORRECTABLE_ERROR , 45 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_ACT0_REG_ARB_TLP_POISON_SIGNALED , 46 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_TLP_POISON_SIGNALED ); +REG64_FLD( PHB_ACT0_REG_ARB_RTT_PENUM_INVALID_ERROR , 47 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_RTT_PENUM_INVALID_ERROR ); +REG64_FLD( PHB_ACT0_REG_MRG_COMMON_FATAL_ERROR , 48 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_COMMON_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_MRG_TABLE_BAR_DISABLED_ERROR , 49 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_TABLE_BAR_DISABLED_ERROR ); +REG64_FLD( PHB_ACT0_REG_MRG_ECC_CORRECTABLE_ERROR , 50 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_ACT0_REG_MRG_ECC_UNCORRECTABLE_ERROR , 51 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_ACT0_REG_MRG_AIB2_TX_TIMEOUT_ERROR , 52 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_AIB2_TX_TIMEOUT_ERROR ); +REG64_FLD( PHB_ACT0_REG_MRG_MRT_ERROR , 53 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_MRT_ERROR ); +REG64_FLD( PHB_ACT0_REG_MRG_RESERVED01 , 54 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_RESERVED01 ); +REG64_FLD( PHB_ACT0_REG_MRG_RESERVED02 , 55 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_RESERVED02 ); +REG64_FLD( PHB_ACT0_REG_TCE_IODA_PAGE_ACCESS_ERROR , 56 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_IODA_PAGE_ACCESS_ERROR ); +REG64_FLD( PHB_ACT0_REG_TCE_REQUEST_TIMEOUT_ERROR , 57 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_REQUEST_TIMEOUT_ERROR ); +REG64_FLD( PHB_ACT0_REG_TCE_UNEXPECTED_RESPONSE_ERROR , 58 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_UNEXPECTED_RESPONSE_ERROR ); +REG64_FLD( PHB_ACT0_REG_TCE_COMMON_FATAL_ERRORS , 59 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_COMMON_FATAL_ERRORS ); +REG64_FLD( PHB_ACT0_REG_TCE_ECC_CORRECTABLE_ERROR , 60 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_ACT0_REG_TCE_ECC_UNCORRECTABLE_ERROR , 61 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_ACT0_REG_TCE_RESERVED01 , 62 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_RESERVED01 ); +REG64_FLD( PHB_ACT0_REG_LEM_FIR_INTERNAL_PARITY_ERROR , 63 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_LEM_FIR_INTERNAL_PARITY_ERROR ); + +REG64_FLD( PHB_ACTION1_REG_AIB_COMMAND_INVALID , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_COMMAND_INVALID ); +REG64_FLD( PHB_ACTION1_REG_AIB_ADDRESSING_ERROR , 1 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_ADDRESSING_ERROR ); +REG64_FLD( PHB_ACTION1_REG_AIB_ACCESS_ERROR , 2 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_ACCESS_ERROR ); +REG64_FLD( PHB_ACTION1_REG_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED , 3 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED ); +REG64_FLD( PHB_ACTION1_REG_AIB_FATAL_CLASS_ERROR , 4 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_FATAL_CLASS_ERROR ); +REG64_FLD( PHB_ACTION1_REG_AIB_INF_CLASS_ERROR , 5 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_INF_CLASS_ERROR ); +REG64_FLD( PHB_ACTION1_REG_PE_STOP_STATE_ERROR , 6 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PE_STOP_STATE_ERROR ); +REG64_FLD( PHB_ACTION1_REG_AIB_DAT_ERR_SIGNALED , 7 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_DAT_ERR_SIGNALED ); +REG64_FLD( PHB_ACTION1_REG_OUT_COMMON_ARRAY_FATAL_ERROR , 8 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_OUT_COMMON_ARRAY_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_OUT_COMMON_LATCH_FATAL_ERROR , 9 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_OUT_COMMON_LATCH_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_OUT_COMMON_LOGIC_FATAL_ERROR , 10 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_OUT_COMMON_LOGIC_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_BLIF_OUT_INTERFACE_PARITY_ERROR , 11 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_BLIF_OUT_INTERFACE_PARITY_ERROR ); +REG64_FLD( PHB_ACTION1_REG_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE , 12 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE ); +REG64_FLD( PHB_ACTION1_REG_MMIO_REQUEST_TIMEOUT , 13 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MMIO_REQUEST_TIMEOUT ); +REG64_FLD( PHB_ACTION1_REG_OUT_RRB_SOURCED_ERROR , 14 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_OUT_RRB_SOURCED_ERROR ); +REG64_FLD( PHB_ACTION1_REG_CFG_LOGIC_SIGNALED_ERROR , 15 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_CFG_LOGIC_SIGNALED_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_REG_REQUEST_ADDRESS_ERROR , 16 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_REG_REQUEST_ADDRESS_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_FDA_FATAL_ERROR , 17 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_FDA_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_FDA_INF_ERROR , 18 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_FDA_INF_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_FDB_FATAL_ERROR , 19 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_FDB_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_FDB_INF_ERROR , 20 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_FDB_INF_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_ERR_FATAL_ERROR , 21 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_ERR_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_ERR_INF_ERROR , 22 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_ERR_INF_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_DBG_FATAL_ERROR , 23 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_DBG_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_DBG_INF_ERROR , 24 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_DBG_INF_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_PCIE_REQUEST_ACCESS_ERROR , 25 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_PCIE_REQUEST_ACCESS_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_BUS_LOGIC_ERROR , 26 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_BUS_LOGIC_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_UVI_FATAL_ERROR , 27 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_UVI_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_UVI_INF_ERROR , 28 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_UVI_INF_ERROR ); +REG64_FLD( PHB_ACTION1_REG_SCOM_FATAL_ERROR , 29 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_SCOM_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_SCOM_INF_ERROR , 30 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_SCOM_INF_ERROR ); +REG64_FLD( PHB_ACTION1_REG_PCIE_MACRO_ERROR_ACTIVE_STATUS , 31 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PCIE_MACRO_ERROR_ACTIVE_STATUS ); +REG64_FLD( PHB_ACTION1_REG_ARB_IODA_FATAL_ERROR , 32 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_IODA_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_ARB_MSI_PE_MATCH_ERROR , 33 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_MSI_PE_MATCH_ERROR ); +REG64_FLD( PHB_ACTION1_REG_ARB_MSI_ADDRESS_ERROR , 34 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_MSI_ADDRESS_ERROR ); +REG64_FLD( PHB_ACTION1_REG_ARB_TVT_ERROR , 35 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_TVT_ERROR ); +REG64_FLD( PHB_ACTION1_REG_ARB_RCVD_FATAL_ERROR_MSG , 36 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_RCVD_FATAL_ERROR_MSG ); +REG64_FLD( PHB_ACTION1_REG_ARB_RCVD_NONFATAL_ERROR_MSG , 37 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_RCVD_NONFATAL_ERROR_MSG ); +REG64_FLD( PHB_ACTION1_REG_ARB_RCVD_CORRECTIBLE_ERROR_MSG , 38 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_RCVD_CORRECTIBLE_ERROR_MSG ); +REG64_FLD( PHB_ACTION1_REG_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED , 39 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED ); +REG64_FLD( PHB_ACTION1_REG_ARB_COMMON_FATAL_ERROR , 40 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_COMMON_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_ARB_TABLE_BAR_DISABLED_ERROR , 41 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_TABLE_BAR_DISABLED_ERROR ); +REG64_FLD( PHB_ACTION1_REG_ARB_BLIF_COMPLETION_ERROR , 42 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_BLIF_COMPLETION_ERROR ); +REG64_FLD( PHB_ACTION1_REG_ARB_PCT_TIMEOUT_ERROR , 43 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_PCT_TIMEOUT_ERROR ); +REG64_FLD( PHB_ACTION1_REG_ARB_ECC_CORRECTABLE_ERROR , 44 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_ACTION1_REG_ARB_ECC_UNCORRECTABLE_ERROR , 45 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_ACTION1_REG_ARB_TLP_POISON_SIGNALED , 46 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_TLP_POISON_SIGNALED ); +REG64_FLD( PHB_ACTION1_REG_ARB_RTT_PENUM_INVALID_ERROR , 47 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_RTT_PENUM_INVALID_ERROR ); +REG64_FLD( PHB_ACTION1_REG_MRG_COMMON_FATAL_ERROR , 48 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_COMMON_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_MRG_TABLE_BAR_DISABLED_ERROR , 49 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_TABLE_BAR_DISABLED_ERROR ); +REG64_FLD( PHB_ACTION1_REG_MRG_ECC_CORRECTABLE_ERROR , 50 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_ACTION1_REG_MRG_ECC_UNCORRECTABLE_ERROR , 51 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_ACTION1_REG_MRG_AIB2_TX_TIMEOUT_ERROR , 52 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_AIB2_TX_TIMEOUT_ERROR ); +REG64_FLD( PHB_ACTION1_REG_MRG_MRT_ERROR , 53 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_MRT_ERROR ); +REG64_FLD( PHB_ACTION1_REG_MRG_RESERVED01 , 54 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_RESERVED01 ); +REG64_FLD( PHB_ACTION1_REG_MRG_RESERVED02 , 55 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_RESERVED02 ); +REG64_FLD( PHB_ACTION1_REG_TCE_IODA_PAGE_ACCESS_ERROR , 56 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_IODA_PAGE_ACCESS_ERROR ); +REG64_FLD( PHB_ACTION1_REG_TCE_REQUEST_TIMEOUT_ERROR , 57 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_REQUEST_TIMEOUT_ERROR ); +REG64_FLD( PHB_ACTION1_REG_TCE_UNEXPECTED_RESPONSE_ERROR , 58 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_UNEXPECTED_RESPONSE_ERROR ); +REG64_FLD( PHB_ACTION1_REG_TCE_COMMON_FATAL_ERRORS , 59 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_COMMON_FATAL_ERRORS ); +REG64_FLD( PHB_ACTION1_REG_TCE_ECC_CORRECTABLE_ERROR , 60 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_ACTION1_REG_TCE_ECC_UNCORRECTABLE_ERROR , 61 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_ACTION1_REG_TCE_RESERVED01 , 62 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_RESERVED01 ); +REG64_FLD( PHB_ACTION1_REG_LEM_FIR_INTERNAL_PARITY_ERROR , 63 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_LEM_FIR_INTERNAL_PARITY_ERROR ); + REG64_FLD( PU_ADDR_0_HASH_FUNCTION_REG_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS ); REG64_FLD( PU_ADDR_0_HASH_FUNCTION_REG_ADDRESS_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , @@ -259,6 +517,8 @@ REG64_FLD( PU_ALTD_CMD_REG_FBC_AXTYPE , 6 , SH_UN SH_FLD_FBC_AXTYPE ); REG64_FLD( PU_ALTD_CMD_REG_FBC_DATA_ONLY , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_DATA_ONLY ); +REG64_FLD( PU_ALTD_CMD_REG_FBC_LOCK_PICK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_LOCK_PICK ); REG64_FLD( PU_ALTD_CMD_REG_FBC_LOCKED , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_LOCKED ); REG64_FLD( PU_ALTD_CMD_REG_FBC_LOCK_ID , 12 , SH_UNT , SH_ACS_SCOM , @@ -295,10 +555,10 @@ REG64_FLD( PU_ALTD_DATA_REG_FBC , 0 , SH_UN REG64_FLD( PU_ALTD_DATA_REG_FBC_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FBC_LEN ); -REG64_FLD( PU_ALTD_OPTION_REG_FBC_WITH_PRE_QUIESCE , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_FBC_WITH_PRE_QUIESCE ); -REG64_FLD( PU_ALTD_OPTION_REG_FBC_WITH_PBINIT_LOW_WAIT , 23 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_ALTD_OPTION_REG_FBC_WITH_PBINIT_LOW_WAIT , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_WITH_PBINIT_LOW_WAIT ); +REG64_FLD( PU_ALTD_OPTION_REG_FBC_WITH_PRE_QUIESCE , 23 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_WITH_PRE_QUIESCE ); REG64_FLD( PU_ALTD_OPTION_REG_FBC_AFTER_QUIESCE_WAIT_COUNT , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_AFTER_QUIESCE_WAIT_COUNT ); REG64_FLD( PU_ALTD_OPTION_REG_FBC_AFTER_QUIESCE_WAIT_COUNT_LEN , 20 , SH_UNT , SH_ACS_SCOM , @@ -310,6 +570,8 @@ REG64_FLD( PU_ALTD_OPTION_REG_FBC_BEFORE_INIT_WAIT_COUNT , 54 , SH_UN REG64_FLD( PU_ALTD_OPTION_REG_FBC_BEFORE_INIT_WAIT_COUNT_LEN , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_BEFORE_INIT_WAIT_COUNT_LEN ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_ALTD_BUSY , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_ALTD_BUSY ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_WAIT_CMD_ARBIT , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_WAIT_CMD_ARBIT ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_ADDR_DONE , 2 , SH_UNT , SH_ACS_SCOM , @@ -355,6 +617,8 @@ REG64_FLD( PU_ALTD_STATUS_REG_FBC_CRESP_VALUE , 59 , SH_UN REG64_FLD( PU_ALTD_STATUS_REG_FBC_CRESP_VALUE_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_CRESP_VALUE_LEN ); +REG64_FLD( CAPP_APCFG_SPARE1 , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SPARE1 ); REG64_FLD( CAPP_APCFG_APCCTL_PHB_SEL , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_PHB_SEL ); REG64_FLD( CAPP_APCFG_APCCTL_PHB_SEL_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , @@ -367,6 +631,8 @@ REG64_FLD( CAPP_APCFG_SPEC_HPC_DIR_STATE , 8 , SH_UN SH_FLD_SPEC_HPC_DIR_STATE ); REG64_FLD( CAPP_APCFG_SPEC_HPC_DIR_STATE_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SPEC_HPC_DIR_STATE_LEN ); +REG64_FLD( CAPP_APCFG_SPARE , 13 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SPARE ); REG64_FLD( CAPP_APCFG_APCCTL_P9_MODE , 14 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_P9_MODE ); REG64_FLD( CAPP_APCFG_APCCTL_SYSADDR , 15 , SH_UNT_CAPP , SH_ACS_SCOM , @@ -414,6 +680,10 @@ REG64_FLD( CAPP_APCTL_APCCTL_HANG_DEAD , 8 , SH_UN SH_FLD_APCCTL_HANG_DEAD ); REG64_FLD( CAPP_APCTL_APCCTL_CFG_BKILL_INC , 9 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_CFG_BKILL_INC ); +REG64_FLD( CAPP_APCTL_DCACHE_MODE , 10 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DCACHE_MODE ); +REG64_FLD( CAPP_APCTL_DCACHE_REPORTS_PHYSICAL , 11 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DCACHE_REPORTS_PHYSICAL ); REG64_FLD( CAPP_APCTL_APCCTL_DISABLE_PSL_CMDQUEUE , 12 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_DISABLE_PSL_CMDQUEUE ); REG64_FLD( CAPP_APCTL_APCCTL_ENABLE_MASTER_RETRY_BACKOFF , 13 , SH_UNT_CAPP , SH_ACS_SCOM , @@ -424,6 +694,8 @@ REG64_FLD( CAPP_APCTL_SCPTGT_LFSR_MODE_LEN , 3 , SH_UN SH_FLD_SCPTGT_LFSR_MODE_LEN ); REG64_FLD( CAPP_APCTL_APCCTL_ENABLE_RD_VG_SCOPE_PREDICT , 17 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_ENABLE_RD_VG_SCOPE_PREDICT ); +REG64_FLD( CAPP_APCTL_SPARE , 18 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SPARE ); REG64_FLD( CAPP_APCTL_WR_EPSILON_VALUE , 39 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_WR_EPSILON_VALUE ); REG64_FLD( CAPP_APCTL_WR_EPSILON_VALUE_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , @@ -433,6 +705,8 @@ REG64_FLD( CAPP_APCTL_APCCTL_MAX_RETRY , 56 , SH_UN REG64_FLD( CAPP_APCTL_APCCTL_MAX_RETRY_LEN , 8 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_MAX_RETRY_LEN ); +REG64_FLD( CAPP_APC_ARRY_ADDR_ENCD_ARRAY_SELECT , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_ENCD_ARRAY_SELECT ); REG64_FLD( CAPP_APC_ARRY_ADDR_APCARY_ADDRESS , 3 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCARY_ADDRESS ); REG64_FLD( CAPP_APC_ARRY_ADDR_APCARY_ADDRESS_LEN , 9 , SH_UNT_CAPP , SH_ACS_SCOM , @@ -554,6 +828,13 @@ REG64_FLD( CAPP_ASE_TUPLE3_TID_LEN , 16 , SH_UN REG64_FLD( CAPP_ASE_TUPLE3_VALID , 63 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_VALID ); +REG64_FLD( PEC_ASSIST_INTERRUPT_REG_ATTN , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ATTN ); +REG64_FLD( PEC_ASSIST_INTERRUPT_REG_RECOV , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RECOV ); +REG64_FLD( PEC_ASSIST_INTERRUPT_REG_XSTOP , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_XSTOP ); + REG64_FLD( PU_N3_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_MASK ); REG64_FLD( PU_N3_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , @@ -721,6 +1002,9 @@ REG64_FLD( PU_NPU_SM1_ATS_TCR_TCE_TIMEOUT , 10 , SH_UN REG64_FLD( PU_NPU_SM1_ATS_TCR_TCE_TIMEOUT_LEN , 6 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_TCE_TIMEOUT_LEN ); +REG64_FLD( PEC_ATTN_INTERRUPT_REG_ATTN , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ATTN ); + REG64_FLD( PU_BANK0_MCD_BOT_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_BANK0_MCD_BOT_CPG , 1 , SH_UNT , SH_ACS_SCOM_RW , @@ -20953,6 +21237,10 @@ REG64_FLD( PU_CME4_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME4_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME4_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME4_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME4_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME4_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , @@ -20963,6 +21251,8 @@ REG64_FLD( PU_CME4_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME4_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME4_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME3_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -20988,6 +21278,10 @@ REG64_FLD( PU_CME3_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME3_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME3_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME3_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME3_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME3_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , @@ -20998,6 +21292,8 @@ REG64_FLD( PU_CME3_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME3_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME3_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME11_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21023,6 +21319,10 @@ REG64_FLD( PU_CME11_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME11_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME11_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME11_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME11_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME11_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , @@ -21033,6 +21333,8 @@ REG64_FLD( PU_CME11_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME11_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME11_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME2_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21058,6 +21360,10 @@ REG64_FLD( PU_CME2_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME2_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME2_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME2_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME2_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME2_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , @@ -21068,6 +21374,8 @@ REG64_FLD( PU_CME2_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME2_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME2_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME5_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21093,6 +21401,10 @@ REG64_FLD( PU_CME5_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME5_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME5_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME5_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME5_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME5_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , @@ -21103,6 +21415,8 @@ REG64_FLD( PU_CME5_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME5_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME5_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME9_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21128,6 +21442,10 @@ REG64_FLD( PU_CME9_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME9_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME9_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME9_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME9_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME9_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , @@ -21138,6 +21456,8 @@ REG64_FLD( PU_CME9_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME9_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME9_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME6_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21163,6 +21483,10 @@ REG64_FLD( PU_CME6_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME6_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME6_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME6_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME6_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME6_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , @@ -21173,6 +21497,8 @@ REG64_FLD( PU_CME6_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME6_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME6_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME10_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21198,6 +21524,10 @@ REG64_FLD( PU_CME10_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME10_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME10_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME10_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME10_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME10_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , @@ -21208,6 +21538,8 @@ REG64_FLD( PU_CME10_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME10_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME10_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME8_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21233,6 +21565,10 @@ REG64_FLD( PU_CME8_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME8_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME8_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME8_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME8_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME8_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , @@ -21243,6 +21579,8 @@ REG64_FLD( PU_CME8_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME8_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME8_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME1_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21268,6 +21606,10 @@ REG64_FLD( PU_CME1_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME1_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME1_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME1_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME1_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME1_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , @@ -21278,6 +21620,8 @@ REG64_FLD( PU_CME1_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME1_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME1_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME0_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21303,6 +21647,10 @@ REG64_FLD( PU_CME0_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME0_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME0_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME0_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME0_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME0_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , @@ -21313,6 +21661,8 @@ REG64_FLD( PU_CME0_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME0_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME0_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME7_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21338,6 +21688,10 @@ REG64_FLD( PU_CME7_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME7_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME7_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME7_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME7_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME7_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , @@ -21348,6 +21702,8 @@ REG64_FLD( PU_CME7_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME7_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME7_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME4_CME_LCL_EIMR_INTERRUPT_MASK , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK ); @@ -22597,6 +22953,66 @@ REG64_FLD( PU_CME7_CME_LCL_EISR_RESERVED_42_43 , 42 , SH_UN REG64_FLD( PU_CME7_CME_LCL_EISR_RESERVED_42_43_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43_LEN ); +REG64_FLD( PU_CME4_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME4_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( PU_CME3_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME3_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( PU_CME11_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME11_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( PU_CME2_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME2_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( PU_CME5_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME5_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( PU_CME9_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME9_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( PU_CME6_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME6_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( PU_CME10_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME10_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( PU_CME8_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME8_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( PU_CME1_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME1_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( PU_CME0_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME0_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( PU_CME7_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME7_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + REG64_FLD( PU_CME4_CME_LCL_EITR_INTERRUPT_TYPE , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE ); REG64_FLD( PU_CME4_CME_LCL_EITR_INTERRUPT_TYPE_LEN , 44 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , @@ -22933,186 +23349,6 @@ REG64_FLD( PU_CME7_CME_LCL_ICSR_COMM_SEND , 0 , SH_UN REG64_FLD( PU_CME7_CME_LCL_ICSR_COMM_SEND_LEN , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_COMM_SEND_LEN ); -REG64_FLD( PU_CME4_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME4_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME4_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME4_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME4_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME4_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME4_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - -REG64_FLD( PU_CME3_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME3_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME3_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME3_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME3_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME3_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME3_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - -REG64_FLD( PU_CME11_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME11_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME11_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME11_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME11_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME11_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME11_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - -REG64_FLD( PU_CME2_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME2_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME2_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME2_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME2_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME2_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME2_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - -REG64_FLD( PU_CME5_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME5_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME5_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME5_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME5_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME5_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME5_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - -REG64_FLD( PU_CME9_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME9_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME9_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME9_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME9_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME9_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME9_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - -REG64_FLD( PU_CME6_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME6_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME6_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME6_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME6_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME6_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME6_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - -REG64_FLD( PU_CME10_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME10_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME10_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME10_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME10_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME10_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME10_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - -REG64_FLD( PU_CME8_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME8_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME8_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME8_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME8_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME8_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME8_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - -REG64_FLD( PU_CME1_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME1_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME1_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME1_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME1_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME1_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME1_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - -REG64_FLD( PU_CME0_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME0_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME0_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME0_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME0_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME0_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME0_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - -REG64_FLD( PU_CME7_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME7_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME7_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME7_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME7_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME7_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME7_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE , @@ -25897,6 +26133,738 @@ REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UN REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( PU_CME3_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( PU_CME11_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( PU_CME2_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( PU_CME5_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( PU_CME9_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( PU_CME6_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( PU_CME10_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( PU_CME8_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( PU_CME1_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( PU_CME0_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( PU_CME7_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + REG64_FLD( PU_CME4_CME_SCOM_PMCRS0_DATA , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME4_CME_SCOM_PMCRS0_DATA_LEN , 64 , SH_UNT_PU_CME4 , SH_ACS_PPE , @@ -29989,8 +30957,8 @@ REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME4_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME4_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME4_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , @@ -30050,8 +31018,8 @@ REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME3_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME3_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME3_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , @@ -30111,8 +31079,8 @@ REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME11_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME11_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME11_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , @@ -30172,8 +31140,8 @@ REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME2_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME2_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME2_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , @@ -30233,8 +31201,8 @@ REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME5_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME5_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME5_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , @@ -30294,8 +31262,8 @@ REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME9_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME9_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME9_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , @@ -30355,8 +31323,8 @@ REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME6_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME6_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME6_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , @@ -30416,8 +31384,8 @@ REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME10_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME10_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME10_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , @@ -30477,8 +31445,8 @@ REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME8_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME8_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME8_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , @@ -30538,8 +31506,8 @@ REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME1_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME1_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME1_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , @@ -30599,8 +31567,8 @@ REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME0_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME0_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME0_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , @@ -30660,8 +31628,8 @@ REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME7_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME7_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME7_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , @@ -32281,6 +33249,246 @@ REG64_FLD( PU_CME7_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UN REG64_FLD( PU_CME7_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME4_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME3_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME3_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME11_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME11_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME2_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME2_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME5_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME5_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME9_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME9_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME6_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME6_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME10_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME10_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME8_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME8_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME1_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME1_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME0_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME0_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME7_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME7_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME4_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME4_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME3_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME3_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME11_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME11_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME2_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME2_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME5_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME5_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME9_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME9_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME6_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME6_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME10_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME10_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME8_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME8_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME1_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME1_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME0_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME0_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME7_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME7_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME4_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME4_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME3_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME3_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME11_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME11_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME2_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME2_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME5_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME5_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME9_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME9_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME6_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME6_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME10_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME10_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME8_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME8_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME1_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME1_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME0_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME0_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME7_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME7_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME4_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME4_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME3_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME3_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME11_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME11_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME2_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME2_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME5_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME5_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME9_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME9_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME6_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME6_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME10_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME10_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME8_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME8_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME1_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME1_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME0_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME0_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME7_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME7_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_BIT_WITHSTART , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMD_REG_BIT_WITHSTART ); REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_BIT_WITHADDR , 1 , SH_UNT , SH_ACS_SCOM , @@ -36278,6 +37486,33 @@ REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UN REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3_LEN ); +REG64_FLD( PEC_CONTROL_REG_RESET_TRIP_HISTORY , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESET_TRIP_HISTORY ); +REG64_FLD( PEC_CONTROL_REG_RESET_SAMPLE_PULSE_CNT , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESET_SAMPLE_PULSE_CNT ); +REG64_FLD( PEC_CONTROL_REG_F_RESET_CPM_RD , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_F_RESET_CPM_RD ); +REG64_FLD( PEC_CONTROL_REG_F_RESET_CPM_WR , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_F_RESET_CPM_WR ); +REG64_FLD( PEC_CONTROL_REG_RESET_SAMPLE_DTS , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESET_SAMPLE_DTS ); +REG64_FLD( PEC_CONTROL_REG_FORCE_SAMPLE_DTS , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FORCE_SAMPLE_DTS ); +REG64_FLD( PEC_CONTROL_REG_FORCE_SAMPLE_DTS_INTERRUPTIBLE , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FORCE_SAMPLE_DTS_INTERRUPTIBLE ); +REG64_FLD( PEC_CONTROL_REG_FORCE_RESET_THRES_L1RESULTS , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_THRES_L1RESULTS ); +REG64_FLD( PEC_CONTROL_REG_FORCE_RESET_THRES_L2RESULTS , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_THRES_L2RESULTS ); +REG64_FLD( PEC_CONTROL_REG_FORCE_RESET_THRES_L3RESULTS , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_THRES_L3RESULTS ); +REG64_FLD( PEC_CONTROL_REG_FORCE_MEASURE_VOLT_INTERRUPTIBLE , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FORCE_MEASURE_VOLT_INTERRUPTIBLE ); +REG64_FLD( PEC_CONTROL_REG_FORCE_RESET_MEASURE_VOLT , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_MEASURE_VOLT ); +REG64_FLD( PEC_CONTROL_REG_FORCE_SHIFT_SENSOR , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FORCE_SHIFT_SENSOR ); + REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_WITHSTART_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_WITHADDR_0 , 1 , SH_UNT , SH_ACS_SCOM , @@ -36599,42 +37834,42 @@ REG64_FLD( PEC_CPLT_CONF0_RESERVED_ID_62C , 62 , SH_UN REG64_FLD( PEC_CPLT_CONF0_RESERVED_ID_63C , 63 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_63C ); -REG64_FLD( PEC_CPLT_CONF1_TC_IOX_MUX_VSEL , 0 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_IOX_MUX_VSEL ); -REG64_FLD( PEC_CPLT_CONF1_TC_IOX_MUX_VSEL_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_IOX_MUX_VSEL_LEN ); -REG64_FLD( PEC_CPLT_CONF1_UNUSED , 3 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED ); -REG64_FLD( PEC_CPLT_CONF1_TC_PBE0_IOVALID_DC , 4 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PBE0_IOVALID_DC ); -REG64_FLD( PEC_CPLT_CONF1_TC_PBE1_IOVALID_DC , 5 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PBE1_IOVALID_DC ); -REG64_FLD( PEC_CPLT_CONF1_TC_PBE2_IOVALID_DC , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PBE2_IOVALID_DC ); -REG64_FLD( PEC_CPLT_CONF1_TC_PBE3_IOVALID_DC , 7 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PBE3_IOVALID_DC ); -REG64_FLD( PEC_CPLT_CONF1_TC_PBE4_IOVALID_DC , 8 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PBE4_IOVALID_DC ); -REG64_FLD( PEC_CPLT_CONF1_TC_PBE5_IOVALID_DC , 9 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PBE5_IOVALID_DC ); -REG64_FLD( PEC_CPLT_CONF1_TC_PSI_IOVALID_DC , 10 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PSI_IOVALID_DC ); -REG64_FLD( PEC_CPLT_CONF1_IOVALID , 11 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_IOVALID ); -REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_12D , 12 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_FREE_USAGE_12D ); -REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_13D , 13 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_FREE_USAGE_13D ); -REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_14D , 14 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_FREE_USAGE_14D ); -REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_15D , 15 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_FREE_USAGE_15D ); -REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_16D , 16 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_FREE_USAGE_16D ); -REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_17D , 17 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_FREE_USAGE_17D ); -REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_18D , 18 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_FREE_USAGE_18D ); +REG64_FLD( PEC_CPLT_CONF1_UNUSED_0D , 0 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_0D ); +REG64_FLD( PEC_CPLT_CONF1_UNUSED_1D , 1 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_1D ); +REG64_FLD( PEC_CPLT_CONF1_UNUSED_2D , 2 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_2D ); +REG64_FLD( PEC_CPLT_CONF1_UNUSED_3D , 3 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_3D ); +REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_IOVALID , 4 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PCI0_IOVALID ); +REG64_FLD( PEC_CPLT_CONF1_IOVALID_5D , 5 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_5D ); +REG64_FLD( PEC_CPLT_CONF1_IOVALID_6D , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_6D ); +REG64_FLD( PEC_CPLT_CONF1_IOVALID_7D , 7 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_7D ); +REG64_FLD( PEC_CPLT_CONF1_IOVALID_8D , 8 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_8D ); +REG64_FLD( PEC_CPLT_CONF1_IOVALID_9D , 9 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_9D ); +REG64_FLD( PEC_CPLT_CONF1_IOVALID_10D , 10 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_10D ); +REG64_FLD( PEC_CPLT_CONF1_IOVALID_11D , 11 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_11D ); +REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_SWAP_DC , 12 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PCI0_SWAP_DC ); +REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_LANE_CFG_DC , 13 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PCI0_LANE_CFG_DC ); +REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_LANE_CFG_DC_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PCI0_LANE_CFG_DC_LEN ); +REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_RATIO_OVERRIDE , 15 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PCI0_RATIO_OVERRIDE ); +REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_RATIO_DC , 16 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PCI0_RATIO_DC ); +REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_RATIO_DC_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PCI0_RATIO_DC_LEN ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_19D , 19 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_19D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_20D , 20 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, @@ -36653,12 +37888,12 @@ REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_26D , 26 , SH_UN SH_FLD_FREE_USAGE_26D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_27D , 27 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_27D ); -REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_28D , 28 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_FREE_USAGE_28D ); -REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_29D , 29 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_FREE_USAGE_29D ); -REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_30D , 30 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_FREE_USAGE_30D ); +REG64_FLD( PEC_CPLT_CONF1_TC_IOP_SYS_RESET_PCS , 28 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_IOP_SYS_RESET_PCS ); +REG64_FLD( PEC_CPLT_CONF1_TC_IOP_SYS_RESET_PMA , 29 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_IOP_SYS_RESET_PMA ); +REG64_FLD( PEC_CPLT_CONF1_TC_IOP_HSSPORWREN , 30 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_IOP_HSSPORWREN ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_31D , 31 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_31D ); @@ -36793,16 +38028,16 @@ REG64_FLD( PEC_CPLT_CTRL1_TC_REGION1_FENCE , 5 , SH_UN SH_FLD_TC_REGION1_FENCE ); REG64_FLD( PEC_CPLT_CTRL1_TC_REGION2_FENCE , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION2_FENCE ); -REG64_FLD( PEC_CPLT_CTRL1_TC_REGION3_FENCE , 7 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION3_FENCE ); -REG64_FLD( PEC_CPLT_CTRL1_TC_REGION4_FENCE , 8 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION4_FENCE ); -REG64_FLD( PEC_CPLT_CTRL1_TC_REGION5_FENCE , 9 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION5_FENCE ); -REG64_FLD( PEC_CPLT_CTRL1_TC_REGION6_FENCE , 10 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION6_FENCE ); -REG64_FLD( PEC_CPLT_CTRL1_TC_REGION7_FENCE , 11 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION7_FENCE ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_7B , 7 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_7B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_8B , 8 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_8B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_9B , 9 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_9B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_10B , 10 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_10B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_11B , 11 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_11B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_12B , 12 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_12B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_13B , 13 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, @@ -37481,10 +38716,18 @@ REG64_FLD( CAPP_CXA_TRIGCTL_SNPBE_TRIGGER_ENABLE , 8 , SH_UN SH_FLD_SNPBE_TRIGGER_ENABLE ); REG64_FLD( CAPP_CXA_TRIGCTL_SNPBE_UOP_TRIGGER_ENABLE , 9 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SNPBE_UOP_TRIGGER_ENABLE ); +REG64_FLD( CAPP_CXA_TRIGCTL_TLBI_TRIGGER_SEL , 10 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TLBI_TRIGGER_SEL ); +REG64_FLD( CAPP_CXA_TRIGCTL_XPT_TRIGGER_SEL , 11 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_XPT_TRIGGER_SEL ); REG64_FLD( CAPP_CXA_TRIGCTL_SNP_MUX_PORT_SEL , 12 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SNP_MUX_PORT_SEL ); REG64_FLD( CAPP_CXA_TRIGCTL_SNP_MUX_PORT_SEL_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SNP_MUX_PORT_SEL_LEN ); +REG64_FLD( CAPP_CXA_TRIGCTL_XPT_MUX_PORT_SEL , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_XPT_MUX_PORT_SEL ); +REG64_FLD( CAPP_CXA_TRIGCTL_XPT_MUX_PORT_SEL_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_XPT_MUX_PORT_SEL_LEN ); REG64_FLD( PU_DATA0TO7_REGISTER_B_PIB_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_0 ); @@ -38557,10 +39800,14 @@ REG64_FLD( PU_N3_DBG_MODE_REG_GLB_BRCST , 0 , SH_UN SH_FLD_GLB_BRCST ); REG64_FLD( PU_N3_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); -REG64_FLD( PU_N3_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); -REG64_FLD( PU_N3_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_MODE_REG_TRACE_SEL_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRACE_SEL_LEN ); +REG64_FLD( PU_N3_DBG_MODE_REG_TRIG_SEL , 6 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); +REG64_FLD( PU_N3_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRIG_SEL_LEN ); REG64_FLD( PU_N3_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( PU_N3_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_PU_N3 , SH_ACS_SCOM , @@ -38569,15 +39816,23 @@ REG64_FLD( PU_N3_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UN SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( PU_N3_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); +REG64_FLD( PU_N3_DBG_MODE_REG_SYNC_BRCST , 12 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST ); +REG64_FLD( PU_N3_DBG_MODE_REG_SYNC_BRCST_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST_LEN ); REG64_FLD( PU_N1_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); REG64_FLD( PU_N1_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); -REG64_FLD( PU_N1_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); -REG64_FLD( PU_N1_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_MODE_REG_TRACE_SEL_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRACE_SEL_LEN ); +REG64_FLD( PU_N1_DBG_MODE_REG_TRIG_SEL , 6 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); +REG64_FLD( PU_N1_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRIG_SEL_LEN ); REG64_FLD( PU_N1_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( PU_N1_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_PU_N1 , SH_ACS_SCOM , @@ -38586,15 +39841,23 @@ REG64_FLD( PU_N1_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UN SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( PU_N1_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); +REG64_FLD( PU_N1_DBG_MODE_REG_SYNC_BRCST , 12 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST ); +REG64_FLD( PU_N1_DBG_MODE_REG_SYNC_BRCST_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST_LEN ); REG64_FLD( PU_N2_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); REG64_FLD( PU_N2_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); -REG64_FLD( PU_N2_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); -REG64_FLD( PU_N2_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_MODE_REG_TRACE_SEL_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRACE_SEL_LEN ); +REG64_FLD( PU_N2_DBG_MODE_REG_TRIG_SEL , 6 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); +REG64_FLD( PU_N2_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRIG_SEL_LEN ); REG64_FLD( PU_N2_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( PU_N2_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_PU_N2 , SH_ACS_SCOM , @@ -38603,15 +39866,23 @@ REG64_FLD( PU_N2_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UN SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( PU_N2_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); +REG64_FLD( PU_N2_DBG_MODE_REG_SYNC_BRCST , 12 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST ); +REG64_FLD( PU_N2_DBG_MODE_REG_SYNC_BRCST_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST_LEN ); REG64_FLD( PEC_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); REG64_FLD( PEC_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); -REG64_FLD( PEC_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); -REG64_FLD( PEC_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_MODE_REG_TRACE_SEL_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRACE_SEL_LEN ); +REG64_FLD( PEC_DBG_MODE_REG_TRIG_SEL , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); +REG64_FLD( PEC_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIG_SEL_LEN ); REG64_FLD( PEC_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( PEC_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_PEC , SH_ACS_SCOM , @@ -38620,15 +39891,23 @@ REG64_FLD( PEC_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UN SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( PEC_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); +REG64_FLD( PEC_DBG_MODE_REG_SYNC_BRCST , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST ); +REG64_FLD( PEC_DBG_MODE_REG_SYNC_BRCST_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST_LEN ); REG64_FLD( PU_N0_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); REG64_FLD( PU_N0_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); -REG64_FLD( PU_N0_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); -REG64_FLD( PU_N0_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_MODE_REG_TRACE_SEL_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRACE_SEL_LEN ); +REG64_FLD( PU_N0_DBG_MODE_REG_TRIG_SEL , 6 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); +REG64_FLD( PU_N0_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRIG_SEL_LEN ); REG64_FLD( PU_N0_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( PU_N0_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_PU_N0 , SH_ACS_SCOM , @@ -38637,6 +39916,10 @@ REG64_FLD( PU_N0_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UN SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( PU_N0_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); +REG64_FLD( PU_N0_DBG_MODE_REG_SYNC_BRCST , 12 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST ); +REG64_FLD( PU_N0_DBG_MODE_REG_SYNC_BRCST_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST_LEN ); REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RUNN_COUNT_COMPARE_VALUE ); @@ -40497,6 +41780,20 @@ REG64_FLD( CAPP_DEBUG_CONTROL_BLOCK_SEL , 4 , SH_UN REG64_FLD( CAPP_DEBUG_CONTROL_BLOCK_SEL_LEN , 8 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BLOCK_SEL_LEN ); +REG64_FLD( PEC_DEBUG_TRACE_CONTROL_SCOM_TRACE_START , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_START ); +REG64_FLD( PEC_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_STOP ); +REG64_FLD( PEC_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_RESET ); + +REG64_FLD( PU_DEBUG_TRACE_CONTROL_SCOM_TRACE_START , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_START ); +REG64_FLD( PU_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_STOP ); +REG64_FLD( PU_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_RESET ); + REG64_FLD( CAPP_DFSUOP1_WORD , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_WORD ); REG64_FLD( CAPP_DFSUOP1_WORD_LEN , 56 , SH_UNT_CAPP , SH_ACS_SCOM , @@ -41314,6 +42611,16 @@ REG64_FLD( PU_OTPROM1_ECID_PART9_REGISTER_PART_9 , 0 , SH_UN REG64_FLD( PU_OTPROM1_ECID_PART9_REGISTER_PART_9_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_9_LEN ); +REG64_FLD( PEC_EDRAM_STATUS_STAT , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STAT ); +REG64_FLD( PEC_EDRAM_STATUS_STAT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STAT_LEN ); + +REG64_FLD( PU_EECNT_REG_EECNT , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EECNT ); +REG64_FLD( PU_EECNT_REG_EECNT_LEN , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EECNT_LEN ); + REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LPID ); REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN , 12 , SH_UNT , SH_ACS_SCOM , @@ -41689,6 +42996,190 @@ REG64_FLD( PU_EHHCA_FIR_REG_SCOM_ERROR , 34 , SH_UN REG64_FLD( PU_EHHCA_FIR_REG_PARITY_ERROR , 35 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_DPX0_DAT_UE , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DPX0_DAT_UE ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_DPX0_DAT_SUE , 1 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DPX0_DAT_SUE ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_DPX0_DAT_CE , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DPX0_DAT_CE ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_CO_DROP_COUNTER_FULL , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_CO_DROP_COUNTER_FULL ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_DATA_HANG_DETECT , 5 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_HANG_DETECT ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_UNEXPECTED_DATA_OR_CRESP , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_UNEXPECTED_DATA_OR_CRESP ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_INTERNAL_ERROR , 7 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERNAL_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_PBDAT_XSTOP_ERROR , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_PBDAT_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_ALTDSM_XSTOP_ERROR , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_ALTDSM_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_XCSMP_XSTOP_ERROR , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_XCSMP_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_PBADR_XSTOP_ERROR , 11 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_PBADR_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_SND_XSTOP_ERROR , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_SND_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_RCV_XSTOP_ERROR , 13 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_RCV_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_PBDAT_RECOV_ERROR , 14 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_PBDAT_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_ALTDSM_RECOV_ERROR , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_ALTDSM_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_XCSMP_RECOV_ERROR , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_XCSMP_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_PBADR_RECOV_ERROR , 17 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_PBADR_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_SND_RECOV_ERROR , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_SND_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_RCV_RRC , 19 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_RCV_RRC ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_NHTM_SCON_E , 20 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_NHTM_SCON_E ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_SCOM_ERROR , 22 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_SCOM_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_PARITY_ERROR , 23 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PARITY_ERROR ); + +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_DPX0_DAT_UE , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DPX0_DAT_UE ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_DPX0_DAT_SUE , 1 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DPX0_DAT_SUE ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_DPX0_DAT_CE , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DPX0_DAT_CE ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_CO_DROP_COUNTER_FULL , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_CO_DROP_COUNTER_FULL ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_DATA_HANG_DETECT , 5 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_HANG_DETECT ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_UNEXPECTED_DATA_OR_CRESP , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_UNEXPECTED_DATA_OR_CRESP ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_INTERNAL_ERROR , 7 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERNAL_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_PBDAT_XSTOP_ERROR , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_PBDAT_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_ALTDSM_XSTOP_ERROR , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_ALTDSM_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_XCSMP_XSTOP_ERROR , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_XCSMP_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_PBADR_XSTOP_ERROR , 11 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_PBADR_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_SND_XSTOP_ERROR , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_SND_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_RCV_XSTOP_ERROR , 13 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_RCV_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_PBDAT_RECOV_ERROR , 14 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_PBDAT_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_ALTDSM_RECOV_ERROR , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_ALTDSM_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_XCSMP_RECOV_ERROR , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_XCSMP_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_PBADR_RECOV_ERROR , 17 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_PBADR_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_SND_RECOV_ERROR , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_SND_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_RCV_RRC , 19 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_RCV_RRC ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_NHTM_SCON_E , 20 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_NHTM_SCON_E ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_SCOM_ERROR , 22 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_SCOM_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_PARITY_ERROR , 23 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PARITY_ERROR ); + +REG64_FLD( PU_ENHCA_FIR_MASK_REG_DPX0_DAT_UE , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DPX0_DAT_UE ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_DPX0_DAT_SUE , 1 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DPX0_DAT_SUE ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_DPX0_DAT_CE , 2 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DPX0_DAT_CE ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_CO_DROP_COUNTER_FULL , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_CO_DROP_COUNTER_FULL ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_DATA_HANG_DETECT , 5 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DATA_HANG_DETECT ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_UNEXPECTED_DATA_OR_CRESP , 6 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_UNEXPECTED_DATA_OR_CRESP ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_INTERNAL_ERROR , 7 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_PBDAT_XSTOP_ERROR , 8 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_PBDAT_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_ALTDSM_XSTOP_ERROR , 9 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_ALTDSM_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_XCSMP_XSTOP_ERROR , 10 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_XCSMP_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_PBADR_XSTOP_ERROR , 11 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_PBADR_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_SND_XSTOP_ERROR , 12 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_SND_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_RCV_XSTOP_ERROR , 13 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_RCV_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_PBDAT_RECOV_ERROR , 14 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_PBDAT_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_ALTDSM_RECOV_ERROR , 15 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_ALTDSM_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_XCSMP_RECOV_ERROR , 16 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_XCSMP_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_PBADR_RECOV_ERROR , 17 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_PBADR_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_SND_RECOV_ERROR , 18 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_SND_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_RCV_RRC , 19 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_RCV_RRC ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_NHTM_SCON_E , 20 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_NHTM_SCON_E ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_SPARE_ERROR_MASK , 21 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_ERROR_MASK ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_SCOM_ERROR , 22 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_PARITY_ERROR , 23 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PARITY_ERROR ); + +REG64_FLD( PU_ENHCA_FIR_REG_DPX0_DAT_UE , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DPX0_DAT_UE ); +REG64_FLD( PU_ENHCA_FIR_REG_DPX0_DAT_SUE , 1 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DPX0_DAT_SUE ); +REG64_FLD( PU_ENHCA_FIR_REG_DPX0_DAT_CE , 2 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DPX0_DAT_CE ); +REG64_FLD( PU_ENHCA_FIR_REG_CO_DROP_COUNTER_FULL , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_CO_DROP_COUNTER_FULL ); +REG64_FLD( PU_ENHCA_FIR_REG_DATA_HANG_DETECT , 5 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DATA_HANG_DETECT ); +REG64_FLD( PU_ENHCA_FIR_REG_UNEXPECTED_DATA_OR_CRESP , 6 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_UNEXPECTED_DATA_OR_CRESP ); +REG64_FLD( PU_ENHCA_FIR_REG_INTERNAL_ERROR , 7 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_PBDAT_XSTOP_ERROR , 8 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_PBDAT_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_ALTDSM_XSTOP_ERROR , 9 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_ALTDSM_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_XCSMP_XSTOP_ERROR , 10 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_XCSMP_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_PBADR_XSTOP_ERROR , 11 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_PBADR_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_SND_XSTOP_ERROR , 12 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_SND_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_RCV_XSTOP_ERROR , 13 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_RCV_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_PBDAT_RECOV_ERROR , 14 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_PBDAT_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_ALTDSM_RECOV_ERROR , 15 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_ALTDSM_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_XCSMP_RECOV_ERROR , 16 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_XCSMP_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_PBADR_RECOV_ERROR , 17 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_PBADR_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_SND_RECOV_ERROR , 18 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_SND_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_RCV_RRC , 19 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_RCV_RRC ); +REG64_FLD( PU_ENHCA_FIR_REG_NHTM_SCON_E , 20 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_NHTM_SCON_E ); +REG64_FLD( PU_ENHCA_FIR_REG_SPARE_ERROR , 21 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_SCOM_ERROR , 22 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_PARITY_ERROR , 23 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PARITY_ERROR ); + REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_RATE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RATE ); REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_RATE_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , @@ -42067,8 +43558,8 @@ REG64_FLD( PEC_ERROR_REG_PCB_INTERFACE , 16 , SH_UN SH_FLD_PCB_INTERFACE ); REG64_FLD( PEC_ERROR_REG_CHIPLET_OFFLINE , 17 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CHIPLET_OFFLINE ); -REG64_FLD( PEC_ERROR_REG_CHIPLET_GRID_SKITTER , 18 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_CHIPLET_GRID_SKITTER ); +REG64_FLD( PEC_ERROR_REG_EDRAM_SEQUENCE_ERR , 18 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EDRAM_SEQUENCE_ERR ); REG64_FLD( PEC_ERROR_REG_CTRL_PARITY , 19 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CTRL_PARITY ); REG64_FLD( PEC_ERROR_REG_ADDRESS_PARITY , 20 , SH_UNT_PEC , SH_ACS_SCOM , @@ -42086,10 +43577,163 @@ REG64_FLD( PEC_ERROR_REG_PLL_UNLOCK , 25 , SH_UN REG64_FLD( PEC_ERROR_REG_PLL_UNLOCK_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PLL_UNLOCK_LEN ); -REG64_FLD( PEC_ERROR_STATUS_ERRORS , 0 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_ERRORS ); -REG64_FLD( PEC_ERROR_STATUS_ERRORS_LEN , 32 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_ERRORS_LEN ); +REG64_FLD( PEC_ERROR_STATUS_PCB_WRITE_NOT_ALLOWED_ERR , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_WRITE_NOT_ALLOWED_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PCB_READ_NOT_ALLOWED_ERR , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_READ_NOT_ALLOWED_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PCB_PARITY_ON_CMD_ERR , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_CMD_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PCB_ADDRESS_NOT_VALID_ERR , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_NOT_VALID_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PCB_PARITY_ON_ADDR_ERR , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_ADDR_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PCB_PARITY_ON_DATA_ERR , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_DATA_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PCB_PROTECTED_ACCESS_INVALID_ERR , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_PROTECTED_ACCESS_INVALID_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PCB_PARITY_ON_SPCIF_ERR , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_SPCIF_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PCB_WRITE_AND_OPCG_IP_ERR , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_WRITE_AND_OPCG_IP_ERR ); +REG64_FLD( PEC_ERROR_STATUS_SCAN_READ_AND_OPCG_IP_ERR , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SCAN_READ_AND_OPCG_IP_ERR ); +REG64_FLD( PEC_ERROR_STATUS_CLOCK_CMD_CONFLICT_ERR , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CLOCK_CMD_CONFLICT_ERR ); +REG64_FLD( PEC_ERROR_STATUS_SCAN_COLLISION_ERR , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SCAN_COLLISION_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PREVENTED_SCAN_COLLISION_ERR , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PREVENTED_SCAN_COLLISION_ERR ); +REG64_FLD( PEC_ERROR_STATUS_OPCG_TRIGGER_ERR , 13 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_OPCG_TRIGGER_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PHASE_CNT_CORRUPTION_ERR , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PHASE_CNT_CORRUPTION_ERR ); +REG64_FLD( PEC_ERROR_STATUS_CLOCK_CMD_PREVENTED_ERR , 15 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CLOCK_CMD_PREVENTED_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PARITY_ON_OPCG_SM_ERR , 16 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARITY_ON_OPCG_SM_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PARITY_ON_CLOCK_MUX_REG_ERR , 17 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARITY_ON_CLOCK_MUX_REG_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PARITY_ON_OPCG_REG_ERR , 18 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARITY_ON_OPCG_REG_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PARITY_ON_SYNC_CONFIG_REG_ERR , 19 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARITY_ON_SYNC_CONFIG_REG_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PARITY_ON_XSTOP_REG_ERR , 20 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARITY_ON_XSTOP_REG_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PARITY_ON_GPIO_REG_ERR , 21 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARITY_ON_GPIO_REG_ERR ); +REG64_FLD( PEC_ERROR_STATUS_CLKCMD_REQUEST_ERR , 22 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CLKCMD_REQUEST_ERR ); +REG64_FLD( PEC_ERROR_STATUS_CBS_PROTOCOL_ERR , 23 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CBS_PROTOCOL_ERR ); +REG64_FLD( PEC_ERROR_STATUS_VITL_ALIGN_ERR , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_VITL_ALIGN_ERR ); +REG64_FLD( PEC_ERROR_STATUS_UNIT_SYNC_LVL_ERR , 25 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT_SYNC_LVL_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PARITY_ON_SELFBOOT_CMD_STATE_ERR , 26 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARITY_ON_SELFBOOT_CMD_STATE_ERR ); +REG64_FLD( PEC_ERROR_STATUS_UNUSED_ERROR27 , 27 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR27 ); +REG64_FLD( PEC_ERROR_STATUS_UNUSED_ERROR28 , 28 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR28 ); +REG64_FLD( PEC_ERROR_STATUS_UNUSED_ERROR29 , 29 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR29 ); +REG64_FLD( PEC_ERROR_STATUS_UNUSED_ERROR30 , 30 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR30 ); +REG64_FLD( PEC_ERROR_STATUS_UNUSED_ERROR31 , 31 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR31 ); + +REG64_FLD( CAPP_ERRRPT_APC_COLLISION , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APC_COLLISION ); +REG64_FLD( CAPP_ERRRPT_FSM_SM_ERROR , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FSM_SM_ERROR ); +REG64_FLD( CAPP_ERRRPT_RBUFSM_ERROR , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RBUFSM_ERROR ); +REG64_FLD( CAPP_ERRRPT_WBUF_SM_ERROR , 3 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_WBUF_SM_ERROR ); +REG64_FLD( CAPP_ERRRPT_PERR_BAR_REG , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PERR_BAR_REG ); +REG64_FLD( CAPP_ERRRPT_PERR_NONBAR_REG , 5 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PERR_NONBAR_REG ); +REG64_FLD( CAPP_ERRRPT_RTAG_HANG_EPOCH , 6 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RTAG_HANG_EPOCH ); +REG64_FLD( CAPP_ERRRPT_CRSP0_REGS_CE_ERR , 7 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP0_REGS_CE_ERR ); +REG64_FLD( CAPP_ERRRPT_CRSP1_REGS_CE_ERR , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP1_REGS_CE_ERR ); +REG64_FLD( CAPP_ERRRPT_UOP_REGS_CE_ERR , 9 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_UOP_REGS_CE_ERR ); +REG64_FLD( CAPP_ERRRPT_CRSP0_REGS_UE_ERR , 10 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP0_REGS_UE_ERR ); +REG64_FLD( CAPP_ERRRPT_CRSP1_REGS_UE_ERR , 11 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP1_REGS_UE_ERR ); +REG64_FLD( CAPP_ERRRPT_UOP_REGS_UE_ERR , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_UOP_REGS_UE_ERR ); +REG64_FLD( CAPP_ERRRPT_CRSP0_REGS_ATAG_PERR , 13 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP0_REGS_ATAG_PERR ); +REG64_FLD( CAPP_ERRRPT_CRSP0_REGS_TTAG_PERR , 14 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP0_REGS_TTAG_PERR ); +REG64_FLD( CAPP_ERRRPT_CRSP1_REGS_ATAG_PERR , 15 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP1_REGS_ATAG_PERR ); +REG64_FLD( CAPP_ERRRPT_CRSP1_REGS_TTAG_PERR , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP1_REGS_TTAG_PERR ); +REG64_FLD( CAPP_ERRRPT_FIR_ACTION1 , 17 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FIR_ACTION1 ); +REG64_FLD( CAPP_ERRRPT_FIR_ACTION2 , 18 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FIR_ACTION2 ); +REG64_FLD( CAPP_ERRRPT_FIR_ACTION3 , 19 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FIR_ACTION3 ); +REG64_FLD( CAPP_ERRRPT_UNEXPECTED_CRESP , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_UNEXPECTED_CRESP ); +REG64_FLD( CAPP_ERRRPT_LD_CLASS_ARE_ERROR , 21 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LD_CLASS_ARE_ERROR ); +REG64_FLD( CAPP_ERRRPT_ST_CLASS_ARE_ERROR , 22 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_ST_CLASS_ARE_ERROR ); +REG64_FLD( CAPP_ERRRPT_LD_CLASS_ACK_DEAD , 23 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LD_CLASS_ACK_DEAD ); +REG64_FLD( CAPP_ERRRPT_FOREIGN_OP_HANG , 24 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FOREIGN_OP_HANG ); +REG64_FLD( CAPP_ERRRPT_DOMESTIC_OP_HANG , 25 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DOMESTIC_OP_HANG ); +REG64_FLD( CAPP_ERRRPT_ST_CLASS_ACK_DEAD , 26 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_ST_CLASS_ACK_DEAD ); +REG64_FLD( CAPP_ERRRPT_ACTIVATE_FSMERR , 27 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_ACTIVATE_FSMERR ); +REG64_FLD( CAPP_ERRRPT_SPARE1 , 28 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SPARE1 ); +REG64_FLD( CAPP_ERRRPT_SPARE2 , 29 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SPARE2 ); +REG64_FLD( CAPP_ERRRPT_CMDQ_CE_ERR , 30 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CMDQ_CE_ERR ); +REG64_FLD( CAPP_ERRRPT_CMDQ_UE_ERR , 31 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CMDQ_UE_ERR ); +REG64_FLD( CAPP_ERRRPT_CRSP2_REGS_CE_ERR , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP2_REGS_CE_ERR ); +REG64_FLD( CAPP_ERRRPT_CRSP3_REGS_CE_ERR , 33 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP3_REGS_CE_ERR ); +REG64_FLD( CAPP_ERRRPT_CRSP2_REGS_UE_ERR , 34 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP2_REGS_UE_ERR ); +REG64_FLD( CAPP_ERRRPT_CRSP3_REGS_UE_ERR , 35 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP3_REGS_UE_ERR ); +REG64_FLD( CAPP_ERRRPT_CRSP2_REGS_ATAG_PERR , 36 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP2_REGS_ATAG_PERR ); +REG64_FLD( CAPP_ERRRPT_CRSP3_REGS_ATAG_PERR , 37 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP3_REGS_ATAG_PERR ); +REG64_FLD( CAPP_ERRRPT_CRSP2_REGS_TTAG_PERR , 38 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP2_REGS_TTAG_PERR ); +REG64_FLD( CAPP_ERRRPT_CRSP3_REGS_TTAG_PERR , 39 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP3_REGS_TTAG_PERR ); +REG64_FLD( CAPP_ERRRPT_SNPRTAG_REGS_CE_ERR0 , 40 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNPRTAG_REGS_CE_ERR0 ); +REG64_FLD( CAPP_ERRRPT_SNPRTAG_REGS_CE_ERR1 , 41 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNPRTAG_REGS_CE_ERR1 ); +REG64_FLD( CAPP_ERRRPT_SNPRTAG_REGS_CE_ERR2 , 42 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNPRTAG_REGS_CE_ERR2 ); +REG64_FLD( CAPP_ERRRPT_SNPRTAG_REGS_UE_ERR0 , 43 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNPRTAG_REGS_UE_ERR0 ); +REG64_FLD( CAPP_ERRRPT_SNPRTAG_REGS_UE_ERR1 , 44 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNPRTAG_REGS_UE_ERR1 ); +REG64_FLD( CAPP_ERRRPT_SNPRTAG_REGS_UE_ERR2 , 45 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNPRTAG_REGS_UE_ERR2 ); REG64_FLD( PU_NPU_SM2_ERR_FIRST_BITS , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_BITS ); @@ -42208,6 +43852,38 @@ REG64_FLD( PU_NPU_CTL_ERR_SCOPE_CTL_CONFIG_CTL , 0 , SH_UN REG64_FLD( PU_NPU_CTL_ERR_SCOPE_CTL_CONFIG_CTL_LEN , 16 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_CTL_LEN ); +REG64_FLD( PEC_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_THERM_MODEREG_PARITY_ERR_HOLD , 1 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_THERM_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_ERR_HOLD , 2 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SKITTER_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_ERR_HOLD , 3 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SKITTER_FORCEREG_PARITY_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD , 4 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_VOLT_MODEREG_PARITY_ERR_HOLD , 5 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_VOLT_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_SKITTER_CLKSRCREG_PARITY_ERR_HOLD , 6 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SKITTER_CLKSRCREG_PARITY_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_COUNT_STATE_ERR_HOLD , 7 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_COUNT_STATE_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_RUN_STATE_ERR_HOLD , 8 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_RUN_STATE_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_THRES_THERM_STATE_ERR_HOLD , 9 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_THRES_THERM_STATE_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_THRES_THERM_OVERFLOW_ERR_HOLD , 10 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_THRES_THERM_OVERFLOW_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_SHIFTER_PARITY_ERR_HOLD , 11 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SHIFTER_PARITY_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_SHIFTER_VALID_ERR_HOLD , 12 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SHIFTER_VALID_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_TIMEOUT_ERR_HOLD , 13 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_TIMEOUT_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_F_SKITTER_ERR_HOLD , 14 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_F_SKITTER_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_PCB_ERR_HOLD_OUT , 15 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_PCB_ERR_HOLD_OUT ); REG64_FLD( PEC_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK , 16 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK ); REG64_FLD( PEC_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK , 17 , SH_UNT_PEC , SH_ACS_SCOM_RO , @@ -42238,6 +43914,36 @@ REG64_FLD( PEC_ERR_STATUS_REG_F_SKITTER_READ_MASK , 30 , SH_UN SH_FLD_F_SKITTER_READ_MASK ); REG64_FLD( PEC_ERR_STATUS_REG_PCB_MASK , 31 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_PCB_MASK ); +REG64_FLD( PEC_ERR_STATUS_REG_COUNT_STATE_LT , 40 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_COUNT_STATE_LT ); +REG64_FLD( PEC_ERR_STATUS_REG_COUNT_STATE_LT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_COUNT_STATE_LT_LEN ); +REG64_FLD( PEC_ERR_STATUS_REG_RUN_STATE_LT , 44 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_RUN_STATE_LT ); +REG64_FLD( PEC_ERR_STATUS_REG_RUN_STATE_LT_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_RUN_STATE_LT_LEN ); +REG64_FLD( PEC_ERR_STATUS_REG_SHIFT_DTS_LT , 47 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SHIFT_DTS_LT ); +REG64_FLD( PEC_ERR_STATUS_REG_SHIFT_VOLT_LT , 48 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SHIFT_VOLT_LT ); +REG64_FLD( PEC_ERR_STATUS_REG_READ_STATE_LT , 49 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_READ_STATE_LT ); +REG64_FLD( PEC_ERR_STATUS_REG_READ_STATE_LT_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_READ_STATE_LT_LEN ); +REG64_FLD( PEC_ERR_STATUS_REG_WRITE_STATE_LT , 51 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_WRITE_STATE_LT ); +REG64_FLD( PEC_ERR_STATUS_REG_WRITE_STATE_LT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_WRITE_STATE_LT_LEN ); +REG64_FLD( PEC_ERR_STATUS_REG_SAMPLE_DTS_LT , 55 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SAMPLE_DTS_LT ); +REG64_FLD( PEC_ERR_STATUS_REG_MEASURE_VOLT_LT , 56 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_MEASURE_VOLT_LT ); +REG64_FLD( PEC_ERR_STATUS_REG_READ_CPM_LT , 57 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_READ_CPM_LT ); +REG64_FLD( PEC_ERR_STATUS_REG_WRITE_CPM_LT , 58 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_WRITE_CPM_LT ); +REG64_FLD( PEC_ERR_STATUS_REG_UNUSED , 59 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_UNUSED ); REG64_FLD( PU_ESB_CI_BASE_BASE , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_BASE ); @@ -42265,8 +43971,8 @@ REG64_FLD( PU_EXPORT_REGL_CTRL_TP_PB_FUSE_TOPOLOGY_GROUP , 4 , SH_UN SH_FLD_TP_PB_FUSE_TOPOLOGY_GROUP ); REG64_FLD( PU_EXPORT_REGL_CTRL_TP_PB_FUSE_TOPOLOGY_GROUP_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_TP_PB_FUSE_TOPOLOGY_GROUP_LEN ); -REG64_FLD( PU_EXPORT_REGL_CTRL_TP_PB_FUSE_SPARE , 6 , SH_UNT , SH_ACS_SCOM , - SH_FLD_TP_PB_FUSE_SPARE ); +REG64_FLD( PU_EXPORT_REGL_CTRL_TP_NP_NVLINK_DISABLE , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TP_NP_NVLINK_DISABLE ); REG64_FLD( PU_EXTENDED_STATUS_B_MSM_CURR_STATE_0 , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_MSM_CURR_STATE_0 ); @@ -42639,6 +44345,18 @@ REG64_FLD( PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ0_0 , 0 , SH_UN SH_FLD_FIFO_BITS_READ0_0 ); REG64_FLD( PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ0_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_0_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ2_0 , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ2_0 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ2_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ2_0_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ3_0 , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ3_0 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ3_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ3_0_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ4_0 , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ4_0 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ4_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ4_0_LEN ); REG64_FLD( PU_FIFO4_REGISTER_READ_B_PEEK_DATA1_0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0 ); REG64_FLD( PU_FIFO4_REGISTER_READ_B_PEEK_DATA1_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , @@ -42650,6 +44368,18 @@ REG64_FLD( PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ0_1 , 0 , SH_UN SH_FLD_FIFO_BITS_READ0_1 ); REG64_FLD( PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ0_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_1_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ2_1 , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ2_1 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ2_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ2_1_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ3_1 , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ3_1 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ3_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ3_1_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ4_1 , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ4_1 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ4_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ4_1_LEN ); REG64_FLD( PU_FIFO4_REGISTER_READ_C_PEEK_DATA1_1 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1 ); REG64_FLD( PU_FIFO4_REGISTER_READ_C_PEEK_DATA1_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , @@ -42661,6 +44391,18 @@ REG64_FLD( PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ0_2 , 0 , SH_UN SH_FLD_FIFO_BITS_READ0_2 ); REG64_FLD( PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ0_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_2_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ2_2 , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ2_2 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ2_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ2_2_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ3_2 , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ3_2 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ3_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ3_2_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ4_2 , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ4_2 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ4_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ4_2_LEN ); REG64_FLD( PU_FIFO4_REGISTER_READ_D_PEEK_DATA1_2 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2 ); REG64_FLD( PU_FIFO4_REGISTER_READ_D_PEEK_DATA1_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , @@ -42672,6 +44414,18 @@ REG64_FLD( PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ0_3 , 0 , SH_UN SH_FLD_FIFO_BITS_READ0_3 ); REG64_FLD( PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ0_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_3_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ2_3 , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ2_3 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ2_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ2_3_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ3_3 , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ3_3 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ3_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ3_3_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ4_3 , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ4_3 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ4_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ4_3_LEN ); REG64_FLD( PU_FIFO4_REGISTER_READ_E_PEEK_DATA1_3 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3 ); REG64_FLD( PU_FIFO4_REGISTER_READ_E_PEEK_DATA1_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , @@ -42679,6 +44433,11 @@ REG64_FLD( PU_FIFO4_REGISTER_READ_E_PEEK_DATA1_3_LEN , 8 , SH_UN REG64_FLD( PU_FIFO4_REGISTER_READ_E_LBUS_PARITY_ERR1_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_3 ); +REG64_FLD( PU_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION0 ); +REG64_FLD( PU_FIR_ACTION0_REG_ACTION0_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION0_LEN ); + REG64_FLD( CAPP_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_CAPP , SH_ACS_SCOM_RO , SH_FLD_ACTION0 ); REG64_FLD( CAPP_FIR_ACTION0_REG_ACTION0_LEN , 52 , SH_UNT_CAPP , SH_ACS_SCOM_RO , @@ -42689,11 +44448,6 @@ REG64_FLD( PEC_FIR_ACTION0_REG_ACTION0 , 0 , SH_UN REG64_FLD( PEC_FIR_ACTION0_REG_ACTION0_LEN , 37 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_ACTION0_LEN ); -REG64_FLD( PU_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_ACTION0 ); -REG64_FLD( PU_FIR_ACTION0_REG_ACTION0_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_ACTION0_LEN ); - REG64_FLD( PU_NPU_MSC_SM0_FIR_ACTION0_REG_0_0 , 0 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_RW , SH_FLD_0 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_ACTION0_REG_0_0_LEN , 64 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_RW , @@ -42704,6 +44458,11 @@ REG64_FLD( PU_NPU_MSC_SM2_FIR_ACTION0_REG_1_1 , 0 , SH_UN REG64_FLD( PU_NPU_MSC_SM2_FIR_ACTION0_REG_1_1_LEN , 64 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM_RW , SH_FLD_1_LEN ); +REG64_FLD( PU_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION1 ); +REG64_FLD( PU_FIR_ACTION1_REG_ACTION1_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION1_LEN ); + REG64_FLD( CAPP_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_CAPP , SH_ACS_SCOM_RO , SH_FLD_ACTION1 ); REG64_FLD( CAPP_FIR_ACTION1_REG_ACTION1_LEN , 52 , SH_UNT_CAPP , SH_ACS_SCOM_RO , @@ -42714,11 +44473,6 @@ REG64_FLD( PEC_FIR_ACTION1_REG_ACTION1 , 0 , SH_UN REG64_FLD( PEC_FIR_ACTION1_REG_ACTION1_LEN , 37 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_ACTION1_LEN ); -REG64_FLD( PU_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_ACTION1 ); -REG64_FLD( PU_FIR_ACTION1_REG_ACTION1_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_ACTION1_LEN ); - REG64_FLD( PU_NPU_MSC_SM0_FIR_ACTION1_REG_0_0 , 0 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_RW , SH_FLD_0 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_ACTION1_REG_0_0_LEN , 64 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_RW , @@ -42748,6 +44502,21 @@ REG64_FLD( PEC_FIR_MASK_IN6_LEN , 20 , SH_UN REG64_FLD( PEC_FIR_MASK_IN26 , 26 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN26 ); +REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED0 , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PSI_RESERVED0 ); +REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED1 , 1 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PSI_RESERVED1 ); +REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED2 , 2 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PSI_RESERVED2 ); +REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED3 , 3 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PSI_RESERVED3 ); +REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED4 , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PSI_RESERVED4 ); +REG64_FLD( PU_FIR_MASK_REG_INTERNAL_SCOM_ERROR , 5 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR ); +REG64_FLD( PU_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE , 6 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); + REG64_FLD( CAPP_FIR_MASK_REG_BAR_PE , 0 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_BAR_PE ); REG64_FLD( CAPP_FIR_MASK_REG_REGISTER_PE , 1 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , @@ -42928,21 +44697,6 @@ REG64_FLD( PEC_FIR_MASK_REG_SCOM_PERR0 , 35 , SH_UN REG64_FLD( PEC_FIR_MASK_REG_SCOM_PERR1 , 36 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PERR1 ); -REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED0 , 0 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_PSI_RESERVED0 ); -REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED1 , 1 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_PSI_RESERVED1 ); -REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED2 , 2 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_PSI_RESERVED2 ); -REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED3 , 3 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_PSI_RESERVED3 ); -REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED4 , 4 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_PSI_RESERVED4 ); -REG64_FLD( PU_FIR_MASK_REG_INTERNAL_SCOM_ERROR , 5 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_INTERNAL_SCOM_ERROR ); -REG64_FLD( PU_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE , 6 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); - REG64_FLD( PU_FIR_MASK_REGISTER_ECC_UNCORRECTED_ERR_PIB , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_UNCORRECTED_ERR_PIB ); REG64_FLD( PU_FIR_MASK_REGISTER_BAD_ARRAY_ADDR_PIB , 5 , SH_UNT , SH_ACS_SCOM , @@ -42970,6 +44724,21 @@ REG64_FLD( PU_NPU_MSC_SM2_FIR_MASK_REG_1_1 , 0 , SH_UN REG64_FLD( PU_NPU_MSC_SM2_FIR_MASK_REG_1_1_LEN , 64 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_1_LEN ); +REG64_FLD( PU_FIR_REG_PSI_RESERVED0 , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PSI_RESERVED0 ); +REG64_FLD( PU_FIR_REG_PSI_RESERVED1 , 1 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PSI_RESERVED1 ); +REG64_FLD( PU_FIR_REG_PSI_RESERVED2 , 2 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PSI_RESERVED2 ); +REG64_FLD( PU_FIR_REG_PSI_RESERVED3 , 3 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PSI_RESERVED3 ); +REG64_FLD( PU_FIR_REG_PSI_RESERVED4 , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PSI_RESERVED4 ); +REG64_FLD( PU_FIR_REG_INTERNAL_SCOM_ERROR , 5 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR ); +REG64_FLD( PU_FIR_REG_INTERNAL_SCOM_ERROR_CLONE , 6 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); + REG64_FLD( CAPP_FIR_REG_BAR_PE , 0 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_BAR_PE ); REG64_FLD( CAPP_FIR_REG_REGISTER_PE , 1 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , @@ -43075,21 +44844,6 @@ REG64_FLD( CAPP_FIR_REG_SCOM_ERR2 , 50 , SH_UN REG64_FLD( CAPP_FIR_REG_SCOM_ERR , 51 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); -REG64_FLD( PU_FIR_REG_PSI_RESERVED0 , 0 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_PSI_RESERVED0 ); -REG64_FLD( PU_FIR_REG_PSI_RESERVED1 , 1 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_PSI_RESERVED1 ); -REG64_FLD( PU_FIR_REG_PSI_RESERVED2 , 2 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_PSI_RESERVED2 ); -REG64_FLD( PU_FIR_REG_PSI_RESERVED3 , 3 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_PSI_RESERVED3 ); -REG64_FLD( PU_FIR_REG_PSI_RESERVED4 , 4 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_PSI_RESERVED4 ); -REG64_FLD( PU_FIR_REG_INTERNAL_SCOM_ERROR , 5 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_INTERNAL_SCOM_ERROR ); -REG64_FLD( PU_FIR_REG_INTERNAL_SCOM_ERROR_CLONE , 6 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); - REG64_FLD( PHB_FIR_REG_AIB_COMMAND_INVALID , 0 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_AIB_COMMAND_INVALID ); REG64_FLD( PHB_FIR_REG_AIB_ADDRESS_INVALID , 1 , SH_UNT_PHB , SH_ACS_SCOM2_OR , @@ -43196,6 +44950,10 @@ REG64_FLD( PHB_FIR_REG_MRG_AIB2_TX_TIMEOUT_ERROR , 52 , SH_UN SH_FLD_MRG_AIB2_TX_TIMEOUT_ERROR ); REG64_FLD( PHB_FIR_REG_MRG_MRT_ERROR , 53 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_MRG_MRT_ERROR ); +REG64_FLD( PHB_FIR_REG_MRG_RESERVED01 , 54 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_RESERVED01 ); +REG64_FLD( PHB_FIR_REG_MRG_RESERVED02 , 55 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_RESERVED02 ); REG64_FLD( PHB_FIR_REG_TCE_IODA_PAGE_ACCESS_ERROR , 56 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_TCE_IODA_PAGE_ACCESS_ERROR ); REG64_FLD( PHB_FIR_REG_TCE_REQUEST_TIMEOUT_ERROR , 57 , SH_UNT_PHB , SH_ACS_SCOM2_OR , @@ -43208,6 +44966,8 @@ REG64_FLD( PHB_FIR_REG_TCE_ECC_CORRECTABLE_ERROR , 60 , SH_UN SH_FLD_TCE_ECC_CORRECTABLE_ERROR ); REG64_FLD( PHB_FIR_REG_TCE_ECC_UNCORRECTABLE_ERROR , 61 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_TCE_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_FIR_REG_TCE_RESERVED01 , 62 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_TCE_RESERVED01 ); REG64_FLD( PHB_FIR_REG_INTERNAL_PARITY_ERROR , 63 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_PARITY_ERROR ); @@ -43549,6 +45309,11 @@ REG64_FLD( PEC_FIR_WOF_REG_WOF , 0 , SH_UN REG64_FLD( PEC_FIR_WOF_REG_WOF_LEN , 37 , SH_UNT_PEC , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LEN ); +REG64_FLD( PU_FIR_WOF_REG_WOF , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF ); +REG64_FLD( PU_FIR_WOF_REG_WOF_LEN , 7 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LEN ); + REG64_FLD( PU_NPU_MSC_SM0_FIR_WOF_REG_0_0 , 0 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_0 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_WOF_REG_0_0_LEN , 64 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_WCLRREG, @@ -43625,50 +45390,77 @@ REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_51 , 16 , SH_UN REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_52 , 17 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BDF2PE_52 ); -REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SBE , 6 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_FSB_DOWNFIFO_DATA_IN_DNFIFO_DATA_IN_PORT , 0 , SH_UNT , SH_ACS_SCOM_WO , + SH_FLD_DNFIFO_DATA_IN_PORT ); +REG64_FLD( PU_FSB_DOWNFIFO_DATA_IN_DNFIFO_DATA_IN_PORT_LEN , 32 , SH_UNT , SH_ACS_SCOM_WO , + SH_FLD_DNFIFO_DATA_IN_PORT_LEN ); + +REG32_FLD( PU_FSB_DOWNFIFO_MTC_DNFIFO_MCT , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DNFIFO_MCT ); +REG32_FLD( PU_FSB_DOWNFIFO_MTC_DNFIFO_MCT_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DNFIFO_MCT_LEN ); + +REG64_FLD( PU_FSB_DOWNFIFO_REQ_RESET_DNFIFO_REQ_RESET , 0 , SH_UNT , SH_ACS_SCOM_WO , + SH_FLD_DNFIFO_REQ_RESET ); + +REG64_FLD( PU_FSB_DOWNFIFO_SIG_EOT_DNFIFO_SIGNAL , 0 , SH_UNT , SH_ACS_SCOM_WO , + SH_FLD_DNFIFO_SIGNAL ); + +REG32_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SBE , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_REQ_RESET_FR_SBE ); -REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SP , 7 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SP , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_REQ_RESET_FR_SP ); -REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_DEQUEUED_EOT_FLAG , 8 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_DEQUEUED_EOT_FLAG , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_DEQUEUED_EOT_FLAG ); -REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_FULL , 10 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_FULL , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_FULL ); -REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EMPTY , 11 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EMPTY , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_EMPTY ); -REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT , 12 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_ENTRY_COUNT ); -REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT_LEN , 4 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_ENTRY_COUNT_LEN ); -REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS , 16 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_VALID_FLAGS ); -REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS_LEN , 8 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_VALID_FLAGS_LEN ); -REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS , 24 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_EOT_FLAGS ); -REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS_LEN , 8 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_EOT_FLAGS_LEN ); -REG64_FLD( PU_FSB_UPFIFO_STATUS_REQ_RESET_FR_SP , 6 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_FSB_UPFIFO_ACK_EOT_UPFIFO_ACK , 0 , SH_UNT , SH_ACS_SCOM_WO , + SH_FLD_UPFIFO_ACK ); + +REG64_FLD( PU_FSB_UPFIFO_DATA_OUT_UPFIFO_DATA_OUT_PORT , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_UPFIFO_DATA_OUT_PORT ); +REG64_FLD( PU_FSB_UPFIFO_DATA_OUT_UPFIFO_DATA_OUT_PORT_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_UPFIFO_DATA_OUT_PORT_LEN ); + +REG64_FLD( PU_FSB_UPFIFO_RESET_UPFIFO_RESET , 0 , SH_UNT , SH_ACS_SCOM_WO , + SH_FLD_UPFIFO_RESET ); + +REG32_FLD( PU_FSB_UPFIFO_STATUS_REQ_RESET_FR_SP , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_REQ_RESET_FR_SP ); -REG64_FLD( PU_FSB_UPFIFO_STATUS_REQ_RESET_FR_SBE , 7 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_UPFIFO_STATUS_REQ_RESET_FR_SBE , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_REQ_RESET_FR_SBE ); -REG64_FLD( PU_FSB_UPFIFO_STATUS_DEQUEUED_EOT_FLAG , 8 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_UPFIFO_STATUS_DEQUEUED_EOT_FLAG , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_DEQUEUED_EOT_FLAG ); -REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_FULL , 10 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_UPFIFO_STATUS_FIFO_FULL , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_FULL ); -REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_EMPTY , 11 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_UPFIFO_STATUS_FIFO_EMPTY , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_EMPTY ); -REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT , 12 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_ENTRY_COUNT ); -REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT_LEN , 4 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_ENTRY_COUNT_LEN ); -REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS , 16 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_VALID_FLAGS ); -REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS_LEN , 8 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_VALID_FLAGS_LEN ); -REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS , 24 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_EOT_FLAGS ); -REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS_LEN , 8 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_EOT_FLAGS_LEN ); REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , @@ -44020,6 +45812,11 @@ REG64_FLD( PU_GPE0_GPEXIEDR_PPE_XIRAMEDR_EDR , 0 , SH_UN REG64_FLD( PU_GPE0_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PPE_XIRAMEDR_EDR_LEN ); +REG64_FLD( PU_GPE0_GPEXIIAR_IAR , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IAR ); +REG64_FLD( PU_GPE0_GPEXIIAR_IAR_LEN , 30 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IAR_LEN ); + REG64_FLD( PU_GPE0_GPEXIIR_PPE_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMGA_IR ); REG64_FLD( PU_GPE0_GPEXIIR_PPE_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , @@ -44035,14 +45832,52 @@ REG64_FLD( PU_GPE0_GPEXIXCR_PPE_XIXCR_XCR , 1 , SH_UN REG64_FLD( PU_GPE0_GPEXIXCR_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR_LEN ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE0_GPEXIXSR_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE0_GPEXIXSR_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE0_GPEXIXSR_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE0_GPEXIXSR_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_LP ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MCS_LEN ); REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_TAG_ADDR ); @@ -44050,6 +45885,12 @@ REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_DCACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_ERR ); +REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_POPULATE_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_POPULATE_PENDING ); +REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_VALID ); +REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_VALID_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_VALID_LEN ); REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR ); @@ -44057,12 +45898,24 @@ REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); +REG64_FLD( PU_GPE0_MIB_XIICAC_PIB_IFETCH_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PIB_IFETCH_PENDING ); REG64_FLD( PU_GPE0_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID ); REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID_LEN ); +REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_LINE2_VALID , 40 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID ); +REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_LINE2_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID_LEN ); +REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_LINE_PTR , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE_PTR ); +REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_LINE2_ERR , 46 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_ERR ); +REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_PREFETCH_PENDING , 47 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_PREFETCH_PENDING ); REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); @@ -44102,23 +45955,103 @@ REG64_FLD( PU_GPE0_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UN REG64_FLD( PU_GPE0_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE0_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE0_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE0_PPE_XIDBGPRO_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE0_PPE_XIDBGPRO_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); - +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_IAR , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IAR ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_IAR_LEN , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IAR_LEN ); + +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE0_PPE_XIRAMDBG_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE0_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE0_PPE_XIRAMDBG_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE0_PPE_XIRAMDBG_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM , @@ -44253,6 +46186,11 @@ REG64_FLD( PU_GPE1_GPEXIEDR_PPE_XIRAMEDR_EDR , 0 , SH_UN REG64_FLD( PU_GPE1_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PPE_XIRAMEDR_EDR_LEN ); +REG64_FLD( PU_GPE1_GPEXIIAR_IAR , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IAR ); +REG64_FLD( PU_GPE1_GPEXIIAR_IAR_LEN , 30 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IAR_LEN ); + REG64_FLD( PU_GPE1_GPEXIIR_PPE_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMGA_IR ); REG64_FLD( PU_GPE1_GPEXIIR_PPE_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , @@ -44268,14 +46206,52 @@ REG64_FLD( PU_GPE1_GPEXIXCR_PPE_XIXCR_XCR , 1 , SH_UN REG64_FLD( PU_GPE1_GPEXIXCR_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR_LEN ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE1_GPEXIXSR_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE1_GPEXIXSR_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE1_GPEXIXSR_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE1_GPEXIXSR_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_LP ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MCS_LEN ); REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_TAG_ADDR ); @@ -44283,6 +46259,12 @@ REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_DCACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_ERR ); +REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_POPULATE_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_POPULATE_PENDING ); +REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_VALID ); +REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_VALID_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_VALID_LEN ); REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR ); @@ -44290,12 +46272,24 @@ REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); +REG64_FLD( PU_GPE1_MIB_XIICAC_PIB_IFETCH_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PIB_IFETCH_PENDING ); REG64_FLD( PU_GPE1_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID ); REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID_LEN ); +REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_LINE2_VALID , 40 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID ); +REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_LINE2_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID_LEN ); +REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_LINE_PTR , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE_PTR ); +REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_LINE2_ERR , 46 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_ERR ); +REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_PREFETCH_PENDING , 47 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_PREFETCH_PENDING ); REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); @@ -44335,23 +46329,103 @@ REG64_FLD( PU_GPE1_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UN REG64_FLD( PU_GPE1_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE1_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE1_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE1_PPE_XIDBGPRO_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE1_PPE_XIDBGPRO_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); - +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_IAR , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IAR ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_IAR_LEN , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IAR_LEN ); + +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE1_PPE_XIRAMDBG_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE1_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE1_PPE_XIRAMDBG_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE1_PPE_XIRAMDBG_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM , @@ -44486,6 +46560,11 @@ REG64_FLD( PU_GPE2_GPEXIEDR_PPE_XIRAMEDR_EDR , 0 , SH_UN REG64_FLD( PU_GPE2_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PPE_XIRAMEDR_EDR_LEN ); +REG64_FLD( PU_GPE2_GPEXIIAR_IAR , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IAR ); +REG64_FLD( PU_GPE2_GPEXIIAR_IAR_LEN , 30 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IAR_LEN ); + REG64_FLD( PU_GPE2_GPEXIIR_PPE_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMGA_IR ); REG64_FLD( PU_GPE2_GPEXIIR_PPE_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , @@ -44501,14 +46580,52 @@ REG64_FLD( PU_GPE2_GPEXIXCR_PPE_XIXCR_XCR , 1 , SH_UN REG64_FLD( PU_GPE2_GPEXIXCR_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR_LEN ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE2_GPEXIXSR_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE2_GPEXIXSR_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE2_GPEXIXSR_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE2_GPEXIXSR_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_LP ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MCS_LEN ); REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_TAG_ADDR ); @@ -44516,6 +46633,12 @@ REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_DCACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_ERR ); +REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_POPULATE_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_POPULATE_PENDING ); +REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_VALID ); +REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_VALID_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_VALID_LEN ); REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR ); @@ -44523,12 +46646,24 @@ REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); +REG64_FLD( PU_GPE2_MIB_XIICAC_PIB_IFETCH_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PIB_IFETCH_PENDING ); REG64_FLD( PU_GPE2_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID ); REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID_LEN ); +REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_LINE2_VALID , 40 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID ); +REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_LINE2_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID_LEN ); +REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_LINE_PTR , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE_PTR ); +REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_LINE2_ERR , 46 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_ERR ); +REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_PREFETCH_PENDING , 47 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_PREFETCH_PENDING ); REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); @@ -44568,23 +46703,103 @@ REG64_FLD( PU_GPE2_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UN REG64_FLD( PU_GPE2_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE2_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE2_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE2_PPE_XIDBGPRO_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE2_PPE_XIDBGPRO_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); - +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_IAR , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IAR ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_IAR_LEN , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IAR_LEN ); + +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE2_PPE_XIRAMDBG_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE2_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE2_PPE_XIRAMDBG_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE2_PPE_XIRAMDBG_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM , @@ -44719,6 +46934,11 @@ REG64_FLD( PU_GPE3_GPEXIEDR_PPE_XIRAMEDR_EDR , 0 , SH_UN REG64_FLD( PU_GPE3_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PPE_XIRAMEDR_EDR_LEN ); +REG64_FLD( PU_GPE3_GPEXIIAR_IAR , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IAR ); +REG64_FLD( PU_GPE3_GPEXIIAR_IAR_LEN , 30 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IAR_LEN ); + REG64_FLD( PU_GPE3_GPEXIIR_PPE_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMGA_IR ); REG64_FLD( PU_GPE3_GPEXIIR_PPE_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , @@ -44734,14 +46954,52 @@ REG64_FLD( PU_GPE3_GPEXIXCR_PPE_XIXCR_XCR , 1 , SH_UN REG64_FLD( PU_GPE3_GPEXIXCR_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR_LEN ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE3_GPEXIXSR_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE3_GPEXIXSR_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE3_GPEXIXSR_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE3_GPEXIXSR_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_LP ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MCS_LEN ); REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_TAG_ADDR ); @@ -44749,6 +47007,12 @@ REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_DCACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_ERR ); +REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_POPULATE_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_POPULATE_PENDING ); +REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_VALID ); +REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_VALID_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_VALID_LEN ); REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR ); @@ -44756,12 +47020,24 @@ REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); +REG64_FLD( PU_GPE3_MIB_XIICAC_PIB_IFETCH_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PIB_IFETCH_PENDING ); REG64_FLD( PU_GPE3_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID ); REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID_LEN ); +REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_LINE2_VALID , 40 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID ); +REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_LINE2_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID_LEN ); +REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_LINE_PTR , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE_PTR ); +REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_LINE2_ERR , 46 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_ERR ); +REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_PREFETCH_PENDING , 47 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_PREFETCH_PENDING ); REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); @@ -44801,23 +47077,103 @@ REG64_FLD( PU_GPE3_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UN REG64_FLD( PU_GPE3_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE3_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE3_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE3_PPE_XIDBGPRO_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE3_PPE_XIDBGPRO_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); - +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_IAR , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IAR ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_IAR_LEN , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IAR_LEN ); + +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE3_PPE_XIRAMDBG_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE3_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE3_PPE_XIRAMDBG_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE3_PPE_XIRAMDBG_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM , @@ -44855,6 +47211,60 @@ REG64_FLD( PU_GPE3_PPE_XIXCR_XCR , 1 , SH_UN REG64_FLD( PU_GPE3_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XCR_LEN ); +REG64_FLD( PU_GPIO_INPUT_DIN_0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DIN_0 ); +REG64_FLD( PU_GPIO_INPUT_DIN_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DIN_1 ); +REG64_FLD( PU_GPIO_INPUT_DIN_2 , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DIN_2 ); + +REG64_FLD( PU_GPIO_INT_COND_INT_COND_0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_COND_0 ); +REG64_FLD( PU_GPIO_INT_COND_INT_COND_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_COND_1 ); +REG64_FLD( PU_GPIO_INT_COND_INT_COND_2 , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_COND_2 ); + +REG64_FLD( PU_GPIO_INT_ENABLE_INT_EN_0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_EN_0 ); +REG64_FLD( PU_GPIO_INT_ENABLE_INT_EN_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_EN_1 ); +REG64_FLD( PU_GPIO_INT_ENABLE_INT_EN_2 , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_EN_2 ); + +REG64_FLD( PU_GPIO_INT_POLARITY_INT_POL_0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_POL_0 ); +REG64_FLD( PU_GPIO_INT_POLARITY_INT_POL_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_POL_1 ); +REG64_FLD( PU_GPIO_INT_POLARITY_INT_POL_2 , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_POL_2 ); + +REG64_FLD( PU_GPIO_INT_STATUS_INT_STAT_0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_STAT_0 ); +REG64_FLD( PU_GPIO_INT_STATUS_INT_STAT_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_STAT_1 ); +REG64_FLD( PU_GPIO_INT_STATUS_INT_STAT_2 , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_STAT_2 ); + +REG64_FLD( PU_GPIO_MODE_NUM_GPIO_PORTS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_NUM_GPIO_PORTS ); +REG64_FLD( PU_GPIO_MODE_NUM_GPIO_PORTS_LEN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_NUM_GPIO_PORTS_LEN ); + +REG64_FLD( PU_GPIO_OUTPUT_DO_0 , 0 , SH_UNT , SH_ACS_SCOM2 , + SH_FLD_DO_0 ); +REG64_FLD( PU_GPIO_OUTPUT_DO_1 , 1 , SH_UNT , SH_ACS_SCOM2 , + SH_FLD_DO_1 ); +REG64_FLD( PU_GPIO_OUTPUT_DO_2 , 2 , SH_UNT , SH_ACS_SCOM2 , + SH_FLD_DO_2 ); + +REG64_FLD( PU_GPIO_OUTPUT_EN_DO_EN_0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DO_EN_0 ); +REG64_FLD( PU_GPIO_OUTPUT_EN_DO_EN_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DO_EN_1 ); +REG64_FLD( PU_GPIO_OUTPUT_EN_DO_EN_2 , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DO_EN_2 ); + REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , @@ -45863,6 +48273,26 @@ REG64_FLD( PU_HCA_COUNT_BAR_ADDR_LEN , 24 , SH_UN REG64_FLD( PU_HCA_COUNT_BAR_VALID , 63 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); +REG64_FLD( PU_HCA_DECAY1_DECAY_SCOM_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DECAY_SCOM_VALID ); +REG64_FLD( PU_HCA_DECAY1_DECAY_SCOM_COUNT , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DECAY_SCOM_COUNT ); +REG64_FLD( PU_HCA_DECAY1_DECAY_SCOM_COUNT_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DECAY_SCOM_COUNT_LEN ); + +REG64_FLD( PU_HCA_DECAY2_DECAY_SCOM_DELAY , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DECAY_SCOM_DELAY ); +REG64_FLD( PU_HCA_DECAY2_DECAY_SCOM_DELAY_LEN , 30 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DECAY_SCOM_DELAY_LEN ); +REG64_FLD( PU_HCA_DECAY2_DECAY_ADDR_COND , 30 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DECAY_ADDR_COND ); +REG64_FLD( PU_HCA_DECAY2_DECAY_ADDR_COND_LEN , 11 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DECAY_ADDR_COND_LEN ); +REG64_FLD( PU_HCA_DECAY2_DECAY_ADDR , 41 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DECAY_ADDR ); +REG64_FLD( PU_HCA_DECAY2_DECAY_ADDR_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DECAY_ADDR_LEN ); + REG64_FLD( PU_HCA_DROP_PIPE_COUNTER , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PIPE_COUNTER ); REG64_FLD( PU_HCA_DROP_PIPE_COUNTER_LEN , 16 , SH_UNT , SH_ACS_SCOM_RO , @@ -47882,12 +50312,18 @@ REG64_FLD( PU_INT_CQ_ERR_INFO1_TSIZE_4_6 , 4 , SH_UN SH_FLD_TSIZE_4_6 ); REG64_FLD( PU_INT_CQ_ERR_INFO1_TSIZE_4_6_LEN , 3 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_TSIZE_4_6_LEN ); -REG64_FLD( PU_INT_CQ_ERR_INFO1_RESERVED_7 , 7 , SH_UNT , SH_ACS_SCOM_WCLRPART, - SH_FLD_RESERVED_7 ); -REG64_FLD( PU_INT_CQ_ERR_INFO1_ADDRESS_8_63 , 8 , SH_UNT , SH_ACS_SCOM_WCLRPART, - SH_FLD_ADDRESS_8_63 ); -REG64_FLD( PU_INT_CQ_ERR_INFO1_ADDRESS_8_63_LEN , 56 , SH_UNT , SH_ACS_SCOM_WCLRPART, - SH_FLD_ADDRESS_8_63_LEN ); +REG64_FLD( PU_INT_CQ_ERR_INFO1_BAR_VEC_0_3 , 7 , SH_UNT , SH_ACS_SCOM_WCLRPART, + SH_FLD_BAR_VEC_0_3 ); +REG64_FLD( PU_INT_CQ_ERR_INFO1_BAR_VEC_0_3_LEN , 4 , SH_UNT , SH_ACS_SCOM_WCLRPART, + SH_FLD_BAR_VEC_0_3_LEN ); +REG64_FLD( PU_INT_CQ_ERR_INFO1_TTAG_0_16 , 11 , SH_UNT , SH_ACS_SCOM_WCLRPART, + SH_FLD_TTAG_0_16 ); +REG64_FLD( PU_INT_CQ_ERR_INFO1_TTAG_0_16_LEN , 17 , SH_UNT , SH_ACS_SCOM_WCLRPART, + SH_FLD_TTAG_0_16_LEN ); +REG64_FLD( PU_INT_CQ_ERR_INFO1_ADDRESS_28_63 , 28 , SH_UNT , SH_ACS_SCOM_WCLRPART, + SH_FLD_ADDRESS_28_63 ); +REG64_FLD( PU_INT_CQ_ERR_INFO1_ADDRESS_28_63_LEN , 36 , SH_UNT , SH_ACS_SCOM_WCLRPART, + SH_FLD_ADDRESS_28_63_LEN ); REG64_FLD( PU_INT_CQ_ERR_INFO2_INFO_CAPTURED , 0 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_INFO_CAPTURED ); @@ -47936,132 +50372,132 @@ REG64_FLD( PU_INT_CQ_ERR_RPT_HOLD_HOLD_0_48 , 0 , SH_UN REG64_FLD( PU_INT_CQ_ERR_RPT_HOLD_HOLD_0_48_LEN , 49 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_0_48_LEN ); -REG64_FLD( PU_INT_CQ_FIR_PI_ECC_CE , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PI_ECC_CE , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PI_ECC_CE ); -REG64_FLD( PU_INT_CQ_FIR_PI_ECC_UE , 1 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PI_ECC_UE , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PI_ECC_UE ); -REG64_FLD( PU_INT_CQ_FIR_PI_ECC_SUE , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PI_ECC_SUE , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PI_ECC_SUE ); -REG64_FLD( PU_INT_CQ_FIR_ST_ECC_CE , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_ST_ECC_CE , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ST_ECC_CE ); -REG64_FLD( PU_INT_CQ_FIR_ST_ECC_UE , 4 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_ST_ECC_UE , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ST_ECC_UE ); -REG64_FLD( PU_INT_CQ_FIR_LD_ECC_CE , 5 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_LD_ECC_CE , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_LD_ECC_CE ); -REG64_FLD( PU_INT_CQ_FIR_LD_ECC_UE , 6 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_LD_ECC_UE , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_LD_ECC_UE ); -REG64_FLD( PU_INT_CQ_FIR_CL_ECC_CE , 7 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_CL_ECC_CE , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CL_ECC_CE ); -REG64_FLD( PU_INT_CQ_FIR_CL_ECC_UE , 8 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_CL_ECC_UE , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CL_ECC_UE ); -REG64_FLD( PU_INT_CQ_FIR_WR_ECC_CE , 9 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_WR_ECC_CE , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WR_ECC_CE ); -REG64_FLD( PU_INT_CQ_FIR_WR_ECC_UE , 10 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_WR_ECC_UE , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WR_ECC_UE ); -REG64_FLD( PU_INT_CQ_FIR_RD_ECC_CE , 11 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_RD_ECC_CE , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RD_ECC_CE ); -REG64_FLD( PU_INT_CQ_FIR_RD_ECC_UE , 12 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_RD_ECC_UE , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RD_ECC_UE ); -REG64_FLD( PU_INT_CQ_FIR_AI_ECC_CE , 13 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_AI_ECC_CE , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AI_ECC_CE ); -REG64_FLD( PU_INT_CQ_FIR_AI_ECC_UE , 14 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_AI_ECC_UE , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AI_ECC_UE ); -REG64_FLD( PU_INT_CQ_FIR_AIB_IN_CMD_CTL_PERR , 15 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_AIB_IN_CMD_CTL_PERR , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AIB_IN_CMD_CTL_PERR ); -REG64_FLD( PU_INT_CQ_FIR_AIB_IN_CMD_PERR , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_AIB_IN_CMD_PERR , 16 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AIB_IN_CMD_PERR ); -REG64_FLD( PU_INT_CQ_FIR_AIB_IN_DAT_CTL_PERR , 17 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_AIB_IN_DAT_CTL_PERR , 17 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AIB_IN_DAT_CTL_PERR ); -REG64_FLD( PU_INT_CQ_FIR_PB_PARITY_ERROR , 18 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PB_PARITY_ERROR , 18 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_PARITY_ERROR ); -REG64_FLD( PU_INT_CQ_FIR_PB_RCMDX_CI_ERR1 , 19 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PB_RCMDX_CI_ERR1 , 19 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_RCMDX_CI_ERR1 ); -REG64_FLD( PU_INT_CQ_FIR_PB_RCMDX_CI_ERR2 , 20 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PB_RCMDX_CI_ERR2 , 20 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_RCMDX_CI_ERR2 ); -REG64_FLD( PU_INT_CQ_FIR_PB_RCMDX_CI_ERR3 , 21 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PB_RCMDX_CI_ERR3 , 21 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_RCMDX_CI_ERR3 ); -REG64_FLD( PU_INT_CQ_FIR_RCVD_POISONED_CIST_DATA , 22 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_RCVD_POISONED_CIST_DATA , 22 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RCVD_POISONED_CIST_DATA ); -REG64_FLD( PU_INT_CQ_FIR_MRT_ERR_NOT_VALID , 23 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_MRT_ERR_NOT_VALID , 23 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MRT_ERR_NOT_VALID ); -REG64_FLD( PU_INT_CQ_FIR_MRT_ERR_PSIZE , 24 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_MRT_ERR_PSIZE , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MRT_ERR_PSIZE ); -REG64_FLD( PU_INT_CQ_FIR_SCOM_S_ERR , 25 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_SCOM_S_ERR , 25 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_S_ERR ); -REG64_FLD( PU_INT_CQ_FIR_TCTXT_PRESP_ERROR , 26 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_TCTXT_PRESP_ERROR , 26 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_TCTXT_PRESP_ERROR ); -REG64_FLD( PU_INT_CQ_FIR_WRQ_OP_HANG , 27 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_WRQ_OP_HANG , 27 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WRQ_OP_HANG ); -REG64_FLD( PU_INT_CQ_FIR_RDQ_OP_HANG , 28 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_RDQ_OP_HANG , 28 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RDQ_OP_HANG ); -REG64_FLD( PU_INT_CQ_FIR_INTQ_OP_HANG , 29 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_INTQ_OP_HANG , 29 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTQ_OP_HANG ); -REG64_FLD( PU_INT_CQ_FIR_RDQ_DATA_HANG , 30 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_RDQ_DATA_HANG , 30 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RDQ_DATA_HANG ); -REG64_FLD( PU_INT_CQ_FIR_STQ_DATA_HANG , 31 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_STQ_DATA_HANG , 31 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_STQ_DATA_HANG ); -REG64_FLD( PU_INT_CQ_FIR_LDQ_DATA_HANG , 32 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_LDQ_DATA_HANG , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_LDQ_DATA_HANG ); -REG64_FLD( PU_INT_CQ_FIR_WRQ_BAD_CRESP , 33 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_WRQ_BAD_CRESP , 33 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WRQ_BAD_CRESP ); -REG64_FLD( PU_INT_CQ_FIR_RDQ_BAD_CRESP , 34 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_RDQ_BAD_CRESP , 34 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RDQ_BAD_CRESP ); -REG64_FLD( PU_INT_CQ_FIR_INTQ_BAD_CRESP , 35 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_INTQ_BAD_CRESP , 35 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTQ_BAD_CRESP ); -REG64_FLD( PU_INT_CQ_FIR_BAD_128K_VP_OP , 36 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_BAD_128K_VP_OP , 36 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BAD_128K_VP_OP ); -REG64_FLD( PU_INT_CQ_FIR_RDQ_ABORT_OP , 37 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_RDQ_ABORT_OP , 37 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RDQ_ABORT_OP ); -REG64_FLD( PU_INT_CQ_FIR_PC_CRD_PERR , 38 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PC_CRD_PERR , 38 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PC_CRD_PERR ); -REG64_FLD( PU_INT_CQ_FIR_PC_CRD_AVAIL_PERR , 39 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PC_CRD_AVAIL_PERR , 39 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PC_CRD_AVAIL_PERR ); -REG64_FLD( PU_INT_CQ_FIR_VC_CRD_PERR , 40 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_VC_CRD_PERR , 40 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_VC_CRD_PERR ); -REG64_FLD( PU_INT_CQ_FIR_VC_CRD_AVAIL_PERR , 41 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_VC_CRD_AVAIL_PERR , 41 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_VC_CRD_AVAIL_PERR ); -REG64_FLD( PU_INT_CQ_FIR_CMD_QX_SEVERE_ERR , 42 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_CMD_QX_SEVERE_ERR , 42 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CMD_QX_SEVERE_ERR ); -REG64_FLD( PU_INT_CQ_FIR_RDQ_ABORT_TRM , 43 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_RDQ_ABORT_TRM , 43 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RDQ_ABORT_TRM ); -REG64_FLD( PU_INT_CQ_FIR_UNSOLICITED_CRESP , 44 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_UNSOLICITED_CRESP , 44 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UNSOLICITED_CRESP ); -REG64_FLD( PU_INT_CQ_FIR_UNSOLICITED_PBDATA , 45 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_UNSOLICITED_PBDATA , 45 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UNSOLICITED_PBDATA ); -REG64_FLD( PU_INT_CQ_FIR_FIR_PARITY_ERR , 46 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_FIR_PARITY_ERR , 46 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FIR_PARITY_ERR ); -REG64_FLD( PU_INT_CQ_FIR_RESERVED_47 , 47 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_47 ); -REG64_FLD( PU_INT_CQ_FIR_RESERVED_48 , 48 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PGM_DBG_ACCESS , 47 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PGM_DBG_ACCESS ); +REG64_FLD( PU_INT_CQ_FIR_RESERVED_48 , 48 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_48 ); -REG64_FLD( PU_INT_CQ_FIR_PC_FATAL_ERROR_0_2 , 49 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PC_FATAL_ERROR_0_2 , 49 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PC_FATAL_ERROR_0_2 ); -REG64_FLD( PU_INT_CQ_FIR_PC_FATAL_ERROR_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PC_FATAL_ERROR_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PC_FATAL_ERROR_0_2_LEN ); -REG64_FLD( PU_INT_CQ_FIR_PC_RECOV_ERROR_0_2 , 52 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PC_RECOV_ERROR_0_2 , 52 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PC_RECOV_ERROR_0_2 ); -REG64_FLD( PU_INT_CQ_FIR_PC_RECOV_ERROR_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PC_RECOV_ERROR_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PC_RECOV_ERROR_0_2_LEN ); -REG64_FLD( PU_INT_CQ_FIR_PC_INFO_ERROR_0_2 , 55 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PC_INFO_ERROR_0_2 , 55 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PC_INFO_ERROR_0_2 ); -REG64_FLD( PU_INT_CQ_FIR_PC_INFO_ERROR_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PC_INFO_ERROR_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PC_INFO_ERROR_0_2_LEN ); -REG64_FLD( PU_INT_CQ_FIR_VC_FATAL_ERROR_0_1 , 58 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_VC_FATAL_ERROR_0_1 , 58 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_VC_FATAL_ERROR_0_1 ); -REG64_FLD( PU_INT_CQ_FIR_VC_FATAL_ERROR_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_VC_FATAL_ERROR_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_VC_FATAL_ERROR_0_1_LEN ); -REG64_FLD( PU_INT_CQ_FIR_VC_RECOV_ERROR_0_1 , 60 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_VC_RECOV_ERROR_0_1 , 60 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_VC_RECOV_ERROR_0_1 ); -REG64_FLD( PU_INT_CQ_FIR_VC_RECOV_ERROR_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_VC_RECOV_ERROR_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_VC_RECOV_ERROR_0_1_LEN ); -REG64_FLD( PU_INT_CQ_FIR_VC_INFO_ERROR_0_1 , 62 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_VC_INFO_ERROR_0_1 , 62 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_VC_INFO_ERROR_0_1 ); -REG64_FLD( PU_INT_CQ_FIR_VC_INFO_ERROR_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_VC_INFO_ERROR_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_VC_INFO_ERROR_0_1_LEN ); -REG64_FLD( PU_INT_CQ_FIRMASK_FIR_MASK , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIRMASK_FIR_MASK , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FIR_MASK ); -REG64_FLD( PU_INT_CQ_FIRMASK_FIR_MASK_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIRMASK_FIR_MASK_LEN , 64 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FIR_MASK_LEN ); REG64_FLD( PU_INT_CQ_IC_BAR_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , @@ -48362,6 +50798,11 @@ REG64_FLD( PU_INT_CQ_VC_BARM_ADDR_21_37 , 21 , SH_UN REG64_FLD( PU_INT_CQ_VC_BARM_ADDR_21_37_LEN , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_21_37_LEN ); +REG64_FLD( PU_INT_CQ_WOF_WOF , 0 , SH_UNT , SH_ACS_SCOM_WCLRPART, + SH_FLD_WOF ); +REG64_FLD( PU_INT_CQ_WOF_WOF_LEN , 64 , SH_UNT , SH_ACS_SCOM_WCLRPART, + SH_FLD_WOF_LEN ); + REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_VLD ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , @@ -48973,10 +51414,47 @@ REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_30_31 , 30 , SH_UN REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_30_31_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_30_31_LEN ); -REG64_FLD( PU_INT_PC_DBG_PMC_RESERVED_0_15 , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_0_15 ); -REG64_FLD( PU_INT_PC_DBG_PMC_RESERVED_0_15_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_0_15_LEN ); +REG64_FLD( PU_INT_PC_DBG_INT_DBG_VLD , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DBG_VLD ); +REG64_FLD( PU_INT_PC_DBG_INT_RESERVED_1_3 , 1 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_1_3 ); +REG64_FLD( PU_INT_PC_DBG_INT_RESERVED_1_3_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_1_3_LEN ); +REG64_FLD( PU_INT_PC_DBG_INT_DBG_LEVEL , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DBG_LEVEL ); +REG64_FLD( PU_INT_PC_DBG_INT_DBG_LEVEL_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DBG_LEVEL_LEN ); +REG64_FLD( PU_INT_PC_DBG_INT_RESERVED_7_8 , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_7_8 ); +REG64_FLD( PU_INT_PC_DBG_INT_RESERVED_7_8_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_7_8_LEN ); +REG64_FLD( PU_INT_PC_DBG_INT_DBG_THRDID , 9 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DBG_THRDID ); +REG64_FLD( PU_INT_PC_DBG_INT_DBG_THRDID_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DBG_THRDID_LEN ); +REG64_FLD( PU_INT_PC_DBG_INT_RESERVED_16 , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_16 ); +REG64_FLD( PU_INT_PC_DBG_INT_DBG_THRDID_MASK , 17 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DBG_THRDID_MASK ); +REG64_FLD( PU_INT_PC_DBG_INT_DBG_THRDID_MASK_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DBG_THRDID_MASK_LEN ); + +REG64_FLD( PU_INT_PC_DBG_PMC_EN_ARX , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EN_ARX ); +REG64_FLD( PU_INT_PC_DBG_PMC_EN_ARX_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EN_ARX_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_EN_CRESP , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EN_CRESP ); +REG64_FLD( PU_INT_PC_DBG_PMC_EN_CRESP_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EN_CRESP_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_EN_CMD , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EN_CMD ); +REG64_FLD( PU_INT_PC_DBG_PMC_EN_CMD_LEN , 10 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EN_CMD_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_RESERVED_14_15 , 14 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_14_15 ); +REG64_FLD( PU_INT_PC_DBG_PMC_RESERVED_14_15_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_14_15_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R0 ); @@ -50090,12 +52568,12 @@ REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_22 , 22 , SH_UN REG64_FLD( PU_INT_TCTXT_CFG_CFG_BLOCK_GROUP_EN , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_BLOCK_GROUP_EN ); -REG64_FLD( PU_INT_TCTXT_CFG_CFG_ACM_EN , 1 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_TCTXT_CFG_CFG_TARGET_EN , 1 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_TARGET_EN ); +REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_2 , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_2 ); +REG64_FLD( PU_INT_TCTXT_CFG_CFG_ACM_EN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_ACM_EN ); -REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_2_3 , 2 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_2_3 ); -REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_2_3_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_2_3_LEN ); REG64_FLD( PU_INT_TCTXT_CFG_CFG_FUSE_CORE_EN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_FUSE_CORE_EN ); REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_5 , 5 , SH_UNT , SH_ACS_SCOM_RW , @@ -50209,14 +52687,18 @@ REG64_FLD( PU_INT_TCTXT_INDIR3_INDIR_THRDID_LEN , 7 , SH_UN REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_EN , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_BLOCK_EN ); -REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_VPD_EN , 1 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_BLOCK_VPD_EN ); -REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_RCMD_FILTER_EN , 2 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_BLOCK_RCMD_FILTER_EN ); -REG64_FLD( PU_INT_TCTXT_TRACK_RESERVED_3_9 , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_3_9 ); -REG64_FLD( PU_INT_TCTXT_TRACK_RESERVED_3_9_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_3_9_LEN ); +REG64_FLD( PU_INT_TCTXT_TRACK_RESERVED_1_3 , 1 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_1_3 ); +REG64_FLD( PU_INT_TCTXT_TRACK_RESERVED_1_3_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_1_3_LEN ); +REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_FILTER_EN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_BLOCK_FILTER_EN ); +REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_FILTER_VPC_EN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_BLOCK_FILTER_VPC_EN ); +REG64_FLD( PU_INT_TCTXT_TRACK_RESERVED_6_9 , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_6_9 ); +REG64_FLD( PU_INT_TCTXT_TRACK_RESERVED_6_9_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_6_9_LEN ); REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_RESET_DELAY , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_BLOCK_RESET_DELAY ); REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_RESET_DELAY_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , @@ -50295,14 +52777,14 @@ REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_EOI , 56 , SH_UN REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_EOI_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SBC_EOI_LEN ); -REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RESERVED_20_21 , 20 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_20_21 ); -REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RESERVED_20_21_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_20_21_LEN ); -REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RELAXED_WR , 22 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RELAXED_WR ); -REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_DISABLE_PTAG_IN_AIBTAG , 23 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_DISABLE_PTAG_IN_AIBTAG ); +REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RESERVED_20 , 20 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_20 ); +REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RELAXED_WR_EQP , 21 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RELAXED_WR_EQP ); +REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RELAXED_WR_DMA , 22 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RELAXED_WR_DMA ); +REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_DISABLE_IDX_IN_AIBTAG , 23 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_IDX_IN_AIBTAG ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_ESBE , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQC_EOI_ESBE ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_ESBE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , @@ -50829,26 +53311,26 @@ REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQP , 4 , SH_UN SH_FLD_CNT_EQP ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQP_LEN ); -REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_WAKEUP , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CNT_WAKEUP ); -REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_WAKEUP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CNT_WAKEUP_LEN ); -REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LS , 12 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CNT_LS ); -REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LS_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CNT_LS_LEN ); +REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_RESUME , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RESUME ); +REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_RESUME_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RESUME_LEN ); +REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EBB , 12 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_EBB ); +REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EBB_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_EBB_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_VP , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VP ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_VP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VP_LEN ); -REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_GROUP , 20 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CNT_GROUP ); -REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_GROUP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CNT_GROUP_LEN ); -REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_BROADCAST , 24 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CNT_BROADCAST ); -REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_BROADCAST_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CNT_BROADCAST_LEN ); +REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LS , 20 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_LS ); +REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LS_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_LS_LEN ); +REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_BROADCAST_BL , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_BROADCAST_BL ); +REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_BROADCAST_BL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_BROADCAST_BL_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQ_FWD , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQ_FWD ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQ_FWD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , @@ -52122,14 +54604,14 @@ REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_IVVC_RESP , 4 , SH_UN SH_FLD_CNT_IVVC_RESP ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_IVVC_RESP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_IVVC_RESP_LEN ); -REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_WRITE , 8 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_RESERVED_8_11 , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_8_11 ); +REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_RESERVED_8_11_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_8_11_LEN ); +REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_WRITE , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_ISB_WRITE ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_WRITE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_ISB_WRITE_LEN ); -REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_RESERVED_12_15 , 12 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_12_15 ); -REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_RESERVED_12_15_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_ISB_FETCH_REPLAY , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_ISB_FETCH_REPLAY ); @@ -52219,20 +54701,208 @@ REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_ADDRESS , 27 , SH_UN REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_ADDRESS_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS_LEN ); -REG64_FLD( PU_INT_VC_WOF_ERR_G0_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, - SH_FLD_ERROR ); -REG64_FLD( PU_INT_VC_WOF_ERR_G0_ERROR_LEN , 55 , SH_UNT , SH_ACS_SCOM_CLRPART, - SH_FLD_ERROR_LEN ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_INVALID_STATE , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_INVALID_STATE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_CRD_ERROR , 1 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_CRD_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_OFFSET_ERROR , 2 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_OFFSET_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_DATA_ERROR , 3 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_DATA_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_ACCESS_ERROR , 4 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_ACCESS_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_OVERFLOW , 5 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_OVERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_IDX_ERROR , 6 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_IDX_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_UNDERFLOW , 7 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_UNDERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_DIR_STATE_ERROR , 8 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_DIR_STATE_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_DIR_WR_ERROR , 9 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_DIR_WR_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_DIR_RD_ERROR , 10 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_DIR_RD_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_ECC_UE , 11 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_EQC_CREDIT_ERROR , 12 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_EQC_CREDIT_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_TRIG_CRD_ERROR , 13 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_TRIG_CRD_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_EFIFO_DIN_ERROR , 14 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_EFIFO_DIN_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_INPUT_BUF_ERROR , 15 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_INPUT_BUF_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_EQ_ERROR , 16 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_EQ_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_PQ_ERROR , 17 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_PQ_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_EQPQ_ERROR , 18 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_EQPQ_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_ECC_CE , 19 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_ECC_CE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ARX_CTRL_PTY_ERROR , 20 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ARX_CTRL_PTY_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ARX_CMD_PTY_ERROR , 21 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ARX_CMD_PTY_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_REGS_SCOM_INTERNAL_ERROR , 22 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_REGS_SCOM_INTERNAL_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ARX_TAG_SRAM_ECC_UE , 23 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ARX_TAG_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ARX_AIB_DATA_ECC_UE , 24 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ARX_AIB_DATA_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_REGS_PARITY_ERROR , 25 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_REGS_PARITY_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_REGS_CMD_CRD_ERROR , 26 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_REGS_CMD_CRD_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_REGS_DATA_CRD_ERROR , 27 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_REGS_DATA_CRD_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ARX_AIB_CMD_ERROR , 28 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ARX_AIB_CMD_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ARX_AIB_RESP_TIMEOUT , 29 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ARX_AIB_RESP_TIMEOUT ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ARX_AIB_DATA_ECC_CE , 30 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ARX_AIB_DATA_ECC_CE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ARX_TAG_SRAM_ECC_CE , 31 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ARX_TAG_SRAM_ECC_CE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_LACK_OF_TAG , 32 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_LACK_OF_TAG ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_TAG_RELEASE_ERROR , 33 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_TAG_RELEASE_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_AT_BAD_CAM_STATE , 34 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_AT_BAD_CAM_STATE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_AT_MULTIPLE_HIT , 35 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_AT_MULTIPLE_HIT ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_AT_PARITY_ERROR , 36 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_AT_PARITY_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_AT_MULTIPLE_PRF_RQ , 37 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_AT_MULTIPLE_PRF_RQ ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_AT_TOO_LARGE_SLOTID , 38 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_AT_TOO_LARGE_SLOTID ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_AT_PRF_OVERFLOW , 39 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_AT_PRF_OVERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_AT_PRF_UNDERFLOW , 40 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_AT_PRF_UNDERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_AT_INVALID_CMD , 41 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_AT_INVALID_CMD ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_AT_INVALID_IND_BAR , 42 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_AT_INVALID_IND_BAR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_AT_INVALID_IND_PZ , 43 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_AT_INVALID_IND_PZ ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_AT_INVALID_I , 44 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_AT_INVALID_I ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_CRD_PARITY_ERROR , 45 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_CRD_PARITY_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_AT_SRAM_ECC_UE , 46 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_AT_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_BAR_SRAM_ECC_UE , 47 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_BAR_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_WB_SRAM_ECC_UE , 48 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_WB_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_SLOT_OVERFLOW , 49 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_SLOT_OVERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_CRD_OVERFLOW , 50 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_CRD_OVERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_CRD_UNDERFLOW , 51 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_CRD_UNDERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_INVALID_BAR , 52 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_INVALID_BAR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_PAGE_OVERFLOW , 53 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_PAGE_OVERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_SRAM_ECC_CE , 54 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_SRAM_ECC_CE ); REG64_FLD( PU_INT_VC_WOF_ERR_G0_DETAIL_ERROR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ERROR ); REG64_FLD( PU_INT_VC_WOF_ERR_G0_DETAIL_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ERROR_LEN ); -REG64_FLD( PU_INT_VC_WOF_ERR_G1_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, - SH_FLD_ERROR ); -REG64_FLD( PU_INT_VC_WOF_ERR_G1_ERROR_LEN , 43 , SH_UNT , SH_ACS_SCOM_CLRPART, - SH_FLD_ERROR_LEN ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_CL_INDEX_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_CL_INDEX_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_CRD_OR_RESP_ERROR , 1 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_CRD_OR_RESP_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_PTAG_ASSIGN_ERROR , 2 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_PTAG_ASSIGN_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_PTAG_RELEASE_ERROR , 3 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_PTAG_RELEASE_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_REPLAY_ERROR , 4 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_REPLAY_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_PARITY_ERROR , 5 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_PARITY_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_TAG_SRAM_ECC_UE , 6 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_TAG_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_STATE_SRAM_ECC_UE , 7 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_STATE_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_DATA_SRAM_ECC_UE , 8 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_DATA_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_CTRL_SRAM_ECC_UE , 9 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_CTRL_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_ARX_DATA_ECC_UE , 10 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_ARX_DATA_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_UNLOCK_FIFO_OVERFLOW , 11 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_UNLOCK_FIFO_OVERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_EOI_OVERFLOW , 12 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_EOI_OVERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_EOI_TAG_ERROR , 13 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_EOI_TAG_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_SRAM_ECC_CE , 14 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_SRAM_ECC_CE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_PROCESSING_ERROR , 15 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_PROCESSING_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_WATCH_ERROR , 16 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_WATCH_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_CONFIG_ERROR , 17 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_CONFIG_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_IVC_AIB_RESP_ERROR , 18 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IVC_AIB_RESP_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_IVC_PTAG_ASSIGN_ERROR , 19 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IVC_PTAG_ASSIGN_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_IVC_PTAG_RELEASE_ERROR , 20 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IVC_PTAG_RELEASE_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_IVC_REPLAY_ERROR , 21 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IVC_REPLAY_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_IVC_PARITY_ERROR , 22 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IVC_PARITY_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_IVC_TAG_SRAM_ECC_UE , 23 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IVC_TAG_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_IVC_STATE_SRAM_ECC_UE , 24 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IVC_STATE_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_IVC_DATA_SRAM_ECC_UE , 25 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IVC_DATA_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_IVC_UNLOCK_FIFO_OVERFLOW , 26 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IVC_UNLOCK_FIFO_OVERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_IVC_SRAM_ECC_CE , 27 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IVC_SRAM_ECC_CE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_IVC_PROCESSING_ERROR , 28 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IVC_PROCESSING_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_CL_INDEX_ERROR , 29 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_CL_INDEX_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_CRD_OR_RESP_ERROR , 30 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_CRD_OR_RESP_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_PTAG_ASSIGN_ERROR , 31 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_PTAG_ASSIGN_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_PTAG_RELEASE_ERROR , 32 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_PTAG_RELEASE_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_REPLAY_ERROR , 33 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_REPLAY_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_PARITY_ERROR , 34 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_PARITY_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_TAG_SRAM_ECC_UE , 35 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_TAG_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_STATE_SRAM_ECC_UE , 36 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_STATE_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_DATA_SRAM_ECC_UE , 37 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_DATA_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_UNLOCK_FIFO_OVERFLOW , 38 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_UNLOCK_FIFO_OVERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_EOI_OVERFLOW , 39 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_EOI_OVERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_EOI_TAG_ERROR , 40 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_EOI_TAG_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_SRAM_ECC_CE , 41 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_SRAM_ECC_CE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_PROCESSING_ERROR , 42 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_PROCESSING_ERROR ); REG64_FLD( PU_INT_VC_WOF_ERR_G1_DETAIL_ERROR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ERROR ); @@ -52369,6 +55039,86 @@ REG64_FLD( PU_NPU_CTL_LCO_CONFIG_RAND_EVENT , 16 , SH_UN REG64_FLD( PU_NPU_CTL_LCO_CONFIG_RAND_EVENT_LEN , 4 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_RAND_EVENT_LEN ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA0_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA0_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA1_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA1_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA10_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA10_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA11_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA11_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA12_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA12_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA13_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA13_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA14_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA14_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA15_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA15_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA2_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA2_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA3_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA3_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA4_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA4_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA5_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA5_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA6_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA6_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA7_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA7_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA8_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA8_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA9_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA9_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + REG64_FLD( CAPP_LINK_DELAY_TIMER_VALUE , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_VALUE ); REG64_FLD( CAPP_LINK_DELAY_TIMER_VALUE_LEN , 29 , SH_UNT_CAPP , SH_ACS_SCOM , @@ -53162,6 +55912,135 @@ REG64_FLD( PU_LPC_STATUS_REG_VALID , 10 , SH_UN REG64_FLD( PU_LPC_STATUS_REG_ACK , 11 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ACK ); +REG64_FLD( PHB_MASK_REG_AIB_COMMAND_INVALID , 0 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_AIB_COMMAND_INVALID ); +REG64_FLD( PHB_MASK_REG_AIB_ADDRESSING_ERROR , 1 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_AIB_ADDRESSING_ERROR ); +REG64_FLD( PHB_MASK_REG_AIB_ACCESS_ERROR , 2 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_AIB_ACCESS_ERROR ); +REG64_FLD( PHB_MASK_REG_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED , 3 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED ); +REG64_FLD( PHB_MASK_REG_AIB_FATAL_CLASS_ERROR , 4 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_AIB_FATAL_CLASS_ERROR ); +REG64_FLD( PHB_MASK_REG_AIB_INF_CLASS_ERROR , 5 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_AIB_INF_CLASS_ERROR ); +REG64_FLD( PHB_MASK_REG_PE_STOP_STATE_ERROR , 6 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_PE_STOP_STATE_ERROR ); +REG64_FLD( PHB_MASK_REG_AIB_DAT_ERR_SIGNALED , 7 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_AIB_DAT_ERR_SIGNALED ); +REG64_FLD( PHB_MASK_REG_OUT_COMMON_ARRAY_FATAL_ERROR , 8 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_OUT_COMMON_ARRAY_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_OUT_COMMON_LATCH_FATAL_ERROR , 9 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_OUT_COMMON_LATCH_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_OUT_COMMON_LOGIC_FATAL_ERROR , 10 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_OUT_COMMON_LOGIC_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_BLIF_OUT_INTERFACE_PARITY_ERROR , 11 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_BLIF_OUT_INTERFACE_PARITY_ERROR ); +REG64_FLD( PHB_MASK_REG_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE , 12 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE ); +REG64_FLD( PHB_MASK_REG_MMIO_REQUEST_TIMEOUT , 13 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MMIO_REQUEST_TIMEOUT ); +REG64_FLD( PHB_MASK_REG_OUT_RRB_SOURCED_ERROR , 14 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_OUT_RRB_SOURCED_ERROR ); +REG64_FLD( PHB_MASK_REG_CFG_LOGIC_SIGNALED_ERROR , 15 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_CFG_LOGIC_SIGNALED_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_REG_REQUEST_ADDRESS_ERROR , 16 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_REG_REQUEST_ADDRESS_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_FDA_FATAL_ERROR , 17 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_FDA_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_FDA_INF_ERROR , 18 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_FDA_INF_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_FDB_FATAL_ERROR , 19 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_FDB_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_FDB_INF_ERROR , 20 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_FDB_INF_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_ERR_FATAL_ERROR , 21 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_ERR_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_ERR_INF_ERROR , 22 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_ERR_INF_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_DBG_FATAL_ERROR , 23 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_DBG_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_DBG_INF_ERROR , 24 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_DBG_INF_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_PCIE_REQUEST_ACCESS_ERROR , 25 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_PCIE_REQUEST_ACCESS_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_BUS_LOGIC_ERROR , 26 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_BUS_LOGIC_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_UVI_FATAL_ERROR , 27 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_UVI_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_UVI_INF_ERROR , 28 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_UVI_INF_ERROR ); +REG64_FLD( PHB_MASK_REG_SCOM_FATAL_ERROR , 29 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_SCOM_INF_ERROR , 30 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_INF_ERROR ); +REG64_FLD( PHB_MASK_REG_PCIE_MACRO_ERROR_ACTIVE_STATUS , 31 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_PCIE_MACRO_ERROR_ACTIVE_STATUS ); +REG64_FLD( PHB_MASK_REG_ARB_IODA_FATAL_ERROR , 32 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_IODA_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_ARB_MSI_PE_MATCH_ERROR , 33 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_MSI_PE_MATCH_ERROR ); +REG64_FLD( PHB_MASK_REG_ARB_MSI_ADDRESS_ERROR , 34 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_MSI_ADDRESS_ERROR ); +REG64_FLD( PHB_MASK_REG_ARB_TVT_ERROR , 35 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_TVT_ERROR ); +REG64_FLD( PHB_MASK_REG_ARB_RCVD_FATAL_ERROR_MSG , 36 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_RCVD_FATAL_ERROR_MSG ); +REG64_FLD( PHB_MASK_REG_ARB_RCVD_NONFATAL_ERROR_MSG , 37 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_RCVD_NONFATAL_ERROR_MSG ); +REG64_FLD( PHB_MASK_REG_ARB_RCVD_CORRECTIBLE_ERROR_MSG , 38 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_RCVD_CORRECTIBLE_ERROR_MSG ); +REG64_FLD( PHB_MASK_REG_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED , 39 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED ); +REG64_FLD( PHB_MASK_REG_ARB_COMMON_FATAL_ERROR , 40 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_COMMON_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_ARB_TABLE_BAR_DISABLED_ERROR , 41 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_TABLE_BAR_DISABLED_ERROR ); +REG64_FLD( PHB_MASK_REG_ARB_BLIF_COMPLETION_ERROR , 42 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_BLIF_COMPLETION_ERROR ); +REG64_FLD( PHB_MASK_REG_ARB_PCT_TIMEOUT_ERROR , 43 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_PCT_TIMEOUT_ERROR ); +REG64_FLD( PHB_MASK_REG_ARB_ECC_CORRECTABLE_ERROR , 44 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_MASK_REG_ARB_ECC_UNCORRECTABLE_ERROR , 45 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_MASK_REG_ARB_TLP_POISON_SIGNALED , 46 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_TLP_POISON_SIGNALED ); +REG64_FLD( PHB_MASK_REG_ARB_RTT_PENUM_INVALID_ERROR , 47 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_RTT_PENUM_INVALID_ERROR ); +REG64_FLD( PHB_MASK_REG_MRG_COMMON_FATAL_ERROR , 48 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_COMMON_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_MRG_TABLE_BAR_DISABLED_ERROR , 49 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_TABLE_BAR_DISABLED_ERROR ); +REG64_FLD( PHB_MASK_REG_MRG_ECC_CORRECTABLE_ERROR , 50 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_MASK_REG_MRG_ECC_UNCORRECTABLE_ERROR , 51 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_MASK_REG_MRG_AIB2_TX_TIMEOUT_ERROR , 52 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_AIB2_TX_TIMEOUT_ERROR ); +REG64_FLD( PHB_MASK_REG_MRG_MRT_ERROR , 53 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_MRT_ERROR ); +REG64_FLD( PHB_MASK_REG_MRG_RESERVED01 , 54 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_RESERVED01 ); +REG64_FLD( PHB_MASK_REG_MRG_RESERVED02 , 55 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_RESERVED02 ); +REG64_FLD( PHB_MASK_REG_TCE_IODA_PAGE_ACCESS_ERROR , 56 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_TCE_IODA_PAGE_ACCESS_ERROR ); +REG64_FLD( PHB_MASK_REG_TCE_REQUEST_TIMEOUT_ERROR , 57 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_TCE_REQUEST_TIMEOUT_ERROR ); +REG64_FLD( PHB_MASK_REG_TCE_UNEXPECTED_RESPONSE_ERROR , 58 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_TCE_UNEXPECTED_RESPONSE_ERROR ); +REG64_FLD( PHB_MASK_REG_TCE_COMMON_FATAL_ERRORS , 59 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_TCE_COMMON_FATAL_ERRORS ); +REG64_FLD( PHB_MASK_REG_TCE_ECC_CORRECTABLE_ERROR , 60 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_TCE_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_MASK_REG_TCE_ECC_UNCORRECTABLE_ERROR , 61 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_TCE_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_MASK_REG_TCE_RESERVED01 , 62 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_TCE_RESERVED01 ); +REG64_FLD( PHB_MASK_REG_LEM_FIR_INTERNAL_PARITY_ERROR , 63 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_LEM_FIR_INTERNAL_PARITY_ERROR ); + REG64_FLD( PU_MCC_FIR_REG_MCD_ARRAY_ECC_UE_ERR , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MCD_ARRAY_ECC_UE_ERR ); REG64_FLD( PU_MCC_FIR_REG_MCD_ARRAY_ECC_CE_ERR , 1 , SH_UNT , SH_ACS_SCOM2_OR , @@ -53484,12 +56363,24 @@ REG64_FLD( PU_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( PU_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); +REG64_FLD( PU_MIB_XIICAC_PIB_IFETCH_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PIB_IFETCH_PENDING ); REG64_FLD( PU_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( PU_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID ); REG64_FLD( PU_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID_LEN ); +REG64_FLD( PU_MIB_XIICAC_ICACHE_LINE2_VALID , 40 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID ); +REG64_FLD( PU_MIB_XIICAC_ICACHE_LINE2_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID_LEN ); +REG64_FLD( PU_MIB_XIICAC_ICACHE_LINE_PTR , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE_PTR ); +REG64_FLD( PU_MIB_XIICAC_ICACHE_LINE2_ERR , 46 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_ERR ); +REG64_FLD( PU_MIB_XIICAC_ICACHE_PREFETCH_PENDING , 47 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_PREFETCH_PENDING ); REG64_FLD( PU_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); @@ -53560,9 +56451,13 @@ REG64_FLD( PU_NPU_CTL_MISC_CONFIG_PERF_PE_MATCH , 7 , SH_UN SH_FLD_PERF_PE_MATCH ); REG64_FLD( PU_NPU_CTL_MISC_CONFIG_PERF_PE_MATCH_LEN , 4 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_PERF_PE_MATCH_LEN ); -REG64_FLD( PU_NPU_CTL_MISC_CONFIG_RSVD , 11 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU_CTL_MISC_CONFIG_IPI_PS , 11 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_IPI_PS ); +REG64_FLD( PU_NPU_CTL_MISC_CONFIG_IPI_OS , 12 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_IPI_OS ); +REG64_FLD( PU_NPU_CTL_MISC_CONFIG_RSVD , 13 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_RSVD ); -REG64_FLD( PU_NPU_CTL_MISC_CONFIG_RSVD_LEN , 53 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU_CTL_MISC_CONFIG_RSVD_LEN , 51 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_RSVD_LEN ); REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL0_STALL , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , @@ -53744,6 +56639,8 @@ REG64_FLD( PEC_STACK0_MMIOBAR1_REG_PE_MMIO_BAR1 , 0 , SH_UN REG64_FLD( PEC_STACK0_MMIOBAR1_REG_PE_MMIO_BAR1_LEN , 40 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR1_LEN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_RESERVED_0 , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_0 ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_BKINV_INTERLOCK_DIS , 1 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_BKINV_INTERLOCK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_EN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -53756,6 +56653,8 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_LFSR_DIS , 9 , SH_UN SH_FLD_FBC_LFSR_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_INV_AMORT_DIS , 10 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_INV_AMORT_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_RESERVED_10_11 , 11 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_10_11 ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_DIN_ECC_CHK_DIS , 12 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_DIN_ECC_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_XLAT_ECC_CHK_DIS , 13 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -53786,6 +56685,8 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_SNP_TIMEOUT_CHK_DIS , 25 , SH_UN SH_FLD_FBC_SNP_TIMEOUT_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_CMD_PROT_ERR_CHK_DIS , 26 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_CMD_PROT_ERR_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_RESERVED_27 , 27 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_27 ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_THRESHOLD , 28 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DYN_ST_MODE_THRESHOLD ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_THRESHOLD_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -53821,6 +56722,22 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_CAC_PERR_CHK_DIS , 21 , SH_UN SH_FLD_CAC_PERR_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_LRU_PERR_CHK_DIS , 22 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_LRU_PERR_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_MULTIHIT_CHK_DIS , 23 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_MULTIHIT_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS505_FIX_DIS , 24 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS505_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS510_FIX_DIS , 25 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS510_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS511_FIX_DIS , 26 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS511_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS544_FIX_DIS , 27 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS544_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS554_FIX_DIS , 28 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS554_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_RESERVED_28_31 , 29 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_RESERVED_28_31_LEN , 3 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_28_31_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS0_STG0_SEL , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DBG_BUS0_STG0_SEL ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS0_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -53829,6 +56746,12 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS1_STG0_SEL , 36 , SH_UN SH_FLD_DBG_BUS1_STG0_SEL ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS1_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DBG_BUS1_STG0_SEL_LEN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_RESERVED_40_51 , 40 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_40_51 ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_RESERVED_40_51_LEN , 12 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_40_51_LEN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS542_FIX_DIS , 52 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS542_FIX_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TWSM_DIS , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TWSM_DIS ); @@ -53842,6 +56765,20 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_INV_SINGLE_THREAD_EN , 20 , SH_UN SH_FLD_INV_SINGLE_THREAD_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_CXT_CAC_DIS , 21 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_CXT_CAC_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_22_23 , 22 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_22_23 ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_22_23_LEN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_22_23_LEN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_ISS487_EN , 24 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS487_EN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_25 , 25 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_25 ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_ISS526_EN , 26 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS526_EN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_27_29 , 27 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_27_29 ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_27_29_LEN , 3 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_27_29_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_MPSS_DIS , 31 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_MPSS_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_NCU_SNP_TLBIE_CNT_THRESH , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -53870,6 +56807,8 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_PWC_L4_DIS , 49 , SH_UN SH_FLD_TW_LCO_RDX_PWC_L4_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_PDE_EN , 50 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_LCO_RDX_PDE_EN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_51 , 51 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_51 ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_PWC_DIS , 52 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_RDX_PWC_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_INT_PWC_DIS , 53 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -53880,6 +56819,8 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_PWC_SPLIT_EN , 55 , SH_UN SH_FLD_TW_RDX_PWC_SPLIT_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_PWC_VA_HASH , 56 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_RDX_PWC_VA_HASH ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_57 , 57 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_57 ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_PTE_UPD_INTR_EN , 58 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_PTE_UPD_INTR_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_NCU_SNP_TLBIE_PACING_CNT_EN , 59 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -53915,6 +56856,16 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_MULTIHIT_CHK_DIS , 25 , SH_UN SH_FLD_MULTIHIT_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_EA_RANGE_CHK_DIS , 26 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_EA_RANGE_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS426_FIX_DIS , 27 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS426_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS486_FIX_DIS , 28 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS486_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS505_FIX_DIS , 29 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS505_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS510_FIX_DIS , 30 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS510_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS512_FIX_DIS , 31 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS512_FIX_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS0_STG0_SEL , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DBG_BUS0_STG0_SEL ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS0_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -53923,14 +56874,28 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS1_STG0_SEL , 36 , SH_UN SH_FLD_DBG_BUS1_STG0_SEL ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS1_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DBG_BUS1_STG0_SEL_LEN ); -REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_GUEST_PREF_PGSZ , 40 , SH_UNT_PU_NMMU , SH_ACS_SCOM , +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS534_FIX_DIS , 40 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS534_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS537_FIX_DIS , 41 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS537_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS540_FIX_DIS , 42 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS540_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS543_FIX_DIS , 43 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS543_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_GUEST_PREF_PGSZ , 44 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_GUEST_PREF_PGSZ ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_GUEST_PREF_PGSZ_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_GUEST_PREF_PGSZ_LEN ); -REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_HOST_PREF_PGSZ , 44 , SH_UNT_PU_NMMU , SH_ACS_SCOM , +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_HOST_PREF_PGSZ , 48 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HOST_PREF_PGSZ ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_HOST_PREF_PGSZ_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HOST_PREF_PGSZ_LEN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS542_FIX_DIS , 52 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS542_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS543B_FIX_EN , 53 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS543B_FIX_EN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS567_FIX_DIS , 54 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS567_FIX_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG0_HRMOR , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HRMOR ); @@ -54132,6 +57097,10 @@ REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TLB_BUS0_STG1_SEL , 25 , SH_UN SH_FLD_TLB_BUS0_STG1_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TLB_BUS1_STG1_SEL , 26 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TLB_BUS1_STG1_SEL ); +REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RESERVED_27_31 , 27 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_27_31 ); +REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RESERVED_27_31_LEN , 5 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_27_31_LEN ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS0_STG0_SEL , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_BUS0_STG0_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS0_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -54853,6 +57822,25 @@ REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UN REG64_FLD( PU_NPU1_SM0_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); +REG64_FLD( PEC_NESTTRC_REG_TRACE_MUX_SEL_A , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_TRACE_MUX_SEL_A ); +REG64_FLD( PEC_NESTTRC_REG_TRACE_MUX_SEL_A_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_TRACE_MUX_SEL_A_LEN ); +REG64_FLD( PEC_NESTTRC_REG_TRACE_MUX_SEL_B , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_TRACE_MUX_SEL_B ); +REG64_FLD( PEC_NESTTRC_REG_TRACE_MUX_SEL_B_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_TRACE_MUX_SEL_B_LEN ); +REG64_FLD( PEC_NESTTRC_REG_TRACE_MUX_SEL_C , 8 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_TRACE_MUX_SEL_C ); +REG64_FLD( PEC_NESTTRC_REG_TRACE_MUX_SEL_C_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_TRACE_MUX_SEL_C_LEN ); +REG64_FLD( PEC_NESTTRC_REG_TRACE_MUX_SEL_D , 12 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_TRACE_MUX_SEL_D ); +REG64_FLD( PEC_NESTTRC_REG_TRACE_MUX_SEL_D_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_TRACE_MUX_SEL_D_LEN ); +REG64_FLD( PEC_NESTTRC_REG_TRACE_ENABLE , 16 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_TRACE_ENABLE ); + REG64_FLD( PEC_STACK0_NET_CTRL0_CHIPLET_ENABLE , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_CHIPLET_ENABLE ); REG64_FLD( PEC_STACK0_NET_CTRL0_PCB_EP_RESET , 1 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, @@ -54895,10 +57883,8 @@ REG64_FLD( PEC_STACK0_NET_CTRL0_CPLT_RCTRL , 19 , SH_UN SH_FLD_CPLT_RCTRL ); REG64_FLD( PEC_STACK0_NET_CTRL0_CPLT_DCTRL , 20 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_CPLT_DCTRL ); -REG64_FLD( PEC_STACK0_NET_CTRL0_L3_EDRAM_ENABLE0 , 23 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, - SH_FLD_L3_EDRAM_ENABLE0 ); -REG64_FLD( PEC_STACK0_NET_CTRL0_L3_EDRAM_ENABLE1 , 24 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, - SH_FLD_L3_EDRAM_ENABLE1 ); +REG64_FLD( PEC_STACK0_NET_CTRL0_ADJ_FUNC_CLKSEL , 22 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_ADJ_FUNC_CLKSEL ); REG64_FLD( PEC_STACK0_NET_CTRL0_TP_FENCE_PCB , 25 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_TP_FENCE_PCB ); REG64_FLD( PEC_STACK0_NET_CTRL0_LVLTRANS_FENCE , 26 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, @@ -54909,6 +57895,8 @@ REG64_FLD( PEC_STACK0_NET_CTRL0_HTB_INTEST , 28 , SH_UN SH_FLD_HTB_INTEST ); REG64_FLD( PEC_STACK0_NET_CTRL0_HTB_EXTEST , 29 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_HTB_EXTEST ); +REG64_FLD( PEC_STACK0_NET_CTRL0_PM_ACCESS , 30 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_PM_ACCESS ); REG64_FLD( PEC_STACK0_NET_CTRL0_PLLFORCE_OUT_EN , 31 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_PLLFORCE_OUT_EN ); @@ -54950,6 +57938,10 @@ REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_PULSE_MODE , 26 , SH_UN SH_FLD_CLK_PULSE_MODE ); REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_PULSE_MODE_LEN , 2 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_MODE_LEN ); +REG64_FLD( PEC_STACK0_NET_CTRL1_PCB_ACCESS , 28 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_PCB_ACCESS ); +REG64_FLD( PEC_STACK0_NET_CTRL1_PCB_ACCESS_LEN , 4 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_PCB_ACCESS_LEN ); REG64_FLD( PEC_STACK2_NFIRACTION0_REG_NFIRACTION0 , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , SH_FLD_NFIRACTION0 ); @@ -55213,6 +58205,39 @@ REG64_FLD( PU_NPU_CTL_NPU_VERSION_MINOR , 48 , SH_UN REG64_FLD( PU_NPU_CTL_NPU_VERSION_MINOR_LEN , 16 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MINOR_LEN ); +REG64_FLD( PEC_NRDSTKOVR_REG_N_RD_STACK0_OVERRIDE , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_RD_STACK0_OVERRIDE ); +REG64_FLD( PEC_NRDSTKOVR_REG_N_RD_STACK0_OVERRIDE_LEN , 32 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_RD_STACK0_OVERRIDE_LEN ); +REG64_FLD( PEC_NRDSTKOVR_REG_N_RD_STACK1_OVERRIDE , 32 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_RD_STACK1_OVERRIDE ); +REG64_FLD( PEC_NRDSTKOVR_REG_N_RD_STACK1_OVERRIDE_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_RD_STACK1_OVERRIDE_LEN ); +REG64_FLD( PEC_NRDSTKOVR_REG_N_RD_STACK_OVERRIDE_ENABLE , 48 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_RD_STACK_OVERRIDE_ENABLE ); + +REG64_FLD( PEC_NSTQSTKOVR_REG_N_ST_STACK0_OVERRIDE , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_ST_STACK0_OVERRIDE ); +REG64_FLD( PEC_NSTQSTKOVR_REG_N_ST_STACK0_OVERRIDE_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_ST_STACK0_OVERRIDE_LEN ); +REG64_FLD( PEC_NSTQSTKOVR_REG_N_ST_STACK1_OVERRIDE , 8 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_ST_STACK1_OVERRIDE ); +REG64_FLD( PEC_NSTQSTKOVR_REG_N_ST_STACK1_OVERRIDE_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_ST_STACK1_OVERRIDE_LEN ); +REG64_FLD( PEC_NSTQSTKOVR_REG_N_ST_STACK_OVERRIDE_ENABLE , 12 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_ST_STACK_OVERRIDE_ENABLE ); + +REG64_FLD( PEC_NWRSTKOVR_REG_N_WR_STACK0_OVERRIDE , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_WR_STACK0_OVERRIDE ); +REG64_FLD( PEC_NWRSTKOVR_REG_N_WR_STACK0_OVERRIDE_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_WR_STACK0_OVERRIDE_LEN ); +REG64_FLD( PEC_NWRSTKOVR_REG_N_WR_STACK1_OVERRIDE , 16 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_WR_STACK1_OVERRIDE ); +REG64_FLD( PEC_NWRSTKOVR_REG_N_WR_STACK1_OVERRIDE_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_WR_STACK1_OVERRIDE_LEN ); +REG64_FLD( PEC_NWRSTKOVR_REG_N_WR_STACK_OVERRIDE_ENABLE , 24 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_WR_STACK_OVERRIDE_ENABLE ); + REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_LN , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DMA_WR_DISABLE_LN ); REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_GROUP , 1 , SH_UNT , SH_ACS_SCOM , @@ -55429,6 +58454,10 @@ REG64_FLD( PU_NX_CQ_FIR_REG_UMAC_CRB_SUE , 28 , SH_UN SH_FLD_UMAC_CRB_SUE ); REG64_FLD( PU_NX_CQ_FIR_REG_ERAT_LOCAL_CSTOP , 29 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ERAT_LOCAL_CSTOP ); +REG64_FLD( PU_NX_CQ_FIR_REG_UMAC_SCOM_SAT_ERR , 30 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_UMAC_SCOM_SAT_ERR ); +REG64_FLD( PU_NX_CQ_FIR_REG_SPARE , 31 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE ); REG64_FLD( PU_NX_CQ_FIR_REG_RNG_FIRST_FAIL , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RNG_FIRST_FAIL ); REG64_FLD( PU_NX_CQ_FIR_REG_RNG_SECOND_FAIL , 33 , SH_UNT , SH_ACS_SCOM2_OR , @@ -55443,6 +58472,10 @@ REG64_FLD( PU_NX_CQ_FIR_REG_PBCQ_CNTRL_LOGIC_ERR , 37 , SH_UN SH_FLD_PBCQ_CNTRL_LOGIC_ERR ); REG64_FLD( PU_NX_CQ_FIR_REG_FAILED_LINK_ON_INTERRUPT , 38 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FAILED_LINK_ON_INTERRUPT ); +REG64_FLD( PU_NX_CQ_FIR_REG_SPARES , 39 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARES ); +REG64_FLD( PU_NX_CQ_FIR_REG_SPARES_LEN , 3 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARES_LEN ); REG64_FLD( PU_NX_CQ_FIR_REG_SCOM_PE , 42 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PE ); REG64_FLD( PU_NX_CQ_FIR_REG_SCOM_PE_DUP , 43 , SH_UNT , SH_ACS_SCOM2_OR , @@ -55760,12 +58793,25 @@ REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_SELECT , 27 , SH_UN REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_SELECT_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_NXCQ_ERAT_ARRAY_SELECT_LEN ); +REG64_FLD( PU_NMMU_NX_PB_ERR_RPT_0_NX_PBI_ERR_RPT_OUT , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_NX_PBI_ERR_RPT_OUT ); +REG64_FLD( PU_NMMU_NX_PB_ERR_RPT_0_NX_PBI_ERR_RPT_OUT_LEN , 52 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_NX_PBI_ERR_RPT_OUT_LEN ); REG64_FLD( PU_NMMU_NX_PB_ERR_RPT_0_PBI_WRITE_IDLE , 52 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_PBI_WRITE_IDLE ); +REG64_FLD( PU_NX_PB_ERR_RPT_0_NX_PBI_ERR_RPT_OUT , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_NX_PBI_ERR_RPT_OUT ); +REG64_FLD( PU_NX_PB_ERR_RPT_0_NX_PBI_ERR_RPT_OUT_LEN , 63 , SH_UNT , SH_ACS_SCOM , + SH_FLD_NX_PBI_ERR_RPT_OUT_LEN ); REG64_FLD( PU_NX_PB_ERR_RPT_0_PBI_WRITE_IDLE , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_PBI_WRITE_IDLE ); +REG64_FLD( PU_NX_PB_ERR_RPT_1_NX_PBI_ERR_RPT_OUT , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_NX_PBI_ERR_RPT_OUT ); +REG64_FLD( PU_NX_PB_ERR_RPT_1_NX_PBI_ERR_RPT_OUT_LEN , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_NX_PBI_ERR_RPT_OUT_LEN ); + REG64_FLD( PU_NX_PMU0_CONTROL_REG_ENABLE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_FREEZE , 1 , SH_UNT , SH_ACS_SCOM , @@ -56178,6 +59224,46 @@ REG64_FLD( PU_OCB_OCI_CCSR_RESERVED_24_LEN , 7 , SH_UN REG64_FLD( PU_OCB_OCI_CCSR_CHANGE_IN_PROGRESS , 31 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CHANGE_IN_PROGRESS ); +REG64_FLD( PU_OCB_OCI_G0ISR0_INTERRUPT_GPE0_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE0_STATUS_N ); +REG64_FLD( PU_OCB_OCI_G0ISR0_INTERRUPT_GPE0_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE0_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_G0ISR1_INTERRUPT_GPE0_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE0_STATUS_N ); +REG64_FLD( PU_OCB_OCI_G0ISR1_INTERRUPT_GPE0_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE0_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_G1ISR0_INTERRUPT_GPE1_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE1_STATUS_N ); +REG64_FLD( PU_OCB_OCI_G1ISR0_INTERRUPT_GPE1_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE1_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_G1ISR1_INTERRUPT_GPE1_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE1_STATUS_N ); +REG64_FLD( PU_OCB_OCI_G1ISR1_INTERRUPT_GPE1_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE1_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_G2ISR0_INTERRUPT_GPE2_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE2_STATUS_N ); +REG64_FLD( PU_OCB_OCI_G2ISR0_INTERRUPT_GPE2_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE2_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_G2ISR1_INTERRUPT_GPE2_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE2_STATUS_N ); +REG64_FLD( PU_OCB_OCI_G2ISR1_INTERRUPT_GPE2_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE2_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_G3ISR0_INTERRUPT_GPE3_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE3_STATUS_N ); +REG64_FLD( PU_OCB_OCI_G3ISR0_INTERRUPT_GPE3_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE3_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_G3ISR1_INTERRUPT_GPE3_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE3_STATUS_N ); +REG64_FLD( PU_OCB_OCI_G3ISR1_INTERRUPT_GPE3_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE3_STATUS_N_LEN ); + REG64_FLD( PU_OCB_OCI_O2SCMD0A_O2SCMD_A_N_RESERVED_0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2SCMD_A_N_RESERVED_0 ); REG64_FLD( PU_OCB_OCI_O2SCMD0A_O2S_CLEAR_STICKY_BITS_A_N , 1 , SH_UNT , SH_ACS_SCOM_RW , @@ -57055,6 +60141,26 @@ REG64_FLD( PU_OCB_OCI_OCICFG_SPARE_24_31 , 25 , SH_UN REG64_FLD( PU_OCB_OCI_OCICFG_SPARE_24_31_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SPARE_24_31_LEN ); +REG64_FLD( PU_OCB_OCI_OCISR0_INTERRUPT_CRIT_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_CRIT_STATUS_N ); +REG64_FLD( PU_OCB_OCI_OCISR0_INTERRUPT_CRIT_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_CRIT_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_OCISR1_INTERRUPT_CRIT_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_CRIT_STATUS_N ); +REG64_FLD( PU_OCB_OCI_OCISR1_INTERRUPT_CRIT_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_CRIT_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_ODISR0_INTERRUPT_DEBUG_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_DEBUG_STATUS_N ); +REG64_FLD( PU_OCB_OCI_ODISR0_INTERRUPT_DEBUG_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_DEBUG_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_ODISR1_INTERRUPT_DEBUG_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_DEBUG_STATUS_N ); +REG64_FLD( PU_OCB_OCI_ODISR1_INTERRUPT_DEBUG_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_DEBUG_STATUS_N_LEN ); + REG64_FLD( PU_OCB_OCI_OEHDR_EVENT2HALT_DELAY , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EVENT2HALT_DELAY ); REG64_FLD( PU_OCB_OCI_OEHDR_EVENT2HALT_DELAY_LEN , 20 , SH_UNT , SH_ACS_SCOM_RW , @@ -57285,6 +60391,16 @@ REG64_FLD( PU_OCB_OCI_OITR1_INTERRUPT_TYPE_N , 0 , SH_UN REG64_FLD( PU_OCB_OCI_OITR1_INTERRUPT_TYPE_N_LEN , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_TYPE_N_LEN ); +REG64_FLD( PU_OCB_OCI_ONISR0_INTERRUPT_NONCRIT_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_NONCRIT_STATUS_N ); +REG64_FLD( PU_OCB_OCI_ONISR0_INTERRUPT_NONCRIT_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_NONCRIT_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_ONISR1_INTERRUPT_NONCRIT_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_NONCRIT_STATUS_N ); +REG64_FLD( PU_OCB_OCI_ONISR1_INTERRUPT_NONCRIT_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_NONCRIT_STATUS_N_LEN ); + REG64_FLD( PU_OCB_OCI_OPIT0C0_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C0_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , @@ -58420,6 +61536,16 @@ REG64_FLD( PU_OCB_OCI_OTR1_TIMER_N , 16 , SH_UN REG64_FLD( PU_OCB_OCI_OTR1_TIMER_N_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_TIMER_N_LEN ); +REG64_FLD( PU_OCB_OCI_OUISR0_INTERRUPT_UNCON_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_UNCON_STATUS_N ); +REG64_FLD( PU_OCB_OCI_OUISR0_INTERRUPT_UNCON_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_UNCON_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_OUISR1_INTERRUPT_UNCON_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_UNCON_STATUS_N ); +REG64_FLD( PU_OCB_OCI_OUISR1_INTERRUPT_UNCON_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_UNCON_STATUS_N_LEN ); + REG64_FLD( PU_OCB_OCI_QCSR_CORE_CONFIG , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CORE_CONFIG ); REG64_FLD( PU_OCB_OCI_QCSR_CORE_CONFIG_LEN , 24 , SH_UNT , SH_ACS_SCOM2_OR , @@ -58737,8 +61863,8 @@ REG64_FLD( PU_OCB_PIB_OCR_CRITICAL_INTERRUPT , 8 , SH_UN SH_FLD_CRITICAL_INTERRUPT ); REG64_FLD( PU_OCB_PIB_OCR_SLAVE_RESET_TO_405_ENABLE , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SLAVE_RESET_TO_405_ENABLE ); -REG64_FLD( PU_OCB_PIB_OCR_OCR_DBG_HALT , 10 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_OCR_DBG_HALT ); +REG64_FLD( PU_OCB_PIB_OCR_OCC_DBG_HALT , 10 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_OCC_DBG_HALT ); REG64_FLD( PU_OCB_PIB_OCR_SPARE , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE ); REG64_FLD( PU_OCB_PIB_OCR_SPARE_LEN , 5 , SH_UNT , SH_ACS_SCOM2_OR , @@ -59119,8 +62245,8 @@ REG64_FLD( PEC_OPCG_REG1_MISR_INIT_WAIT , 36 , SH_UN SH_FLD_MISR_INIT_WAIT ); REG64_FLD( PEC_OPCG_REG1_MISR_INIT_WAIT_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MISR_INIT_WAIT_LEN ); -REG64_FLD( PEC_OPCG_REG1_SUPPRESS_EVEN_CLK , 48 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_SUPPRESS_EVEN_CLK ); +REG64_FLD( PEC_OPCG_REG1_SUPPRESS_LAST_RUNN_CLK , 48 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SUPPRESS_LAST_RUNN_CLK ); REG64_FLD( PEC_OPCG_REG1_SCAN_CLK_USE_EVEN , 49 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SCAN_CLK_USE_EVEN ); REG64_FLD( PEC_OPCG_REG1_UNUSED2 , 50 , SH_UNT_PEC , SH_ACS_SCOM , @@ -59608,10 +62734,16 @@ REG64_FLD( PU_PBAFIRMASK_FIR_PARITY_ERR2_MASK , 44 , SH_UN REG64_FLD( PU_PBAFIRMASK_FIR_PARITY_ERR_MASK , 45 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FIR_PARITY_ERR_MASK ); +REG64_FLD( PEC_PBAIBHWCFG_REG_RESERVED0 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_RESERVED0 ); +REG64_FLD( PEC_PBAIBHWCFG_REG_RESERVED0_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_RESERVED0_LEN ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_OSMB_DATASTART_MODE , 16 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_OSMB_DATASTART_MODE ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_OSMB_DATASTART_MODE_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_OSMB_DATASTART_MODE_LEN ); +REG64_FLD( PEC_PBAIBHWCFG_REG_RESERVED1 , 19 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_RESERVED1 ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_TX_RESP_HWM , 20 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_TX_RESP_HWM ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_TX_RESP_HWM_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , @@ -59636,11 +62768,169 @@ REG64_FLD( PEC_PBAIBHWCFG_REG_PE_ISMB_ERROR_INJECT , 36 , SH_UN SH_FLD_PE_ISMB_ERROR_INJECT ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_ISMB_ERROR_INJECT_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_ISMB_ERROR_INJECT_LEN ); +REG64_FLD( PEC_PBAIBHWCFG_REG_RESERVED2 , 39 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_RESERVED2 ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_OSMB_HOL_BLK_CNT , 40 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_OSMB_HOL_BLK_CNT ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_OSMB_HOL_BLK_CNT_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_OSMB_HOL_BLK_CNT_LEN ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PBAIBHWCFG_PE , 0 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PBAIBHWCFG_PE ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PHBRESET_PE , 1 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PHBRESET_PE ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PBAIBTXCITR_PE , 2 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXCITR_PE ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PBAIBTXCCR_PE , 3 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXCCR_PE ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PBAIBTXDCR_PE , 4 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXDCR_PE ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PEAIB_OVERRUN , 5 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_OVERRUN ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PEAIB_QCNT_ERR , 6 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_QCNT_ERR ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PEAIB_TX_DAT_ERR , 7 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_TX_DAT_ERR ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PEAIB_CMD_PE , 8 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_PE ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PEAIB_DAT_PE , 9 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_PE ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PEAIB_CMD_CRD_AVAIL_PE , 10 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_CRD_AVAIL_PE ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PEAIB_DAT_CRD_AVAIL_PE , 11 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_CRD_AVAIL_PE ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PEAIB_CMD_CRD_PE , 12 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_CRD_PE ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PEAIB_DAT_CRD_PE , 13 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_CRD_PE ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PHBRESET_SCOM_ERR , 14 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PHBRESET_SCOM_ERR ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_ASYNC_ERROR , 15 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_ASYNC_ERROR ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_AIB_STACK_SCOM_ERR , 16 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_AIB_STACK_SCOM_ERR ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_AIB_PEC_SCOM_ERR , 17 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_AIB_PEC_SCOM_ERR ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PBAIB_FENCE_PCIE , 18 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PBAIB_FENCE_PCIE ); + +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PBAIBHWCFG_PE , 0 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PBAIBHWCFG_PE ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PHBRESET_PE , 1 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PHBRESET_PE ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PBAIBTXCITR_PE , 2 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXCITR_PE ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PBAIBTXCCR_PE , 3 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXCCR_PE ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PBAIBTXDCR_PE , 4 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXDCR_PE ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PEAIB_OVERRUN , 5 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PEAIB_OVERRUN ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PEAIB_QCNT_ERR , 6 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PEAIB_QCNT_ERR ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PEAIB_TX_DAT_ERR , 7 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PEAIB_TX_DAT_ERR ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PEAIB_CMD_PE , 8 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_PE ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PEAIB_DAT_PE , 9 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_PE ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PEAIB_CMD_CRD_AVAIL_PE , 10 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_CRD_AVAIL_PE ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PEAIB_DAT_CRD_AVAIL_PE , 11 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_CRD_AVAIL_PE ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PEAIB_CMD_CRD_PE , 12 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_CRD_PE ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PEAIB_DAT_CRD_PE , 13 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_CRD_PE ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PHBRESET_SCOM_ERR , 14 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PHBRESET_SCOM_ERR ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_ASYNC_ERROR , 15 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_ASYNC_ERROR ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_AIB_STACK_SCOM_ERR , 16 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_AIB_STACK_SCOM_ERR ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_AIB_PEC_SCOM_ERR , 17 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_AIB_PEC_SCOM_ERR ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PBAIB_FENCE_PCIE , 18 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PBAIB_FENCE_PCIE ); + +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PBAIBHWCFG_PE , 0 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PBAIBHWCFG_PE ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PHBRESET_PE , 1 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PHBRESET_PE ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PBAIBTXCITR_PE , 2 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXCITR_PE ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PBAIBTXCCR_PE , 3 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXCCR_PE ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PBAIBTXDCR_PE , 4 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXDCR_PE ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PEAIB_OVERRUN , 5 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_OVERRUN ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PEAIB_QCNT_ERR , 6 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_QCNT_ERR ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PEAIB_TX_DAT_ERR , 7 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_TX_DAT_ERR ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PEAIB_CMD_PE , 8 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_PE ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PEAIB_DAT_PE , 9 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_PE ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PEAIB_CMD_CRD_AVAIL_PE , 10 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_CRD_AVAIL_PE ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PEAIB_DAT_CRD_AVAIL_PE , 11 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_CRD_AVAIL_PE ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PEAIB_CMD_CRD_PE , 12 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_CRD_PE ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PEAIB_DAT_CRD_PE , 13 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_CRD_PE ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PHBRESET_SCOM_ERR , 14 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PHBRESET_SCOM_ERR ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_ASYNC_ERROR , 15 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_ASYNC_ERROR ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_AIB_STACK_SCOM_ERR , 16 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_AIB_STACK_SCOM_ERR ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_AIB_PEC_SCOM_ERR , 17 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_AIB_PEC_SCOM_ERR ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PBAIB_FENCE_PCIE , 18 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PBAIB_FENCE_PCIE ); + +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PBAIBHWCFG_PE , 0 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PBAIBHWCFG_PE ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PHBRESET_PE , 1 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PHBRESET_PE ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PBAIBTXCITR_PE , 2 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXCITR_PE ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PBAIBTXCCR_PE , 3 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXCCR_PE ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PBAIBTXDCR_PE , 4 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXDCR_PE ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PEAIB_OVERRUN , 5 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_OVERRUN ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PEAIB_QCNT_ERR , 6 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_QCNT_ERR ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PEAIB_TX_DAT_ERR , 7 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_TX_DAT_ERR ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PEAIB_CMD_PE , 8 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_PE ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PEAIB_DAT_PE , 9 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_PE ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PEAIB_CMD_CRD_AVAIL_PE , 10 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_CRD_AVAIL_PE ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PEAIB_DAT_CRD_AVAIL_PE , 11 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_CRD_AVAIL_PE ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PEAIB_CMD_CRD_PE , 12 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_CRD_PE ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PEAIB_DAT_CRD_PE , 13 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_CRD_PE ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PHBRESET_SCOM_ERR , 14 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PHBRESET_SCOM_ERR ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_ASYNC_ERROR , 15 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_ASYNC_ERROR ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_AIB_STACK_SCOM_ERR , 16 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_AIB_STACK_SCOM_ERR ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_AIB_PEC_SCOM_ERR , 17 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_AIB_PEC_SCOM_ERR ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PBAIB_FENCE_PCIE , 18 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PBAIB_FENCE_PCIE ); + REG64_FLD( PU_PBAMODE_RESERVED_0_3 , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_0_3 ); REG64_FLD( PU_PBAMODE_RESERVED_0_3_LEN , 4 , SH_UNT , SH_ACS_PIB , @@ -60415,6 +63705,10 @@ REG64_FLD( PEC_PBCQHWCFG_REG_PE_QFIFO_HOLD_MODE , 27 , SH_UN SH_FLD_PE_QFIFO_HOLD_MODE ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_QFIFO_HOLD_MODE_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_QFIFO_HOLD_MODE_LEN ); +REG64_FLD( PEC_PBCQHWCFG_REG_RESERVED1 , 29 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_RESERVED1 ); +REG64_FLD( PEC_PBCQHWCFG_REG_RESERVED1_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_RESERVED1_LEN ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_WR_STRICT_ORDER_MODE , 32 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_WR_STRICT_ORDER_MODE ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_CHANNEL_STREAMING_EN , 33 , SH_UNT_PEC , SH_ACS_SCOM_RW , @@ -60431,6 +63725,8 @@ REG64_FLD( PEC_PBCQHWCFG_REG_PE_FORCE_DISABLED_CTAG_TO_FOLLOW_FLOW , 38 , SH_UN SH_FLD_PE_FORCE_DISABLED_CTAG_TO_FOLLOW_FLOW ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_ENABLE_ENH_FLOW , 39 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_ENABLE_ENH_FLOW ); +REG64_FLD( PEC_PBCQHWCFG_REG_RESERVED2 , 40 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_RESERVED2 ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_WR_VG , 41 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_WR_VG ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_WR_SCOPE_GROUP , 42 , SH_UNT_PEC , SH_ACS_SCOM_RW , @@ -60441,6 +63737,10 @@ REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_INTWR_SCOPE_GROUP , 44 , SH_UN SH_FLD_PE_DISABLE_INTWR_SCOPE_GROUP ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_INTWR_SCOPE_NODE , 45 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_INTWR_SCOPE_NODE ); +REG64_FLD( PEC_PBCQHWCFG_REG_RESERVED3 , 46 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_RESERVED3 ); +REG64_FLD( PEC_PBCQHWCFG_REG_RESERVED3_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_RESERVED3_LEN ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_RD_WRITE_ORDERING , 48 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_RD_WRITE_ORDERING ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_RD_WRITE_ORDERING_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM_RW , @@ -60650,6 +63950,8 @@ REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC3_MCS0_MASK , 53 , SH_UN SH_FLD_CFG_MC3_MCS0_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC3_MCS1_MASK , 54 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_MC3_MCS1_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_PB_CFG_CNPME_MASK , 55 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_PB_CFG_CNPME_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MCD_MASK , 56 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_MCD_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_PE0_MASK , 57 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , @@ -60771,6 +64073,39 @@ REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_PE1_MASK , 58 , SH_UN SH_FLD_CFG_PE1_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_PE2_MASK , 59 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PE2_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_PB_CFG_CNPMW_MASK , 60 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_PB_CFG_CNPMW_MASK ); + +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CRESP_ERROR , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CRESP_ERROR ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CRESP_ADDR_ERROR , 1 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CRESP_ADDR_ERROR ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_ERROR_OTHER , 2 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_CRESP_ERROR_OTHER ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TTYPE , 3 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_CRESP_TTYPE ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TTYPE_LEN , 7 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_CRESP_TTYPE_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TSIZE , 10 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_CRESP_TSIZE ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TSIZE_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_CRESP_TSIZE_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TTAG , 18 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_CRESP_TTAG ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TTAG_LEN , 22 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_CRESP_TTAG_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_SCOPE , 40 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_CRESP_SCOPE ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_SCOPE_LEN , 3 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_CRESP_SCOPE_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP , 43 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_CRESP ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_LEN , 5 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_CRESP_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_PRESP , 48 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_PRESP ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_PRESP_LEN , 14 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_PRESP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTYPE , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TTYPE ); @@ -60918,6 +64253,15 @@ REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_CNPMW_BITWISE_ENABLE_LEN , 16 , REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_PORT , 56 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PMU_PORT ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_EXTDAT_COUNTER_PB_APM_EXTDATASND_CNT , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_APM_EXTDATASND_CNT ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_EXTDAT_COUNTER_PB_APM_EXTDATASND_CNT_LEN , 32 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PB_APM_EXTDATASND_CNT_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_EXTDAT_COUNTER_PB_APM_EXTDATARCV_CNT , 32 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_APM_EXTDATARCV_CNT ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_EXTDAT_COUNTER_PB_APM_EXTDATARCV_CNT_LEN , 32 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PB_APM_EXTDATARCV_CNT_LEN ); + REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG_ACTION0_LEN , 18 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM_RW , @@ -61068,6 +64412,152 @@ REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL7 , 56 , SH_UN REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL7_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL7_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA0_EN , 0 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA0_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA1_EN , 1 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA1_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA2_EN , 2 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA2_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA3_EN , 3 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA3_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA0_EN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA0_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA1_EN , 5 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA1_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA2_EN , 6 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA2_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA3_EN , 7 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA3_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA0_EN , 8 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA0_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA1_EN , 9 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA1_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA2_EN , 10 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA2_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA3_EN , 11 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA3_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA0_GROUPID , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA0_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA1_GROUPID , 20 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA1_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA2_GROUPID , 24 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA2_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA3_GROUPID , 28 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA3_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA0_GROUPID , 32 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA0_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA1_GROUPID , 36 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA1_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA2_GROUPID , 40 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA2_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA3_GROUPID , 44 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA3_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA0_GROUPID , 48 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA0_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA1_GROUPID , 52 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA1_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA2_GROUPID , 56 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA2_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA3_GROUPID , 60 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA3_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA3_GROUPID_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA0_EN , 0 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA0_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA1_EN , 1 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA1_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA2_EN , 2 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA2_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA3_EN , 3 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA3_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA0_EN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA0_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA1_EN , 5 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA1_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA2_EN , 6 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA2_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA3_EN , 7 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA3_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA0_EN , 8 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA0_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA1_EN , 9 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA1_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA2_EN , 10 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA2_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA3_EN , 11 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA3_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA0_GROUPID , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA0_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA1_GROUPID , 20 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA1_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA2_GROUPID , 24 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA2_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA3_GROUPID , 28 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA3_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA0_GROUPID , 32 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA0_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA1_GROUPID , 36 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA1_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA2_GROUPID , 40 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA2_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA3_GROUPID , 44 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA3_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA0_GROUPID , 48 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA0_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA1_GROUPID , 52 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA1_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA2_GROUPID , 56 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA2_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA3_GROUPID , 60 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA3_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA3_GROUPID_LEN ); + REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X0_EN , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X1_EN , 1 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , @@ -61274,6 +64764,8 @@ REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID , 40 , SH_U SH_FLD_CFG_XLATE_ADDR_TO_ID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_PB_CFG_CENT_A_INDIRECT_EN , 49 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_A_INDIRECT_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_A_GATHER_ENABLE , 50 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_GATHER_ENABLE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_PHYP_IS_GROUP , 52 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , @@ -61357,6 +64849,8 @@ REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID , 40 , SH_U SH_FLD_CFG_XLATE_ADDR_TO_ID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_PB_CFG_CENT_A_INDIRECT_EN , 49 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_A_INDIRECT_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_A_GATHER_ENABLE , 50 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_GATHER_ENABLE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_PHYP_IS_GROUP , 52 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , @@ -61388,7 +64882,21 @@ REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_LO_COMP , 12 , SH_UN SH_FLD_CFG_APM_LM_LO_COMP ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_LO_COMP_LEN , 4 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_APM_LM_LO_COMP_LEN ); - +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_PB_APM_LM_LO_CNT , 16 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_APM_LM_LO_CNT ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_PB_APM_LM_LO_CNT_LEN , 24 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_APM_LM_LO_CNT_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_PB_APM_LM_HI_CNT , 40 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_APM_LM_HI_CNT ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_PB_APM_LM_HI_CNT_LEN , 24 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_APM_LM_HI_CNT_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_PB_CENT_PBIXXX_INIT , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_PB_CENT_PBIXXX_INIT ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_PB_CENT_DBG_MAX_HANG_STAGE_REACHED , 1 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CENT_DBG_MAX_HANG_STAGE_REACHED ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_PB_CENT_DBG_MAX_HANG_STAGE_REACHED_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CENT_DBG_MAX_HANG_STAGE_REACHED_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CHIP_IS_SYSTEM , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CHIP_IS_SYSTEM ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_HNG_CHK_DISABLE , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , @@ -61411,6 +64919,10 @@ REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_LCL_HW_MARK , 30 , SH_UN SH_FLD_CFG_LCL_HW_MARK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_LCL_HW_MARK_LEN , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LCL_HW_MARK_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CPU_RATIO_OVERRIDE , 36 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CPU_RATIO_OVERRIDE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CPU_RATIO_OVERRIDE_LEN , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CPU_RATIO_OVERRIDE_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_REQ_GATHER_ENABLE , 57 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_REQ_GATHER_ENABLE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SWITCH_CD_PULSE , 58 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , @@ -61440,6 +64952,150 @@ REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_LO_COMP , 12 , SH_UN SH_FLD_CFG_APM_NM_LO_COMP ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_LO_COMP_LEN , 4 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_APM_NM_LO_COMP_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_PB_APM_NM_LO_CNT , 16 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_APM_NM_LO_CNT ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_PB_APM_NM_LO_CNT_LEN , 24 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_APM_NM_LO_CNT_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_PB_APM_NM_HI_CNT , 40 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_APM_NM_HI_CNT ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_PB_APM_NM_HI_CNT_LEN , 24 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_APM_NM_HI_CNT_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER0 , 0 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER0_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER1 , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER1_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER2 , 32 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER2_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER3 , 48 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER3_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER3_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER0 , 0 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER0_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER1 , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER1_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER2 , 32 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER2_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER3 , 48 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER3_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER3_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER0 , 0 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER0_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER1 , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER1_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER2 , 32 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER2_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER3 , 48 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER3_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER3_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER0 , 0 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER0_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER1 , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER1_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER2 , 32 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER2_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER3 , 48 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER3_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER3_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER0 , 0 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER0_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER1 , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER1_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER2 , 32 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER2_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER3 , 48 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER3_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER3_LEN ); + +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER0 , 0 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER0 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER0_LEN , 16 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER0_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER1 , 16 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER1 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER1_LEN , 16 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER1_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER2 , 32 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER2 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER2_LEN , 16 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER2_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER3 , 48 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER3 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER3_LEN , 16 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER3_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER0 , 0 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER0_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER1 , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER1_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER2 , 32 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER2_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER3 , 48 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER3_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER3_LEN ); + +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER0 , 0 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER0 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER0_LEN , 16 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER0_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER1 , 16 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER1 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER1_LEN , 16 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER1_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER2 , 32 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER2 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER2_LEN , 16 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER2_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER3 , 48 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER3 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER3_LEN , 16 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER3_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C0 , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP0_C0 ); @@ -61568,6 +65224,15 @@ REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C3 , 62 , SH_UN REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP3_C3_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RCMD_INTDAT_COUNTER_PB_APM_RCMD_CNT , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_APM_RCMD_CNT ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RCMD_INTDAT_COUNTER_PB_APM_RCMD_CNT_LEN , 32 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PB_APM_RCMD_CNT_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RCMD_INTDAT_COUNTER_PB_APM_INTDATA_CNT , 32 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PB_APM_INTDATA_CNT ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RCMD_INTDAT_COUNTER_PB_APM_INTDATA_CNT_LEN , 32 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PB_APM_INTDATA_CNT_LEN ); + REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL0 , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL0 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL0_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , @@ -61948,6 +65613,162 @@ REG64_FLD( PU_PB_EAST_FIR_REG_SCOM_ERR , 32 , SH_UN REG64_FLD( PU_PB_EAST_FIR_REG_SCOM_ERR_DUP , 33 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); +REG64_FLD( PU_PB_EAST_FW_SCRATCH0_PB_EAST_FW_SCRATCH0 , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PB_EAST_FW_SCRATCH0 ); +REG64_FLD( PU_PB_EAST_FW_SCRATCH0_PB_EAST_FW_SCRATCH0_LEN , 64 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PB_EAST_FW_SCRATCH0_LEN ); + +REG64_FLD( PU_PB_EAST_FW_SCRATCH1_PB_EAST_FW_SCRATCH1 , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PB_EAST_FW_SCRATCH1 ); +REG64_FLD( PU_PB_EAST_FW_SCRATCH1_PB_EAST_FW_SCRATCH1_LEN , 64 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PB_EAST_FW_SCRATCH1_LEN ); + +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA0_EN , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA0_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA1_EN , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA1_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA2_EN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA2_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA3_EN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA3_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA0_EN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA0_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA1_EN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA1_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA2_EN , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA2_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA3_EN , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA3_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA0_EN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA0_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA1_EN , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA1_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA2_EN , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA2_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA3_EN , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA3_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA0_GROUPID , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA0_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA0_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA1_GROUPID , 20 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA1_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA1_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA2_GROUPID , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA2_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA2_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA3_GROUPID , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA3_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA3_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA0_GROUPID , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA0_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA0_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA1_GROUPID , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA1_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA1_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA2_GROUPID , 40 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA2_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA2_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA3_GROUPID , 44 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA3_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA3_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA0_GROUPID , 48 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA0_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA0_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA1_GROUPID , 52 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA1_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA1_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA2_GROUPID , 56 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA2_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA2_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA3_GROUPID , 60 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA3_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA3_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA3_GROUPID_LEN ); + +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA0_EN , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA0_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA1_EN , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA1_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA2_EN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA2_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA3_EN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA3_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA0_EN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA0_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA1_EN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA1_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA2_EN , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA2_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA3_EN , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA3_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA0_EN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA0_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA1_EN , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA1_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA2_EN , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA2_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA3_EN , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA3_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA0_GROUPID , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA0_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA0_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA1_GROUPID , 20 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA1_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA1_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA2_GROUPID , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA2_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA2_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA3_GROUPID , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA3_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA3_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA0_GROUPID , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA0_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA0_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA1_GROUPID , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA1_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA1_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA2_GROUPID , 40 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA2_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA2_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA3_GROUPID , 44 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA3_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA3_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA0_GROUPID , 48 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA0_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA0_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA1_GROUPID , 52 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA1_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA1_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA2_GROUPID , 56 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA2_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA2_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA3_GROUPID , 60 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA3_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA3_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA3_GROUPID_LEN ); + REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X0_EN , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_EN ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X1_EN , 1 , SH_UNT , SH_ACS_SCOM , @@ -62154,6 +65975,8 @@ REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID , 40 , SH_UN SH_FLD_CFG_XLATE_ADDR_TO_ID ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_PB_CFG_EAST_A_INDIRECT_EN , 49 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_A_INDIRECT_EN ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_A_GATHER_ENABLE , 50 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_A_GATHER_ENABLE ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_PHYP_IS_GROUP , 52 , SH_UNT , SH_ACS_SCOM , @@ -62237,6 +66060,8 @@ REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID , 40 , SH_UN SH_FLD_CFG_XLATE_ADDR_TO_ID ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_PB_CFG_EAST_A_INDIRECT_EN , 49 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_A_INDIRECT_EN ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_A_GATHER_ENABLE , 50 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_A_GATHER_ENABLE ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_PHYP_IS_GROUP , 52 , SH_UNT , SH_ACS_SCOM , @@ -62252,6 +66077,8 @@ REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_A_CMD_RATE , 56 , SH_UN REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_A_CMD_RATE_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_A_CMD_RATE_LEN ); +REG64_FLD( PU_PB_EAST_MODE_PB_EAST_PBIXXX_INIT , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_EAST_PBIXXX_INIT ); REG64_FLD( PU_PB_EAST_MODE_CFG_CHIP_IS_SYSTEM , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_CHIP_IS_SYSTEM ); REG64_FLD( PU_PB_EAST_MODE_CFG_HNG_CHK_DISABLE , 8 , SH_UNT , SH_ACS_SCOM , @@ -62274,12 +66101,18 @@ REG64_FLD( PU_PB_EAST_MODE_CFG_LCL_HW_MARK , 30 , SH_UN SH_FLD_CFG_LCL_HW_MARK ); REG64_FLD( PU_PB_EAST_MODE_CFG_LCL_HW_MARK_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LCL_HW_MARK_LEN ); +REG64_FLD( PU_PB_EAST_MODE_PB_CFG_EAST_CPU_RATIO_OVERRIDE , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_CPU_RATIO_OVERRIDE ); +REG64_FLD( PU_PB_EAST_MODE_PB_CFG_EAST_CPU_RATIO_OVERRIDE_LEN , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_CPU_RATIO_OVERRIDE_LEN ); REG64_FLD( PU_PB_EAST_MODE_CFG_REQ_GATHER_ENABLE , 57 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_REQ_GATHER_ENABLE ); REG64_FLD( PU_PB_EAST_MODE_CFG_SWITCH_CD_PULSE , 58 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_SWITCH_CD_PULSE ); REG64_FLD( PU_PB_EAST_MODE_CFG_SWITCH_OPTION_AB , 59 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_SWITCH_OPTION_AB ); +REG64_FLD( PU_PB_EAST_MODE_PB_CFG_EAST_RESET_ERROR_CAPTURE , 63 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_RESET_ERROR_CAPTURE ); REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG ); @@ -62298,6 +66131,11 @@ REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_DATA , 12 , SH_UN REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_DATA_LEN , 52 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_SHIFT_DATA_LEN ); +REG64_FLD( PU_PB_EAST_SPARE_SPARE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE ); +REG64_FLD( PU_PB_EAST_SPARE_SPARE_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LEN ); + REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_LIMIT , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK0_DOB_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , @@ -62385,6 +66223,32 @@ REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT , 49 , SH_UN REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK5_DOB_VC1_LIMIT_LEN ); +REG64_FLD( PU_PB_ELINK_DLY_0123_REG_FMR0_LINK_DELAY , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_LINK_DELAY ); +REG64_FLD( PU_PB_ELINK_DLY_0123_REG_FMR0_LINK_DELAY_LEN , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_LINK_DELAY_LEN ); +REG64_FLD( PU_PB_ELINK_DLY_0123_REG_FMR1_LINK_DELAY , 20 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_LINK_DELAY ); +REG64_FLD( PU_PB_ELINK_DLY_0123_REG_FMR1_LINK_DELAY_LEN , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_LINK_DELAY_LEN ); +REG64_FLD( PU_PB_ELINK_DLY_0123_REG_FMR2_LINK_DELAY , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_LINK_DELAY ); +REG64_FLD( PU_PB_ELINK_DLY_0123_REG_FMR2_LINK_DELAY_LEN , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_LINK_DELAY_LEN ); +REG64_FLD( PU_PB_ELINK_DLY_0123_REG_FMR3_LINK_DELAY , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_LINK_DELAY ); +REG64_FLD( PU_PB_ELINK_DLY_0123_REG_FMR3_LINK_DELAY_LEN , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_LINK_DELAY_LEN ); + +REG64_FLD( PU_PB_ELINK_DLY_45_REG_FMR4_LINK_DELAY , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_LINK_DELAY ); +REG64_FLD( PU_PB_ELINK_DLY_45_REG_FMR4_LINK_DELAY_LEN , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_LINK_DELAY_LEN ); +REG64_FLD( PU_PB_ELINK_DLY_45_REG_FMR5_LINK_DELAY , 20 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_LINK_DELAY ); +REG64_FLD( PU_PB_ELINK_DLY_45_REG_FMR5_LINK_DELAY_LEN , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_LINK_DELAY_LEN ); + REG64_FLD( PU_PB_ELINK_PMU0_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); REG64_FLD( PU_PB_ELINK_PMU0_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, @@ -62626,11 +66490,652 @@ REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_SET , 0 , SH_UN SH_FLD_SET ); REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_SET_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_SET_LEN ); +REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_RT_SPARE0 , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RT_SPARE0 ); +REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_RT_SPARE0_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RT_SPARE0_LEN ); REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_STAT , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_STAT ); REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_STAT_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_STAT_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN0 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN0 ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN0_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN0_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN1 , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN1 ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN1_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN1_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN2 , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN2 ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN2_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN2_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN3 , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN3 ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN3_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN3_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN0 , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN0 ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN0_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN0_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN1 , 40 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN1 ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN1_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN1_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN2 , 48 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN2 ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN2_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN2_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN3 , 56 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN3 ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN3_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN3_LEN ); + +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN0 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN0 ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN0_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN0_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN1 , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN1 ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN1_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN1_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN2 , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN2 ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN2_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN2_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN3 , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN3 ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN3_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN3_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN0 , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN0 ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN0_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN0_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN1 , 40 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN1 ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN1_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN1_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN2 , 48 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN2 ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN2_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN2_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN3 , 56 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN3 ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN3_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN3_LEN ); + +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN0 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN0 ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN0_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN0_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN1 , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN1 ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN1_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN1_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN2 , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN2 ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN2_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN2_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN3 , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN3 ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN3_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN3_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN0 , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN0 ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN0_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN0_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN1 , 40 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN1 ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN1_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN1_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN2 , 48 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN2 ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN2_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN2_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN3 , 56 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN3 ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN3_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN3_LEN ); + +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB01_UE , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_UE ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB01_UE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_UE_LEN ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB01_CE , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_CE ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB01_CE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_CE_LEN ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB01_SUE , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SUE ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB01_SUE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SUE_LEN ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB23_UE , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB23_UE ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB23_UE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB23_UE_LEN ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB23_CE , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB23_CE ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB23_CE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB23_CE_LEN ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB23_SUE , 20 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB23_SUE ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB23_SUE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB23_SUE_LEN ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB45_UE , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB45_UE ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB45_UE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB45_UE_LEN ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB45_CE , 28 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB45_CE ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB45_CE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB45_CE_LEN ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB45_SUE , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB45_SUE ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB45_SUE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB45_SUE_LEN ); + +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_UE , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_UE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_UE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_UE_LEN ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_CE , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_CE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_CE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_CE_LEN ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_SUE , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SUE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_SUE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SUE_LEN ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_UE , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB23_UE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_UE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB23_UE_LEN ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_CE , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB23_CE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_CE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB23_CE_LEN ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_SUE , 20 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB23_SUE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_SUE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB23_SUE_LEN ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_UE , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB45_UE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_UE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB45_UE_LEN ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_CE , 28 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB45_CE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_CE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB45_CE_LEN ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_SUE , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB45_SUE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_SUE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB45_SUE_LEN ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_UE , 36 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB67_UE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_UE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB67_UE_LEN ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_CE , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB67_CE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_CE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB67_CE_LEN ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_SUE , 44 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB67_SUE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_SUE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB67_SUE_LEN ); + +REG64_FLD( PU_PB_FM0123_ERR_FMR0_CONTROL_ERROR , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_CONTROL_ERROR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_ADDR_PERR , 1 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_ADDR_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_CC0_CREDITERR , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_CC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_CC1_CREDITERR , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_CC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_CC2_CREDITERR , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_CC2_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_CC3_CREDITERR , 5 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_CC3_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_DAT_HI_PERR , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_DAT_HI_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_DAT_LO_PERR , 7 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_DAT_LO_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_FRAME_CREDITERR , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_FRAME_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_PC0_CREDITERR , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_PC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_PC1_CREDITERR , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_PC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_PRSP_PTYERR , 11 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_PRSP_PTYERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_TTAG_PERR , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_TTAG_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_VC0_CREDITERR , 13 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_VC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_VC1_CREDITERR , 14 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_VC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_RTAG_PTYERR , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_RTAG_PTYERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_CONTROL_ERROR , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_CONTROL_ERROR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_ADDR_PERR , 17 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_ADDR_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_CC0_CREDITERR , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_CC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_CC1_CREDITERR , 19 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_CC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_CC2_CREDITERR , 20 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_CC2_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_CC3_CREDITERR , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_CC3_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_DAT_HI_PERR , 22 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_DAT_HI_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_DAT_LO_PERR , 23 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_DAT_LO_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_FRAME_CREDITERR , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_FRAME_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_PC0_CREDITERR , 25 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_PC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_PC1_CREDITERR , 26 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_PC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_PRSP_PTYERR , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_PRSP_PTYERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_TTAG_PERR , 28 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_TTAG_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_VC0_CREDITERR , 29 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_VC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_VC1_CREDITERR , 30 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_VC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_RTAG_PTYERR , 31 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_RTAG_PTYERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_CONTROL_ERROR , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_CONTROL_ERROR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_ADDR_PERR , 33 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_ADDR_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_CC0_CREDITERR , 34 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_CC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_CC1_CREDITERR , 35 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_CC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_CC2_CREDITERR , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_CC2_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_CC3_CREDITERR , 37 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_CC3_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_DAT_HI_PERR , 38 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_DAT_HI_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_DAT_LO_PERR , 39 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_DAT_LO_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_FRAME_CREDITERR , 40 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_FRAME_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_PC0_CREDITERR , 41 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_PC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_PC1_CREDITERR , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_PC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_PRSP_PTYERR , 43 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_PRSP_PTYERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_TTAG_PERR , 44 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_TTAG_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_VC0_CREDITERR , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_VC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_VC1_CREDITERR , 46 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_VC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_RTAG_PTYERR , 47 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_RTAG_PTYERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_CONTROL_ERROR , 48 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_CONTROL_ERROR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_ADDR_PERR , 49 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_ADDR_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_CC0_CREDITERR , 50 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_CC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_CC1_CREDITERR , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_CC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_CC2_CREDITERR , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_CC2_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_CC3_CREDITERR , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_CC3_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_DAT_HI_PERR , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_DAT_HI_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_DAT_LO_PERR , 55 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_DAT_LO_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_FRAME_CREDITERR , 56 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_FRAME_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_PC0_CREDITERR , 57 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_PC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_PC1_CREDITERR , 58 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_PC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_PRSP_PTYERR , 59 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_PRSP_PTYERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_TTAG_PERR , 60 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_TTAG_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_VC0_CREDITERR , 61 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_VC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_VC1_CREDITERR , 62 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_VC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_RTAG_PTYERR , 63 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_RTAG_PTYERR ); + +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_CONTROL_ERROR , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_ADDR_PERR , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_ADDR_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_CC0_CREDITERR , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_CC1_CREDITERR , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_CC2_CREDITERR , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_CC3_CREDITERR , 5 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_DAT_HI_PERR , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_DAT_HI_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_DAT_LO_PERR , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_DAT_LO_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_FRAME_CREDITERR , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_FRAME_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_PC0_CREDITERR , 9 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_PC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_PC1_CREDITERR , 10 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_PC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_PRSP_PTYERR , 11 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_PRSP_PTYERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_TTAG_PERR , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_TTAG_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_VC0_CREDITERR , 13 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_VC1_CREDITERR , 14 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_RTAG_PTYERR , 15 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_RTAG_PTYERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_CONTROL_ERROR , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_ADDR_PERR , 17 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_ADDR_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_CC0_CREDITERR , 18 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_CC1_CREDITERR , 19 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_CC2_CREDITERR , 20 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_CC3_CREDITERR , 21 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_DAT_HI_PERR , 22 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_DAT_HI_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_DAT_LO_PERR , 23 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_DAT_LO_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_FRAME_CREDITERR , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_FRAME_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_PC0_CREDITERR , 25 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_PC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_PC1_CREDITERR , 26 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_PC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_PRSP_PTYERR , 27 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_PRSP_PTYERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_TTAG_PERR , 28 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_TTAG_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_VC0_CREDITERR , 29 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_VC1_CREDITERR , 30 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_RTAG_PTYERR , 31 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_RTAG_PTYERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_CONTROL_ERROR , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_ADDR_PERR , 33 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_ADDR_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_CC0_CREDITERR , 34 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_CC1_CREDITERR , 35 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_CC2_CREDITERR , 36 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_CC3_CREDITERR , 37 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_DAT_HI_PERR , 38 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_DAT_HI_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_DAT_LO_PERR , 39 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_DAT_LO_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_FRAME_CREDITERR , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_FRAME_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_PC0_CREDITERR , 41 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_PC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_PC1_CREDITERR , 42 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_PC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_PRSP_PTYERR , 43 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_PRSP_PTYERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_TTAG_PERR , 44 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_TTAG_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_VC0_CREDITERR , 45 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_VC1_CREDITERR , 46 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_RTAG_PTYERR , 47 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_RTAG_PTYERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_CONTROL_ERROR , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_ADDR_PERR , 49 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_ADDR_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_CC0_CREDITERR , 50 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_CC1_CREDITERR , 51 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_CC2_CREDITERR , 52 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_CC3_CREDITERR , 53 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_DAT_HI_PERR , 54 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_DAT_HI_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_DAT_LO_PERR , 55 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_DAT_LO_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_FRAME_CREDITERR , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_FRAME_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_PC0_CREDITERR , 57 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_PC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_PC1_CREDITERR , 58 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_PC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_PRSP_PTYERR , 59 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_PRSP_PTYERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_TTAG_PERR , 60 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_TTAG_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_VC0_CREDITERR , 61 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_VC1_CREDITERR , 62 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_RTAG_PTYERR , 63 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_RTAG_PTYERR ); + +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_CONTROL_ERROR , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_ADDR_PERR , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_ADDR_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_CC0_CREDITERR , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_CC1_CREDITERR , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_CC2_CREDITERR , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_CC3_CREDITERR , 5 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_DAT_HI_PERR , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_DAT_HI_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_DAT_LO_PERR , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_DAT_LO_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_FRAME_CREDITERR , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_FRAME_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_PC0_CREDITERR , 9 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_PC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_PC1_CREDITERR , 10 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_PC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_PRSP_PTYERR , 11 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_PRSP_PTYERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_TTAG_PERR , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_TTAG_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_VC0_CREDITERR , 13 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_VC1_CREDITERR , 14 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_RTAG_PTYERR , 15 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_RTAG_PTYERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_CONTROL_ERROR , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_ADDR_PERR , 17 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_ADDR_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_CC0_CREDITERR , 18 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_CC1_CREDITERR , 19 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_CC2_CREDITERR , 20 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_CC3_CREDITERR , 21 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_DAT_HI_PERR , 22 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_DAT_HI_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_DAT_LO_PERR , 23 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_DAT_LO_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_FRAME_CREDITERR , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_FRAME_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_PC0_CREDITERR , 25 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_PC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_PC1_CREDITERR , 26 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_PC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_PRSP_PTYERR , 27 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_PRSP_PTYERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_TTAG_PERR , 28 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_TTAG_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_VC0_CREDITERR , 29 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_VC1_CREDITERR , 30 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_RTAG_PTYERR , 31 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_RTAG_PTYERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_CONTROL_ERROR , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_ADDR_PERR , 33 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_ADDR_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_CC0_CREDITERR , 34 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_CC1_CREDITERR , 35 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_CC2_CREDITERR , 36 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_CC3_CREDITERR , 37 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_DAT_HI_PERR , 38 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_DAT_HI_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_DAT_LO_PERR , 39 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_DAT_LO_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_FRAME_CREDITERR , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_FRAME_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_PC0_CREDITERR , 41 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_PC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_PC1_CREDITERR , 42 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_PC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_PRSP_PTYERR , 43 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_PRSP_PTYERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_TTAG_PERR , 44 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_TTAG_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_VC0_CREDITERR , 45 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_VC1_CREDITERR , 46 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_RTAG_PTYERR , 47 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_RTAG_PTYERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_CONTROL_ERROR , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_ADDR_PERR , 49 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_ADDR_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_CC0_CREDITERR , 50 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_CC1_CREDITERR , 51 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_CC2_CREDITERR , 52 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_CC3_CREDITERR , 53 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_DAT_HI_PERR , 54 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_DAT_HI_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_DAT_LO_PERR , 55 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_DAT_LO_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_FRAME_CREDITERR , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_FRAME_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_PC0_CREDITERR , 57 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_PC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_PC1_CREDITERR , 58 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_PC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_PRSP_PTYERR , 59 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_PRSP_PTYERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_TTAG_PERR , 60 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_TTAG_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_VC0_CREDITERR , 61 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_VC1_CREDITERR , 62 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_RTAG_PTYERR , 63 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_RTAG_PTYERR ); + +REG64_FLD( PU_PB_FM45_ERR_FMR4_CONTROL_ERROR , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_CONTROL_ERROR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_ADDR_PERR , 1 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_ADDR_PERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_CC0_CREDITERR , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_CC0_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_CC1_CREDITERR , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_CC1_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_CC2_CREDITERR , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_CC2_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_CC3_CREDITERR , 5 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_CC3_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_DAT_HI_PERR , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_DAT_HI_PERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_DAT_LO_PERR , 7 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_DAT_LO_PERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_FRAME_CREDITERR , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_FRAME_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_PC0_CREDITERR , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_PC0_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_PC1_CREDITERR , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_PC1_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_PRSP_PTYERR , 11 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_PRSP_PTYERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_TTAG_PERR , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_TTAG_PERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_VC0_CREDITERR , 13 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_VC0_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_VC1_CREDITERR , 14 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_VC1_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_RTAG_PTYERR , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_RTAG_PTYERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_CONTROL_ERROR , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_CONTROL_ERROR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_ADDR_PERR , 17 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_ADDR_PERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_CC0_CREDITERR , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_CC0_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_CC1_CREDITERR , 19 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_CC1_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_CC2_CREDITERR , 20 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_CC2_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_CC3_CREDITERR , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_CC3_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_DAT_HI_PERR , 22 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_DAT_HI_PERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_DAT_LO_PERR , 23 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_DAT_LO_PERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_FRAME_CREDITERR , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_FRAME_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_PC0_CREDITERR , 25 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_PC0_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_PC1_CREDITERR , 26 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_PC1_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_PRSP_PTYERR , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_PRSP_PTYERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_TTAG_PERR , 28 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_TTAG_PERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_VC0_CREDITERR , 29 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_VC0_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_VC1_CREDITERR , 30 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_VC1_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_RTAG_PTYERR , 31 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_RTAG_PTYERR ); + REG64_FLD( PU_PB_FP01_CFG_FP0_CREDIT_PRIORITY_4_NOT_8 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP0_CREDIT_PRIORITY_4_NOT_8 ); REG64_FLD( PU_PB_FP01_CFG_FP0_DISABLE_GATHERING , 1 , SH_UNT , SH_ACS_SCOM_RW , @@ -63308,6 +67813,11 @@ REG64_FLD( PU_PB_IOE_FIR_REG_SCOM_ERR_DUP , 62 , SH_UN REG64_FLD( PU_PB_IOE_FIR_REG_SCOM_ERR , 63 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); +REG64_FLD( PU_PB_IOE_FIR_WOF_REG_WOF , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF ); +REG64_FLD( PU_PB_IOE_FIR_WOF_REG_WOF_LEN , 64 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LEN ); + REG64_FLD( PU_IOE_PB_IOO_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( PU_IOE_PB_IOO_FIR_ACTION0_REG_ACTION0_LEN , 64 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , @@ -63568,6 +68078,11 @@ REG64_FLD( PU_IOE_PB_IOO_FIR_REG_SCOM_ERR_DUP , 62 , SH_UN REG64_FLD( PU_IOE_PB_IOO_FIR_REG_SCOM_ERR , 63 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); +REG64_FLD( PU_IOE_PB_IOO_FIR_WOF_REG_WOF , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF ); +REG64_FLD( PU_IOE_PB_IOO_FIR_WOF_REG_WOF_LEN , 64 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LEN ); + REG64_FLD( PU_PB_MISC_CFG_IOE01_IS_LOGICAL_PAIR , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_IOE01_IS_LOGICAL_PAIR ); REG64_FLD( PU_PB_MISC_CFG_IOE23_IS_LOGICAL_PAIR , 1 , SH_UNT , SH_ACS_SCOM , @@ -63770,6 +68285,40 @@ REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC1_LIMIT , 48 , SH_UN REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC1_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK7_DOB_VC1_LIMIT_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_0123_REG_FMR0_LINK_DELAY , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_LINK_DELAY ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_0123_REG_FMR0_LINK_DELAY_LEN , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_LINK_DELAY_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_0123_REG_FMR1_LINK_DELAY , 20 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_LINK_DELAY ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_0123_REG_FMR1_LINK_DELAY_LEN , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_LINK_DELAY_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_0123_REG_FMR2_LINK_DELAY , 36 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_LINK_DELAY ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_0123_REG_FMR2_LINK_DELAY_LEN , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_LINK_DELAY_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_0123_REG_FMR3_LINK_DELAY , 52 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_LINK_DELAY ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_0123_REG_FMR3_LINK_DELAY_LEN , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_LINK_DELAY_LEN ); + +REG64_FLD( PU_IOE_PB_OLINK_DLY_4567_REG_FMR4_LINK_DELAY , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_LINK_DELAY ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_4567_REG_FMR4_LINK_DELAY_LEN , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_LINK_DELAY_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_4567_REG_FMR5_LINK_DELAY , 20 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_LINK_DELAY ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_4567_REG_FMR5_LINK_DELAY_LEN , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_LINK_DELAY_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_4567_REG_FMR6_LINK_DELAY , 36 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_LINK_DELAY ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_4567_REG_FMR6_LINK_DELAY_LEN , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_LINK_DELAY_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_4567_REG_FMR7_LINK_DELAY , 52 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_LINK_DELAY ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_4567_REG_FMR7_LINK_DELAY_LEN , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_LINK_DELAY_LEN ); + REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, @@ -64016,6 +68565,138 @@ REG64_FLD( PU_IOE_PB_OLINK_RT_DELAY_CTL_REG_STAT , 8 , SH_UN REG64_FLD( PU_IOE_PB_OLINK_RT_DELAY_CTL_REG_STAT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_STAT_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN0 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN0_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN0_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN1 , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN1 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN1_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN1_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN2 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN2 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN2_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN2_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN3 , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN3 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN3_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN3_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN0 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN0 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN0_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN0_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN1 , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN1 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN1_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN1_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN2 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN2 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN2_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN2_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN3 , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN3 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN3_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN3_LEN ); + +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN0 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN0_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN0_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN1 , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN1 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN1_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN1_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN2 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN2 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN2_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN2_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN3 , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN3 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN3_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN3_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN0 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN0 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN0_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN0_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN1 , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN1 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN1_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN1_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN2 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN2 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN2_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN2_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN3 , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN3 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN3_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN3_LEN ); + +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN0 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN0_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN0_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN1 , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN1 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN1_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN1_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN2 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN2 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN2_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN2_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN3 , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN3 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN3_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN3_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN0 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN0 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN0_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN0_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN1 , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN1 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN1_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN1_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN2 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN2 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN2_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN2_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN3 , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN3 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN3_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN3_LEN ); + +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB06_SCOM_SYN0 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN0_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB06_SCOM_SYN0_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN1 , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB06_SCOM_SYN1 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN1_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB06_SCOM_SYN1_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN2 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB06_SCOM_SYN2 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN2_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB06_SCOM_SYN2_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN3 , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB06_SCOM_SYN3 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN3_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB06_SCOM_SYN3_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN0 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB07_SCOM_SYN0 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN0_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB07_SCOM_SYN0_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN1 , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB07_SCOM_SYN1 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN1_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB07_SCOM_SYN1_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN2 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB07_SCOM_SYN2 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN2_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB07_SCOM_SYN2_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN3 , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB07_SCOM_SYN3 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN3_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB07_SCOM_SYN3_LEN ); + REG64_FLD( PU_PB_PERFTRACE_CFG_REG_HI_ENABLE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HI_ENABLE ); REG64_FLD( PU_PB_PERFTRACE_CFG_REG_HI_FIXED_WINDOW_MODE , 1 , SH_UNT , SH_ACS_SCOM_RW , @@ -64110,6 +68791,379 @@ REG64_FLD( PU_PB_PPE_LFIRMASK_FIR_MASK , 0 , SH_UN REG64_FLD( PU_PB_PPE_LFIRMASK_FIR_MASK_LEN , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FIR_MASK_LEN ); +REG64_FLD( PU_PB_PPE_LFIRWOF_LFIR_WOF , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_LFIR_WOF ); +REG64_FLD( PU_PB_PPE_LFIRWOF_LFIR_WOF_LEN , 14 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_LFIR_WOF_LEN ); + +REG64_FLD( PU_PB_PR0123_ERR_PRS0_ADDRESS_PTY , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_ADDRESS_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_ATAG_PTY , 1 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_ATAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_CC0_CREDITERR , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_CC0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_CC1_CREDITERR , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_CC1_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_CC2_CREDITERR , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_CC2_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_CC3_CREDITERR , 5 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_CC3_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_CONTROL_ERROR , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_CONTROL_ERROR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_PR0_CREDITERR , 7 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_PR0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_PR1_CREDITERR , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_PR1_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_RTAG_PTY , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_RTAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_TTAG_PTY , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_TTAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_VC0_CREDITERR , 11 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_VC0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_VC1_CREDITERR , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_VC1_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_ADDRESS_PTY , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_ADDRESS_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_ATAG_PTY , 17 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_ATAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_CC0_CREDITERR , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_CC0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_CC1_CREDITERR , 19 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_CC1_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_CC2_CREDITERR , 20 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_CC2_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_CC3_CREDITERR , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_CC3_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_CONTROL_ERROR , 22 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_CONTROL_ERROR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_PR0_CREDITERR , 23 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_PR0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_PR1_CREDITERR , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_PR1_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_RTAG_PTY , 25 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_RTAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_TTAG_PTY , 26 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_TTAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_VC0_CREDITERR , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_VC0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_VC1_CREDITERR , 28 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_VC1_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_ADDRESS_PTY , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_ADDRESS_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_ATAG_PTY , 33 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_ATAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_CC0_CREDITERR , 34 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_CC0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_CC1_CREDITERR , 35 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_CC1_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_CC2_CREDITERR , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_CC2_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_CC3_CREDITERR , 37 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_CC3_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_CONTROL_ERROR , 38 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_CONTROL_ERROR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_PR0_CREDITERR , 39 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_PR0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_PR1_CREDITERR , 40 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_PR1_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_RTAG_PTY , 41 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_RTAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_TTAG_PTY , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_TTAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_VC0_CREDITERR , 43 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_VC0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_VC1_CREDITERR , 44 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_VC1_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_ADDRESS_PTY , 48 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_ADDRESS_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_ATAG_PTY , 49 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_ATAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_CC0_CREDITERR , 50 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_CC0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_CC1_CREDITERR , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_CC1_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_CC2_CREDITERR , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_CC2_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_CC3_CREDITERR , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_CC3_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_CONTROL_ERROR , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_CONTROL_ERROR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_PR0_CREDITERR , 55 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_PR0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_PR1_CREDITERR , 56 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_PR1_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_RTAG_PTY , 57 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_RTAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_TTAG_PTY , 58 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_TTAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_VC0_CREDITERR , 59 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_VC0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_VC1_CREDITERR , 60 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_VC1_CREDITERR ); + +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_ADDRESS_PTY , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_ADDRESS_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_ATAG_PTY , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_ATAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_CC0_CREDITERR , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_CC1_CREDITERR , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_CC2_CREDITERR , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_CC3_CREDITERR , 5 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_CONTROL_ERROR , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_PR0_CREDITERR , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_PR0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_PR1_CREDITERR , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_PR1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_RTAG_PTY , 9 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_RTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_TTAG_PTY , 10 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_TTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_VC0_CREDITERR , 11 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_VC1_CREDITERR , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_ADDRESS_PTY , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_ADDRESS_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_ATAG_PTY , 17 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_ATAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_CC0_CREDITERR , 18 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_CC1_CREDITERR , 19 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_CC2_CREDITERR , 20 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_CC3_CREDITERR , 21 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_CONTROL_ERROR , 22 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_PR0_CREDITERR , 23 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_PR0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_PR1_CREDITERR , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_PR1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_RTAG_PTY , 25 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_RTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_TTAG_PTY , 26 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_TTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_VC0_CREDITERR , 27 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_VC1_CREDITERR , 28 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_ADDRESS_PTY , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_ADDRESS_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_ATAG_PTY , 33 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_ATAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_CC0_CREDITERR , 34 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_CC1_CREDITERR , 35 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_CC2_CREDITERR , 36 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_CC3_CREDITERR , 37 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_CONTROL_ERROR , 38 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_PR0_CREDITERR , 39 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_PR0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_PR1_CREDITERR , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_PR1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_RTAG_PTY , 41 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_RTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_TTAG_PTY , 42 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_TTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_VC0_CREDITERR , 43 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_VC1_CREDITERR , 44 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_ADDRESS_PTY , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_ADDRESS_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_ATAG_PTY , 49 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_ATAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_CC0_CREDITERR , 50 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_CC1_CREDITERR , 51 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_CC2_CREDITERR , 52 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_CC3_CREDITERR , 53 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_CONTROL_ERROR , 54 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_PR0_CREDITERR , 55 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_PR0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_PR1_CREDITERR , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_PR1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_RTAG_PTY , 57 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_RTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_TTAG_PTY , 58 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_TTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_VC0_CREDITERR , 59 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_VC1_CREDITERR , 60 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_VC1_CREDITERR ); + +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_ADDRESS_PTY , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_ADDRESS_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_ATAG_PTY , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_ATAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_CC0_CREDITERR , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_CC1_CREDITERR , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_CC2_CREDITERR , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_CC3_CREDITERR , 5 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_CONTROL_ERROR , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_PR0_CREDITERR , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_PR0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_PR1_CREDITERR , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_PR1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_RTAG_PTY , 9 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_RTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_TTAG_PTY , 10 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_TTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_VC0_CREDITERR , 11 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_VC1_CREDITERR , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_ADDRESS_PTY , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_ADDRESS_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_ATAG_PTY , 17 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_ATAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_CC0_CREDITERR , 18 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_CC1_CREDITERR , 19 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_CC2_CREDITERR , 20 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_CC3_CREDITERR , 21 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_CONTROL_ERROR , 22 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_PR0_CREDITERR , 23 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_PR0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_PR1_CREDITERR , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_PR1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_RTAG_PTY , 25 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_RTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_TTAG_PTY , 26 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_TTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_VC0_CREDITERR , 27 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_VC1_CREDITERR , 28 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_ADDRESS_PTY , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_ADDRESS_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_ATAG_PTY , 33 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_ATAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_CC0_CREDITERR , 34 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_CC1_CREDITERR , 35 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_CC2_CREDITERR , 36 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_CC3_CREDITERR , 37 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_CONTROL_ERROR , 38 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_PR0_CREDITERR , 39 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_PR0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_PR1_CREDITERR , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_PR1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_RTAG_PTY , 41 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_RTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_TTAG_PTY , 42 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_TTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_VC0_CREDITERR , 43 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_VC1_CREDITERR , 44 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_ADDRESS_PTY , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_ADDRESS_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_ATAG_PTY , 49 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_ATAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_CC0_CREDITERR , 50 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_CC1_CREDITERR , 51 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_CC2_CREDITERR , 52 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_CC3_CREDITERR , 53 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_CONTROL_ERROR , 54 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_PR0_CREDITERR , 55 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_PR0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_PR1_CREDITERR , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_PR1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_RTAG_PTY , 57 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_RTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_TTAG_PTY , 58 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_TTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_VC0_CREDITERR , 59 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_VC1_CREDITERR , 60 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_VC1_CREDITERR ); + +REG64_FLD( PU_PB_PR45_ERR_PRS4_ADDRESS_PTY , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_ADDRESS_PTY ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_ATAG_PTY , 1 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_ATAG_PTY ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_CC0_CREDITERR , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_CC0_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_CC1_CREDITERR , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_CC1_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_CC2_CREDITERR , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_CC2_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_CC3_CREDITERR , 5 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_CC3_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_CONTROL_ERROR , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_CONTROL_ERROR ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_PR0_CREDITERR , 7 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_PR0_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_PR1_CREDITERR , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_PR1_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_RTAG_PTY , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_RTAG_PTY ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_TTAG_PTY , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_TTAG_PTY ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_VC0_CREDITERR , 11 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_VC0_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_VC1_CREDITERR , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_VC1_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_ADDRESS_PTY , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_ADDRESS_PTY ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_ATAG_PTY , 17 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_ATAG_PTY ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_CC0_CREDITERR , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_CC0_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_CC1_CREDITERR , 19 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_CC1_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_CC2_CREDITERR , 20 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_CC2_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_CC3_CREDITERR , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_CC3_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_CONTROL_ERROR , 22 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_CONTROL_ERROR ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_PR0_CREDITERR , 23 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_PR0_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_PR1_CREDITERR , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_PR1_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_RTAG_PTY , 25 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_RTAG_PTY ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_TTAG_PTY , 26 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_TTAG_PTY ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_VC0_CREDITERR , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_VC0_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_VC1_CREDITERR , 28 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_VC1_CREDITERR ); + REG64_FLD( PU_PB_PSAVE_CFG_ENABLE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_PB_PSAVE_CFG_X0_ACT , 1 , SH_UNT , SH_ACS_SCOM , @@ -64166,6 +69220,396 @@ REG64_FLD( PU_PB_PSAVE_MON_CFG_X2_HI , 43 , SH_UN REG64_FLD( PU_PB_PSAVE_MON_CFG_X2_HI_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_X2_HI_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_00 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_00_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_01 , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_01_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_02 , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_02_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_03 , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_03_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_04 , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_04_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_05 , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_05_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_06 , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_06_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_07 , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_07_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_08 , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_08_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_09 , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_09_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_10 , 30 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_10_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_11 , 33 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_11_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_12 , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_12_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_13 , 39 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_13_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_14 , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_14_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_15 , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_15_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15_LEN ); + +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_00 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_00_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_01 , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_01_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_02 , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_02_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_03 , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_03_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_04 , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_04_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_05 , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_05_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_06 , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_06_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_07 , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_07_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_08 , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_08_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_09 , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_09_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_10 , 30 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_10_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_11 , 33 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_11_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_12 , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_12_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_13 , 39 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_13_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_14 , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_14_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_15 , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_15_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15_LEN ); + +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_00 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_00_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_01 , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_01_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_02 , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_02_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_03 , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_03_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_04 , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_04_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_05 , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_05_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_06 , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_06_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_07 , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_07_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_08 , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_08_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_09 , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_09_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_10 , 30 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_10_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_11 , 33 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_11_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_12 , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_12_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_13 , 39 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_13_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_14 , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_14_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_15 , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_15_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15_LEN ); + +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_00 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_00_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_01 , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_01_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_02 , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_02_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_03 , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_03_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_04 , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_04_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_05 , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_05_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_06 , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_06_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_07 , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_07_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_08 , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_08_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_09 , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_09_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_10 , 30 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_10_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_11 , 33 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_11_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_12 , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_12_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_13 , 39 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_13_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_14 , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_14_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_15 , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_15_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15_LEN ); + +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_00 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_00_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_01 , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_01_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_02 , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_02_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_03 , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_03_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_04 , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_04_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_05 , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_05_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_06 , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_06_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_07 , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_07_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_08 , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_08_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_09 , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_09_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_10 , 30 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_10_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_11 , 33 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_11_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_12 , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_12_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_13 , 39 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_13_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_14 , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_14_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_15 , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_15_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15_LEN ); + +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_00 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_00_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_01 , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_01_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_02 , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_02_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_03 , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_03_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_04 , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_04_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_05 , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_05_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_06 , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_06_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_07 , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_07_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_08 , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_08_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_09 , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_09_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_10 , 30 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_10_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_11 , 33 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_11_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_12 , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_12_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_13 , 39 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_13_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_14 , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_14_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_15 , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_15_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15_LEN ); + REG64_FLD( PU_PB_TRACE_CFG_LINK00_HI , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK00_HI ); REG64_FLD( PU_PB_TRACE_CFG_LINK00_HI_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , @@ -64428,6 +69872,162 @@ REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SCOM_ERR , 32 , SH_UN REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SCOM_ERR_DUP , 33 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH0_PB_WEST_FW_SCRATCH0 , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , + SH_FLD_PB_WEST_FW_SCRATCH0 ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH0_PB_WEST_FW_SCRATCH0_LEN , 64 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , + SH_FLD_PB_WEST_FW_SCRATCH0_LEN ); + +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH1_PB_WEST_FW_SCRATCH1 , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , + SH_FLD_PB_WEST_FW_SCRATCH1 ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH1_PB_WEST_FW_SCRATCH1_LEN , 64 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , + SH_FLD_PB_WEST_FW_SCRATCH1_LEN ); + +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA0_EN , 0 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA0_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA1_EN , 1 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA1_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA2_EN , 2 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA2_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA3_EN , 3 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA3_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA0_EN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA0_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA1_EN , 5 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA1_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA2_EN , 6 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA2_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA3_EN , 7 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA3_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA0_EN , 8 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA0_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA1_EN , 9 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA1_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA2_EN , 10 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA2_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA3_EN , 11 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA3_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA0_GROUPID , 16 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA0_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA1_GROUPID , 20 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA1_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA2_GROUPID , 24 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA2_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA3_GROUPID , 28 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA3_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA0_GROUPID , 32 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA0_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA1_GROUPID , 36 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA1_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA2_GROUPID , 40 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA2_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA3_GROUPID , 44 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA3_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA0_GROUPID , 48 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA0_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA1_GROUPID , 52 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA1_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA2_GROUPID , 56 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA2_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA3_GROUPID , 60 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA3_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA3_GROUPID_LEN ); + +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA0_EN , 0 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA0_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA1_EN , 1 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA1_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA2_EN , 2 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA2_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA3_EN , 3 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA3_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA0_EN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA0_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA1_EN , 5 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA1_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA2_EN , 6 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA2_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA3_EN , 7 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA3_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA0_EN , 8 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA0_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA1_EN , 9 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA1_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA2_EN , 10 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA2_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA3_EN , 11 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA3_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA0_GROUPID , 16 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA0_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA1_GROUPID , 20 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA1_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA2_GROUPID , 24 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA2_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA3_GROUPID , 28 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA3_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA0_GROUPID , 32 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA0_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA1_GROUPID , 36 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA1_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA2_GROUPID , 40 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA2_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA3_GROUPID , 44 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA3_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA0_GROUPID , 48 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA0_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA1_GROUPID , 52 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA1_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA2_GROUPID , 56 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA2_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA3_GROUPID , 60 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA3_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA3_GROUPID_LEN ); + REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X0_EN , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X1_EN , 1 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , @@ -64634,6 +70234,8 @@ REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID , 40 , SH_U SH_FLD_CFG_XLATE_ADDR_TO_ID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_PB_CFG_WEST_A_INDIRECT_EN , 49 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_A_INDIRECT_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_A_GATHER_ENABLE , 50 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_GATHER_ENABLE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_PHYP_IS_GROUP , 52 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , @@ -64717,6 +70319,8 @@ REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID , 40 , SH_U SH_FLD_CFG_XLATE_ADDR_TO_ID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_PB_CFG_WEST_A_INDIRECT_EN , 49 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_A_INDIRECT_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_GATHER_ENABLE , 50 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_GATHER_ENABLE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_PHYP_IS_GROUP , 52 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , @@ -64732,6 +70336,8 @@ REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_CMD_RATE , 56 , SH_UN REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_CMD_RATE_LEN , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_CMD_RATE_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_PB_WEST_PBIXXX_INIT , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_PB_WEST_PBIXXX_INIT ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_CHIP_IS_SYSTEM , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_CHIP_IS_SYSTEM ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_HNG_CHK_DISABLE , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , @@ -64754,16 +70360,18 @@ REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_LCL_HW_MARK , 30 , SH_UN SH_FLD_CFG_LCL_HW_MARK ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_LCL_HW_MARK_LEN , 6 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LCL_HW_MARK_LEN ); -REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_CPU_RATIO_OVERRIDE , 36 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , - SH_FLD_CFG_CPU_RATIO_OVERRIDE ); -REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_CPU_RATIO_OVERRIDE_LEN , 6 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , - SH_FLD_CFG_CPU_RATIO_OVERRIDE_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_PB_CFG_WEST_CPU_RATIO_OVERRIDE , 36 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_PB_CFG_WEST_CPU_RATIO_OVERRIDE ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_PB_CFG_WEST_CPU_RATIO_OVERRIDE_LEN , 6 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_CPU_RATIO_OVERRIDE_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_REQ_GATHER_ENABLE , 57 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_REQ_GATHER_ENABLE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SWITCH_CD_PULSE , 58 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_SWITCH_CD_PULSE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SWITCH_OPTION_AB , 59 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_SWITCH_OPTION_AB ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_PB_CFG_WEST_RESET_ERROR_CAPTURE , 63 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_PB_CFG_WEST_RESET_ERROR_CAPTURE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG ); @@ -64782,6 +70390,11 @@ REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_DATA , 12 , SH_UN REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_DATA_LEN , 52 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_SHIFT_DATA_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SPARE_PB_WEST_SPARE , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_PB_WEST_SPARE ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SPARE_PB_WEST_SPARE_LEN , 64 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_PB_WEST_SPARE_LEN ); + REG64_FLD( PEC_PCS_M1_CONTROL_REG_CONTROL , 48 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CONTROL ); REG64_FLD( PEC_PCS_M1_CONTROL_REG_CONTROL_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM , @@ -64825,6 +70438,63 @@ REG64_FLD( PEC_PECAPP_SEC_BAR_PE_CAPP , 0 , SH_UN REG64_FLD( PEC_PECAPP_SEC_BAR_PE_CAPP_LEN , 26 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PE_CAPP_LEN ); +REG64_FLD( PHB_PERF_CFG_REG_CNT_EN , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_CNT_EN ); +REG64_FLD( PHB_PERF_CFG_REG_STOP_CORR_EN , 4 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_STOP_CORR_EN ); +REG64_FLD( PHB_PERF_CFG_REG_CNT0_LE_EN , 6 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_CNT0_LE_EN ); +REG64_FLD( PHB_PERF_CFG_REG_CNT1_LE_EN , 7 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_CNT1_LE_EN ); +REG64_FLD( PHB_PERF_CFG_REG_CNT2_LE_EN , 8 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_CNT2_LE_EN ); +REG64_FLD( PHB_PERF_CFG_REG_CNT3_LE_EN , 9 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_CNT3_LE_EN ); +REG64_FLD( PHB_PERF_CFG_REG_CNT0_TE_EN , 10 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_CNT0_TE_EN ); +REG64_FLD( PHB_PERF_CFG_REG_CNT1_TE_EN , 11 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_CNT1_TE_EN ); +REG64_FLD( PHB_PERF_CFG_REG_CNT2_TE_EN , 12 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_CNT2_TE_EN ); +REG64_FLD( PHB_PERF_CFG_REG_CNT3_TE_EN , 13 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_CNT3_TE_EN ); +REG64_FLD( PHB_PERF_CFG_REG_COUNT0_EVENT , 18 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT0_EVENT ); +REG64_FLD( PHB_PERF_CFG_REG_COUNT0_EVENT_LEN , 6 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT0_EVENT_LEN ); +REG64_FLD( PHB_PERF_CFG_REG_COUNT1_EVENT , 26 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT1_EVENT ); +REG64_FLD( PHB_PERF_CFG_REG_COUNT1_EVENT_LEN , 6 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT1_EVENT_LEN ); +REG64_FLD( PHB_PERF_CFG_REG_COUNT2_EVENT , 33 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT2_EVENT ); +REG64_FLD( PHB_PERF_CFG_REG_COUNT2_EVENT_LEN , 7 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT2_EVENT_LEN ); +REG64_FLD( PHB_PERF_CFG_REG_COUNT3_EVENT , 42 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT3_EVENT ); +REG64_FLD( PHB_PERF_CFG_REG_COUNT3_EVENT_LEN , 6 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT3_EVENT_LEN ); + +REG64_FLD( PHB_PERF_CNT0_REG_COUNT0_VALUE , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT0_VALUE ); +REG64_FLD( PHB_PERF_CNT0_REG_COUNT0_VALUE_LEN , 48 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT0_VALUE_LEN ); + +REG64_FLD( PHB_PERF_CNT1_REG_COUNT1_VALUE , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT1_VALUE ); +REG64_FLD( PHB_PERF_CNT1_REG_COUNT1_VALUE_LEN , 48 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT1_VALUE_LEN ); + +REG64_FLD( PHB_PERF_CNT2_REG_COUNT2_VALUE , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT2_VALUE ); +REG64_FLD( PHB_PERF_CNT2_REG_COUNT2_VALUE_LEN , 48 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT2_VALUE_LEN ); + +REG64_FLD( PHB_PERF_CNT3_REG_COUNT3_VALUE , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT3_VALUE ); +REG64_FLD( PHB_PERF_CNT3_REG_COUNT3_VALUE_LEN , 48 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT3_VALUE_LEN ); + REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_LATSTART ); REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , @@ -66085,6 +71755,46 @@ REG64_FLD( PU_PBAIB_STACK1_PFIR_REG_PFIRPFIR , 0 , SH_UN REG64_FLD( PU_PBAIB_STACK1_PFIR_REG_PFIRPFIR_LEN , 7 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PFIRPFIR_LEN ); +REG64_FLD( PHB_PHB4_SCOM_HVIAR_HV_REQ_ADDR_VLD , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_HV_REQ_ADDR_VLD ); +REG64_FLD( PHB_PHB4_SCOM_HVIAR_HV_REQ_4B , 1 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_HV_REQ_4B ); +REG64_FLD( PHB_PHB4_SCOM_HVIAR_HV_AUTO_INC , 2 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_HV_AUTO_INC ); +REG64_FLD( PHB_PHB4_SCOM_HVIAR_HV_REQ_ADDR_VALUE , 51 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_HV_REQ_ADDR_VALUE ); +REG64_FLD( PHB_PHB4_SCOM_HVIAR_HV_REQ_ADDR_VALUE_LEN , 11 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_HV_REQ_ADDR_VALUE_LEN ); + +REG64_FLD( PHB_PHB4_SCOM_HVIDR_SCOM_HV_REQ_READ_DATA , 0 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_SCOM_HV_REQ_READ_DATA ); +REG64_FLD( PHB_PHB4_SCOM_HVIDR_SCOM_HV_REQ_READ_DATA_LEN , 64 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_SCOM_HV_REQ_READ_DATA_LEN ); + +REG64_FLD( PHB_PHB4_SCOM_HVIDWR_SCOM_HV_REQ_WRITE_DATA , 0 , SH_UNT_PHB , SH_ACS_SCOM_WO , + SH_FLD_SCOM_HV_REQ_WRITE_DATA ); +REG64_FLD( PHB_PHB4_SCOM_HVIDWR_SCOM_HV_REQ_WRITE_DATA_LEN , 64 , SH_UNT_PHB , SH_ACS_SCOM_WO , + SH_FLD_SCOM_HV_REQ_WRITE_DATA_LEN ); + +REG64_FLD( PHB_PHB4_SCOM_UVIAR_UV_REQ_ADDR_VLD , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_UV_REQ_ADDR_VLD ); +REG64_FLD( PHB_PHB4_SCOM_UVIAR_UV_AUTO_INC , 2 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_UV_AUTO_INC ); +REG64_FLD( PHB_PHB4_SCOM_UVIAR_UV_REQ_ADDR_VALUE , 52 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_UV_REQ_ADDR_VALUE ); +REG64_FLD( PHB_PHB4_SCOM_UVIAR_UV_REQ_ADDR_VALUE_LEN , 9 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_UV_REQ_ADDR_VALUE_LEN ); + +REG64_FLD( PHB_PHB4_SCOM_UVIDR_SCOM_UV_REQ_READ_DATA , 0 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_SCOM_UV_REQ_READ_DATA ); +REG64_FLD( PHB_PHB4_SCOM_UVIDR_SCOM_UV_REQ_READ_DATA_LEN , 64 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_SCOM_UV_REQ_READ_DATA_LEN ); + +REG64_FLD( PHB_PHB4_SCOM_UVIDWR_SCOM_UV_REQ_WRITE_DATA , 0 , SH_UNT_PHB , SH_ACS_SCOM_WO , + SH_FLD_SCOM_UV_REQ_WRITE_DATA ); +REG64_FLD( PHB_PHB4_SCOM_UVIDWR_SCOM_UV_REQ_WRITE_DATA_LEN , 64 , SH_UNT_PHB , SH_ACS_SCOM_WO , + SH_FLD_SCOM_UV_REQ_WRITE_DATA_LEN ); + REG64_FLD( PEC_STACK2_PHBBAR_REG_PE_PHB_BAR , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , SH_FLD_PE_PHB_BAR ); REG64_FLD( PEC_STACK2_PHBBAR_REG_PE_PHB_BAR_LEN , 42 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , @@ -66491,6 +72201,8 @@ REG64_FLD( PU_PIBMEM_STATUS_REG_ECC_UNCORRECTED_ERROR_PIB , 3 , SH_UN SH_FLD_ECC_UNCORRECTED_ERROR_PIB ); REG64_FLD( PU_PIBMEM_STATUS_REG_ECC_CORRECTED_ERROR_PIB , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_CORRECTED_ERROR_PIB ); +REG64_FLD( PU_PIBMEM_STATUS_REG_BAD_ARRAY_ADDRESS_PIB , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BAD_ARRAY_ADDRESS_PIB ); REG64_FLD( PU_PIBMEM_STATUS_REG_WRITE_RST_INTERRUPT_PIB , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_WRITE_RST_INTERRUPT_PIB ); REG64_FLD( PU_PIBMEM_STATUS_REG_READ_RST_INTERRUPT_PIB , 7 , SH_UNT , SH_ACS_SCOM , @@ -66543,6 +72255,11 @@ REG64_FLD( PU_PIB_RESET_REG_STATE , 1 , SH_UN REG64_FLD( PU_PIB_RESET_REG_ABORTED_CMD , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_ABORTED_CMD ); +REG64_FLD( PEC_PLL_LOCK_REG_LOCK , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_LOCK ); +REG64_FLD( PEC_PLL_LOCK_REG_LOCK_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_LOCK_LEN ); + REG64_FLD( PEC_PMONCTL_REG_PE_PERFMON_EN , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PERFMON_EN ); REG64_FLD( PEC_PMONCTL_REG_PE_PERFMON_EN_LEN , 32 , SH_UNT_PEC , SH_ACS_SCOM_RW , @@ -66551,6 +72268,10 @@ REG64_FLD( PEC_PMONCTL_REG_PE_PERFMON_READ_TYPE , 32 , SH_UN SH_FLD_PE_PERFMON_READ_TYPE ); REG64_FLD( PEC_PMONCTL_REG_PE_PERFMON_READ_TYPE_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PERFMON_READ_TYPE_LEN ); +REG64_FLD( PEC_PMONCTL_REG_RESERVED , 34 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_RESERVED ); +REG64_FLD( PEC_PMONCTL_REG_RESERVED_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_LEN ); REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE0 , 36 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PMON_MUX_BYTE0 ); REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE0_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , @@ -66724,23 +72445,164 @@ REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_3 , 48 , SH_UN REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_3_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_COUNTERB_3_LEN ); +REG64_FLD( PU_PPE_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION0 ); +REG64_FLD( PU_PPE_FIR_ACTION0_REG_ACTION0_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION0_LEN ); + +REG64_FLD( PU_PPE_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION1 ); +REG64_FLD( PU_PPE_FIR_ACTION1_REG_ACTION1_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION1_LEN ); + +REG64_FLD( PU_PPE_FIR_MASK_REG_ERROR , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ERROR ); +REG64_FLD( PU_PPE_FIR_MASK_REG_ERROR_LEN , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ERROR_LEN ); +REG64_FLD( PU_PPE_FIR_MASK_REG_HALTED , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_HALTED ); +REG64_FLD( PU_PPE_FIR_MASK_REG_WATCHDOG_TIMEOUT , 5 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_WATCHDOG_TIMEOUT ); +REG64_FLD( PU_PPE_FIR_MASK_REG_MMIO_DATA_IN , 6 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_MMIO_DATA_IN ); +REG64_FLD( PU_PPE_FIR_MASK_REG_ARB_MISSED_SCRUB_TICK , 7 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ARB_MISSED_SCRUB_TICK ); +REG64_FLD( PU_PPE_FIR_MASK_REG_ARB_ARY_UE , 8 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ARB_ARY_UE ); +REG64_FLD( PU_PPE_FIR_MASK_REG_ARB_ARY_CE , 9 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ARB_ARY_CE ); +REG64_FLD( PU_PPE_FIR_MASK_REG_RESERVED , 10 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED ); +REG64_FLD( PU_PPE_FIR_MASK_REG_INTERNAL_SCOM_ERROR , 11 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR ); +REG64_FLD( PU_PPE_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE , 12 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); + +REG64_FLD( PU_PPE_FIR_REG_ERROR , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ERROR ); +REG64_FLD( PU_PPE_FIR_REG_ERROR_LEN , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ERROR_LEN ); +REG64_FLD( PU_PPE_FIR_REG_HALTED , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_HALTED ); +REG64_FLD( PU_PPE_FIR_REG_WATCHDOG_TIMEOUT , 5 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_WATCHDOG_TIMEOUT ); +REG64_FLD( PU_PPE_FIR_REG_MMIO_DATA_IN , 6 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_MMIO_DATA_IN ); +REG64_FLD( PU_PPE_FIR_REG_ARB_MISSED_SCRUB_TICK , 7 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ARB_MISSED_SCRUB_TICK ); +REG64_FLD( PU_PPE_FIR_REG_ARB_ARY_UE , 8 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ARB_ARY_UE ); +REG64_FLD( PU_PPE_FIR_REG_ARB_ARY_CE , 9 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ARB_ARY_CE ); +REG64_FLD( PU_PPE_FIR_REG_RESERVED , 10 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED ); +REG64_FLD( PU_PPE_FIR_REG_SCOMFIR_ERROR , 11 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SCOMFIR_ERROR ); +REG64_FLD( PU_PPE_FIR_REG_SCOMFIR_ERROR_CLONE , 12 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SCOMFIR_ERROR_CLONE ); + +REG64_FLD( PU_PPE_FIR_WOF_REG_WOF , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF ); +REG64_FLD( PU_PPE_FIR_WOF_REG_WOF_LEN , 13 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LEN ); + +REG64_FLD( PU_PPE_XIDBGPRO_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); - +REG64_FLD( PU_PPE_XIDBGPRO_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); +REG64_FLD( PU_PPE_XIDBGPRO_IAR , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IAR ); +REG64_FLD( PU_PPE_XIDBGPRO_IAR_LEN , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IAR_LEN ); + +REG64_FLD( PU_PPE_XIRAMDBG_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( PU_PPE_XIRAMDBG_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( PU_PPE_XIRAMDBG_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_PPE_XIRAMDBG_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); REG64_FLD( PU_PPE_XIRAMDBG_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( PU_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM , @@ -66829,6 +72691,17 @@ REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_END , 17 , SH_UN REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_END_LEN , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_END_LEN ); +REG64_FLD( PEC_PRDSTKOVR_REG_N_WR_STACK0_OVERRIDE , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_WR_STACK0_OVERRIDE ); +REG64_FLD( PEC_PRDSTKOVR_REG_N_WR_STACK0_OVERRIDE_LEN , 32 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_WR_STACK0_OVERRIDE_LEN ); +REG64_FLD( PEC_PRDSTKOVR_REG_N_WR_STACK1_OVERRIDE , 32 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_WR_STACK1_OVERRIDE ); +REG64_FLD( PEC_PRDSTKOVR_REG_N_WR_STACK1_OVERRIDE_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_WR_STACK1_OVERRIDE_LEN ); +REG64_FLD( PEC_PRDSTKOVR_REG_N_WR_STACK_OVERRIDE_ENABLE , 48 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_WR_STACK_OVERRIDE_ENABLE ); + REG64_FLD( PEC_PREDV_REG_PE_RD_TIMEOUT_MASK , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_RD_TIMEOUT_MASK ); REG64_FLD( PEC_PREDV_REG_PE_RD_TIMEOUT_MASK_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM_RW , @@ -66852,6 +72725,11 @@ REG64_FLD( PU_PRGM_REGISTER_PRG_BIT_LOCATION , 32 , SH_UN REG64_FLD( PU_PRGM_REGISTER_PRG_BIT_LOCATION_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRG_BIT_LOCATION_LEN ); +REG64_FLD( PEC_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PRIMARY_ADDRESS ); +REG64_FLD( PEC_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PRIMARY_ADDRESS_LEN ); + REG64_FLD( PU_NPU2_NTL0_PRI_CONFIG_NDL , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NDL ); REG64_FLD( PU_NPU2_NTL0_PRI_CONFIG_NDL_LEN , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , @@ -67983,6 +73861,68 @@ REG64_FLD( PU_PSIHB_INTERRUPT_CONTROL_ESB_OR_LSI_INTERRUPTS , 0 , SH_UN REG64_FLD( PU_PSIHB_INTERRUPT_CONTROL_SM_RESET , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_SM_RESET ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_PSI_INTERRUPT_HIGH , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PSI_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_OCC_INTERRUPT_HIGH , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_OCC_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_FSI_INTERRUPT_HIGH , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FSI_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_LPC_INTERRUPT_HIGH , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LPC_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_LOCAL_INTERRUPT_HIGH , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_SYSTEM_ATTENTION_HIGH , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SYSTEM_ATTENTION_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_TPM_INTERRUPT_HIGH , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TPM_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_LPC_OTHER_INTERRUPT_HIGH , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LPC_OTHER_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_LPC_OTHER_INTERRUPT_HIGH_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LPC_OTHER_INTERRUPT_HIGH_LEN ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_SBE_OR_I2C_INTERRUPT_HIGH , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SBE_OR_I2C_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_DIO_INTERRUPT_HIGH , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DIO_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_PSU_INTERRUPT_HIGH , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PSU_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_I2C_C_INTERRUPT_HIGH , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_I2C_C_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_I2C_D_INTERRUPT_HIGH , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_I2C_D_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_I2C_E_INTERRUPT_HIGH , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_I2C_E_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_RESERVED , 17 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_RESERVED_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_LEN ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_PURE_SBE_INTERRUPT_HIGH , 19 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PURE_SBE_INTERRUPT_HIGH ); + +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_PSI_INTERRUPT_PENDING , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PSI_INTERRUPT_PENDING ); +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_OCC_INTERRUPT_PENDING , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_OCC_INTERRUPT_PENDING ); +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_FSI_INTERRUPT_PENDING , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FSI_INTERRUPT_PENDING ); +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_LPC_INTERRUPT_PENDING , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LPC_INTERRUPT_PENDING ); +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_LOCAL_INTERRUPT_PENDING , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_INTERRUPT_PENDING ); +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_SYSTEM_ATTENTION , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SYSTEM_ATTENTION ); +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_TPM_INTERRUPT_PENDING , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TPM_INTERRUPT_PENDING ); +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_LPC_OTHER_INTERRUPT_PENDING , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LPC_OTHER_INTERRUPT_PENDING ); +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_LPC_OTHER_INTERRUPT_PENDING_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LPC_OTHER_INTERRUPT_PENDING_LEN ); +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_SBE_INTERRUPT_PENDING , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SBE_INTERRUPT_PENDING ); +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_DIO_INTERRUPT_PENDING , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DIO_INTERRUPT_PENDING ); +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_PSU_INTERRUPT_PENDING , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PSU_INTERRUPT_PENDING ); + REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_CMD_ENABLE , 0 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_FSP_CMD_ENABLE ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_MMIO_ENABLE , 1 , SH_UNT , SH_ACS_SCOM2 , @@ -68576,6 +74516,9 @@ REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP15 , 56 , SH_UN REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP15_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP15_LEN ); +REG64_FLD( PEC_RECOV_INTERRUPT_REG_RECOV , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RECOV ); + REG64_FLD( PU_NPU0_REM0_IBUF_WSRC , 17 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IBUF_WSRC ); REG64_FLD( PU_NPU0_REM0_IBUF_WSRC_LEN , 5 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , @@ -68828,43 +74771,31 @@ REG64_FLD( PEC_RFIR_IN6 , 4 , SH_UN REG64_FLD( PEC_RFIR_IN6_LEN , 20 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN6_LEN ); -REG64_FLD( PU_N3_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_DISABLED ); REG64_FLD( PU_N3_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_N3_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); -REG64_FLD( PU_N1_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_DISABLED ); REG64_FLD( PU_N1_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_N1_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); -REG64_FLD( PU_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT , SH_ACS_SCOM , - SH_FLD_DISABLED ); REG64_FLD( PU_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); -REG64_FLD( PU_N2_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_DISABLED ); REG64_FLD( PU_N2_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_N2_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); -REG64_FLD( PEC_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_DISABLED ); REG64_FLD( PEC_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PEC_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); -REG64_FLD( PU_N0_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_DISABLED ); REG64_FLD( PU_N0_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_N0_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_PU_N0 , SH_ACS_SCOM , @@ -69016,8 +74947,55 @@ REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_END , 17 , SH_UN REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_END_LEN , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_END_LEN ); +REG64_FLD( PU_RX_CH_FSM_REG_RX_CH_FSM , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RX_CH_FSM ); +REG64_FLD( PU_RX_CH_FSM_REG_RX_CH_FSM_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RX_CH_FSM_LEN ); + +REG64_FLD( PU_RX_CH_INTADDR_REG_SCOM_MODE_0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_0 ); +REG64_FLD( PU_RX_CH_INTADDR_REG_SCOM_MODE_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_1 ); +REG64_FLD( PU_RX_CH_INTADDR_REG_SCOM_MODE_2 , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_2 ); +REG64_FLD( PU_RX_CH_INTADDR_REG_SCOM_MODE_3 , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_3 ); +REG64_FLD( PU_RX_CH_INTADDR_REG_SCOM_MODE_4 , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_4 ); +REG64_FLD( PU_RX_CH_INTADDR_REG_SCOM_MODE_5 , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_5 ); +REG64_FLD( PU_RX_CH_INTADDR_REG_SCOM_MODE_6 , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_6 ); +REG64_FLD( PU_RX_CH_INTADDR_REG_SCOM_MODE_7 , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_7 ); + +REG64_FLD( PU_RX_CH_MISC_REG_FSM0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FSM0 ); +REG64_FLD( PU_RX_CH_MISC_REG_FSM0_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FSM0_LEN ); +REG64_FLD( PU_RX_CH_MISC_REG_FSM1 , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FSM1 ); +REG64_FLD( PU_RX_CH_MISC_REG_FSM1_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FSM1_LEN ); +REG64_FLD( PU_RX_CH_MISC_REG_TFRAMESIZE , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TFRAMESIZE ); +REG64_FLD( PU_RX_CH_MISC_REG_TFRAMESIZE_LEN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TFRAMESIZE_LEN ); +REG64_FLD( PU_RX_CH_MISC_REG_WEN0 , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WEN0 ); +REG64_FLD( PU_RX_CH_MISC_REG_WEN1 , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WEN1 ); +REG64_FLD( PU_RX_CH_MISC_REG_WEN2 , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WEN2 ); +REG64_FLD( PU_RX_CH_MISC_REG_EN_SCRD , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_SCRD ); +REG64_FLD( PU_RX_CH_MISC_REG_STTRTOGX , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STTRTOGX ); + REG64_FLD( PU_RX_CTRL_STAT_REG_ENABLE_SCWR_TO_RXRF , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_SCWR_TO_RXRF ); +REG64_FLD( PU_RX_CTRL_STAT_REG_RXSC , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RXSC ); REG64_FLD( PU_RX_CTRL_STAT_REG_DISABLE_ECC_COR_RXRF_PSI , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_ECC_COR_RXRF_PSI ); REG64_FLD( PU_RX_CTRL_STAT_REG_CRC_MODE , 3 , SH_UNT , SH_ACS_SCOM , @@ -69031,6 +75009,77 @@ REG64_FLD( PU_RX_CTRL_STAT_REG_CHIP_INTERFACEMODE , 6 , SH_UN REG64_FLD( PU_RX_CTRL_STAT_REG_CHIP_PERSONALISATION , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHIP_PERSONALISATION ); +REG64_FLD( PU_RX_DBFF_REG0_DATA_BUFF0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DATA_BUFF0 ); +REG64_FLD( PU_RX_DBFF_REG0_DATA_BUFF0_LEN , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DATA_BUFF0_LEN ); + +REG64_FLD( PU_RX_DBFF_REG1_DATA_BUFF1 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DATA_BUFF1 ); +REG64_FLD( PU_RX_DBFF_REG1_DATA_BUFF1_LEN , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DATA_BUFF1_LEN ); + +REG64_FLD( PU_RX_DF_FSM_REG_RX_DF_FSM , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RX_DF_FSM ); +REG64_FLD( PU_RX_DF_FSM_REG_RX_DF_FSM_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RX_DF_FSM_LEN ); + +REG64_FLD( PU_RX_ERROR_REG_C1_PSIRXINS_RFGSHIFT_PCK , 0 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSIRXINS_RFGSHIFT_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C1_PSIRXINS_RZRTMP_PCK , 1 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSIRXINS_RZRTMP_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C1_PSIRXINS_DATA_PCK , 2 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSIRXINS_DATA_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C1_PSIRXEI_SHIFT_PCK , 3 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSIRXEI_SHIFT_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C1_PSIRXEI_TRANSMIT_PCK , 4 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSIRXEI_TRANSMIT_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C1_PSIRXINS_OVERRUN , 5 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSIRXINS_OVERRUN ); +REG64_FLD( PU_RX_ERROR_REG_C1_PSIRXBFF_DATA_PCK , 6 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSIRXBFF_DATA_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C2_PSIRXBFF_DATAO_PCK , 7 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSIRXBFF_DATAO_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C2_PSIRXBFF_RFC_PCK , 8 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSIRXBFF_RFC_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C2_PSIRXLC_FSM_PCK , 9 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSIRXLC_FSM_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C3_PSIRXLC_DATA_BUFF_PCK , 10 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSIRXLC_DATA_BUFF_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C2_PSIRXLC_DATA_PCK , 11 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSIRXLC_DATA_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C2_PSIRXLC_RADDR_PCK , 12 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSIRXLC_RADDR_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C2_PSIRXLC_RCTRL_PCK , 13 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSIRXLC_RCTRL_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C3_PSIRXLC_UE_RF , 14 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSIRXLC_UE_RF ); +REG64_FLD( PU_RX_ERROR_REG_C0_PSIRXLC_CE_RF , 15 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C0_PSIRXLC_CE_RF ); +REG64_FLD( PU_RX_ERROR_REG_C2_PSIRXLC_DATA_GXST1_PCK_2N , 16 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSIRXLC_DATA_GXST1_PCK_2N ); +REG64_FLD( PU_RX_ERROR_REG_C2_PSIRFACC_RADDR_PCK , 17 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSIRFACC_RADDR_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C2_PSIRFACC_RCTRL_PCK , 18 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSIRFACC_RCTRL_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C3_PSIRFACC_RFSM_PCK , 19 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSIRFACC_RFSM_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C3_PSIRFACC_RDL_FSM_PCK , 20 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSIRFACC_RDL_FSM_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C4_PSIRFACC_RXSC_PCK , 21 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C4_PSIRFACC_RXSC_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C0_PSIRFACC_RLINK_STATE_LT_02 , 22 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C0_PSIRFACC_RLINK_STATE_LT_02 ); +REG64_FLD( PU_RX_ERROR_REG_C0_PSIRFACC_C_RXDATA_RDY_ERR , 23 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C0_PSIRFACC_C_RXDATA_RDY_ERR ); +REG64_FLD( PU_RX_ERROR_REG_C0_ERRACK_RISE , 24 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C0_ERRACK_RISE ); + +REG64_FLD( PU_RX_ERR_MODE_RX_ERR_MODE_0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RX_ERR_MODE_0 ); +REG64_FLD( PU_RX_ERR_MODE_RX_ERR_MODE_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RX_ERR_MODE_1 ); + REG64_FLD( PU_RX_MASK_REG_PSIRXINS_RFGSHIFT_PCK , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRXINS_RFGSHIFT_PCK ); REG64_FLD( PU_RX_MASK_REG_PSIRXINS_RZRTMP_PCK , 1 , SH_UNT , SH_ACS_SCOM , @@ -69079,7 +75128,11 @@ REG64_FLD( PU_RX_MASK_REG_PSIRFACC_RLINK_STATE_LT_02 , 22 , SH_UN SH_FLD_PSIRFACC_RLINK_STATE_LT_02 ); REG64_FLD( PU_RX_MASK_REG_PSIRFACC_C_RXDATA_RDY_ERR , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRFACC_C_RXDATA_RDY_ERR ); +REG64_FLD( PU_RX_MASK_REG_C0_ERRACK_RISE , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_C0_ERRACK_RISE ); +REG64_FLD( PU_RX_PSI_CNTL_RX_PSI_IORESET_WO_PULSE_SLOW_SIGNAL , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RX_PSI_IORESET_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( PU_RX_PSI_CNTL_PATTERN_CHECK_EN , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERN_CHECK_EN ); REG64_FLD( PU_RX_PSI_CNTL_PATTERN_SEL , 2 , SH_UNT , SH_ACS_SCOM , @@ -69124,6 +75177,12 @@ REG64_FLD( PU_RX_PSI_MODE_SPARE , 24 , SH_UN REG64_FLD( PU_RX_PSI_MODE_SPARE_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); +REG64_FLD( PU_RX_PSI_STATUS_RX_PSI_PATTERN_CHECK_PASS_RO_SIGNAL , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RX_PSI_PATTERN_CHECK_PASS_RO_SIGNAL ); +REG64_FLD( PU_RX_PSI_STATUS_RX_PSI_PATTERN_CHECK_FAIL_RO_SIGNAL , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RX_PSI_PATTERN_CHECK_FAIL_RO_SIGNAL ); +REG64_FLD( PU_RX_PSI_STATUS_RX_PSI_NO_PATTERN_FOUND_RO_SIGNAL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RX_PSI_NO_PATTERN_FOUND_RO_SIGNAL ); REG64_FLD( PU_RX_PSI_STATUS_LD_UNLD_DLY , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_LD_UNLD_DLY ); REG64_FLD( PU_RX_PSI_STATUS_LD_UNLD_DLY_LEN , 4 , SH_UNT , SH_ACS_SCOM , @@ -69188,6 +75247,83 @@ REG64_FLD( PEC_SCAN_REGION_TYPE_CMSK , 58 , SH_UN REG64_FLD( PEC_SCAN_REGION_TYPE_INEX , 59 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INEX ); +REG64_FLD( PEC_SCOM0X01_SDOCTL , 48 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SDOCTL ); +REG64_FLD( PEC_SCOM0X01_SDOVAL , 49 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SDOVAL ); +REG64_FLD( PEC_SCOM0X01_PCHKEN , 52 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCHKEN ); +REG64_FLD( PEC_SCOM0X01_FRCERR , 53 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FRCERR ); +REG64_FLD( PEC_SCOM0X01_WRPSM , 56 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WRPSM ); +REG64_FLD( PEC_SCOM0X01_WPLPEN , 57 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WPLPEN ); +REG64_FLD( PEC_SCOM0X01_WRPMD , 58 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WRPMD ); +REG64_FLD( PEC_SCOM0X01_PRST , 59 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PRST ); +REG64_FLD( PEC_SCOM0X01_PATSEL , 60 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PATSEL ); +REG64_FLD( PEC_SCOM0X01_PATSEL_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PATSEL_LEN ); + +REG64_FLD( PEC_SCOM0X04_ROTA , 52 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ROTA ); +REG64_FLD( PEC_SCOM0X04_ROTA_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ROTA_LEN ); +REG64_FLD( PEC_SCOM0X04_ROTB , 58 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ROTB ); +REG64_FLD( PEC_SCOM0X04_ROTB_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ROTB_LEN ); + +REG64_FLD( PEC_SCOM0X05_FREQFW , 48 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FREQFW ); +REG64_FLD( PEC_SCOM0X05_FREQFW_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FREQFW_LEN ); +REG64_FLD( PEC_SCOM0X05_FWSNAP , 56 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FWSNAP ); +REG64_FLD( PEC_SCOM0X05_FRCLEL , 57 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FRCLEL ); +REG64_FLD( PEC_SCOM0X05_ROT90 , 58 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ROT90 ); +REG64_FLD( PEC_SCOM0X05_ROT90_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ROT90_LEN ); + +REG64_FLD( PEC_SCOM0X2B_SMQM , 48 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SMQM ); +REG64_FLD( PEC_SCOM0X2B_SMQM_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SMQM_LEN ); +REG64_FLD( PEC_SCOM0X2B_SMQ , 51 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SMQ ); +REG64_FLD( PEC_SCOM0X2B_SMQ_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SMQ_LEN ); +REG64_FLD( PEC_SCOM0X2B_EMMD , 59 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMMD ); +REG64_FLD( PEC_SCOM0X2B_EMMD_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMMD_LEN ); +REG64_FLD( PEC_SCOM0X2B_EMBRDY , 61 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMBRDY ); +REG64_FLD( PEC_SCOM0X2B_EMBUMP , 62 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMBUMP ); +REG64_FLD( PEC_SCOM0X2B_EMEN , 63 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMEN ); + +REG64_FLD( PEC_SCOM0X2C_EMF8 , 48 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMF8 ); +REG64_FLD( PEC_SCOM0X2C_EMSF , 50 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMSF ); +REG64_FLD( PEC_SCOM0X2C_EMCNT , 52 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMCNT ); +REG64_FLD( PEC_SCOM0X2C_EMCNT_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMCNT_LEN ); +REG64_FLD( PEC_SCOM0X2C_EMOFLO , 61 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMOFLO ); +REG64_FLD( PEC_SCOM0X2C_EMCRST , 62 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMCRST ); +REG64_FLD( PEC_SCOM0X2C_EMCEN , 63 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMCEN ); + REG64_FLD( PU_SCOM_PPE_CNTL_IORESET , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_IORESET ); REG64_FLD( PU_SCOM_PPE_CNTL_PDWN , 1 , SH_UNT , SH_ACS_SCOM , @@ -69404,7 +75540,7 @@ REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE , 7 , SH_UN SH_FLD_CFG_PM_MUX_DISABLE ); REG64_FLD( PEC_SLAVE_CONFIG_REG_ERROR_MASK , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ERROR_MASK ); -REG64_FLD( PEC_SLAVE_CONFIG_REG_ERROR_MASK_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_SLAVE_CONFIG_REG_ERROR_MASK_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ERROR_MASK_LEN ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , @@ -71215,16 +77351,18 @@ REG64_FLD( PEC_SYNC_CONFIG_USE_FOR_SCAN , 6 , SH_UN SH_FLD_USE_FOR_SCAN ); REG64_FLD( PEC_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CLEAR_CHIPLET_IS_ALIGNED ); -REG64_FLD( PEC_SYNC_CONFIG_UNIT_REGION_CLKCMD_DISABLE , 8 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_UNIT_REGION_CLKCMD_DISABLE ); +REG64_FLD( PEC_SYNC_CONFIG_UNIT_REGION_CLKCMD_ENABLE , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT_REGION_CLKCMD_ENABLE ); REG64_FLD( PEC_SYNC_CONFIG_DISABLE_PCB_ITR , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DISABLE_PCB_ITR ); REG64_FLD( PEC_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ENABLE_VITL_ALIGN_CHECK ); -REG64_FLD( PEC_SYNC_CONFIG_UNUSED1119 , 11 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_UNUSED1119 ); -REG64_FLD( PEC_SYNC_CONFIG_UNUSED1119_LEN , 9 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_UNUSED1119_LEN ); +REG64_FLD( PEC_SYNC_CONFIG_PULSE_OUT_DIS , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PULSE_OUT_DIS ); +REG64_FLD( PEC_SYNC_CONFIG_UNUSED1219 , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED1219 ); +REG64_FLD( PEC_SYNC_CONFIG_UNUSED1219_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED1219_LEN ); REG64_FLD( PU_SYNC_FIR_ACTION0_REG_INVALID_TRANSFER_SIZE , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INVALID_TRANSFER_SIZE ); @@ -71326,6 +77464,11 @@ REG64_FLD( PU_SYNC_FIR_REG_PARITY_ERR2 , 10 , SH_UN REG64_FLD( PU_SYNC_FIR_REG_PARITY_ERR , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERR ); +REG64_FLD( PU_SYNC_FIR_WOF_REG_WOF , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF ); +REG64_FLD( PU_SYNC_FIR_WOF_REG_WOF_LEN , 6 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LEN ); + REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_ALL , 0 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_INVALIDATE_ALL ); REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_ONE , 2 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , @@ -71369,8 +77512,28 @@ REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , + SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -71462,6 +77625,14 @@ REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_U SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , + SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -71493,8 +77664,28 @@ REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , + SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -71586,6 +77777,14 @@ REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_U SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , + SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -71617,8 +77816,28 @@ REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , + SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -71710,6 +77929,14 @@ REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_U SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , + SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -71741,8 +77968,28 @@ REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , + SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -71834,6 +78081,14 @@ REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_U SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , + SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -71865,8 +78120,28 @@ REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -71958,6 +78233,14 @@ REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -71989,8 +78272,28 @@ REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -72082,6 +78385,14 @@ REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -72113,8 +78424,28 @@ REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -72206,6 +78537,14 @@ REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -72237,8 +78576,28 @@ REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -72330,6 +78689,14 @@ REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -72361,8 +78728,28 @@ REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -72454,6 +78841,14 @@ REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -72485,8 +78880,28 @@ REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -72578,6 +78993,14 @@ REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -72609,8 +79032,28 @@ REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -72702,6 +79145,14 @@ REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -72733,8 +79184,28 @@ REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -72826,6 +79297,14 @@ REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -72857,8 +79336,28 @@ REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -72950,6 +79449,14 @@ REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -72981,8 +79488,28 @@ REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -73074,6 +79601,14 @@ REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -73105,8 +79640,28 @@ REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -73198,6 +79753,14 @@ REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -73229,8 +79792,28 @@ REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -73322,6 +79905,14 @@ REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -73353,8 +79944,28 @@ REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -73446,6 +80057,14 @@ REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -73477,8 +80096,28 @@ REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -73570,6 +80209,14 @@ REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -73601,8 +80248,28 @@ REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -73694,6 +80361,14 @@ REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -73725,8 +80400,28 @@ REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -73818,6 +80513,14 @@ REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -73849,8 +80552,28 @@ REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -73942,6 +80665,14 @@ REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -73973,8 +80704,28 @@ REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -74066,6 +80817,14 @@ REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -74097,8 +80856,28 @@ REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -74190,6 +80969,14 @@ REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -74221,8 +81008,28 @@ REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -74314,6 +81121,14 @@ REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -74345,8 +81160,28 @@ REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -74438,6 +81273,14 @@ REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -74469,8 +81312,28 @@ REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -74562,6 +81425,14 @@ REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -74593,8 +81464,28 @@ REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -74686,6 +81577,14 @@ REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -74717,8 +81616,28 @@ REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -74810,6 +81729,14 @@ REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -74841,8 +81768,28 @@ REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -74934,6 +81881,14 @@ REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -74965,8 +81920,28 @@ REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -75058,6 +82033,14 @@ REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -75089,8 +82072,28 @@ REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_PEC , + SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -75182,6 +82185,14 @@ REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_U SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_PEC , + SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_NPU_SM2_TEST_CERR_ATR_ERR_INJ_PEND , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATR_ERR_INJ_PEND ); @@ -75196,10 +82207,74 @@ REG64_FLD( PU_NPU_SM2_TEST_CERR_BITSEL , 58 , SH_UN REG64_FLD( PU_NPU_SM2_TEST_CERR_BITSEL_LEN , 6 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_BITSEL_LEN ); +REG64_FLD( CAPP_TFMR_MAX_CYC_BET_STEPS , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_MAX_CYC_BET_STEPS ); +REG64_FLD( CAPP_TFMR_MAX_CYC_BET_STEPS_LEN , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_MAX_CYC_BET_STEPS_LEN ); +REG64_FLD( CAPP_TFMR_N_CLKS_PER_STEP , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_N_CLKS_PER_STEP ); +REG64_FLD( CAPP_TFMR_N_CLKS_PER_STEP_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_N_CLKS_PER_STEP_LEN ); +REG64_FLD( CAPP_TFMR_RESERVED_BIT10 , 10 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RESERVED_BIT10 ); +REG64_FLD( CAPP_TFMR_SYNC_BIT_SEL , 11 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SYNC_BIT_SEL ); +REG64_FLD( CAPP_TFMR_SYNC_BIT_SEL_LEN , 3 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SYNC_BIT_SEL_LEN ); +REG64_FLD( CAPP_TFMR_TB_ECLIPZ , 14 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TB_ECLIPZ ); +REG64_FLD( CAPP_TFMR_RESERVED_BIT15 , 15 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RESERVED_BIT15 ); +REG64_FLD( CAPP_TFMR_LOAD_TOD_MOD , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LOAD_TOD_MOD ); +REG64_FLD( CAPP_TFMR_RESERVED_BIT17 , 17 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RESERVED_BIT17 ); +REG64_FLD( CAPP_TFMR_MOVE_CHIP_TOD_TO_TB , 18 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_MOVE_CHIP_TOD_TO_TB ); +REG64_FLD( CAPP_TFMR_RESERVED_BIT19 , 19 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RESERVED_BIT19 ); +REG64_FLD( CAPP_TFMR_RESERVED_BIT20 , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RESERVED_BIT20 ); +REG64_FLD( CAPP_TFMR_RESERVED_BIT21 , 21 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RESERVED_BIT21 ); +REG64_FLD( CAPP_TFMR_RESERVED_BIT22 , 22 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RESERVED_BIT22 ); +REG64_FLD( CAPP_TFMR_RESERVED_BIT23 , 23 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RESERVED_BIT23 ); +REG64_FLD( CAPP_TFMR_CLEAR_TB_ERRORS , 24 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CLEAR_TB_ERRORS ); +REG64_FLD( CAPP_TFMR_TBST_CORRUPT , 27 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TBST_CORRUPT ); +REG64_FLD( CAPP_TFMR_TBST_ENCODED , 28 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TBST_ENCODED ); +REG64_FLD( CAPP_TFMR_TBST_ENCODED_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TBST_ENCODED_LEN ); +REG64_FLD( CAPP_TFMR_TBST_LAST , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TBST_LAST ); +REG64_FLD( CAPP_TFMR_TBST_LAST_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TBST_LAST_LEN ); +REG64_FLD( CAPP_TFMR_TB_ENABLED , 40 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TB_ENABLED ); +REG64_FLD( CAPP_TFMR_TB_VALID , 41 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TB_VALID ); +REG64_FLD( CAPP_TFMR_TB_SYNC_OCCURRED , 42 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TB_SYNC_OCCURRED ); +REG64_FLD( CAPP_TFMR_TB_MISSING_SYNC , 43 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TB_MISSING_SYNC ); +REG64_FLD( CAPP_TFMR_TB_MISSING_STEP , 44 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TB_MISSING_STEP ); +REG64_FLD( CAPP_TFMR_TB_RESIDUE_ERR , 45 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TB_RESIDUE_ERR ); +REG64_FLD( CAPP_TFMR_FIRMWARE_CONTROL_ERROR , 46 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FIRMWARE_CONTROL_ERROR ); REG64_FLD( CAPP_TFMR_CHIP_TOD_STATUS , 47 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_CHIP_TOD_STATUS ); REG64_FLD( CAPP_TFMR_CHIP_TOD_STATUS_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_CHIP_TOD_STATUS_LEN ); +REG64_FLD( CAPP_TFMR_CHIP_TOD_INTERRUPT , 51 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CHIP_TOD_INTERRUPT ); +REG64_FLD( CAPP_TFMR_TFMR_CORRUPT , 60 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TFMR_CORRUPT ); REG64_FLD( PEC_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DIS_CPM_BUBBLE_CORR ); @@ -75235,6 +82310,15 @@ REG64_FLD( PEC_THERM_MODE_REG_DTS_ENABLE_L1 , 20 , SH_UN SH_FLD_DTS_ENABLE_L1 ); REG64_FLD( PEC_THERM_MODE_REG_DTS_ENABLE_L1_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DTS_ENABLE_L1_LEN ); +REG64_FLD( PEC_THERM_MODE_REG_THERM_CPM_ENABLE_L1 , 35 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_THERM_CPM_ENABLE_L1 ); +REG64_FLD( PEC_THERM_MODE_REG_THERM_CPM_ENABLE_L1_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_THERM_CPM_ENABLE_L1_LEN ); + +REG64_FLD( PEC_TIMEOUT_REG_INT_TIMEOUT , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INT_TIMEOUT ); +REG64_FLD( PEC_TIMEOUT_REG_INT_TIMEOUT_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INT_TIMEOUT_LEN ); REG64_FLD( PEC_TIMESTAMP_COUNTER_READ_VALUE , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_VALUE ); @@ -75256,6 +82340,229 @@ REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_SNP_ADDR_PERR , 4 , SH_UN REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_SNP_TTAG_PERR , 5 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_IN_SNP_TTAG_PERR ); +REG64_FLD( CAPP_TLBI_FILTER_REG0_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG0_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG0_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG0_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG0_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG0_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG1_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG1_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG1_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG1_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG1_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG1_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG10_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG10_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG10_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG10_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG10_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG10_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG11_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG11_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG11_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG11_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG11_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG11_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG12_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG12_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG12_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG12_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG12_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG12_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG13_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG13_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG13_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG13_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG13_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG13_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG14_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG14_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG14_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG14_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG14_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG14_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG15_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG15_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG15_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG15_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG15_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG15_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG2_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG2_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG2_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG2_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG2_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG2_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG3_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG3_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG3_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG3_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG3_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG3_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG4_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG4_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG4_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG4_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG4_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG4_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG5_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG5_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG5_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG5_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG5_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG5_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG6_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG6_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG6_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG6_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG6_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG6_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG7_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG7_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG7_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG7_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG7_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG7_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG8_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG8_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG8_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG8_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG8_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG8_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG9_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG9_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG9_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG9_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG9_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG9_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_QOS_COMPARE , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COMPARE ); +REG64_FLD( CAPP_TLBI_QOS_COMPARE_LEN , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COMPARE_LEN ); +REG64_FLD( CAPP_TLBI_QOS_INC , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_INC ); +REG64_FLD( CAPP_TLBI_QOS_INC_LEN , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_INC_LEN ); +REG64_FLD( CAPP_TLBI_QOS_DEC , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DEC ); +REG64_FLD( CAPP_TLBI_QOS_DEC_LEN , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DEC_LEN ); +REG64_FLD( CAPP_TLBI_QOS_EN , 24 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_EN ); + REG64_FLD( PU_TOD_CMD_REG_ADR , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADR ); REG64_FLD( PU_TOD_CMD_REG_ADR_LEN , 31 , SH_UNT , SH_ACS_SCOM , @@ -75282,12 +82589,57 @@ REG64_FLD( CAPP_TOD_SYNC000_CHIP_STATUS_LEN , 4 , SH_UN REG64_FLD( PU_TRUST_CONTROL_FSP_TCE_ENABLE , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_FSP_TCE_ENABLE ); +REG64_FLD( PU_TRUST_CONTROL_SECURE_BOOTH , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SECURE_BOOTH ); REG64_FLD( PEC_TUNNEL_BAR_REG_PE , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE ); REG64_FLD( PEC_TUNNEL_BAR_REG_PE_LEN , 43 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_LEN ); +REG64_FLD( PU_TX_CH_FSM_REG_TX_CH_FSM , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TX_CH_FSM ); +REG64_FLD( PU_TX_CH_FSM_REG_TX_CH_FSM_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TX_CH_FSM_LEN ); + +REG64_FLD( PU_TX_CH_INTADDR_REG_SCOM_MODE_0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_0 ); +REG64_FLD( PU_TX_CH_INTADDR_REG_SCOM_MODE_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_1 ); +REG64_FLD( PU_TX_CH_INTADDR_REG_SCOM_MODE_2 , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_2 ); +REG64_FLD( PU_TX_CH_INTADDR_REG_SCOM_MODE_3 , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_3 ); +REG64_FLD( PU_TX_CH_INTADDR_REG_SCOM_MODE_4 , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_4 ); +REG64_FLD( PU_TX_CH_INTADDR_REG_SCOM_MODE_5 , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_5 ); +REG64_FLD( PU_TX_CH_INTADDR_REG_SCOM_MODE_6 , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_6 ); +REG64_FLD( PU_TX_CH_INTADDR_REG_SCOM_MODE_7 , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_7 ); + +REG64_FLD( PU_TX_CH_MISC_REG_FSM , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FSM ); +REG64_FLD( PU_TX_CH_MISC_REG_FSM_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FSM_LEN ); +REG64_FLD( PU_TX_CH_MISC_REG_TFRAMESIZE , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TFRAMESIZE ); +REG64_FLD( PU_TX_CH_MISC_REG_TFRAMESIZE_LEN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TFRAMESIZE_LEN ); +REG64_FLD( PU_TX_CH_MISC_REG_WEN0 , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WEN0 ); +REG64_FLD( PU_TX_CH_MISC_REG_WEN1 , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WEN1 ); +REG64_FLD( PU_TX_CH_MISC_REG_WEN2 , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WEN2 ); +REG64_FLD( PU_TX_CH_MISC_REG_DATA_REQ , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DATA_REQ ); +REG64_FLD( PU_TX_CH_MISC_REG_START_TRANS , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_START_TRANS ); +REG64_FLD( PU_TX_CH_MISC_REG_GXDATAAVAIL_Q , 17 , SH_UNT , SH_ACS_SCOM , + SH_FLD_GXDATAAVAIL_Q ); + REG64_FLD( PU_TX_CTRL_STAT_REG_ENABLE_SCWR_TO_TXRF , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_SCWR_TO_TXRF ); REG64_FLD( PU_TX_CTRL_STAT_REG_DISABLE_ECC_COR_GXC_PSI , 1 , SH_UNT , SH_ACS_SCOM , @@ -75310,6 +82662,85 @@ REG64_FLD( PU_TX_CTRL_STAT_REG_FENCE_GX_INTERFACE , 9 , SH_UN SH_FLD_FENCE_GX_INTERFACE ); REG64_FLD( PU_TX_CTRL_STAT_REG_GX_ENABLE_OVERWRITE , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_GX_ENABLE_OVERWRITE ); +REG64_FLD( PU_TX_CTRL_STAT_REG_TXSC , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TXSC ); + +REG64_FLD( PU_TX_DBFF_REG0_DATA_BUFF0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DATA_BUFF0 ); +REG64_FLD( PU_TX_DBFF_REG0_DATA_BUFF0_LEN , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DATA_BUFF0_LEN ); + +REG64_FLD( PU_TX_DBFF_REG1_DATA_BUFF1 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DATA_BUFF1 ); +REG64_FLD( PU_TX_DBFF_REG1_DATA_BUFF1_LEN , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DATA_BUFF1_LEN ); + +REG64_FLD( PU_TX_DF_FSM_REG_TX_DF_FSM , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TX_DF_FSM ); +REG64_FLD( PU_TX_DF_FSM_REG_TX_DF_FSM_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TX_DF_FSM_LEN ); + +REG64_FLD( PU_TX_ERROR_REG_C1_PSITXINS_DATA_PCK , 0 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSITXINS_DATA_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C1_PSITXINS_TZRTMP_PCK , 1 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSITXINS_TZRTMP_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C1_PSITXEI_SHIFT_PCK , 2 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSITXEI_SHIFT_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C1_PSITXEI_TRANSMIT_PCK , 3 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSITXEI_TRANSMIT_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C1_PSITXINS_PARITY , 4 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSITXINS_PARITY ); +REG64_FLD( PU_TX_ERROR_REG_C1_PSITXINS_UNDERRUN , 5 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSITXINS_UNDERRUN ); +REG64_FLD( PU_TX_ERROR_REG_C2_PSITXBFF_DATA_PCK , 6 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSITXBFF_DATA_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C1_PSITXBFF_TDO_PCK , 7 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSITXBFF_TDO_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C2_PSITXBFF_TFC_PCK , 8 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSITXBFF_TFC_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C2_PSITXLC_FSM_PCK , 9 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSITXLC_FSM_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C3_PSITXLC_DATA_BUFF_PCK , 10 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSITXLC_DATA_BUFF_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C2_PSITXLC_TDO_PCK , 11 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSITXLC_TDO_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C2_PSITXLC_TADDR_PCK , 12 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSITXLC_TADDR_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C2_PSITXLC_TCTRL_PCK , 13 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSITXLC_TCTRL_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C2_PSITXLC_UE_RF , 14 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSITXLC_UE_RF ); +REG64_FLD( PU_TX_ERROR_REG_C0_PSITXLC_CE_RF , 15 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C0_PSITXLC_CE_RF ); +REG64_FLD( PU_TX_ERROR_REG_C3_PSITXLC_UE_GX_2N , 16 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSITXLC_UE_GX_2N ); +REG64_FLD( PU_TX_ERROR_REG_C0_PSITXLC_CE_GX_2N , 17 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C0_PSITXLC_CE_GX_2N ); +REG64_FLD( PU_TX_ERROR_REG_C3_PSITXLC_DATA_GXST2_PCK_2N , 18 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSITXLC_DATA_GXST2_PCK_2N ); +REG64_FLD( PU_TX_ERROR_REG_C3_PSITXLC_DATA_GXST3_PCK_2N , 19 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSITXLC_DATA_GXST3_PCK_2N ); +REG64_FLD( PU_TX_ERROR_REG_C3_PSIRFACC_TADDR_PCK , 20 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSIRFACC_TADDR_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C3_PSIRFACC_TCTRL_PCK , 21 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSIRFACC_TCTRL_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C3_PSIRFACC_TDL_CMD_CTRL_PCK , 22 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSIRFACC_TDL_CMD_CTRL_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C3_PSIRFACC_TDL_RSP_CTRL_PCK , 23 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSIRFACC_TDL_RSP_CTRL_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C3_PSIRFACC_TFSM_PCK , 24 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSIRFACC_TFSM_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C3_PSIRFACC_TDL_FSM_PCK , 25 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSIRFACC_TDL_FSM_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C4_PSIRFACC_TXSC_PCK , 26 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C4_PSIRFACC_TXSC_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C3_PSIRFACC_TDL_RETRY_ERR , 27 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSIRFACC_TDL_RETRY_ERR ); + +REG64_FLD( PU_TX_ERR_MODE_TX_ERR_MODE_0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TX_ERR_MODE_0 ); +REG64_FLD( PU_TX_ERR_MODE_TX_ERR_MODE_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TX_ERR_MODE_1 ); REG64_FLD( PU_TX_MASK_REG_PSITXINS_DATA_PCK , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSITXINS_DATA_PCK ); @@ -75368,6 +82799,8 @@ REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TXSC_PCK , 26 , SH_UN REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TDL_RETRY_ERR , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRFACC_TDL_RETRY_ERR ); +REG64_FLD( PU_TX_PSI_CNTL_TX_PSI_IORESET_WO_PULSE_SLOW_SIGNAL , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TX_PSI_IORESET_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( PU_TX_PSI_CNTL_DRV_PATTERN_EN , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_DRV_PATTERN_EN ); REG64_FLD( PU_TX_PSI_CNTL_PATTERN_SEL , 2 , SH_UNT , SH_ACS_SCOM , @@ -75430,6 +82863,10 @@ REG64_FLD( PU_TX_PSI_STATUS_BIST_ERROR , 4 , SH_UN SH_FLD_BIST_ERROR ); REG64_FLD( PU_TX_PSI_STATUS_BIST_ERROR_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_BIST_ERROR_LEN ); +REG64_FLD( PU_TX_PSI_STATUS_TX_PSI_BIST_DONE_RO_SIGNAL , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TX_PSI_BIST_DONE_RO_SIGNAL ); +REG64_FLD( PU_TX_PSI_STATUS_TX_PSI_BIST_DONE_RO_SIGNAL_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TX_PSI_BIST_DONE_RO_SIGNAL_LEN ); REG64_FLD( PU_TX_TO_RT_REG_TIMEOUT_VALUE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_TIMEOUT_VALUE ); @@ -75872,6 +83309,8 @@ REG64_FLD( PU_VAS_FIR_MASK_REG_IN_PARITY_ERROR , 21 , SH_UN SH_FLD_IN_PARITY_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_IN_SW_CAST_ERROR , 22 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IN_SW_CAST_ERROR ); +REG64_FLD( PU_VAS_FIR_MASK_REG_UNUSED23 , 23 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED23 ); REG64_FLD( PU_VAS_FIR_MASK_REG_EG_ECC_SUE_ERROR , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_EG_ECC_SUE_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_IN_ECC_SUE_ERROR , 25 , SH_UNT , SH_ACS_SCOM2_OR , @@ -75979,6 +83418,8 @@ REG64_FLD( PU_VAS_FIR_REG_IN_PARITY_ERROR , 21 , SH_UN SH_FLD_IN_PARITY_ERROR ); REG64_FLD( PU_VAS_FIR_REG_IN_SW_CAST_ERROR , 22 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IN_SW_CAST_ERROR ); +REG64_FLD( PU_VAS_FIR_REG_UNUSED23 , 23 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED23 ); REG64_FLD( PU_VAS_FIR_REG_EG_ECC_SUE_ERROR , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_EG_ECC_SUE_ERROR ); REG64_FLD( PU_VAS_FIR_REG_IN_ECC_SUE_ERROR , 25 , SH_UNT , SH_ACS_SCOM2_OR , @@ -76874,6 +84315,135 @@ REG64_FLD( PU_WATER_MARK_REGISTER_E_PEEK_DATA1_3_LEN , 8 , SH_UN REG64_FLD( PU_WATER_MARK_REGISTER_E_LBUS_PARITY_ERR1_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_3 ); +REG64_FLD( PHB_WOF_REG_AIB_COMMAND_INVALID , 0 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_AIB_COMMAND_INVALID ); +REG64_FLD( PHB_WOF_REG_AIB_ADDRESSING_ERROR , 1 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_AIB_ADDRESSING_ERROR ); +REG64_FLD( PHB_WOF_REG_AIB_ACCESS_ERROR , 2 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_AIB_ACCESS_ERROR ); +REG64_FLD( PHB_WOF_REG_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED , 3 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED ); +REG64_FLD( PHB_WOF_REG_AIB_FATAL_CLASS_ERROR , 4 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_AIB_FATAL_CLASS_ERROR ); +REG64_FLD( PHB_WOF_REG_AIB_INF_CLASS_ERROR , 5 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_AIB_INF_CLASS_ERROR ); +REG64_FLD( PHB_WOF_REG_PE_STOP_STATE_ERROR , 6 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_PE_STOP_STATE_ERROR ); +REG64_FLD( PHB_WOF_REG_AIB_DAT_ERR_SIGNALED , 7 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_AIB_DAT_ERR_SIGNALED ); +REG64_FLD( PHB_WOF_REG_OUT_COMMON_ARRAY_FATAL_ERROR , 8 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_OUT_COMMON_ARRAY_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_OUT_COMMON_LATCH_FATAL_ERROR , 9 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_OUT_COMMON_LATCH_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_OUT_COMMON_LOGIC_FATAL_ERROR , 10 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_OUT_COMMON_LOGIC_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_BLIF_OUT_INTERFACE_PARITY_ERROR , 11 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_BLIF_OUT_INTERFACE_PARITY_ERROR ); +REG64_FLD( PHB_WOF_REG_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE , 12 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE ); +REG64_FLD( PHB_WOF_REG_MMIO_REQUEST_TIMEOUT , 13 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_MMIO_REQUEST_TIMEOUT ); +REG64_FLD( PHB_WOF_REG_OUT_RRB_SOURCED_ERROR , 14 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_OUT_RRB_SOURCED_ERROR ); +REG64_FLD( PHB_WOF_REG_CFG_LOGIC_SIGNALED_ERROR , 15 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_CFG_LOGIC_SIGNALED_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_REG_REQUEST_ADDRESS_ERROR , 16 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_REG_REQUEST_ADDRESS_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_FDA_FATAL_ERROR , 17 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_FDA_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_FDA_INF_ERROR , 18 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_FDA_INF_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_FDB_FATAL_ERROR , 19 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_FDB_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_FDB_INF_ERROR , 20 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_FDB_INF_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_ERR_FATAL_ERROR , 21 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_ERR_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_ERR_INF_ERROR , 22 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_ERR_INF_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_DBG_FATAL_ERROR , 23 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_DBG_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_DBG_INF_ERROR , 24 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_DBG_INF_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_PCIE_REQUEST_ACCESS_ERROR , 25 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_PCIE_REQUEST_ACCESS_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_BUS_LOGIC_ERROR , 26 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_BUS_LOGIC_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_UVI_FATAL_ERROR , 27 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_UVI_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_UVI_INF_ERROR , 28 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_UVI_INF_ERROR ); +REG64_FLD( PHB_WOF_REG_SCOM_FATAL_ERROR , 29 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_SCOM_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_SCOM_INF_ERROR , 30 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_SCOM_INF_ERROR ); +REG64_FLD( PHB_WOF_REG_PCIE_MACRO_ERROR_ACTIVE_STATUS , 31 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_PCIE_MACRO_ERROR_ACTIVE_STATUS ); +REG64_FLD( PHB_WOF_REG_ARB_IODA_FATAL_ERROR , 32 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_IODA_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_ARB_MSI_PE_MATCH_ERROR , 33 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_MSI_PE_MATCH_ERROR ); +REG64_FLD( PHB_WOF_REG_ARB_MSI_ADDRESS_ERROR , 34 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_MSI_ADDRESS_ERROR ); +REG64_FLD( PHB_WOF_REG_ARB_TVT_ERROR , 35 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_TVT_ERROR ); +REG64_FLD( PHB_WOF_REG_ARB_RCVD_FATAL_ERROR_MSG , 36 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_RCVD_FATAL_ERROR_MSG ); +REG64_FLD( PHB_WOF_REG_ARB_RCVD_NONFATAL_ERROR_MSG , 37 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_RCVD_NONFATAL_ERROR_MSG ); +REG64_FLD( PHB_WOF_REG_ARB_RCVD_CORRECTIBLE_ERROR_MSG , 38 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_RCVD_CORRECTIBLE_ERROR_MSG ); +REG64_FLD( PHB_WOF_REG_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED , 39 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED ); +REG64_FLD( PHB_WOF_REG_ARB_COMMON_FATAL_ERROR , 40 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_COMMON_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_ARB_TABLE_BAR_DISABLED_ERROR , 41 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_TABLE_BAR_DISABLED_ERROR ); +REG64_FLD( PHB_WOF_REG_ARB_BLIF_COMPLETION_ERROR , 42 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_BLIF_COMPLETION_ERROR ); +REG64_FLD( PHB_WOF_REG_ARB_PCT_TIMEOUT_ERROR , 43 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_PCT_TIMEOUT_ERROR ); +REG64_FLD( PHB_WOF_REG_ARB_ECC_CORRECTABLE_ERROR , 44 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_WOF_REG_ARB_ECC_UNCORRECTABLE_ERROR , 45 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_WOF_REG_ARB_TLP_POISON_SIGNALED , 46 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_TLP_POISON_SIGNALED ); +REG64_FLD( PHB_WOF_REG_ARB_RTT_PENUM_INVALID_ERROR , 47 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_RTT_PENUM_INVALID_ERROR ); +REG64_FLD( PHB_WOF_REG_MRG_COMMON_FATAL_ERROR , 48 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_MRG_COMMON_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_MRG_TABLE_BAR_DISABLED_ERROR , 49 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_MRG_TABLE_BAR_DISABLED_ERROR ); +REG64_FLD( PHB_WOF_REG_MRG_ECC_CORRECTABLE_ERROR , 50 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_MRG_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_WOF_REG_MRG_ECC_UNCORRECTABLE_ERROR , 51 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_MRG_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_WOF_REG_MRG_AIB2_TX_TIMEOUT_ERROR , 52 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_MRG_AIB2_TX_TIMEOUT_ERROR ); +REG64_FLD( PHB_WOF_REG_MRG_MRT_ERROR , 53 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_MRG_MRT_ERROR ); +REG64_FLD( PHB_WOF_REG_MRG_RESERVED01 , 54 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_MRG_RESERVED01 ); +REG64_FLD( PHB_WOF_REG_MRG_RESERVED02 , 55 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_MRG_RESERVED02 ); +REG64_FLD( PHB_WOF_REG_TCE_IODA_PAGE_ACCESS_ERROR , 56 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_TCE_IODA_PAGE_ACCESS_ERROR ); +REG64_FLD( PHB_WOF_REG_TCE_REQUEST_TIMEOUT_ERROR , 57 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_TCE_REQUEST_TIMEOUT_ERROR ); +REG64_FLD( PHB_WOF_REG_TCE_UNEXPECTED_RESPONSE_ERROR , 58 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_TCE_UNEXPECTED_RESPONSE_ERROR ); +REG64_FLD( PHB_WOF_REG_TCE_COMMON_FATAL_ERRORS , 59 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_TCE_COMMON_FATAL_ERRORS ); +REG64_FLD( PHB_WOF_REG_TCE_ECC_CORRECTABLE_ERROR , 60 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_TCE_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_WOF_REG_TCE_ECC_UNCORRECTABLE_ERROR , 61 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_TCE_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_WOF_REG_TCE_RESERVED01 , 62 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_TCE_RESERVED01 ); +REG64_FLD( PHB_WOF_REG_LEM_FIR_INTERNAL_PARITY_ERROR , 63 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_LEM_FIR_INTERNAL_PARITY_ERROR ); + REG64_FLD( PU_N3_WRITE_PROTECT_ENABLE_REG_RING_LOCKING , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RING_LOCKING ); REG64_FLD( PU_N3_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1 , SH_UNT_PU_N3 , SH_ACS_SCOM , @@ -77384,6 +84954,9 @@ REG64_FLD( PEC_XSTOP3_WAIT_CYCLES , 48 , SH_UN REG64_FLD( PEC_XSTOP3_WAIT_CYCLES_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES_LEN ); +REG64_FLD( PEC_XSTOP_INTERRUPT_REG_XSTOP , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_XSTOP ); + REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , @@ -78011,9 +85584,11 @@ REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREFEVOD , 10 , SH_UN SH_FLD_PREFEVOD ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_EAINJ , 11 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_EAINJ ); -REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED1 , 12 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU_SM2_XTS_CONFIG_SPL_ONLY , 12 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_SPL_ONLY ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED1 , 13 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED1 ); -REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED1_LEN , 4 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED1_LEN , 3 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED1_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TLBIE_DEC_RATE , 16 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_TLBIE_DEC_RATE ); |
