diff options
Diffstat (limited to 'src/import/chips/ocmb')
| -rw-r--r-- | src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.H | 55 | ||||
| -rw-r--r-- | src/import/chips/ocmb/common/procedures/hwp/pmic/pmic_enable.C | 36 |
2 files changed, 54 insertions, 37 deletions
diff --git a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.H b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.H index 0d6f5a692..527cc24e9 100644 --- a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.H +++ b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.H @@ -748,8 +748,7 @@ fapi_try_exit: template <mss::pmic::module_height H> fapi2::ReturnCode enable_chip(const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target, const fapi2::Target<fapi2::TargetType::TARGET_TYPE_DIMM>& i_dimm_target, - const uint16_t i_vendor_id, - const mss::pmic::enable_mode i_mode); + const uint16_t i_vendor_id); /// /// @brief enable procedure for IDT PMIC and 1U or 2U DIMM @@ -764,45 +763,33 @@ template <> inline fapi2::ReturnCode enable_chip<mss::pmic::module_height::HEIGHT_1U>( const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_pmic_target, const fapi2::Target<fapi2::TargetType::TARGET_TYPE_DIMM>& i_dimm_target, - const uint16_t i_vendor_id, - const mss::pmic::enable_mode i_mode) + const uint16_t i_vendor_id) { - if (i_mode == mss::pmic::enable_mode::SPD) - { - FAPI_INF("Setting PMIC settings from SPD"); + FAPI_INF("Setting PMIC %s settings from SPD", mss::c_str(i_pmic_target)); - // Make sure it is TI or IDT - FAPI_ASSERT((i_vendor_id == mss::pmic::vendor::IDT || - i_vendor_id == mss::pmic::vendor::TI), - fapi2::PMIC_CHIP_NOT_RECOGNIZED() - .set_TARGET(i_pmic_target) - .set_VENDOR_ID(i_vendor_id), - "Unknown PMIC: %s with vendor ID 0x%04hhX", - mss::c_str(i_pmic_target), - uint8_t(i_vendor_id) ); + // Make sure it is TI or IDT + FAPI_ASSERT((i_vendor_id == mss::pmic::vendor::IDT || + i_vendor_id == mss::pmic::vendor::TI), + fapi2::PMIC_CHIP_NOT_RECOGNIZED() + .set_TARGET(i_pmic_target) + .set_VENDOR_ID(i_vendor_id), + "Unknown PMIC: %s with vendor ID 0x%04hhX", + mss::c_str(i_pmic_target), + uint8_t(i_vendor_id) ); - if (i_vendor_id == mss::pmic::vendor::IDT) - { - FAPI_TRY(mss::pmic::bias_with_spd_settings<mss::pmic::vendor::IDT>(i_pmic_target, i_dimm_target), - "enable_chip<IDT, 1U/2U>: Error biasing PMIC %s with SPD settings", - mss::c_str(i_pmic_target)); - } - else // assert done in pmic_enable.C that vendor is IDT or TI - { - FAPI_TRY(mss::pmic::bias_with_spd_settings<mss::pmic::vendor::TI>(i_pmic_target, i_dimm_target), - "enable_chip<TI, 1U/2U>: Error biasing PMIC %s with SPD settings", - mss::c_str(i_pmic_target)); - } + if (i_vendor_id == mss::pmic::vendor::IDT) + { + FAPI_TRY(mss::pmic::bias_with_spd_settings<mss::pmic::vendor::IDT>(i_pmic_target, i_dimm_target), + "enable_chip<IDT, 1U/2U>: Error biasing PMIC %s with SPD settings", + mss::c_str(i_pmic_target)); } - else // manual mode + else // assert done in pmic_enable.C that vendor is IDT or TI { - FAPI_INF("Using built-in PMIC settings (defaults or from pmic_update)"); + FAPI_TRY(mss::pmic::bias_with_spd_settings<mss::pmic::vendor::TI>(i_pmic_target, i_dimm_target), + "enable_chip<TI, 1U/2U>: Error biasing PMIC %s with SPD settings", + mss::c_str(i_pmic_target)); } - // Execute VR Enable command - FAPI_TRY((mss::pmic::start_vr_enable(i_pmic_target)), - "enable_chip: Failed to start VR Enable for %s", mss::c_str(i_pmic_target)); - return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: diff --git a/src/import/chips/ocmb/common/procedures/hwp/pmic/pmic_enable.C b/src/import/chips/ocmb/common/procedures/hwp/pmic/pmic_enable.C index a10f772b6..1318bab0c 100644 --- a/src/import/chips/ocmb/common/procedures/hwp/pmic/pmic_enable.C +++ b/src/import/chips/ocmb/common/procedures/hwp/pmic/pmic_enable.C @@ -72,11 +72,42 @@ extern "C" return mss::index(l_first_pmic) < mss::index(l_second_pmic); }); + uint8_t l_pmic_index = 0; + + // If we're enabling via internal settings, we can just run VR ENABLE down the line + if (i_mode == mss::pmic::enable_mode::MANUAL) + { + using CONSTS = mss::pmic::consts<mss::pmic::product::JEDEC_COMPLIANT>; + using REGS = pmicRegs<mss::pmic::product::JEDEC_COMPLIANT>; + using FIELDS = pmicFields<mss::pmic::product::JEDEC_COMPLIANT>; + + for (const auto& l_pmic : l_pmics) + { + fapi2::buffer<uint8_t> l_programmable_mode; + l_programmable_mode.writeBit<FIELDS::R2F_SECURE_MODE>(CONSTS::PROGRAMMABLE_MODE); + + FAPI_INF("Enabling PMIC %s with default settings", mss::c_str(l_pmic)); + + // Make sure power is applied and we can read the PMIC + FAPI_TRY(mss::pmic::poll_for_pbulk_good(l_pmic), + "pmic_enable: poll for pbulk good either failed, or returned not good status on PMIC %s", + mss::c_str(l_pmic)); + + // Enable programmable mode + FAPI_TRY(mss::pmic::i2c::reg_write_reverse_buffer(l_pmic, REGS::R2F, l_programmable_mode)); + + // Start VR Enable + FAPI_TRY(mss::pmic::start_vr_enable(l_pmic), + "Error starting VR_ENABLE on PMIC %s", mss::c_str(l_pmic)); + } + + return fapi2::FAPI2_RC_SUCCESS; + } + // Start at PMIC0. If there was ever a weird case where there is a 4U dimm // on the same OCMB as a 2U dimm (is this possible?), // we would have 6 total PMICs. So, we need to keep // track of where we left off for the last pmic we enabled - uint8_t l_pmic_index = 0; // Not asserting vectors non-empty because there could be OCMBs without DIMMs on them for (const auto& l_dimm : l_dimms) @@ -108,9 +139,8 @@ extern "C" // Call the enable procedure FAPI_TRY((mss::pmic::enable_chip <mss::pmic::module_height::HEIGHT_1U> - (l_current_pmic_target, l_dimm, l_vendor_id, i_mode)), + (l_current_pmic_target, l_dimm, l_vendor_id)), "pmic_enable: Error enabling PMIC %s", mss::c_str(l_current_pmic_target)); - } // Increment by the number of PMICs that were enabled and move on to the next dimm |
