diff options
Diffstat (limited to 'src/import/chips/ocmb/explorer')
| -rw-r--r-- | src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/dimm/exp_rank.H | 5 | ||||
| -rw-r--r-- | src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C | 34 |
2 files changed, 21 insertions, 18 deletions
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/dimm/exp_rank.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/dimm/exp_rank.H index 8ffe98097..f61dc0db0 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/dimm/exp_rank.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/dimm/exp_rank.H @@ -44,6 +44,11 @@ class rankTraits<mss::mc_type::EXPLORER> static constexpr uint8_t MAX_DIMMS_PER_PORT = 2; static constexpr uint8_t MAX_RANKS_PER_DIMM = 4; static constexpr uint8_t RANK_INDEX_STEP = 4; + + // Note! a configuration of 2 4-rank dimms is not possible. + // In this hypothetical scenario, the value for phy-rank would not + // be valid / does not apply, as there will be some rollover. + static constexpr uint8_t PHY_RANK_INDEX_STEP = 2; }; /// diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C index 477335d6f..fa39f9e5c 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C @@ -35,6 +35,8 @@ #include <fapi2.H> #include <lib/shared/exp_consts.H> +#include <lib/shared/exp_defaults.H> +#include <lib/dimm/exp_rank.H> #include <generic/memory/lib/utils/shared/mss_generic_consts.H> #include <generic/memory/lib/utils/index.H> #include <generic/memory/lib/utils/c_str.H> @@ -113,29 +115,25 @@ fapi2::ReturnCode display_mrs_info(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_C const user_response_msdg_t& i_training_info) { // Loop through all DIMM's - for(const auto& l_dimm : mss::find_targets<fapi2::TARGET_TYPE_DIMM>(i_target)) + for (const auto& l_dimm : mss::find_targets<fapi2::TARGET_TYPE_DIMM>(i_target)) { - // Gets the number of DIMM's and x4 vs x8 DRAM - // TK update ranks to use rank API - uint8_t l_num_master_ranks = 0; + // Rank info object for + std::vector<mss::rank::info<>> l_rank_info_vect; uint8_t l_dram_width = 0; - FAPI_TRY(mss::attr::get_num_master_ranks_per_dimm(l_dimm, l_num_master_ranks)); + FAPI_TRY(mss::rank::ranks_on_dimm<>(l_dimm, l_rank_info_vect)); FAPI_TRY(mss::attr::get_dram_width(l_dimm, l_dram_width)); // Loops through all of the ranks - for(uint8_t l_dimm_rank = 0; l_dimm_rank < l_num_master_ranks; ++l_dimm_rank) + for (const auto& l_rank_info : l_rank_info_vect) { - // TK update to rank API - constexpr uint8_t DIMM_OFFSET = 2; - const auto l_rank = l_dimm_rank + mss::index(l_dimm) * DIMM_OFFSET; - + const uint8_t l_phy_rank = l_rank_info.get_phy_rank(); // MR0->5 are easy, just display the value - FAPI_DBG("%s rank%u MR%u 0x%04x", mss::c_str(i_target), l_rank, 0, i_training_info.mrs_resp.MR0); - FAPI_DBG("%s rank%u MR%u 0x%04x", mss::c_str(i_target), l_rank, 1, i_training_info.mrs_resp.MR1[l_rank]); - FAPI_DBG("%s rank%u MR%u 0x%04x", mss::c_str(i_target), l_rank, 2, i_training_info.mrs_resp.MR2[l_rank]); - FAPI_DBG("%s rank%u MR%u 0x%04x", mss::c_str(i_target), l_rank, 3, i_training_info.mrs_resp.MR3); - FAPI_DBG("%s rank%u MR%u 0x%04x", mss::c_str(i_target), l_rank, 4, i_training_info.mrs_resp.MR4); - FAPI_DBG("%s rank%u MR%u 0x%04x", mss::c_str(i_target), l_rank, 5, i_training_info.mrs_resp.MR5[l_rank]); + FAPI_DBG("%s rank%u MR%u 0x%04x", mss::c_str(i_target), l_phy_rank, 0, i_training_info.mrs_resp.MR0); + FAPI_DBG("%s rank%u MR%u 0x%04x", mss::c_str(i_target), l_phy_rank, 1, i_training_info.mrs_resp.MR1[l_phy_rank]); + FAPI_DBG("%s rank%u MR%u 0x%04x", mss::c_str(i_target), l_phy_rank, 2, i_training_info.mrs_resp.MR2[l_phy_rank]); + FAPI_DBG("%s rank%u MR%u 0x%04x", mss::c_str(i_target), l_phy_rank, 3, i_training_info.mrs_resp.MR3); + FAPI_DBG("%s rank%u MR%u 0x%04x", mss::c_str(i_target), l_phy_rank, 4, i_training_info.mrs_resp.MR4); + FAPI_DBG("%s rank%u MR%u 0x%04x", mss::c_str(i_target), l_phy_rank, 5, i_training_info.mrs_resp.MR5[l_phy_rank]); // The number of the DRAM's and the position to access each DRAM changes based upon x4 vs x8 const auto l_num_dram = l_dram_width == fapi2::ENUM_ATTR_MEM_EFF_DRAM_WIDTH_X4 ? @@ -148,8 +146,8 @@ fapi2::ReturnCode display_mrs_info(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_C for(uint64_t l_dram = 0; l_dram < l_num_dram; ++l_dram) { const auto l_dram_pos = l_correction_factor * l_dram; - FAPI_DBG("%s rank%u MR6 dram%u 0x%04x", mss::c_str(i_target), l_rank, l_dram, - i_training_info.mrs_resp.MR6[l_rank][l_dram_pos]); + FAPI_DBG("%s rank%u MR6 dram%u 0x%04x", mss::c_str(i_target), l_phy_rank, l_dram, + i_training_info.mrs_resp.MR6[l_phy_rank][l_dram_pos]); } } } |
