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-rw-r--r--src/build/citest/etc/bbuild3
-rwxr-xr-xsrc/build/citest/etc/workarounds.postsimsetup9
-rwxr-xr-xsrc/build/citest/etc/workarounds.presimsetup5
-rwxr-xr-xsrc/build/mkrules/hbfw/img/makefile5
-rwxr-xr-xsrc/build/simics/standalone.simics4
5 files changed, 19 insertions, 7 deletions
diff --git a/src/build/citest/etc/bbuild b/src/build/citest/etc/bbuild
index 14fddbc07..5d549ca19 100644
--- a/src/build/citest/etc/bbuild
+++ b/src/build/citest/etc/bbuild
@@ -1,2 +1 @@
-/esw/fips920/Builds/b0710c_1827.920
-
+/esw/fips930/Builds/b0731a_1832.930
diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup
index 82a1c72fe..8708e2b03 100755
--- a/src/build/citest/etc/workarounds.postsimsetup
+++ b/src/build/citest/etc/workarounds.postsimsetup
@@ -38,3 +38,12 @@ cp $BACKING_BUILD/src/simu/data/cec-chip/centaur_memory.act $sb/simu/data/cec-ch
chmod 777 $sb/simu/data/cec-chip/centaur_memory.act
patch -p0 $sb/simu/data/cec-chip/centaur_memory.act $PROJECT_ROOT/src/build/citest/etc/patches/centaur_memory.act.patch
+
+##########################################################################
+echo "+++ SBE support for Cumulus DD1.3 +++"
+#Pull in the code
+sbex -t 1060757
+#Build sbei to create p9c_13.sbe_seeprom.hdr.bin
+mkdir -p $sb/sbei/sbfw/
+cd $sb/sbei/sbfw/
+mk
diff --git a/src/build/citest/etc/workarounds.presimsetup b/src/build/citest/etc/workarounds.presimsetup
index a4d682dd7..08da3baed 100755
--- a/src/build/citest/etc/workarounds.presimsetup
+++ b/src/build/citest/etc/workarounds.presimsetup
@@ -35,12 +35,17 @@
#echo "WSALIAS DEFAULT FIPSLEVEL env/gfwb/simics-4.2.0/simics-4.2.83/fips/fld36/fi120201a700.42" >> $sb/simu/data/simicsInfo
#echo "WSALIAS DEFAULT SIMICSLEVEL env/vtechb/simics-4.2.0/simics-4.2.83/bin" >> $sb/simu/data/simicsInfo
+##########################################################################
+echo "+++ Update standalone configs to use modern proc levels +++"
+sbex -t 1063108
+
echo "+++ Need to alter where we look for pnor images so they will be picked up properly"
mkdir -p $sb/simu/data
###############################################################################
### NOTE - if you need to sbex a simicsInfo track it needs to be done BEFORE
### executing the code below
+### NOTE - these lines are permanent to allow external PNOR testing
###############################################################################
cp $bb/src/simu/data/simicsInfo $sb/simu/data/
chmod +w $sb/simu/data/simicsInfo
diff --git a/src/build/mkrules/hbfw/img/makefile b/src/build/mkrules/hbfw/img/makefile
index 5cf263bc2..002a46b2d 100755
--- a/src/build/mkrules/hbfw/img/makefile
+++ b/src/build/mkrules/hbfw/img/makefile
@@ -266,17 +266,16 @@ SBE_BUILD_SCRIPT = ${buildSbePart.pl:P}
NIMBUS_SBE_IMG = p9n.SbePartition.bin
CUMULUS_SBE_IMG = p9c.SbePartition.bin
-P9N_EC10_BIN = ${SBEI_OBJPATH:Fp9n_10.sbe_seeprom.hdr.bin}
P9N_EC20_BIN = ${SBEI_OBJPATH:Fp9n_20.sbe_seeprom.hdr.bin}
P9N_EC21_BIN = ${SBEI_OBJPATH:Fp9n_21.sbe_seeprom.hdr.bin}
P9N_EC22_BIN = ${SBEI_OBJPATH:Fp9n_22.sbe_seeprom.hdr.bin}
-P9C_EC10_BIN = ${SBEI_OBJPATH:Fp9c_10.sbe_seeprom.hdr.bin}
+P9C_EC13_BIN = ${SBEI_OBJPATH:Fp9c_13.sbe_seeprom.hdr.bin}
P9C_EC11_BIN = ${SBEI_OBJPATH:Fp9c_11.sbe_seeprom.hdr.bin}
P9C_EC12_BIN = ${SBEI_OBJPATH:Fp9c_12.sbe_seeprom.hdr.bin}
SBE_PART_INFO = \
${NIMBUS_SBE_IMG}:20=${P9N_EC20_BIN},21=${P9N_EC21_BIN},22=${P9N_EC22_BIN} \
- ${CUMULUS_SBE_IMG}:10=${P9C_EC10_BIN},11=${P9C_EC11_BIN},12=${P9C_EC12_BIN}
+ ${CUMULUS_SBE_IMG}:13=${P9C_EC13_BIN},11=${P9C_EC11_BIN},12=${P9C_EC12_BIN}
__SBE_PART_BUILD/% : .SPECTARG .PMAKE
diff --git a/src/build/simics/standalone.simics b/src/build/simics/standalone.simics
index 92dcaacb6..76027b8b1 100755
--- a/src/build/simics/standalone.simics
+++ b/src/build/simics/standalone.simics
@@ -68,7 +68,7 @@ echo "Enable the SBE"
# Set Boot Freq valid bit (bit 3) and valid data bit (bit 7)
($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003F "31000000_00000000" 64
($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003A "00000000_00000000" 64
-# Set the Nest PLL Bucket ID to 3 in the 4th byte of Mbox Scratch Reg 4
-($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003B "00000003_00000000" 64
+# Set the Nest PLL Bucket ID to 5 in the 4th byte of Mbox Scratch Reg 4
+($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003B "00000005_00000000" 64
($hb_masterproc).proc_chip.invoke parallel_store FSIMBOX 0x01 "80000000" 32
($hb_masterproc).proc_chip.invoke parallel_store FSIMBOX 0x08 "00080000" 32
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