diff options
Diffstat (limited to 'src/build/citest')
| -rw-r--r-- | src/build/citest/etc/bbuild | 2 | ||||
| -rw-r--r-- | src/build/citest/etc/patches/patchlist.txt | 7 | ||||
| -rw-r--r-- | src/build/citest/etc/patches/s1.act.patch | 22 | ||||
| -rwxr-xr-x | src/build/citest/etc/workarounds.postsimsetup | 7 |
4 files changed, 4 insertions, 34 deletions
diff --git a/src/build/citest/etc/bbuild b/src/build/citest/etc/bbuild index aa59ddf6f..f3b7f4ff9 100644 --- a/src/build/citest/etc/bbuild +++ b/src/build/citest/etc/bbuild @@ -1 +1 @@ -/esw/fips801/Builds/b1221a_1251.801 +/esw/fips801/Builds/b0102c_1251.801 diff --git a/src/build/citest/etc/patches/patchlist.txt b/src/build/citest/etc/patches/patchlist.txt index f6bdfca5e..5c8c92fb3 100644 --- a/src/build/citest/etc/patches/patchlist.txt +++ b/src/build/citest/etc/patches/patchlist.txt @@ -4,10 +4,3 @@ Brief description of the problem or reason for patch -CMVC: Defect/Req for checking the changes into fips810 -Files: list of files -Coreq: list of associated changes, e.g. workarounds.presimsetup - -Move to memory based on different scom address write --RTC: Task 61075 will remove the patch --CMVC: F865077 is integrating the changes --Files: s1.act.patch --Coreq: there are related changes in workarounds.postsimsetup - diff --git a/src/build/citest/etc/patches/s1.act.patch b/src/build/citest/etc/patches/s1.act.patch deleted file mode 100644 index d2df187ea..000000000 --- a/src/build/citest/etc/patches/s1.act.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- s1.act.old 2013-01-02 13:32:25.000000000 -0600 -+++ s1.act 2013-01-03 07:02:03.000000000 -0600 -@@ -31,6 +31,7 @@ - # mc01 F864674 missyc 12/17/12 Added PLL Lock actions - # F864543 thi 12/19/12 Fix action file error - # D864795 dsanner 12/20/12 Fix clock actions -+# F865077 dsanner 01/02/13 Updated exitCacheContainedMode - - CAUSE_EFFECT { - LABEL=[Assert all logic clock domains off when chip logic power asserted off] -@@ -483,9 +484,10 @@ - # Note: Memory regions must have been created prior to this - # This will exit cache contained when non mirror bar is writen to any EX core. - # This only happens on the master core --CAUSE_EFFECT CHIPLETS ex { -+CAUSE_EFFECT { - LABEL=[Exit Cache Contained mode] -- WATCH=[REG(MYCHIPLET,0x0001080b)] -+ WATCH=[REG(0x0201340C)] -+ CAUSE: TARGET=[LOGIC(0xFF0CC005)] OP=[BIT,ON] BIT=[0] # Master chip - EFFECT: TARGET=[MODULE(exitCacheContainedMode)] OP=[MODULECALL] - } diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup index 24a53b5e7..dd7fc7f32 100755 --- a/src/build/citest/etc/workarounds.postsimsetup +++ b/src/build/citest/etc/workarounds.postsimsetup @@ -31,8 +31,7 @@ echo "+++ Updating s1.act" mkdir -p $sb/simu/data/cec-chip cp $BACKING_BUILD/src/simu/data/cec-chip/s1.act $sb/simu/data/cec-chip -## Update exitCacheContainedMode action to remove sim workaround -## Remove with RTC 61075, CMVC F865077 -echo "+++ Update exitCacheContainedMode action to remove sim workaround" -patch -p0 $sb/simu/data/cec-chip/s1.act $HOSTBOOTROOT/src/build/citest/etc/patches/s1.act.patch +## Update tweak address till F865457 goes in, RTC 61075 +echo "+++ Update exitCacheContainedMode scom addr" +sed -i -e's/0x02012040/0x0201340C/' $sb/simu/data/cec-chip/s1.act |
