diff options
10 files changed, 1992 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.C b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.C index b9eec1b5e..c18f014ff 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.C @@ -16,3 +16,30 @@ /* deposited with the U.S. Copyright Office. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file ecc_traits.C +/// @brief Traits class for the MC ECC syndrome registers +/// +// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> +// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#include <fapi2.H> +#include <lib/ecc/ecc_traits.H> + +namespace mss +{ + +// we need these declarations here in order for the linker to see the definitions +// in the eccTraits class +constexpr const uint64_t eccTraits<fapi2::TARGET_TYPE_MCA>::MAINLINE_NCE_REGS[]; +constexpr const uint64_t eccTraits<fapi2::TARGET_TYPE_MCA>::MAINLINE_RCE_REGS[]; +constexpr const uint64_t eccTraits<fapi2::TARGET_TYPE_MCA>::MAINLINE_MPE_REGS[]; +constexpr const uint64_t eccTraits<fapi2::TARGET_TYPE_MCA>::MAINLINE_UE_REGS[]; +constexpr const uint64_t eccTraits<fapi2::TARGET_TYPE_MCA>::MAINLINE_AUE_REGS[]; +constexpr const uint64_t eccTraits<fapi2::TARGET_TYPE_MCA>::ERROR_VECTOR_REGS[]; + +} // close namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.H index fafa73be9..75f79b42f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.H @@ -16,3 +16,226 @@ /* deposited with the U.S. Copyright Office. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file ecc_traits.H +/// @brief Traits class for the MC ECC syndrome registers +/// +// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> +// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#ifndef _MSS_ECC_TRAITS_H_ +#define _MSS_ECC_TRAITS_H_ + +#include <p9_mc_scom_addresses.H> +#include <p9_mc_scom_addresses_fld.H> +#include <lib/shared/mss_const.H> + +namespace mss +{ + +/// +/// @class eccTraits +/// @brief a collection of traits associated with the MC ECC interface +/// @tparam T fapi2::TargetType representing the memory controller +/// +template< fapi2::TargetType T > +class eccTraits; + +/// +/// @class eccTraits +/// @brief a collection of traits associated with the Centaur MC ECC interface +/// +template<> +class eccTraits<fapi2::TARGET_TYPE_MBA> +{ +}; + +/// +/// @class eccTraits +/// @brief a collection of traits associated with the Nimbus MC ECC interface +/// +template<> +class eccTraits<fapi2::TARGET_TYPE_MCA> +{ + public: + // MCA ECC registers - must be 64 bits. + static constexpr uint64_t HARDWARE_MS0_REG = MCA_HWMS0; + static constexpr uint64_t HARDWARE_MS1_REG = MCA_WDF_HWMS1; + static constexpr uint64_t HARDWARE_MS2_REG = MCA_HWMS2; + static constexpr uint64_t HARDWARE_MS3_REG = MCA_HWMS3; + static constexpr uint64_t HARDWARE_MS4_REG = MCA_HWMS4; + static constexpr uint64_t HARDWARE_MS5_REG = MCA_HWMS5; + static constexpr uint64_t HARDWARE_MS6_REG = MCA_HWMS6; + static constexpr uint64_t HARDWARE_MS7_REG = MCA_HWMS7; + static constexpr uint64_t FIRMWARE_MS0_REG = MCA_FWMS0; + static constexpr uint64_t FIRMWARE_MS1_REG = MCA_WREITE_FWMS1; + static constexpr uint64_t FIRMWARE_MS2_REG = MCA_FWMS2; + static constexpr uint64_t FIRMWARE_MS3_REG = MCA_FWMS3; + static constexpr uint64_t FIRMWARE_MS4_REG = MCA_FWMS4; + static constexpr uint64_t FIRMWARE_MS5_REG = MCA_FWMS5; + static constexpr uint64_t FIRMWARE_MS6_REG = MCA_FWMS6; + static constexpr uint64_t FIRMWARE_MS7_REG = MCA_FWMS7; + + // MCBIST ECC registers - Register API uses an MCA target instead + // of MCBIST since MCA's relative position is needed to find + // correct reg+field + constexpr static const uint64_t MAINLINE_NCE_REGS[] = + { + MCBIST_MBNCER0Q, + MCBIST_MBNCER1Q, + MCBIST_MBNCER2Q, + MCBIST_MBNCER3Q, + }; + + constexpr static const uint64_t MAINLINE_RCE_REGS[] = + { + MCBIST_MBRCER0Q, + MCBIST_MBRCER1Q, + MCBIST_MBRCER2Q, + MCBIST_MBRCER3Q + }; + + constexpr static const uint64_t MAINLINE_MPE_REGS[] = + { + MCBIST_MBMPER0Q, + MCBIST_MBMPER1Q, + MCBIST_MBMPER2Q, + MCBIST_MBMPER3Q + }; + + constexpr static const uint64_t MAINLINE_UE_REGS[] = + { + MCBIST_MBUER0Q, + MCBIST_MBUER1Q, + MCBIST_MBUER2Q, + MCBIST_MBUER3Q + }; + + constexpr static const uint64_t MAINLINE_AUE_REGS[] = + { + MCBIST_MBAUER0Q, + MCBIST_MBAUER1Q, + MCBIST_MBAUER2Q, + MCBIST_MBAUER3Q + }; + + // Note that these registers store info for a pair of ports + // (thus the duplication) + constexpr static const uint64_t ERROR_VECTOR_REGS[] = + { + MCBIST_MBSEVR0Q, + MCBIST_MBSEVR0Q, + MCBIST_MBSEVR1Q, + MCBIST_MBSEVR1Q + }; + + // Fields, can be any size. + enum + { + HARDWARE_MS_CHIPMARK = MCA_HWMS0_CHIPMARK, + HARDWARE_MS_CHIPMARK_LEN = MCA_HWMS0_CHIPMARK_LEN, + HARDWARE_MS_CONFIRMED = MCA_HWMS0_CONFIRMED, + HARDWARE_MS_EXIT1 = MCA_HWMS0_EXIT_1, + FIRMWARE_MS_MARK = MCA_FWMS0_MARK, + FIRMWARE_MS_MARK_LEN = MCA_FWMS0_MARK_LEN, + FIRMWARE_MS_TYPE = MCA_FWMS0_TYPE, + FIRMWARE_MS_REGION = MCA_FWMS0_REGION, + FIRMWARE_MS_REGION_LEN = MCA_FWMS0_REGION_LEN, + FIRMWARE_MS_ADDRESS = MCA_FWMS0_ADDRESS, + FIRMWARE_MS_ADDRESS_LEN = MCA_FWMS0_ADDRESS_LEN, + FIRMWARE_MS_EXIT1 = MCA_FWMS0_EXIT_1, + NCE_ADDR_TRAP = MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ADDR_TRAP, + NCE_ADDR_TRAP_LEN = MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ADDR_TRAP_LEN, + NCE_ON_RCE = MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ON_RCE, + NCE_IS_TCE = MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_IS_TCE, + RCE_ADDR_TRAP = MCBIST_MBRCER0Q_PORT_0_MAINLINE_RCE_ADDR_TRAP, + RCE_ADDR_TRAP_LEN = MCBIST_MBRCER0Q_PORT_0_MAINLINE_RCE_ADDR_TRAP_LEN, + MPE_ADDR_TRAP = MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ADDR_TRAP, + MPE_ADDR_TRAP_LEN = MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ADDR_TRAP_LEN, + MPE_ON_RCE = MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ON_RCE, + UE_ADDR_TRAP = MCBIST_MBUER0Q_PORT_0_MAINLINE_UE_ADDR_TRAP, + UE_ADDR_TRAP_LEN = MCBIST_MBUER0Q_PORT_0_MAINLINE_UE_ADDR_TRAP_LEN, + AUE_ADDR_TRAP = MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP, + AUE_ADDR_TRAP_LEN = MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP_LEN, + P0_NCE_GALOIS = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_GALOIS_FIELD, + P0_NCE_GALOIS_LEN = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_GALOIS_FIELD_LEN, + P0_NCE_MAGNITUDE = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD, + P0_NCE_MAGNITUDE_LEN = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD_LEN, + P0_TCE_GALOIS = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_GALOIS_FIELD, + P0_TCE_GALOIS_LEN = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_GALOIS_FIELD_LEN, + P0_TCE_MAGNITUDE = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD, + P0_TCE_MAGNITUDE_LEN = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD_LEN, + P1_NCE_GALOIS = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_GALOIS_FIELD, + P1_NCE_GALOIS_LEN = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_GALOIS_FIELD_LEN, + P1_NCE_MAGNITUDE = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD, + P1_NCE_MAGNITUDE_LEN = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD_LEN, + P1_TCE_GALOIS = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_GALOIS_FIELD, + P1_TCE_GALOIS_LEN = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_GALOIS_FIELD_LEN, + P1_TCE_MAGNITUDE = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD, + P1_TCE_MAGNITUDE_LEN = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD_LEN, + CURRENT_ADDR_TRAP = MCBIST_MCBMCATQ_CFG_CURRENT_ADDR_TRAP, + CURRENT_ADDR_TRAP_LEN = MCBIST_MCBMCATQ_CFG_CURRENT_ADDR_TRAP_LEN, + CURRENT_PORT = MCBIST_MCBMCATQ_CFG_CURRENT_PORT_TRAP, + CURRENT_PORT_LEN = MCBIST_MCBMCATQ_CFG_CURRENT_PORT_TRAP_LEN, + CURRENT_DIMM = MCBIST_MCBMCATQ_CFG_CURRENT_DIMM_TRAP, + + }; + +}; + +/// +/// @class eccTraits +/// @brief a collection of traits associated with the Nimbus MC ECC interface +/// +template<> +class eccTraits<fapi2::TARGET_TYPE_MCBIST> +{ + public: + // MCBIST ECC registers - must be 64 bits. + static constexpr uint64_t READ_ERROR_COUNT_REG0 = MCBIST_MBSEC0Q; + static constexpr uint64_t READ_ERROR_COUNT_REG1 = MCBIST_MBSEC1Q; + static constexpr uint64_t MARK_SYMBOL_COUNT_REG = MCBIST_MBSMSECQ; + + // Fields, can be any size. + enum + { + INTERMITTENT_CE_COUNT = MCBIST_MBSEC0Q_INTERMITTENT_CE_COUNT, + INTERMITTENT_CE_COUNT_LEN = MCBIST_MBSEC0Q_INTERMITTENT_CE_COUNT_LEN, + SOFT_CE_COUNT = MCBIST_MBSEC0Q_SOFT_CE_COUNT, + SOFT_CE_COUNT_LEN = MCBIST_MBSEC0Q_SOFT_CE_COUNT_LEN, + HARD_CE_COUNT = MCBIST_MBSEC0Q_HARD_CE_COUNT, + HARD_CE_COUNT_LEN = MCBIST_MBSEC0Q_HARD_CE_COUNT_LEN, + INTERMITTENT_MCE_COUNT = MCBIST_MBSEC0Q_INTERMITTENT_MCE_COUNT, + INTERMITTENT_MCE_COUNT_LEN = MCBIST_MBSEC0Q_INTERMITTENT_MCE_COUNT_LEN, + SOFT_MCE_COUNT = MCBIST_MBSEC0Q_SOFT_MCE_COUNT, + SOFT_MCE_COUNT_LEN = MCBIST_MBSEC0Q_SOFT_MCE_COUNT_LEN, + HARD_MCE_COUNT = MCBIST_MBSEC1Q_HARD_MCE_COUNT, + HARD_MCE_COUNT_LEN = MCBIST_MBSEC1Q_HARD_MCE_COUNT_LEN, + ICE_COUNT = MCBIST_MBSEC1Q_ICE_COUNT, + ICE_COUNT_LEN = MCBIST_MBSEC1Q_ICE_COUNT_LEN, + UE_COUNT = MCBIST_MBSEC1Q_UE_COUNT, + UE_COUNT_LEN = MCBIST_MBSEC1Q_UE_COUNT_LEN, + AUE_COUNT = MCBIST_MBSEC1Q_AUE, + AUE_COUNT_LEN = MCBIST_MBSEC1Q_AUE_LEN, + RCE_COUNT = MCBIST_MBSEC1Q_RCE_COUNT, + RCE_COUNT_LEN = MCBIST_MBSEC1Q_RCE_COUNT_LEN, + SYMBOL0_COUNT = MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT, + SYMBOL0_COUNT_LEN = MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT_LEN, + SYMBOL1_COUNT = MCBIST_MBSMSECQ_MCE_SYMBOL1_COUNT, + SYMBOL1_COUNT_LEN = MCBIST_MBSMSECQ_MCE_SYMBOL1_COUNT_LEN, + SYMBOL2_COUNT = MCBIST_MBSMSECQ_MCE_SYMBOL2_COUNT, + SYMBOL2_COUNT_LEN = MCBIST_MBSMSECQ_MCE_SYMBOL2_COUNT_LEN, + SYMBOL3_COUNT = MCBIST_MBSMSECQ_MCE_SYMBOL3_COUNT, + SYMBOL3_COUNT_LEN = MCBIST_MBSMSECQ_MCE_SYMBOL3_COUNT_LEN, + + }; + +}; + +} // close namespace mss + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/fw_mark_store.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/fw_mark_store.H index 43041e520..ef73c7c96 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/fw_mark_store.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/fw_mark_store.H @@ -16,3 +16,550 @@ /* deposited with the U.S. Copyright Office. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file fw_mark_store.H +/// @brief Subroutines for the MC firmware mark store registers +/// +// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> +// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#ifndef _MSS_FW_MARK_STORE_H_ +#define _MSS_FW_MARK_STORE_H_ + +#include <fapi2.H> +#include <lib/mcbist/address.H> +#include <lib/utils/scom.H> +#include <lib/ecc/ecc_traits.H> +#include <lib/shared/mss_const.H> + +namespace mss +{ + +namespace ecc +{ + +namespace fwms +{ + +/// +/// @brief Read Firmware Mark Store (FWMS) register +/// @tparam R master rank number +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< uint64_t R, fapi2::TargetType T, typename TT = eccTraits<T> > +inline fapi2::ReturnCode read_rank( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + static_assert((R < MAX_MRANK_PER_PORT), "Master rank index failed range check"); + FAPI_TRY( mss::getScom(i_target, (TT::FIRMWARE_MS0_REG + R), o_data) ); + FAPI_INF("read_rank<%d>: 0x%016lx", R, o_data); +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Read Firmware Mark Store (FWMS) rank 0 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode read_rank0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + return ( read_rank<0>(i_target, o_data) ); +} + +/// +/// @brief Read Firmware Mark Store (FWMS) rank 1 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode read_rank1( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + return ( read_rank<1>(i_target, o_data) ); +} + +/// +/// @brief Read Firmware Mark Store (FWMS) rank 2 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode read_rank2( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + return ( read_rank<2>(i_target, o_data) ); +} + +/// +/// @brief Read Firmware Mark Store (FWMS) rank 3 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode read_rank3( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + return ( read_rank<3>(i_target, o_data) ); +} + +/// +/// @brief Read Firmware Mark Store (FWMS) rank 4 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode read_rank4( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + return ( read_rank<4>(i_target, o_data) ); +} + +/// +/// @brief Read Firmware Mark Store (FWMS) rank 5 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode read_rank5( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + return ( read_rank<5>(i_target, o_data) ); +} + +/// +/// @brief Read Firmware Mark Store (FWMS) rank 6 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode read_rank6( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + return ( read_rank<6>(i_target, o_data) ); +} + +/// +/// @brief Read Firmware Mark Store (FWMS) rank 7 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode read_rank7( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + return ( read_rank<7>(i_target, o_data) ); +} + +/// +/// @brief Read Firmware Mark Store (FWMS) register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_rank the master rank index +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, + const uint64_t i_rank, + fapi2::buffer<uint64_t>& o_data ) +{ + switch (i_rank) + { + case(0): + return ( read_rank0(i_target, o_data) ); + + case(1): + return ( read_rank1(i_target, o_data) ); + + case(2): + return ( read_rank2(i_target, o_data) ); + + case(3): + return ( read_rank3(i_target, o_data) ); + + case(4): + return ( read_rank4(i_target, o_data) ); + + case(5): + return ( read_rank5(i_target, o_data) ); + + case(6): + return ( read_rank6(i_target, o_data) ); + + case(7): + return ( read_rank7(i_target, o_data) ); + + default: + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } +} + +/// +/// @brief Write Firmware Mark Store (FWMS) register +/// @tparam R master rank number +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< uint64_t R, fapi2::TargetType T, typename TT = eccTraits<T> > +inline fapi2::ReturnCode write_rank( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + static_assert((R < MAX_MRANK_PER_PORT), "Master rank index failed range check"); + FAPI_TRY( mss::putScom(i_target, (TT::FIRMWARE_MS0_REG + R), i_data) ); + FAPI_INF("write_rank<%d>: 0x%016lx", R, i_data); +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Write Firmware Mark Store (FWMS) rank 0 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode write_rank0( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + return ( write_rank<0>(i_target, i_data) ); +} + +/// +/// @brief Write Firmware Mark Store (FWMS) rank 1 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode write_rank1( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + return ( write_rank<1>(i_target, i_data) ); +} + +/// +/// @brief Write Firmware Mark Store (FWMS) rank 2 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode write_rank2( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + return ( write_rank<2>(i_target, i_data) ); +} + +/// +/// @brief Write Firmware Mark Store (FWMS) rank 3 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode write_rank3( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + return ( write_rank<3>(i_target, i_data) ); +} + +/// +/// @brief Write Firmware Mark Store (FWMS) rank 4 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode write_rank4( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + return ( write_rank<4>(i_target, i_data) ); +} + +/// +/// @brief Write Firmware Mark Store (FWMS) rank 5 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode write_rank5( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + return ( write_rank<5>(i_target, i_data) ); +} + +/// +/// @brief Write Firmware Mark Store (FWMS) rank 6 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode write_rank6( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + return ( write_rank<6>(i_target, i_data) ); +} + +/// +/// @brief Write Firmware Mark Store (FWMS) rank 7 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode write_rank7( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + return ( write_rank<7>(i_target, i_data) ); +} + +/// +/// @brief Write Firmware Mark Store (FWMS) register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_rank the master rank index +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, + const uint64_t i_rank, + const fapi2::buffer<uint64_t>& i_data ) +{ + switch (i_rank) + { + case(0): + return ( write_rank0(i_target, i_data) ); + + case(1): + return ( write_rank1(i_target, i_data) ); + + case(2): + return ( write_rank2(i_target, i_data) ); + + case(3): + return ( write_rank3(i_target, i_data) ); + + case(4): + return ( write_rank4(i_target, i_data) ); + + case(5): + return ( write_rank5(i_target, i_data) ); + + case(6): + return ( write_rank6(i_target, i_data) ); + + case(7): + return ( write_rank7(i_target, i_data) ); + + default: + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } +} + +/// +/// @brief set_mark +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in, out] io_data the register value +/// @param[in] i_value the value of the field +/// @note FWMS0_MARK: mark (Galois field code) +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void set_mark( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) +{ + io_data.insertFromRight<TT::FIRMWARE_MS_MARK, TT::FIRMWARE_MS_MARK_LEN>(i_value); + FAPI_INF("set_mark: 0x%02lx", i_value); +} + +/// +/// @brief get_mark +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_data the register value +/// @param[out] o_value the value of the field +/// @note FWMS0_MARK: mark (Galois field code) +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void get_mark( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) +{ + i_data.extractToRight<TT::FIRMWARE_MS_MARK, TT::FIRMWARE_MS_MARK_LEN>(o_value); + FAPI_INF("get_mark: 0x%02lx", o_value); +} + +/// +/// @brief set_type +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in, out] io_data the register value +/// @param[in] i_value the value of the field +/// @note FWMS0_TYPE: mark type +/// @note Dial enums: +/// @note SYMBOL=>0b1 +/// @note CHIP=>0b0 +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void set_type( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) +{ + io_data.writeBit<TT::FIRMWARE_MS_TYPE>(i_value); + FAPI_INF("set_type: 0x%01lx", i_value); +} + +/// +/// @brief get_type +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_data the register value +/// @param[out] o_value the value of the field +/// @note FWMS0_TYPE: mark type +/// @note Dial enums: +/// @note SYMBOL=>0b1 +/// @note CHIP=>0b0 +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void get_type( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) +{ + o_value = i_data.getBit<TT::FIRMWARE_MS_TYPE>(); + FAPI_INF("get_type: 0x%01lx", o_value); +} + +/// +/// @brief set_region +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in, out] io_data the register value +/// @param[in] i_value the value of the field +/// @note FWMS0_REGION: Selects mark region (address range to which mark applies) +/// @note Dial enums: +/// @note DISABLED=>0b000 +/// @note RESERVED=>0b001 +/// @note BANK=>0b010 +/// @note BANKGROUP=>0b011 +/// @note SRANK=>0b100 +/// @note MRANK=>0b101 +/// @note DIMM=>0b110 +/// @note UNIVERSAL=>0b111 +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void set_region( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) +{ + io_data.insertFromRight<TT::FIRMWARE_MS_REGION, TT::FIRMWARE_MS_REGION_LEN>(i_value); + FAPI_INF("set_region: 0x%02lx", i_value); +} + +/// +/// @brief get_region +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_data the register value +/// @param[out] o_value the value of the field +/// @note FWMS0_REGION: Selects mark region (address range to which mark applies) +/// @note Dial enums: +/// @note DISABLED=>0b000 +/// @note RESERVED=>0b001 +/// @note BANK=>0b010 +/// @note BANKGROUP=>0b011 +/// @note SRANK=>0b100 +/// @note MRANK=>0b101 +/// @note DIMM=>0b110 +/// @note UNIVERSAL=>0b111 +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void get_region( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) +{ + i_data.extractToRight<TT::FIRMWARE_MS_REGION, TT::FIRMWARE_MS_REGION_LEN>(o_value); + FAPI_INF("get_region: 0x%02lx", o_value); +} + +/// +/// @brief set_address +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in, out] io_data the register value +/// @param[in] i_address mcbist::address form of address field +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void set_address( fapi2::buffer<uint64_t>& io_data, const mcbist::address& i_address) +{ + // construct fwms::address from mcbist::address + const auto l_addr = address<T>(i_address); + io_data.insert<TT::FIRMWARE_MS_ADDRESS, TT::FIRMWARE_MS_ADDRESS_LEN, TT::FIRMWARE_MS_ADDRESS>(l_addr); + FAPI_INF("set_address: 0x%016lx", uint64_t(l_addr)); +} + +/// +/// @brief get_address +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_data the register value +/// @param[out] o_address mcbist::address form of address field +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void get_address( const fapi2::buffer<uint64_t>& i_data, mcbist::address& o_address ) +{ + // construct fwms::address from i_data + const auto l_addr = address<T>(uint64_t(i_data)); + // construct mcbist::address from fwms::address + o_address = mcbist::address(l_addr); + FAPI_INF("get_address: 0x%016lx", uint64_t(l_addr)); +} + +/// +/// @brief set_exit_1 +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in, out] io_data the register value +/// @param[in] i_state mss::YES or mss::NO - desired state +/// @note FWMS0_EXIT_1: When set, bypass-enabled reads using this mark will use exit 1 +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void set_exit_1( fapi2::buffer<uint64_t>& io_data, const mss::states i_state ) +{ + io_data.writeBit<TT::FIRMWARE_MS_EXIT1>(i_state); + FAPI_INF("set_exit_1: 0x%01lx", i_state); +} + +/// +/// @brief get_exit_1 +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_data the register value +/// @param[out] o_state mss::YES or mss::NO - representing the state of the field +/// @note FWMS0_EXIT_1: When set, bypass-enabled reads using this mark will use exit 1 +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void get_exit_1( const fapi2::buffer<uint64_t>& i_data, mss::states& o_state ) +{ + o_state = (i_data.getBit<TT::FIRMWARE_MS_EXIT1>() == false) ? mss::NO : mss::YES; + FAPI_INF("get_exit_1: 0x%01lx", o_state); +} + +} // close namespace fwms + +} // close namespace ecc + +} // close namespace mss + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/hw_mark_store.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/hw_mark_store.H index c25aa4136..7aa728f5a 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/hw_mark_store.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/hw_mark_store.H @@ -16,3 +16,463 @@ /* deposited with the U.S. Copyright Office. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file hw_mark_store.H +/// @brief Subroutines for the MC hardware mark store registers +/// +// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> +// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#ifndef _MSS_HW_MARK_STORE_H_ +#define _MSS_HW_MARK_STORE_H_ + +#include <fapi2.H> +#include <lib/ecc/ecc_traits.H> +#include <lib/utils/scom.H> + +namespace mss +{ + +namespace ecc +{ + +namespace hwms +{ + +/// +/// @brief Read Hardware Mark Store (HWMS) register +/// @tparam R master rank number +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< uint64_t R, fapi2::TargetType T, typename TT = eccTraits<T> > +inline fapi2::ReturnCode read_rank( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + static_assert((R < MAX_MRANK_PER_PORT), "Master rank index failed range check"); + FAPI_TRY( mss::getScom(i_target, (TT::HARDWARE_MS0_REG + R), o_data) ); + FAPI_INF("read_rank<%d>: 0x%016lx", R, o_data); +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Read Hardware Mark Store (HWMS) rank 0 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode read_rank0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + return ( read_rank<0>(i_target, o_data) ); +} + +/// +/// @brief Read Hardware Mark Store (HWMS) rank 1 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode read_rank1( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + return ( read_rank<1>(i_target, o_data) ); +} + +/// +/// @brief Read Hardware Mark Store (HWMS) rank 2 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode read_rank2( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + return ( read_rank<2>(i_target, o_data) ); +} + +/// +/// @brief Read Hardware Mark Store (HWMS) rank 3 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode read_rank3( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + return ( read_rank<3>(i_target, o_data) ); +} + +/// +/// @brief Read Hardware Mark Store (HWMS) rank 4 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode read_rank4( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + return ( read_rank<4>(i_target, o_data) ); +} + +/// +/// @brief Read Hardware Mark Store (HWMS) rank 5 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode read_rank5( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + return ( read_rank<5>(i_target, o_data) ); +} + +/// +/// @brief Read Hardware Mark Store (HWMS) rank 6 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode read_rank6( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + return ( read_rank<6>(i_target, o_data) ); +} + +/// +/// @brief Read Hardware Mark Store (HWMS) rank 7 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode read_rank7( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + return ( read_rank<7>(i_target, o_data) ); +} + +/// +/// @brief Read Hardware Mark Store (HWMS) register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_rank the master rank index +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, + const uint64_t i_rank, + fapi2::buffer<uint64_t>& o_data ) +{ + switch (i_rank) + { + case(0): + return ( read_rank0(i_target, o_data) ); + + case(1): + return ( read_rank1(i_target, o_data) ); + + case(2): + return ( read_rank2(i_target, o_data) ); + + case(3): + return ( read_rank3(i_target, o_data) ); + + case(4): + return ( read_rank4(i_target, o_data) ); + + case(5): + return ( read_rank5(i_target, o_data) ); + + case(6): + return ( read_rank6(i_target, o_data) ); + + case(7): + return ( read_rank7(i_target, o_data) ); + + default: + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } +} + +/// +/// @brief Write Hardware Mark Store (HWMS) register +/// @tparam R master rank number +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< uint64_t R, fapi2::TargetType T, typename TT = eccTraits<T> > +inline fapi2::ReturnCode write_rank( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + static_assert((R < MAX_MRANK_PER_PORT), "Master rank index failed range check"); + FAPI_TRY( mss::putScom(i_target, (TT::HARDWARE_MS0_REG + R), i_data) ); + FAPI_INF("write_rank<%d>: 0x%016lx", R, i_data); +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Write Hardware Mark Store (HWMS) rank 0 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode write_rank0( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + return ( write_rank<0>(i_target, i_data) ); +} + +/// +/// @brief Write Hardware Mark Store (HWMS) rank 1 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode write_rank1( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + return ( write_rank<1>(i_target, i_data) ); +} + +/// +/// @brief Write Hardware Mark Store (HWMS) rank 2 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode write_rank2( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + return ( write_rank<2>(i_target, i_data) ); +} + +/// +/// @brief Write Hardware Mark Store (HWMS) rank 3 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode write_rank3( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + return ( write_rank<3>(i_target, i_data) ); +} + +/// +/// @brief Write Hardware Mark Store (HWMS) rank 4 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode write_rank4( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + return ( write_rank<4>(i_target, i_data) ); +} + +/// +/// @brief Write Hardware Mark Store (HWMS) rank 5 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode write_rank5( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + return ( write_rank<5>(i_target, i_data) ); +} + +/// +/// @brief Write Hardware Mark Store (HWMS) rank 6 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode write_rank6( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + return ( write_rank<6>(i_target, i_data) ); +} + +/// +/// @brief Write Hardware Mark Store (HWMS) rank 7 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode write_rank7( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + return ( write_rank<7>(i_target, i_data) ); +} + +/// +/// @brief Write Hardware Mark Store (HWMS) register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_rank the master rank index +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, + const uint64_t i_rank, + const fapi2::buffer<uint64_t>& i_data ) +{ + switch (i_rank) + { + case(0): + return ( write_rank0(i_target, i_data) ); + + case(1): + return ( write_rank1(i_target, i_data) ); + + case(2): + return ( write_rank2(i_target, i_data) ); + + case(3): + return ( write_rank3(i_target, i_data) ); + + case(4): + return ( write_rank4(i_target, i_data) ); + + case(5): + return ( write_rank5(i_target, i_data) ); + + case(6): + return ( write_rank6(i_target, i_data) ); + + case(7): + return ( write_rank7(i_target, i_data) ); + + default: + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } +} + +/// +/// @brief set_chipmark +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in, out] io_data the register value +/// @param[in] i_value the value of the field +/// @note HWMS0_CHIPMARK: Hardware chipmark (Galois field code) +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void set_chipmark( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) +{ + io_data.insertFromRight<TT::HARDWARE_MS_CHIPMARK, TT::HARDWARE_MS_CHIPMARK_LEN>(i_value); + FAPI_INF("set_chipmark: 0x%02lx", i_value); +} + +/// +/// @brief get_chipmark +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_data the register value +/// @param[out] o_value the value of the field +/// @note HWMS0_CHIPMARK: Hardware chipmark (Galois field code) +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void get_chipmark( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) +{ + i_data.extractToRight<TT::HARDWARE_MS_CHIPMARK, TT::HARDWARE_MS_CHIPMARK_LEN>(o_value); + FAPI_INF("get_chipmark: 0x%02lx", o_value); +} + +/// +/// @brief set_confirmed +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in, out] io_data the register value +/// @param[in] i_state mss::YES or mss::NO - desired state +/// @note HWMS0_CONFIRMED: chipmark confirmed +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void set_confirmed( fapi2::buffer<uint64_t>& io_data, const mss::states i_state ) +{ + io_data.writeBit<TT::HARDWARE_MS_CONFIRMED>(i_state); + FAPI_INF("set_confirmed: 0x%01lx", i_state); +} + +/// +/// @brief get_confirmed +/// @tparam T fapi2 Target Type +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_data the register value +/// @param[out] o_state mss::YES or mss::NO - representing the state of the field +/// @note HWMS0_CONFIRMED: chipmark confirmed +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void get_confirmed( const fapi2::buffer<uint64_t>& i_data, mss::states& o_state ) +{ + o_state = (i_data.getBit<TT::HARDWARE_MS_CONFIRMED>() == false) ? mss::NO : mss::YES; + FAPI_INF("get_confirmed: 0x%01lx", o_state); +} + +/// +/// @brief set_exit_1 +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in, out] io_data the register value +/// @param[in] i_state mss::YES or mss::NO - desired state +/// @note HWMS0_EXIT_1: When set, bypass-enabled reads using this mark will +/// @note use exit 1; otherwise exit 0 +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void set_exit_1( fapi2::buffer<uint64_t>& io_data, const mss::states i_state ) +{ + io_data.writeBit<TT::HARDWARE_MS_EXIT1>(i_state); + FAPI_INF("set_exit_1: 0x%01lx", i_state); +} + +/// +/// @brief get_exit_1 +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_data the register value +/// @param[out] o_state mss::YES or mss::NO - representing the state of the field +/// @note HWMS0_EXIT_1: When set, bypass-enabled reads using this mark will +/// @note use exit 1; otherwise exit 0 +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void get_exit_1( const fapi2::buffer<uint64_t>& i_data, mss::states& o_state ) +{ + o_state = (i_data.getBit<TT::HARDWARE_MS_EXIT1>() == false) ? mss::NO : mss::YES; + FAPI_INF("get_exit_1: 0x%01lx", o_state); +} + +} // close namespace hwms + +} // close namespace ecc + +} // close namespace mss + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_mpe_trap.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_mpe_trap.H index 1d038128e..6e2d35eff 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_mpe_trap.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_mpe_trap.H @@ -16,3 +16,141 @@ /* deposited with the U.S. Copyright Office. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file mainline_mpe_trap.H +/// @brief Subroutines for the MC mainline mpe address trap registers (MBNCER*Q) +/// +// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> +// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#ifndef _MSS_MAINLINE_MPE_TRAP_H_ +#define _MSS_MAINLINE_MPE_TRAP_H_ + +#include <fapi2.H> +#include <lib/mcbist/address.H> +#include <lib/utils/scom.H> +#include <lib/utils/find.H> +#include <lib/ecc/ecc_traits.H> + +namespace mss +{ + +namespace ecc +{ + +namespace mainline_mpe_trap +{ + +/// +/// @brief Read MBS Mainline MPE Address Trap (MBMPER*Q) register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = eccTraits<T> > +inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + const auto& l_mcbist_target = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); + const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); + + FAPI_TRY( mss::getScom(l_mcbist_target, (TT::MAINLINE_MPE_REGS[l_port]), o_data) ); + FAPI_INF("read: 0x%016lx", o_data); +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Write MBS Mainline MPE Address Trap (MBMPER*Q) register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = eccTraits<T> > +inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + const auto& l_mcbist_target = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); + const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); + + FAPI_TRY( mss::putScom(l_mcbist_target, (TT::MAINLINE_MPE_REGS[l_port]), i_data) ); + FAPI_INF("write: 0x%016lx", i_data); +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief set_address +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in, out] io_data the register value +/// @param[in] i_address mcbist::address form of address field +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void set_address( fapi2::buffer<uint64_t>& io_data, const mcbist::address& i_address) +{ + io_data.insertFromRight<TT::MPE_ADDR_TRAP, TT::MPE_ADDR_TRAP_LEN>(uint64_t(i_address)); + FAPI_INF("set_address: 0x%016lx", uint64_t(i_address)); +} + +/// +/// @brief get_address +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_data the register value +/// @param[out] o_address mcbist::address form of address field +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void get_address( const fapi2::buffer<uint64_t>& i_data, mcbist::address& o_address ) +{ + uint64_t l_addr = 0; + i_data.extractToRight<TT::MPE_ADDR_TRAP, TT::MPE_ADDR_TRAP_LEN>(l_addr); + o_address = mcbist::address(l_addr); + FAPI_INF("get_address: 0x%016lx", uint64_t(l_addr)); +} + +/// +/// @brief set_mpe_on_rce +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in, out] io_data the register value +/// @param[in] i_state mss::YES or mss::NO - desired state +/// @note MBMPER0Q_PORT_0_MAINLINE_MPE_ON_RCE: Indicates whether if this error +/// @note came on the retry of a UE, RCD, or AUE as part of an RCE +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void set_mpe_on_rce( fapi2::buffer<uint64_t>& io_data, const mss::states i_state ) +{ + io_data.writeBit<TT::MPE_ON_RCE>(i_state); + FAPI_INF("set_mpe_on_rce: 0x%01lx", i_state); +} + +/// +/// @brief get_mpe_on_rce +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_data the register value +/// @param[out] o_state mss::YES or mss::NO - representing the state of the field +/// @note MBMPER0Q_PORT_0_MAINLINE_MPE_ON_RCE: Indicates whether if this error +/// @note came on the retry of a UE, RCD, or AUE as part of an RCE +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void get_mpe_on_rce( const fapi2::buffer<uint64_t>& i_data, mss::states& o_state ) +{ + o_state = (i_data.getBit<TT::MPE_ON_RCE>() == false) ? mss::NO : mss::YES; + FAPI_INF("get_mpe_on_rce: 0x%01lx", o_state); +} + +} // close namespace mainline_mpe_trap + +} // close namespace ecc + +} // close namespace mss + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_nce_trap.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_nce_trap.H index 41efaa2ff..b5a671f6c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_nce_trap.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_nce_trap.H @@ -16,3 +16,173 @@ /* deposited with the U.S. Copyright Office. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file mainline_nce_trap.H +/// @brief Subroutines for the MC mainline nce address trap registers (MBNCER*Q) +/// +// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> +// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#ifndef _MSS_MAINLINE_NCE_TRAP_H_ +#define _MSS_MAINLINE_NCE_TRAP_H_ + +#include <fapi2.H> +#include <lib/mcbist/address.H> +#include <lib/utils/scom.H> +#include <lib/utils/find.H> +#include <lib/ecc/ecc_traits.H> + +namespace mss +{ + +namespace ecc +{ + +namespace mainline_nce_trap +{ + +/// +/// @brief Read MBS Mainline NCE Address Trap (MBNCER*Q) register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = eccTraits<T> > +inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + const auto& l_mcbist_target = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); + const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); + + FAPI_TRY( mss::getScom(l_mcbist_target, (TT::MAINLINE_NCE_REGS[l_port]), o_data) ); + FAPI_INF("read: 0x%016lx", o_data); +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Write MBS Mainline NCE Address Trap (MBNCER*Q) register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = eccTraits<T> > +inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + const auto& l_mcbist_target = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); + const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); + + FAPI_TRY( mss::putScom(l_mcbist_target, (TT::MAINLINE_NCE_REGS[l_port]), i_data) ); + FAPI_INF("write: 0x%016lx", i_data); +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief set_address +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in, out] io_data the register value +/// @param[in] i_address mcbist::address form of address field +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void set_address( fapi2::buffer<uint64_t>& io_data, const mcbist::address& i_address) +{ + io_data.insertFromRight<TT::NCE_ADDR_TRAP, TT::NCE_ADDR_TRAP_LEN>(uint64_t(i_address)); + FAPI_INF("set_address: 0x%016lx", uint64_t(i_address)); +} + +/// +/// @brief get_address +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_data the register value +/// @param[out] o_address mcbist::address form of address field +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void get_address( const fapi2::buffer<uint64_t>& i_data, mcbist::address& o_address ) +{ + uint64_t l_addr = 0; + i_data.extractToRight<TT::NCE_ADDR_TRAP, TT::NCE_ADDR_TRAP_LEN>(l_addr); + o_address = mcbist::address(l_addr); + FAPI_INF("get_address: 0x%016lx", uint64_t(l_addr)); +} + +/// +/// @brief set_nce_on_rce +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in, out] io_data the register value +/// @param[in] i_state mss::YES or mss::NO - desired state +/// @note MBNCER0Q_PORT_0_MAINLINE_NCE_ON_RCE: Indicates whether if this NCE came on the +/// @note retry of a UE, RCD, or AUE as part of an RCE +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void set_nce_on_rce( fapi2::buffer<uint64_t>& io_data, const mss::states i_state ) +{ + io_data.writeBit<TT::NCE_ON_RCE>(i_state); + FAPI_INF("set_nce_on_rce: 0x%01lx", i_state); +} + +/// +/// @brief get_nce_on_rce +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_data the register value +/// @param[out] o_state mss::YES or mss::NO - representing the state of the field +/// @note MBNCER0Q_PORT_0_MAINLINE_NCE_ON_RCE: Indicates whether if this NCE came on the +/// @note retry of a UE, RCD, or AUE as part of an RCE +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void get_nce_on_rce( const fapi2::buffer<uint64_t>& i_data, mss::states& o_state ) +{ + o_state = (i_data.getBit<TT::NCE_ON_RCE>() == false) ? mss::NO : mss::YES; + FAPI_INF("get_nce_on_rce: 0x%01lx", o_state); +} + +/// +/// @brief set_nce_is_tce +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in, out] io_data the register value +/// @param[in] i_state mss::YES or mss::NO - desired state +/// @note MBNCER0Q_PORT_0_MAINLINE_NCE_IS_TCE: Indicates if this NCE is actually +/// @note a two symbol error (TCE) +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void set_nce_is_tce( fapi2::buffer<uint64_t>& io_data, const mss::states i_state ) +{ + io_data.writeBit<TT::NCE_IS_TCE>(i_state); + FAPI_INF("set_nce_is_tce: 0x%01lx", i_state); +} + +/// +/// @brief get_nce_is_tce +/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_data the register value +/// @param[out] o_state mss::YES or mss::NO - representing the state of the field +/// @note MBNCER0Q_PORT_0_MAINLINE_NCE_IS_TCE: Indicates if this NCE is actually +/// @note a two symbol error (TCE) +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > +inline void get_nce_is_tce( const fapi2::buffer<uint64_t>& i_data, mss::states& o_state ) +{ + o_state = (i_data.getBit<TT::NCE_IS_TCE>() == false) ? mss::NO : mss::YES; + FAPI_INF("get_nce_is_tce: 0x%01lx", o_state); +} + +} // close namespace mainline_nce_trap + +} // close namespace ecc + +} // close namespace mss + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mbs_error_vector_trap.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mbs_error_vector_trap.H index f25c2ee7f..f903bb197 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mbs_error_vector_trap.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mbs_error_vector_trap.H @@ -16,3 +16,302 @@ /* deposited with the U.S. Copyright Office. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file mbs_error_vector_trap.H +/// @brief Subroutines for the MC MBS error vector trap registers (MBSEVR*Q) +/// +// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> +// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#ifndef _MSS_MBS_ERROR_VECTOR_TRAP_H_ +#define _MSS_MBS_ERROR_VECTOR_TRAP_H_ + +#include <fapi2.H> +#include <lib/utils/scom.H> +#include <lib/utils/find.H> +#include <lib/ecc/ecc_traits.H> + +namespace mss +{ + +namespace ecc +{ + +namespace mbs_error_vector_trap +{ + +/// +/// @brief Read MBS Error Vector Trap (MBSEVR*Q) register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = eccTraits<T> > +inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + const auto& l_mcbist_target = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); + const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); + + FAPI_TRY( mss::getScom(l_mcbist_target, (TT::ERROR_VECTOR_REGS[l_port]), o_data) ); + FAPI_INF("read: 0x%016lx", o_data); +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Write MBS Error Vector Trap (MBSEVR*Q) register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = eccTraits<T> > +inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + const auto& l_mcbist_target = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); + const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); + + FAPI_TRY( mss::putScom(l_mcbist_target, (TT::ERROR_VECTOR_REGS[l_port]), i_data) ); + FAPI_INF("write: 0x%016lx", i_data); +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief set_nce_galois +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[in, out] io_data the register value +/// @param[in] i_value the value of the field +/// +template< fapi2::TargetType T, typename TT = eccTraits<T> > +inline void set_nce_galois( const fapi2::Target<T>& i_target, + fapi2::buffer<uint64_t>& io_data, + const uint64_t i_value) +{ + const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); + + // divide by 2 because each register holds info for a pair of ports + if ((l_port % 2) == 0) + { + io_data.insertFromRight<TT::P0_NCE_GALOIS, TT::P0_NCE_GALOIS_LEN>(i_value); + } + else + { + io_data.insertFromRight<TT::P1_NCE_GALOIS, TT::P1_NCE_GALOIS_LEN>(i_value); + } + + FAPI_INF("set_nce_galois: 0x%016lx", i_value); +} + +/// +/// @brief get_nce_galois +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the register value +/// @param[out] i_value the value of the field +/// +template< fapi2::TargetType T, typename TT = eccTraits<T> > +inline void get_nce_galois( const fapi2::Target<T>& i_target, + const fapi2::buffer<uint64_t>& i_data, + uint64_t& o_value) +{ + const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); + + // divide by 2 because each register holds info for a pair of ports + if ((l_port % 2) == 0) + { + i_data.extractToRight<TT::P0_NCE_GALOIS, TT::P0_NCE_GALOIS_LEN>(o_value); + } + else + { + i_data.extractToRight<TT::P1_NCE_GALOIS, TT::P1_NCE_GALOIS_LEN>(o_value); + } + + FAPI_INF("get_nce_galois: 0x%016lx", o_value); +} + +/// +/// @brief set_nce_magnitude +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[in, out] io_data the register value +/// @param[in] i_value the value of the field +/// +template< fapi2::TargetType T, typename TT = eccTraits<T> > +inline void set_nce_magnitude( const fapi2::Target<T>& i_target, + fapi2::buffer<uint64_t>& io_data, + const uint64_t i_value) +{ + const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); + + // divide by 2 because each register holds info for a pair of ports + if ((l_port % 2) == 0) + { + io_data.insertFromRight<TT::P0_NCE_MAGNITUDE, TT::P0_NCE_MAGNITUDE_LEN>(i_value); + } + else + { + io_data.insertFromRight<TT::P1_NCE_MAGNITUDE, TT::P1_NCE_MAGNITUDE_LEN>(i_value); + } + + FAPI_INF("set_nce_magnitude: 0x%016lx", i_value); +} + +/// +/// @brief get_nce_magnitude +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the register value +/// @param[out] i_value the value of the field +/// +template< fapi2::TargetType T, typename TT = eccTraits<T> > +inline void get_nce_magnitude( const fapi2::Target<T>& i_target, + const fapi2::buffer<uint64_t>& i_data, + uint64_t& o_value) +{ + const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); + + // divide by 2 because each register holds info for a pair of ports + if ((l_port % 2) == 0) + { + i_data.extractToRight<TT::P0_NCE_MAGNITUDE, TT::P0_NCE_MAGNITUDE_LEN>(o_value); + } + else + { + i_data.extractToRight<TT::P1_NCE_MAGNITUDE, TT::P1_NCE_MAGNITUDE_LEN>(o_value); + } + + FAPI_INF("get_nce_magnitude: 0x%016lx", o_value); +} + +/// +/// @brief set_tce_galois +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[in, out] io_data the register value +/// @param[in] i_value the value of the field +/// +template< fapi2::TargetType T, typename TT = eccTraits<T> > +inline void set_tce_galois( const fapi2::Target<T>& i_target, + fapi2::buffer<uint64_t>& io_data, + const uint64_t i_value) +{ + const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); + + // divide by 2 because each register holds info for a pair of ports + if ((l_port % 2) == 0) + { + io_data.insertFromRight<TT::P0_TCE_GALOIS, TT::P0_TCE_GALOIS_LEN>(i_value); + } + else + { + io_data.insertFromRight<TT::P1_TCE_GALOIS, TT::P1_TCE_GALOIS_LEN>(i_value); + } + + FAPI_INF("set_tce_galois: 0x%016lx", i_value); +} + +/// +/// @brief get_tce_galois +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the register value +/// @param[out] i_value the value of the field +/// +template< fapi2::TargetType T, typename TT = eccTraits<T> > +inline void get_tce_galois( const fapi2::Target<T>& i_target, + const fapi2::buffer<uint64_t>& i_data, + uint64_t& o_value) +{ + const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); + + // divide by 2 because each register holds info for a pair of ports + if ((l_port % 2) == 0) + { + i_data.extractToRight<TT::P0_TCE_GALOIS, TT::P0_TCE_GALOIS_LEN>(o_value); + } + else + { + i_data.extractToRight<TT::P1_TCE_GALOIS, TT::P1_TCE_GALOIS_LEN>(o_value); + } + + FAPI_INF("get_tce_galois: 0x%016lx", o_value); +} + +/// +/// @brief set_tce_magnitude +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[in, out] io_data the register value +/// @param[in] i_value the value of the field +/// +template< fapi2::TargetType T, typename TT = eccTraits<T> > +inline void set_tce_magnitude( const fapi2::Target<T>& i_target, + fapi2::buffer<uint64_t>& io_data, + const uint64_t i_value) +{ + const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); + + // divide by 2 because each register holds info for a pair of ports + if ((l_port % 2) == 0) + { + io_data.insertFromRight<TT::P0_TCE_MAGNITUDE, TT::P0_TCE_MAGNITUDE_LEN>(i_value); + } + else + { + io_data.insertFromRight<TT::P1_TCE_MAGNITUDE, TT::P1_TCE_MAGNITUDE_LEN>(i_value); + } + + FAPI_INF("set_tce_magnitude: 0x%016lx", i_value); +} + +/// +/// @brief get_tce_magnitude +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the register value +/// @param[out] i_value the value of the field +/// +template< fapi2::TargetType T, typename TT = eccTraits<T> > +inline void get_tce_magnitude( const fapi2::Target<T>& i_target, + const fapi2::buffer<uint64_t>& i_data, + uint64_t& o_value) +{ + const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); + + // divide by 2 because each register holds info for a pair of ports + if ((l_port % 2) == 0) + { + i_data.extractToRight<TT::P0_TCE_MAGNITUDE, TT::P0_TCE_MAGNITUDE_LEN>(o_value); + } + else + { + i_data.extractToRight<TT::P1_TCE_MAGNITUDE, TT::P1_TCE_MAGNITUDE_LEN>(o_value); + } + + FAPI_INF("get_tce_magnitude: 0x%016lx", o_value); +} + +} // close namespace mbs_error_vector_trap + +} // close namespace ecc + +} // close namespace mss + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/address.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/address.H index 707e27dad..23d325245 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/address.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/address.H @@ -32,9 +32,36 @@ #include <fapi2.H> #include <utility> +#include <lib/ecc/ecc_traits.H> namespace mss { + +namespace ecc +{ + +namespace fwms +{ + +/// +/// @class address +/// @brief Converts Firmware Mark Store ADDRESS field into mcbist::address +/// @tparam T fapi2 Target Type defaults to fapi2::TARGET_TYPE_MCA +/// @tparam TT traits type defaults to eccTraits<T> +/// @note template argument defaults are in forward declaration in lib/mcbist/address.H +/// @note 12 = dimm +/// @note 13:14 = mrank +/// @note 15:17 = srank +/// @note 18:19 = bank group +/// @note 20:22 = bank +/// +// See declaration below +template< fapi2::TargetType T, typename TT = eccTraits<T> > +class address; + +} // close namespace fwms +} // close namespace ecc + namespace mcbist { @@ -89,6 +116,28 @@ class address } /// + /// @brief Construct an address from an ecc::fwms::address + /// @tparam T fapi2 Target Type + /// @param[in] i_address representing an address field from a firmware mark store register + /// + template< fapi2::TargetType T > + address( const ecc::fwms::address<T>& i_address ) + { + fapi2::buffer<uint64_t> l_value = uint64_t(i_address); + uint64_t l_temp = 0; + l_value.extractToRight<ecc::fwms::address<T>::DIMM.first, ecc::fwms::address<T>::DIMM.second>(l_temp); + this->set_field<DIMM>(l_temp); + l_value.extractToRight<ecc::fwms::address<T>::MRANK.first, ecc::fwms::address<T>::MRANK.second>(l_temp); + this->set_field<MRANK>(l_temp); + l_value.extractToRight<ecc::fwms::address<T>::SRANK.first, ecc::fwms::address<T>::SRANK.second>(l_temp); + this->set_field<SRANK>(l_temp); + l_value.extractToRight<ecc::fwms::address<T>::BANK_GROUP.first, ecc::fwms::address<T>::BANK_GROUP.second>(l_temp); + this->set_field<BANK_GROUP>(l_temp); + l_value.extractToRight<ecc::fwms::address<T>::BANK.first, ecc::fwms::address<T>::BANK.second>(l_temp); + this->set_field<BANK>(l_temp); + } + + /// /// @brief Conversion operator to uint64_t /// @warn Right-aligns the address /// @@ -372,8 +421,64 @@ class address fapi2::buffer<uint64_t> iv_address; }; -} // namespace +} // close namespace mcbist + +// Documented above in its declaration. +template< fapi2::TargetType T, typename TT > +class ecc::fwms::address +{ + public: + // first is the start bit of the field, second is the length + typedef std::pair<uint64_t, uint64_t> field; + + constexpr static field DIMM = {TT::FIRMWARE_MS_ADDRESS, 1}; + constexpr static field MRANK = {TT::FIRMWARE_MS_ADDRESS + 1, 2}; + constexpr static field SRANK = {TT::FIRMWARE_MS_ADDRESS + 3, 3}; + constexpr static field BANK_GROUP = {TT::FIRMWARE_MS_ADDRESS + 6, 2}; + constexpr static field BANK = {TT::FIRMWARE_MS_ADDRESS + 8, 3}; + constexpr static field LAST_VALID = BANK; + + address() = default; + + /// + /// @brief Construct an address from a uint64_t (scom'ed value) + /// @param[in] i_value representing raw value from FWMS register + /// + address( const uint64_t& i_value ): + iv_value(i_value) + { + } + + /// + /// @brief Construct an address from an mcbist::address + /// @param[in] i_mcbist_address mcbist formatted address + /// @note Construction of mcbist::address from ecc::fwms::address + /// @note located in mcbist::address class + /// + address( const mcbist::address& i_mcbist_address ) + { + iv_value.insertFromRight<DIMM.first, DIMM.second>(i_mcbist_address.get_field<mcbist::address::DIMM>()); + iv_value.insertFromRight<MRANK.first, MRANK.second>(i_mcbist_address.get_field<mcbist::address::MRANK>()); + iv_value.insertFromRight<SRANK.first, SRANK.second>(i_mcbist_address.get_field<mcbist::address::SRANK>()); + iv_value.insertFromRight<BANK_GROUP.first, BANK_GROUP.second> + (i_mcbist_address.get_field<mcbist::address::BANK_GROUP>()); + iv_value.insertFromRight<BANK.first, BANK.second>(i_mcbist_address.get_field<mcbist::address::BANK>()); + } + + /// + /// @brief Conversion operator to uint64_t + /// + inline operator uint64_t() const + { + uint64_t l_temp = 0; + iv_value.extract<TT::FIRMWARE_MS_ADDRESS, TT::FIRMWARE_MS_ADDRESS_LEN, TT::FIRMWARE_MS_ADDRESS>(l_temp); + return l_temp; + } + + private: + fapi2::buffer<uint64_t> iv_value; +}; -} // namespace +} // close namespace mss #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H index 29af7ba94..61be05a2f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H @@ -144,6 +144,7 @@ class mcbistTraits<fapi2::TARGET_TYPE_MCBIST> MCBIST_START = MCBIST_MCB_CNTLQ_START, MCBIST_STOP = MCBIST_MCB_CNTLQ_STOP, MCBIST_RESUME = MCBIST_MCB_CNTLQ_RESUME_FROM_PAUSE, + MCBIST_RESET_ERRORS = MCBIST_MCB_CNTLQ_RESET_ERROR_LOGS, MCBIST_IN_PROGRESS = MCBIST_MCB_CNTLSTATQ_IP, MCBIST_DONE = MCBIST_MCB_CNTLSTATQ_DONE, @@ -1389,6 +1390,25 @@ fapi_try_exit: } /// +/// @brief Reset the MCBIST error logs +/// @tparam T the fapi2::TargetType - derived +/// @tparam TT the mcbistTraits associated with T - derived +/// @param[in] i_target the target to effect +/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS iff OK +/// +template< fapi2::TargetType T, typename TT = mcbistTraits<T> > +inline fapi2::ReturnCode reset_errors( const fapi2::Target<T>& i_target ) +{ + fapi2::buffer<uint64_t> l_buf; + + FAPI_TRY( mss::getScom(i_target, TT::CNTLQ_REG, l_buf) ); + FAPI_TRY( mss::putScom(i_target, TT::CNTLQ_REG, l_buf.setBit<TT::MCBIST_RESET_ERRORS>()) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// /// @brief Return whether or not the MCBIST engine has an operation in progress /// @tparam T the fapi2::TargetType - derived /// @param[in] i_target the target to effect diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H index 5d75691ac..c10073723 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H @@ -44,6 +44,7 @@ enum sizes MAX_DIMM_PER_PORT = 2, MAX_RANK_PER_DIMM = 4, MAX_PRIMARY_RANKS_PER_PORT = 4, + MAX_MRANK_PER_PORT = MAX_DIMM_PER_PORT * MAX_RANK_PER_DIMM, RANK_MID_POINT = 4, ///< Which rank number indicates the switch to the other DIMM DEFAULT_POLL_LIMIT = 10, ///< the number of poll attempts in the event we can't calculate another MAX_NUM_IMP = 4, ///< number of impedances valid per slew type |
