diff options
| -rw-r--r-- | src/usr/isteps/istep13/call_mss_ddr_phy_reset.C | 9 | ||||
| -rwxr-xr-x | src/usr/targeting/common/xmltohb/target_types.xml | 23 |
2 files changed, 32 insertions, 0 deletions
diff --git a/src/usr/isteps/istep13/call_mss_ddr_phy_reset.C b/src/usr/isteps/istep13/call_mss_ddr_phy_reset.C index dc4f2c93e..63eb8c34a 100644 --- a/src/usr/isteps/istep13/call_mss_ddr_phy_reset.C +++ b/src/usr/isteps/istep13/call_mss_ddr_phy_reset.C @@ -53,6 +53,12 @@ void* call_mss_ddr_phy_reset (void *io_pArgs) IStepError l_stepError; + TARGETING::Target * sys = NULL; + TARGETING::targetService().getTopLevelTarget( sys ); + +// TODO: RTC 155373 Need to remove hack that is setting IS_SIMULATION to 1 for this substep + sys->setAttr<TARGETING::ATTR_IS_SIMULATION>(1); + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_ddr_phy_reset entry" ); @@ -94,6 +100,9 @@ void* call_mss_ddr_phy_reset (void *io_pArgs) } } // end l_mcbistNum loop +// TODO: RTC 155373 Need to remove hack that is setting IS_SIMULATION to 1 for this substep + sys->setAttr<TARGETING::ATTR_IS_SIMULATION>(0); + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_ddr_phy_reset exit" ); diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index 0c791401f..1a2250451 100755 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -2116,6 +2116,20 @@ <attribute><id>PROC_EPS_WRITE_CYCLES_T1</id></attribute> <attribute><id>PROC_EPS_WRITE_CYCLES_T2</id></attribute> <!-- End proc_fbc_eff_config --> + <attribute><id>MSS_VOLT_DDR3_VDDR_SLOPE</id></attribute> + <attribute><id>MSS_VOLT_DDR3_VDDR_INTERCEPT</id></attribute> + <attribute><id>MSS_VOLT_DDR4_VDDR_SLOPE</id></attribute> + <attribute><id>MSS_VOLT_DDR4_VDDR_INTERCEPT</id></attribute> + <attribute><id>MRW_DDR3_VDDR_MAX_LIMIT</id></attribute> + <attribute><id>MRW_DDR4_VDDR_MAX_LIMIT</id></attribute> + <attribute><id>MSS_VOLT_DDR3_VDDR_SLOPE_POST_DRAM_INIT</id></attribute> + <attribute><id>MSS_VOLT_DDR3_VDDR_INTERCEPT_POST_DRAM_INIT</id></attribute> + <attribute><id>MRW_DDR3_VDDR_MAX_LIMIT_POST_DRAM_INIT</id></attribute> + <attribute><id>MSS_VOLT_DDR4_VDDR_SLOPE_POST_DRAM_INIT</id></attribute> + <attribute><id>MSS_VOLT_DDR4_VDDR_INTERCEPT_POST_DRAM_INIT</id></attribute> + <attribute><id>MRW_DDR4_VDDR_MAX_LIMIT_POST_DRAM_INIT</id></attribute> + <attribute><id>MSS_VOLT_VPP_SLOPE</id></attribute> + <attribute><id>MSS_VOLT_VPP_INTERCEPT</id></attribute> </targetType> <!-- enc-node-power9 --> @@ -2143,6 +2157,14 @@ <attribute><id>FRU_ID</id></attribute> <attribute><id>TPM_PRIMARY_INFO</id></attribute> <attribute><id>TPM_BACKUP_INFO</id></attribute> + <attribute><id>MSS_VOLT_VPP_SLOPE_EFF_CONFIG</id></attribute> + <attribute><id>MSS_VOLT_VPP_INTERCEPT_EFF_CONFIG</id></attribute> + <attribute><id>MSS_VOLT_DDR3_VDDR_SLOPE_EFF_CONFIG</id></attribute> + <attribute><id>MSS_VOLT_DDR3_VDDR_INTERCEPT_EFF_CONFIG</id></attribute> + <attribute><id>MRW_DDR3_VDDR_MAX_LIMIT_EFF_CONFIG</id></attribute> + <attribute><id>MSS_VOLT_DDR4_VDDR_SLOPE_EFF_CONFIG</id></attribute> + <attribute><id>MSS_VOLT_DDR4_VDDR_INTERCEPT_EFF_CONFIG</id></attribute> + <attribute><id>MRW_DDR4_VDDR_MAX_LIMIT_EFF_CONFIG</id></attribute> </targetType> <!-- chip-processor-power9 --> @@ -2758,6 +2780,7 @@ <attribute><id>EFF_DRAM_TWTR_L</id></attribute> <attribute><id>EFF_DRAM_TMAW</id></attribute> <attribute><id>CDM_DOMAIN</id><default>MEM</default></attribute> + <attribute><id>VMEM_ID</id></attribute> </targetType> <targetType> |
