diff options
| -rw-r--r-- | src/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h | 298 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h | 296 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h | 233 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h | 178 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h | 230 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h | 132 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/pm/p9_pm_utils.C | 69 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/pm/p9_pm_utils.H | 46 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C | 8 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.H | 31 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.mk | 11 | ||||
| -rw-r--r-- | src/usr/isteps/istep06/makefile | 3 | ||||
| -rw-r--r-- | src/usr/isteps/istep08/makefile | 3 | ||||
| -rw-r--r-- | src/usr/isteps/pm/pm.mk | 3 |
14 files changed, 1490 insertions, 51 deletions
diff --git a/src/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h b/src/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h new file mode 100644 index 000000000..e50561ac3 --- /dev/null +++ b/src/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h @@ -0,0 +1,298 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// @file p9_pstates_pgpe_occ_api.h +/// @brief Structures used between PGPE HCode and OCC Firmware +/// +// *HWP HW Owner : Rahul Batra <rbatra@us.ibm.com> +// *HWP HW Owner : Michael Floyd <mfloyd@us.ibm.com> +// *HWP Team : PM +// *HWP Level : 1 +// *HWP Consumed by : PGPE:OCC + + +#ifndef __P9_PSTATES_PGPE_API_H__ +#define __P9_PSTATES_PGPE_API_H__ + +#include <p9_pstates_common.h> + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------- +// IPC from 405 +//--------------- + +enum MESSAGE_ID_IPI2HI +{ + MSGID_405_INVALID = 0, + MSGID_405_START_SUSPEND = 1, + MSGID_405_CLIPS = 2, + MSGID_405_WOF_INDEX = 3 +}; + +// +// Return Codes +// +// Will be filled in with the PK_PANIC code + +// +// PMCR Owner +// +enum PMCR_OWNER +{ + PMCR_OWNER_OCC = 0, + PMCR_OWNER_HOST = 1 +}; + +typedef struct ipcmsg_base +{ + uint8_t msg_id; + uint8_t rc; +} ipcmsg_base_t; + +typedef struct ipcmsg_start_suspend +{ + ipcmsg_base_t msg_cb; + uint8_t action; + PMCR_OWNER pmcr_owner; + +} ipcmsg_start_suspend_t; + + +typedef struct ipcmsg_clips +{ + ipcmsg_base_t msg_cb; + uint8_t ps_clip_min[MAX_QUADS]; + uint8_t ps_clip_max[MAX_QUADS]; + uint8_t pad[2]; +} ipcmsg_clips_t; + + +typedef struct ipcmsg_wof +{ + ipcmsg_base_t msg_cb; + uint8_t enable; // WOF enable + uint8_t ceff_vdd_index; // Effective Capacitance VDD + uint8_t ceff_vdn_index; // Effective Capacitance VDN + uint8_t fratio_index; // Frequency Ratio + uint8_t vratio_index; // Voltage Ratio + uint8_t pad; +} ipcmsg_wof_t; + + +typedef struct ipcmsg_reset +{ + ipcmsg_base_t msg_cb; +} ipcmsg_reset_t; + + +// ----------------------------------------------------------------------------- +// Start Pstate Table + +#define MAX_PSTATE_TABLE_ENTRIES 256 + +/// Pstate Table produce by the PGPE for consumption by OCC Firmware +/// +/// This structure defines the Pstate Table content +/// -- 16B structure + +typedef struct +{ + /// Pstate number + Pstate pstate; + + /// Assocated Frequency (in MHz) + uint16_t frequency_mhz; + + /// Internal VDD voltage ID at the output of the PFET header + uint8_t internal_vdd_vid; + +} OCCPstateTable_entry_t; + +typedef struct +{ + /// Number of Pstate Table entries + uint32_t entries; + + /// Internal VDD voltage ID at the output of the PFET header + OCCPstateTable_entry_t table[MAX_PSTATE_TABLE_ENTRIES]; + +} OCCPstateTable_t; + +// End Pstate Table +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +// Start FFDC + +/// Scopes of the First Failure Data Capture (FFDC) registers +enum scope_type = +{ + FFDC_CHIP = 0, // Address is chip scope (eg absolute) + FFDC_QUAD = 1, // Address + 0x01000000*quad for good quads from 0 to 5 + FFDC_CORE = 2, // Address + 0x01000000*core for good cores from 0 to 23 + FFDC_CME = 3 // Address if EX is even; Address + 0x400*EX for EX odd for good Exs from 0 to 11 +}; + +/// Address types of First Failure Data Capture (FFDC) register addresses +enum scope_type = +{ + FFDC_OCI = 0, // Address is an OCI address + FFDC_SCOM = 1 // Address is a SCOM address +}; + +/// Register definition of the Hcode FFDC register list +typedef struct +{ + uint32_t address; + union address_attribute + { + uint32_t value; + struct + { + uint32_t address_type : 16; + uint32_t scope : 16; + } attr; + } +} Hcode_FFDC_entry_t; + +/// Hcode FFDC register list +typedef struct +{ + /// Number of FFDC address list entries + uint32_t list_entries; + + /// FFDC Address list + Hcode_FFDC_entry_t list[MAX_FFDC_REG_LIST]; +} Hcode_FFDC_list_t; + + + +/// Hcode FFDC register list +/// @todo RTC: 161183 Fill out the rest of this FFDC list +/// @note The reserved FFDC space for registers and traces set aside in the +/// OCC is 1KB. On the register side, the following list will generate +/// 12B of content (4B address, 8B data) x the good entries per scope. +/// CHIP scope are not dependent on partial good or currently active and will +/// take 12B x 8 = 96B. CME scope entries will, at maximum, generate 12B x +/// 12 CMEs x 4 SCOMs = 576B.. The overall totla for registers is 96 + 576 +/// +#define MAX_FFDC_REG_LIST 12 +typedef struct Hcode_FFDC_list = +{ + {PERV_TP_OCC_SCOM_OCCLFIR, FFDC_SCOM, FFDC_CHIP }, // OCC LFIR + {PU_PBAFIR, FFDC_SCOM, FFDC_CHIP }, // PBA LFIR + {EX_CME_SCOM_LFIR, FFDC_SCOM, FFDC_CME }, // CME LFIR + {PU_GPE3_GPEDBG_OCI, FFDC_OCI, FFDC_CHIP }, // SGPE XSR, SPRG0 + {PU_GPE3_GPEDDR_OCI, FFDC_OCI, FFDC_CHIP }, // SGPE IR, EDR + {PU_GPE3_PPE_XIDBGPRO, FFDC_OCI, FFDC_CHIP }, // SGPE XSR, IAR + {PU_GPE2_GPEDBG_OCI, FFDC_OCI, FFDC_CHIP }, // PGPE XSR, SPRG0 + {PU_GPE2_GPEDDR_OCI, FFDC_OCI, FFDC_CHIP }, // PGPE IR, EDR + {PU_GPE2_PPE_XIDBGPRO, FFDC_OCI, FFDC_CHIP }, // PGPE XSR, IAR + {EX_PPE_XIRAMDBG, FFDC_SCOM, FFDC_CME }, // CME XSR, SPRG0 + {EX_PPE_XIRAMEDR, FFDC_SCOM, FFDC_CME }, // CME IR, EDR + {EX_PPE_XIDBGPRO, FFDC_SCOM, FFDC_CME }, // CME XSR, IAR +}; + +// End FFDC +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +// Start Quad State + +typedef union quad_state0 +{ + uint64_t value; + struct + { + uint32_t high_order; + uint32_t low_order; + } words; + struct + { + uint64_t quad0_pstate : 8; // Pstate of Quad 0; 0xFF indicates EQ is off + uint64_t quad1_pstate : 8; // Pstate of Quad 1; 0xFF indicates EQ is off + uint64_t quad2_pstate : 8; // Pstate of Quad 2; 0xFF indicates EQ is off + uint64_t quad3_pstate : 8; // Pstate of Quad 3; 0xFF indicates EQ is off + uint64_t ivrm_state : 4; // ivrm state: bit vector 0:quad0, 1:quad1, 2:quad2, 3;quad3 + uint64_t ivrm_state_rsvd : 4; + uint64_t core_poweron_state : 16; // bit vector: 0:core0, 1:core1, ..., 15:core15 + uint64_t external_vrm_setpoint : 8; // set point in mV + } fields; +} quad_state0_t; + +typedef union quad_state1 +{ + uint64_t value; + struct + { + uint32_t high_order; + uint32_t low_order; + } words; + struct + { + uint64_t quad4_pstate : 8; // Pstate of Quad 4; 0xFF indicates EQ is off + uint64_t quad5_pstate : 8; // Pstate of Quad 5; 0xFF indicates EQ is off + uint64_t quad_pstate_rsvd : 16; + uint64_t ivrm_state : 2; // ivrm state: bit vector 0:quad4, 1:quad5 + uint64_t ivrm_state_rsvd : 6; + uint64_t core_poweron_state : 8; // bit vector: 0:core16, 1:core17, ..., 7:core23 + uint64_t core_poweron_state_rsvd : 8; + uint64_t external_vrm_setpoint : 8; // set point in mV + } fields; +} quad_state1_t; + +// End Quad State +// ----------------------------------------------------------------------------- + + +typedef struct +{ + /// Magic number + version. "OPS" || version (nibble) + uint32_t magic; + + /// PGPE Beacon + uint32_t pgpe_beacon; + + /// Actual Pstate 0 - Quads 0, 1, 2, 3 + quad_state0_t quad_pstate_0; + + /// Actual Pstate 1 - Quads 4, 5 + quad_state1_t quad_pstate_1; + + /// FFDC Address list + Hcode_FFDC_list_t ffdc_list; + + /// Pstate Table + OCCPstateTable_t pstate_table; + +} HcodeOCCSharedData_t; + +#ifdef __cplusplus +} // end extern C +#endif + +#endif /* __P9_PSTATES_PGPE_API_H__ */ diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h new file mode 100644 index 000000000..20b216e34 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h @@ -0,0 +1,296 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// @file p9_pstates_cmeqm.h +/// @brief Pstate structures and support routines for CME Hcode +/// +// *HWP HW Owner : Rahul Batra <rbatra@us.ibm.com> +// *HWP HW Owner : Michael Floyd <mfloyd@us.ibm.com> +// *HWP Team : PM +// *HWP Level : 1 +// *HWP Consumed by : CME:PGPE + +#ifndef __P9_PSTATES_CME_H__ +#define __P9_PSTATES_CME_H__ + + +/// \defgroup QM Flags +/// +/// These are flag bits for the \a Quad Manager field. +/// +/// @{ + +/// qmflag() - Disable Resonant Clock use. +#define PSTATE_RESCLK_DISABLE 0x8000 + +/// qmflag() - Disable IVRM use. +#define PSTATE_IVRMS_DISABLE 0x4000 + +/// qmflag() - Disable VDM use. +#define PSTATE_VDM_DISABLE 0x2000 + +/// qmflag() - Disable WOF. +#define PSTATE_WOF_DISABLE 0x1000 + +/// qmflag() - dpll_dynamic_fmax_enable +#define PSTATE_DPLL_DYNAMIC_FMAX_ENABLE 0x0800 + +/// qmflag() - dpll_dynamic_fmin_enable +#define PSTATE_DPLL_DYNAMIC_FMIN_ENABLE 0x0400 + +/// qmflag() - dpll_droop_protect_enable +#define PSTATE_DPLL_DROOP_PROTECT_ENABLE 0x0200 + +/// @} + + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> + +/// Quad Manager Flags +/// + +typedef union +{ + uint16_t value; + struct + { +#ifdef _BIG_ENDIAN + uint16_t resclk_enable : 1; + uint16_t ivrm_enable : 1; + uint16_t wof_enable : 1; + uint16_t dpll_dynamic_fmax_enable : 1; + uint16_t dpll_dynamic_fmin_enable : 1; + uint16_t dpll_droop_protect_enable : 1; + uint16_t reserved : 10; +#else + uint16_t reserved : 10; + uint16_t dpll_droop_protect_enable : 1; + uint16_t dpll_dynamic_fmin_enable : 1; + uint16_t dpll_dynamic_fmax_enable : 1; + uint16_t wof_enable : 1; + uint16_t ivrm_enable : 1; + uint16_t resclk_enable : 1; +#endif // _BIG_ENDIAN + } fields; + +} QuadManagerFlags; + +/// Resonant Clock Stepping Entry +/// +typedef union +{ + uint16_t value; + struct + { +#ifdef _BIG_ENDIAN + uint16_t sector_buffer : 4; + uint16_t spare1 : 1; + uint16_t pulse_enable : 1; + uint16_t pulse_mode : 2; + uint16_t resonant_switch : 4; + uint16_t spare4 : 4; +#else + uint16_t spare4 : 4; + uint16_t resonant_switch : 4; + uint16_t pulse_mode : 2; + uint16_t pulse_enable : 1; + uint16_t spare1 : 1; + uint16_t sector_buffer : 4; +#endif // _BIG_ENDIAN + } fields; + +} ResonantClockingStepEntry; + +#define RESCLK_FREQ_REGIONS 8 +#define RESCLK_STEPS 64 +#define RESCLK_L3_STEPS 4 + +typedef struct ResonantClockControl +{ + uint8_t resclk_freq[RESCLK_FREQ_REGIONS]; // Lower frequency of Resclk Regions + + uint8_t resclk_index[RESCLK_FREQ_REGIONS]; // Index into value array for the + // respective Resclk Region + + /// Array containing the transition steps + ResonantClockingStepEntry steparray[RESCLK_STEPS]; + + /// Delay between steps (in nanoseconds) + /// Maximum delay: 65.536us + uint16_t step_delay_ns; + + /// L3 Clock Stepping Array + uint8_t l3_steparray[RESCLK_L3_STEPS]; + + /// Resonant Clock Voltage Threshold (in millivolts) + /// This value is used to choose the appropriate L3 clock region setting. + uint16_t l3_threshold_mv; + +} ResonantClockingSetup; + + +/// VDM/Droop Parameter Block +/// +typedef struct +{ + uint8_t vid_compare_override_mv_enable; + uint8_t vid_compare_override_mv[VPD_PV_POINTS]; + uint8_t vdm_response; + + // For the following *_enable fields, bits are defined to indicate + // which of the respective *override* array entries are valid. + // bit 0: UltraTurbo; bit 1: Turbo; bit 2: Nominal; bit 3: PowSave + uint8_t droop_small_override_enable; + uint8_t droop_large_override_enable; + uint8_t droop_extreme_override_enable; + uint8_t overvolt_override_enable; + uint16_t fmin_override_khz_enable; + uint16_t fmax_override_khz_enable; + + // The respecitve *_enable above indicate which index values are valid + uint8_t droop_small_override[VPD_PV_POINTS]; + uint8_t droop_large_override[VPD_PV_POINTS]; + uint8_t droop_extreme_override[VPD_PV_POINTS]; + uint8_t overvolt_override[VPD_PV_POINTS]; + uint16_t fmin_override_khz[VPD_PV_POINTS]; + uint16_t fmax_override_khz[VPD_PV_POINTS]; + + /// Pad structure to 8-byte alignment + /// @todo pad once fully structure is complete. + // uint8_t pad[1]; + +} VDMParmBlock; + + +/// The layout of the data created by the Pstate table creation firmware for +/// comsumption by the Pstate GPE. This data will reside in the Quad +/// Power Management Region (QPMR). +/// + +/// Standard options controlling Pstate setup procedures + +/// System Power Distribution Paramenters +/// +/// Parameters set by system design that influence the power distribution +/// for a rail to the processor module. This values are typically set in the +/// system machine readable workbook and are used in the generation of the +/// Global Pstate Table. This values are carried in the Pstate SuperStructure +/// for use and/or reference by OCC firmware (eg the WOF algorithm) + + +/// IVRM Parameter Block +/// +/// @todo Major work item. Largely will seed the CME Quad Manager to perform +/// iVRM voltage calculations + +#define IVRM_ARRAY_SIZE 64 +typedef struct iVRMInfo +{ + + /// Pwidth from 0.03125 to 1.96875 in 1/32 increments at Vin=Vin_Max + uint8_t strength_lookup[IVRM_ARRAY_SIZE]; // Each entry is a six bit value, right justified + + /// Scaling factor for the Vin_Adder calculation. + uint8_t vin_multiplier[IVRM_ARRAY_SIZE]; // Each entry is from 0 to 255. + + /// Vin_Max used in Vin_Adder calculation (in millivolts) + uint16_t vin_max_mv; + + /// Delay between steps (in nanoseconds) + /// Maximum delay: 65.536us + uint16_t step_delay_ns; + + /// Stabilization delay once target voltage has been reached (in nanoseconds) + /// Maximum delay: 65.536us + uint16_t stablization_delay_ns; + + /// Deadzone (in millivolts) + /// Maximum: 255mV. If this value is 0, 50mV is assumed. + uint8_t deadzone_mv; + + /// Pad to 8B + uint8_t pad; + +} IvrmParmBlock; + + +/// The layout of the data created by the Pstate table creation firmware for +/// comsumption by the CME Quad Manager. This data will reside in the Core +/// Power Management Region (CPMR). +/// +typedef struct +{ + + /// Magic Number + uint64_t magic; // the last byte of this number the structure's version. + + // QM Flags + QuadManagerFlags qmflags; + + /// Operating points + /// + /// VPD operating points are stored without load-line correction. Frequencies + /// are in MHz, voltages are specified in units of 5mV, and currents are + /// in units of 500mA. + VpdOperatingPoint operating_points[VPD_PV_POINTS]; + + /// Loadlines and Distribution values for the VDD rail + SysPowerDistParms vdd_sysparm; + + /// External Biases + /// + /// Biases applied to the VPD operating points prior to load-line correction + /// in setting the external voltages. This is used to recompute the Vin voltage + /// based on the Global Actual Pstate . + /// Values in 0.5% + VpdBias ext_biases[VPD_PV_POINTS]; + + /// Internal Biases + /// + /// Biases applied to the VPD operating points that are used for interpolation + /// in setting the internal voltages (eg Vout to the iVRMs) as part of the + /// Local Actual Pstate. + /// Values in 0.5% + VpdBias int_biases[VPD_PV_POINTS]; + + /// IVRM Data + IvrmParmBlock ivrm; + + /// Resonant Clock Grid Management Setup + ResonantClockingSetup resclk; + + /// VDM Data + VDMParmBlock vdm; + +} LocalPstateParmBlock; + +#ifdef __cplusplus +} // end extern C +#endif + +#endif /* __P9_PSTATES_CME_H__ */ diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h new file mode 100644 index 000000000..4ed35f8e5 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h @@ -0,0 +1,233 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// @file p9_pstates_common.h +/// @brief Common Pstate definitions +/// +// *HWP HW Owner : Rahul Batra <rbatra@us.ibm.com> +// *HWP HW Owner : Michael Floyd <mfloyd@us.ibm.com> +// *HWP Team : PM +// *HWP Level : 1 +// *HWP Consumed by : PGPE:CME:HB:OCC + + +#ifndef __P9_PSTATES_COMMON_H__ +#define __P9_PSTATES_COMMON_H__ + +/// The minimum Pstate (knowing the increasing Pstates numbers represent +/// decreasing frequency) +#define PSTATE_MIN 255 + +/// The maximum Pstate (knowing the increasing Pstates numbers represent +/// decreasing frequency) +#define PSTATE_MAX 0 + +/// The minimum \e legal DPLL frequency code +/// +/// This is ~1GHz with a 16.6MHz tick frequency. +/// @todo Check this and the maximum +#define DPLL_MIN 0x03c + +/// The maximum DPLL frequency code +#define DPLL_MAX 0x1ff + +/// The minimum \a legal (non-power-off) AVS VID code +/// @todo Need to check with J. Kuesmann if there is a limit. May want this +/// to be an attribute. +#define AVS_MIN 0x0000 + +/// The maximum \a legal (non-power-off) AVS VID code +/// @todo Need to check with J. Kuesmann if there is a limit. May want this +/// to be an attribute. +#define AVS_MAX 0xFFFF + +/// The AVS VID base voltage in micro-Volts +#define AVS_BASE_UV 1612500 + +/// The AVS VID step as an unsigned number (micro-Volts) +#define AVS_STEP_UV 1000 + +//ssrivath, Is this the same as IVID_BASE_UV and IVID_STEP_UV below +/// The VRM-11 VID base voltage in micro-Volts +#define VRM11_BASE_UV 1612500 + +/// The VRM-11 VID step as an unsigned number (micro-Volts) +#define VRM11_STEP_UV 6250 + +// ssrivath, iVID values based on Section 2.8.7 of spec +/// The iVID base voltage in micro-Volts +#define IVID_BASE_UV 512000 + +/// The iVID step as an unsigned number (micro-Volts) +#define IVID_STEP_UV 4000 + +/// Maximum number of Quads (4 cores plus associated caches) +#define MAX_QUADS 6 + +// Constants associated with VRM stepping +// @todo Determine what is needed here (eg Attribute mapping) and if any constants +// are warrented + +/// VPD #V Operating Points +#define VPD_PV_POINTS 4 +#define VPD_PV_ORDER_STR {"PowerSave", "Nominal ", "Turbo ", "UltraTurbo"} +#define POWERSAVE 1 +#define NOMINAL 0 +#define TURBO 2 +#define ULTRA 3 +#define POWERBUS 4 +#define VPD_PV_ORDER {POWERSAVE, NOMINAL, TURBO, ULTRA} + +/// IDDQ readings, +#define IDDQ_MEASUREMENTS 6 +#define MEASUREMENT_ELEMENTS 6 // Number of Quads for P9 +#define IDDQ_READINGS_PER_IQ 2 +#define IDDQ_ARRAY_VOLTAGES {0.60, 0.70, 0.80, 0.90, 1.00, 1.10} + +/// WOF Items +#define NUM_ACTIVE_CORES 24 +#define MAX_UT_PSTATES 64 // Oversized + +//ssrivath, Temporary definition +#define PGP_NCORES 24 + +/// Error/Panic codes for support routines +/// @todo Review the necessary error codes. This are really PGPE functions now +/// and many below elsewhere. However, the error code plumbing from PGPE to +/// OCC for error logging purposes is an action. + +#define VRM11_INVALID_VOLTAGE 0x00876101 + +#define PSTATE_OVERFLOW 0x00778a01 +#define PSTATE_UNDERFLOW 0x00778a02 + +#define PSTATE_LT_PSTATE_MIN 0x00778a03 +#define PSTATE_GT_PSTATE_MAX 0x00778a04 + +#define DPLL_OVERFLOW 0x00d75501 +#define DPLL_UNDERFLOW 0x00d75502 + +#define AVSVID_OVERFLOW 0x00843101 +#define AVSVID_UNDERFLOW 0x00843102 + +#define GPST_INVALID_OBJECT 0x00477801 +#define GPST_INVALID_ARGUMENT 0x00477802 +#define GPST_INVALID_ENTRY 0x00477803 +#define GPST_PSTATE_CLIPPED_LOW 0x00477804 +#define GPST_PSTATE_CLIPPED_HIGH 0x00477805 +#define GPST_BUG 0x00477806 +#define GPST_PSTATE_GT_GPST_PMAX 0x00477807 + +#define LPST_INVALID_OBJECT 0x00477901 +#define LPST_GPST_WARNING 0x00477902 +#define LPST_INCR_CLIP_ERROR 0x00477903 + +#ifdef __cplusplus +extern "C" { +#endif + +/// A Pstate type +/// +/// Pstates are unsigned but, to avoid bugs, Pstate register fields should +/// always be extracted to a variable of type Pstate. If the size of Pstate +/// variables ever changes we will have to revisit this convention. +typedef uint8_t Pstate; + +/// A DPLL frequency code +/// +/// DPLL frequency codes (Fmax and Fmult) are 15 bits +typedef uint16_t DpllCode; + +/// An AVS VID code +typedef uint16_t VidAVS; + +// ssrivath, Modified units for vdd/vcs/idd/ics as per P9 VPD spec +/// A VPD operating point +/// +/// VPD operating points are stored without load-line correction. Frequencies +/// are in MHz, voltages are specified in units of 1mV, and characterization +/// currents are specified in units of 100mA. +/// +typedef struct +{ + + uint32_t vdd_mv; + uint32_t vcs_mv; + uint32_t idd_100ma; + uint32_t ics_100ma; + uint32_t frequency_mhz; + uint8_t pstate; // Pstate of this VpdOperating + uint8_t pad[3]; + +} VpdOperatingPoint; + +/// VPD Biases. +/// +/// Percent bias applied to VPD operating points prior to interolation +/// +/// All values on in .5 percent (half percent -> hp) +typedef struct +{ + + int8_t vdd_ext_hp; + int8_t vdd_int_hp; + int8_t vdn_ext_hp; + int8_t vcs_ext_hp; + int8_t frequency_hp; + +} VpdBias; + +/// System Power Distribution Paramenters +/// +/// Parameters set by system design that influence the power distribution +/// for a rail to the processor module. This values are typically set in the +/// system machine readable workbook and are used in the generation of the +/// Global Pstate Table. This values are carried in the Pstate SuperStructure +/// for use and/or reference by OCC firmware (eg the WOF algorithm) + +typedef struct +{ + + /// Loadline + /// Impedance (binary microOhms) of the load line from a processor VDD VRM + /// to the Processor Module pins. + uint32_t loadline_uohm; + + /// Distribution Loss + /// Impedance (binary in microOhms) of the VDD distribution loss sense point + /// to the circuit. + uint32_t distloss_uohm; + + /// Distribution Offset + /// Offset voltage (binary in microvolts) to apply to the rail VRM + /// distribution to the processor module. + uint32_t distoffset_uv; + +} SysPowerDistParms; + +#ifdef __cplusplus +} // end extern C +#endif + +#endif /* __P9_PSTATES_COMMON_H__ */ diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h new file mode 100644 index 000000000..ca3a260b0 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h @@ -0,0 +1,178 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// @file p9_pstates.h +/// @brief Pstate structures and support routines for OCC product firmware +/// +// *HWP HW Owner : Greg Still <stillgs@us.ibm.com> +// *HWP HW Owner : Michael Floyd <mfloyd@us.ibm.com> +// *HWP FW Owner : Martha Broyles <bilpatil@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 1 +// *HWP Consumed by : HB:OCC + +#ifndef __P9_PSTATES_OCC_H__ +#define __P9_PSTATES_OCC_H__ + +#include <p9_pstates_common.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/// IDDQ Reading Type +/// Each entry is 2 bytes. The values are in 6.25mA units; this allow for a +/// maximum value of 409.6A to be represented. +/// +typedef uint16_t iddq_entry_t; + +/// AvgTemp Reading Type +/// Each entry is 1 byte. The values are in 0.5degC units; this allow for a +/// maximum value of 127degC to be represented. +/// +typedef uint16_t avgtemp_entry_t; + +/// Iddq Table +/// +/// A set of arrays of leakage values (Iddq) collected at various voltage +/// conditions during manufacturing test that will feed into the Workload +/// Optimized Frequency algorithms on the OCC. These values are not installed +/// in any hardware facilities. +/// +typedef struct +{ + + /// IDDQ version + uint8_t iddq_version; + + /// Good Quads per Sort + uint8_t good_quads_per_sort; + + /// Good Normal Cores per Sort + uint8_t good_normal_cores_per_sort; + + /// Good Caches per Sort + uint8_t good_caches_per_sort; + + /// Good Normal Cores + uint8_t good_normal_cores[MAX_QUADS]; + + /// Good Caches + uint8_t good_caches[MAX_QUADS]; + + /// RDP to TDP Scaling Factor in 0.01% units + uint16_t rdp_to_tdp_scale_factor; + + /// WOF Iddq Margin (aging factor) in 0.01% units + uint16_t wof_iddq_margin_factor; + + /// Temperature Scale Factor per 10C in 0.01% units + uint16_t temperature_scale_factor; + + /// Spare + uint8_t spare[10]; + + /// IVDD ALL Good Cores ON; 6.25mA units + iddq_entry_t ivdd_all_good_cores_on_caches_on[IDDQ_MEASUREMENTS]; + + /// IVDD ALL Cores OFF; 6.25mA units + iddq_entry_t ivdd_all_cores_off_caches_off[IDDQ_MEASUREMENTS]; + + /// IVDD ALL Good Cores OFF; 6.25mA units + iddq_entry_t ivdd_all_good_cores_off_good_caches_on[IDDQ_MEASUREMENTS]; + + /// IVDD Quad 0 Good Cores ON, Caches ON; 6.25mA units + iddq_entry_t ivdd_quad_good_cores_on_good_caches_on[MAX_QUADS][IDDQ_MEASUREMENTS]; + + /// IVDDN ; 6.25mA units + iddq_entry_t ivdn; + + + /// IVDD ALL Good Cores ON, Caches ON; 6.25mA units + avgtemp_entry_t avgtemp_all_good_cores_on[IDDQ_MEASUREMENTS]; + + /// avgtemp ALL Cores OFF, Caches OFF; 6.25mA units + avgtemp_entry_t avgtemp_all_cores_off_caches_off[IDDQ_MEASUREMENTS]; + + /// avgtemp ALL Good Cores OFF, Caches ON; 6.25mA units + avgtemp_entry_t avgtemp_all_good_cores_off[IDDQ_MEASUREMENTS]; + + /// avgtemp Quad 0 Good Cores ON, Caches ON; 6.25mA units + avgtemp_entry_t avgtemp_quad_good_cores_on[MAX_QUADS][IDDQ_MEASUREMENTS]; + + /// avgtempN ; 6.25mA units + avgtemp_entry_t avgtemp_vdn; + +} IddqTable; + + + +/// The layout of the data created by the Pstate table creation firmware for +/// comsumption by the OCC firmware. This data will reside in the Quad +/// Power Management Region (QPMR). +/// +typedef struct +{ + + /// Magic Number + uint64_t magic; // the last byte of this number the structure's version. + + /// Operating points + /// + /// VPD operating points are stored without load-line correction. Frequencies + /// are in MHz, voltages are specified in units of 5mV, and currents are + /// in units of 500mA. + VpdOperatingPoint operating_points[VPD_PV_POINTS]; + + /// Loadlines and Distribution values for the VDD rail + SysPowerDistParms vdd_sysparm; + + /// Loadlines and Distribution values for the VDN rail + SysPowerDistParms vdn_sysparm; + + /// Loadlines and Distribution values for the VCS rail + SysPowerDistParms vcs_sysparm; + + /// Iddq Table + IddqTable iddq; + + /// WOF Controls + WOFElements wof; + + // Frequency Limits + uint32_t frequency_min_khz; // Comes from PowerSave #V point after biases + uint32_t frequency_max_khz; // Comes from UltraTurbo #V point after biases + uint32_t frequency_step_khz; // Comes from refclk/dpll_divider attributes. + + // Minimum Pstate; Maximum is always 0. + uint32_t pstate_min; // Comes from PowerSave #V point after biases + +} OCCPstateParmBlock; + + +#ifdef __cplusplus +} // end extern C +#endif + +#endif /* __P9_PSTATES_OCC_H__ */ diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h new file mode 100644 index 000000000..0ecad6632 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h @@ -0,0 +1,230 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// @file p9_pstates_pgpe.h +/// @brief Pstate structures and support routines for PGPE Hcode +/// +// *HWP HW Owner : Rahul Batra <rbatra@us.ibm.com> +// *HWP HW Owner : Michael Floyd <mfloyd@us.ibm.com> +// *HWP Team : PM +// *HWP Level : 1 +// *HWP Consumed by : PGPE:HS + + +#ifndef __P9_PSTATES_PGPE_H__ +#define __P9_PSTATES_PGPE_H__ + +#include <p9_pstates_common.h> +#include <p9_pstates_cmeqm.h> + +/// PstateParmsBlock Magic Number +/// +/// This magic number identifies a particular version of the +/// PstateParmsBlock and its substructures. The version number should be +/// kept up to date as changes are made to the layout or contents of the +/// structure. + +#define PSTATE_PARMSBLOCK_MAGIC 0x5053544154453030ull /* PSTATE00 */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> + + +/// Standard options controlling Pstate setup and installation procedures +typedef struct +{ + + /// Option flags; See \ref pstate_options + uint32_t options; + + /// Pad structure to 8 bytes. Could also be used for other options later. + uint32_t pad; + +} PGPEOptions; + +/// UltraTurbo Segment VIDs by Core Count +typedef struct +{ + + /// Number of Segment Pstates + uint8_t ut_segment_pstates; + + /// Maximum number of core possibly active + uint8_t ut_max_cores; + + /// VDD VID modification + /// 1 core active = offset 0 + /// 2 cores active = offset 1 + /// ... + /// 12 cores active = offset 11 + uint8_t ut_segment_vdd_vid[MAX_UT_PSTATES][NUM_ACTIVE_CORES]; + + /// VCS VID modification + /// 1 core active = offset 0 + /// 2 cores active = offset 1 + /// ... + /// 12 cores active = offset 11 + uint8_t ut_segment_vcs_vid[MAX_UT_PSTATES][NUM_ACTIVE_CORES]; + +} VIDModificationTable; + +/// Workload Optimized Frequency (WOF) Elements +/// +/// Structure defining various control elements needed by the WOF algorithm +/// firmware running on the OCC. +/// +typedef struct +{ + + /// WOF Enablement + uint8_t wof_enabled; + + /// TDP<>RDP Current Factor + /// Value read from ??? VPD + /// Defines the scaling factor that converts current (amperage) value from + /// the Thermal Design Point to the Regulator Design Point (RDP) as input + /// to the Workload Optimization Frequency (WOF) OCC algorithm. + /// + /// This is a ratio value and has a granularity of 0.01 decimal. Data + /// is held in hexidecimal (eg 1.22 is represented as 122 and then converted + /// to hex 0x7A). + uint32_t tdp_rdp_factor; + + /// UltraTurbo Segment VIDs by Core Count + VIDModificationTable ut_vid_mod; + + uint8_t pad[4]; + +} WOFElements; + + +/// Global Pstate Parameter Block +/// +/// The GlobalPstateParameterBlock is an abstraction of a set of voltage/frequency +/// operating points along with hardware limits. Besides the hardware global +/// Pstate table, the abstract table contains enough extra information to make +/// it the self-contained source for setting up and managing voltage and +/// frequency in either Hardware or Firmware Pstate mode. +/// +/// When installed in PMC, Global Pstate table indices are adjusted such that +/// the defined Pstates begin with table entry 0. The table need not be full - +/// the \a pmin and \a entries fields define the minimum and maximum Pstates +/// represented in the table. However at least 1 entry must be defined to +/// create a legal table. +/// +/// Note that Global Pstate table structures to be mapped into PMC hardware +/// must be 1KB-aligned. This requirement is fullfilled by ensuring that +/// instances of this structure are 1KB-aligned. +typedef struct +{ + + + /// Magic Number + uint64_t magic; // the last byte of this number the structure's version. + + /// Pstate options + /// + /// The options are included as part of the GlobalPstateTable so that they + /// are available to upon PGPE initialization. + PGPEOptions options; + + /// The frequency associated with Pstate[0] in KHz + uint32_t reference_frequency_khz; + + /// The frequency step in KHz + uint32_t frequency_step_khz; + + /// Operating points + /// + /// VPD operating points are stored without load-line correction. Frequencies + /// are in MHz, voltages are specified in units of 5mV, and currents are + /// in units of 500mA. + VpdOperatingPoint operating_points[VPD_PV_POINTS]; + + /// Biases + /// + /// Biases applied to the VPD operating points prior to load-line correction + /// in setting the external voltages. + /// Values in 0.5% + VpdBias ext_biases[VPD_PV_POINTS]; + + /// Loadlines and Distribution values for the VDD rail + SysPowerDistParms vdd_sysparm; + + /// Loadlines and Distribution values for the VCS rail + SysPowerDistParms vcs_sysparm; + + /// Loadlines and Distribution values for the VDN rail + SysPowerDistParms vdn_sysparm; + + /// The "Safe" Voltage + /// + /// A voltage to be used when safe-mode is activated + /// @todo Need to detail this out yet. + uint32_t safe_voltage_mv; + + /// The "Safe" Frequency + /// + /// A voltage to be used when safe-mode is activated + /// @todo Need to detail this out yet. + uint32_t safe_frequency_khz; + + /// The exponent of the exponential encoding of Pstate stepping delay + uint8_t vrm_stepdelay_range; + + /// The significand of the exponential encoding of Pstate stepping delay + uint8_t vrm_stepdelay_value; + + /// VDM Data + VDMParmBlock vdm; + + /// The following are needed to generated the Pstate Table to HOMER. + + /// Internal Biases + /// + /// Biases applied to the VPD operating points that are used for interpolation + /// in setting the internal voltages (eg Vout to the iVRMs) as part of the + /// Local Actual Pstate. + /// Values in 0.5% + VpdBias int_biases[VPD_PV_POINTS]; + + /// IVRM Data + IvrmParmBlock ivrm; + + /// Resonant Clock Grid Management Setup + ResonantClockingSetup resclk; + + // @todo DPLL Droop Settings. These need communication to SGPE for STOP + +} GlobalPstateParmBlock; + + +#ifdef __cplusplus +} // end extern C +#endif + +#endif /* __P9_PSTATES_PGPE_H__ */ diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h new file mode 100644 index 000000000..a4432c4bd --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h @@ -0,0 +1,132 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// @file p9_pstates_table.h +/// @brief Definition of generated pstate tables written to HOMER PPMR +/// +// *HWP HW Owner : Rahul Batra <rbatra@us.ibm.com> +// *HWP HW Owner : Michael Floyd <mfloyd@us.ibm.com> +// *HWP FW Owner : Martha Broyles <bilpatil@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 1 +// *HWP Consumed by : PGPE:HS + +#ifndef __P9_PSTATES_TABLE_H__ +#define __P9_PSTATES_TABLE_H__ + +#include <p9_pstates_common.h> +#include <p9_pstates_pgpe.h> +#include <p9_pstates_cmeqm.h> + +/// Generated Pstate Table +/// +/// This structure defines the Pstate Tables generated by PGPE Hcode upon +/// initialization. This content depicts the values that will be computed +/// on the fly during Pstate protocol execution based on the Pstate Parameter +/// Block content. + +static const uint32_t MAX_PSTATE_TABLE_ENTRIES = 128; + +#ifdef __cplusplus +extern "C" { +#endif + +/// Pstate Table +/// +/// This structure defines the Pstate Table content +/// -- 16B structure + +typedef struct +{ + /// Pstate number + Pstate pstate; + + /// Assocated Frequency (in MHz) + uint16_t frequency_mhz; + + /// External VRM setpoint (in mV). this directly translates to AVSBus value + uint16_t external_vdd_mv; + + /// Effective VDD voltage at the module pins. This accounts for the system + /// parameter effects. + uint16_t effective_vdd_mv; + + /// Minimum Effective Regulation Voltage (in mV) that supports iVRMs being + /// enabled for this Pstate. This is effective_vdd_mv + the iVRM dead zone + /// (in mV) at this effective_vdd_mv point. + uint16_t effective_regulation_vdd_mv; + + /// Internal VDD voltage at the output of the PFET header + uint16_t internal_vdd_mv; + + /// Internal VDD Voltage Id. Voltage is 512mV + internal_vid*4mV + uint8_t internal_vid; + + /// Voltage Droop Monitor (VDM) setting (in mV) + uint8_t vdm_mv; + + /// Voltage Droop Monitor (VDM) Voltage ID. Voltage is 512mV + vdm_vid*4mV + uint8_t vdm_vid; + + /// Voltage Droop Monitor (VDM) Thresholds + /// Really 4 nibbles holding the encoded threshold value per VDM. + /// @todo Blow this up for which VDM each of the nibbles controls and the + /// encoding. + uint16_t vdm_thresholds; + +} PstateTable; + + +typedef struct +{ + + /// Magic Number + uint64_t magic; // ASCII: "PSTATABL" + + // PGPE content + GlobalPstateParmBlock globalppb; + + /// The fastest frequency - after biases have been applied + uint32_t pstate0_frequency_khz; + + /// Highest Pstate Number => slowest Pstate generated + uint32_t highest_pstate; + + /// Generated table with system paramters included but without biases + PstateTable raw_pstates[MAX_PSTATE_TABLE_ENTRIES]; + + /// Generated table with system paramters and biases + /// Note: if all bias attributes are 0, this content will be the same + /// as the raw_pstates content. + PstateTable biased_pstates[MAX_PSTATE_TABLE_ENTRIES]; + +} GeneratedPstateInfo; + + + +#ifdef __cplusplus +} // end extern C +#endif + +#endif /* __P9_PSTATES_TABLE_H__ */ diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_utils.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_utils.C index 46b6618bc..a30bc4dd4 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_utils.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_utils.C @@ -41,6 +41,75 @@ #include <p9_pm_utils.H> #include <p9_const_common.H> +/// Byte-reverse a 16-bit integer if on a little-endian machine + +uint16_t +revle16(const uint16_t i_x) +{ + uint16_t rx; + +#ifndef _BIG_ENDIAN + uint8_t* pix = (uint8_t*)(&i_x); + uint8_t* prx = (uint8_t*)(&rx); + + prx[0] = pix[1]; + prx[1] = pix[0]; +#else + rx = i_x; +#endif + + return rx; +} + +/// Byte-reverse a 32-bit integer if on a little-endian machine + +uint32_t +revle32(const uint32_t i_x) +{ + uint32_t rx; + +#ifndef _BIG_ENDIAN + uint8_t* pix = (uint8_t*)(&i_x); + uint8_t* prx = (uint8_t*)(&rx); + + prx[0] = pix[3]; + prx[1] = pix[2]; + prx[2] = pix[1]; + prx[3] = pix[0]; +#else + rx = i_x; +#endif + + return rx; +} + + +/// Byte-reverse a 64-bit integer if on a little-endian machine + +uint64_t +revle64(const uint64_t i_x) +{ + uint64_t rx; + +#ifndef _BIG_ENDIAN + uint8_t* pix = (uint8_t*)(&i_x); + uint8_t* prx = (uint8_t*)(&rx); + + prx[0] = pix[7]; + prx[1] = pix[6]; + prx[2] = pix[5]; + prx[3] = pix[4]; + prx[4] = pix[3]; + prx[5] = pix[2]; + prx[6] = pix[1]; + prx[7] = pix[0]; +#else + rx = i_x; +#endif + + return rx; +} + fapi2::ReturnCode p9_pm_glob_fir_trace( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, const char* i_msg) diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_utils.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_utils.H index e311dcfa6..1e6d797a6 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_utils.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_utils.H @@ -29,7 +29,7 @@ // *HWP HWP Owner : Amit Kumar <akumar3@us.ibm.com> // *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Bilicon Patil <bilpatil@in.ibm.com> +// *HWP FW Owner : Prem Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Level : 1 // *HWP Consumed by : HS @@ -46,47 +46,9 @@ // Common macros //------------------------------------------------------------------------------ -#define SET_FIR_ACTION(b, x, y) \ - action_0.writeBit<b>(x); \ - action_1.writeBit<b>(y); - -#define SET_CHECK_STOP(b){SET_FIR_ACTION(b, 0, 0);} -#define SET_RECOV_ATTN(b){SET_FIR_ACTION(b, 0, 1);} -#define SET_RECOV_INTR(b){SET_FIR_ACTION(b, 1, 0);} -#define SET_MALF_ALERT(b){SET_FIR_ACTION(b, 1, 1);} -#define SET_FIR_MASKED(b){mask.setBit<b>();} -#define CLEAR_FIR_MASK(b){mask.clearBit<b>()} - - -/** - * @brief helper function to swizzle given input data - * @note swizles bytes to handle endianess issue. - */ -#if( __BYTE_ORDER == __BIG_ENDIAN ) - -// NOP if it is a big endian system -#define RevLe16(WORD) WORD -#define RevLe32(WORD) WORD -#define RevLe64(WORD) WORD - -#else -#define RevLe16(WORD) \ - ( (((WORD) >> 8) & 0x00FF) | (((WORD) << 8) & 0xFF00) ) - -#define RevLe32(WORD) \ - ( (((WORD) >> 24) & 0x000000FF) | (((WORD) >> 8) & 0x0000FF00) | \ - (((WORD) << 8) & 0x00FF0000) | (((WORD) << 24) & 0xFF000000) ) - -#define RevLe64(WORD) \ - ( (((WORD) >> 56) & 0x00000000000000FF) | \ - (((WORD) >> 40) & 0x000000000000FF00)| \ - (((WORD) >> 24) & 0x0000000000FF0000) | \ - (((WORD) >> 8) & 0x00000000FF000000) | \ - (((WORD) << 8) & 0x000000FF00000000) | \ - (((WORD) << 24) & 0x0000FF0000000000) | \ - (((WORD) << 40) & 0x00FF000000000000) | \ - (((WORD) << 56) & 0xFF00000000000000) ) -#endif +uint16_t revle16(const uint16_t i_x); +uint32_t revle32(const uint32_t i_x); +uint64_t revle64(const uint64_t i_x); //------------------------------------------------------------------------------ // Function prototype diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C index ecfd0372f..efe8c687e 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C @@ -796,7 +796,7 @@ proc_get_mvpd_iddq( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, for (i = 0; i < IDDQ_MEASUREMENTS; i++) { l_iddq_data = *(reinterpret_cast<iddq_entry_t*>(l_buffer_iq_inc)); - io_iddqt->ivdd_all_good_cores_on[i] = revle16(l_iddq_data); + io_iddqt->ivdd_all_good_cores_on_caches_on[i] = revle16(l_iddq_data); FAPI_INF(" IVDDQ with all good cores ON, Measurement %d = %u", i, l_iddq_data); l_buffer_iq_inc += sizeof(iddq_entry_t); } @@ -805,7 +805,7 @@ proc_get_mvpd_iddq( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, for (i = 0; i < IDDQ_MEASUREMENTS; i++) { l_iddq_data = *(reinterpret_cast<iddq_entry_t*>(l_buffer_iq_inc)); - io_iddqt->ivdd_all_cores_off[i] = revle16(l_iddq_data); + io_iddqt->ivdd_all_cores_off_caches_off[i] = revle16(l_iddq_data); FAPI_INF("IVDDQ with all cores and caches OFF, Measurement %d = %u", i, l_iddq_data); l_buffer_iq_inc += sizeof(iddq_entry_t); } @@ -814,7 +814,7 @@ proc_get_mvpd_iddq( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, for (i = 0; i < IDDQ_MEASUREMENTS; i++) { l_iddq_data = *(reinterpret_cast<iddq_entry_t*>(l_buffer_iq_inc)); - io_iddqt->ivdd_all_good_cores_off[i] = revle16(l_iddq_data); + io_iddqt->ivdd_all_good_cores_off_good_caches_on[i] = revle16(l_iddq_data); FAPI_INF("IVDDQ with all good cores OFF and caches ON, Measurement %d = %u", i, l_iddq_data); l_buffer_iq_inc += sizeof(iddq_entry_t); } @@ -825,7 +825,7 @@ proc_get_mvpd_iddq( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, for (j = 0; j < IDDQ_MEASUREMENTS; j++) { l_iddq_data = *(reinterpret_cast<iddq_entry_t*>(l_buffer_iq_inc)); - io_iddqt->ivdd_quad_good_cores_on[i][j] = revle16(l_iddq_data); + io_iddqt->ivdd_quad_good_cores_on_good_caches_on[i][j] = revle16(l_iddq_data); FAPI_INF(" IVDDQ will all good cores ON , Quad %d, Measurement %d = %u", i, j, l_iddq_data); l_buffer_iq_inc += sizeof(iddq_entry_t); } diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.H b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.H index 327c9f686..23085f532 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.H @@ -35,7 +35,11 @@ #ifndef __P9_PSTATE_PARAMETER_BLOCK_H__ #define __P9_PSTATE_PARAMETER_BLOCK_H__ -#include <p9_pstates.h> +#include <p9_pm_utils.H> +#include <p9_pstates_common.h> +#include <p9_pstates_pgpe.h> +#include <p9_pstates_cmeqm.h> +#include <p9_pstates_occ.h> // ssrivath- See if this is required #ifdef __cplusplus @@ -224,6 +228,31 @@ typedef struct } AttributeList; +/// The layout of the various Pstate Parameter Blocks (PPBs) passed a single +/// structure for data movement. +/// +/// This structure is only used for passing Pstate data from +/// p9_pstate_parameter_block to it caller for placement into HOMER for +/// consumption by into OCC, the Pstate PGPE and CME. Therefore there is no +/// alignment requirement. + +typedef struct +{ + + /// Magic Number + uint64_t magic; + + // PGPE content + GlobalPstateParmBlock globalppb; + + // CME content + LocalPstateParmBlock localppb; + + // OCC content + OCCPstateParmBlock occppb; + +} PstateSuperStructure; + // Start of function declarations // ---------------------------------------------------------------------- diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.mk b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.mk index 4c5f29fe9..bac8f0f54 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.mk +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.mk @@ -23,8 +23,11 @@ # # IBM_PROLOG_END_TAG PROCEDURE=p9_pstate_parameter_block -$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(PROJECT_ROOT)/chips/p9/procedures/hwp/pm/include/registers) -$(call ADD_MODULE_SRCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/lib) -#OBJS+=p9_pstates.o -#p9_pstate_parameter_block_PATH+=$(PROJECT_ROOT)/chips/p9/procedures/hwp/lib +PPB_INCLUDES=$(PROJECT_ROOT)/chips/p9/procedures/hwp/pm/include/registers +PPB_INCLUDES+=$(PROJECT_ROOT)/chips/p9/common/pmlib/include +PPB_INCLUDES+=$(PROJECT_ROOT)/chips/p9/procedures/hwp/lib +PPB_INCLUDES+=$(PROJECT_ROOT)/chips/p9/procedures/hwp/pm +$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(PPB_INCLUDES)) +#$(call ADD_MODULE_SRCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/lib) +lib$(PROCEDURE)_DEPLIBS+=p9_pm_utils $(call BUILD_PROCEDURE) diff --git a/src/usr/isteps/istep06/makefile b/src/usr/isteps/istep06/makefile index 07eee71fe..df25da33e 100644 --- a/src/usr/isteps/istep06/makefile +++ b/src/usr/isteps/istep06/makefile @@ -62,6 +62,9 @@ include ${ROOTPATH}/procedure.rules.mk #Include all the procedure makefiles include $(NEST_HWP_PATH)/p9_revert_sbe_mcs_setup.mk +#TODO RTC: 164237 +# Take another look at PM lib +include $(PM_HWP_PATH)/p9_pm_utils.mk include $(PM_HWP_PATH)/p9_setup_evid.mk include $(LIB_HWP_PATH)/p9_avsbus_lib.mk diff --git a/src/usr/isteps/istep08/makefile b/src/usr/isteps/istep08/makefile index 3f611c1bd..db813aadc 100644 --- a/src/usr/isteps/istep08/makefile +++ b/src/usr/isteps/istep08/makefile @@ -150,6 +150,9 @@ include ${PROCEDURES_PATH}/hwp/nest/p9_rng_init_phase1.mk # p9_setup_evid : apply voltage settings include ${PROCEDURES_PATH}/hwp/pm/p9_setup_evid.mk include ${PROCEDURES_PATH}/hwp/lib/p9_avsbus_lib.mk +# TODO RTC: 164237 +# Take another look at PM lib +include $(PROCEDURES_PATH)/hwp/pm/p9_pm_utils.mk MODULE=istep08 diff --git a/src/usr/isteps/pm/pm.mk b/src/usr/isteps/pm/pm.mk index 976d44c12..849dfdf41 100644 --- a/src/usr/isteps/pm/pm.mk +++ b/src/usr/isteps/pm/pm.mk @@ -51,6 +51,9 @@ OBJS += pm_common.o ## NOTE: add a new directory onto the vpaths when you add a new HWP VPATH += ${HWP_PATH} ${HWP_XIP_PATH} ${HWP_IMAGEPROCS_PATH} +# TODO RTC: 164237 +# Take another look at PM lib + include ${ROOTPATH}/procedure.rules.mk include ${HWP_PATH}/p9_pm_pba_bar_config.mk include ${HWP_PATH}/p9_pm_pba_init.mk |
