diff options
28 files changed, 340 insertions, 123 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc.H index 1bd25dda8..02cee02be 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc.H @@ -28,9 +28,9 @@ /// @brief Top level API for MSS ECC /// // *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _MSS_ECC_H_ @@ -521,6 +521,7 @@ inline fapi2::ReturnCode get_per_symbol_error_counts( const fapi2::Target<T>& i_ { fapi2::buffer<uint64_t> l_buffer; uint64_t l_count = 0; + o_error_counts.clear(); for (uint64_t l_index = 0; l_index < TT::NUM_MBSSYM_REGS; ++l_index) { diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.C b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.C index c4d8260f3..de58c465c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -28,9 +28,9 @@ /// @brief Traits class for the MC ECC syndrome registers /// // *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.H index c78413f96..b714aaa2d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -28,7 +28,7 @@ /// @brief Traits class for the MC ECC syndrome registers /// // *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory // *HWP Level: 2 // *HWP Consumed by: FSP:HB diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/fw_mark_store.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/fw_mark_store.H index c81c6827c..c27603b6b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/fw_mark_store.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/fw_mark_store.H @@ -28,9 +28,9 @@ /// @brief Subroutines for the MC firmware mark store registers /// // *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _MSS_FW_MARK_STORE_H_ @@ -51,12 +51,18 @@ namespace ecc namespace fwms { +/// +/// @brief chip mark type enums +/// enum mark_type { SYMBOL = 1, CHIP = 0 }; +/// +/// @brief Chip Mark Region. Used for region field values in the FWMS regs +/// enum mark_region { DISABLED = 0b000, @@ -232,8 +238,19 @@ inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, return ( read_rank7(i_target, o_data) ); default: - return fapi2::FAPI2_RC_INVALID_PARAMETER; + FAPI_ASSERT( false, + fapi2::MSS_INVALID_RANK_PASSED() + .set_RANK(i_rank) + .set_TARGET(i_target) + .set_FUNCTION(FWMS_READ), + "%s Invalid rank passed to fwms::ecc::read (%d)", + mss::c_str(i_target), + i_rank); } + + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; } /// @@ -399,8 +416,19 @@ inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, return ( write_rank7(i_target, i_data) ); default: - return fapi2::FAPI2_RC_INVALID_PARAMETER; + FAPI_ASSERT( false, + fapi2::MSS_INVALID_RANK_PASSED() + .set_RANK(i_rank) + .set_TARGET(i_target) + .set_FUNCTION(FWMS_WRITE), + "%s Invalid rank passed to fwms::ecc::write (%d)", + mss::c_str(i_target), + i_rank); } + + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; } /// diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/galois.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/galois.H index 3161b1759..981350955 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/galois.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/galois.H @@ -28,9 +28,9 @@ /// @brief Translate ECC mark Galois codes to symbol and DQ /// // *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP #ifndef _MSS_ECC_GALOIS_H_ @@ -57,14 +57,17 @@ fapi2::ReturnCode galois_to_symbol( const uint8_t i_galois, uint8_t& o_symbol ) { const auto& l_p = std::find(TT::symbol2galois, (TT::symbol2galois + MAX_DQ_BITS), i_galois); - if (l_p == (TT::symbol2galois + MAX_DQ_BITS)) - { - FAPI_ERR("galois_to_symbol: invalid Galois code: 0x%02x", i_galois); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } + FAPI_ASSERT( l_p != (TT::symbol2galois + MAX_DQ_BITS), + fapi2::MSS_INVALID_GALOIS_TO_SYMBOL() + .set_GALOIS(i_galois), + "Invalid Galois code: 0x%02x", + i_galois); o_symbol = (l_p - TT::symbol2galois); + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; } /// @@ -78,14 +81,17 @@ fapi2::ReturnCode galois_to_symbol( const uint8_t i_galois, uint8_t& o_symbol ) template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > fapi2::ReturnCode symbol_to_galois( const uint8_t i_symbol, uint8_t& o_galois ) { - if (i_symbol >= MAX_DQ_BITS) - { - FAPI_ERR("symbol_to_galois: invalid symbol: %d", i_symbol); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } + FAPI_ASSERT( i_symbol < MAX_DQ_BITS, + fapi2::MSS_INVALID_SYMBOL_FOR_GALOIS() + .set_SYMBOL(i_symbol), + "Invalid symbol: %d", + i_symbol); o_galois = TT::symbol2galois[i_symbol]; + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; } /// @@ -101,14 +107,17 @@ fapi2::ReturnCode dq_to_symbol( const uint8_t i_dq, uint8_t& o_symbol ) { const auto& l_p = std::find(TT::symbol2dq, (TT::symbol2dq + MAX_DQ_BITS), i_dq); - if (l_p == (TT::symbol2dq + MAX_DQ_BITS)) - { - FAPI_ERR("dq_to_symbol: invalid DQ index: %d", i_dq); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } + FAPI_ASSERT( l_p != (TT::symbol2dq + MAX_DQ_BITS), + fapi2::MSS_INVALID_DQ_TO_SYMBOL() + .set_DQ(i_dq), + "Invalid DQ index: %d", + i_dq); o_symbol = (l_p - TT::symbol2dq); + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; } /// @@ -122,14 +131,17 @@ fapi2::ReturnCode dq_to_symbol( const uint8_t i_dq, uint8_t& o_symbol ) template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > fapi2::ReturnCode symbol_to_dq( const uint8_t i_symbol, uint8_t& o_dq ) { - if (i_symbol >= MAX_DQ_BITS) - { - FAPI_ERR("symbol_to_dq: invalid symbol: %d", i_symbol); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } + FAPI_ASSERT( i_symbol < MAX_DQ_BITS, + fapi2::MSS_INVALID_SYMBOL_TO_DQ() + .set_SYMBOL(i_symbol), + "symbol_to_dq: invalid symbol: %d", + i_symbol); o_dq = TT::symbol2dq[i_symbol]; + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; } /// @@ -145,8 +157,8 @@ fapi2::ReturnCode galois_to_dq( const uint8_t i_galois, uint8_t& o_dq ) { uint8_t l_symbol = 0; - FAPI_TRY( galois_to_symbol<T>(i_galois, l_symbol) ); - FAPI_TRY( symbol_to_dq<T>(l_symbol, o_dq) ); + FAPI_TRY( galois_to_symbol<T>(i_galois, l_symbol), "Failed galois_to_symbol"); + FAPI_TRY( symbol_to_dq<T>(l_symbol, o_dq), "Failed symbol_to_dq" ); fapi_try_exit: return fapi2::current_err; @@ -165,8 +177,8 @@ fapi2::ReturnCode dq_to_galois( const uint8_t i_dq, uint8_t& o_galois ) { uint8_t l_symbol = 0; - FAPI_TRY( mss::ecc::dq_to_symbol<T>(i_dq, l_symbol) ); - FAPI_TRY( mss::ecc::symbol_to_galois<T>(l_symbol, o_galois) ); + FAPI_TRY( mss::ecc::dq_to_symbol<T>(i_dq, l_symbol), "Failed dq_to_symbol"); + FAPI_TRY( mss::ecc::symbol_to_galois<T>(l_symbol, o_galois) , "Failed symbol_to_galois" ); fapi_try_exit: return fapi2::current_err; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/hw_mark_store.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/hw_mark_store.H index d94b39655..7a206c5bb 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/hw_mark_store.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/hw_mark_store.H @@ -28,9 +28,9 @@ /// @brief Subroutines for the MC hardware mark store registers /// // *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _MSS_HW_MARK_STORE_H_ @@ -39,6 +39,7 @@ #include <fapi2.H> #include <lib/ecc/ecc_traits.H> #include <generic/memory/lib/utils/scom.H> +#include <lib/shared/mss_const.H> namespace mss { @@ -212,8 +213,19 @@ inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, return ( read_rank7(i_target, o_data) ); default: - return fapi2::FAPI2_RC_INVALID_PARAMETER; + FAPI_ASSERT( false, + fapi2::MSS_INVALID_RANK_PASSED() + .set_RANK(i_rank) + .set_TARGET(i_target) + .set_FUNCTION(HWMS_READ), + "%s Invalid rank passed to fwms::ecc::hwms::read (%d)", + mss::c_str(i_target), + i_rank); } + + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; } /// @@ -379,8 +391,19 @@ inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, return ( write_rank7(i_target, i_data) ); default: - return fapi2::FAPI2_RC_INVALID_PARAMETER; + FAPI_ASSERT( false, + fapi2::MSS_INVALID_RANK_PASSED() + .set_RANK(i_rank) + .set_TARGET(i_target) + .set_FUNCTION(HWMS_WRITE), + "%s Invalid rank passed to fwms::ecc::hwms::write(%d)", + mss::c_str(i_target), + i_rank); } + + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; } /// diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_aue_trap.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_aue_trap.H index ca0adda6f..c6d4a239a 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_aue_trap.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_aue_trap.H @@ -28,9 +28,9 @@ /// @brief Subroutines for the MC mainline aue address trap registers (MBAUER*Q) /// // *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _MSS_MAINLINE_AUE_TRAP_H_ @@ -66,7 +66,7 @@ inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, fapi2::buffer<u const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); FAPI_TRY( mss::getScom(l_mcbist_target, (TT::MAINLINE_AUE_REGS[l_port]), o_data) ); - FAPI_INF("read: 0x%016lx", o_data); + FAPI_INF("%s read: 0x%016lx", mss::c_str(i_target), o_data); fapi_try_exit: return fapi2::current_err; } @@ -86,7 +86,7 @@ inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, const fapi2::b const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); FAPI_TRY( mss::putScom(l_mcbist_target, (TT::MAINLINE_AUE_REGS[l_port]), i_data) ); - FAPI_INF("write: 0x%016lx", i_data); + FAPI_INF("%s write: 0x%016lx", mss::c_str(i_target), i_data); fapi_try_exit: return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_mpe_trap.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_mpe_trap.H index 5c6e3dcde..a8ea60c98 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_mpe_trap.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_mpe_trap.H @@ -28,9 +28,9 @@ /// @brief Subroutines for the MC mainline mpe address trap registers (MBNCER*Q) /// // *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _MSS_MAINLINE_MPE_TRAP_H_ @@ -66,7 +66,7 @@ inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, fapi2::buffer<u const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); FAPI_TRY( mss::getScom(l_mcbist_target, (TT::MAINLINE_MPE_REGS[l_port]), o_data) ); - FAPI_INF("read: 0x%016lx", o_data); + FAPI_INF("%s read: 0x%016lx", mss::c_str(i_target), o_data); fapi_try_exit: return fapi2::current_err; } @@ -86,7 +86,7 @@ inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, const fapi2::b const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); FAPI_TRY( mss::putScom(l_mcbist_target, (TT::MAINLINE_MPE_REGS[l_port]), i_data) ); - FAPI_INF("write: 0x%016lx", i_data); + FAPI_INF("%s write: 0x%016lx", mss::c_str(i_target), i_data); fapi_try_exit: return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_nce_trap.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_nce_trap.H index 278ac84ff..bfded0433 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_nce_trap.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_nce_trap.H @@ -28,9 +28,9 @@ /// @brief Subroutines for the MC mainline nce address trap registers (MBNCER*Q) /// // *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _MSS_MAINLINE_NCE_TRAP_H_ @@ -66,7 +66,7 @@ inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, fapi2::buffer<u const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); FAPI_TRY( mss::getScom(l_mcbist_target, (TT::MAINLINE_NCE_REGS[l_port]), o_data) ); - FAPI_INF("read: 0x%016lx", o_data); + FAPI_INF("%s read: 0x%016lx", mss::c_str(i_target), o_data); fapi_try_exit: return fapi2::current_err; } @@ -86,7 +86,7 @@ inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, const fapi2::b const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); FAPI_TRY( mss::putScom(l_mcbist_target, (TT::MAINLINE_NCE_REGS[l_port]), i_data) ); - FAPI_INF("write: 0x%016lx", i_data); + FAPI_INF("%s write: 0x%016lx", mss::c_str(i_target), i_data); fapi_try_exit: return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_rce_trap.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_rce_trap.H index 272d98e4a..fbb100ed0 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_rce_trap.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_rce_trap.H @@ -28,7 +28,7 @@ /// @brief Subroutines for the MC mainline rce address trap registers (MBRCER*Q) /// // *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory // *HWP Level: 2 // *HWP Consumed by: FSP:HB diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_ue_trap.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_ue_trap.H index bdfc24442..885e37596 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_ue_trap.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_ue_trap.H @@ -28,7 +28,7 @@ /// @brief Subroutines for the MC mainline ue address trap registers (MBUER*Q) /// // *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory // *HWP Level: 2 // *HWP Consumed by: FSP:HB diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/maint_current_trap.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/maint_current_trap.H index f18ec6496..61e57869f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/maint_current_trap.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/maint_current_trap.H @@ -28,7 +28,7 @@ /// @brief Subroutines for the MC maint current address trap register (MCBMCATQ) /// // *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory // *HWP Level: 2 // *HWP Consumed by: FSP:HB diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mark_shadow_reg.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mark_shadow_reg.H index 229df0098..6f413559b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mark_shadow_reg.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mark_shadow_reg.H @@ -28,9 +28,9 @@ /// @brief Subroutines for the MC mark shadow registers (MSR) /// // *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _MSS_MARK_SHADOW_REG_H_ @@ -62,7 +62,7 @@ template< fapi2::TargetType T, typename TT = eccTraits<T> > inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) { FAPI_TRY( mss::getScom(i_target, TT::MARK_SHADOW_REG, o_data) ); - FAPI_INF("read: 0x%016lx", o_data); + FAPI_INF("%s read: 0x%016lx", mss::c_str(i_target), o_data); fapi_try_exit: return fapi2::current_err; } @@ -79,7 +79,7 @@ template< fapi2::TargetType T, typename TT = eccTraits<T> > inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) { FAPI_TRY( mss::putScom(i_target, TT::MARK_SHADOW_REG, i_data) ); - FAPI_INF("write: 0x%016lx", i_data); + FAPI_INF("%s write: 0x%016lx", mss::c_str(i_target), i_data); fapi_try_exit: return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mbs_error_vector_trap.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mbs_error_vector_trap.H index c9778e3ec..4ed773988 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mbs_error_vector_trap.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mbs_error_vector_trap.H @@ -28,9 +28,9 @@ /// @brief Subroutines for the MC MBS error vector trap registers (MBSEVR*Q) /// // *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _MSS_MBS_ERROR_VECTOR_TRAP_H_ @@ -65,7 +65,7 @@ inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, fapi2::buffer<u const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); FAPI_TRY( mss::getScom(l_mcbist_target, (TT::ERROR_VECTOR_REGS[l_port]), o_data) ); - FAPI_INF("read: 0x%016lx", o_data); + FAPI_INF("%s read: 0x%016lx", mss::c_str(i_target), o_data); fapi_try_exit: return fapi2::current_err; } @@ -85,7 +85,7 @@ inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, const fapi2::b const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); FAPI_TRY( mss::putScom(l_mcbist_target, (TT::ERROR_VECTOR_REGS[l_port]), i_data) ); - FAPI_INF("write: 0x%016lx", i_data); + FAPI_INF("%s write: 0x%016lx", mss::c_str(i_target), i_data); fapi_try_exit: return fapi2::current_err; } @@ -115,7 +115,7 @@ inline void set_nce_galois( const fapi2::Target<T>& i_target, io_data.insertFromRight<TT::P1_NCE_GALOIS, TT::P1_NCE_GALOIS_LEN>(i_value); } - FAPI_INF("set_nce_galois: 0x%016lx", i_value); + FAPI_INF("%s set_nce_galois: 0x%016lx", mss::c_str(i_target), i_value); } /// @@ -143,7 +143,7 @@ inline void get_nce_galois( const fapi2::Target<T>& i_target, i_data.extractToRight<TT::P1_NCE_GALOIS, TT::P1_NCE_GALOIS_LEN>(o_value); } - FAPI_INF("get_nce_galois: 0x%016lx", o_value); + FAPI_INF("%s get_nce_galois: 0x%016lx", mss::c_str(i_target), o_value); } /// @@ -171,7 +171,7 @@ inline void set_nce_magnitude( const fapi2::Target<T>& i_target, io_data.insertFromRight<TT::P1_NCE_MAGNITUDE, TT::P1_NCE_MAGNITUDE_LEN>(i_value); } - FAPI_INF("set_nce_magnitude: 0x%016lx", i_value); + FAPI_INF("%s set_nce_magnitude: 0x%016lx", mss::c_str(i_target), i_value); } /// @@ -199,7 +199,7 @@ inline void get_nce_magnitude( const fapi2::Target<T>& i_target, i_data.extractToRight<TT::P1_NCE_MAGNITUDE, TT::P1_NCE_MAGNITUDE_LEN>(o_value); } - FAPI_INF("get_nce_magnitude: 0x%016lx", o_value); + FAPI_INF("%s get_nce_magnitude: 0x%016lx", mss::c_str(i_target), o_value); } /// @@ -227,7 +227,7 @@ inline void set_tce_galois( const fapi2::Target<T>& i_target, io_data.insertFromRight<TT::P1_TCE_GALOIS, TT::P1_TCE_GALOIS_LEN>(i_value); } - FAPI_INF("set_tce_galois: 0x%016lx", i_value); + FAPI_INF("%s set_tce_galois: 0x%016lx", mss::c_str(i_target), i_value); } /// @@ -255,7 +255,7 @@ inline void get_tce_galois( const fapi2::Target<T>& i_target, i_data.extractToRight<TT::P1_TCE_GALOIS, TT::P1_TCE_GALOIS_LEN>(o_value); } - FAPI_INF("get_tce_galois: 0x%016lx", o_value); + FAPI_INF("%s get_tce_galois: 0x%016lx", mss::c_str(i_target), o_value); } /// @@ -283,7 +283,7 @@ inline void set_tce_magnitude( const fapi2::Target<T>& i_target, io_data.insertFromRight<TT::P1_TCE_MAGNITUDE, TT::P1_TCE_MAGNITUDE_LEN>(i_value); } - FAPI_INF("set_tce_magnitude: 0x%016lx", i_value); + FAPI_INF("%s set_tce_magnitude: 0x%016lx", mss::c_str(i_target), i_value); } /// @@ -311,7 +311,7 @@ inline void get_tce_magnitude( const fapi2::Target<T>& i_target, i_data.extractToRight<TT::P1_TCE_MAGNITUDE, TT::P1_TCE_MAGNITUDE_LEN>(o_value); } - FAPI_INF("get_tce_magnitude: 0x%016lx", o_value); + FAPI_INF("%s get_tce_magnitude: 0x%016lx", mss::c_str(i_target), o_value); } } // close namespace mbs_error_vector_trap diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/modal_symbol_count.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/modal_symbol_count.H index ead000d53..f19185fee 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/modal_symbol_count.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/modal_symbol_count.H @@ -28,9 +28,9 @@ /// @brief Subroutines for the MC modal symbol count (MBSSYMEC*Q) registers /// // *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _MSS_MODAL_SYMBOL_COUNT_H_ @@ -39,6 +39,7 @@ #include <fapi2.H> #include <lib/ecc/ecc_traits.H> #include <generic/memory/lib/utils/scom.H> +#include <lib/shared/mss_const.H> namespace mss { @@ -228,8 +229,18 @@ inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, return ( read_index8(i_target, o_data) ); default: - return fapi2::FAPI2_RC_INVALID_PARAMETER; + FAPI_ASSERT( false, + fapi2::MSS_INVALID_INDEX_PASSED() + .set_INDEX(i_index) + .set_FUNCTION(SYMBOL_COUNT_READ), + "%s Invalid index passed to fwms::ecc::modal_symbol_count::read (%d)", + mss::c_str(i_target), + i_index); } + + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; } /// @@ -411,8 +422,18 @@ inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, return ( write_index8(i_target, i_data) ); default: - return fapi2::FAPI2_RC_INVALID_PARAMETER; + FAPI_ASSERT( false, + fapi2::MSS_INVALID_INDEX_PASSED() + .set_INDEX(i_index) + .set_FUNCTION(SYMBOL_COUNT_WRITE), + "%s Invalid index passed to fwms::ecc::modal_symbol_count::write (%d)", + mss::c_str(i_target), + i_index); } + + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; } /// @@ -431,6 +452,8 @@ inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > inline void set_count( fapi2::buffer<uint64_t>& io_data, const uint64_t i_index, const uint64_t i_value ) { + static_assert ( TT::MODAL_SYMBOL_COUNTERS_PER_REG <= 8, + "mss::ecc_count::modal_symbol_count: Modal symbol count field index failed range check" ); const uint64_t l_field = i_index % TT::MODAL_SYMBOL_COUNTERS_PER_REG; switch (l_field) @@ -468,7 +491,7 @@ inline void set_count( fapi2::buffer<uint64_t>& io_data, const uint64_t i_index, break; default: - // shouldn't happen due to modulo above, but here just in case + // Shouldn't happen due to modulo above, but here just in case - JLH FAPI_ERR("Modal symbol count field index failed range check"); fapi2::Assert(false); break; @@ -494,6 +517,8 @@ template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTrai inline void get_count( const fapi2::buffer<uint64_t>& i_data, const uint64_t i_index, uint64_t& o_value ) { const uint64_t l_field = i_index % TT::MODAL_SYMBOL_COUNTERS_PER_REG; + static_assert ( TT::MODAL_SYMBOL_COUNTERS_PER_REG <= 8, + "mss::ecc_count::get_count: Modal symbol count field index failed range check" ); switch (l_field) { diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/read_error_count_regs.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/read_error_count_regs.H index 54f9d6170..834f01b19 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/read_error_count_regs.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/read_error_count_regs.H @@ -28,9 +28,9 @@ /// @brief Subroutines for the MBS Memory Scrub/Read Error Count registers (MBSEC*Q) /// // *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _MSS_READ_ERROR_COUNT_REGS_H_ @@ -63,7 +63,7 @@ template< fapi2::TargetType T, typename TT = eccTraits<T> > inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) { FAPI_TRY( mss::getScom(i_target, TT::READ_ERROR_COUNT_REG0, o_data) ); - FAPI_INF("read: 0x%016lx", o_data); + FAPI_INF("%s read: 0x%016lx", mss::c_str(i_target), o_data); fapi_try_exit: return fapi2::current_err; } @@ -80,7 +80,7 @@ template< fapi2::TargetType T, typename TT = eccTraits<T> > inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) { FAPI_TRY( mss::putScom(i_target, TT::READ_ERROR_COUNT_REG0, i_data) ); - FAPI_INF("write: 0x%016lx", i_data); + FAPI_INF("%s write: 0x%016lx", mss::c_str(i_target), i_data); fapi_try_exit: return fapi2::current_err; } @@ -272,7 +272,7 @@ template< fapi2::TargetType T, typename TT = eccTraits<T> > inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) { FAPI_TRY( mss::getScom(i_target, TT::READ_ERROR_COUNT_REG1, o_data) ); - FAPI_INF("read: 0x%016lx", o_data); + FAPI_INF("%s read: 0x%016lx", mss::c_str(i_target), o_data); fapi_try_exit: return fapi2::current_err; } @@ -289,7 +289,7 @@ template< fapi2::TargetType T, typename TT = eccTraits<T> > inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) { FAPI_TRY( mss::putScom(i_target, TT::READ_ERROR_COUNT_REG1, i_data) ); - FAPI_INF("write: 0x%016lx", i_data); + FAPI_INF("%s write: 0x%016lx", mss::c_str(i_target), i_data); fapi_try_exit: return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/address.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/address.H index 1272ed4d2..15b63fd6a 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/address.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/address.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,7 +27,7 @@ /// @file address.H /// @brief Class for mcbist related addresses (addresses below the hash translation) /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 2 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.C b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.C index 43094f293..8a0f3a7c3 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.C @@ -27,7 +27,7 @@ /// @file mcbist.C /// @brief Run and manage the MCBIST engine /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 2 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H index 4ae7f94a8..d3399197c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H @@ -30,7 +30,7 @@ // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> // *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP #ifndef _MSS_MCBIST_H_ @@ -1023,7 +1023,6 @@ inline subtest_t<T> init_subtest() /// - ENABLE_SPEC_ATTN - disabled /// - ENABLE_HOST_ATTN - enabled /// - template< fapi2::TargetType T, typename TT = mcbistTraits<T> > class program { @@ -1067,6 +1066,7 @@ class program } + /// /// @brief Change the DIMM select in the address mapping /// @param[in] i_bitmap DIMM select bit map in the address counter /// @note Assumes data is right-aligned @@ -1077,6 +1077,7 @@ class program return; } + /// /// @brief Change the MRANK0 address mapping when not in 5D mode /// @param[in] i_bitmap MRANK0 bit map in the address counter /// @note Assumes data is right-aligned @@ -1087,6 +1088,7 @@ class program return; } + /// /// @brief Change the MRANK0 address mapping when in 5D mode /// @param[in] i_bitmap MRANK0 bit map in the address counter /// @note Assumes data is right-aligned @@ -1097,6 +1099,7 @@ class program return; } + /// /// @brief Change the MRANK1 address mapping when not in 5D mode /// @param[in] i_bitmap MRANK1 bit map in the address counter /// @note Assumes data is right-aligned @@ -1107,6 +1110,7 @@ class program return; } + /// /// @brief Change the MRANK1 address mapping when in 5D mode /// @param[in] i_bitmap MRANK1 bit map in the address counter /// @note Assumes data is right-aligned @@ -1117,6 +1121,7 @@ class program return; } + /// /// @brief Change the MRANK2 address mapping when in 5D mode /// @param[in] i_bitmap MRANK2 bit map in the address counter /// @note Assumes data is right-aligned @@ -1127,6 +1132,7 @@ class program return; } + /// /// @brief Change the SRANK0 address mapping when in 5D mode /// @param[in] i_bitmap SRANK0 bit map in the address counter /// @note Assumes data is right-aligned @@ -1137,6 +1143,7 @@ class program return; } + /// /// @brief Change the SRANK1 address mapping /// @param[in] i_bitmap SRANK1 bit map in the address counter /// @note Assumes data is right-aligned @@ -1147,6 +1154,7 @@ class program return; } + /// /// @brief Change the SRANK2 address mapping /// @param[in] i_bitmap SRANK2 bit map in the address counter /// @note Assumes data is right-aligned @@ -1157,6 +1165,7 @@ class program return; } + /// /// @brief Change the BANK2 address mapping /// @param[in] i_bitmap BANK2 bit map in the address counter /// @note Assumes data is right-aligned @@ -1167,6 +1176,7 @@ class program return; } + /// /// @brief Change the BANK1 address mapping /// @param[in] i_bitmap BANK1 bit map in the address counter /// @note Assumes data is right-aligned @@ -1177,6 +1187,7 @@ class program return; } + /// /// @brief Change the BANK0 address mapping /// @param[in] i_bitmap BANK0 bit map in the address counter /// @note Assumes data is right-aligned @@ -1187,6 +1198,7 @@ class program return; } + /// /// @brief Change the BANK_GROUP1 address mapping /// @param[in] i_bitmap BANK_GROUP1 bit map in the address counter /// @note Assumes data is right-aligned @@ -1197,6 +1209,7 @@ class program return; } + /// /// @brief Change the BANK_GROUP0 address mapping /// @param[in] i_bitmap BANK_GROUP0 bit map in the address counter /// @note Assumes data is right-aligned @@ -1207,6 +1220,7 @@ class program return; } + /// /// @brief Change the ROW17 address mapping /// @param[in] i_bitmap ROW17 bit map in the address counter /// @note Assumes data is right-aligned @@ -1217,6 +1231,7 @@ class program return; } + /// /// @brief Change the ROW16 address mapping /// @param[in] i_bitmap ROW16 bit map in the address counter /// @note Assumes data is right-aligned @@ -1227,6 +1242,7 @@ class program return; } + /// /// @brief Change the ROW15 address mapping /// @param[in] i_bitmap ROW15 bit map in the address counter /// @note Assumes data is right-aligned @@ -1237,6 +1253,7 @@ class program return; } + /// /// @brief Change the ROW14 address mapping /// @param[in] i_bitmap ROW14 bit map in the address counter /// @note Assumes data is right-aligned @@ -1247,6 +1264,7 @@ class program return; } + /// /// @brief Change the ROW13 address mapping /// @param[in] i_bitmap ROW13 bit map in the address counter /// @note Assumes data is right-aligned @@ -1258,17 +1276,19 @@ class program return; } - ///CFG_AMAP_ROW12 = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12 , + /// /// @brief Change the ROW12 address mapping /// @param[in] i_bitmap ROW12 bit map in the address counter /// @note Assumes data is right-aligned /// inline void change_row12_bit( const uint64_t i_bitmap ) { + // CFG_AMAP_ROW12 = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12 , iv_addr_map1.insertFromRight<TT::CFG_AMAP_ROW12, TT::CFG_AMAP_ROW12_LEN>(i_bitmap); return; } + /// /// @brief Change the ROW11 address mapping /// @param[in] i_bitmap ROW11 bit map in the address counter /// @note Assumes data is right-aligned @@ -1279,6 +1299,7 @@ class program return; } + /// /// @brief Change the ROW10 address mapping /// @param[in] i_bitmap ROW10 bit map in the address counter /// @note Assumes data is right-aligned @@ -1289,6 +1310,7 @@ class program return; } + /// /// @brief Change the ROW9 address mapping /// @param[in] i_bitmap ROW9 bit map in the address counter /// @note Assumes data is right-aligned @@ -1299,6 +1321,7 @@ class program return; } + /// /// @brief Change the ROW8 address mapping /// @param[in] i_bitmap ROW8 bit map in the address counter /// @note Assumes data is right-aligned @@ -1309,6 +1332,7 @@ class program return; } + /// /// @brief Change the ROW7 address mapping /// @param[in] i_bitmap ROW7 bit map in the address counter /// @note Assumes data is right-aligned @@ -1319,6 +1343,7 @@ class program return; } + /// /// @brief Change the ROW6 address mapping /// @param[in] i_bitmap ROW6 bit map in the address counter /// @note Assumes data is right-aligned @@ -1329,6 +1354,7 @@ class program return; } + /// /// @brief Change the ROW5 address mapping /// @param[in] i_bitmap ROW5 bit map in the address counter /// @note Assumes data is right-aligned @@ -1339,6 +1365,7 @@ class program return; } + /// /// @brief Change the ROW4 address mapping /// @param[in] i_bitmap ROW4 bit map in the address counter /// @note Assumes data is right-aligned @@ -1349,6 +1376,7 @@ class program return; } + /// /// @brief Change the ROW3 address mapping /// @param[in] i_bitmap ROW3 bit map in the address counter /// @note Assumes data is right-aligned @@ -1359,6 +1387,7 @@ class program return; } + /// /// @brief Change the ROW2 address mapping /// @param[in] i_bitmap ROW2 bit map in the address counter /// @note Assumes data is right-aligned @@ -1369,6 +1398,7 @@ class program return; } + /// /// @brief Change the ROW1 address mapping /// @param[in] i_bitmap ROW1 bit map in the address counter /// @note Assumes data is right-aligned @@ -1379,6 +1409,7 @@ class program return; } + /// /// @brief Change the ROW0 address mapping /// @param[in] i_bitmap ROW0 bit map in the address counter /// @note Assumes data is right-aligned @@ -1389,6 +1420,7 @@ class program return; } + /// /// @brief Change the COL9 address mapping /// @param[in] i_bitmap COL9 bit map in the address counter /// @note Assumes data is right-aligned @@ -1399,6 +1431,7 @@ class program return; } + /// /// @brief Change the COL8 address mapping /// @param[in] i_bitmap COL8 bit map in the address counter /// @note Assumes data is right-aligned @@ -1409,6 +1442,7 @@ class program return; } + /// /// @brief Change the COL7 address mapping /// @param[in] i_bitmap COL7 bit map in the address counter /// @note Assumes data is right-aligned @@ -1419,6 +1453,7 @@ class program return; } + /// /// @brief Change the COL6 address mapping /// @param[in] i_bitmap COL6 bit map in the address counter /// @note Assumes data is right-aligned @@ -2067,14 +2102,16 @@ class program { iv_control.insertFromRight<TT::PORT_SEL, TT::PORT_SEL_LEN>(i_ports); FAPI_INF("mcbist select ports: iv_control 0x%016lx (ports: 0x%x)", iv_control, i_ports); - return; } /// /// @brief Process mcbist errors - /// @param[in] i_target fapi2::Target<T> of the MCBIST + /// @tparam MCBIST target type + /// @tparam T fapi2::TargetType representing the fapi2 target which + /// contains the MCBIST engine (e.g., fapi2::TARGET_TYPE_MCBIST) /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok + /// This shouldn't be called in firmware? Check with PRD /// inline fapi2::ReturnCode process_errors( const fapi2::Target<T> i_target ) const { @@ -2084,7 +2121,7 @@ class program fapi2::buffer<uint64_t> l_data; uint64_t l_port = 0; uint64_t l_subtest = 0; - FAPI_TRY( mss::getScom(i_target, TT::MCBSTATQ_REG, l_data) ); + FAPI_TRY( mss::getScom(i_target, TT::MCBSTATQ_REG, l_data), "%s Failed getScom", mss::c_str(i_target) ); l_data.extractToRight<TT::LOGGED_ERROR_ON_PORT_INDICATOR, TT::LOGGED_ERROR_ON_PORT_INDICATOR_LEN>(l_port); l_data.extractToRight<TT::SUBTEST_NUM_INDICATOR, TT::SUBTEST_NUM_INDICATOR_LEN>(l_subtest); @@ -2093,7 +2130,7 @@ class program .set_TARGET(i_target) .set_PORT(mss::first_bit_set(l_port)) .set_SUBTEST(l_subtest), - "MCBIST error on port %d subtest %d", mss::first_bit_set(l_port), l_subtest ); + "%s MCBIST error on port %d subtest %d", mss::c_str(i_target), mss::first_bit_set(l_port), l_subtest ); } // Check for UE errors @@ -2101,18 +2138,18 @@ class program fapi2::buffer<uint64_t> l_read0; fapi2::buffer<uint64_t> l_read1; - FAPI_TRY( mss::getScom(i_target, TT::SRERR0_REG, l_read0) ); - FAPI_TRY( mss::getScom(i_target, TT::SRERR1_REG, l_read1) ); + FAPI_TRY( mss::getScom(i_target, TT::SRERR0_REG, l_read0), "%s Failed getScom", mss::c_str(i_target) ); + FAPI_TRY( mss::getScom(i_target, TT::SRERR1_REG, l_read1), "%s Failed getScom", mss::c_str(i_target) ); FAPI_ASSERT( ((l_read0 == 0) && (l_read1 == 0)), fapi2::MSS_MEMDIAGS_ERROR_IN_LAST_PATTERN() .set_TARGET(i_target) .set_STATUS0(l_read0) .set_STATUS1(l_read1), - "MCBIST scrub/read error reg0: 0x%016lx reg1: 0x%016lx", l_read0, l_read1 ); + "%s MCBIST scrub/read error reg0: 0x%016lx reg1: 0x%016lx", mss::c_str(i_target), l_read0, l_read1 ); } - FAPI_INF("Execution success - no errors seen from MCBIST program"); + FAPI_INF("%s Execution success - no errors seen from MCBIST program", mss::c_str(i_target)); fapi_try_exit: return fapi2::current_err; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.C b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.C index 508f98901..3a25dd8c9 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.C @@ -27,10 +27,10 @@ /// @file memdiags.C /// @brief Run and manage the MEMDIAGS engine /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.H index c6d609f02..9ce8ad0aa 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.H @@ -27,7 +27,7 @@ /// @file memdiags.H /// @brief API for memory diagnostics /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/patterns.C b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/patterns.C index bb2f60823..b77698190 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/patterns.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/patterns.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,7 +27,7 @@ /// @file patterns.C /// @brief Static definition of MCBIST patterns /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com> // *HWP Team: Memory // *HWP Level: 2 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/patterns.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/patterns.H index af083012f..b5faeeffd 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/patterns.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/patterns.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,10 +27,10 @@ /// @file patterns.H /// @brief Static definition of MCBIST patterns /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _MSS_MCBIST_PATTERNS_ @@ -84,7 +84,7 @@ constexpr uint64_t NO_RANDOM24_SEED_MAP = LAST_RANDOM24_SEED_MAP + 1; constexpr uint64_t RANDOM24_SEED_MAP_FIELD_LEN = 4; -/// Vector of cache lines, seaprated in to two 64B chunks +/// Vector of cache lines, separated in to two 64B chunks typedef std::pair<uint64_t, uint64_t> cache_line; typedef std::vector< cache_line > pattern; extern const std::vector< pattern > patterns; @@ -97,9 +97,8 @@ extern const std::vector< random24_data_seed > random24_data_seeds; typedef std::vector< uint64_t > random24_seed_map; extern const std::vector< random24_seed_map > random24_seed_maps; +}// mcbist -} - -} +}// mss #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/settings.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/settings.H index f2f5496c7..6c9d66ea9 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/settings.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/settings.H @@ -27,7 +27,7 @@ /// @file settings.H /// @brief MCBIST settings, like stop conditions, thresholds, etc /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com> // *HWP Team: Memory // *HWP Level: 2 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.C b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.C index cd92114f3..9db0721ea 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,7 +27,7 @@ /// @file mcbist/sim.C /// @brief MCBIST/memdiags functions for when we're in simulation mode /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 2 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.H index ba58929cb..a6b5b9400 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,7 +27,7 @@ /// @file mcbist/sim.H /// @brief MCBIST/memdiags functions for when we're in simulation mode /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 2 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H index a225fb1ec..6543a8ae1 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H @@ -128,6 +128,24 @@ enum times FULL_DLL_CAL_DELAY = 37382, ///< Full DLL calibration (in ddphy_nck cycles) }; +/// +/// @brief ID codes so we can lookup which function triggered the ffdc fail +/// +enum ffdc_function_codes +{ + // Used in fw_mark_store.H for MSS_INVALID_RANK_PASSED + FWMS_READ = 30, + FWMS_WRITE = 31, + + // Used in hw_mark_store.H for MSS_INVALID_RANK_PASSED + HWMS_READ = 40, + HWMS_WRITE = 41, + + // MSS_INVALID_INDEX_PASSED + SYMBOL_COUNT_READ = 50, + SYMBOL_COUNT_WRITE = 51, +}; + enum states { LOW = 0, diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_memdiags.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_memdiags.xml index 80a6b90ee..539759838 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_memdiags.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_memdiags.xml @@ -118,6 +118,83 @@ <rc>RC_MSS_MEMDIAGS_INVALID_PATTERN_INDEX</rc> <description>An invalid pattern index was passed to the pattern loader</description> <ffdc>INDEX</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_MSS_MEMDIAGS_ERROR_CHANGING_RANDOM_SEED</rc> + <description>Attempting to change to a 24b random data seed which does not exist</description> + <ffdc>RANDOM_SEED</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_MSS_INVALID_GALOIS_TO_SYMBOL</rc> + <description> An invalid galois code was found</description> + <ffdc>GALOIS</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_MSS_INVALID_SYMBOL_FOR_GALOIS</rc> + <description> An invalid symbol was passed to symbol_to_galois</description> + <ffdc>SYMBOL</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_MSS_INVALID_DQ_TO_SYMBOL</rc> + <description> An invalid DQ bit index received to map to Galois symbol</description> + <ffdc>DQ</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_MSS_INVALID_SYMBOL_TO_DQ</rc> + <description> An invalid symbol received to map to DQ bit index</description> + <ffdc>SYMBOL</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_MSS_INVALID_RANK_PASSED</rc> + <description> An invalid rank was passed to ecc::read function</description> + <ffdc>RANK</ffdc> + <ffdc>FUNCTION</ffdc> + <ffdc>TARGET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_MSS_INVALID_INDEX_PASSED</rc> + <description> An invalid index was passed to MODAL_SYMBOL_COUNT function</description> + <ffdc>INDEX</ffdc> + <ffdc>FUNCTION</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <hwpError> @@ -130,7 +207,7 @@ <targetType>TARGET_TYPE_MCBIST</targetType> </collectRegisterFfdc> <callout> - <target>TARGET</target> + <procedure>CODE</procedure> <priority>HIGH</priority> </callout> </hwpError> @@ -170,13 +247,14 @@ <description>The port used in an MCBIST program is not functional</description> <ffdc>RELATIVE_PORT_POSITION</ffdc> <ffdc>ADDRESS</ffdc> + <ffdc>TARGET</ffdc> <collectRegisterFfdc> <id>REG_FFDC_MSS_MEMDIAGS_FAILURE</id> <target>TARGET</target> <targetType>TARGET_TYPE_MCBIST</targetType> </collectRegisterFfdc> <callout> - <target>TARGET</target> + <procedure>CODE</procedure> <priority>HIGH</priority> </callout> </hwpError> @@ -184,7 +262,6 @@ <hwpError> <rc>RC_MSS_MEMDIAGS_SUPERFAST_READ_FAILED_TO_INIT</rc> <description>A superfast read operation failed initialization</description> - <ffdc>TARGET</ffdc> <collectRegisterFfdc> <id>REG_FFDC_MSS_MEMDIAGS_FAILURE</id> <target>TARGET</target> @@ -199,7 +276,6 @@ <hwpError> <rc>RC_MSS_MEMDIAGS_SUPERFAST_INIT_FAILED_TO_INIT</rc> <description>A superfast init operation failed initialization</description> - <ffdc>TARGET</ffdc> <collectRegisterFfdc> <id>REG_FFDC_MSS_MEMDIAGS_FAILURE</id> <target>TARGET</target> @@ -214,7 +290,6 @@ <hwpError> <rc>RC_MSS_MEMDIAGS_CONTINUOUS_SCRUB_FAILED_TO_INIT</rc> <description>A continuous scrub operation failed initialization</description> - <ffdc>TARGET</ffdc> <collectRegisterFfdc> <id>REG_FFDC_MSS_MEMDIAGS_FAILURE</id> <target>TARGET</target> @@ -229,7 +304,6 @@ <hwpError> <rc>RC_MSS_MEMDIAGS_TARGETED_SCRUB_FAILED_TO_INIT</rc> <description>A continuous scrub operation failed initialization</description> - <ffdc>TARGET</ffdc> <collectRegisterFfdc> <id>REG_FFDC_MSS_MEMDIAGS_FAILURE</id> <target>TARGET</target> @@ -252,7 +326,7 @@ <targetType>TARGET_TYPE_MCBIST</targetType> </collectRegisterFfdc> <callout> - <target>TARGET</target> + <procedure>CODE</procedure> <priority>HIGH</priority> </callout> </hwpError> @@ -262,7 +336,7 @@ <description>Attempt to run an MCBIST program with no subtests</description> <ffdc>TARGET</ffdc> <callout> - <target>TARGET</target> + <procedure>CODE</procedure> <priority>HIGH</priority> </callout> </hwpError> @@ -293,7 +367,7 @@ <targetType>TARGET_TYPE_MCA</targetType> </collectRegisterFfdc> <callout> - <target>TARGET</target> + <procedure>CODE</procedure> <priority>HIGH</priority> </callout> </hwpError> |
