diff options
18 files changed, 959 insertions, 1326 deletions
diff --git a/src/include/sys/misc.h b/src/include/sys/misc.h index 74f5ac46a..12fb89fa4 100644 --- a/src/include/sys/misc.h +++ b/src/include/sys/misc.h @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2015 */ +/* Contributors Listed Below - COPYRIGHT 2011,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -44,6 +44,14 @@ enum p8SystemConsts }; +enum p9SystemConsts +{ + /// max possible processors in a P9 system + P9_MAX_PROCS = 8, + /// max EC (cores available in a processor ) + P9_MAX_EC_PER_PROC = 16, + +}; /** * @enum ShutdownStatus @@ -71,18 +79,22 @@ enum WinkleScope WINKLE_SCOPE_ALL = 0x1, }; + + +//TODO RTC:147693 +//Need to determine what HOMER layout offsets should be /** * HOMER layout offsets * see: HOMER_Image_Layout.odt */ /** OCC image is at the start of the HOMER layout */ -#define HOMER_OFFSET_TO_OCC_IMG 0 +#define HOMER_OFFSET_TO_OCC_IMG (1*MEGABYTE) /** Offset from HOMER to OCC Host Data Area */ #define HOMER_OFFSET_TO_OCC_HOST_DATA (MEGABYTE) /** SLW image is 2MB into the HOMER layout */ -#define HOMER_SLW_IMG_OFFSET (2*MEGABYTE) -/** SLW Image Max ouput size */ -#define HOMER_MAX_SLW_IMG_SIZE_IN_MB 1 +#define HOMER_HCODE_IMG_OFFSET (2*MEGABYTE) +/** STOP Image Max ouput size */ +#define HOMER_MAX_HCODE_IMG_SIZE_IN_MB 1 #ifdef __cplusplus diff --git a/src/include/usr/isteps/istep15list.H b/src/include/usr/isteps/istep15list.H index 1dbf97c11..5a7386b45 100644 --- a/src/include/usr/isteps/istep15list.H +++ b/src/include/usr/isteps/istep15list.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ +/* Contributors Listed Below - COPYRIGHT 2012,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -28,11 +28,17 @@ /** * @file istep15list.H * - * IStep 15 Build Winkle Images - * IPL FLow Doc v0.67 (11/11/15) + * IStep 15 Build Hcode Images + * IPL FLow Doc v0.84 (11/11/15) * - * 15.1 host_build_winkle - * : Build runtime winkle images + * 15.1 host_build_stop_image + * : Build runtime stop images + * 15.2 proc_set_pba_homer_bar + * : Set HOMER location in OCC + * 15.3 host_establish_ex_chiplet + * : Select Hostboot Core + * 15.4 host_start_stop_engine + * : Initialize STOPGPE engine * * Please see the note in initsvcstructs.H for description of * the ISTEPNAME macro. @@ -54,7 +60,7 @@ namespace ISTEP_15 * return any errlogs to istep * */ -void* call_host_build_stop_image( void *io_pArgs ); +void* host_build_stop_image( void *io_pArgs ); @@ -66,7 +72,7 @@ void* call_host_build_stop_image( void *io_pArgs ); * return any errlogs to istep * */ -void* call_proc_set_pba_homer_bar( void *io_pArgs ); +void* proc_set_pba_homer_bar( void *io_pArgs ); @@ -78,7 +84,7 @@ void* call_proc_set_pba_homer_bar( void *io_pArgs ); * return any errlogs to istep * */ -void* call_host_establish_ex_chiplet( void *io_pArgs ); +void* host_establish_ex_chiplet( void *io_pArgs ); /** * @brief host_start_stop_engine @@ -88,7 +94,7 @@ void* call_host_establish_ex_chiplet( void *io_pArgs ); * return any errlogs to istep * */ -void* call_host_start_stop_engine( void *io_pArgs ); +void* host_start_stop_engine( void *io_pArgs ); }; @@ -102,22 +108,22 @@ namespace INITSERVICE }, { ISTEPNAME(15,01,"host_build_stop_image"), - ISTEP_15::call_host_build_stop_image, + ISTEP_15::host_build_stop_image, { START_FN, EXT_IMAGE, NORMAL_IPL_OP, true } }, { ISTEPNAME(15,02,"proc_set_pba_homer_bar"), - ISTEP_15::call_proc_set_pba_homer_bar, + ISTEP_15::proc_set_pba_homer_bar, { START_FN, EXT_IMAGE, NORMAL_IPL_OP, true } }, { ISTEPNAME(15,03,"host_establish_ex_chiplet"), - ISTEP_15::call_host_establish_ex_chiplet, + ISTEP_15::host_establish_ex_chiplet, { START_FN, EXT_IMAGE, NORMAL_IPL_OP, true } }, { ISTEPNAME(15,04,"host_start_stop_engine"), - ISTEP_15::call_host_start_stop_engine, + ISTEP_15::host_start_stop_engine, { START_FN, EXT_IMAGE, NORMAL_IPL_OP, true } }, }; diff --git a/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.H b/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.H deleted file mode 100644 index 2a54ce9f7..000000000 --- a/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.H +++ /dev/null @@ -1,121 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2012,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -#ifndef __BUILD_WINKLE_IMAGES_BUILD_WINKLE_IMAGES_H -#define __BUILD_WINKLE_IMAGES_BUILD_WINKLE_IMAGES_H - -/** - * @file build_winkle_images.H - * - * Build Winkle Images - * - * All of the following routines are "named isteps" - they are invoked as - * tasks by the @ref IStepDispatcher. - * - * ***************************************************************** - * THIS FILE WAS GENERATED ON 2012-04-12:1228 - * ***************************************************************** - * - * HWP_IGNORE_VERSION_CHECK - * - */ - - /* @tag isteplist - * @docversion v1.28 (12/03/12) - * @istepname build_winkle_images - * @istepnum 15 - * @istepdesc Build Winkle Images - * - * @{ - * @substepnum 1 - * @substepname host_build_winkle - * @substepdesc : Build runtime winkle images - * @target_sched serial - * @} - * @{ - * @substepnum 2 - * @substepname p8_set_pore_bar - * @substepdesc : Tell SLW Eng where winkle image is - * @target_sched serial - * @} - * @{ - * @substepnum 3 - * @substepname proc_poreslw_init - * @substepdesc : Initialize the PORE-SLW engine - * @target_sched serial - * @} - * - */ - -/******************************************************************************/ -// Includes -/******************************************************************************/ -#include <stdint.h> - -namespace BUILD_WINKLE_IMAGES -{ - - -/** - * @brief host_build_winkle - * - * Build runtime winkle images - * - * param[in,out] - pointer to any arguments, usually NULL - * - * return any error logs to istep - * - */ -void* call_host_build_winkle( void *io_pArgs ); - - - -/** - * @brief proc_set_pore_bar - * - * Tell SLW Eng where winkle image is - * - * param[in,out] - pointer to any arguments, usually NULL - * - * return any error logs to istep - * - * - */ -void* call_proc_set_pore_bar( void *io_pArgs ); - - -/** - * @brief p8_poreslw_init - * - * Initialize the PORE-SLW engine - * - * param[in,out] - pointer to any arguments, usually NULL - * - * return any error logs to istep - * - */ -void* call_p8_poreslw_init( void *io_pArgs ); - -}; // end namespace - -#endif - diff --git a/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.mk b/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.mk deleted file mode 100644 index f8673ea1a..000000000 --- a/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.mk +++ /dev/null @@ -1,76 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.mk $ -# -# OpenPOWER HostBoot Project -# -# COPYRIGHT International Business Machines Corp. 2014 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -## support for Targeting and fapi -EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer -EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi -EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat -EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp - -## pointer to common HWP files -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include - -## NOTE: add the base istep dir here. -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mvpd_accessors - -## Include sub dirs -## NOTE: add a new EXTRAINCDIR when you add a new HWP -## EXAMPLE: -## EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/<HWP_dir> -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/occ/occ_procedures -EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp/utility_procedures -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_block_wakeup_intr -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/proc_mailbox_utils - -CFLAGS += -D __FAPI - -## NOTE: add new object files when you add a new HWP -OBJS += p8_image_help.o -OBJS += p8_scan_compression.o -OBJS += pore_inline_assembler.o -OBJS += p8_pba_bar_config.o -OBJS += sbe_xip_image.o -OBJS += p8_pore_table_static_data.o -OBJS += p8_pore_table_gen_api_fixed.o -OBJS += p8_pmc_deconfig_setup.o -OBJS += p8_poreslw_init.o -OBJS += p8_set_pore_bar.o -OBJS += p8_xip_customize.o -OBJS += p8_ring_identification.o -OBJS += p8_slw_build_fixed.o -OBJS += p8_image_help_base.o -OBJS += p8_pfet_init.o -OBJS += p8_pfet_control.o -OBJS += p8_block_wakeup_intr.o -OBJS += p8_mailbox_utils.o - -## NOTE: add a new directory onto the vpaths when you add a new HWP -## EXAMPLE: -# VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/<HWP_dir> -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_block_wakeup_intr -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/proc_mailbox_utils - diff --git a/src/usr/hwpf/hwp/build_winkle_images/makefile b/src/usr/hwpf/hwp/build_winkle_images/makefile deleted file mode 100644 index 4379b38e1..000000000 --- a/src/usr/hwpf/hwp/build_winkle_images/makefile +++ /dev/null @@ -1,37 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/hwpf/hwp/build_winkle_images/makefile $ -# -# OpenPOWER HostBoot Project -# -# COPYRIGHT International Business Machines Corp. 2012,2014 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -ROOTPATH = ../../../../.. - -MODULE = build_winkle_images - -SUBDIRS += runtime.d - -# objects unique to HB IPL -OBJS += build_winkle_images.o - -# include objs common to HBRT and HB IPL -include build_winkle_images.mk - - -include ${ROOTPATH}/config.mk - diff --git a/src/usr/hwpf/hwp/runtime_attributes/pm_hwp_attributes.xml b/src/usr/hwpf/hwp/runtime_attributes/pm_hwp_attributes.xml deleted file mode 100644 index 1c9eab424..000000000 --- a/src/usr/hwpf/hwp/runtime_attributes/pm_hwp_attributes.xml +++ /dev/null @@ -1,898 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/runtime_attributes/pm_hwp_attributes.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012,2014 --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: pm_hwp_attributes.xml,v 1.13 2014/07/09 15:25:15 dcrowell Exp $ --> -<!-- - XML file specifying Power Management HWPF attributes. - These attributes are initialized to zero by the platform and set to a - meaningful value by a HWP ---> - -<attributes> -<!-- *********************************************************************** --> - -<attribute> - <id>ATTR_PROC_DPLL_DIVIDER</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>The product of the DPLL internal prescalar divide (CD_DIV124_DC) and the output divider(CD_DPLLOUT124_DC). This estalishes the step size of the DPLL in terms of this number divided into the processor reference clock.</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - - -<attribute> - <id>ATTR_PM_POWER_PROXY_TRACE_TIMER</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>The Power Proxy Trace timer (binary in microseconds) defines the time between Power Proxy Trace records when no other event that would otherwise produce a record has occured. Values must be within a range of 32us to 64ms.</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PPT_TIMER_MATCH_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>The delay is 32us * ATTR_PM_PPT_TIMER_MATCH_VALUE</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PPT_TIMER_TICK</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Defines the Power Proxy Trace interval timer tick (0=25us, 1=0.5us, 2=1us, and 3=2us)</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_AISS_TIMEOUT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Defines the timeout value for the Architected Idle State Sequencer (AISS).</description> - <valueType>uint8</valueType> - <enum>1MS=0, 2MS=1, 4MS=2, 8MS=3, 16MS=4, 32MS=5, 64MS=6, 128MS=7, 256MS=8, 512MS=9</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PSTATE_STEPSIZE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Unsigned 7 bit (baby-) stepsize for Pstate transitions between the Global Pstate Actual and the Global Pstate Target. Only non-zero values are supported for this dial. - -Used to setup the PMC voltage controller - -Producer: proc_build_pstate_tables.C - -Consumer: OCC pstate_init()</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_EXTERNAL_VRM_STEPDELAY_RANGE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Selects the resolution for the step delay count after a voltage change (decimal value N for this field divides the prv clock by 2^(N+3)) - -A 4 bit field selects one of the the upper 16bit of a 19bit counter (16+3) incremented in the nest/4 domain - -Consumer: proc_pm.scominit</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_EXTERNAL_VRM_STEPDELAY_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Step delay after a voltage change in increments of vrm_stepdelay_range. Setting this dial to a value N causes a delay of N cycles of the divided nest clk (see dial vrm_stepdelay_range). The closed formula is as follows: Delay_seconds = vrm_stepdelay_value * ( 2^(3 + vrm_stepdelay_range) / (Nest_frequency_Hz/4)) - -Consumer: proc_pm.scominit</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PMC_HANGPULSE_DIVIDER</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Divides the hang pulse to PMC to achieve XXXX. Note that this needs to be set according to the description of dial pmc_occ_heartbeat_time - -Producer: proc_pm_init - -Consumer: proc_pm.scominit</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PVSAFE_PSTATE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description> -Pstate that is invoked in the PMC voltage controller upon the loss of the OCC Heartbeat.. - -Producer: proc_pm_init.C - -Consumer: proc_pm.scominit</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_FRAME_SIZE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Number of data bits per individual SPIVID transaction (also referred to as frame) during chip select assertion - -Supported values: 0x20 (32d) - -Chip Select assertion duration is spi_frame_size + 2</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_IN_DELAY_FRAME1</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Number of SPIVID clocks after chip select to wait before capturing MISO input in frame 1 - -Supported values: 0x00 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_IN_DELAY_FRAME2</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Number of SPI clocks after chip select to wait before capturing MISO input in frame 2 - -Supported values: 0x00 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_CLOCK_POLARITY</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>SPVID Clock Polarity (CPOL=0 means that clk idle is deasserted, CPOL=1 means that clk idle is asserted)</description> - <valueType>uint8</valueType> - <enum>IDLELOW=0, IDLEHIGH = 1</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_CLOCK_PHASE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>SPI clock phase (CPHA=0 means to change/sample values of data signals on first edge, otherwise on 2nd)</description> - <valueType>uint8</valueType> - <enum>FIRSTEDGE=0, -SECONDEDGE=1</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_CLOCK_DIVIDER</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>SPIVID clock speed divider to divide the nest_nclk/4 mesh clock, which results in a divider = (nest_freq/ (SPI_freq*8))-1 -For a 2.4GHz nest clock, this means that the SPI clk can be theoretically adjusted between 600MHz and 0.29MHz (cycle time 1.66ns...3.41us, in 1.66ns steps). However, a practical range is 0.5...25MHz.</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay between command and status frames of a SPIVID WRITE operation (binary in nanoseconds) -Consumer: proc_pmc_init</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay between two frames of a Write command as measured from the end of the last bit of the first frame until the chip select of the second frame, which contains the status, is asserted. This delay allows for the checking and status data production in the SPIVID chip. - -Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time - -0x00000: Wait 1 SPI Clock -0x00001 - 0x1FFFF: value = number of ~100ns_hang_pulses - -For values greater than 0x00000, the actual delay is 1 SPI Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 SPI clock cycle.</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay between command retry attempts. - -Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time - -0x0000: Wait 1 SPI Clock -0x0001 - 0xFFFF: value = number of ~100ns_hang_pulses - -For values greater than 0x00000, the actual delay is 1 SPI Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 SPI clock cycle.</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_INTER_RETRY_DELAY</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay between SPIVID reture attempts when WRITE command status indicates an error (binary in nanoseconds) -Consumer: proc_pmc_init</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_CRC_GEN_ENABLE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>EnableS CRC generation from processor to VRM device. This will produce an 8b CRC per the enabled polynomial. If CRC generation is disabled, the full 32 bits at the data input of the SPI master are transmitted.</description> - <valueType>uint8</valueType> - <enum>TRUE = 1, FALSE = 0</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_CRC_CHECK_ENABLE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Enables CRC checking in the processor of frames from the VRM device.</description> - <valueType>uint8</valueType> - <enum>TRUE = 1, FALSE = 0</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>enables the a majority vote on the 3B of status payload on a frame received by the master as each of these have a 1 byte status field replicated three (3) times by the slave.</description> - <valueType>uint8</valueType> - <enum>TRUE = 1, FALSE = 0</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_MAX_RETRIES</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Number retries upon detected errors. - -0x00: No retry -0x01 to 0x1F: 1 to 31 respectively</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>CRC8 Polynomial Enables - -An 8 bit mask vector to enable XORs in the CRC generation and checking LFSRs at the respective bit position. MSB (x^8) is omitted since it is always enabled, so the mask layout is (x^7,x^6,x^5,x^4,x^3,x^2,x^1,1) - -Planned CRC8 polynomial: x^8 + x^7 + x^6 + x^4 + x^2 + 1 -Value to enable planned polynomial: 0b1101_0101 (=0xD5)</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_OCC_HEARTBEAT_TIME</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Time within which the OCC firmware must access the PMC or the OCC will be considered faulty whereby FIRs and malfunction alerts will be produced . (binary in nanoseconds) -Consumer: OCC FW</description> - <valueType>uint32</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_SLEEP_WINKLE_REQUEST_TIMEOUT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Time (binary in ns) that will be the threshold value for the PMC PORE request timeout. - -Consumer: proc_pmc_init.C. Will be translated to a DYNAMIC ATTRIBUTE for use by proc_pm..scominit as a multiple of PM hang pulses.. Counter starts at 0, is increased with every tp_pmc_hang_pulse as long as PORE is busy and set the PMC local FIR bit 19 when count = threshold.</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - - -<attribute> - <id>ATTR_PM_PFET_POWERUP_CORE_DELAY0</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) after a step in the Core power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT</description> - <valueType>uint32</valueType> - <platInit/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERUP_CORE_DELAY1</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) after a step in the Core power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT</description> - <valueType>uint32</valueType> - <platInit/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERUP_CORE_DELAY0_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 0 between any step in the Core power-up PFET sequence.</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERUP_CORE_DELAY1_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 1 between any step in the Core power-up PFET sequence.</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Binary vector where the most significant bits (0:11) identify the delay to be used for that step of the sequence. Power up goes from 11, then 10, then 9,.... then 0. - -0 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY0; - -1 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY1</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY0</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) between a step in the Core power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT</description> - <valueType>uint32</valueType> - <platInit/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY1</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) between a step in the Core power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT</description> - <valueType>uint32</valueType> - <platInit/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY0_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 0 between any step in the Core power-up PFET sequence.</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY1_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 1 between any step in the Core power-up PFET sequence.</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Binary vector where the most significant bits (0:11) identify the delay to be used for that step of the sequence. Power up goes from 11, then 10, then 9,.... then 0. - -0 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY0; - -1 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY1</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERUP_ECO_DELAY0</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) after a step in the ECO power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT</description> - <valueType>uint32</valueType> - <platInit/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERUP_ECO_DELAY1</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) after a step in the ECO power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT</description> - <valueType>uint32</valueType> - <platInit/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERUP_ECO_DELAY0_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 0 between any step in the ECO power-up PFET sequence.</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERUP_ECO_DELAY1_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 1 between any step in the ECO power-up PFET sequence.</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Binary vector where the most significant bits (0:11) identify the delay to be used for that step of the sequence. Power up goes from 11, then 10, then 9,.... then 0. - -0 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY0; - -1 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY1</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY0</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) between a step in the ECO power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT</description> - <valueType>uint32</valueType> - <platInit/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY1</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) between a step in the ECO power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT</description> - <valueType>uint32</valueType> - <platInit/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY0_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 0 between any step in the ECO power-up PFET sequence.</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY1_VALUE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 1 between any step in the ECO power-up PFET sequence.</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Binary vector where the most significant bits (0:11) identify the delay to be used for that step of the ECO power up sequence. Power up goes from 11, then 10, then 9,.... then 0. 0 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY0; 1 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY1</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PSTATE0_FREQUENCY</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Defines the center point of the Pstate space in the frequency domain. Binary in Khz. - -Producer: proc_build_gpstate.C - -Consumers: proc_pcbs_init.C, proc_pcbs_lpst_init.C, </description> - <valueType>uint32</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_IVRMS_ENABLED</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Indicates whether available internal voltage regulation macros (iVRMs) are to enabled. This indicates that module VPD has valid #M keywords available.</description> - <valueType>uint8</valueType> - <enum>TRUE = 1, FALSE = 0</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SAFE_PSTATE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Safe Pstate - -Valid Values:-128 thru 127 - -Producer: proc_pm_init.C - -DYNAMIC_ATTRIBUTE - -Consumer: proc_pcbs_init.C - -Establishes the Pstate that the core chiplet will take on if: -psafe less-than-or-equal PMSR[global_actual_pstate] -AND any of the following conditions are true: -Loss of OCC Heartbeat if occ_heartbeat_en is set -PMGP0[force_safe_mode] is set - -If psafe greater-than PMSR[global_actual_pstate], the global_actual_pstate is forced. - -The value of Psafe needs to be at or below the nominal Pstate to make sure safe operation of all chiplets.</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_RESONANT_CLOCK_ENABLE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Resonant Clock Enable</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_RESONANT_CLOCK_FULL_CSB_PSTATE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>FCSB Full Clock Sector Buffer (8b in terms of Pstate) -Defines the Pstate for the point at which clock sector buffers should be at full strength. This is to support Vmin operation. -</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_RESONANT_CLOCK_LFRLOW_PSTATE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>LFRLower Low Frequency Resonant Lower. Defines the Pstate for the lower end of the Low Frequency Resonant band</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_RESONANT_CLOCK_LFRUPPER_PSTATE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>LFRUpper Low Frequency Resonant Upper. Defines the Pstate for the upper end of the Low Frequency Resonant band</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_RESONANT_CLOCK_HFRLOW_PSTATE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>HFRLower High Frequency Resonant Low. Defines the Pstate for the lower end of the High Frequency Resonant band</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_RESONANT_CLOCK_HFRHIGH_PSTATE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>HFRUpper High Frequency Resonant Upper. Defines the Pstate for the upper end of the High Frequency Resonant band</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIPSS_FRAME_SIZE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Number of data bits per individual SPIPSS transaction (also referred to as frame) during chip select assertion - -Supported values: 0x10 (16d), - -Chip Select assertion duration is spi_frame_size + 2</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIPSS_OUT_COUNT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Number of bits sent out MOSI of the frame - -Supported values: 0x000 to spi_frame_size. Values beyond spi_frame_size are ignored.</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIPSS_IN_DELAY</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Number of SPI clocks after chip select to wait before capturing MISO input - -Supported values: 0x000 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIPSS_IN_COUNT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Number of bits captured on MISO input - -Supported values: 0x000 to spi_frame_size. The actual number of bits captured is spi_frame_size - spi_in_delay</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIPSS_CLOCK_POLARITY</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>SPIPSS Clock Polarity (CPOL=0 means that clk idle is deasserted, CPOH=1 means that clk idle is asserted)</description> - <valueType>uint8</valueType> - <enum>CPOL=0, CPOH=1</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIPSS_CLOCK_PHASE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>SPIPSS clock phase (CPHA=0 means to change/sample values of data signals on first edge, otherwise on 2nd)</description> - <valueType>uint8</valueType> - <enum>FIRSTEDGE=0, SECONDEDGE=1</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIPSS_CLOCK_DIVIDER</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>SPI clock speed divider to divide the nest_nclk/4 mesh clock, which results in a divider = (nest_freq/ (SPI_freq*8))-1</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIPSS_INTER_FRAME_DELAY_SETTING</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description> -Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time - -0x00000: Wait 1 PSS Clock -0x00001 - 0x1FFFF: value = number of ~100ns_hang_pulses - -For values greater than 0x00000, the actual delay is 1 PSS Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 PSSI clock cycle. - -Producer: proc_pm_init - -Consumer: proc_pss_init</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPIPSS_INTER_FRAME_DELAY</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay between two frames of a P2S command as measured from the end of the last bit of the first frame until the chip select of the second frame. (binary in nanoseconds) - -Consumer: proc_pm_init - -Produces ATTR_PM_SPIPSS_INTER_FRAME_DELAY_SETTING</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PBAX_RCV_RESERV_TIMEOUT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>PBAX Data Timeout Divider -Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang pulses are received under the following conditions: - Data Hi packet accepted and timeout waiting for Data Lo packet. - Reservation aquired and timeout waiting for Data Hi packet. - -00000 Data Timeout is Disabled -00001 divided hang pulse = PBAX hang pulse -00010 divided hang pulse = PBAX hang pulse/2 -00011 divided hang pulse = PBAX hang pulse/3 -. . . -11111 divided hang pulse = PBAX hang pulse/31</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>PBAX Send Retry count overcommit -Mode bit to count overcommit retries for the send retry threshold when sending PBAX commands on the powerbus.</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_PBAX_SND_RETRY_THRESHOLD</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>PBAX Send Retry Threshold -Defines the maximum number of retry attempts by the Send Engine for any phase of the PBAX transaction set before the operation is dropped and status bit are set. This does not count PowerBus overcommit retries unless snd_retry_count_overcom bit is set. - -0x00 : No Timeout -0x01 : 1 attempt -0x02 : 2 attempts -.etc. -0xFF : 255 attempts</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_PBAX_SND_RESERV_TIMEOUT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>PBAX Send Reservation Timeout Divider -Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang pulses are received after attempting to acquire a reservation with the PBAX Receive engine before declaring a Send Reservation Timeout error. - -00000 Send Reservation Timeout is Disabled -00001 divided hang pulse = PBAX hang pulse -00010 divided hang pulse = PBAX hang pulse/2 -00011 divided hang pulse = PBAX hang pulse/3 -. . . -11111 divided hang pulse = PBAX hang pulse/31</description> - <valueType>uint8</valueType> -</attribute> - -<attribute> - <id>ATTR_PM_SPWUP_FSP</id> - <targetType>TARGET_TYPE_EX_CHIPLET</targetType> - <description>Arbitration Attribute for FSP special wakeups: upon set, increment, upon clear, decrement; hardware bit only cleared upon attribute being 0.</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPWUP_OCC</id> - <targetType>TARGET_TYPE_EX_CHIPLET</targetType> - <description>Arbitration Attribute for OCC special wakeups: upon set, increment, upon clear, decrement; hardware bit only cleared upon attribute being 0.</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPWUP_PHYP</id> - <targetType>TARGET_TYPE_EX_CHIPLET</targetType> - <description>Arbitration Attribute for PHUP special wakeups: upon set, increment, upon clear, decrement; hardware bit only cleared upon attribute being 0.</description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPWUP_OHA_FLAG</id> - <targetType>TARGET_TYPE_EX_CHIPLET</targetType> - <description>Flag storage to break the recursive calling loop for when accessing the OHA address space from the Special Wakeup procedure.</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG</id> - <targetType>TARGET_TYPE_EX_CHIPLET</targetType> - <description>Flag storage to have the Special Wakeup procedure ignore a checkstop condition.</description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_CPM_INFLECTION_POINTS</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Structure to communicate the CPM inflection points from the CPM code to the Pstate code - - Datablock consisting of: - 8 Inflection Point frequency entries (binary in ATTR_FREQ_PROC_REFCLOCK_KHZ / ATTR_PROC_DPLL_DIVIDER units) - 1 ValidRanges entry - the number of valid inflection points in the previous locations (unit origin) - 1 pMax frequency entry - the maximum allowed boosted frequency (binary in ATTR_FREQ_PROC_REFCLOCK_KHZ / ATTR_DPLL_DIVIDER units) - 6 spare entries - - - Producer: p8_cpm_cal_load - - Consumer: p8_pstate_datablock - </description> - - <valueType>uint32</valueType> - <array>16</array> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SLW_CONTROL_VECTOR_OFFSET</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - Stores the offset in SLW image of this control vector for later use by scripts to control error injection. - This value is added to the contents of PBABAR2 for given chip to calculated the memory address for this vector per chip. - </description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SLW_DEEP_WINKLE_EXIT_GOOD_HALT_ADDR</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - Stores the offset in SLW image of the halt point for a good Deep Winkle Exit transition. - This is value may used by FAPI code to check that the SLW engine achieved an expected state. - </description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SLW_DEEP_SLEEP_EXIT_GOOD_HALT_ADDR</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - Stores the offset in SLW image of the halt point for a good Deep Sleep Exit transition. - This is value may used by FAPI code to check that the SLW engine achieved an expected state. - </description> - <valueType>uint32</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PCBS_FSM_TRACE_EN</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - Overridable attribute to allow for PCBS FSM tracing by Power Management procedures - </description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_GLOBAL_FIR_TRACE_EN</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - Overridable attribute to allow for Global checkstop and recoverable FIR tracing by Power Management procedures - </description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PFET_WORKAROUND_RUN_FLAG</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - Flag to store that the work-around for HW250017 as been run so that during any resets it is skipped. - </description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_OCC_LFIR_MASK</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description> - Upon an UE event, PRD may update some fir masks in occ domain. To avoid this update getting lost during occ reset, which could eventually cause multiple occ resets, this attribute is added to be the storage to remember the OCC_LFIR_MASK in the RESET phase so that reset procedures can later overlay this updated settings with the default instalation in INIT phase. See details in SW260003. - Producer/Consumer: p8_pm_occ_firinit.C - </description> - <valueType>uint64</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PBA_FIR_MASK</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description> - Upon an UE event, PRD may update some fir masks in occ domain. To avoid this update getting lost during occ reset, which could eventually cause multiple occ resets, this attribute is added to be the storage to remember the PBA_FIR_MASK in the RESET phase so that reset procedures can later overlay this updated settings with the default instalation in INIT phase. See details in SW260003. - Producer/Consumer: p8_pm_pba_firinit.C - </description> - <valueType>uint64</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_PMC_LFIR_MASK</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description> - Upon an UE event, PRD may update some fir masks in occ domain. To avoid this update getting lost during occ reset, which could eventually cause multiple occ resets, this attribute is added to be the storage to remember the PMC_LFIR_MASK in the RESET phase so that reset procedures can later overlay this updated settings with the default instalation in INIT phase. See details in SW260003. - Producer/Consumer: p8_pm_pmc_firinit.C - </description> - <valueType>uint64</valueType> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_FIRINIT_DONE_ONCE_FLAG</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description> - 0 = OCC has never been loaded and FIR Masks have never been initialized, - 1 = FIR masks have been initialized and the hardware should reflect correct values, - 2 = FIR masks have been initialized but the current hardware state is the reset value - Producer/Consumer: p8_pm_firinit.C - </description> - <valueType>uint8</valueType> - <writeable/> -</attribute> - -</attributes> - diff --git a/src/usr/isteps/istep15/call_host_build_stop_image.C b/src/usr/isteps/istep15/call_host_build_stop_image.C deleted file mode 100644 index 243dfbc45..000000000 --- a/src/usr/isteps/istep15/call_host_build_stop_image.C +++ /dev/null @@ -1,40 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/isteps/istep15/call_host_build_stop_image.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -#include <errl/errlentry.H> - -using namespace ERRORLOG; - -namespace ISTEP_15 -{ -void* call_host_build_stop_image (void *io_pArgs) -{ - errlHndl_t l_err = NULL; - //@TODO RTC:133832 call p9_hcode_image_build.C HWP - //@TODO RTC:133832 call p9_stop_gen_cpu_reg HWP - return l_err; -} - -}; diff --git a/src/usr/isteps/istep15/call_host_establish_ex_chiplet.C b/src/usr/isteps/istep15/call_host_establish_ex_chiplet.C deleted file mode 100644 index 531669028..000000000 --- a/src/usr/isteps/istep15/call_host_establish_ex_chiplet.C +++ /dev/null @@ -1,39 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/isteps/istep15/call_host_establish_ex_chiplet.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -#include <errl/errlentry.H> - -using namespace ERRORLOG; - -namespace ISTEP_15 -{ -void* call_host_establish_ex_chiplet (void *io_pArgs) -{ - errlHndl_t l_err = NULL; - //@TODO RTC:133832 call p9_update_ec_eq_state.C HWP - return l_err; -} - -}; diff --git a/src/usr/isteps/istep15/call_host_start_stop_engine.C b/src/usr/isteps/istep15/call_host_start_stop_engine.C deleted file mode 100644 index 0d8b745cc..000000000 --- a/src/usr/isteps/istep15/call_host_start_stop_engine.C +++ /dev/null @@ -1,40 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/isteps/istep15/call_host_start_stop_engine.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -#include <errl/errlentry.H> - -using namespace ERRORLOG; - -namespace ISTEP_15 -{ -void* call_host_start_stop_engine (void *io_pArgs) -{ - errlHndl_t l_err = NULL; - //@TODO RTC:133832 call p9_pm_stop_gpe_init HWP - //@TODO RTC:133832 call p9_pfet_init HWP - return l_err; -} - -}; diff --git a/src/usr/isteps/istep15/call_proc_set_pba_homer_bar.C b/src/usr/isteps/istep15/call_proc_set_pba_homer_bar.C deleted file mode 100644 index 552cba672..000000000 --- a/src/usr/isteps/istep15/call_proc_set_pba_homer_bar.C +++ /dev/null @@ -1,40 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/isteps/istep15/call_proc_set_pba_homer_bar.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -#include <errl/errlentry.H> - -using namespace ERRORLOG; - -namespace ISTEP_15 -{ -void* call_proc_set_pba_homer_bar (void *io_pArgs) -{ - errlHndl_t l_err = NULL; - //@TODO RTC:133832 call p9_pm_set_homer_bar.C HWP - //@TODO RTC:133832 call p9_pm_pba_bar_config.C HWP - return l_err; -} - -}; diff --git a/src/usr/isteps/istep15/host_build_stop_image.C b/src/usr/isteps/istep15/host_build_stop_image.C new file mode 100644 index 000000000..b577f2994 --- /dev/null +++ b/src/usr/isteps/istep15/host_build_stop_image.C @@ -0,0 +1,594 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/istep15/host_build_stop_image.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + + +////System +#include <sys/misc.h> +#include <sys/mmio.h> +#include <sys/mm.h> +#include <usr/vmmconst.h> +#include <arch/pirformat.H> + +//Error handling and tracing +#include <errl/errlentry.H> +#include <errl/errluserdetails.H> +#include <errl/errludtarget.H> +#include <errl/errlmanager.H> +#include <isteps/hwpisteperror.H> +#include <initservice/isteps_trace.H> + +//PNOR Resource Provider +#include <pnor/pnorif.H> + +//Targeting Support +#include <targeting/common/utilFilter.H> +#include <fapi2/target.H> + +//HWP Invoker +#include <fapi2/plat_hwp_invoker.H> + +//Import directory (from EKB repository) +#include <p9_hcode_image_build.H> +#include <p9_stop_api.H> +#include <p9_xip_image.h> +#include <p9_image_help_base.H> + +using namespace ERRORLOG; +using namespace ISTEP; +using namespace ISTEP_ERROR; +using namespace TARGETING; +using namespace PNOR; +using namespace stopImageSection; +using namespace fapi2; + +namespace ISTEP_15 +{ + + +/** + * @brief Load HCODE image and return a pointer to it, or NULL + * + * @param[out] - address of the HCODE image + * @param[out] - size of the HCODE image + * + * @return NULL if success, errorlog if failure + * + */ +errlHndl_t loadHcodeImage( char *& o_rHcodeAddr, + uint32_t & o_rHcodeSize ) +{ + errlHndl_t l_errl = NULL; + PNOR::SectionInfo_t l_info; +// uint64_t rc = 0; + o_rHcodeSize = 0; + + do + { + // Get WINK PNOR section info from PNOR RP + l_errl = PNOR::getSectionInfo( PNOR::WINK, l_info ); + if( l_errl ) + { + break; + } + +//@TODO RTC: 147560 Enable checks and manipulation on the hcode image +// rc = p9_xip_image_size(reinterpret_cast<void*>(l_info.vaddr), +// &o_rHcodeSize); + +// if((rc !=0) || (o_rHcodeSize == 0) || o_rHcodeSize > l_info.size) +// { +// TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, +// "ERROR: invalid WINK image rc[%d] hcodeSize[%d] part size[%d]", +// rc, o_rHcodeSize, l_info.size); +// /*@ +// * @errortype +// * @reasoncode RC_LOAD_HCODE_FROM_PNOR_FAILED +// * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE +// * @moduleid MOD_BUILD_HCODE_IMAGES +// * @userdata1 Hi 32 bits: return code from sbe_xip_image_size +// * Lo 32 bits: Size of memory requested +// * @userdata2 Size of WINK PNOR partition +// * @devdesc Image from PNOR WINK partition invalid, too small, +// * or too big +// * @custdesc A problem occurred during the IPL +// * of the system. +// */ +// l_errl = +// new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, +// ISTEP::MOD_BUILD_HCODE_IMAGES, +// ISTEP::RC_LOAD_HCODE_FROM_PNOR_FAILED, +// (rc<<32)|o_rHcodeSize, +// l_info.size, +// true); +// break; +// } + + o_rHcodeAddr = reinterpret_cast<char*>(l_info.vaddr); + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "HCODE addr = 0x%p, size=0x%x", + o_rHcodeAddr, + o_rHcodeSize ); + + } while ( 0 ); + + return l_errl; +} + +/** + * @brief apply cpu reg information to the HCODE image using + * p9_stop_save_cpureg() . + * + * @param i_procChipTarg - proc target + * @param io_image - pointer to the HCODE image + * @param i_sizeImage - size of the HCODE image + * + * @return errorlog if error, NULL otherwise. + * + */ +errlHndl_t applyHcodeGenCpuRegs( TARGETING::Target *i_procChipTarg, + void *io_image, + uint32_t i_sizeImage ) +{ + errlHndl_t l_errl = NULL; + + //Use TARGETING code to look up CORE target handles + TARGETING::TargetHandleList l_coreIds; + getChildChiplets( l_coreIds, + i_procChipTarg, + TYPE_CORE, + false ); + + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "applyHcodeGenCpuRegs: Process cores=0x%x, threads=0x%x", + l_coreIds.size(), + cpu_thread_count() ); + + //Thread tracking + const size_t l_cpu_thread_count = cpu_thread_count(); + TARGETING::ATTR_CHIP_UNIT_type l_coreId = 0; + size_t l_threadId = 0; + //Error Handling + uint32_t l_rc = 0; + uint32_t l_failAddr = 0; + //Register Values + uint64_t l_msrVal = cpu_spr_value(CPU_SPR_MSR) ; + uint64_t l_lpcrVal = cpu_spr_value( CPU_SPR_LPCR); + + // See LPCR def, PECE "reg" in Power ISA AS Version: Power8 June 27, 2012 + // and 23.7.3.5 - 6 in Murano Book 4 + l_lpcrVal &= ~(0x0000000000002000) ; + +//@TODO RTC:147565 +//Force Core Checkstops by telling ACTION1 Reg after coming out of winkle +// Core FIR Action1 Register value from Nick +// const uint64_t action1_reg = 0xEA5C139705980000; + + //Get top-lvl system target with TARGETING code to find the enabled threads + TARGETING::Target* sys = NULL; + TARGETING::targetService().getTopLevelTarget(sys); + assert( sys != NULL ); + uint64_t en_threads = sys->getAttr<ATTR_ENABLED_THREADS>(); + + //look up the HRMOR value from the HRMOR CPU special purpose register(SPR) + uint64_t l_hrmorVal = cpu_spr_value(CPU_SPR_HRMOR); + + //iterate through the cores while copying information from SPRs + for (const auto & l_core: l_coreIds) + { + // trace the HUID of the core we are writing to + TRACDCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "target HUID %.8X", TARGETING::get_huid(l_core)); + + l_threadId = 0; + + //Get core's parent processor target handle + ConstTargetHandle_t l_processor = getParentChip(l_core); + + //Read core's chip unit id attribute and store it as the core's id + CHIP_UNIT_ATTR l_coreId = + (l_core)->getAttr<TARGETING::ATTR_CHIP_UNIT>(); + //Read the processor's fabric group id + FABRIC_GROUP_ID_ATTR l_logicalGroupId = + l_processor->getAttr<TARGETING::ATTR_FABRIC_GROUP_ID>(); + + //Read the processor's fabric chip id + FABRIC_CHIP_ID_ATTR l_chipId = + l_processor->getAttr<TARGETING::ATTR_FABRIC_CHIP_ID>(); + + TRACDCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "chip unit: %d fabric group: %d chip id: %d", + l_coreId, l_logicalGroupId,l_chipId); + + //store the PIR value by passing the values read in above into the + //PIR_t constructor and read the .word attribute on the new PIR struct + uint64_t l_pirVal = PIR_t(l_logicalGroupId, l_chipId, l_coreId).word; + + //Call p9_stop_save_cpureg from p9_stop_api to store the MSR SPR value + l_rc = p9_stop_save_cpureg( io_image, + P9_STOP_SPR_MSR, + l_msrVal, + l_pirVal); + if ( l_rc ) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR: MSR: core=0x%x,thread=0x%x,l_rc=0x%x", + l_coreId, l_threadId, l_rc ); + l_failAddr = P9_STOP_SPR_MSR; + break; + } + + + //Call p9_stop_save_cpureg from p9_stop_api to store the HRMOR SPR value + l_rc = p9_stop_save_cpureg( io_image, + P9_STOP_SPR_HRMOR, + l_hrmorVal, + l_pirVal); + + if ( l_rc ){ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR: HRMOR: core=0x%x,thread=0x%x,l_rc=0x%x", + l_coreId, l_threadId, l_rc ); + l_failAddr = P9_STOP_SPR_HRMOR; + break; + } + + // fill in lpcr for each thread + for ( l_threadId=0; l_threadId < l_cpu_thread_count; l_threadId++ ) + { + // Skip threads that we shouldn't be starting + if( !(en_threads & (0x8000000000000000>>l_threadId)) ) + { + continue; + } + + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "applyHcodeGenCpuRegs: core=0x%x,thread=0x%x: ", + l_coreId, l_threadId ); + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "applyHcodeGenCpuRegs: msrc=0x%x,lpcr=0x%x,hrmor=0x%x", + l_msrVal, l_lpcrVal, l_hrmorVal ); + + //the thread ID is the last 3 bytes of pirVal so you can just OR + l_pirVal |= l_threadId; + + //Call p9_stop_save_cpureg from p9_stop_api + //to store the LPCR SPR value + l_rc = p9_stop_save_cpureg( io_image, + P9_STOP_SPR_LPCR, + l_lpcrVal, + l_pirVal); + if ( l_rc ) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR: LPCR: core=0x%x,thread=0x%x,l_rc=0x%x", + l_coreId, l_threadId, l_rc ); + l_failAddr = P9_STOP_SPR_LPCR; + break; + } + } // end for l_threadId + + // if error writing thread break out of l_coreId loop + if ( l_rc !=0 ) + { + break; + } +//@TODO RTC:147565 +//Force Core Checkstops by telling ACTION1 Reg after coming out of winkle +//@fixme HACK in place for OPAL + // Need to force core checkstops to escalate to a system checkstop + // by telling the HCODE to update the ACTION1 register when it + // comes out of winkle (see HW286670) +// l_rc = p8_pore_gen_scom_fixed( io_image, +// P8_SLW_MODEBUILD_IPL, +// EX_CORE_FIR_ACTION1_0x10013107, +// l_coreId, +// action1_reg, +// P8_PORE_SCOM_REPLACE, +// P8_SCOM_SECTION_NC ); +// if( l_rc ) +// { +// TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, +// "ERROR: ACTION1: core=0x%x,l_rc=0x%x", +// l_coreId, l_rc ); +// l_failAddr = EX_CORE_FIR_ACTION1_0x10013107; +// break; +// } + + } // end for l_coreIds + + if ( l_rc ){ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR: p9 stop api fail core=0x%x, thread=0x%x, l_rc=0x%x", + l_coreId, l_threadId, l_rc ); + /*@ + * @errortype + * @reasoncode ISTEP::RC_BAD_RC + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid ISTEP::MOD_BUILD_HCODE_IMAGES + * @userdata1 Hi 32 bits: return code from p8_pore_gen_scom_fixed + * Lo 32 bits: Address of EX_CORE_FIR_ACTION1_0x10013107 + * @userdata2 Hi 32 bits: ID of core + * Lo 32 bits: Thread id + * @devdesc Unable to force core checkstops by updating ACTION1 + * when it comes out of winkle + * @custdesc A problem occurred during the IPL + * of the system. + */ + l_errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, + ISTEP::MOD_BUILD_HCODE_IMAGES, + ISTEP::RC_BAD_RC, + TWO_UINT32_TO_UINT64(l_rc,l_failAddr), + TWO_UINT32_TO_UINT64(l_coreId,l_threadId), + true); + l_errl->collectTrace(FAPI_TRACE_NAME,256); + l_errl->collectTrace(FAPI_IMP_TRACE_NAME,256); + l_errl->collectTrace("ISTEPS_TRACE",256); + } + + return l_errl; +} + +void* host_build_stop_image (void *io_pArgs) +{ + errlHndl_t l_errl = NULL; + ISTEP_ERROR::IStepError l_StepError; + + char* l_pHcodeImage = NULL; + uint32_t l_hcodeSize = 0; + void* l_pRealMemBase = NULL; + void* l_pVirtMemBase = NULL; + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "host_build_stop_image entry" ); + + // allocate a temporary buffer + void* l_temp_buffer = malloc(FIXED_RING_BUF_SIZE); + + + do { + // Get the node-offset for our instance by looking at the HRMOR + uint64_t l_memBase = cpu_spr_value(CPU_SPR_HRMOR); + // mask off the secureboot offset + l_memBase = 0xFFFFF00000000000 & l_memBase; + + // Now offset up to our hardcoded region + l_memBase += VMM_HOMER_REGION_START_ADDR; + + // Get a chunk of real memory big enough to store all the possible + // HCODE images. (4MB is size of HOMER) + + assert(VMM_HOMER_REGION_SIZE <= (P9_MAX_PROCS * (4 * MEGABYTE)), + "host_build_stop_image: Unsupported HOMER Region size"); + + //If running Sapphire need to place this at the top of memory instead + if(is_sapphire_load()) + { + l_memBase = get_top_mem_addr(); + assert (l_memBase != 0, + "host_build_stop_image: Top of memory was 0!"); + l_memBase -= VMM_ALL_HOMER_OCC_MEMORY_SIZE; + } + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "HOMER base = %x", l_memBase); + + l_pRealMemBase = reinterpret_cast<void * const>(l_memBase ); + + //Convert the real memory pointer to a pointer in virtual memory + l_pVirtMemBase = + mm_block_map(l_pRealMemBase, VMM_HOMER_REGION_SIZE); + + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Got virtual mem buffer for %d cpus = 0x%p", + P9_MAX_PROCS, + l_pVirtMemBase ); + + // Continue, build hcode images + + //Load the reference image from PNOR + l_errl = loadHcodeImage( l_pHcodeImage, + l_hcodeSize ); + if ( l_errl ) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "host_build_stop_image ERROR : errorlog PLID=0x%x", + l_errl->plid() ); + + // drop out of do block with errorlog. + break; + } + + + // Loop through all functional Procs and generate images for them. + TARGETING::TargetHandleList l_procChips; + getAllChips( l_procChips, + TARGETING::TYPE_PROC ); + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Found %d procs in system", + l_procChips.size() ); + + for (const auto & l_procChip: l_procChips) + { + do { + + // write the HUID of the core we are writing to + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "Build STOP image for proc " + "target HUID %.8X", TARGETING::get_huid(l_procChip)); + + + // calculate size and location of the HCODE output buffer + uint32_t l_procNum = + l_procChip->getAttr<TARGETING::ATTR_POSITION>(); + uint64_t l_procOffsetAddr = + ( l_procNum *VMM_HOMER_INSTANCE_SIZE ); + + uint64_t l_procRealMemAddr = + reinterpret_cast<uint64_t>(l_pRealMemBase) + + l_procOffsetAddr; + + void *l_pImageOut = + reinterpret_cast<void * const> + (reinterpret_cast<uint64_t>(l_pVirtMemBase) + + l_procOffsetAddr) ; + + uint32_t l_sizeImageOut = + ((P9_MAX_PROCS * (4 * MEGABYTE))); + + // set default values, p9_hcode_build will provide actual size + l_procChip->setAttr<TARGETING::ATTR_HCODE_IMAGE_ADDR> + ( l_procRealMemAddr ); + l_procChip->setAttr<TARGETING::ATTR_HCODE_IMAGE_SIZE> + ( l_sizeImageOut ) ; + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Real mem buffer for cpu 0x%08x = %p, virtAddr=%p", + l_procNum, + l_procRealMemAddr, + l_pImageOut); + + // cast OUR type of target to a FAPI2 type of target. + const fapi2::Target<TARGET_TYPE_PROC_CHIP> + l_fapi_cpu_target( const_cast<TARGETING::Target*>(l_procChip)); + + ImageType_t img_type; + + //Call p9_hcode_image_build.C HWP +// FAPI_INVOKE_HWP( l_errl, +// p9_hcode_image_build, +// l_fapi_cpu_target, //Proc chip target. +// reinterpret_cast<void*>(l_pHcodeImage), +// l_pImageOut, +// PHASE_IPL, //sys_Phase +// img_type, +// l_temp_buffer) + if ( l_errl ) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "host_build_stop_image ERROR : errorlog PLID=0x%x", + l_errl->plid() ); + + // drop out of block with errorlog. + break; + } + + + // set the actual size of the image now. + l_procChip->setAttr<TARGETING::ATTR_HCODE_IMAGE_SIZE> + ( l_sizeImageOut ); + +//@TODO RTC: 147560 Enable checks and manipulation on the hcode image +// l_errl = applyHcodeGenCpuRegs( l_procChip, +// l_pImageOut, +// l_sizeImageOut ); + if ( l_errl ) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "applyHcodeGenCpuRegs ERROR : errorlog PLID=0x%x", + l_errl->plid() ); + + // drop out of block with errorlog. + break; + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "applyHcodeGenCpuRegs SUCCESS " ); + } + + } while (0) ; + + // broke out due to an error, store all the details away, store + // the errlog in IStepError, and continue to next proc + if (l_errl) + { + // capture the target data in the elog + ErrlUserDetailsTarget(l_procChip).addToLog( l_errl ); + + // Create IStep error log and cross ref error that occurred + l_StepError.addErrorDetails( l_errl ); + + // Commit Error + errlCommit( l_errl, HWPF_COMP_ID ); + } + + } ; // endfor + + } while (0); + // @@@@@ END CUSTOM BLOCK: @@@@@ + + if (l_errl) + { + // Create IStep error log and cross ref error that occurred + l_StepError.addErrorDetails( l_errl ); + + // Commit Error + errlCommit( l_errl, HWPF_COMP_ID ); + } + + // delete working buffers + if( l_temp_buffer ) { free(l_temp_buffer); } + + if(l_pVirtMemBase) + { + int rc = 0; + rc = mm_block_unmap(l_pVirtMemBase); + if (rc != 0) + { + /*@ + * @errortype + * @reasoncode ISTEP::RC_MM_UNMAP_ERR + * @moduleid ISTEP::MOD_BUILD_HCODE_IMAGES + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @userdata1 Return Code + * @userdata2 Unmap address + * @devdesc mm_block_unmap() returns error + * @custdesc A problem occurred during the IPL + * of the system. + */ + l_errl = + new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + ISTEP::MOD_BUILD_HCODE_IMAGES, + ISTEP::RC_MM_UNMAP_ERR, + rc, + reinterpret_cast<uint64_t> + (l_pVirtMemBase)); + + // Create IStep error log and cross reference error that occurred + l_StepError.addErrorDetails( l_errl ); + + // Commit error + errlCommit( l_errl, ISTEP_COMP_ID ); + } + } + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "host_build_stop_image exit" ); + + // end task, returning any errorlogs to IStepDisp + return l_StepError.getErrorHandle(); +} +}; diff --git a/src/usr/isteps/istep15/host_establish_ex_chiplet.C b/src/usr/isteps/istep15/host_establish_ex_chiplet.C new file mode 100644 index 000000000..e96394007 --- /dev/null +++ b/src/usr/isteps/istep15/host_establish_ex_chiplet.C @@ -0,0 +1,85 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/istep15/host_establish_ex_chiplet.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +//From Hostboot Directory +////Error handling and traces +#include <errl/errlentry.H> +#include <errl/errluserdetails.H> +#include <errl/errludtarget.H> +#include <errl/errlmanager.H> +#include <isteps/hwpisteperror.H> +#include <initservice/isteps_trace.H> + +//HWP Invoker +#include <fapi2/plat_hwp_invoker.H> + +//Targeting Support +#include <targeting/common/utilFilter.H> +#include <fapi2/target.H> + +//From Import Directory (EKB Repository) +#include <p9_update_ec_eq_state.H> + +//Namespaces +using namespace ERRORLOG; +using namespace TARGETING; +using namespace fapi2; + +namespace ISTEP_15 +{ +void* host_establish_ex_chiplet (void *io_pArgs) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "host_establish_ex_chiplet entry" ); + ISTEP_ERROR::IStepError l_StepError; + errlHndl_t l_errl = NULL; + do { + //Use targeting code to get a list of all processors + TARGETING::TargetHandleList l_procChips; + getAllChips( l_procChips, TARGETING::TYPE_PROC ); + + for (const auto & l_procChip: l_procChips) + { + const fapi2::Target<TARGET_TYPE_PROC_CHIP> + l_fapi_cpu_target(l_procChip); + // call p9_update_ec_eq_state.C HWP + FAPI_INVOKE_HWP( l_errl, + p9_update_ec_eq_state, + l_fapi_cpu_target); + + if(l_errl) + { + ErrlUserDetailsTarget(l_procChip).addToLog(l_errl); + l_StepError.addErrorDetails( l_errl ); + errlCommit( l_errl, HWPF_COMP_ID ); + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "host_establish_ex_chiplet:: failed on proc with HUID : %d",TARGETING::get_huid(l_procChip) ); + } + } + }while(0); + + // end task, returning any errorlogs to IStepDisp + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "host_establish_ex_chiplet exit" ); + return l_StepError.getErrorHandle(); +} +}; diff --git a/src/usr/isteps/istep15/host_start_stop_engine.C b/src/usr/isteps/istep15/host_start_stop_engine.C new file mode 100644 index 000000000..7f3bdbbcb --- /dev/null +++ b/src/usr/isteps/istep15/host_start_stop_engine.C @@ -0,0 +1,93 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/istep15/host_start_stop_engine.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +//From Hostboot Directory +////Error handling and traces +#include <errl/errlentry.H> +#include <errl/errlmanager.H> +#include <isteps/hwpisteperror.H> +#include <initservice/isteps_trace.H> +#include <errl/errluserdetails.H> +#include <errl/errludtarget.H> + +//HWP Invoker +#include <fapi2/plat_hwp_invoker.H> + +////Targeting support +#include <fapi2/target.H> +#include <targeting/common/utilFilter.H> + +//From Import Directory (EKB Repository) +#include <p9_pm.H> +#include <p9_pm_stop_gpe_init.H> + +//Namespaces +using namespace ERRORLOG; +using namespace TARGETING; +using namespace p9pm; +using namespace fapi2; + +namespace ISTEP_15 +{ +void* host_start_stop_engine (void *io_pArgs) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_host_start_stop_engine entry" ); + ISTEP_ERROR::IStepError l_StepError; + errlHndl_t l_errl = NULL; + + do { + //Use targeting code to get a list of all processors + TARGETING::TargetHandleList l_procChips; + getAllChips( l_procChips, TARGETING::TYPE_PROC ); + + for (const auto & l_procChip: l_procChips) + { + //Convert the TARGETING::Target into a fapi2::Target by passing + //the const_casted l_procChip into the fapi::Target constructor + fapi2::Target<TARGET_TYPE_PROC_CHIP>l_fapi2_cpu_target( + (l_procChip)); + +//RTC:149398 Re-enable when new vector constructor is implemented + //call p9_pm_stop_gpe_init.C HWP +// FAPI_INVOKE_HWP(l_errl, +// p9_pm_stop_gpe_init, +// l_fapi2_cpu_target, +// PM_INIT); + if(l_errl) + { + ErrlUserDetailsTarget(l_procChip).addToLog(l_errl); + l_StepError.addErrorDetails( l_errl ); + errlCommit( l_errl, HWPF_COMP_ID ); + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "host_start_stop_engine:: failed on proc with HUID : %d",TARGETING::get_huid(l_procChip) ); + } + } + }while (0); + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_host_start_stop_engine exit" ); + // end task, returning any errorlogs to IStepDisp + return l_StepError.getErrorHandle(); +} + +}; diff --git a/src/usr/isteps/istep15/makefile b/src/usr/isteps/istep15/makefile index 392773dc8..4dfceaa2d 100644 --- a/src/usr/isteps/istep15/makefile +++ b/src/usr/isteps/istep15/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2015 +# Contributors Listed Below - COPYRIGHT 2015,2016 # [+] International Business Machines Corp. # # @@ -24,10 +24,46 @@ # IBM_PROLOG_END_TAG ROOTPATH = ../../../.. MODULE = istep15 +PROCEDURES_PATH = ${ROOTPATH}/src/import/chips/p9/procedures + +EXTRAINCDIR += ${PROCEDURES_PATH}/hwp/pm/ +EXTRAINCDIR += ${PROCEDURES_PATH}/stop_reg/ +EXTRAINCDIR += ${PROCEDURES_PATH}/hwp/lib/ +EXTRAINCDIR += ${PROCEDURES_PATH}/utils/stopreg/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/common/include/ +EXTRAINCDIR += ${ROOTPATH}/src/import/hwpf/fapi2/include/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/xip/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/utils/ +EXTRAINCDIR += ${ROOTPATH}/src/include/usr/fapi2/ +EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/ +EXTRAINCDIR += ${PROCEDURES_PATH}/ppe/include/registers/ + +OBJS += host_build_stop_image.o +OBJS += proc_set_pba_homer_bar.o +OBJS += host_establish_ex_chiplet.o +OBJS += host_start_stop_engine.o + +#@TODO RTC:147621 Pull p9_stop_util into a seperate library +OBJS += p9_stop_util.o + + +include ${ROOTPATH}/procedure.rules.mk +include $(PROCEDURES_PATH)/hwp/pm/p9_pm_pfet_init.mk +include $(PROCEDURES_PATH)/hwp/pm/p9_pm_pba_bar_config.mk +include $(PROCEDURES_PATH)/hwp/pm/p9_pm_set_homer_bar.mk +# include $(PROCEDURES_PATH)/hwp/pm/p9_pm_stop_gpe_init.mk +include $(PROCEDURES_PATH)/hwp/pm/p9_pm_utils.mk +include $(PROCEDURES_PATH)/hwp/pm/p9_update_ec_eq_state.mk +include $(PROCEDURES_PATH)/hwp/pm/p9_hcode_image_build.mk +include $(PROCEDURES_PATH)/utils/stopreg/p9_stop_api.mk +# include $(PROCEDURES_PATH)/hwp/pm/p9_pm_pba_init.mk +include ${ROOTPATH}/src/import/chips/p9/xip/p9_xip_image.mk + + -OBJS += call_host_build_stop_image.o -OBJS += call_proc_set_pba_homer_bar.o -OBJS += call_host_establish_ex_chiplet.o -OBJS += call_host_start_stop_engine.o include ${ROOTPATH}/config.mk + +VPATH += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/pm/ +VPATH += ${ROOTPATH}/src/import/chips/p9/procedures/utils/stopreg/ +VPATH += ${ROOTPATH}/src/import/chips/p9/xip/
\ No newline at end of file diff --git a/src/usr/isteps/istep15/proc_set_pba_homer_bar.C b/src/usr/isteps/istep15/proc_set_pba_homer_bar.C new file mode 100644 index 000000000..983fc4d31 --- /dev/null +++ b/src/usr/isteps/istep15/proc_set_pba_homer_bar.C @@ -0,0 +1,97 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/isteps/istep15/proc_set_pba_homer_bar.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + + +//From Hostboot Directory +////System + #include <limits.h> + #include <sys/misc.h> + +////Error handling and traces + #include <errl/errluserdetails.H> + #include <errl/errlmanager.H> + #include <errl/errlentry.H> + #include <errl/errludtarget.H> + #include <isteps/hwpisteperror.H> + #include <initservice/isteps_trace.H> + +////Targeting support + #include <targeting/common/utilFilter.H> + #include <fapi2/plat_hwp_invoker.H> + #include <fapi2/target.H> + +//From Import Directory (EKB Repository) +#include <return_code.H> +#include <p9_pm_set_homer_bar.H> + +//Namespaces +using namespace ERRORLOG; +using namespace TARGETING; +using namespace fapi2; + +namespace ISTEP_15 +{ +void* proc_set_pba_homer_bar (void *io_pArgs) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_set_pba_homer_bar entry" ); + ISTEP_ERROR::IStepError l_StepError; + errlHndl_t l_errl = NULL; + TARGETING::TargetHandleList l_procChips; + + //Use targeting code to get a list of all processors + getAllChips( l_procChips, TARGETING::TYPE_PROC ); + + //Loop through all of the procs and call the HWP on each one + for (const auto & l_procChip: l_procChips) + { + + //Convert the TARGETING::Target into a fapi2::Target by passing + //the const_casted l_procChip into the fapi::Target constructor + const fapi2::Target<TARGET_TYPE_PROC_CHIP> + l_fapi_cpu_target((l_procChip)); + + //call p9_pm_set_homer_bar.C HWP + //TODO RTC:147693 + //Need to determine what address this procedures is actually expecting +// const uint64_t homerAddr = l_procChip->getAttr<TARGETING::ATTR_HOMER_PHYS_ADDR>(); +// FAPI_INVOKE_HWP( l_errl, +// p9_pm_set_homer_bar, +// l_fapi_cpu_target, +// homerAddr + HOMER_OFFSET_TO_OCC_IMG, +// 3); + + if(l_errl) + { + l_StepError.addErrorDetails( l_errl ); + errlCommit( l_errl, HWPF_COMP_ID ); + } + } + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_set_pba_homer_bar exit" ); + // end task, returning any errorlogs to IStepDisp + return l_StepError.getErrorHandle(); +} + +}; diff --git a/src/usr/isteps/istep21/call_host_start_payload.C b/src/usr/isteps/istep21/call_host_start_payload.C index 886a5b4f4..07eb58363 100644 --- a/src/usr/isteps/istep21/call_host_start_payload.C +++ b/src/usr/isteps/istep21/call_host_start_payload.C @@ -578,7 +578,7 @@ errlHndl_t enableCoreCheckstops() uint64_t l_physAddr = l_pChipTarget->getAttr<TARGETING::ATTR_SLW_IMAGE_ADDR>(); l_slwPtr = mm_block_map(reinterpret_cast<void*>(l_physAddr), - HOMER_MAX_SLW_IMG_SIZE_IN_MB*MEGABYTE); + HOMER_MAX_STOP_IMG_SIZE_IN_MB*MEGABYTE); if( l_slwPtr == NULL ) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "Error from mm_block_map : phys=%.16X", l_physAddr ); @@ -587,7 +587,7 @@ errlHndl_t enableCoreCheckstops() * @reasoncode RC_MM_MAP_ERR * @moduleid MOD_ENABLE_CORE_CHECKSTOPS * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE - * @userdata1 <unused> + * @userdata1 Size of STOP IMG * @userdata2 Physical address * @devdesc mm_block_map() returns error * @custdesc A problem occurred during the IPL @@ -596,9 +596,9 @@ errlHndl_t enableCoreCheckstops() l_errl = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, - MOD_ENABLE_CORE_CHECKSTOPS, - RC_MM_MAP_ERR, - 0, + ISTEP::MOD_ENABLE_CORE_CHECKSTOPS, + ISTEP::RC_MM_MAP_ERR, + HOMER_MAX_STOP_IMG_SIZE_IN_MB*MEGABYTE, l_physAddr); } @@ -680,8 +680,8 @@ errlHndl_t enableCoreCheckstops() TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "Error from mm_block_unmap : rc=%d, ptr=%p", mm_rc, l_slwPtr ); /*@ * @errortype - * @reasoncode RC_MM_UNMAP_ERR - * @moduleid MOD_ENABLE_CORE_CHECKSTOPS + * @reasoncode ISTEP::RC_MM_UNMAP_ERR + * @moduleid ISTEP::MOD_ENABLE_CORE_CHECKSTOPS * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE * @userdata1 Return Code * @userdata2 Unmap address @@ -692,8 +692,8 @@ errlHndl_t enableCoreCheckstops() l_errl = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, - MOD_ENABLE_CORE_CHECKSTOPS, - RC_MM_UNMAP_ERR, + ISTEP::MOD_ENABLE_CORE_CHECKSTOPS, + ISTEP::RC_MM_UNMAP_ERR, mm_rc, reinterpret_cast<uint64_t> (l_slwPtr)); diff --git a/src/usr/targeting/common/xmltohb/common.mk b/src/usr/targeting/common/xmltohb/common.mk index 6868c4b56..48fe16a15 100755 --- a/src/usr/targeting/common/xmltohb/common.mk +++ b/src/usr/targeting/common/xmltohb/common.mk @@ -62,14 +62,11 @@ FAPI_ATTR_SOURCES += chip_attributes.xml FAPI_ATTR_SOURCES += $(if $(CONFIG_VPD_GETMACRO_USE_EFF_ATTR), lab_dimm_spd_attributes.xml, dimm_spd_attributes.xml) FAPI_ATTR_SOURCES += $(if $(CONFIG_VPD_GETMACRO_USE_EFF_ATTR), lab_dimm_attributes.xml, dimm_attributes.xml) FAPI_ATTR_SOURCES += unit_attributes.xml -FAPI_ATTR_SOURCES += freq_attributes.xml FAPI_ATTR_SOURCES += ei_bus_attributes.xml FAPI_ATTR_SOURCES += dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml FAPI_ATTR_SOURCES += dram_initialization/proc_setup_bars/proc_setup_bars_l3_attributes.xml FAPI_ATTR_SOURCES += dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml FAPI_ATTR_SOURCES += activate_powerbus/proc_build_smp/proc_fab_smp_fabric_attributes.xml -#FAPI_ATTR_SOURCES += runtime_attributes/pm_hwp_attributes.xml -#FAPI_ATTR_SOURCES += runtime_attributes/pm_plat_attributes.xml FAPI_ATTR_SOURCES += nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml FAPI_ATTR_SOURCES += dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr_attributes.xml FAPI_ATTR_SOURCES += common_attributes.xml diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index 29dac74dd..d1c25a5bf 100755 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -2021,6 +2021,10 @@ <attribute><id>HB_RSV_MEM_SIZE_MB</id></attribute> <attribute><id>FREQ_CORE_MAX</id></attribute> <attribute><id>THREAD_COUNT</id></attribute> + <attribute><id>PFET_POWERUP_DELAY_NS</id></attribute> + <attribute><id>PFET_POWERDOWN_DELAY_NS</id></attribute> + <attribute><id>PFET_VDD_VOFF_SEL</id></attribute> + <attribute><id>PFET_VCS_VOFF_SEL</id></attribute> </targetType> <!-- enc-node-power9 --> |
