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6 files changed, 8282 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_avsbus_lib.C b/src/import/chips/p9/procedures/hwp/lib/p9_avsbus_lib.C new file mode 100644 index 000000000..528bd67d0 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/p9_avsbus_lib.C @@ -0,0 +1,446 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/lib/p9_avsbus_lib.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_avsbus_lib.C +/// @brief Library functions for AVSBus +/// +// *HW Owner : Sudheendra K Srivathsa <sudheendraks@in.ibm.com> +// *FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *Team : PM +// *Consumed by : HB +// *Level : 2 +/// +/// @todo (to be considered in L2/L3 development) AVSBus timing parameters +/// as attributes or not. They were hardcoded in P8. + +#include <p9_avsbus_lib.H> +#include <p9_avsbus_registers.H> +#include <p9_ocb_firmware_registers.h> + +//############################################################################## +// Function which generates a 3 bit CRC value for 29 bit data +//############################################################################## +uint32_t +avsCRCcalc(const uint32_t i_data) +{ + //Polynomial= x^3 + x^2 + 1 = 1*x^3 + 0*x^2 + 1*x^1 + 1*x^0 = divisor(1011) + + uint32_t l_crc_value = 0; + uint32_t l_polynomial = 0xb0000000; + uint32_t l_msb = 0x80000000; + + l_crc_value = i_data & p9avslib::AVS_CRC_DATA_MASK; + + while (l_crc_value & p9avslib::AVS_CRC_DATA_MASK) + { + if (l_crc_value & l_msb) + { + //if l_msb is 1'b1, divide by l_polynomial and shift l_polynomial + // to the right + l_crc_value = l_crc_value ^ l_polynomial; + l_polynomial = l_polynomial >> 1; + } + else + { + // if l_msb is zero, shift l_polynomial + l_polynomial = l_polynomial >> 1; + } + + l_msb = l_msb >> 1; + } + + return l_crc_value; +} +//############################################################################## + + +//############################################################################## +// Function which initializes the OCB O2S registers +//############################################################################## +fapi2::ReturnCode +avsInitExtVoltageControl(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& + i_target, + const p9avslib::avsBusNum i_avsBusNum, + const uint8_t i_o2sBridgeNum) +{ + + fapi2::buffer<uint64_t> l_data64; + // if using interrupt clear ongoing in OITR1 and OIEPR0 + + FAPI_TRY(putScom(i_target, OCB_OITR1, 0)); //edge + FAPI_TRY(putScom(i_target, OCB_OIEPR0, 0)); + + // O2SCTRLF + // [ 0: 5] o2s_frame_size = 32; -> 0x20 + // [ 6:11] o2s_out_count1 = 32; -> 0x20 + // [12:17] o2s_in_delay1 = 0; No concurrent input + // [18:23] o2s_in_l_count1 = X; No input on first frame + + //uint32_t O2SCTRLF_value = 0b10000010000011111100000000000000; + ocb_o2sctrlf0a_t O2SCTRLF_value; + + O2SCTRLF_value.fields.o2s_frame_size_an = p9avslib::O2S_FRAME_SIZE; + O2SCTRLF_value.fields.o2s_out_count1_an = p9avslib::O2S_FRAME_SIZE; + O2SCTRLF_value.fields.o2s_in_delay1_an = p9avslib::O2S_IN_DELAY1; + + l_data64.insertFromRight<0, 6>(O2SCTRLF_value.fields.o2s_frame_size_an); + l_data64.insertFromRight<6, 6>(O2SCTRLF_value.fields.o2s_out_count1_an); + l_data64.insertFromRight<12, 6>(O2SCTRLF_value.fields.o2s_in_delay1_an); + + FAPI_TRY(putScom(i_target, + p9avslib::OCB_O2SCTRLF[i_avsBusNum][i_o2sBridgeNum], l_data64)); + // Note to self: the buffer is a 32bit buffer. make sure it is left + // aligned for the SCOM + + // O2SCTRLS + // [ 0: 5] o2s_out_count2 = 0; + // [ 6:11] o2s_in_delay2 = 0; + // [12:17] o2s_in_l_count2 = 32; -> 0x20; + + // uint32_t O2SCTRLS_value = 0b00000000000010000000000000000000; + ocb_o2sctrls0a_t O2SCTRLS_value; + O2SCTRLS_value.fields.o2s_in_count2_an = p9avslib::O2S_FRAME_SIZE; + + //O2SCTRLS_value.value = 0b00000000000010000000000000000000; + + l_data64.flush<0>(); + l_data64.insertFromRight<12, 6>(O2SCTRLS_value.fields.o2s_in_count2_an); + + FAPI_TRY(putScom(i_target, + p9avslib::OCB_O2SCTRLS[i_avsBusNum][i_o2sBridgeNum], l_data64)); + + // O2SCTRL2 + // [ 0] o2s_bridge_enable + // [ 1] pmcocr1_reserved_1 + // [ 2] o2s_cpol = 0; Low idle clock + // [ 3] o2s_cpha = 0; First edge + // [ 4:13] o2s_clock_divider = 0xFA Yield 1MHz with 2GHz nest + // [14:16] pmcocr1_reserved_2 + // [ 17] o2s_nr_of_frames = 1; Two frames + // [18:20] o2s_port_enable (only port 0 (18) by default + + // Divider calculation (which can be overwritten) + // Nest Frequency: 2000MHz (0x7D0) + // AVSBus Frequency: 1MHz (0x1) (eg 1us per bit) + // + // Divider = Nest Frequency / (AVSBus Frequency * 8) - 1 + // + // @note: PPE can multiply by a recipricol. A precomputed + // 1 / (AVSBus frequency *8) held in an attribute allows a + // fully l_data64 driven computation without a divide operation. + + + // uint32_t O2SCTRL1_value = 0b10000000000100000100000000000000; + + // uint32_t nest_freq; + // FAPI_ATTR_GET(ATTR_PB_FREQ, &nest_freq); + + ocb_o2sctrl10a_t O2SCTRL1_value; + O2SCTRL1_value.fields.o2s_bridge_enable_an = 1; + O2SCTRL1_value.fields.o2s_clock_divider_an = 0x04;//@todo attr candidate + O2SCTRL1_value.fields.o2s_nr_of_frames_an = 1; + +// O2SCTRL2_value.value = 0b00000000000000000000000000000000; + + l_data64.flush<0>(); + l_data64.insertFromRight<0, 1>(O2SCTRL1_value.fields.o2s_bridge_enable_an); + l_data64.insertFromRight<4, 10>(O2SCTRL1_value.fields.o2s_clock_divider_an); + l_data64.insertFromRight<17, 1>(O2SCTRL1_value.fields.o2s_nr_of_frames_an); + + FAPI_TRY(putScom(i_target, + p9avslib::OCB_O2SCTRL1[i_avsBusNum][i_o2sBridgeNum], l_data64)); + + // O2SCTRL1 + // OCC O2S Control2 + // [ 0:16] o2s_inter_frame_delay = filled in with ATTR l_data64 + // Needs to be 10us or greater for SPIVID part operation + // Set to ~16us for conservatism using a 100ns hang pulse + // 16us = 16000ns -> 16000/100 = 160 = 0xA0; aligned to 0:16 -> 0x005 + ocb_o2sctrl20a_t O2SCTRL2_value; + O2SCTRL2_value.fields.o2s_inter_frame_delay_an = 0x0; + + l_data64.flush<0>(); + l_data64.insertFromRight<0, 17> + (O2SCTRL2_value.fields.o2s_inter_frame_delay_an); + + FAPI_TRY(putScom(i_target, + p9avslib::OCB_O2SCTRL2[i_avsBusNum][i_o2sBridgeNum], l_data64)); + +fapi_try_exit: + return fapi2::current_err; +} +//############################################################################## + + +//############################################################################## +// Function polls OCB status register O2SST for o2s_ongoing=0 +//############################################################################## +fapi2::ReturnCode +avsPollVoltageTransDone(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& + i_target, + const uint8_t i_avsBusNum, + const uint8_t i_o2sBridgeNum) +{ + fapi2::buffer<uint64_t> l_data64; + + uint8_t l_count = 0; + + while (l_count < p9avslib::MAX_POLL_COUNT_AVS) + { + FAPI_TRY(getScom(i_target, p9avslib::OCB_O2SST[i_avsBusNum] + [i_o2sBridgeNum], l_data64), "Error in polling ongoing bit"); + + l_data64 &= 0x8000000000000000ull; + + if (l_data64 == 0) + { + break; // Leave the polling loop as "ongoing" has deasserted + } + + l_count++; + // May put a delay (or sleep) in here to keep off of the OCI bus + } + + // Check for timeout condition + if (l_count >= p9avslib::MAX_POLL_COUNT_AVS) + { + + // @todo L3: Added Timeout FAPI2_SET_RC error point + // This will set current_err to a non success value that can be + // checked by the caller. + + } + +fapi_try_exit: + return fapi2::current_err; +} +//############################################################################## + +//############################################################################## +// Function which outputs a downstream command +//############################################################################## +fapi2::ReturnCode +avsDriveCommand(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint8_t i_avsBusNum, + const uint8_t i_o2sBridgeNum, + const uint32_t i_RailSelect, + const uint32_t i_CmdType, + const uint32_t i_CmdGroup, + const uint32_t i_CmdDataType, + const uint32_t i_CmdData) +{ + + fapi2::buffer<uint64_t> l_data64; + fapi2::buffer<uint32_t> l_data64WithoutCRC; + + fapi2::ReturnCode l_rc; + + uint32_t l_StartCode = 0b01; + uint32_t l_Reserved = 0b000; + uint32_t l_crc; + + // clear sticky bits in o2s_status_reg + // @todo check this register in the EPM code + l_data64.setBit<1, 1>(); + FAPI_TRY(putScom(i_target, + p9avslib::OCB_O2SCMD[i_avsBusNum][i_o2sBridgeNum], l_data64)); + + //unmask pmc_o2s_ongoing in OISR1 + FAPI_TRY(getScom(i_target, OCB_OIMR1, l_data64)); + l_data64 &= p9avslib::OCB_OIMR1_MASK_VALUES[i_avsBusNum][i_o2sBridgeNum]; + FAPI_TRY(putScom(i_target, OCB_OIMR1, l_data64)); + + // @todo: double check on Endianess definition + // compose and send frame + // CRC(31:29), + // l_Reserved(28:13) (read), CmdData(28:13) (write) + // RailSelect(12:9), + // l_CmdDataType(8:5), + // l_CmdGroup(4), + // l_CmdType(3:2), + // l_StartCode(1:0) + l_data64.flush<0>(); + + //l_data64 = l_data64 | + // (l_StartCode << 60) | + // (i_CmdType << 28) | + // (i_CmdGroup << 27) | + // (i_CmdDataType << 23) | + // (i_RailSelect << 19) | + // (l_Reserved << 3); + l_data64.insertFromRight<0, 2>(l_StartCode); + l_data64.insertFromRight<2, 2>(i_CmdType); + l_data64.insertFromRight<4, 1>(i_CmdGroup); + l_data64.insertFromRight<5, 4>(i_CmdDataType); + l_data64.insertFromRight<9, 4>(i_RailSelect); + l_data64.insertFromRight<13, 16>(i_CmdData); + l_data64.insertFromRight<29, 3>(l_Reserved); + + l_data64.extract(l_data64WithoutCRC, 0, 32); + + // generate CRC + l_crc = avsCRCcalc(l_data64WithoutCRC); + + l_data64.insertFromRight<29, 3>(l_crc); + FAPI_TRY(putScom(i_target, + p9avslib::OCB_O2SWD[i_avsBusNum][i_o2sBridgeNum], l_data64)); + + // Wait on o2s_ongoing = 0 + FAPI_TRY(avsPollVoltageTransDone(i_target, i_avsBusNum, i_o2sBridgeNum)); + // Note: caller will check for the specific timeout return code. + +fapi_try_exit: + return fapi2::current_err; +} + +//############################################################################## +// Function which writes to OCB registers to initiate a AVS read transaction +//############################################################################## +fapi2::ReturnCode +avsVoltageRead(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint8_t i_avsBusNum, + const uint8_t i_o2sBridgeNum, + const uint32_t i_RailSelect, + uint32_t* o_Voltage) +{ + + fapi2::buffer<uint64_t> l_data64; + + uint32_t l_CmdType = 3; // read + uint32_t l_CmdGroup = 0; + uint32_t l_CmdDataType = 0; + uint32_t l_outboundCmdData = 0; // @todo check the spec on this for a read + + // Drive a Read Command + FAPI_TRY(avsDriveCommand(i_target, + i_avsBusNum, + i_o2sBridgeNum, + i_RailSelect, + l_CmdType, + l_CmdGroup, + l_CmdDataType, + l_outboundCmdData)); + + // Read returned voltage value from Read frame + FAPI_TRY(putScom(i_target, + p9avslib::OCB_O2SRD[i_avsBusNum][i_o2sBridgeNum], l_data64)); + *o_Voltage = ((l_data64 >> 8) & 0x0000FFFF) >> 32; + + // @todo L3 insert SET_HWP_RC macro with FFDC + // FFDC: + // i_avsBusNum + // i_o2sBridgeNum, + // i_RailSelect, + // l_CmdType, + // l_CmdGroup + // l_CmdDataType + // O2S Registers (need to create in XML + +fapi_try_exit: + return fapi2::current_err; +} +//############################################################################## + +//############################################################################## +// Function which writes to OCB registers to initiate a AVS write transaction +//############################################################################## +fapi2::ReturnCode +avsVoltageWrite(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint8_t i_avsBusNum, + const uint8_t i_o2sBridgeNum, + const uint32_t i_RailSelect, + const uint32_t i_Voltage) +{ + + uint32_t l_CmdType = 0; // write and commit + uint32_t l_CmdGroup = 0; + uint32_t l_CmdDataType = 0; + + // Drive a Write Command + FAPI_TRY(avsDriveCommand(i_target, + i_avsBusNum, + i_o2sBridgeNum, + i_RailSelect, + l_CmdType, + l_CmdGroup, + l_CmdDataType, + i_Voltage)); // @todo command data flow + + // @todo L3 insert SET_HWP_RC macro with FFDC + // FFDC: + // i_avsBusNum + // i_o2sBridgeNum, + // i_RailSelect, + // l_CmdType, + // l_CmdGroup + // l_CmdDataType + // O2S Registers (need to create in XML) + +fapi_try_exit: + return fapi2::current_err; +} +//############################################################################## + + +//############################################################################## +// Function which writes to OCB registers to initialize the AVS Slave with an +// idle frame +//############################################################################## +fapi2::ReturnCode +avsIdleFrame(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint8_t i_avsBusNum, + const uint8_t i_o2sBridgeNum) +{ + fapi2::buffer<uint64_t> l_idleframe = 0xFFFFFFFF00000000ull; + fapi2::buffer<uint64_t> l_scomdata; + + // clear sticky bits in o2s_status_reg + l_scomdata.setBit<1, 1>(); + FAPI_TRY(putScom(i_target, + p9avslib::OCB_O2SCMD[i_avsBusNum][i_o2sBridgeNum], + l_scomdata), + "Error clearing sticky bits in o2s_status_reg"); + + //unmask pmc_o2s_ongoing in OISR1 + FAPI_TRY(getScom(i_target, OCB_OIMR1, l_scomdata)); + l_scomdata &= p9avslib::OCB_OIMR1_MASK_VALUES[i_avsBusNum][i_o2sBridgeNum]; + FAPI_TRY(putScom(i_target, OCB_OIMR1, l_scomdata)); + + // Send the idle frame + l_scomdata = l_idleframe << 32; + FAPI_TRY(putScom(i_target, + p9avslib::OCB_O2SWD[i_avsBusNum][i_o2sBridgeNum], l_scomdata)); + + // Wait on o2s_ongoing = 0 + FAPI_TRY(avsPollVoltageTransDone(i_target, i_avsBusNum, i_o2sBridgeNum)); + + // @todo L3 insert SET_HWP_RC macro with FFDC + // FFDC: + // i_avsBusNum + // i_o2sBridgeNum, + // i_RailSelect, + // l_CmdType, + // l_CmdGroup + // l_CmdDataType + // O2S Registers (need to create in XML + +fapi_try_exit: + return fapi2::current_err; +} +//############################################################################## diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_avsbus_lib.H b/src/import/chips/p9/procedures/hwp/lib/p9_avsbus_lib.H new file mode 100644 index 000000000..97878bc33 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/p9_avsbus_lib.H @@ -0,0 +1,260 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/lib/p9_avsbus_lib.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file p9_avsbus_lib.H +/// @brief Library functions for AVSBus +/// +/// *HW Owner : Sudheendra K Srivathsa <sudheendraks@in.ibm.com> +/// *FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *Team : PM +/// *Consumed by : HB +/// *Level : 2 +/// +/// @todo (to be considered in L2/L3 development) AVSBus timing parameters +/// as attributes or not. They were hardcoded in P8. + +#ifndef __P9_AVSBUS_LIB_H__ +#define __P9_AVSBUS_LIB_H__ + +#include <fapi2.H> + +namespace p9avslib +{ +enum avsRails +{ + VDD, + VDN, + VCS +}; + +enum avsBusNum +{ + AVSBUSVDD = 0, + AVSBUSVDN = 1, + AVSBUSVCS = 0 +}; + +union avsMasterFrame +{ + uint32_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t StartCode : 2; + uint32_t Cmd : 2; + uint32_t CmdGroup : 1; + uint32_t CmdDataType: 4; + uint32_t Select : 4; + uint32_t CmdData : 16; + uint32_t CRC : 3; +#else + uint32_t CRC : 3; + uint32_t CmdData : 16; + uint32_t Select : 4; + uint32_t CmdDataType: 4; + uint32_t CmdGroup : 1; + uint32_t Cmd : 2; + uint32_t StartCode : 2; +#endif // _BIG_ENDIAN + } fields; +}; + +union avsSlaveFrame +{ + uint32_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t SlaveAck : 2; + uint32_t reserved1 : 1; + uint32_t StatusResp : 5; + uint32_t CmdData : 16; + uint32_t reserved5 : 5; + uint32_t CRC : 3; +#else + uint32_t CRC : 3; + uint32_t reserved5 : 5; + uint32_t CmdData : 16; + uint32_t StatusResp : 5; + uint32_t reserved1 : 1; + uint32_t SlaveAck : 2; +#endif // _BIG_ENDIAN + + } fields; +}; + +union avsStatus +{ + uint16_t value; + struct + { +#ifdef _BIG_ENDIAN + uint16_t VDone : 1; // Voltage done + uint16_t OCW : 1; // IOUT_OC_WARNING (Output over-current) + uint16_t UCW : 1; // VOUT_UV_WARNING (Output under-voltage) + uint16_t OTW : 1; // IOUT_OT_WARNING (Over-temperature) + uint16_t OPW : 1; // POUT_OP_WARNING (Output over-power) + uint16_t Reserved_3 : 3; + uint16_t MfrSpcfc_8 : 8; // Mfg Specific defined by the AVSBus Slave +#else + uint16_t MfrSpcfc_8 : 8; // Mfg Specific defined by the AVSBus Slave + uint16_t Reserved_3 : 3; + uint16_t OPW : 1; // POUT_OP_WARNING (Output over-power) + uint16_t OTW : 1; // IOUT_OT_WARNING (Over-temperature) + uint16_t UCW : 1; // VOUT_UV_WARNING (Output under-voltage) + uint16_t OCW : 1; // IOUT_OC_WARNING (Output over-current) + uint16_t VDone : 1; // Voltage done +#endif // _BIG_ENDIAN + } fields; +}; + +enum avslibconstants +{ + +// @todo: This should be calculated based on time (eg 100ms) and the projected +// time that a SCOM poll will take. +// const uint32_t MAX_POLL_COUNT_AVS = 0x1000; + MAX_POLL_COUNT_AVS = 0x1000, + AVS_CRC_DATA_MASK = 0xfffffff8, + O2S_FRAME_SIZE = 0x20, + O2S_IN_DELAY1 = 0x3F + +}; + +// Constant definitions +//const uint64_t O2S_FRAME_SIZE = 0x20; + +// OIMR Mask Values +const uint32_t OCB_OIMR1_MASK_VALUES[2][2] = +{ + 0xFFFFFBFF, //bit 21 + 0xFFFFFCFF, //bit 22 + 0xFFFFFBFF, //bit 23 + 0xFFFFFEFF //bit 24 +}; + +//const uint64_t OCB_O2SST_MASK = 0x8000000000000000; + +} //end of p9avslib namespace + +///@brief Generates a 3 bit CRC value for 29 bit data +///@param[i] i_data +///@return 3 bit CRC result (right aligned) + +uint32_t avsCRCcalc(uint32_t i_data); + + + +///@brief Initialize an O2S bridge for AVSBus usage +///@param[i] i_target Chip target +///@param[i] i_avsBusNum AVSBus Number (0 or 1) +///@param[i] i_o2sBridgeNum O2S Bridge Number (0 or 1) +///@return FAPI2::ReturnCode defined in XML + +fapi2::ReturnCode +avsInitExtVoltageControl(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const p9avslib::avsBusNum i_avsBusNum, + const uint8_t i_o2sBridgeNum); + + +///@brief Polls OCB status register O2SST for o2s_ongoing=0 +///@param[i] i_target Chip target +///@param[i] i_avsBusNum AVSBus Number (0 or 1) +///@param[i] i_o2sBridgeNum O2S Bridge Number (0 or 1) +///@return FAPI2::SUCCESS +///@return FAPI2::RC_PROCPM_AVSBUS_TIMEOUT + +fapi2::ReturnCode +avsPollVoltageTransDone(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint8_t i_avsBusNum, + const uint8_t i_o2sBridgeNum); + + + +///@brief Drives a downstream command to a select bus via a selected bridge +///@param[i] i_target Chip target +///@param[i] i_avsBusNum AVSBus Number (0 or 1) +///@param[i] i_o2sBridgeNum O2S Bridge Number (0 or 1) +///@param[i] i_RailSelect Rail Select (value depends on the system implementation) +///@param[i] i_CmdType Defined by AVSBus spec (4b, right justified) +///@param[i] i_CmdGroup Defined by AVSBus spec (0 = AVSBus defined; 1 = Mfg defined) +///@param[i] i_CmdData Defined by AVSBus spec and command dependent (16b, right justified) +///@return FAPI2::SUCCESS +///@return FAPI2::RC_PROCPM_AVSBUS_TIMEOUT + +fapi2::ReturnCode +avsDriveCommand(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint8_t i_avsBusNum, + const uint8_t i_o2sBridgeNum, + const uint32_t i_RailSelect, + const uint32_t i_CmdType, + const uint32_t i_CmdGroup, + const uint32_t i_CmdDataType, + const uint32_t i_CmdData); + + + +///@brief Perform an AVS read transaction +///@param[i] i_target Chip target +///@param[i] i_avsBusNum AVSBus Number (0 or 1) +///@param[i] i_o2sBridgeNum O2S Bridge Number (0 or 1) +///@param[i] i_RailSelect Rail Select (value depends on the system implementation) +///@param[o] o_CmdData Defined by AVSBus spec and command dependent (16b, right justified) +///@return FAPI2::SUCCESS +///@return FAPI2::RC_PROCPM_AVSBUS_TIMEOUT + +fapi2::ReturnCode +avsVoltageRead(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint8_t i_avsBusNum, + const uint8_t i_o2sBridgeNum, + const uint32_t i_RailSelect, + uint32_t* o_Voltage); + + +///@brief Perform an AVS write transaction +///@param[i] i_target Chip target +///@param[i] i_avsBusNum AVSBus Number (0 or 1) +///@param[i] i_o2sBridgeNum O2S Bridge Number (0 or 1) +///@param[i] i_RailSelect Rail Select (value depends on the system implementation) +///@param[i] i_CmdData Defined by AVSBus spec and command dependent (16b, right justified) +///@return FAPI2::SUCCESS +///@return FAPI2::RC_PROCPM_AVSBUS_TIMEOUT + +fapi2::ReturnCode +avsVoltageWrite(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint8_t i_avsBusNum, + const uint8_t i_o2sBridgeNum, + const uint32_t i_RailSelect, + const uint32_t o_Voltage); + + +///@brief Drive an Idle Frame on an AVSBus +///@param[i] i_target Chip target +///@param[i] i_avsBusNum AVSBus Number (0 or 1) +///@param[i] i_o2sBridgeNum O2S Bridge Number (0 or 1) +///@return FAPI2::SUCCESS + +fapi2::ReturnCode +avsIdleFrame(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint8_t i_avsBusNum, + const uint8_t i_o2sBridgeNum); + + +#endif // __P9_AVSBUS_LIB_H__ diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_avsbus_lib.mk b/src/import/chips/p9/procedures/hwp/lib/p9_avsbus_lib.mk new file mode 100644 index 000000000..566bbbf4f --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/p9_avsbus_lib.mk @@ -0,0 +1,22 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: chips/p9/procedures/hwp/lib/p9_avsbus_lib.mk $ +# +# IBM CONFIDENTIAL +# +# EKB Project +# +# COPYRIGHT 2015,2016 +# [+] International Business Machines Corp. +# +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# IBM_PROLOG_END_TAG +MODULE=p9_avsbus_lib +$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(PROJECT_ROOT)/chips/p9/procedures/hwp/pm/include/registers) +#p9_avsbus_lib_PATH+=$(PROJECT_ROOT)/chips/p9/procedures/hwp/lib +$(call BUILD_MODULE) diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_avsbus_registers.H b/src/import/chips/p9/procedures/hwp/lib/p9_avsbus_registers.H new file mode 100644 index 000000000..9c7726770 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/p9_avsbus_registers.H @@ -0,0 +1,32 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/lib/p9_avsbus_registers.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file p9_avsbus_registers.H +/// @brief Include of the relevent register header based on the platform +/// +// *HW Owner : Sudheendra K Srivathsa <sudheendraks@in.ibm.com> +// *FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *Team : PM +// *Consumed by : HB +// *Level : 2 +/// + +// Include SCOM address header file +#include <p9_avsbus_scom.H> diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_avsbus_scom.H b/src/import/chips/p9/procedures/hwp/lib/p9_avsbus_scom.H new file mode 100644 index 000000000..c72183816 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/p9_avsbus_scom.H @@ -0,0 +1,175 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/lib/p9_avsbus_scom.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file p9_avsbus_scom.H +/// @brief Specific elements for AVSBus access via SCOM +/// +// *HW Owner : Sudheendra K Srivathsa <sudheendraks@in.ibm.com> +// *FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *Team : PM +// *Consumed by : HB +// *Level : 2 +/// + +#include <p9_misc_scom_addresses.H> + +#ifndef __P9_AVSBUS_SCOM_H__ +#define __P9_AVSBUS_SCOM_H__ + +namespace p9avslib +{ +//#define OCB_OCI_BASE PU_OCB_OCI_OCI_BASE +#define OCB_OISR0 PU_OCB_OCI_OISR0_SCOM +#define OCB_OISR0_CLR PU_OCB_OCI_OISR0_SCOM1 +#define OCB_OISR0_OR PU_OCB_OCI_OISR0_SCOM2 +#define OCB_OIMR0 PU_OCB_OCI_OIMR0_SCOM +#define OCB_OIMR0_CLR PU_OCB_OCI_OIMR0_SCOM1 +#define OCB_OIMR0_OR PU_OCB_OCI_OIMR0_SCOM2 +#define OCB_OITR0 PU_OCB_OCI_OITR0_SCOM +#define OCB_OITR0_CLR PU_OCB_OCI_OITR0_SCOM1 +#define OCB_OITR0_OR PU_OCB_OCI_OITR0_SCOM2 +#define OCB_OIEPR0 PU_OCB_OCI_OIEPR0_SCOM +#define OCB_OIEPR0_CLR PU_OCB_OCI_OIEPR0_SCOM1 +#define OCB_OIEPR0_OR PU_OCB_OCI_OIEPR0_SCOM2 +#define OCB_OISR1 PU_OCB_OCI_OISR1_SCOM +#define OCB_OISR1_CLR PU_OCB_OCI_OISR1_SCOM1 +#define OCB_OISR1_OR PU_OCB_OCI_OISR1_SCOM2 +#define OCB_OIMR1 PU_OCB_OCI_OIMR1_SCOM +#define OCB_OIMR1_CLR PU_OCB_OCI_OIMR1_SCOM1 +#define OCB_OIMR1_OR PU_OCB_OCI_OIMR1_SCOM2 +#define OCB_OITR1 PU_OCB_OCI_OITR1_SCOM +#define OCB_OITR1_CLR PU_OCB_OCI_OITR1_SCOM1 +#define OCB_OITR1_OR PU_OCB_OCI_OITR1_SCOM2 +#define OCB_OIEPR1 PU_OCB_OCI_OIEPR1_SCOM +#define OCB_OIEPR1_CLR PU_OCB_OCI_OIEPR1_SCOM1 +#define OCB_OIEPR1_OR PU_OCB_OCI_OIEPR1_SCOM2 + +/// Need SCOM SBE, HB, PHYP or OPAL accesses + +#define OCB_O2SCTRLF0A PU_OCB_OCI_O2SCTRLF0A_SCOM +#define OCB_O2SCTRLS0A PU_OCB_OCI_O2SCTRLS0A_SCOM +#define OCB_O2SCTRL10A PU_OCB_OCI_O2SCTRL10A_SCOM +#define OCB_O2SCTRL20A PU_OCB_OCI_O2SCTRL20A_SCOM +#define OCB_O2SST0A PU_OCB_OCI_O2SST0A_SCOM +#define OCB_O2SCMD0A PU_OCB_OCI_O2SCMD0A_SCOM +#define OCB_O2SWD0A PU_OCB_OCI_O2SWD0A_SCOM +#define OCB_O2SRD0A PU_OCB_OCI_O2SRD0A_SCOM +#define OCB_O2SCTRLF0B PU_OCB_OCI_O2SCTRLF0B_SCOM +#define OCB_O2SCTRLS0B PU_OCB_OCI_O2SCTRLS0B_SCOM +#define OCB_O2SCTRL10B PU_OCB_OCI_O2SCTRL10B_SCOM +#define OCB_O2SCTRL20B PU_OCB_OCI_O2SCTRL20B_SCOM +#define OCB_O2SST0B PU_OCB_OCI_O2SST0B_SCOM +#define OCB_O2SCMD0B PU_OCB_OCI_O2SCMD0B_SCOM +#define OCB_O2SWD0B PU_OCB_OCI_O2SWD0B_SCOM +#define OCB_O2SRD0B PU_OCB_OCI_O2SRD0B_SCOM +#define OCB_O2SCTRLF1A PU_OCB_OCI_O2SCTRLF1A_SCOM +#define OCB_O2SCTRLS1A PU_OCB_OCI_O2SCTRLS1A_SCOM +#define OCB_O2SCTRL11A PU_OCB_OCI_O2SCTRL11A_SCOM +#define OCB_O2SCTRL21A PU_OCB_OCI_O2SCTRL21A_SCOM +#define OCB_O2SST1A PU_OCB_OCI_O2SST1A_SCOM +#define OCB_O2SCMD1A PU_OCB_OCI_O2SCMD1A_SCOM +#define OCB_O2SWD1A PU_OCB_OCI_O2SWD1A_SCOM +#define OCB_O2SRD1A PU_OCB_OCI_O2SRD1A_SCOM +#define OCB_O2SCTRLF1B PU_OCB_OCI_O2SCTRLF1B_SCOM +#define OCB_O2SCTRLS1B PU_OCB_OCI_O2SCTRLS1B_SCOM +#define OCB_O2SCTRL11B PU_OCB_OCI_O2SCTRL11B_SCOM +#define OCB_O2SCTRL21B PU_OCB_OCI_O2SCTRL21B_SCOM +#define OCB_O2SST1B PU_OCB_OCI_O2SST1B_SCOM +#define OCB_O2SCMD1B PU_OCB_OCI_O2SCMD1B_SCOM +#define OCB_O2SWD1B PU_OCB_OCI_O2SWD1B_SCOM +#define OCB_O2SRD1B PU_OCB_OCI_O2SRD1B_SCOM + + +//#define OCB_O2SRD1B + +// O2S Control Frame Registers +const uint32_t OCB_O2SCTRLF[2][2] = +{ + OCB_O2SCTRLF0A, + OCB_O2SCTRLF0B, + OCB_O2SCTRLF1A, + OCB_O2SCTRLF1B +}; + +// O2S Control Status Registers +const uint32_t OCB_O2SCTRLS[2][2] = +{ + OCB_O2SCTRLS0A, + OCB_O2SCTRLS0B, + OCB_O2SCTRLS1A, + OCB_O2SCTRLS1B +}; + +// O2S Control 1 Registers +const uint32_t OCB_O2SCTRL1[2][2] = +{ + OCB_O2SCTRL10A, + OCB_O2SCTRL10B, + OCB_O2SCTRL11A, + OCB_O2SCTRL11B +}; + +// O2S Control 2 Registers +const uint32_t OCB_O2SCTRL2[2][2] = +{ + OCB_O2SCTRL20A, + OCB_O2SCTRL20B, + OCB_O2SCTRL21A, + OCB_O2SCTRL21B +}; + +// O2S Status Registers +const uint32_t OCB_O2SST[2][2] = +{ + OCB_O2SST0A, + OCB_O2SST0B, + OCB_O2SST1A, + OCB_O2SST1B +}; + +// O2S Command Registers +const uint32_t OCB_O2SCMD[2][2] = +{ + OCB_O2SCMD0A, + OCB_O2SCMD0B, + OCB_O2SCMD1A, + OCB_O2SCMD1B +}; + +// O2S Write Data Registers +const uint32_t OCB_O2SWD[2][2] = +{ + OCB_O2SWD0A, + OCB_O2SWD0B, + OCB_O2SWD1A, + OCB_O2SWD1B +}; + +// O2S Read Data Registers +const uint32_t OCB_O2SRD[2][2] = +{ + OCB_O2SRD0A, + OCB_O2SRD0B, + OCB_O2SRD1A, + OCB_O2SRD1A +}; + +} //end of p9avslib namespace +#endif // __P9_AVSBUS_SCOM_H__ diff --git a/src/import/chips/p9/procedures/hwp/pm/include/registers/p9_ocb_firmware_registers.h b/src/import/chips/p9/procedures/hwp/pm/include/registers/p9_ocb_firmware_registers.h new file mode 100755 index 000000000..e6ef07dce --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/pm/include/registers/p9_ocb_firmware_registers.h @@ -0,0 +1,7347 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/pm/include/registers/p9_ocb_firmware_registers.h $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef P9_OCB_FIRMWARE_REGISTERS_H__ +#define P9_OCB_FIRMWARE_REGISTERS_H__ + +// $Id$ +// $Source$ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2015 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file ocb_firmware_registers.h +/// \brief C register structs for the OCB unit + +// *** WARNING *** - This file is generated automatically, do not edit. + +#ifndef SIXTYFOUR_BIT_CONSTANT + #ifdef __ASSEMBLER__ + #define SIXTYFOUR_BIT_CONSTANT(x) x + #else + #define SIXTYFOUR_BIT_CONSTANT(x) x##ull + #endif +#endif + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + + + + +typedef union ocb_oisr0 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t debugger : 1; + uint64_t trace_trigger : 1; + uint64_t occ_error : 1; + uint64_t pba_error : 1; + uint64_t srt_error : 1; + uint64_t gpe0_error : 1; + uint64_t gpe1_error : 1; + uint64_t gpe2_error : 1; + uint64_t gpe3_error : 1; + uint64_t ppc405_halt : 1; + uint64_t ocb_error : 1; + uint64_t spipss_error : 1; + uint64_t check_stop_ppc405 : 1; + uint64_t check_stop_gpe0 : 1; + uint64_t check_stop_gpe1 : 1; + uint64_t check_stop_gpe2 : 1; + uint64_t check_stop_gpe3 : 1; + uint64_t occ_malf_alert : 1; + uint64_t adu_malf_alert : 1; + uint64_t external_trap : 1; + uint64_t ivrm_pvref_error : 1; + uint64_t occ_timer0 : 1; + uint64_t occ_timer1 : 1; + uint64_t avs_slave0 : 1; + uint64_t avs_slave1 : 1; + uint64_t ipi0_hi_priority : 1; + uint64_t ipi1_hi_priority : 1; + uint64_t ipi2_hi_priority : 1; + uint64_t ipi3_hi_priority : 1; + uint64_t ipi4_hi_priority : 1; + uint64_t adcfsm_ongoing : 1; + uint64_t spare_31 : 1; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t spare_31 : 1; + uint64_t adcfsm_ongoing : 1; + uint64_t ipi4_hi_priority : 1; + uint64_t ipi3_hi_priority : 1; + uint64_t ipi2_hi_priority : 1; + uint64_t ipi1_hi_priority : 1; + uint64_t ipi0_hi_priority : 1; + uint64_t avs_slave1 : 1; + uint64_t avs_slave0 : 1; + uint64_t occ_timer1 : 1; + uint64_t occ_timer0 : 1; + uint64_t ivrm_pvref_error : 1; + uint64_t external_trap : 1; + uint64_t adu_malf_alert : 1; + uint64_t occ_malf_alert : 1; + uint64_t check_stop_gpe3 : 1; + uint64_t check_stop_gpe2 : 1; + uint64_t check_stop_gpe1 : 1; + uint64_t check_stop_gpe0 : 1; + uint64_t check_stop_ppc405 : 1; + uint64_t spipss_error : 1; + uint64_t ocb_error : 1; + uint64_t ppc405_halt : 1; + uint64_t gpe3_error : 1; + uint64_t gpe2_error : 1; + uint64_t gpe1_error : 1; + uint64_t gpe0_error : 1; + uint64_t srt_error : 1; + uint64_t pba_error : 1; + uint64_t occ_error : 1; + uint64_t trace_trigger : 1; + uint64_t debugger : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_oisr0_t; + + + +typedef union ocb_oisr0_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t debugger : 1; + uint64_t trace_trigger : 1; + uint64_t occ_error : 1; + uint64_t pba_error : 1; + uint64_t srt_error : 1; + uint64_t gpe0_error : 1; + uint64_t gpe1_error : 1; + uint64_t gpe2_error : 1; + uint64_t gpe3_error : 1; + uint64_t ppc405_halt : 1; + uint64_t ocb_error : 1; + uint64_t spipss_error : 1; + uint64_t check_stop_ppc405 : 1; + uint64_t check_stop_gpe0 : 1; + uint64_t check_stop_gpe1 : 1; + uint64_t check_stop_gpe2 : 1; + uint64_t check_stop_gpe3 : 1; + uint64_t occ_malf_alert : 1; + uint64_t adu_malf_alert : 1; + uint64_t external_trap : 1; + uint64_t ivrm_pvref_error : 1; + uint64_t occ_timer0 : 1; + uint64_t occ_timer1 : 1; + uint64_t avs_slave0 : 1; + uint64_t avs_slave1 : 1; + uint64_t ipi0_hi_priority : 1; + uint64_t ipi1_hi_priority : 1; + uint64_t ipi2_hi_priority : 1; + uint64_t ipi3_hi_priority : 1; + uint64_t ipi4_hi_priority : 1; + uint64_t adcfsm_ongoing : 1; + uint64_t spare_31 : 1; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t spare_31 : 1; + uint64_t adcfsm_ongoing : 1; + uint64_t ipi4_hi_priority : 1; + uint64_t ipi3_hi_priority : 1; + uint64_t ipi2_hi_priority : 1; + uint64_t ipi1_hi_priority : 1; + uint64_t ipi0_hi_priority : 1; + uint64_t avs_slave1 : 1; + uint64_t avs_slave0 : 1; + uint64_t occ_timer1 : 1; + uint64_t occ_timer0 : 1; + uint64_t ivrm_pvref_error : 1; + uint64_t external_trap : 1; + uint64_t adu_malf_alert : 1; + uint64_t occ_malf_alert : 1; + uint64_t check_stop_gpe3 : 1; + uint64_t check_stop_gpe2 : 1; + uint64_t check_stop_gpe1 : 1; + uint64_t check_stop_gpe0 : 1; + uint64_t check_stop_ppc405 : 1; + uint64_t spipss_error : 1; + uint64_t ocb_error : 1; + uint64_t ppc405_halt : 1; + uint64_t gpe3_error : 1; + uint64_t gpe2_error : 1; + uint64_t gpe1_error : 1; + uint64_t gpe0_error : 1; + uint64_t srt_error : 1; + uint64_t pba_error : 1; + uint64_t occ_error : 1; + uint64_t trace_trigger : 1; + uint64_t debugger : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_oisr0_clr_t; + + + +typedef union ocb_oisr0_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t debugger : 1; + uint64_t trace_trigger : 1; + uint64_t occ_error : 1; + uint64_t pba_error : 1; + uint64_t srt_error : 1; + uint64_t gpe0_error : 1; + uint64_t gpe1_error : 1; + uint64_t gpe2_error : 1; + uint64_t gpe3_error : 1; + uint64_t ppc405_halt : 1; + uint64_t ocb_error : 1; + uint64_t spipss_error : 1; + uint64_t check_stop_ppc405 : 1; + uint64_t check_stop_gpe0 : 1; + uint64_t check_stop_gpe1 : 1; + uint64_t check_stop_gpe2 : 1; + uint64_t check_stop_gpe3 : 1; + uint64_t occ_malf_alert : 1; + uint64_t adu_malf_alert : 1; + uint64_t external_trap : 1; + uint64_t ivrm_pvref_error : 1; + uint64_t occ_timer0 : 1; + uint64_t occ_timer1 : 1; + uint64_t avs_slave0 : 1; + uint64_t avs_slave1 : 1; + uint64_t ipi0_hi_priority : 1; + uint64_t ipi1_hi_priority : 1; + uint64_t ipi2_hi_priority : 1; + uint64_t ipi3_hi_priority : 1; + uint64_t ipi4_hi_priority : 1; + uint64_t adcfsm_ongoing : 1; + uint64_t spare_31 : 1; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t spare_31 : 1; + uint64_t adcfsm_ongoing : 1; + uint64_t ipi4_hi_priority : 1; + uint64_t ipi3_hi_priority : 1; + uint64_t ipi2_hi_priority : 1; + uint64_t ipi1_hi_priority : 1; + uint64_t ipi0_hi_priority : 1; + uint64_t avs_slave1 : 1; + uint64_t avs_slave0 : 1; + uint64_t occ_timer1 : 1; + uint64_t occ_timer0 : 1; + uint64_t ivrm_pvref_error : 1; + uint64_t external_trap : 1; + uint64_t adu_malf_alert : 1; + uint64_t occ_malf_alert : 1; + uint64_t check_stop_gpe3 : 1; + uint64_t check_stop_gpe2 : 1; + uint64_t check_stop_gpe1 : 1; + uint64_t check_stop_gpe0 : 1; + uint64_t check_stop_ppc405 : 1; + uint64_t spipss_error : 1; + uint64_t ocb_error : 1; + uint64_t ppc405_halt : 1; + uint64_t gpe3_error : 1; + uint64_t gpe2_error : 1; + uint64_t gpe1_error : 1; + uint64_t gpe0_error : 1; + uint64_t srt_error : 1; + uint64_t pba_error : 1; + uint64_t occ_error : 1; + uint64_t trace_trigger : 1; + uint64_t debugger : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_oisr0_or_t; + + + +typedef union ocb_oimr0 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_mask_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_mask_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oimr0_t; + + + +typedef union ocb_oimr0_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_mask_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_mask_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oimr0_clr_t; + + + +typedef union ocb_oimr0_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_mask_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_mask_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oimr0_or_t; + + + +typedef union ocb_oitr0 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_type_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_type_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oitr0_t; + + + +typedef union ocb_oitr0_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_type_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_type_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oitr0_clr_t; + + + +typedef union ocb_oitr0_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_type_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_type_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oitr0_or_t; + + + +typedef union ocb_oiepr0 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_edge_pol_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_edge_pol_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oiepr0_t; + + + +typedef union ocb_oiepr0_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_edge_pol_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_edge_pol_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oiepr0_clr_t; + + + +typedef union ocb_oiepr0_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_edge_pol_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_edge_pol_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oiepr0_or_t; + + + +typedef union ocb_oisr1 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t pbax_occ_send : 1; + uint64_t pbax_occ_push0 : 1; + uint64_t pbax_occ_push1 : 1; + uint64_t pba_bcde_attn : 1; + uint64_t pba_bcue_attn : 1; + uint64_t occ_strm0_pull : 1; + uint64_t occ_strm0_push : 1; + uint64_t occ_strm1_pull : 1; + uint64_t occ_strm1_push : 1; + uint64_t occ_strm2_pull : 1; + uint64_t occ_strm2_push : 1; + uint64_t occ_strm3_pull : 1; + uint64_t occ_strm3_push : 1; + uint64_t pmc_pcb_intr_type0_pending : 1; + uint64_t pmc_pcb_intr_type1_pending : 1; + uint64_t pmc_pcb_intr_type2_pending : 1; + uint64_t pmc_pcb_intr_type3_pending : 1; + uint64_t pmc_pcb_intr_type4_pending : 1; + uint64_t pmc_pcb_intr_type5_pending : 1; + uint64_t pmc_pcb_intr_type6_pending : 1; + uint64_t pmc_pcb_intr_type7_pending : 1; + uint64_t pmc_o2s_0a_ongoing : 1; + uint64_t pmc_o2s_0b_ongoing : 1; + uint64_t pmc_o2s_1a_ongoing : 1; + uint64_t pmc_o2s_1b_ongoing : 1; + uint64_t pssbridge_ongoing : 1; + uint64_t ipi0_lo_priority : 1; + uint64_t ipi1_lo_priority : 1; + uint64_t ipi2_lo_priority : 1; + uint64_t ipi3_lo_priority : 1; + uint64_t ipi4_lo_priority : 1; + uint64_t spare_31 : 1; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t spare_31 : 1; + uint64_t ipi4_lo_priority : 1; + uint64_t ipi3_lo_priority : 1; + uint64_t ipi2_lo_priority : 1; + uint64_t ipi1_lo_priority : 1; + uint64_t ipi0_lo_priority : 1; + uint64_t pssbridge_ongoing : 1; + uint64_t pmc_o2s_1b_ongoing : 1; + uint64_t pmc_o2s_1a_ongoing : 1; + uint64_t pmc_o2s_0b_ongoing : 1; + uint64_t pmc_o2s_0a_ongoing : 1; + uint64_t pmc_pcb_intr_type7_pending : 1; + uint64_t pmc_pcb_intr_type6_pending : 1; + uint64_t pmc_pcb_intr_type5_pending : 1; + uint64_t pmc_pcb_intr_type4_pending : 1; + uint64_t pmc_pcb_intr_type3_pending : 1; + uint64_t pmc_pcb_intr_type2_pending : 1; + uint64_t pmc_pcb_intr_type1_pending : 1; + uint64_t pmc_pcb_intr_type0_pending : 1; + uint64_t occ_strm3_push : 1; + uint64_t occ_strm3_pull : 1; + uint64_t occ_strm2_push : 1; + uint64_t occ_strm2_pull : 1; + uint64_t occ_strm1_push : 1; + uint64_t occ_strm1_pull : 1; + uint64_t occ_strm0_push : 1; + uint64_t occ_strm0_pull : 1; + uint64_t pba_bcue_attn : 1; + uint64_t pba_bcde_attn : 1; + uint64_t pbax_occ_push1 : 1; + uint64_t pbax_occ_push0 : 1; + uint64_t pbax_occ_send : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_oisr1_t; + + + +typedef union ocb_oisr1_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t pbax_occ_send : 1; + uint64_t pbax_occ_push0 : 1; + uint64_t pbax_occ_push1 : 1; + uint64_t pba_bcde_attn : 1; + uint64_t pba_bcue_attn : 1; + uint64_t occ_strm0_pull : 1; + uint64_t occ_strm0_push : 1; + uint64_t occ_strm1_pull : 1; + uint64_t occ_strm1_push : 1; + uint64_t occ_strm2_pull : 1; + uint64_t occ_strm2_push : 1; + uint64_t occ_strm3_pull : 1; + uint64_t occ_strm3_push : 1; + uint64_t pmc_pcb_intr_type0_pending : 1; + uint64_t pmc_pcb_intr_type1_pending : 1; + uint64_t pmc_pcb_intr_type2_pending : 1; + uint64_t pmc_pcb_intr_type3_pending : 1; + uint64_t pmc_pcb_intr_type4_pending : 1; + uint64_t pmc_pcb_intr_type5_pending : 1; + uint64_t pmc_pcb_intr_type6_pending : 1; + uint64_t pmc_pcb_intr_type7_pending : 1; + uint64_t pmc_o2s_0a_ongoing : 1; + uint64_t pmc_o2s_0b_ongoing : 1; + uint64_t pmc_o2s_1a_ongoing : 1; + uint64_t pmc_o2s_1b_ongoing : 1; + uint64_t pssbridge_ongoing : 1; + uint64_t ipi0_lo_priority : 1; + uint64_t ipi1_lo_priority : 1; + uint64_t ipi2_lo_priority : 1; + uint64_t ipi3_lo_priority : 1; + uint64_t ipi4_lo_priority : 1; + uint64_t spare_31 : 1; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t spare_31 : 1; + uint64_t ipi4_lo_priority : 1; + uint64_t ipi3_lo_priority : 1; + uint64_t ipi2_lo_priority : 1; + uint64_t ipi1_lo_priority : 1; + uint64_t ipi0_lo_priority : 1; + uint64_t pssbridge_ongoing : 1; + uint64_t pmc_o2s_1b_ongoing : 1; + uint64_t pmc_o2s_1a_ongoing : 1; + uint64_t pmc_o2s_0b_ongoing : 1; + uint64_t pmc_o2s_0a_ongoing : 1; + uint64_t pmc_pcb_intr_type7_pending : 1; + uint64_t pmc_pcb_intr_type6_pending : 1; + uint64_t pmc_pcb_intr_type5_pending : 1; + uint64_t pmc_pcb_intr_type4_pending : 1; + uint64_t pmc_pcb_intr_type3_pending : 1; + uint64_t pmc_pcb_intr_type2_pending : 1; + uint64_t pmc_pcb_intr_type1_pending : 1; + uint64_t pmc_pcb_intr_type0_pending : 1; + uint64_t occ_strm3_push : 1; + uint64_t occ_strm3_pull : 1; + uint64_t occ_strm2_push : 1; + uint64_t occ_strm2_pull : 1; + uint64_t occ_strm1_push : 1; + uint64_t occ_strm1_pull : 1; + uint64_t occ_strm0_push : 1; + uint64_t occ_strm0_pull : 1; + uint64_t pba_bcue_attn : 1; + uint64_t pba_bcde_attn : 1; + uint64_t pbax_occ_push1 : 1; + uint64_t pbax_occ_push0 : 1; + uint64_t pbax_occ_send : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_oisr1_clr_t; + + + +typedef union ocb_oisr1_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t pbax_occ_send : 1; + uint64_t pbax_occ_push0 : 1; + uint64_t pbax_occ_push1 : 1; + uint64_t pba_bcde_attn : 1; + uint64_t pba_bcue_attn : 1; + uint64_t occ_strm0_pull : 1; + uint64_t occ_strm0_push : 1; + uint64_t occ_strm1_pull : 1; + uint64_t occ_strm1_push : 1; + uint64_t occ_strm2_pull : 1; + uint64_t occ_strm2_push : 1; + uint64_t occ_strm3_pull : 1; + uint64_t occ_strm3_push : 1; + uint64_t pmc_pcb_intr_type0_pending : 1; + uint64_t pmc_pcb_intr_type1_pending : 1; + uint64_t pmc_pcb_intr_type2_pending : 1; + uint64_t pmc_pcb_intr_type3_pending : 1; + uint64_t pmc_pcb_intr_type4_pending : 1; + uint64_t pmc_pcb_intr_type5_pending : 1; + uint64_t pmc_pcb_intr_type6_pending : 1; + uint64_t pmc_pcb_intr_type7_pending : 1; + uint64_t pmc_o2s_0a_ongoing : 1; + uint64_t pmc_o2s_0b_ongoing : 1; + uint64_t pmc_o2s_1a_ongoing : 1; + uint64_t pmc_o2s_1b_ongoing : 1; + uint64_t pssbridge_ongoing : 1; + uint64_t ipi0_lo_priority : 1; + uint64_t ipi1_lo_priority : 1; + uint64_t ipi2_lo_priority : 1; + uint64_t ipi3_lo_priority : 1; + uint64_t ipi4_lo_priority : 1; + uint64_t spare_31 : 1; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t spare_31 : 1; + uint64_t ipi4_lo_priority : 1; + uint64_t ipi3_lo_priority : 1; + uint64_t ipi2_lo_priority : 1; + uint64_t ipi1_lo_priority : 1; + uint64_t ipi0_lo_priority : 1; + uint64_t pssbridge_ongoing : 1; + uint64_t pmc_o2s_1b_ongoing : 1; + uint64_t pmc_o2s_1a_ongoing : 1; + uint64_t pmc_o2s_0b_ongoing : 1; + uint64_t pmc_o2s_0a_ongoing : 1; + uint64_t pmc_pcb_intr_type7_pending : 1; + uint64_t pmc_pcb_intr_type6_pending : 1; + uint64_t pmc_pcb_intr_type5_pending : 1; + uint64_t pmc_pcb_intr_type4_pending : 1; + uint64_t pmc_pcb_intr_type3_pending : 1; + uint64_t pmc_pcb_intr_type2_pending : 1; + uint64_t pmc_pcb_intr_type1_pending : 1; + uint64_t pmc_pcb_intr_type0_pending : 1; + uint64_t occ_strm3_push : 1; + uint64_t occ_strm3_pull : 1; + uint64_t occ_strm2_push : 1; + uint64_t occ_strm2_pull : 1; + uint64_t occ_strm1_push : 1; + uint64_t occ_strm1_pull : 1; + uint64_t occ_strm0_push : 1; + uint64_t occ_strm0_pull : 1; + uint64_t pba_bcue_attn : 1; + uint64_t pba_bcde_attn : 1; + uint64_t pbax_occ_push1 : 1; + uint64_t pbax_occ_push0 : 1; + uint64_t pbax_occ_send : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_oisr1_or_t; + + + +typedef union ocb_oimr1 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_mask_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_mask_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oimr1_t; + + + +typedef union ocb_oimr1_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_mask_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_mask_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oimr1_clr_t; + + + +typedef union ocb_oimr1_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_mask_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_mask_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oimr1_or_t; + + + +typedef union ocb_oitr1 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_type_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_type_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oitr1_t; + + + +typedef union ocb_oitr1_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_type_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_type_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oitr1_clr_t; + + + +typedef union ocb_oitr1_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_type_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_type_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oitr1_or_t; + + + +typedef union ocb_oiepr1 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_edge_pol_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_edge_pol_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oiepr1_t; + + + +typedef union ocb_oiepr1_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_edge_pol_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_edge_pol_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oiepr1_clr_t; + + + +typedef union ocb_oiepr1_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_edge_pol_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_edge_pol_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oiepr1_or_t; + + + +typedef union ocb_oirr0a +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_route_a_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_route_a_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oirr0a_t; + + + +typedef union ocb_oirr0a_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_route_a_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_route_a_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oirr0a_clr_t; + + + +typedef union ocb_oirr0a_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_route_a_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_route_a_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oirr0a_or_t; + + + +typedef union ocb_oirr0b +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_route_a_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_route_a_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oirr0b_t; + + + +typedef union ocb_oirr0b_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_route_a_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_route_a_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oirr0b_clr_t; + + + +typedef union ocb_oirr0b_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_route_a_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_route_a_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oirr0b_or_t; + + + +typedef union ocb_oirr0c +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_route_a_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_route_a_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oirr0c_t; + + + +typedef union ocb_oirr0c_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_route_a_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_route_a_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oirr0c_clr_t; + + + +typedef union ocb_oirr0c_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_route_a_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_route_a_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oirr0c_or_t; + + + +typedef union ocb_oirr1a +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_route_a_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_route_a_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oirr1a_t; + + + +typedef union ocb_oirr1a_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_route_a_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_route_a_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oirr1a_clr_t; + + + +typedef union ocb_oirr1a_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_route_a_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_route_a_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oirr1a_or_t; + + + +typedef union ocb_oirr1b +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_route_a_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_route_a_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oirr1b_t; + + + +typedef union ocb_oirr1b_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_route_a_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_route_a_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oirr1b_clr_t; + + + +typedef union ocb_oirr1b_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_route_a_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_route_a_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oirr1b_or_t; + + + +typedef union ocb_oirr1c +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_route_a_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_route_a_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oirr1c_t; + + + +typedef union ocb_oirr1c_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_route_a_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_route_a_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oirr1c_clr_t; + + + +typedef union ocb_oirr1c_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_route_a_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_route_a_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oirr1c_or_t; + + + +typedef union ocb_onisr0 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_noncrit_status_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_noncrit_status_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_onisr0_t; + + + +typedef union ocb_ocisr0 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_crit_status_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_crit_status_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocisr0_t; + + + +typedef union ocb_ouisr0 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_uncon_status_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_uncon_status_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_ouisr0_t; + + + +typedef union ocb_odisr0 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_debug_status_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_debug_status_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_odisr0_t; + + + +typedef union ocb_g0isr0 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_gpe0_status_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_gpe0_status_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_g0isr0_t; + + + +typedef union ocb_g1isr0 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_gpe1_status_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_gpe1_status_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_g1isr0_t; + + + +typedef union ocb_g2isr0 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_gpe2_status_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_gpe2_status_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_g2isr0_t; + + + +typedef union ocb_g3isr0 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_gpe3_status_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_gpe3_status_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_g3isr0_t; + + + +typedef union ocb_onisr1 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_noncrit_status_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_noncrit_status_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_onisr1_t; + + + +typedef union ocb_ocisr1 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_crit_status_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_crit_status_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocisr1_t; + + + +typedef union ocb_ouisr1 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_uncon_status_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_uncon_status_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_ouisr1_t; + + + +typedef union ocb_odisr1 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_debug_status_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_debug_status_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_odisr1_t; + + + +typedef union ocb_g0isr1 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_gpe0_status_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_gpe0_status_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_g0isr1_t; + + + +typedef union ocb_g1isr1 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_gpe1_status_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_gpe1_status_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_g1isr1_t; + + + +typedef union ocb_g2isr1 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_gpe2_status_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_gpe2_status_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_g2isr1_t; + + + +typedef union ocb_g3isr1 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t interrupt_gpe3_status_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t interrupt_gpe3_status_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_g3isr1_t; + + + +typedef union ocb_occmisc +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t core_ext_intr : 1; + uint64_t spare : 15; + uint64_t reserved1 : 48; +#else + uint64_t reserved1 : 48; + uint64_t spare : 15; + uint64_t core_ext_intr : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_occmisc_t; + + + +typedef union ocb_occmisc_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t core_ext_intr : 1; + uint64_t spare : 15; + uint64_t reserved1 : 48; +#else + uint64_t reserved1 : 48; + uint64_t spare : 15; + uint64_t core_ext_intr : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_occmisc_clr_t; + + + +typedef union ocb_occmisc_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t core_ext_intr : 1; + uint64_t spare : 15; + uint64_t reserved1 : 48; +#else + uint64_t reserved1 : 48; + uint64_t spare : 15; + uint64_t core_ext_intr : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_occmisc_or_t; + + + +typedef union ocb_ohtmcr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t htm_src_sel : 2; + uint64_t htm_stop : 1; + uint64_t htm_marker_slave_adrs : 3; + uint64_t event2halt_mode : 2; + uint64_t event2halt_en : 11; + uint64_t reserved1 : 4; + uint64_t event2halt_occ : 1; + uint64_t event2halt_gpe0 : 1; + uint64_t event2halt_gpe1 : 1; + uint64_t event2halt_gpe2 : 1; + uint64_t event2halt_gpe3 : 1; + uint64_t reserved2 : 3; + uint64_t event2halt_halt_state : 1; + uint64_t reserved3 : 32; +#else + uint64_t reserved3 : 32; + uint64_t event2halt_halt_state : 1; + uint64_t reserved2 : 3; + uint64_t event2halt_gpe3 : 1; + uint64_t event2halt_gpe2 : 1; + uint64_t event2halt_gpe1 : 1; + uint64_t event2halt_gpe0 : 1; + uint64_t event2halt_occ : 1; + uint64_t reserved1 : 4; + uint64_t event2halt_en : 11; + uint64_t event2halt_mode : 2; + uint64_t htm_marker_slave_adrs : 3; + uint64_t htm_stop : 1; + uint64_t htm_src_sel : 2; +#endif // _BIG_ENDIAN + } fields; +} ocb_ohtmcr_t; + + + +typedef union ocb_oehdr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t event2halt_delay : 20; + uint64_t reserved1 : 44; +#else + uint64_t reserved1 : 44; + uint64_t event2halt_delay : 20; +#endif // _BIG_ENDIAN + } fields; +} ocb_oehdr_t; + + + +typedef union ocb_ocicfg +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t m0_priority : 2; + uint64_t m1_priority : 2; + uint64_t m2_priority : 2; + uint64_t m3_priority : 2; + uint64_t m4_priority : 2; + uint64_t m5_priority : 2; + uint64_t m6_priority : 2; + uint64_t m7_priority : 2; + uint64_t m0_priority_sel : 1; + uint64_t m1_priority_sel : 1; + uint64_t m2_priority_sel : 1; + uint64_t m3_priority_sel : 1; + uint64_t ocicfg_reserved_20 : 1; + uint64_t m5_priority_sel : 1; + uint64_t ocicfg_reserved_23 : 1; + uint64_t m7_priority_sel : 1; + uint64_t plbarb_lockerr : 1; + uint64_t spare_24_31 : 7; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t spare_24_31 : 7; + uint64_t plbarb_lockerr : 1; + uint64_t m7_priority_sel : 1; + uint64_t ocicfg_reserved_23 : 1; + uint64_t m5_priority_sel : 1; + uint64_t ocicfg_reserved_20 : 1; + uint64_t m3_priority_sel : 1; + uint64_t m2_priority_sel : 1; + uint64_t m1_priority_sel : 1; + uint64_t m0_priority_sel : 1; + uint64_t m7_priority : 2; + uint64_t m6_priority : 2; + uint64_t m5_priority : 2; + uint64_t m4_priority : 2; + uint64_t m3_priority : 2; + uint64_t m2_priority : 2; + uint64_t m1_priority : 2; + uint64_t m0_priority : 2; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocicfg_t; + + + +typedef union ocb_occs0 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t occ_scratch_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t occ_scratch_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_occs0_t; + + + +typedef union ocb_occs1 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t occ_scratch_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t occ_scratch_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_occs1_t; + + + +typedef union ocb_occs2 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t occ_scratch_n : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t occ_scratch_n : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_occs2_t; + + + +typedef union ocb_occflg +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t occ_flags : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t occ_flags : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_occflg_t; + + + +typedef union ocb_occflg_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t occ_flags : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t occ_flags : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_occflg_clr_t; + + + +typedef union ocb_occflg_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t occ_flags : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t occ_flags : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_occflg_or_t; + + + +typedef union ocb_occhbr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t occ_heartbeat_count : 16; + uint64_t occ_heartbeat_en : 1; + uint64_t reserved1 : 47; +#else + uint64_t reserved1 : 47; + uint64_t occ_heartbeat_en : 1; + uint64_t occ_heartbeat_count : 16; +#endif // _BIG_ENDIAN + } fields; +} ocb_occhbr_t; + + + +typedef union ocb_ccsr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t core_config : 24; + uint64_t reserved1 : 40; +#else + uint64_t reserved1 : 40; + uint64_t core_config : 24; +#endif // _BIG_ENDIAN + } fields; +} ocb_ccsr_t; + + + +typedef union ocb_ccsr_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t core_config : 24; + uint64_t reserved1 : 40; +#else + uint64_t reserved1 : 40; + uint64_t core_config : 24; +#endif // _BIG_ENDIAN + } fields; +} ocb_ccsr_clr_t; + + + +typedef union ocb_ccsr_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t core_config : 24; + uint64_t reserved1 : 40; +#else + uint64_t reserved1 : 40; + uint64_t core_config : 24; +#endif // _BIG_ENDIAN + } fields; +} ocb_ccsr_or_t; + + + +typedef union ocb_qcsr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t reserved1 : 12; + uint64_t l3_config : 12; + uint64_t reserved2 : 39; + uint64_t change_in_progress : 1; +#else + uint64_t change_in_progress : 1; + uint64_t reserved2 : 39; + uint64_t l3_config : 12; + uint64_t reserved1 : 12; +#endif // _BIG_ENDIAN + } fields; +} ocb_qcsr_t; + + + +typedef union ocb_qcsr_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t reserved1 : 12; + uint64_t l3_config : 12; + uint64_t reserved2 : 39; + uint64_t change_in_progress : 1; +#else + uint64_t change_in_progress : 1; + uint64_t reserved2 : 39; + uint64_t l3_config : 12; + uint64_t reserved1 : 12; +#endif // _BIG_ENDIAN + } fields; +} ocb_qcsr_clr_t; + + + +typedef union ocb_qcsr_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t reserved1 : 12; + uint64_t l3_config : 12; + uint64_t reserved2 : 39; + uint64_t change_in_progress : 1; +#else + uint64_t change_in_progress : 1; + uint64_t reserved2 : 39; + uint64_t l3_config : 12; + uint64_t reserved1 : 12; +#endif // _BIG_ENDIAN + } fields; +} ocb_qcsr_or_t; + + + +typedef union ocb_qssr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t l2_stopped : 12; + uint64_t l3_stopped : 12; + uint64_t quad_stopped : 6; + uint64_t reserved1 : 1; + uint64_t stop_in_progress : 1; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t stop_in_progress : 1; + uint64_t reserved1 : 1; + uint64_t quad_stopped : 6; + uint64_t l3_stopped : 12; + uint64_t l2_stopped : 12; +#endif // _BIG_ENDIAN + } fields; +} ocb_qssr_t; + + + +typedef union ocb_qssr_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t l2_stopped : 12; + uint64_t l3_stopped : 12; + uint64_t quad_stopped : 6; + uint64_t reserved1 : 1; + uint64_t stop_in_progress : 1; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t stop_in_progress : 1; + uint64_t reserved1 : 1; + uint64_t quad_stopped : 6; + uint64_t l3_stopped : 12; + uint64_t l2_stopped : 12; +#endif // _BIG_ENDIAN + } fields; +} ocb_qssr_clr_t; + + + +typedef union ocb_qssr_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t l2_stopped : 12; + uint64_t l3_stopped : 12; + uint64_t quad_stopped : 6; + uint64_t reserved1 : 1; + uint64_t stop_in_progress : 1; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t stop_in_progress : 1; + uint64_t reserved1 : 1; + uint64_t quad_stopped : 6; + uint64_t l3_stopped : 12; + uint64_t l2_stopped : 12; +#endif // _BIG_ENDIAN + } fields; +} ocb_qssr_or_t; + + + +typedef union ocb_otbr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t ocb_timebase : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t ocb_timebase : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_otbr_t; + + + +typedef union ocb_otrn +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t timeout : 1; + uint64_t control : 1; + uint64_t auto_reload : 1; + uint64_t spare : 13; + uint64_t timer : 16; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t timer : 16; + uint64_t spare : 13; + uint64_t auto_reload : 1; + uint64_t control : 1; + uint64_t timeout : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_otrn_t; + + + +typedef union ocb_ocbslbrn +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t pull_oci_region : 3; + uint64_t pull_start : 26; + uint64_t reserved1 : 35; +#else + uint64_t reserved1 : 35; + uint64_t pull_start : 26; + uint64_t pull_oci_region : 3; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbslbrn_t; + + + +typedef union ocb_ocbslcsn +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t pull_full : 1; + uint64_t pull_empty : 1; + uint64_t spare : 2; + uint64_t pull_intr_action : 2; + uint64_t pull_length : 5; + uint64_t reserved1 : 2; + uint64_t pull_write_ptr : 5; + uint64_t reserved2 : 3; + uint64_t pull_read_ptr : 5; + uint64_t reserved3 : 5; + uint64_t pull_enable : 1; + uint64_t reserved4 : 32; +#else + uint64_t reserved4 : 32; + uint64_t pull_enable : 1; + uint64_t reserved3 : 5; + uint64_t pull_read_ptr : 5; + uint64_t reserved2 : 3; + uint64_t pull_write_ptr : 5; + uint64_t reserved1 : 2; + uint64_t pull_length : 5; + uint64_t pull_intr_action : 2; + uint64_t spare : 2; + uint64_t pull_empty : 1; + uint64_t pull_full : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbslcsn_t; + + + +typedef union ocb_ocbslin +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t reserved1 : 64; +#else + uint64_t reserved1 : 64; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbslin_t; + + + +typedef union ocb_ocbshbrn +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t push_oci_region : 3; + uint64_t push_start : 26; + uint64_t reserved1 : 35; +#else + uint64_t reserved1 : 35; + uint64_t push_start : 26; + uint64_t push_oci_region : 3; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbshbrn_t; + + + +typedef union ocb_ocbshcsn +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t push_full : 1; + uint64_t push_empty : 1; + uint64_t spare : 2; + uint64_t push_intr_action : 2; + uint64_t push_length : 5; + uint64_t reserved1 : 2; + uint64_t push_write_ptr : 5; + uint64_t reserved2 : 3; + uint64_t push_read_ptr : 5; + uint64_t reserved3 : 5; + uint64_t push_enable : 1; + uint64_t reserved4 : 32; +#else + uint64_t reserved4 : 32; + uint64_t push_enable : 1; + uint64_t reserved3 : 5; + uint64_t push_read_ptr : 5; + uint64_t reserved2 : 3; + uint64_t push_write_ptr : 5; + uint64_t reserved1 : 2; + uint64_t push_length : 5; + uint64_t push_intr_action : 2; + uint64_t spare : 2; + uint64_t push_empty : 1; + uint64_t push_full : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbshcsn_t; + + + +typedef union ocb_ocbshin +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t reserved1 : 64; +#else + uint64_t reserved1 : 64; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbshin_t; + + + +typedef union ocb_ocbsesn +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t push_read_underflow : 1; + uint64_t pull_write_overflow : 1; + uint64_t reserved1 : 62; +#else + uint64_t reserved1 : 62; + uint64_t pull_write_overflow : 1; + uint64_t push_read_underflow : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbsesn_t; + + + +typedef union ocb_ocblwcrn +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t linear_window_enable : 1; + uint64_t spare_0 : 2; + uint64_t linear_window_bar : 17; + uint64_t linear_window_mask : 12; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t linear_window_mask : 12; + uint64_t linear_window_bar : 17; + uint64_t spare_0 : 2; + uint64_t linear_window_enable : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocblwcrn_t; + + + +typedef union ocb_ocblwsrn +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t linear_window_scresp : 3; + uint64_t spare0 : 5; + uint64_t reserved1 : 56; +#else + uint64_t reserved1 : 56; + uint64_t spare0 : 5; + uint64_t linear_window_scresp : 3; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocblwsrn_t; + + + +typedef union ocb_ocblwsbrn +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t linear_window_region : 3; + uint64_t linear_window_base : 7; + uint64_t reserved1 : 54; +#else + uint64_t reserved1 : 54; + uint64_t linear_window_base : 7; + uint64_t linear_window_region : 3; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocblwsbrn_t; + + + +typedef union ocb_opit0cn +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t reserved1 : 22; + uint64_t pcb_intr_type_a_core_n : 10; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t pcb_intr_type_a_core_n : 10; + uint64_t reserved1 : 22; +#endif // _BIG_ENDIAN + } fields; +} ocb_opit0cn_t; + + + +typedef union ocb_opit1cn +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t reserved1 : 22; + uint64_t pcb_intr_type_a_core_n : 10; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t pcb_intr_type_a_core_n : 10; + uint64_t reserved1 : 22; +#endif // _BIG_ENDIAN + } fields; +} ocb_opit1cn_t; + + + +typedef union ocb_opit2cn +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t reserved1 : 22; + uint64_t pcb_intr_type_a_core_n : 10; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t pcb_intr_type_a_core_n : 10; + uint64_t reserved1 : 22; +#endif // _BIG_ENDIAN + } fields; +} ocb_opit2cn_t; + + + +typedef union ocb_opit3cn +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t reserved1 : 22; + uint64_t pcb_intr_type_a_core_n : 10; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t pcb_intr_type_a_core_n : 10; + uint64_t reserved1 : 22; +#endif // _BIG_ENDIAN + } fields; +} ocb_opit3cn_t; + + + +typedef union ocb_opit4cn +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t reserved1 : 22; + uint64_t pcb_intr_type_a_core_n : 10; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t pcb_intr_type_a_core_n : 10; + uint64_t reserved1 : 22; +#endif // _BIG_ENDIAN + } fields; +} ocb_opit4cn_t; + + + +typedef union ocb_opit5cn +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t reserved1 : 22; + uint64_t pcb_intr_type_a_core_n : 10; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t pcb_intr_type_a_core_n : 10; + uint64_t reserved1 : 22; +#endif // _BIG_ENDIAN + } fields; +} ocb_opit5cn_t; + + + +typedef union ocb_opit6xn +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t reserved1 : 22; + uint64_t pcb_intr_type_a_quad_n : 4; + uint64_t reserved2 : 6; + uint64_t reserved3 : 32; +#else + uint64_t reserved3 : 32; + uint64_t reserved2 : 6; + uint64_t pcb_intr_type_a_quad_n : 4; + uint64_t reserved1 : 22; +#endif // _BIG_ENDIAN + } fields; +} ocb_opit6xn_t; + + + +typedef union ocb_opit7xn +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t reserved1 : 22; + uint64_t pcb_intr_type_a_quad_n : 1; + uint64_t reserved2 : 9; + uint64_t reserved3 : 32; +#else + uint64_t reserved3 : 32; + uint64_t reserved2 : 9; + uint64_t pcb_intr_type_a_quad_n : 1; + uint64_t reserved1 : 22; +#endif // _BIG_ENDIAN + } fields; +} ocb_opit7xn_t; + + + +typedef union ocb_opit0cnrp +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t reserved1 : 22; + uint64_t pcb_intr_type_a_reset_core_n : 10; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t pcb_intr_type_a_reset_core_n : 10; + uint64_t reserved1 : 22; +#endif // _BIG_ENDIAN + } fields; +} ocb_opit0cnrp_t; + + + +typedef union ocb_opit1cnrp +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t reserved1 : 22; + uint64_t pcb_intr_type_a_reset_core_n : 10; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t pcb_intr_type_a_reset_core_n : 10; + uint64_t reserved1 : 22; +#endif // _BIG_ENDIAN + } fields; +} ocb_opit1cnrp_t; + + + +typedef union ocb_opit2cnrp +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t reserved1 : 22; + uint64_t pcb_intr_type_a_reset_core_n : 10; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t pcb_intr_type_a_reset_core_n : 10; + uint64_t reserved1 : 22; +#endif // _BIG_ENDIAN + } fields; +} ocb_opit2cnrp_t; + + + +typedef union ocb_opit3cnrp +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t reserved1 : 22; + uint64_t pcb_intr_type_a_reset_core_n : 10; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t pcb_intr_type_a_reset_core_n : 10; + uint64_t reserved1 : 22; +#endif // _BIG_ENDIAN + } fields; +} ocb_opit3cnrp_t; + + + +typedef union ocb_opit4cnrp +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t reserved1 : 22; + uint64_t pcb_intr_type_a_reset_core_n : 10; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t pcb_intr_type_a_reset_core_n : 10; + uint64_t reserved1 : 22; +#endif // _BIG_ENDIAN + } fields; +} ocb_opit4cnrp_t; + + + +typedef union ocb_opit5cnrp +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t reserved1 : 22; + uint64_t pcb_intr_type_a_reset_core_n : 10; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t pcb_intr_type_a_reset_core_n : 10; + uint64_t reserved1 : 22; +#endif // _BIG_ENDIAN + } fields; +} ocb_opit5cnrp_t; + + + +typedef union ocb_opit6xnrp +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t reserved1 : 22; + uint64_t pcb_intr_type_a_reset_quad_n : 4; + uint64_t reserved2 : 6; + uint64_t reserved3 : 32; +#else + uint64_t reserved3 : 32; + uint64_t reserved2 : 6; + uint64_t pcb_intr_type_a_reset_quad_n : 4; + uint64_t reserved1 : 22; +#endif // _BIG_ENDIAN + } fields; +} ocb_opit6xnrp_t; + + + +typedef union ocb_opit7xnrp +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t reserved1 : 22; + uint64_t pcb_intr_type_a_reset_quad_n : 1; + uint64_t reserved2 : 9; + uint64_t reserved3 : 32; +#else + uint64_t reserved3 : 32; + uint64_t reserved2 : 9; + uint64_t pcb_intr_type_a_reset_quad_n : 1; + uint64_t reserved1 : 22; +#endif // _BIG_ENDIAN + } fields; +} ocb_opit7xnrp_t; + + + +typedef union ocb_opitnpra +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t pcb_intr_type_n_pending_0 : 1; + uint64_t pcb_intr_type_n_pending_1 : 1; + uint64_t pcb_intr_type_n_pending_2 : 1; + uint64_t pcb_intr_type_n_pending_3 : 1; + uint64_t pcb_intr_type_n_pending_4 : 1; + uint64_t pcb_intr_type_n_pending_5 : 1; + uint64_t pcb_intr_type_n_pending_6 : 1; + uint64_t pcb_intr_type_n_pending_7 : 1; + uint64_t pcb_intr_type_n_pending_8 : 1; + uint64_t pcb_intr_type_n_pending_9 : 1; + uint64_t pcb_intr_type_n_pending_10 : 1; + uint64_t pcb_intr_type_n_pending_11 : 1; + uint64_t pcb_intr_type_n_pending_12 : 1; + uint64_t pcb_intr_type_n_pending_13 : 1; + uint64_t pcb_intr_type_n_pending_14 : 1; + uint64_t pcb_intr_type_n_pending_15 : 1; + uint64_t pcb_intr_type_n_pending_16 : 1; + uint64_t pcb_intr_type_n_pending_17 : 1; + uint64_t pcb_intr_type_n_pending_18 : 1; + uint64_t pcb_intr_type_n_pending_19 : 1; + uint64_t pcb_intr_type_n_pending_20 : 1; + uint64_t pcb_intr_type_n_pending_21 : 1; + uint64_t pcb_intr_type_n_pending_22 : 1; + uint64_t pcb_intr_type_n_pending_23 : 1; + uint64_t reserved1 : 8; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t reserved1 : 8; + uint64_t pcb_intr_type_n_pending_23 : 1; + uint64_t pcb_intr_type_n_pending_22 : 1; + uint64_t pcb_intr_type_n_pending_21 : 1; + uint64_t pcb_intr_type_n_pending_20 : 1; + uint64_t pcb_intr_type_n_pending_19 : 1; + uint64_t pcb_intr_type_n_pending_18 : 1; + uint64_t pcb_intr_type_n_pending_17 : 1; + uint64_t pcb_intr_type_n_pending_16 : 1; + uint64_t pcb_intr_type_n_pending_15 : 1; + uint64_t pcb_intr_type_n_pending_14 : 1; + uint64_t pcb_intr_type_n_pending_13 : 1; + uint64_t pcb_intr_type_n_pending_12 : 1; + uint64_t pcb_intr_type_n_pending_11 : 1; + uint64_t pcb_intr_type_n_pending_10 : 1; + uint64_t pcb_intr_type_n_pending_9 : 1; + uint64_t pcb_intr_type_n_pending_8 : 1; + uint64_t pcb_intr_type_n_pending_7 : 1; + uint64_t pcb_intr_type_n_pending_6 : 1; + uint64_t pcb_intr_type_n_pending_5 : 1; + uint64_t pcb_intr_type_n_pending_4 : 1; + uint64_t pcb_intr_type_n_pending_3 : 1; + uint64_t pcb_intr_type_n_pending_2 : 1; + uint64_t pcb_intr_type_n_pending_1 : 1; + uint64_t pcb_intr_type_n_pending_0 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_opitnpra_t; + + + +typedef union ocb_opitnpra_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t pcb_intr_type_n_pending_0 : 1; + uint64_t pcb_intr_type_n_pending_1 : 1; + uint64_t pcb_intr_type_n_pending_2 : 1; + uint64_t pcb_intr_type_n_pending_3 : 1; + uint64_t pcb_intr_type_n_pending_4 : 1; + uint64_t pcb_intr_type_n_pending_5 : 1; + uint64_t pcb_intr_type_n_pending_6 : 1; + uint64_t pcb_intr_type_n_pending_7 : 1; + uint64_t pcb_intr_type_n_pending_8 : 1; + uint64_t pcb_intr_type_n_pending_9 : 1; + uint64_t pcb_intr_type_n_pending_10 : 1; + uint64_t pcb_intr_type_n_pending_11 : 1; + uint64_t pcb_intr_type_n_pending_12 : 1; + uint64_t pcb_intr_type_n_pending_13 : 1; + uint64_t pcb_intr_type_n_pending_14 : 1; + uint64_t pcb_intr_type_n_pending_15 : 1; + uint64_t pcb_intr_type_n_pending_16 : 1; + uint64_t pcb_intr_type_n_pending_17 : 1; + uint64_t pcb_intr_type_n_pending_18 : 1; + uint64_t pcb_intr_type_n_pending_19 : 1; + uint64_t pcb_intr_type_n_pending_20 : 1; + uint64_t pcb_intr_type_n_pending_21 : 1; + uint64_t pcb_intr_type_n_pending_22 : 1; + uint64_t pcb_intr_type_n_pending_23 : 1; + uint64_t reserved1 : 8; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t reserved1 : 8; + uint64_t pcb_intr_type_n_pending_23 : 1; + uint64_t pcb_intr_type_n_pending_22 : 1; + uint64_t pcb_intr_type_n_pending_21 : 1; + uint64_t pcb_intr_type_n_pending_20 : 1; + uint64_t pcb_intr_type_n_pending_19 : 1; + uint64_t pcb_intr_type_n_pending_18 : 1; + uint64_t pcb_intr_type_n_pending_17 : 1; + uint64_t pcb_intr_type_n_pending_16 : 1; + uint64_t pcb_intr_type_n_pending_15 : 1; + uint64_t pcb_intr_type_n_pending_14 : 1; + uint64_t pcb_intr_type_n_pending_13 : 1; + uint64_t pcb_intr_type_n_pending_12 : 1; + uint64_t pcb_intr_type_n_pending_11 : 1; + uint64_t pcb_intr_type_n_pending_10 : 1; + uint64_t pcb_intr_type_n_pending_9 : 1; + uint64_t pcb_intr_type_n_pending_8 : 1; + uint64_t pcb_intr_type_n_pending_7 : 1; + uint64_t pcb_intr_type_n_pending_6 : 1; + uint64_t pcb_intr_type_n_pending_5 : 1; + uint64_t pcb_intr_type_n_pending_4 : 1; + uint64_t pcb_intr_type_n_pending_3 : 1; + uint64_t pcb_intr_type_n_pending_2 : 1; + uint64_t pcb_intr_type_n_pending_1 : 1; + uint64_t pcb_intr_type_n_pending_0 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_opitnpra_clr_t; + + + +typedef union ocb_opitnpra_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t pcb_intr_type_n_pending_0 : 1; + uint64_t pcb_intr_type_n_pending_1 : 1; + uint64_t pcb_intr_type_n_pending_2 : 1; + uint64_t pcb_intr_type_n_pending_3 : 1; + uint64_t pcb_intr_type_n_pending_4 : 1; + uint64_t pcb_intr_type_n_pending_5 : 1; + uint64_t pcb_intr_type_n_pending_6 : 1; + uint64_t pcb_intr_type_n_pending_7 : 1; + uint64_t pcb_intr_type_n_pending_8 : 1; + uint64_t pcb_intr_type_n_pending_9 : 1; + uint64_t pcb_intr_type_n_pending_10 : 1; + uint64_t pcb_intr_type_n_pending_11 : 1; + uint64_t pcb_intr_type_n_pending_12 : 1; + uint64_t pcb_intr_type_n_pending_13 : 1; + uint64_t pcb_intr_type_n_pending_14 : 1; + uint64_t pcb_intr_type_n_pending_15 : 1; + uint64_t pcb_intr_type_n_pending_16 : 1; + uint64_t pcb_intr_type_n_pending_17 : 1; + uint64_t pcb_intr_type_n_pending_18 : 1; + uint64_t pcb_intr_type_n_pending_19 : 1; + uint64_t pcb_intr_type_n_pending_20 : 1; + uint64_t pcb_intr_type_n_pending_21 : 1; + uint64_t pcb_intr_type_n_pending_22 : 1; + uint64_t pcb_intr_type_n_pending_23 : 1; + uint64_t reserved1 : 8; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t reserved1 : 8; + uint64_t pcb_intr_type_n_pending_23 : 1; + uint64_t pcb_intr_type_n_pending_22 : 1; + uint64_t pcb_intr_type_n_pending_21 : 1; + uint64_t pcb_intr_type_n_pending_20 : 1; + uint64_t pcb_intr_type_n_pending_19 : 1; + uint64_t pcb_intr_type_n_pending_18 : 1; + uint64_t pcb_intr_type_n_pending_17 : 1; + uint64_t pcb_intr_type_n_pending_16 : 1; + uint64_t pcb_intr_type_n_pending_15 : 1; + uint64_t pcb_intr_type_n_pending_14 : 1; + uint64_t pcb_intr_type_n_pending_13 : 1; + uint64_t pcb_intr_type_n_pending_12 : 1; + uint64_t pcb_intr_type_n_pending_11 : 1; + uint64_t pcb_intr_type_n_pending_10 : 1; + uint64_t pcb_intr_type_n_pending_9 : 1; + uint64_t pcb_intr_type_n_pending_8 : 1; + uint64_t pcb_intr_type_n_pending_7 : 1; + uint64_t pcb_intr_type_n_pending_6 : 1; + uint64_t pcb_intr_type_n_pending_5 : 1; + uint64_t pcb_intr_type_n_pending_4 : 1; + uint64_t pcb_intr_type_n_pending_3 : 1; + uint64_t pcb_intr_type_n_pending_2 : 1; + uint64_t pcb_intr_type_n_pending_1 : 1; + uint64_t pcb_intr_type_n_pending_0 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_opitnpra_or_t; + + + +typedef union ocb_opit6prb +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t pcb_intr_type_n_pending_0 : 1; + uint64_t pcb_intr_type_n_pending_1 : 1; + uint64_t pcb_intr_type_n_pending_2 : 1; + uint64_t pcb_intr_type_n_pending_3 : 1; + uint64_t pcb_intr_type_n_pending_4 : 1; + uint64_t pcb_intr_type_n_pending_5 : 1; + uint64_t reserved1 : 26; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t reserved1 : 26; + uint64_t pcb_intr_type_n_pending_5 : 1; + uint64_t pcb_intr_type_n_pending_4 : 1; + uint64_t pcb_intr_type_n_pending_3 : 1; + uint64_t pcb_intr_type_n_pending_2 : 1; + uint64_t pcb_intr_type_n_pending_1 : 1; + uint64_t pcb_intr_type_n_pending_0 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_opit6prb_t; + + + +typedef union ocb_opit6prb_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t pcb_intr_type_n_pending_0 : 1; + uint64_t pcb_intr_type_n_pending_1 : 1; + uint64_t pcb_intr_type_n_pending_2 : 1; + uint64_t pcb_intr_type_n_pending_3 : 1; + uint64_t pcb_intr_type_n_pending_4 : 1; + uint64_t pcb_intr_type_n_pending_5 : 1; + uint64_t reserved1 : 26; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t reserved1 : 26; + uint64_t pcb_intr_type_n_pending_5 : 1; + uint64_t pcb_intr_type_n_pending_4 : 1; + uint64_t pcb_intr_type_n_pending_3 : 1; + uint64_t pcb_intr_type_n_pending_2 : 1; + uint64_t pcb_intr_type_n_pending_1 : 1; + uint64_t pcb_intr_type_n_pending_0 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_opit6prb_clr_t; + + + +typedef union ocb_opit6prb_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t pcb_intr_type_n_pending_0 : 1; + uint64_t pcb_intr_type_n_pending_1 : 1; + uint64_t pcb_intr_type_n_pending_2 : 1; + uint64_t pcb_intr_type_n_pending_3 : 1; + uint64_t pcb_intr_type_n_pending_4 : 1; + uint64_t pcb_intr_type_n_pending_5 : 1; + uint64_t reserved1 : 26; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t reserved1 : 26; + uint64_t pcb_intr_type_n_pending_5 : 1; + uint64_t pcb_intr_type_n_pending_4 : 1; + uint64_t pcb_intr_type_n_pending_3 : 1; + uint64_t pcb_intr_type_n_pending_2 : 1; + uint64_t pcb_intr_type_n_pending_1 : 1; + uint64_t pcb_intr_type_n_pending_0 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_opit6prb_or_t; + + + +typedef union ocb_opit7prb +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t pcb_intr_type_n_pending_0 : 1; + uint64_t pcb_intr_type_n_pending_1 : 1; + uint64_t pcb_intr_type_n_pending_2 : 1; + uint64_t pcb_intr_type_n_pending_3 : 1; + uint64_t pcb_intr_type_n_pending_4 : 1; + uint64_t pcb_intr_type_n_pending_5 : 1; + uint64_t reserved1 : 26; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t reserved1 : 26; + uint64_t pcb_intr_type_n_pending_5 : 1; + uint64_t pcb_intr_type_n_pending_4 : 1; + uint64_t pcb_intr_type_n_pending_3 : 1; + uint64_t pcb_intr_type_n_pending_2 : 1; + uint64_t pcb_intr_type_n_pending_1 : 1; + uint64_t pcb_intr_type_n_pending_0 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_opit7prb_t; + + + +typedef union ocb_opit7prb_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t pcb_intr_type_n_pending_0 : 1; + uint64_t pcb_intr_type_n_pending_1 : 1; + uint64_t pcb_intr_type_n_pending_2 : 1; + uint64_t pcb_intr_type_n_pending_3 : 1; + uint64_t pcb_intr_type_n_pending_4 : 1; + uint64_t pcb_intr_type_n_pending_5 : 1; + uint64_t reserved1 : 26; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t reserved1 : 26; + uint64_t pcb_intr_type_n_pending_5 : 1; + uint64_t pcb_intr_type_n_pending_4 : 1; + uint64_t pcb_intr_type_n_pending_3 : 1; + uint64_t pcb_intr_type_n_pending_2 : 1; + uint64_t pcb_intr_type_n_pending_1 : 1; + uint64_t pcb_intr_type_n_pending_0 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_opit7prb_clr_t; + + + +typedef union ocb_opit7prb_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t pcb_intr_type_n_pending_0 : 1; + uint64_t pcb_intr_type_n_pending_1 : 1; + uint64_t pcb_intr_type_n_pending_2 : 1; + uint64_t pcb_intr_type_n_pending_3 : 1; + uint64_t pcb_intr_type_n_pending_4 : 1; + uint64_t pcb_intr_type_n_pending_5 : 1; + uint64_t reserved1 : 26; + uint64_t reserved2 : 32; +#else + uint64_t reserved2 : 32; + uint64_t reserved1 : 26; + uint64_t pcb_intr_type_n_pending_5 : 1; + uint64_t pcb_intr_type_n_pending_4 : 1; + uint64_t pcb_intr_type_n_pending_3 : 1; + uint64_t pcb_intr_type_n_pending_2 : 1; + uint64_t pcb_intr_type_n_pending_1 : 1; + uint64_t pcb_intr_type_n_pending_0 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_opit7prb_or_t; + + + +typedef union ocb_o2sctrlf0a +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_frame_size_an : 6; + uint64_t o2s_out_count1_an : 6; + uint64_t o2s_in_delay1_an : 6; + uint64_t o2s_in_count1_an : 6; + uint64_t reserved1 : 40; +#else + uint64_t reserved1 : 40; + uint64_t o2s_in_count1_an : 6; + uint64_t o2s_in_delay1_an : 6; + uint64_t o2s_out_count1_an : 6; + uint64_t o2s_frame_size_an : 6; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2sctrlf0a_t; + + + +typedef union ocb_o2sctrls0a +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_out_count2_an : 6; + uint64_t o2s_in_delay2_an : 6; + uint64_t o2s_in_count2_an : 6; + uint64_t reserved1 : 46; +#else + uint64_t reserved1 : 46; + uint64_t o2s_in_count2_an : 6; + uint64_t o2s_in_delay2_an : 6; + uint64_t o2s_out_count2_an : 6; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2sctrls0a_t; + + + +typedef union ocb_o2sctrl10a +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_bridge_enable_an : 1; + uint64_t o2sctrl1an_reserved_1 : 1; + uint64_t o2s_cpol_an : 1; + uint64_t o2s_cpha_an : 1; + uint64_t o2s_clock_divider_an : 10; + uint64_t o2sctrl1an_reserved_14_16 : 3; + uint64_t o2s_nr_of_frames_an : 1; + uint64_t reserved1 : 46; +#else + uint64_t reserved1 : 46; + uint64_t o2s_nr_of_frames_an : 1; + uint64_t o2sctrl1an_reserved_14_16 : 3; + uint64_t o2s_clock_divider_an : 10; + uint64_t o2s_cpha_an : 1; + uint64_t o2s_cpol_an : 1; + uint64_t o2sctrl1an_reserved_1 : 1; + uint64_t o2s_bridge_enable_an : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2sctrl10a_t; + + + +typedef union ocb_o2sctrl20a +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_inter_frame_delay_an : 17; + uint64_t reserved1 : 47; +#else + uint64_t reserved1 : 47; + uint64_t o2s_inter_frame_delay_an : 17; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2sctrl20a_t; + + + +typedef union ocb_o2sst0a +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_ongoing_an : 1; + uint64_t o2sstan_reserved_1_4 : 4; + uint64_t o2s_write_while_bridge_busy_err_an : 1; + uint64_t o2sstan_reserved_6 : 1; + uint64_t o2s_fsm_err_an : 1; + uint64_t reserved1 : 56; +#else + uint64_t reserved1 : 56; + uint64_t o2s_fsm_err_an : 1; + uint64_t o2sstan_reserved_6 : 1; + uint64_t o2s_write_while_bridge_busy_err_an : 1; + uint64_t o2sstan_reserved_1_4 : 4; + uint64_t o2s_ongoing_an : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2sst0a_t; + + + +typedef union ocb_o2scmd0a +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2scmdan_reserved_0 : 1; + uint64_t o2s_clear_sticky_bits_an : 1; + uint64_t reserved1 : 62; +#else + uint64_t reserved1 : 62; + uint64_t o2s_clear_sticky_bits_an : 1; + uint64_t o2scmdan_reserved_0 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2scmd0a_t; + + + +typedef union ocb_o2swd0a +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_wdata_an : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t o2s_wdata_an : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2swd0a_t; + + + +typedef union ocb_o2srd0a +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_rdata_an : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t o2s_rdata_an : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2srd0a_t; + + + +typedef union ocb_o2sctrlf0b +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_frame_size_an : 6; + uint64_t o2s_out_count1_an : 6; + uint64_t o2s_in_delay1_an : 6; + uint64_t o2s_in_count1_an : 6; + uint64_t reserved1 : 40; +#else + uint64_t reserved1 : 40; + uint64_t o2s_in_count1_an : 6; + uint64_t o2s_in_delay1_an : 6; + uint64_t o2s_out_count1_an : 6; + uint64_t o2s_frame_size_an : 6; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2sctrlf0b_t; + + + +typedef union ocb_o2sctrls0b +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_out_count2_an : 6; + uint64_t o2s_in_delay2_an : 6; + uint64_t o2s_in_count2_an : 6; + uint64_t reserved1 : 46; +#else + uint64_t reserved1 : 46; + uint64_t o2s_in_count2_an : 6; + uint64_t o2s_in_delay2_an : 6; + uint64_t o2s_out_count2_an : 6; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2sctrls0b_t; + + + +typedef union ocb_o2sctrl10b +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_bridge_enable_an : 1; + uint64_t o2sctrl1an_reserved_1 : 1; + uint64_t o2s_cpol_an : 1; + uint64_t o2s_cpha_an : 1; + uint64_t o2s_clock_divider_an : 10; + uint64_t o2sctrl1an_reserved_14_16 : 3; + uint64_t o2s_nr_of_frames_an : 1; + uint64_t reserved1 : 46; +#else + uint64_t reserved1 : 46; + uint64_t o2s_nr_of_frames_an : 1; + uint64_t o2sctrl1an_reserved_14_16 : 3; + uint64_t o2s_clock_divider_an : 10; + uint64_t o2s_cpha_an : 1; + uint64_t o2s_cpol_an : 1; + uint64_t o2sctrl1an_reserved_1 : 1; + uint64_t o2s_bridge_enable_an : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2sctrl10b_t; + + + +typedef union ocb_o2sctrl20b +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_inter_frame_delay_an : 17; + uint64_t reserved1 : 47; +#else + uint64_t reserved1 : 47; + uint64_t o2s_inter_frame_delay_an : 17; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2sctrl20b_t; + + + +typedef union ocb_o2sst0b +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_ongoing_an : 1; + uint64_t o2sstan_reserved_1_4 : 4; + uint64_t o2s_write_while_bridge_busy_err_an : 1; + uint64_t o2sstan_reserved_6 : 1; + uint64_t o2s_fsm_err_an : 1; + uint64_t reserved1 : 56; +#else + uint64_t reserved1 : 56; + uint64_t o2s_fsm_err_an : 1; + uint64_t o2sstan_reserved_6 : 1; + uint64_t o2s_write_while_bridge_busy_err_an : 1; + uint64_t o2sstan_reserved_1_4 : 4; + uint64_t o2s_ongoing_an : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2sst0b_t; + + + +typedef union ocb_o2scmd0b +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2scmdan_reserved_0 : 1; + uint64_t o2s_clear_sticky_bits_an : 1; + uint64_t reserved1 : 62; +#else + uint64_t reserved1 : 62; + uint64_t o2s_clear_sticky_bits_an : 1; + uint64_t o2scmdan_reserved_0 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2scmd0b_t; + + + +typedef union ocb_o2swd0b +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_wdata_an : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t o2s_wdata_an : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2swd0b_t; + + + +typedef union ocb_o2srd0b +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_rdata_an : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t o2s_rdata_an : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2srd0b_t; + + + +typedef union ocb_o2sctrlf1a +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_frame_size_an : 6; + uint64_t o2s_out_count1_an : 6; + uint64_t o2s_in_delay1_an : 6; + uint64_t o2s_in_count1_an : 6; + uint64_t reserved1 : 40; +#else + uint64_t reserved1 : 40; + uint64_t o2s_in_count1_an : 6; + uint64_t o2s_in_delay1_an : 6; + uint64_t o2s_out_count1_an : 6; + uint64_t o2s_frame_size_an : 6; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2sctrlf1a_t; + + + +typedef union ocb_o2sctrls1a +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_out_count2_an : 6; + uint64_t o2s_in_delay2_an : 6; + uint64_t o2s_in_count2_an : 6; + uint64_t reserved1 : 46; +#else + uint64_t reserved1 : 46; + uint64_t o2s_in_count2_an : 6; + uint64_t o2s_in_delay2_an : 6; + uint64_t o2s_out_count2_an : 6; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2sctrls1a_t; + + + +typedef union ocb_o2sctrl11a +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_bridge_enable_an : 1; + uint64_t o2sctrl1an_reserved_1 : 1; + uint64_t o2s_cpol_an : 1; + uint64_t o2s_cpha_an : 1; + uint64_t o2s_clock_divider_an : 10; + uint64_t o2sctrl1an_reserved_14_16 : 3; + uint64_t o2s_nr_of_frames_an : 1; + uint64_t reserved1 : 46; +#else + uint64_t reserved1 : 46; + uint64_t o2s_nr_of_frames_an : 1; + uint64_t o2sctrl1an_reserved_14_16 : 3; + uint64_t o2s_clock_divider_an : 10; + uint64_t o2s_cpha_an : 1; + uint64_t o2s_cpol_an : 1; + uint64_t o2sctrl1an_reserved_1 : 1; + uint64_t o2s_bridge_enable_an : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2sctrl11a_t; + + + +typedef union ocb_o2sctrl21a +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_inter_frame_delay_an : 17; + uint64_t reserved1 : 47; +#else + uint64_t reserved1 : 47; + uint64_t o2s_inter_frame_delay_an : 17; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2sctrl21a_t; + + + +typedef union ocb_o2sst1a +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_ongoing_an : 1; + uint64_t o2sstan_reserved_1_4 : 4; + uint64_t o2s_write_while_bridge_busy_err_an : 1; + uint64_t o2sstan_reserved_6 : 1; + uint64_t o2s_fsm_err_an : 1; + uint64_t reserved1 : 56; +#else + uint64_t reserved1 : 56; + uint64_t o2s_fsm_err_an : 1; + uint64_t o2sstan_reserved_6 : 1; + uint64_t o2s_write_while_bridge_busy_err_an : 1; + uint64_t o2sstan_reserved_1_4 : 4; + uint64_t o2s_ongoing_an : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2sst1a_t; + + + +typedef union ocb_o2scmd1a +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2scmdan_reserved_0 : 1; + uint64_t o2s_clear_sticky_bits_an : 1; + uint64_t reserved1 : 62; +#else + uint64_t reserved1 : 62; + uint64_t o2s_clear_sticky_bits_an : 1; + uint64_t o2scmdan_reserved_0 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2scmd1a_t; + + + +typedef union ocb_o2swd1a +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_wdata_an : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t o2s_wdata_an : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2swd1a_t; + + + +typedef union ocb_o2srd1a +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_rdata_an : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t o2s_rdata_an : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2srd1a_t; + + + +typedef union ocb_o2sctrlf1b +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_frame_size_an : 6; + uint64_t o2s_out_count1_an : 6; + uint64_t o2s_in_delay1_an : 6; + uint64_t o2s_in_count1_an : 6; + uint64_t reserved1 : 40; +#else + uint64_t reserved1 : 40; + uint64_t o2s_in_count1_an : 6; + uint64_t o2s_in_delay1_an : 6; + uint64_t o2s_out_count1_an : 6; + uint64_t o2s_frame_size_an : 6; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2sctrlf1b_t; + + + +typedef union ocb_o2sctrls1b +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_out_count2_an : 6; + uint64_t o2s_in_delay2_an : 6; + uint64_t o2s_in_count2_an : 6; + uint64_t reserved1 : 46; +#else + uint64_t reserved1 : 46; + uint64_t o2s_in_count2_an : 6; + uint64_t o2s_in_delay2_an : 6; + uint64_t o2s_out_count2_an : 6; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2sctrls1b_t; + + + +typedef union ocb_o2sctrl11b +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_bridge_enable_an : 1; + uint64_t o2sctrl1an_reserved_1 : 1; + uint64_t o2s_cpol_an : 1; + uint64_t o2s_cpha_an : 1; + uint64_t o2s_clock_divider_an : 10; + uint64_t o2sctrl1an_reserved_14_16 : 3; + uint64_t o2s_nr_of_frames_an : 1; + uint64_t reserved1 : 46; +#else + uint64_t reserved1 : 46; + uint64_t o2s_nr_of_frames_an : 1; + uint64_t o2sctrl1an_reserved_14_16 : 3; + uint64_t o2s_clock_divider_an : 10; + uint64_t o2s_cpha_an : 1; + uint64_t o2s_cpol_an : 1; + uint64_t o2sctrl1an_reserved_1 : 1; + uint64_t o2s_bridge_enable_an : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2sctrl11b_t; + + + +typedef union ocb_o2sctrl21b +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_inter_frame_delay_an : 17; + uint64_t reserved1 : 47; +#else + uint64_t reserved1 : 47; + uint64_t o2s_inter_frame_delay_an : 17; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2sctrl21b_t; + + + +typedef union ocb_o2sst1b +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_ongoing_an : 1; + uint64_t o2sstan_reserved_1_4 : 4; + uint64_t o2s_write_while_bridge_busy_err_an : 1; + uint64_t o2sstan_reserved_6 : 1; + uint64_t o2s_fsm_err_an : 1; + uint64_t reserved1 : 56; +#else + uint64_t reserved1 : 56; + uint64_t o2s_fsm_err_an : 1; + uint64_t o2sstan_reserved_6 : 1; + uint64_t o2s_write_while_bridge_busy_err_an : 1; + uint64_t o2sstan_reserved_1_4 : 4; + uint64_t o2s_ongoing_an : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2sst1b_t; + + + +typedef union ocb_o2scmd1b +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2scmdan_reserved_0 : 1; + uint64_t o2s_clear_sticky_bits_an : 1; + uint64_t reserved1 : 62; +#else + uint64_t reserved1 : 62; + uint64_t o2s_clear_sticky_bits_an : 1; + uint64_t o2scmdan_reserved_0 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2scmd1b_t; + + + +typedef union ocb_o2swd1b +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_wdata_an : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t o2s_wdata_an : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2swd1b_t; + + + +typedef union ocb_o2srd1b +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t o2s_rdata_an : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t o2s_rdata_an : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_o2srd1b_t; + + + +typedef union ocb_ocr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t core_reset : 1; + uint64_t chip_reset : 1; + uint64_t system_reset : 1; + uint64_t oci_arb_reset : 1; + uint64_t trace_disable : 1; + uint64_t trace_event : 1; + uint64_t dbg_unconditional_event : 1; + uint64_t ext_interrupt : 1; + uint64_t critical_interrupt : 1; + uint64_t pib_slave_reset_to_405_enable : 1; + uint64_t ocr_dbg_halt : 1; + uint64_t spare : 5; + uint64_t reserved1 : 48; +#else + uint64_t reserved1 : 48; + uint64_t spare : 5; + uint64_t ocr_dbg_halt : 1; + uint64_t pib_slave_reset_to_405_enable : 1; + uint64_t critical_interrupt : 1; + uint64_t ext_interrupt : 1; + uint64_t dbg_unconditional_event : 1; + uint64_t trace_event : 1; + uint64_t trace_disable : 1; + uint64_t oci_arb_reset : 1; + uint64_t system_reset : 1; + uint64_t chip_reset : 1; + uint64_t core_reset : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocr_t; + + + +typedef union ocb_ocr_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t core_reset : 1; + uint64_t chip_reset : 1; + uint64_t system_reset : 1; + uint64_t oci_arb_reset : 1; + uint64_t trace_disable : 1; + uint64_t trace_event : 1; + uint64_t dbg_unconditional_event : 1; + uint64_t ext_interrupt : 1; + uint64_t critical_interrupt : 1; + uint64_t pib_slave_reset_to_405_enable : 1; + uint64_t ocr_dbg_halt : 1; + uint64_t spare : 5; + uint64_t reserved1 : 48; +#else + uint64_t reserved1 : 48; + uint64_t spare : 5; + uint64_t ocr_dbg_halt : 1; + uint64_t pib_slave_reset_to_405_enable : 1; + uint64_t critical_interrupt : 1; + uint64_t ext_interrupt : 1; + uint64_t dbg_unconditional_event : 1; + uint64_t trace_event : 1; + uint64_t trace_disable : 1; + uint64_t oci_arb_reset : 1; + uint64_t system_reset : 1; + uint64_t chip_reset : 1; + uint64_t core_reset : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocr_clr_t; + + + +typedef union ocb_ocr_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t core_reset : 1; + uint64_t chip_reset : 1; + uint64_t system_reset : 1; + uint64_t oci_arb_reset : 1; + uint64_t trace_disable : 1; + uint64_t trace_event : 1; + uint64_t dbg_unconditional_event : 1; + uint64_t ext_interrupt : 1; + uint64_t critical_interrupt : 1; + uint64_t pib_slave_reset_to_405_enable : 1; + uint64_t ocr_dbg_halt : 1; + uint64_t spare : 5; + uint64_t reserved1 : 48; +#else + uint64_t reserved1 : 48; + uint64_t spare : 5; + uint64_t ocr_dbg_halt : 1; + uint64_t pib_slave_reset_to_405_enable : 1; + uint64_t critical_interrupt : 1; + uint64_t ext_interrupt : 1; + uint64_t dbg_unconditional_event : 1; + uint64_t trace_event : 1; + uint64_t trace_disable : 1; + uint64_t oci_arb_reset : 1; + uint64_t system_reset : 1; + uint64_t chip_reset : 1; + uint64_t core_reset : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocr_or_t; + + + +typedef union ocb_ocdbg +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t mst_dis_abusparen : 1; + uint64_t mst_dis_beparen : 1; + uint64_t mst_dis_wrdbusparen : 1; + uint64_t mst_dis_rddbuspar : 1; + uint64_t mst_spare : 1; + uint64_t slv_dis_sack : 1; + uint64_t slv_dis_abuspar : 1; + uint64_t slv_dis_bepar : 1; + uint64_t slv_dis_be : 1; + uint64_t slv_dis_wrdbuspar : 1; + uint64_t slv_dis_rddbusparen : 1; + uint64_t slv_spare : 1; + uint64_t spare : 4; + uint64_t reserved1 : 48; +#else + uint64_t reserved1 : 48; + uint64_t spare : 4; + uint64_t slv_spare : 1; + uint64_t slv_dis_rddbusparen : 1; + uint64_t slv_dis_wrdbuspar : 1; + uint64_t slv_dis_be : 1; + uint64_t slv_dis_bepar : 1; + uint64_t slv_dis_abuspar : 1; + uint64_t slv_dis_sack : 1; + uint64_t mst_spare : 1; + uint64_t mst_dis_rddbuspar : 1; + uint64_t mst_dis_wrdbusparen : 1; + uint64_t mst_dis_beparen : 1; + uint64_t mst_dis_abusparen : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocdbg_t; + + + +typedef union ocb_ojcfg +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t jtag_src_sel : 1; + uint64_t run_tck : 1; + uint64_t tck_width : 3; + uint64_t jtag_trst_b : 1; + uint64_t dbg_halt : 1; + uint64_t reserved1 : 57; +#else + uint64_t reserved1 : 57; + uint64_t dbg_halt : 1; + uint64_t jtag_trst_b : 1; + uint64_t tck_width : 3; + uint64_t run_tck : 1; + uint64_t jtag_src_sel : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ojcfg_t; + + + +typedef union ocb_ojcfg_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t jtag_src_sel : 1; + uint64_t run_tck : 1; + uint64_t tck_width : 3; + uint64_t jtag_trst_b : 1; + uint64_t dbg_halt : 1; + uint64_t reserved1 : 57; +#else + uint64_t reserved1 : 57; + uint64_t dbg_halt : 1; + uint64_t jtag_trst_b : 1; + uint64_t tck_width : 3; + uint64_t run_tck : 1; + uint64_t jtag_src_sel : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ojcfg_clr_t; + + + +typedef union ocb_ojcfg_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t jtag_src_sel : 1; + uint64_t run_tck : 1; + uint64_t tck_width : 3; + uint64_t jtag_trst_b : 1; + uint64_t dbg_halt : 1; + uint64_t reserved1 : 57; +#else + uint64_t reserved1 : 57; + uint64_t dbg_halt : 1; + uint64_t jtag_trst_b : 1; + uint64_t tck_width : 3; + uint64_t run_tck : 1; + uint64_t jtag_src_sel : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ojcfg_or_t; + + + +typedef union ocb_ojfrst +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t reserved1 : 64; +#else + uint64_t reserved1 : 64; +#endif // _BIG_ENDIAN + } fields; +} ocb_ojfrst_t; + + + +typedef union ocb_ojic +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t start_jtag_cmd : 1; + uint64_t do_ir : 1; + uint64_t do_dr : 1; + uint64_t do_tap_reset : 1; + uint64_t wr_valid : 1; + uint64_t reserved1 : 7; + uint64_t jtag_instr : 4; + uint64_t reserved2 : 48; +#else + uint64_t reserved2 : 48; + uint64_t jtag_instr : 4; + uint64_t reserved1 : 7; + uint64_t wr_valid : 1; + uint64_t do_tap_reset : 1; + uint64_t do_dr : 1; + uint64_t do_ir : 1; + uint64_t start_jtag_cmd : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ojic_t; + + + +typedef union ocb_ojic_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t start_jtag_cmd : 1; + uint64_t do_ir : 1; + uint64_t do_dr : 1; + uint64_t do_tap_reset : 1; + uint64_t wr_valid : 1; + uint64_t reserved1 : 7; + uint64_t jtag_instr : 4; + uint64_t reserved2 : 48; +#else + uint64_t reserved2 : 48; + uint64_t jtag_instr : 4; + uint64_t reserved1 : 7; + uint64_t wr_valid : 1; + uint64_t do_tap_reset : 1; + uint64_t do_dr : 1; + uint64_t do_ir : 1; + uint64_t start_jtag_cmd : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ojic_clr_t; + + + +typedef union ocb_ojic_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t start_jtag_cmd : 1; + uint64_t do_ir : 1; + uint64_t do_dr : 1; + uint64_t do_tap_reset : 1; + uint64_t wr_valid : 1; + uint64_t reserved1 : 7; + uint64_t jtag_instr : 4; + uint64_t reserved2 : 48; +#else + uint64_t reserved2 : 48; + uint64_t jtag_instr : 4; + uint64_t reserved1 : 7; + uint64_t wr_valid : 1; + uint64_t do_tap_reset : 1; + uint64_t do_dr : 1; + uint64_t do_ir : 1; + uint64_t start_jtag_cmd : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ojic_or_t; + + + +typedef union ocb_ojstat +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t jtag_inprog : 1; + uint64_t src_sel_eq1_err : 1; + uint64_t run_tck_eq0_err : 1; + uint64_t trst_b_eq0_err : 1; + uint64_t ir_dr_eq0_err : 1; + uint64_t inprog_wr_err : 1; + uint64_t fsm_error : 1; + uint64_t reserved1 : 57; +#else + uint64_t reserved1 : 57; + uint64_t fsm_error : 1; + uint64_t inprog_wr_err : 1; + uint64_t ir_dr_eq0_err : 1; + uint64_t trst_b_eq0_err : 1; + uint64_t run_tck_eq0_err : 1; + uint64_t src_sel_eq1_err : 1; + uint64_t jtag_inprog : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ojstat_t; + + + +typedef union ocb_ojtdi +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t jtag_tdi : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t jtag_tdi : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_ojtdi_t; + + + +typedef union ocb_ojtdo +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t jtag_tdo : 32; + uint64_t jtag_src_sel : 1; + uint64_t run_tck : 1; + uint64_t tck_width : 3; + uint64_t jtag_trst_b : 1; + uint64_t dbg_halt : 1; + uint64_t reserved1 : 1; + uint64_t jtag_inprog : 1; + uint64_t src_sel_eq1_err : 1; + uint64_t run_tck_eq0_err : 1; + uint64_t trst_b_eq0_err : 1; + uint64_t ir_dr_eq0_err : 1; + uint64_t inprog_wr_err : 1; + uint64_t fsm_error : 1; + uint64_t reserved2 : 2; + uint64_t do_ir : 1; + uint64_t do_dr : 1; + uint64_t do_tap_reset : 1; + uint64_t wr_valid : 1; + uint64_t reserved3 : 7; + uint64_t jtag_instr : 4; +#else + uint64_t jtag_instr : 4; + uint64_t reserved3 : 7; + uint64_t wr_valid : 1; + uint64_t do_tap_reset : 1; + uint64_t do_dr : 1; + uint64_t do_ir : 1; + uint64_t reserved2 : 2; + uint64_t fsm_error : 1; + uint64_t inprog_wr_err : 1; + uint64_t ir_dr_eq0_err : 1; + uint64_t trst_b_eq0_err : 1; + uint64_t run_tck_eq0_err : 1; + uint64_t src_sel_eq1_err : 1; + uint64_t jtag_inprog : 1; + uint64_t reserved1 : 1; + uint64_t dbg_halt : 1; + uint64_t jtag_trst_b : 1; + uint64_t tck_width : 3; + uint64_t run_tck : 1; + uint64_t jtag_src_sel : 1; + uint64_t jtag_tdo : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_ojtdo_t; + + + +typedef union ocb_ocbarn +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t oci_region : 3; + uint64_t ocb_address : 26; + uint64_t reserved1 : 35; +#else + uint64_t reserved1 : 35; + uint64_t ocb_address : 26; + uint64_t oci_region : 3; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbarn_t; + + + +typedef union ocb_ocbcsrn +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t pull_read_underflow : 1; + uint64_t push_write_overflow : 1; + uint64_t pull_read_underflow_en : 1; + uint64_t push_write_overflow_en : 1; + uint64_t ocb_stream_mode : 1; + uint64_t ocb_stream_type : 1; + uint64_t spare0 : 2; + uint64_t ocb_oci_timeout : 1; + uint64_t ocb_oci_read_data_parity : 1; + uint64_t ocb_oci_slave_error : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_pib_data_parity_err : 1; + uint64_t spare1 : 1; + uint64_t ocb_fsm_err : 1; + uint64_t spare2 : 1; + uint64_t reserved1 : 48; +#else + uint64_t reserved1 : 48; + uint64_t spare2 : 1; + uint64_t ocb_fsm_err : 1; + uint64_t spare1 : 1; + uint64_t ocb_pib_data_parity_err : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_oci_slave_error : 1; + uint64_t ocb_oci_read_data_parity : 1; + uint64_t ocb_oci_timeout : 1; + uint64_t spare0 : 2; + uint64_t ocb_stream_type : 1; + uint64_t ocb_stream_mode : 1; + uint64_t push_write_overflow_en : 1; + uint64_t pull_read_underflow_en : 1; + uint64_t push_write_overflow : 1; + uint64_t pull_read_underflow : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbcsrn_t; + + + +typedef union ocb_ocbcsrn_clr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t pull_read_underflow : 1; + uint64_t push_write_overflow : 1; + uint64_t pull_read_underflow_en : 1; + uint64_t push_write_overflow_en : 1; + uint64_t ocb_stream_mode : 1; + uint64_t ocb_stream_type : 1; + uint64_t spare0 : 2; + uint64_t ocb_oci_timeout : 1; + uint64_t ocb_oci_read_data_parity : 1; + uint64_t ocb_oci_slave_error : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_pib_data_parity_err : 1; + uint64_t spare1 : 1; + uint64_t ocb_fsm_err : 1; + uint64_t spare2 : 1; + uint64_t reserved1 : 48; +#else + uint64_t reserved1 : 48; + uint64_t spare2 : 1; + uint64_t ocb_fsm_err : 1; + uint64_t spare1 : 1; + uint64_t ocb_pib_data_parity_err : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_oci_slave_error : 1; + uint64_t ocb_oci_read_data_parity : 1; + uint64_t ocb_oci_timeout : 1; + uint64_t spare0 : 2; + uint64_t ocb_stream_type : 1; + uint64_t ocb_stream_mode : 1; + uint64_t push_write_overflow_en : 1; + uint64_t pull_read_underflow_en : 1; + uint64_t push_write_overflow : 1; + uint64_t pull_read_underflow : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbcsrn_clr_t; + + + +typedef union ocb_ocbcsrn_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t pull_read_underflow : 1; + uint64_t push_write_overflow : 1; + uint64_t pull_read_underflow_en : 1; + uint64_t push_write_overflow_en : 1; + uint64_t ocb_stream_mode : 1; + uint64_t ocb_stream_type : 1; + uint64_t spare0 : 2; + uint64_t ocb_oci_timeout : 1; + uint64_t ocb_oci_read_data_parity : 1; + uint64_t ocb_oci_slave_error : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_pib_data_parity_err : 1; + uint64_t spare1 : 1; + uint64_t ocb_fsm_err : 1; + uint64_t spare2 : 1; + uint64_t reserved1 : 48; +#else + uint64_t reserved1 : 48; + uint64_t spare2 : 1; + uint64_t ocb_fsm_err : 1; + uint64_t spare1 : 1; + uint64_t ocb_pib_data_parity_err : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_oci_slave_error : 1; + uint64_t ocb_oci_read_data_parity : 1; + uint64_t ocb_oci_timeout : 1; + uint64_t spare0 : 2; + uint64_t ocb_stream_type : 1; + uint64_t ocb_stream_mode : 1; + uint64_t push_write_overflow_en : 1; + uint64_t pull_read_underflow_en : 1; + uint64_t push_write_overflow : 1; + uint64_t pull_read_underflow : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbcsrn_or_t; + + + +typedef union ocb_ocbesrn +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t ocb_error_addr : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t ocb_error_addr : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbesrn_t; + + + +typedef union ocb_ocbdrn +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t ocb_data : 64; +#else + uint64_t ocb_data : 64; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbdrn_t; + + + +typedef union ocb_otdcr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t trace_bus_en : 1; + uint64_t ocb_trace_mux_sel : 1; + uint64_t occ_trace_mux_sel : 2; + uint64_t oci_trace_mux_sel : 4; + uint64_t reserved1 : 56; +#else + uint64_t reserved1 : 56; + uint64_t oci_trace_mux_sel : 4; + uint64_t occ_trace_mux_sel : 2; + uint64_t ocb_trace_mux_sel : 1; + uint64_t trace_bus_en : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_otdcr_t; + + + +typedef union ocb_oppcinj +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t oci_err_inj_dcu : 1; + uint64_t oci_err_inj_icu : 1; + uint64_t oci_err_inj_ce_ue : 1; + uint64_t oci_err_inj_singl_cont : 1; + uint64_t reserved1 : 60; +#else + uint64_t reserved1 : 60; + uint64_t oci_err_inj_singl_cont : 1; + uint64_t oci_err_inj_ce_ue : 1; + uint64_t oci_err_inj_icu : 1; + uint64_t oci_err_inj_dcu : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_oppcinj_t; + + + +typedef union ocb_ostoear +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t occ_spcl_timeout_addr : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t occ_spcl_timeout_addr : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_ostoear_t; + + + +typedef union ocb_ostoesr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t icu_timeout_error : 1; + uint64_t icu_rnw : 1; + uint64_t reserved1 : 2; + uint64_t dcu_timeout_error : 1; + uint64_t dcu_rnw : 1; + uint64_t reserved2 : 58; +#else + uint64_t reserved2 : 58; + uint64_t dcu_rnw : 1; + uint64_t dcu_timeout_error : 1; + uint64_t reserved1 : 2; + uint64_t icu_rnw : 1; + uint64_t icu_timeout_error : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ostoesr_t; + + + +typedef union ocb_orev +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t oci_arb_revision : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t oci_arb_revision : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_orev_t; + + + +typedef union ocb_oesr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t oci_m0_timeout_error : 1; + uint64_t oci_m0_rw_status : 1; + uint64_t oci_m0_oesr_flck : 1; + uint64_t oci_m0_oear_lock : 1; + uint64_t oci_m1_timeout_error : 1; + uint64_t oci_m1_rw_status : 1; + uint64_t oci_m1_oesr_flck : 1; + uint64_t oci_m1_oear_lock : 1; + uint64_t oci_m2_timeout_error : 1; + uint64_t oci_m2_rw_status : 1; + uint64_t oci_m2_oesr_flck : 1; + uint64_t oci_m2_oear_lock : 1; + uint64_t oci_m3_timeout_error : 1; + uint64_t oci_m3_rw_status : 1; + uint64_t oci_m3_oesr_flck : 1; + uint64_t oci_m3_oear_lock : 1; + uint64_t oci_m4_timeout_error : 1; + uint64_t oci_m4_rw_status : 1; + uint64_t oci_m4_oesr_flck : 1; + uint64_t oci_m4_oear_lock : 1; + uint64_t oci_m5_timeout_error : 1; + uint64_t oci_m5_rw_status : 1; + uint64_t oci_m5_oesr_flck : 1; + uint64_t oci_m5_oear_lock : 1; + uint64_t oci_m6_timeout_error : 1; + uint64_t oci_m6_rw_status : 1; + uint64_t oci_m6_oesr_flck : 1; + uint64_t oci_m6_oear_lock : 1; + uint64_t oci_m7_timeout_error : 1; + uint64_t oci_m7_rw_status : 1; + uint64_t oci_m7_oesr_flck : 1; + uint64_t oci_m7_oear_lock : 1; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t oci_m7_oear_lock : 1; + uint64_t oci_m7_oesr_flck : 1; + uint64_t oci_m7_rw_status : 1; + uint64_t oci_m7_timeout_error : 1; + uint64_t oci_m6_oear_lock : 1; + uint64_t oci_m6_oesr_flck : 1; + uint64_t oci_m6_rw_status : 1; + uint64_t oci_m6_timeout_error : 1; + uint64_t oci_m5_oear_lock : 1; + uint64_t oci_m5_oesr_flck : 1; + uint64_t oci_m5_rw_status : 1; + uint64_t oci_m5_timeout_error : 1; + uint64_t oci_m4_oear_lock : 1; + uint64_t oci_m4_oesr_flck : 1; + uint64_t oci_m4_rw_status : 1; + uint64_t oci_m4_timeout_error : 1; + uint64_t oci_m3_oear_lock : 1; + uint64_t oci_m3_oesr_flck : 1; + uint64_t oci_m3_rw_status : 1; + uint64_t oci_m3_timeout_error : 1; + uint64_t oci_m2_oear_lock : 1; + uint64_t oci_m2_oesr_flck : 1; + uint64_t oci_m2_rw_status : 1; + uint64_t oci_m2_timeout_error : 1; + uint64_t oci_m1_oear_lock : 1; + uint64_t oci_m1_oesr_flck : 1; + uint64_t oci_m1_rw_status : 1; + uint64_t oci_m1_timeout_error : 1; + uint64_t oci_m0_oear_lock : 1; + uint64_t oci_m0_oesr_flck : 1; + uint64_t oci_m0_rw_status : 1; + uint64_t oci_m0_timeout_error : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_oesr_t; + + + +typedef union ocb_oear +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t oci_timeout_addr : 32; + uint64_t reserved1 : 32; +#else + uint64_t reserved1 : 32; + uint64_t oci_timeout_addr : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oear_t; + + + +typedef union ocb_oacr +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t oci_priority_mode : 1; + uint64_t oci_priority_order : 3; + uint64_t oci_hi_bus_mode : 1; + uint64_t oci_read_pipeline_control : 2; + uint64_t oci_write_pipeline_control : 1; + uint64_t reserved1 : 56; +#else + uint64_t reserved1 : 56; + uint64_t oci_write_pipeline_control : 1; + uint64_t oci_read_pipeline_control : 2; + uint64_t oci_hi_bus_mode : 1; + uint64_t oci_priority_order : 3; + uint64_t oci_priority_mode : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_oacr_t; + + + +typedef union ocb_ocbear +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t ocb_error_address : 32; + uint64_t reserved1 : 3; + uint64_t direct_bridge_source : 1; + uint64_t indirect_bridge_0_source : 1; + uint64_t indirect_bridge_1_source : 1; + uint64_t indirect_bridge_2_source : 1; + uint64_t indirect_bridge_3_source : 1; + uint64_t reserved2 : 24; +#else + uint64_t reserved2 : 24; + uint64_t indirect_bridge_3_source : 1; + uint64_t indirect_bridge_2_source : 1; + uint64_t indirect_bridge_1_source : 1; + uint64_t indirect_bridge_0_source : 1; + uint64_t direct_bridge_source : 1; + uint64_t reserved1 : 3; + uint64_t ocb_error_address : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbear_t; + + + +typedef union ocb_occlfir +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t occ_fw0 : 1; + uint64_t occ_fw1 : 1; + uint64_t cme_error_notify : 1; + uint64_t stop_recovery_notify_prd : 1; + uint64_t occ_hb_error : 1; + uint64_t gpe0_watchdog_timeout : 1; + uint64_t gpe1_watchdog_timeout : 1; + uint64_t gpe2_watchdog_timeout : 1; + uint64_t gpe3_watchdog_timeout : 1; + uint64_t gpe0_error : 1; + uint64_t gpe1_error : 1; + uint64_t gpe2_error : 1; + uint64_t gpe3_error : 1; + uint64_t ocb_error : 1; + uint64_t srt_ue : 1; + uint64_t srt_ce : 1; + uint64_t srt_read_error : 1; + uint64_t srt_write_error : 1; + uint64_t srt_dataout_perr : 1; + uint64_t srt_oci_write_data_parity : 1; + uint64_t srt_oci_be_parity_err : 1; + uint64_t srt_oci_addr_parity_err : 1; + uint64_t gpe0_halted : 1; + uint64_t gpe1_halted : 1; + uint64_t gpe2_halted : 1; + uint64_t gpe3_halted : 1; + uint64_t external_trap : 1; + uint64_t ppc405_core_reset : 1; + uint64_t ppc405_chip_reset : 1; + uint64_t ppc405_system_reset : 1; + uint64_t ppc405_dbgmsrwe : 1; + uint64_t ppc405_dbgstopack : 1; + uint64_t ocb_db_oci_timeout : 1; + uint64_t ocb_db_oci_read_data_parity : 1; + uint64_t ocb_db_oci_slave_error : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_db_pib_data_parity_err : 1; + uint64_t ocb_idc0_error : 1; + uint64_t ocb_idc1_error : 1; + uint64_t ocb_idc2_error : 1; + uint64_t ocb_idc3_error : 1; + uint64_t srt_fsm_err : 1; + uint64_t jtagacc_err : 1; + uint64_t spare_err_38 : 1; + uint64_t c405_ecc_ue : 1; + uint64_t c405_ecc_ce : 1; + uint64_t c405_oci_machinecheck : 1; + uint64_t sram_spare_direct_error0 : 1; + uint64_t sram_spare_direct_error1 : 1; + uint64_t sram_spare_direct_error2 : 1; + uint64_t sram_spare_direct_error3 : 1; + uint64_t gpe0_ocislv_err : 1; + uint64_t gpe1_ocislv_err : 1; + uint64_t gpe2_ocislv_err : 1; + uint64_t gpe3_ocislv_err : 1; + uint64_t c405icu_m_timeout : 1; + uint64_t c405dcu_m_timeout : 1; + uint64_t occ_complex_fault_safe : 1; + uint64_t spare_58_61 : 4; + uint64_t fir_parity_err_dup : 1; + uint64_t fir_parity_err : 1; +#else + uint64_t fir_parity_err : 1; + uint64_t fir_parity_err_dup : 1; + uint64_t spare_58_61 : 4; + uint64_t occ_complex_fault_safe : 1; + uint64_t c405dcu_m_timeout : 1; + uint64_t c405icu_m_timeout : 1; + uint64_t gpe3_ocislv_err : 1; + uint64_t gpe2_ocislv_err : 1; + uint64_t gpe1_ocislv_err : 1; + uint64_t gpe0_ocislv_err : 1; + uint64_t sram_spare_direct_error3 : 1; + uint64_t sram_spare_direct_error2 : 1; + uint64_t sram_spare_direct_error1 : 1; + uint64_t sram_spare_direct_error0 : 1; + uint64_t c405_oci_machinecheck : 1; + uint64_t c405_ecc_ce : 1; + uint64_t c405_ecc_ue : 1; + uint64_t spare_err_38 : 1; + uint64_t jtagacc_err : 1; + uint64_t srt_fsm_err : 1; + uint64_t ocb_idc3_error : 1; + uint64_t ocb_idc2_error : 1; + uint64_t ocb_idc1_error : 1; + uint64_t ocb_idc0_error : 1; + uint64_t ocb_db_pib_data_parity_err : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_db_oci_slave_error : 1; + uint64_t ocb_db_oci_read_data_parity : 1; + uint64_t ocb_db_oci_timeout : 1; + uint64_t ppc405_dbgstopack : 1; + uint64_t ppc405_dbgmsrwe : 1; + uint64_t ppc405_system_reset : 1; + uint64_t ppc405_chip_reset : 1; + uint64_t ppc405_core_reset : 1; + uint64_t external_trap : 1; + uint64_t gpe3_halted : 1; + uint64_t gpe2_halted : 1; + uint64_t gpe1_halted : 1; + uint64_t gpe0_halted : 1; + uint64_t srt_oci_addr_parity_err : 1; + uint64_t srt_oci_be_parity_err : 1; + uint64_t srt_oci_write_data_parity : 1; + uint64_t srt_dataout_perr : 1; + uint64_t srt_write_error : 1; + uint64_t srt_read_error : 1; + uint64_t srt_ce : 1; + uint64_t srt_ue : 1; + uint64_t ocb_error : 1; + uint64_t gpe3_error : 1; + uint64_t gpe2_error : 1; + uint64_t gpe1_error : 1; + uint64_t gpe0_error : 1; + uint64_t gpe3_watchdog_timeout : 1; + uint64_t gpe2_watchdog_timeout : 1; + uint64_t gpe1_watchdog_timeout : 1; + uint64_t gpe0_watchdog_timeout : 1; + uint64_t occ_hb_error : 1; + uint64_t stop_recovery_notify_prd : 1; + uint64_t cme_error_notify : 1; + uint64_t occ_fw1 : 1; + uint64_t occ_fw0 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_occlfir_t; + + + +typedef union ocb_occlfir_and +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t occ_fw0 : 1; + uint64_t occ_fw1 : 1; + uint64_t cme_error_notify : 1; + uint64_t stop_recovery_notify_prd : 1; + uint64_t occ_hb_error : 1; + uint64_t gpe0_watchdog_timeout : 1; + uint64_t gpe1_watchdog_timeout : 1; + uint64_t gpe2_watchdog_timeout : 1; + uint64_t gpe3_watchdog_timeout : 1; + uint64_t gpe0_error : 1; + uint64_t gpe1_error : 1; + uint64_t gpe2_error : 1; + uint64_t gpe3_error : 1; + uint64_t ocb_error : 1; + uint64_t srt_ue : 1; + uint64_t srt_ce : 1; + uint64_t srt_read_error : 1; + uint64_t srt_write_error : 1; + uint64_t srt_dataout_perr : 1; + uint64_t srt_oci_write_data_parity : 1; + uint64_t srt_oci_be_parity_err : 1; + uint64_t srt_oci_addr_parity_err : 1; + uint64_t gpe0_halted : 1; + uint64_t gpe1_halted : 1; + uint64_t gpe2_halted : 1; + uint64_t gpe3_halted : 1; + uint64_t external_trap : 1; + uint64_t ppc405_core_reset : 1; + uint64_t ppc405_chip_reset : 1; + uint64_t ppc405_system_reset : 1; + uint64_t ppc405_dbgmsrwe : 1; + uint64_t ppc405_dbgstopack : 1; + uint64_t ocb_db_oci_timeout : 1; + uint64_t ocb_db_oci_read_data_parity : 1; + uint64_t ocb_db_oci_slave_error : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_db_pib_data_parity_err : 1; + uint64_t ocb_idc0_error : 1; + uint64_t ocb_idc1_error : 1; + uint64_t ocb_idc2_error : 1; + uint64_t ocb_idc3_error : 1; + uint64_t srt_fsm_err : 1; + uint64_t jtagacc_err : 1; + uint64_t spare_err_38 : 1; + uint64_t c405_ecc_ue : 1; + uint64_t c405_ecc_ce : 1; + uint64_t c405_oci_machinecheck : 1; + uint64_t sram_spare_direct_error0 : 1; + uint64_t sram_spare_direct_error1 : 1; + uint64_t sram_spare_direct_error2 : 1; + uint64_t sram_spare_direct_error3 : 1; + uint64_t gpe0_ocislv_err : 1; + uint64_t gpe1_ocislv_err : 1; + uint64_t gpe2_ocislv_err : 1; + uint64_t gpe3_ocislv_err : 1; + uint64_t c405icu_m_timeout : 1; + uint64_t c405dcu_m_timeout : 1; + uint64_t occ_complex_fault_safe : 1; + uint64_t spare_58_61 : 4; + uint64_t fir_parity_err_dup : 1; + uint64_t fir_parity_err : 1; +#else + uint64_t fir_parity_err : 1; + uint64_t fir_parity_err_dup : 1; + uint64_t spare_58_61 : 4; + uint64_t occ_complex_fault_safe : 1; + uint64_t c405dcu_m_timeout : 1; + uint64_t c405icu_m_timeout : 1; + uint64_t gpe3_ocislv_err : 1; + uint64_t gpe2_ocislv_err : 1; + uint64_t gpe1_ocislv_err : 1; + uint64_t gpe0_ocislv_err : 1; + uint64_t sram_spare_direct_error3 : 1; + uint64_t sram_spare_direct_error2 : 1; + uint64_t sram_spare_direct_error1 : 1; + uint64_t sram_spare_direct_error0 : 1; + uint64_t c405_oci_machinecheck : 1; + uint64_t c405_ecc_ce : 1; + uint64_t c405_ecc_ue : 1; + uint64_t spare_err_38 : 1; + uint64_t jtagacc_err : 1; + uint64_t srt_fsm_err : 1; + uint64_t ocb_idc3_error : 1; + uint64_t ocb_idc2_error : 1; + uint64_t ocb_idc1_error : 1; + uint64_t ocb_idc0_error : 1; + uint64_t ocb_db_pib_data_parity_err : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_db_oci_slave_error : 1; + uint64_t ocb_db_oci_read_data_parity : 1; + uint64_t ocb_db_oci_timeout : 1; + uint64_t ppc405_dbgstopack : 1; + uint64_t ppc405_dbgmsrwe : 1; + uint64_t ppc405_system_reset : 1; + uint64_t ppc405_chip_reset : 1; + uint64_t ppc405_core_reset : 1; + uint64_t external_trap : 1; + uint64_t gpe3_halted : 1; + uint64_t gpe2_halted : 1; + uint64_t gpe1_halted : 1; + uint64_t gpe0_halted : 1; + uint64_t srt_oci_addr_parity_err : 1; + uint64_t srt_oci_be_parity_err : 1; + uint64_t srt_oci_write_data_parity : 1; + uint64_t srt_dataout_perr : 1; + uint64_t srt_write_error : 1; + uint64_t srt_read_error : 1; + uint64_t srt_ce : 1; + uint64_t srt_ue : 1; + uint64_t ocb_error : 1; + uint64_t gpe3_error : 1; + uint64_t gpe2_error : 1; + uint64_t gpe1_error : 1; + uint64_t gpe0_error : 1; + uint64_t gpe3_watchdog_timeout : 1; + uint64_t gpe2_watchdog_timeout : 1; + uint64_t gpe1_watchdog_timeout : 1; + uint64_t gpe0_watchdog_timeout : 1; + uint64_t occ_hb_error : 1; + uint64_t stop_recovery_notify_prd : 1; + uint64_t cme_error_notify : 1; + uint64_t occ_fw1 : 1; + uint64_t occ_fw0 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_occlfir_and_t; + + + +typedef union ocb_occlfir_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t occ_fw0 : 1; + uint64_t occ_fw1 : 1; + uint64_t cme_error_notify : 1; + uint64_t stop_recovery_notify_prd : 1; + uint64_t occ_hb_error : 1; + uint64_t gpe0_watchdog_timeout : 1; + uint64_t gpe1_watchdog_timeout : 1; + uint64_t gpe2_watchdog_timeout : 1; + uint64_t gpe3_watchdog_timeout : 1; + uint64_t gpe0_error : 1; + uint64_t gpe1_error : 1; + uint64_t gpe2_error : 1; + uint64_t gpe3_error : 1; + uint64_t ocb_error : 1; + uint64_t srt_ue : 1; + uint64_t srt_ce : 1; + uint64_t srt_read_error : 1; + uint64_t srt_write_error : 1; + uint64_t srt_dataout_perr : 1; + uint64_t srt_oci_write_data_parity : 1; + uint64_t srt_oci_be_parity_err : 1; + uint64_t srt_oci_addr_parity_err : 1; + uint64_t gpe0_halted : 1; + uint64_t gpe1_halted : 1; + uint64_t gpe2_halted : 1; + uint64_t gpe3_halted : 1; + uint64_t external_trap : 1; + uint64_t ppc405_core_reset : 1; + uint64_t ppc405_chip_reset : 1; + uint64_t ppc405_system_reset : 1; + uint64_t ppc405_dbgmsrwe : 1; + uint64_t ppc405_dbgstopack : 1; + uint64_t ocb_db_oci_timeout : 1; + uint64_t ocb_db_oci_read_data_parity : 1; + uint64_t ocb_db_oci_slave_error : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_db_pib_data_parity_err : 1; + uint64_t ocb_idc0_error : 1; + uint64_t ocb_idc1_error : 1; + uint64_t ocb_idc2_error : 1; + uint64_t ocb_idc3_error : 1; + uint64_t srt_fsm_err : 1; + uint64_t jtagacc_err : 1; + uint64_t spare_err_38 : 1; + uint64_t c405_ecc_ue : 1; + uint64_t c405_ecc_ce : 1; + uint64_t c405_oci_machinecheck : 1; + uint64_t sram_spare_direct_error0 : 1; + uint64_t sram_spare_direct_error1 : 1; + uint64_t sram_spare_direct_error2 : 1; + uint64_t sram_spare_direct_error3 : 1; + uint64_t gpe0_ocislv_err : 1; + uint64_t gpe1_ocislv_err : 1; + uint64_t gpe2_ocislv_err : 1; + uint64_t gpe3_ocislv_err : 1; + uint64_t c405icu_m_timeout : 1; + uint64_t c405dcu_m_timeout : 1; + uint64_t occ_complex_fault_safe : 1; + uint64_t spare_58_61 : 4; + uint64_t fir_parity_err_dup : 1; + uint64_t fir_parity_err : 1; +#else + uint64_t fir_parity_err : 1; + uint64_t fir_parity_err_dup : 1; + uint64_t spare_58_61 : 4; + uint64_t occ_complex_fault_safe : 1; + uint64_t c405dcu_m_timeout : 1; + uint64_t c405icu_m_timeout : 1; + uint64_t gpe3_ocislv_err : 1; + uint64_t gpe2_ocislv_err : 1; + uint64_t gpe1_ocislv_err : 1; + uint64_t gpe0_ocislv_err : 1; + uint64_t sram_spare_direct_error3 : 1; + uint64_t sram_spare_direct_error2 : 1; + uint64_t sram_spare_direct_error1 : 1; + uint64_t sram_spare_direct_error0 : 1; + uint64_t c405_oci_machinecheck : 1; + uint64_t c405_ecc_ce : 1; + uint64_t c405_ecc_ue : 1; + uint64_t spare_err_38 : 1; + uint64_t jtagacc_err : 1; + uint64_t srt_fsm_err : 1; + uint64_t ocb_idc3_error : 1; + uint64_t ocb_idc2_error : 1; + uint64_t ocb_idc1_error : 1; + uint64_t ocb_idc0_error : 1; + uint64_t ocb_db_pib_data_parity_err : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_db_oci_slave_error : 1; + uint64_t ocb_db_oci_read_data_parity : 1; + uint64_t ocb_db_oci_timeout : 1; + uint64_t ppc405_dbgstopack : 1; + uint64_t ppc405_dbgmsrwe : 1; + uint64_t ppc405_system_reset : 1; + uint64_t ppc405_chip_reset : 1; + uint64_t ppc405_core_reset : 1; + uint64_t external_trap : 1; + uint64_t gpe3_halted : 1; + uint64_t gpe2_halted : 1; + uint64_t gpe1_halted : 1; + uint64_t gpe0_halted : 1; + uint64_t srt_oci_addr_parity_err : 1; + uint64_t srt_oci_be_parity_err : 1; + uint64_t srt_oci_write_data_parity : 1; + uint64_t srt_dataout_perr : 1; + uint64_t srt_write_error : 1; + uint64_t srt_read_error : 1; + uint64_t srt_ce : 1; + uint64_t srt_ue : 1; + uint64_t ocb_error : 1; + uint64_t gpe3_error : 1; + uint64_t gpe2_error : 1; + uint64_t gpe1_error : 1; + uint64_t gpe0_error : 1; + uint64_t gpe3_watchdog_timeout : 1; + uint64_t gpe2_watchdog_timeout : 1; + uint64_t gpe1_watchdog_timeout : 1; + uint64_t gpe0_watchdog_timeout : 1; + uint64_t occ_hb_error : 1; + uint64_t stop_recovery_notify_prd : 1; + uint64_t cme_error_notify : 1; + uint64_t occ_fw1 : 1; + uint64_t occ_fw0 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_occlfir_or_t; + + + +typedef union ocb_occlfirmask +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t occ_fw0_mask : 1; + uint64_t occ_fw1_mask : 1; + uint64_t spare_2_mask : 1; + uint64_t spare_3_mask : 1; + uint64_t occ_hb_malf_mask : 1; + uint64_t gpe0_watchdog_timeout_mask : 1; + uint64_t gpe1_watchdog_timeout_mask : 1; + uint64_t gpe2_watchdog_timeout_mask : 1; + uint64_t gpe3_watchdog_timeout_mask : 1; + uint64_t gpe0_error_mask : 1; + uint64_t gpe1_error_mask : 1; + uint64_t gpe2_error_mask : 1; + uint64_t gpe3_error_mask : 1; + uint64_t ocb_error_mask : 1; + uint64_t srt_ue_mask : 1; + uint64_t srt_ce_mask : 1; + uint64_t srt_read_error_mask : 1; + uint64_t srt_write_error_mask : 1; + uint64_t srt_dataout_perr_mask : 1; + uint64_t srt_oci_write_data_parity_mask : 1; + uint64_t srt_oci_be_parity_err_mask : 1; + uint64_t srt_oci_addr_parity_err_mask : 1; + uint64_t gpe0_halted_mask : 1; + uint64_t gpe1_halted_mask : 1; + uint64_t gpe2_halted_mask : 1; + uint64_t gpe3_halted_mask : 1; + uint64_t external_trap_mask : 1; + uint64_t ppc405_core_reset_mask : 1; + uint64_t ppc405_chip_reset_mask : 1; + uint64_t ppc405_system_reset_mask : 1; + uint64_t ppc405_dbgmsrwe_mask : 1; + uint64_t ppc405_dbgstopack_mask : 1; + uint64_t ocb_db_oci_timeout_mask : 1; + uint64_t ocb_db_oci_read_data_parity_mask : 1; + uint64_t ocb_db_oci_slave_error_mask : 1; + uint64_t ocb_pib_addr_parity_err_mask : 1; + uint64_t ocb_db_pib_data_parity_err_mask : 1; + uint64_t ocb_idc0_error_mask : 1; + uint64_t ocb_idc1_error_mask : 1; + uint64_t ocb_idc2_error_mask : 1; + uint64_t ocb_idc3_error_mask : 1; + uint64_t srt_fsm_err_mask : 1; + uint64_t jtagacc_err_mask : 1; + uint64_t spare_err_38_mask : 1; + uint64_t c405_ecc_ue_mask : 1; + uint64_t c405_ecc_ce_mask : 1; + uint64_t c405_oci_machinecheck_mask : 1; + uint64_t sram_spare_direct_error0_mask : 1; + uint64_t sram_spare_direct_error1_mask : 1; + uint64_t sram_spare_direct_error2_mask : 1; + uint64_t sram_spare_direct_error3_mask : 1; + uint64_t gpe0_ocislv_err_mask : 1; + uint64_t gpe1_ocislv_err_mask : 1; + uint64_t gpe2_ocislv_err_mask : 1; + uint64_t gpe3_ocislv_err_mask : 1; + uint64_t c405icu_m_timeout_mask : 1; + uint64_t c405dcu_m_timeout_mask : 1; + uint64_t occ_complex_fault_safe_mask : 1; + uint64_t spare_58_61_mask : 4; + uint64_t fir_parity_err_dup_mask : 1; + uint64_t fir_parity_err_mask : 1; +#else + uint64_t fir_parity_err_mask : 1; + uint64_t fir_parity_err_dup_mask : 1; + uint64_t spare_58_61_mask : 4; + uint64_t occ_complex_fault_safe_mask : 1; + uint64_t c405dcu_m_timeout_mask : 1; + uint64_t c405icu_m_timeout_mask : 1; + uint64_t gpe3_ocislv_err_mask : 1; + uint64_t gpe2_ocislv_err_mask : 1; + uint64_t gpe1_ocislv_err_mask : 1; + uint64_t gpe0_ocislv_err_mask : 1; + uint64_t sram_spare_direct_error3_mask : 1; + uint64_t sram_spare_direct_error2_mask : 1; + uint64_t sram_spare_direct_error1_mask : 1; + uint64_t sram_spare_direct_error0_mask : 1; + uint64_t c405_oci_machinecheck_mask : 1; + uint64_t c405_ecc_ce_mask : 1; + uint64_t c405_ecc_ue_mask : 1; + uint64_t spare_err_38_mask : 1; + uint64_t jtagacc_err_mask : 1; + uint64_t srt_fsm_err_mask : 1; + uint64_t ocb_idc3_error_mask : 1; + uint64_t ocb_idc2_error_mask : 1; + uint64_t ocb_idc1_error_mask : 1; + uint64_t ocb_idc0_error_mask : 1; + uint64_t ocb_db_pib_data_parity_err_mask : 1; + uint64_t ocb_pib_addr_parity_err_mask : 1; + uint64_t ocb_db_oci_slave_error_mask : 1; + uint64_t ocb_db_oci_read_data_parity_mask : 1; + uint64_t ocb_db_oci_timeout_mask : 1; + uint64_t ppc405_dbgstopack_mask : 1; + uint64_t ppc405_dbgmsrwe_mask : 1; + uint64_t ppc405_system_reset_mask : 1; + uint64_t ppc405_chip_reset_mask : 1; + uint64_t ppc405_core_reset_mask : 1; + uint64_t external_trap_mask : 1; + uint64_t gpe3_halted_mask : 1; + uint64_t gpe2_halted_mask : 1; + uint64_t gpe1_halted_mask : 1; + uint64_t gpe0_halted_mask : 1; + uint64_t srt_oci_addr_parity_err_mask : 1; + uint64_t srt_oci_be_parity_err_mask : 1; + uint64_t srt_oci_write_data_parity_mask : 1; + uint64_t srt_dataout_perr_mask : 1; + uint64_t srt_write_error_mask : 1; + uint64_t srt_read_error_mask : 1; + uint64_t srt_ce_mask : 1; + uint64_t srt_ue_mask : 1; + uint64_t ocb_error_mask : 1; + uint64_t gpe3_error_mask : 1; + uint64_t gpe2_error_mask : 1; + uint64_t gpe1_error_mask : 1; + uint64_t gpe0_error_mask : 1; + uint64_t gpe3_watchdog_timeout_mask : 1; + uint64_t gpe2_watchdog_timeout_mask : 1; + uint64_t gpe1_watchdog_timeout_mask : 1; + uint64_t gpe0_watchdog_timeout_mask : 1; + uint64_t occ_hb_malf_mask : 1; + uint64_t spare_3_mask : 1; + uint64_t spare_2_mask : 1; + uint64_t occ_fw1_mask : 1; + uint64_t occ_fw0_mask : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_occlfirmask_t; + + + +typedef union ocb_occlfirmask_and +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t occ_fw0_mask : 1; + uint64_t occ_fw1_mask : 1; + uint64_t spare_2_mask : 1; + uint64_t spare_3_mask : 1; + uint64_t occ_hb_malf_mask : 1; + uint64_t gpe0_watchdog_timeout_mask : 1; + uint64_t gpe1_watchdog_timeout_mask : 1; + uint64_t gpe2_watchdog_timeout_mask : 1; + uint64_t gpe3_watchdog_timeout_mask : 1; + uint64_t gpe0_error_mask : 1; + uint64_t gpe1_error_mask : 1; + uint64_t gpe2_error_mask : 1; + uint64_t gpe3_error_mask : 1; + uint64_t ocb_error_mask : 1; + uint64_t srt_ue_mask : 1; + uint64_t srt_ce_mask : 1; + uint64_t srt_read_error_mask : 1; + uint64_t srt_write_error_mask : 1; + uint64_t srt_dataout_perr_mask : 1; + uint64_t srt_oci_write_data_parity_mask : 1; + uint64_t srt_oci_be_parity_err_mask : 1; + uint64_t srt_oci_addr_parity_err_mask : 1; + uint64_t gpe0_halted_mask : 1; + uint64_t gpe1_halted_mask : 1; + uint64_t gpe2_halted_mask : 1; + uint64_t gpe3_halted_mask : 1; + uint64_t external_trap_mask : 1; + uint64_t ppc405_core_reset_mask : 1; + uint64_t ppc405_chip_reset_mask : 1; + uint64_t ppc405_system_reset_mask : 1; + uint64_t ppc405_dbgmsrwe_mask : 1; + uint64_t ppc405_dbgstopack_mask : 1; + uint64_t ocb_db_oci_timeout_mask : 1; + uint64_t ocb_db_oci_read_data_parity_mask : 1; + uint64_t ocb_db_oci_slave_error_mask : 1; + uint64_t ocb_pib_addr_parity_err_mask : 1; + uint64_t ocb_db_pib_data_parity_err_mask : 1; + uint64_t ocb_idc0_error_mask : 1; + uint64_t ocb_idc1_error_mask : 1; + uint64_t ocb_idc2_error_mask : 1; + uint64_t ocb_idc3_error_mask : 1; + uint64_t srt_fsm_err_mask : 1; + uint64_t jtagacc_err_mask : 1; + uint64_t spare_err_38_mask : 1; + uint64_t c405_ecc_ue_mask : 1; + uint64_t c405_ecc_ce_mask : 1; + uint64_t c405_oci_machinecheck_mask : 1; + uint64_t sram_spare_direct_error0_mask : 1; + uint64_t sram_spare_direct_error1_mask : 1; + uint64_t sram_spare_direct_error2_mask : 1; + uint64_t sram_spare_direct_error3_mask : 1; + uint64_t gpe0_ocislv_err_mask : 1; + uint64_t gpe1_ocislv_err_mask : 1; + uint64_t gpe2_ocislv_err_mask : 1; + uint64_t gpe3_ocislv_err_mask : 1; + uint64_t c405icu_m_timeout_mask : 1; + uint64_t c405dcu_m_timeout_mask : 1; + uint64_t occ_complex_fault_safe_mask : 1; + uint64_t spare_58_61_mask : 4; + uint64_t fir_parity_err_dup_mask : 1; + uint64_t fir_parity_err_mask : 1; +#else + uint64_t fir_parity_err_mask : 1; + uint64_t fir_parity_err_dup_mask : 1; + uint64_t spare_58_61_mask : 4; + uint64_t occ_complex_fault_safe_mask : 1; + uint64_t c405dcu_m_timeout_mask : 1; + uint64_t c405icu_m_timeout_mask : 1; + uint64_t gpe3_ocislv_err_mask : 1; + uint64_t gpe2_ocislv_err_mask : 1; + uint64_t gpe1_ocislv_err_mask : 1; + uint64_t gpe0_ocislv_err_mask : 1; + uint64_t sram_spare_direct_error3_mask : 1; + uint64_t sram_spare_direct_error2_mask : 1; + uint64_t sram_spare_direct_error1_mask : 1; + uint64_t sram_spare_direct_error0_mask : 1; + uint64_t c405_oci_machinecheck_mask : 1; + uint64_t c405_ecc_ce_mask : 1; + uint64_t c405_ecc_ue_mask : 1; + uint64_t spare_err_38_mask : 1; + uint64_t jtagacc_err_mask : 1; + uint64_t srt_fsm_err_mask : 1; + uint64_t ocb_idc3_error_mask : 1; + uint64_t ocb_idc2_error_mask : 1; + uint64_t ocb_idc1_error_mask : 1; + uint64_t ocb_idc0_error_mask : 1; + uint64_t ocb_db_pib_data_parity_err_mask : 1; + uint64_t ocb_pib_addr_parity_err_mask : 1; + uint64_t ocb_db_oci_slave_error_mask : 1; + uint64_t ocb_db_oci_read_data_parity_mask : 1; + uint64_t ocb_db_oci_timeout_mask : 1; + uint64_t ppc405_dbgstopack_mask : 1; + uint64_t ppc405_dbgmsrwe_mask : 1; + uint64_t ppc405_system_reset_mask : 1; + uint64_t ppc405_chip_reset_mask : 1; + uint64_t ppc405_core_reset_mask : 1; + uint64_t external_trap_mask : 1; + uint64_t gpe3_halted_mask : 1; + uint64_t gpe2_halted_mask : 1; + uint64_t gpe1_halted_mask : 1; + uint64_t gpe0_halted_mask : 1; + uint64_t srt_oci_addr_parity_err_mask : 1; + uint64_t srt_oci_be_parity_err_mask : 1; + uint64_t srt_oci_write_data_parity_mask : 1; + uint64_t srt_dataout_perr_mask : 1; + uint64_t srt_write_error_mask : 1; + uint64_t srt_read_error_mask : 1; + uint64_t srt_ce_mask : 1; + uint64_t srt_ue_mask : 1; + uint64_t ocb_error_mask : 1; + uint64_t gpe3_error_mask : 1; + uint64_t gpe2_error_mask : 1; + uint64_t gpe1_error_mask : 1; + uint64_t gpe0_error_mask : 1; + uint64_t gpe3_watchdog_timeout_mask : 1; + uint64_t gpe2_watchdog_timeout_mask : 1; + uint64_t gpe1_watchdog_timeout_mask : 1; + uint64_t gpe0_watchdog_timeout_mask : 1; + uint64_t occ_hb_malf_mask : 1; + uint64_t spare_3_mask : 1; + uint64_t spare_2_mask : 1; + uint64_t occ_fw1_mask : 1; + uint64_t occ_fw0_mask : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_occlfirmask_and_t; + + + +typedef union ocb_occlfirmask_or +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t occ_fw0_mask : 1; + uint64_t occ_fw1_mask : 1; + uint64_t spare_2_mask : 1; + uint64_t spare_3_mask : 1; + uint64_t occ_hb_malf_mask : 1; + uint64_t gpe0_watchdog_timeout_mask : 1; + uint64_t gpe1_watchdog_timeout_mask : 1; + uint64_t gpe2_watchdog_timeout_mask : 1; + uint64_t gpe3_watchdog_timeout_mask : 1; + uint64_t gpe0_error_mask : 1; + uint64_t gpe1_error_mask : 1; + uint64_t gpe2_error_mask : 1; + uint64_t gpe3_error_mask : 1; + uint64_t ocb_error_mask : 1; + uint64_t srt_ue_mask : 1; + uint64_t srt_ce_mask : 1; + uint64_t srt_read_error_mask : 1; + uint64_t srt_write_error_mask : 1; + uint64_t srt_dataout_perr_mask : 1; + uint64_t srt_oci_write_data_parity_mask : 1; + uint64_t srt_oci_be_parity_err_mask : 1; + uint64_t srt_oci_addr_parity_err_mask : 1; + uint64_t gpe0_halted_mask : 1; + uint64_t gpe1_halted_mask : 1; + uint64_t gpe2_halted_mask : 1; + uint64_t gpe3_halted_mask : 1; + uint64_t external_trap_mask : 1; + uint64_t ppc405_core_reset_mask : 1; + uint64_t ppc405_chip_reset_mask : 1; + uint64_t ppc405_system_reset_mask : 1; + uint64_t ppc405_dbgmsrwe_mask : 1; + uint64_t ppc405_dbgstopack_mask : 1; + uint64_t ocb_db_oci_timeout_mask : 1; + uint64_t ocb_db_oci_read_data_parity_mask : 1; + uint64_t ocb_db_oci_slave_error_mask : 1; + uint64_t ocb_pib_addr_parity_err_mask : 1; + uint64_t ocb_db_pib_data_parity_err_mask : 1; + uint64_t ocb_idc0_error_mask : 1; + uint64_t ocb_idc1_error_mask : 1; + uint64_t ocb_idc2_error_mask : 1; + uint64_t ocb_idc3_error_mask : 1; + uint64_t srt_fsm_err_mask : 1; + uint64_t jtagacc_err_mask : 1; + uint64_t spare_err_38_mask : 1; + uint64_t c405_ecc_ue_mask : 1; + uint64_t c405_ecc_ce_mask : 1; + uint64_t c405_oci_machinecheck_mask : 1; + uint64_t sram_spare_direct_error0_mask : 1; + uint64_t sram_spare_direct_error1_mask : 1; + uint64_t sram_spare_direct_error2_mask : 1; + uint64_t sram_spare_direct_error3_mask : 1; + uint64_t gpe0_ocislv_err_mask : 1; + uint64_t gpe1_ocislv_err_mask : 1; + uint64_t gpe2_ocislv_err_mask : 1; + uint64_t gpe3_ocislv_err_mask : 1; + uint64_t c405icu_m_timeout_mask : 1; + uint64_t c405dcu_m_timeout_mask : 1; + uint64_t occ_complex_fault_safe_mask : 1; + uint64_t spare_58_61_mask : 4; + uint64_t fir_parity_err_dup_mask : 1; + uint64_t fir_parity_err_mask : 1; +#else + uint64_t fir_parity_err_mask : 1; + uint64_t fir_parity_err_dup_mask : 1; + uint64_t spare_58_61_mask : 4; + uint64_t occ_complex_fault_safe_mask : 1; + uint64_t c405dcu_m_timeout_mask : 1; + uint64_t c405icu_m_timeout_mask : 1; + uint64_t gpe3_ocislv_err_mask : 1; + uint64_t gpe2_ocislv_err_mask : 1; + uint64_t gpe1_ocislv_err_mask : 1; + uint64_t gpe0_ocislv_err_mask : 1; + uint64_t sram_spare_direct_error3_mask : 1; + uint64_t sram_spare_direct_error2_mask : 1; + uint64_t sram_spare_direct_error1_mask : 1; + uint64_t sram_spare_direct_error0_mask : 1; + uint64_t c405_oci_machinecheck_mask : 1; + uint64_t c405_ecc_ce_mask : 1; + uint64_t c405_ecc_ue_mask : 1; + uint64_t spare_err_38_mask : 1; + uint64_t jtagacc_err_mask : 1; + uint64_t srt_fsm_err_mask : 1; + uint64_t ocb_idc3_error_mask : 1; + uint64_t ocb_idc2_error_mask : 1; + uint64_t ocb_idc1_error_mask : 1; + uint64_t ocb_idc0_error_mask : 1; + uint64_t ocb_db_pib_data_parity_err_mask : 1; + uint64_t ocb_pib_addr_parity_err_mask : 1; + uint64_t ocb_db_oci_slave_error_mask : 1; + uint64_t ocb_db_oci_read_data_parity_mask : 1; + uint64_t ocb_db_oci_timeout_mask : 1; + uint64_t ppc405_dbgstopack_mask : 1; + uint64_t ppc405_dbgmsrwe_mask : 1; + uint64_t ppc405_system_reset_mask : 1; + uint64_t ppc405_chip_reset_mask : 1; + uint64_t ppc405_core_reset_mask : 1; + uint64_t external_trap_mask : 1; + uint64_t gpe3_halted_mask : 1; + uint64_t gpe2_halted_mask : 1; + uint64_t gpe1_halted_mask : 1; + uint64_t gpe0_halted_mask : 1; + uint64_t srt_oci_addr_parity_err_mask : 1; + uint64_t srt_oci_be_parity_err_mask : 1; + uint64_t srt_oci_write_data_parity_mask : 1; + uint64_t srt_dataout_perr_mask : 1; + uint64_t srt_write_error_mask : 1; + uint64_t srt_read_error_mask : 1; + uint64_t srt_ce_mask : 1; + uint64_t srt_ue_mask : 1; + uint64_t ocb_error_mask : 1; + uint64_t gpe3_error_mask : 1; + uint64_t gpe2_error_mask : 1; + uint64_t gpe1_error_mask : 1; + uint64_t gpe0_error_mask : 1; + uint64_t gpe3_watchdog_timeout_mask : 1; + uint64_t gpe2_watchdog_timeout_mask : 1; + uint64_t gpe1_watchdog_timeout_mask : 1; + uint64_t gpe0_watchdog_timeout_mask : 1; + uint64_t occ_hb_malf_mask : 1; + uint64_t spare_3_mask : 1; + uint64_t spare_2_mask : 1; + uint64_t occ_fw1_mask : 1; + uint64_t occ_fw0_mask : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_occlfirmask_or_t; + + + +typedef union ocb_occlfiract0 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t fir_action0 : 64; +#else + uint64_t fir_action0 : 64; +#endif // _BIG_ENDIAN + } fields; +} ocb_occlfiract0_t; + + + +typedef union ocb_occlfiract1 +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t fir_action1 : 64; +#else + uint64_t fir_action1 : 64; +#endif // _BIG_ENDIAN + } fields; +} ocb_occlfiract1_t; + + + +typedef union ocb_occlfirwof +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t wof : 64; +#else + uint64_t wof : 64; +#endif // _BIG_ENDIAN + } fields; +} ocb_occlfirwof_t; + + + +typedef union ocb_occerrrpt +{ + + uint64_t value; + struct + { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct + { +#ifdef _BIG_ENDIAN + uint64_t sram_cerrrpt : 10; + uint64_t jtagacc_cerrpt : 6; + uint64_t c405_dcu_ecc_ue : 1; + uint64_t c405_dcu_ecc_ce : 1; + uint64_t c405_icu_ecc_ue : 1; + uint64_t c405_icu_ecc_ce : 1; + uint64_t gpe0_ocislv_err : 7; + uint64_t reserved1 : 1; + uint64_t gpe1_ocislv_err : 7; + uint64_t reserved2 : 1; + uint64_t gpe2_ocislv_err : 7; + uint64_t reserved3 : 1; + uint64_t gpe3_ocislv_err : 7; + uint64_t reserved4 : 1; + uint64_t ocb_ocislv_err : 7; + uint64_t reserved5 : 5; +#else + uint64_t reserved5 : 5; + uint64_t ocb_ocislv_err : 7; + uint64_t reserved4 : 1; + uint64_t gpe3_ocislv_err : 7; + uint64_t reserved3 : 1; + uint64_t gpe2_ocislv_err : 7; + uint64_t reserved2 : 1; + uint64_t gpe1_ocislv_err : 7; + uint64_t reserved1 : 1; + uint64_t gpe0_ocislv_err : 7; + uint64_t c405_icu_ecc_ce : 1; + uint64_t c405_icu_ecc_ue : 1; + uint64_t c405_dcu_ecc_ce : 1; + uint64_t c405_dcu_ecc_ue : 1; + uint64_t jtagacc_cerrpt : 6; + uint64_t sram_cerrrpt : 10; +#endif // _BIG_ENDIAN + } fields; +} ocb_occerrrpt_t; + + +#endif // __ASSEMBLER__ +#endif // P9_OCB_FIRMWARE_REGISTERS_H__ + |
