diff options
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C | 21 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml | 16 |
2 files changed, 34 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C index 2f13f38cd..23eca6ac6 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C @@ -1553,7 +1553,8 @@ fapi2::ReturnCode EffGroupingBaseSizeData::set_HTM_OCC_base_addr( } // Setting NHTM & OCC base addresses - if ( (l_nhtmSize + l_chtmSize) < i_procAttrs.iv_occSandboxSize) + // Set larger allocations on top (at higher addresses) + if ( (l_nhtmSize + l_chtmSize) >= i_procAttrs.iv_occSandboxSize) { iv_occ_sandbox_base = l_mem_bases[l_index] + l_mem_sizes[l_index]; iv_nhtm_bar_base = iv_occ_sandbox_base + i_procAttrs.iv_occSandboxSize; @@ -1564,6 +1565,22 @@ fapi2::ReturnCode EffGroupingBaseSizeData::set_HTM_OCC_base_addr( iv_occ_sandbox_base = iv_nhtm_bar_base + l_nhtmSize + l_chtmSize; } + // Verify NHTM base addresses aligned with allocated size. + // The OCC sandbox base is just a FW scratch area and no HW + // functions mapped to it so we don't need to check its base alignment. + if (iv_nhtm_bar_base & (l_nhtmSize + l_chtmSize - 1) ) + { + FAPI_ASSERT(false, + fapi2::MSS_EFF_GROUPING_ADDRESS_NOT_ALIGNED() + .set_NHTM_BAR_BASE(iv_nhtm_bar_base) + .set_NHTM_SIZE(l_nhtmSize) + .set_CHTM_SIZE(l_chtmSize), + "EffGroupingBaseSizeData::set_HTM_OCC_base_addr: " + "NHTM BAR base address is not aligned with its size " + "NHTM_BAR_BASE 0x%.16llX, NHTM_SIZE 0x%.16llX, CTHM_SIZE 0x%.16llX", + iv_nhtm_bar_base, l_nhtmSize, l_chtmSize); + } + // Setting CHTM base addresses for (uint8_t ii = 0; ii < NUM_OF_CHTM_REGIONS; ii++) { @@ -1839,7 +1856,7 @@ fapi2::ReturnCode EffGroupingBaseSizeData::setSMFBaseSizeData( ii, l_mem_bases[ii], l_mem_sizes[ii]); } - FAPI_INF("SMF_BASE %.16lld (%d GB)", iv_smf_bar_base, iv_smf_bar_base >> 30); + FAPI_INF("SMF_BASE 0x%.16llX", iv_smf_bar_base); for (uint8_t ii = 0; ii < l_numRegions; ii++) { diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml index 5147e960f..5a5764e97 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2015,2018 --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2019 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -239,4 +239,18 @@ </callout> </hwpError> +<hwpError> + <rc>RC_MSS_EFF_GROUPING_ADDRESS_NOT_ALIGNED</rc> + <description> + NHTM BAR address is not aligned with requested size. + </description> + <ffdc>NHTM_BAR_BASE</ffdc> + <ffdc>NHTM_SIZE</ffdc> + <ffdc>CHTM_SIZE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> +</hwpError> + </hwpErrors> |
