diff options
| -rw-r--r-- | src/include/usr/hwpf/istepreasoncodes.H | 2 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.C | 51 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/start_payload/makefile | 1 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/start_payload/start_payload.C | 170 |
4 files changed, 216 insertions, 8 deletions
diff --git a/src/include/usr/hwpf/istepreasoncodes.H b/src/include/usr/hwpf/istepreasoncodes.H index 960230ba9..e5f27ec8c 100644 --- a/src/include/usr/hwpf/istepreasoncodes.H +++ b/src/include/usr/hwpf/istepreasoncodes.H @@ -53,6 +53,7 @@ enum istepModuleId ISTEP_PROC_SET_PORE_BAR = 0x05, ISTEP_HOST_ACTIVATE_MASTER = 0x06, ISTEP_SBE_CENTAUR_INIT = 0x07, + ISTEP_ENABLE_CORE_CHECKSTOPS = 0x08, }; /** @@ -71,6 +72,7 @@ enum istepReasonCode ISTEP_MM_UNMAP_ERR = ISTEP_COMP_ID | 0x05, ISTEP_LOAD_SLW_FROM_PNOR_FAILED = ISTEP_COMP_ID | 0x06, ISTEP_REPAIR_LOADER_RETRY_OCCURED = ISTEP_COMP_ID | 0x07, + ISTEP_MM_MAP_ERR = ISTEP_COMP_ID | 0x08, }; // end ISTEP } diff --git a/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.C b/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.C index 37f290468..7554598a1 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.C +++ b/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.C @@ -164,14 +164,14 @@ errlHndl_t loadPoreImage( char *& o_rporeAddr, * @brief apply cpu reg information to the SLW image using * p8_pore_gen_cpureg() . * - * @param i_cpuTarget - proc target + * @param i_procChipTarg - proc target * @param io_image - pointer to the SLW image * @param i_sizeImage - size of the SLW image * * @return errorlog if error, NULL otherwise. * */ -errlHndl_t applyPoreGenCpuRegs( TARGETING::Target *i_cpuTarget, +errlHndl_t applyPoreGenCpuRegs( TARGETING::Target *i_procChipTarg, void *io_image, uint32_t i_sizeImage ) { @@ -179,7 +179,7 @@ errlHndl_t applyPoreGenCpuRegs( TARGETING::Target *i_cpuTarget, TARGETING::TargetHandleList l_coreIds; getChildChiplets( l_coreIds, - i_cpuTarget, + i_procChipTarg, TYPE_CORE, false ); @@ -192,6 +192,8 @@ errlHndl_t applyPoreGenCpuRegs( TARGETING::Target *i_cpuTarget, TARGETING::ATTR_CHIP_UNIT_type l_coreId = 0; size_t l_threadId = 0; uint32_t l_rc = 0; + uint32_t l_failAddr = 0; + uint64_t l_msrVal = cpu_spr_value(CPU_SPR_MSR) ; uint64_t l_lpcrVal = cpu_spr_value( CPU_SPR_LPCR); @@ -202,6 +204,9 @@ errlHndl_t applyPoreGenCpuRegs( TARGETING::Target *i_cpuTarget, // and 23.7.3.5 - 6 in Murano Book 4 l_lpcrVal &= ~(0x0000000000002000) ; + // Core FIR Action1 Register value from Nick + const uint64_t action1_reg = 0xEA5C139705980000; + TARGETING::Target* sys = NULL; TARGETING::targetService().getTopLevelTarget(sys); assert( sys != NULL ); @@ -236,6 +241,7 @@ errlHndl_t applyPoreGenCpuRegs( TARGETING::Target *i_cpuTarget, TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "ERROR: MSR: core=0x%x,thread=0x%x,l_rc=0x%x", l_coreId, l_threadId, l_rc ); + l_failAddr = P8_MSR_MSR; break; } @@ -249,6 +255,7 @@ errlHndl_t applyPoreGenCpuRegs( TARGETING::Target *i_cpuTarget, TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "ERROR: HRMOR: core=0x%x,thread=0x%x,l_rc=0x%x", l_coreId, l_threadId, l_rc ); + l_failAddr = P8_SPR_HRMOR; break; } @@ -279,6 +286,7 @@ errlHndl_t applyPoreGenCpuRegs( TARGETING::Target *i_cpuTarget, TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "ERROR: LPCR: core=0x%x,thread=0x%x,l_rc=0x%x", l_coreId, l_threadId, l_rc ); + l_failAddr = P8_SPR_LPCR; break; } } // end for l_threadId @@ -288,26 +296,53 @@ errlHndl_t applyPoreGenCpuRegs( TARGETING::Target *i_cpuTarget, { break; } + + // Need to force core checkstops to escalate to a system checkstop + // by telling the SLW to update the ACTION1 register when it + // comes out of winkle (see HW286670) + l_rc = p8_pore_gen_scom_fixed( io_image, + P8_SLW_MODEBUILD_IPL, + EX_CORE_FIR_ACTION1_0x10013107, + l_coreId, + action1_reg, + P8_PORE_SCOM_REPLACE, + P8_SCOM_SECTION_NC ); + if( l_rc ) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR: ACTION1: core=0x%x,l_rc=0x%x", + l_coreId, l_rc ); + l_failAddr = EX_CORE_FIR_ACTION1_0x10013107; + break; + } + } // end for l_coreIds if ( l_rc ){ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR: core=0x%x, thread=0x%x, l_rc=0x%x", + "ERROR: p8_pore_gen api fail core=0x%x, thread=0x%x, l_rc=0x%x", l_coreId, l_threadId, l_rc ); /*@ * @errortype * @reasoncode ISTEP_BAD_RC * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE * @moduleid ISTEP_BUILD_WINKLE_IMAGES - * @userdata1 return code from p8_pore_gen_cpureg + * @userdata1[00:31] return code from p8_pore_gen_xxx function + * @userdata1[32:63] address being added to image + * @userdata2[00:31] Failing Core Id + * @userdata2[32:63] Failing Thread Id * - * @devdesc p8_pore_gen_cpureg returned an error when + * @devdesc p8_pore_gen_xxx returned an error when * attempting to change a reg value in the PORE image. */ l_errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, ISTEP::ISTEP_BUILD_WINKLE_IMAGES, ISTEP::ISTEP_BAD_RC, - l_rc ); + TWO_UINT32_TO_UINT64(l_rc,l_failAddr), + TWO_UINT32_TO_UINT64(l_coreId,l_threadId) ); + l_errl->collectTrace(FAPI_TRACE_NAME,256); + l_errl->collectTrace(FAPI_IMP_TRACE_NAME,256); + l_errl->collectTrace("ISTEPS_TRACE",256); } return l_errl; @@ -600,7 +635,7 @@ void* call_host_build_winkle( void *io_pArgs ) l_StepError.addErrorDetails( l_errl ); // Commit error - errlCommit( l_errl, HWPF_COMP_ID ); + errlCommit( l_errl, ISTEP_COMP_ID ); } } diff --git a/src/usr/hwpf/hwp/start_payload/makefile b/src/usr/hwpf/hwp/start_payload/makefile index 1d6ebc2fb..209fc281c 100644 --- a/src/usr/hwpf/hwp/start_payload/makefile +++ b/src/usr/hwpf/hwp/start_payload/makefile @@ -43,6 +43,7 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/start_payload ## EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/start_payload/<HWP_dir> EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp/utility_procedures +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build ## NOTE: add new object files when you add a new HWP OBJS = start_payload.o diff --git a/src/usr/hwpf/hwp/start_payload/start_payload.C b/src/usr/hwpf/hwp/start_payload/start_payload.C index 5bf0943a7..b77f839ab 100644 --- a/src/usr/hwpf/hwp/start_payload/start_payload.C +++ b/src/usr/hwpf/hwp/start_payload/start_payload.C @@ -53,6 +53,8 @@ #include <mbox/mboxif.H> #include <i2c/i2cif.H> #include <hwpf/hwp/occ/occ.H> +#include <sys/mm.h> +#include <devicefw/userif.H> #include <initservice/isteps_trace.H> #include <hwpisteperror.H> @@ -65,6 +67,8 @@ #include <fapiPlatHwpInvoker.H> #include "p8_set_pore_bar.H" #include "p8_cpu_special_wakeup.H" +#include "p8_pore_table_gen_api.H" +#include <p8_scom_addresses.H> #include "start_payload.H" #include <runtime/runtime.H> @@ -129,6 +133,13 @@ errlHndl_t notifyFsp ( bool i_istepModeFlag, */ errlHndl_t disableSpecialWakeup(); +/** + * @brief Re-enables the local core checkstop function + * + * @return errlHndl_t error handle + */ +errlHndl_t enableCoreCheckstops(); + /** * @brief This function will clear the PORE BARs. Needs to be done @@ -377,6 +388,14 @@ void* call_host_runtime_setup( void *io_pArgs ) } } + // Revert back to standard runtime mode where core checkstops + // do not escalate to system checkstops + // Workaround for HW286670 + l_err = enableCoreCheckstops(); + if ( l_err ) + { + break; + } // - Update HDAT/DEVTREE with tpmd logs @@ -825,4 +844,155 @@ errlHndl_t disableSpecialWakeup() return l_errl; } + +/** + * @brief Re-enables the local core checkstop function + */ +errlHndl_t enableCoreCheckstops() +{ + errlHndl_t l_errl = NULL; + void* l_slwPtr = NULL; + int mm_rc = 0; + + // loop thru all proc and find all functional ex units + TARGETING::TargetHandleList l_procTargetList; + getAllChips(l_procTargetList, TYPE_PROC); + for (TargetHandleList::const_iterator l_procIter = + l_procTargetList.begin(); + l_procIter != l_procTargetList.end(); + ++l_procIter) + { + const TARGETING::Target* l_pChipTarget = *l_procIter; + + // calculate location of the SLW output buffer + uint64_t l_physAddr = + l_pChipTarget->getAttr<TARGETING::ATTR_SLW_IMAGE_ADDR>(); + l_slwPtr = mm_block_map(reinterpret_cast<void*>(l_physAddr), + HOMER_MAX_SLW_IMG_SIZE_IN_MB*MEGABYTE); + if( l_slwPtr == NULL ) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "Error from mm_block_map : phys=%.16X", l_physAddr ); + /*@ + * @errortype + * @reasoncode ISTEP::ISTEP_MM_MAP_ERR + * @moduleid ISTEP::ISTEP_ENABLE_CORE_CHECKSTOPS + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @userdata1 <unused> + * @userdata2 Physical address + * @devdesc mm_block_map() returns error + */ + l_errl = + new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + ISTEP::ISTEP_ENABLE_CORE_CHECKSTOPS, + ISTEP::ISTEP_MM_MAP_ERR, + 0, + l_physAddr); + } + + // Get EX list under this proc + TARGETING::TargetHandleList l_exList; + getChildChiplets( l_exList, l_pChipTarget, TYPE_EX ); + + for (TargetHandleList::const_iterator + l_exIter = l_exList.begin(); + l_exIter != l_exList.end(); + ++l_exIter) + { + TARGETING::Target* l_exTarget = *l_exIter; + + // Write the runtime version of the Action1 reg + // Core FIR Action1 Register value from Nick + uint64_t action1_reg = 0xFEFC17F78F9C8A01; + size_t opsize = sizeof(uint64_t); + l_errl = deviceWrite( l_exTarget, + &action1_reg, + opsize, + DEVICE_SCOM_ADDRESS(EX_CORE_FIR_ACTION1_0x10013107) ); + if( l_errl ) + { + break; + } + + // Need to force core checkstops to escalate to a system checkstop + // by telling the SLW to update the ACTION1 register when it + // comes out of winkle (see HW286670) + TARGETING::ATTR_CHIP_UNIT_type l_coreId = + l_exTarget->getAttr<ATTR_CHIP_UNIT>(); + uint32_t l_rc = p8_pore_gen_scom_fixed( l_slwPtr, + P8_SLW_MODEBUILD_IPL, + EX_CORE_FIR_ACTION1_0x10013107, + l_coreId, + action1_reg,//ignored + P8_PORE_SCOM_NOOP, + P8_SCOM_SECTION_NC ); + if( l_rc ) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR: ACTION1: chip=%.8X, core=0x%x,l_rc=0x%x", + get_huid(l_pChipTarget), l_coreId, l_rc ); + /*@ + * @errortype + * @reasoncode ISTEP_BAD_RC + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid ISTEP_ENABLE_CORE_CHECKSTOPS + * @userdata1[00:31] rc from p8_pore_gen_scom_fixed function + * @userdata1[32:63] address being added to image + * @userdata2[00:31] Failing Proc HUID + * @userdata2[32:63] Failing Core Id + * + * @devdesc p8_pore_gen_scom_fixed returned an error when + * attempting to erase a reg value in the PORE image. + */ + l_errl = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + ISTEP::ISTEP_ENABLE_CORE_CHECKSTOPS, + ISTEP::ISTEP_BAD_RC, + TWO_UINT32_TO_UINT64(l_rc, + EX_CORE_FIR_ACTION1_0x10013107), + TWO_UINT32_TO_UINT64( + get_huid(l_pChipTarget), + l_coreId) ); + l_errl->collectTrace(FAPI_TRACE_NAME,256); + l_errl->collectTrace(FAPI_IMP_TRACE_NAME,256); + l_errl->collectTrace("ISTEPS_TRACE",256); + break; + } + } + + mm_rc = mm_block_unmap(l_slwPtr); + if( mm_rc ) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "Error from mm_block_unmap : rc=%d, ptr=%p", mm_rc, l_slwPtr ); + /*@ + * @errortype + * @reasoncode ISTEP::ISTEP_MM_UNMAP_ERR + * @moduleid ISTEP::ISTEP_ENABLE_CORE_CHECKSTOPS + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @userdata1 Return Code + * @userdata2 Unmap address + * @devdesc mm_block_unmap() returns error + */ + l_errl = + new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + ISTEP::ISTEP_ENABLE_CORE_CHECKSTOPS, + ISTEP::ISTEP_MM_UNMAP_ERR, + mm_rc, + reinterpret_cast<uint64_t> + (l_slwPtr)); + // Just commit error and keep going + errlCommit( l_errl, ISTEP_COMP_ID ); + } + l_slwPtr = NULL; + + if(l_errl) + { + break; + } + } + + return l_errl; +} + }; // end namespace |
