diff options
6 files changed, 129 insertions, 98 deletions
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api.C b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api.C index 470c76d07..b38c02ee0 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api.C +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_pore_table_gen_api.C,v 1.11 2012/10/04 02:39:07 cmolsen Exp $ +// $Id: p8_pore_table_gen_api.C,v 1.13 2013/05/08 20:16:58 cmolsen Exp $ // /*------------------------------------------------------------------------------*/ /* *! (C) Copyright International Business Machines Corp. 2012 */ @@ -61,8 +61,8 @@ */ uint32_t p8_pore_gen_cpureg( void *io_image, uint32_t i_sizeImage, - uint32_t i_regName, - uint64_t i_regData, + uint32_t i_regName, + uint64_t i_regData, uint32_t i_coreId, // [0:15] uint32_t i_threadId) { @@ -83,12 +83,12 @@ uint32_t p8_pore_gen_cpureg( void *io_image, uint32_t sprSwiz=0; #ifdef DYNAMIC_RAM_TABLE uint32_t iCore=0, sizeTableThis=0, sizeTableAll=0; - void *hostRamEntryFirstAll; // First entry of all Ram tables. - void *hostRamEntryLastAll; // Last entry of all Ram tables. + void *hostRamEntryFirstAll; // First entry of all Ram tables. + void *hostRamEntryLastAll; // Last entry of all Ram tables. uint64_t xipRamTableNext; void *hostRamTableNext; #endif - + // ------------------------------------------------------------------------- // Validate Ramming parameters. // @@ -121,7 +121,7 @@ uint32_t p8_pore_gen_cpureg( void *io_image, if (rcLoc) return IMGBUILD_ERR_RAM_INVALID_PARM; rcLoc = 0; - + // ------------------------------------------------------------------------- // Validate image and get pointer to SLW section. // @@ -146,7 +146,7 @@ uint32_t p8_pore_gen_cpureg( void *io_image, } hostSlwRamSection = (void*)((uint8_t*)io_image + xipSection.iv_offset); sbe_xip_host2pore( io_image, hostSlwRamSection, &xipSlwRamSection); - + // ------------------------------------------------------------------------- // Cross check SPR register and table defines // @@ -155,7 +155,7 @@ uint32_t p8_pore_gen_cpureg( void *io_image, return IMGBUILD_ERR_RAM_HDRS_NOT_SYNCED; } if (xipSection.iv_size!=SLW_RAM_TABLE_SIZE+SLW_SCOM_TABLE_SIZE_ALL) { - MY_ERR("SLW table size in *.H header file differs from SLW section size in image.\n"); + MY_ERR("SLW table size in *.H header file differs from SLW section size in image.\n"); MY_ERR("Check code or image version.\n"); return IMGBUILD_ERR_RAM_HDRS_NOT_SYNCED; } @@ -169,7 +169,7 @@ uint32_t p8_pore_gen_cpureg( void *io_image, MY_INF("Image validation and size checks - OK\n"); MY_INF("\tImage size = %i\n",i_sizeImage); MY_INF("\tSLW section size= %i\n",xipSection.iv_size); - + // ------------------------------------------------------------------------- // Locate RAM vector and locate RAM table associated with "This" core ID. // @@ -188,13 +188,13 @@ uint32_t p8_pore_gen_cpureg( void *io_image, hostRamTableThis = NULL; bNewTable = 1; } - + #ifdef DYNAMIC_RAM_TABLE hostRamEntryFirstAll = hostSlwRamSection; hostRamEntryLastAll = hostRamEntryFirstAll; // ------------------------------------------------------------------------- - // Walk the RAM vector and RAM tables to + // Walk the RAM vector and RAM tables to // - determine size of present tables, sizeTableAll - we'll need it when/if shifting entries forward // - check for RAM table overflow. // @@ -237,14 +237,14 @@ uint32_t p8_pore_gen_cpureg( void *io_image, } #else // ------------------------------------------------------------------------- - // We don't need to walk the "this" RAM table to check for RAM table + // We don't need to walk the "this" RAM table to check for RAM table // as this is done further down during insertion of the entry. // #endif - - + + // ------------------------------------------------------------------------- - // Walk the "This" core ID's RAM table to + // Walk the "This" core ID's RAM table to // - determine insertion point, hostRamEntryThis, of new RAM entry // if (bNewTable) { @@ -258,11 +258,11 @@ uint32_t p8_pore_gen_cpureg( void *io_image, bEntryEnd = 1; #else // Append to beginning of agreed upon static position for this coreId. - hostRamTableThis = (void*)((uint8_t*)hostSlwRamSection + + hostRamTableThis = (void*)((uint8_t*)hostSlwRamSection + (uint32_t)(SLW_RAM_TABLE_SIZE/SLW_MAX_CORES)*i_coreId ); hostRamEntryThis = hostRamTableThis; // ...update RAM vector (since it is currently NULL) - *((uint64_t*)hostRamVector + i_coreId) = myRev64( xipSlwRamSection + + *((uint64_t*)hostRamVector + i_coreId) = myRev64( xipSlwRamSection + (uint32_t)(SLW_RAM_TABLE_SIZE/SLW_MAX_CORES)*i_coreId ); bEntryEnd = 1; #endif @@ -308,8 +308,8 @@ uint32_t p8_pore_gen_cpureg( void *io_image, // (Need to do this before inserting new RAM entry at hostRamEntryThis.) // if (!bNewTable) - for ( ramEntryNext=(RamTableEntry*)hostRamEntryLastAll; - ramEntryNext>=(RamTableEntry*)hostRamEntryThis; + for ( ramEntryNext=(RamTableEntry*)hostRamEntryLastAll; + ramEntryNext>=(RamTableEntry*)hostRamEntryThis; ramEntryNext-- ) { *(ramEntryNext+1) = *ramEntryNext; if ((ramEntryNext+1)->instr!=ramEntryNext->instr) { @@ -326,7 +326,8 @@ uint32_t p8_pore_gen_cpureg( void *io_image, // ...do the MSR header headerType = 0x1; // MTMSRD header. ramEntryThis.header = ( ((uint32_t)bEntryEnd) << RAM_HEADER_END_START_C & RAM_HEADER_END_MASK_C ) | - ( ((uint32_t)headerType) << RAM_HEADER_TYPE_START_C & RAM_HEADER_TYPE_MASK_C ); + ( ((uint32_t)headerType) << RAM_HEADER_TYPE_START_C & RAM_HEADER_TYPE_MASK_C ) | + ( i_threadId << RAM_HEADER_THREAD_START_C & RAM_HEADER_THREAD_MASK_C ); // ...do the MSR instr ramEntryThis.instr = RAM_MTMSRD_INSTR_TEMPL_C; } @@ -337,7 +338,7 @@ uint32_t p8_pore_gen_cpureg( void *io_image, ( ((uint32_t)headerType) << RAM_HEADER_TYPE_START_C & RAM_HEADER_TYPE_MASK_C ) | ( i_regName << RAM_HEADER_SPRN_START_C & RAM_HEADER_SPRN_MASK_C ) | ( i_threadId << RAM_HEADER_THREAD_START_C & RAM_HEADER_THREAD_MASK_C ); - // ...do the SPR instr + // ...do the SPR instr sprSwiz = i_regName>>5 | (i_regName & 0x0000001f)<<5; if (sprSwiz!=SLW_SPR_REGS[iReg].swizzled) { MY_ERR("Inconsistent swizzle rules implemented. Check code. Dumping data.\n"); @@ -389,7 +390,7 @@ uint32_t p8_pore_gen_cpureg( void *io_image, uint32_t p8_pore_gen_scom( void *io_image, uint32_t i_sizeImage, uint32_t i_scomAddr, - uint32_t i_coreId, // [0:15] + uint32_t i_coreId, // [0:15] uint64_t i_scomData, uint32_t i_operation, // [0:5] uint32_t i_section) // [0,2,3] @@ -399,7 +400,6 @@ uint32_t p8_pore_gen_scom( void *io_image, uint32_t operation=0; uint32_t entriesCount=0, entriesMatch=0, entriesNOP=0; uint32_t sizeImageIn=0; - void __attribute__((unused)) *hostSlwSection; // HACK uint64_t xipScomTableThis; void *hostScomVector, *hostScomTableThis; void *hostScomEntryNext; // running entry pointer @@ -410,7 +410,7 @@ uint32_t p8_pore_gen_scom( void *io_image, SbeXipSection xipSection; SbeXipItem xipTocItem; PoreInlineContext ctx; - + // ------------------------------------------------------------------------- // Validate Scom parameters. // @@ -433,7 +433,7 @@ uint32_t p8_pore_gen_scom( void *io_image, if (rcLoc) return IMGBUILD_ERR_SCOM_INVALID_PARM; rcLoc = 0; - + // ------------------------------------------------------------------------- // Validate image and get pointer to SLW section. // @@ -456,10 +456,9 @@ uint32_t p8_pore_gen_scom( void *io_image, MY_ERR("Probably invalid section name for SBE_XIP_SECTION_SLW.\n"); return IMGBUILD_ERR_GET_SECTION; } - hostSlwSection = (void*)((uint8_t*)io_image + xipSection.iv_offset); // ...check .slw section size if (xipSection.iv_size!=SLW_RAM_TABLE_SIZE+SLW_SCOM_TABLE_SIZE_ALL) { - MY_ERR("SLW table size in *.H header file differs from SLW section size in image.\n"); + MY_ERR("SLW table size in *.H header file differs from SLW section size in image.\n"); MY_ERR("Check code or image version.\n"); return IMGBUILD_ERR_SCOM_HDRS_NOT_SYNCD; } @@ -475,9 +474,9 @@ uint32_t p8_pore_gen_scom( void *io_image, MY_INF("Image validation and size checks - OK\n"); MY_INF("\tImage size = %i\n",i_sizeImage); MY_INF("\tSLW section size= %i\n",xipSection.iv_size); - + // ------------------------------------------------------------------------- - // Locate Scom vector according to i_section and then locate Scom table + // Locate Scom vector according to i_section and then locate Scom table // associated with "This" core ID. // switch (i_section) { @@ -528,7 +527,7 @@ uint32_t p8_pore_gen_scom( void *io_image, // doesn't include NOP entries.) // - If no NOP found, insert at first RET. // - + // First, create search strings for addr, nop and ret. // Note, the following IIS will also be used in case of // - i_operation==append @@ -552,7 +551,7 @@ uint32_t p8_pore_gen_scom( void *io_image, MY_ERR("pore_NOP generated rc = %d", ctx.error); return IMGBUILD_ERR_PORE_INLINE_ASM; } - + // Second, search for addr and nop in relevant coreId table until first RET. // Note: // - We go through ALL entries until first RET instr. We MUST find a RET instr, @@ -560,7 +559,7 @@ uint32_t p8_pore_gen_scom( void *io_image, // - Count number of entries and check for overrun, though we'll continue // searching until we find an RET. (Should be improved.) // - The STI(+SCOM_addr) opcode is in the 2nd word of the Scom entry. - // - For an append operation, if a NOP is found (before a RET obviously), the + // - For an append operation, if a NOP is found (before a RET obviously), the // SCOM is replacing that NNNN sequence. hostScomEntryNext = hostScomTableThis; while (memcmp(hostScomEntryNext, bufRET, sizeof(uint32_t))) { @@ -576,7 +575,7 @@ uint32_t p8_pore_gen_scom( void *io_image, hostScomEntryNext = (void*)((uintptr_t)hostScomEntryNext + XIPSIZE_SCOM_ENTRY); } hostScomEntryRET = hostScomEntryNext; // The last EntryNext will always be the first RET. - + switch (i_section) { case 0: if (entriesCount>=SLW_MAX_SCOMS_NC) { @@ -651,7 +650,7 @@ uint32_t p8_pore_gen_scom( void *io_image, i_operation, P8_PORE_SCOM_FIRST_OP, P8_PORE_SCOM_LAST_OP); return IMGBUILD_ERR_SCOM_INVALID_PARM; } - + // ------------------------------------------------------------------------- // Assuming pre-allocated Scom table (after pre-allocated Ram table): // - Table is pre-filled with RNNN ISS. @@ -660,7 +659,7 @@ uint32_t p8_pore_gen_scom( void *io_image, // - Remember to check for more than SLW_MAX_SCOMS_NC entries! switch (operation) { - case P8_PORE_SCOM_APPEND: // Append a Scom at first occurring NNNN or RNNN, + case P8_PORE_SCOM_APPEND: // Append a Scom at first occurring NNNN or RNNN, if (hostScomEntryNOP) { // ... replace the NNNN MY_INF("Append at NOP\n"); @@ -695,7 +694,7 @@ uint32_t p8_pore_gen_scom( void *io_image, MY_INF("Replace existing Scom w/NOPs\n"); memcpy(hostScomEntryMatch,(void*)bufIIS,XIPSIZE_SCOM_ENTRY); } - else { + else { // do nothing, and assume everything is fine, since we did no damage. } break; @@ -703,10 +702,10 @@ uint32_t p8_pore_gen_scom( void *io_image, if (hostScomEntryMatch) { // ... do an OR on the data (which is the 2nd DWord in the entry) MY_INF("Overlay existing Scom - OR case\n"); - *((uint64_t*)hostScomEntryMatch+1) = + *((uint64_t*)hostScomEntryMatch+1) = *((uint64_t*)hostScomEntryMatch+1) | myRev64(i_scomData); } - else { + else { MY_ERR("No Scom entry found to do OR operation with.\n"); return IMGBUILD_ERR_SCOM_ENTRY_NOT_FOUND; } @@ -715,10 +714,10 @@ uint32_t p8_pore_gen_scom( void *io_image, if (hostScomEntryMatch) { // ... do an AND on the data (which is the 2nd DWord in the entry) MY_INF("Overlay existing Scom - AND case\n"); - *((uint64_t*)hostScomEntryMatch+1) = + *((uint64_t*)hostScomEntryMatch+1) = *((uint64_t*)hostScomEntryMatch+1) & myRev64(i_scomData); } - else { + else { MY_ERR("No Scom entry found to do AND operation with.\n"); return IMGBUILD_ERR_SCOM_ENTRY_NOT_FOUND; } @@ -734,7 +733,7 @@ uint32_t p8_pore_gen_scom( void *io_image, default: MY_ERR("Impossible value of operation (=%i). Check code.\n",operation); return IMGBUILD_ERR_CHECK_CODE; - + } // End of switch(operation) return rc; diff --git a/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.C b/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.C index da63f3081..b55d6cdc0 100644 --- a/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.C +++ b/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_dmi_scominit.C,v 1.5 2013/02/11 03:58:59 jmcgill Exp $ +// $Id: proc_dmi_scominit.C,v 1.7 2013/05/14 15:45:32 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_dmi_scominit.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -39,6 +39,8 @@ //------------------------------------------------------------------------------ // Version Date Owner Description //------------------------------------------------------------------------------ +// 1.7 05/14/13 jmcgill Address review comments +// 1.6 05/01/13 jgrell Added proc chip target // 1.5 02/06/13 jmcgill Change passed targets in order to match scominit file updates. // 1.4 02/04/13 thomsen Fixed informational print to not say Error // 1.3 01/23/13 thomsen Added separate calls to base & customized scominit files. Removed separate calls to SIM vs. HW scominit files @@ -64,6 +66,7 @@ extern "C" { // HWP entry point, comments in header fapi::ReturnCode proc_dmi_scominit(const fapi::Target & i_target) { + fapi::ReturnCode rc; fapi::Target i_this_pu_target; std::vector<fapi::Target> targets; @@ -73,18 +76,23 @@ fapi::ReturnCode proc_dmi_scominit(const fapi::Target & i_target) do { + // Get parent chip target + rc = fapiGetParentChip(i_target, i_this_pu_target); + if (!rc.ok()) + { + FAPI_ERR("proc_dmi_scominit: Error from fapiGetParentChip"); + break; + } - // Get parent chip target - rc = fapiGetParentChip(i_target, i_this_pu_target); if(rc) return rc; - - // populate targets vector (i_target=chiplet target) + // populate targets vector (i_target=chiplet target) targets.push_back(i_target); + targets.push_back(i_this_pu_target); // processor MCS chiplet target // test target type to confirm correct before calling initfile(s) to execute if (i_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET) { - // Call BASE DMI SCOMINIT + // Call BASE DMI SCOMINIT FAPI_INF("proc_dmi_scominit: fapiHwpExecInitfile executing %s on %s", MCS_DMI_BASE_IF, i_target.toEcmdString()); FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, targets, MCS_DMI_BASE_IF); @@ -94,7 +102,7 @@ fapi::ReturnCode proc_dmi_scominit(const fapi::Target & i_target) MCS_DMI_BASE_IF, i_target.toEcmdString()); break; } - // Call CUSTOMIZED DMI SCOMINIT (system specific) + // Call CUSTOMIZED DMI SCOMINIT (system specific) FAPI_INF("proc_dmi_scominit: fapiHwpExecInitfile executing %s on %s", MCS_DMI_CUSTOM_IF, i_target.toEcmdString()); FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, targets, MCS_DMI_CUSTOM_IF); @@ -104,7 +112,7 @@ fapi::ReturnCode proc_dmi_scominit(const fapi::Target & i_target) MCS_DMI_CUSTOM_IF, i_target.toEcmdString()); break; } - } + } // unsupported target type else { @@ -116,7 +124,7 @@ fapi::ReturnCode proc_dmi_scominit(const fapi::Target & i_target) // mark HWP exit FAPI_INF("proc_dmi_scominit: End"); - return rc; + return rc; } diff --git a/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile index 4a4932786..183ed1a35 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile @@ -1,8 +1,10 @@ -#-- $Id: p8.dmi.custom.scom.initfile,v 1.7 2013/03/15 21:19:29 thomsen Exp $ +#-- $Id: p8.dmi.custom.scom.initfile,v 1.9 2013/05/01 20:31:29 jgrell Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.9 |thomsen |04/30/13|Added TGT1. to ATTR_CHIP_EC* attribute instances to reference a chip target rather than a chiplet target +#-- 1.8 |jgrell |04/18/13|Added EC level control of the Recal DFE, DDC, and CTLE enable bits. ('0' when EC < 20) #-- 1.7 |jgrell |03/14/13|Added temporary masking of the GCR Buffer Parity Checkers in the GCR Master until the source of the error can be found. This ungates the lab. #-- 1.6 |thomsen |03/07/13|Temporarily mask the GCR Buffer Parity Checker until the source of the error can be found. This ungates the lab. #-- 1.5 |thomsen |02/12/13|Added Lane Power Ups and Clock Invert @@ -17,8 +19,6 @@ #-- TARGETS: #-- SYS. Chiplet target #-- TGT1. Proc target -#-- TGT2. Connected Chiplet target -#-- TGT3. Connected Proc target #-- ATTR_CHIP_UNIT_POS is the MCS unit number (0-7 on Venice, 4-7 on Murano) and corresponds to the scom address translation done in #-- the p8.chipunit.scominfo file. It is used to be able to select a specific clock group number. @@ -288,6 +288,21 @@ scom_data; 0xC000000000000000; } + +#--************************************************************************************************************** +#---------------------------------------------------------------------------------------------------------------- +# Recal +#---------------------------------------------------------------------------------------------------------------- +#--************************************************************************************************************** +# HW235842 + +scom 0x800.0b(rx_rc_step_cntl_pg)(rx_grp3)(lane_na).0x(dmi0_gcr_addr) { +bits, scom_data, expr; +rx_rc_enable_dfe_h1_cal, 0b0, TGT1.ATTR_CHIP_EC_FEATURE_RECAL_DFE_ENABLE==0; +rx_rc_enable_ddc, 0b0, TGT1.ATTR_CHIP_EC_FEATURE_RECAL_DDC_ENABLE==0; +rx_rc_enable_ctle_cal, 0b0, TGT1.ATTR_CHIP_EC_FEATURE_RECAL_CTLE_ENABLE==0; +} + ############################################################################################ # END OF FILE ############################################################################################ diff --git a/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile index 551bd91d1..30eaeb1fe 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile @@ -1,8 +1,10 @@ -#-- $Id: p8.mcs.scom.initfile,v 1.8 2013/05/02 16:32:15 jmcgill Exp $ +#-- $Id: p8.mcs.scom.initfile,v 1.9 2013/05/06 00:52:59 baysah Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.90|baysah |05/05/13|- Disabled MCMODE1Q_DISABLE_FASTPATH_CRC_ECC_BYPASS and MCMODE0Q_CL_CHANNEL_TIMEOUT_FORCES_CHANNEL_FAIL. +#-- | | | #-- 1.70|baysah |04/26/13|- Disabled MCMODE0Q_ENABLE_FAULT_LINE_FOR_GLOBAL_CHECKSTOP per firmware request for MPIPL. #-- | | | #-- 1.60|baysah |04/25/13|- Fix problem with incorrectly setting mcmode0 bit 1 which is marked as reserved, but its actually used to @@ -30,34 +32,36 @@ SyntaxVersion = 1 #-- MCS Mode0 Register #--****************************************************************************** scom 0x0000000002011807 { - bits , scom_data ; - 0 , 0b1 ; # MCMODE0Q_ENABLE_CMD_BYP_STUTTER - 1 , 0b0 ; # MCMODE0Q_RESERVED Reserved - 2 , 0b1 ; # MCMODE0Q_ENABLE_NS_RD_AO_SFU_FOR_DCBZ - 3 , 0b1 ; # MCMODE0Q_ENABLE_CENTAUR_LOCAL_CHECKSTOP_COMMAND - 4:7 , 0xF ; # MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD - 8:11 , 0x0 ; # MCMODE0Q_Number_of_CL_Entries_Reserved_for_Read - 12:15, 0x1 ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_MIRRORED_OPS - 16:19, 0x0 ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_WRITES - 20:23, 0x1 ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_CP_WRITES - 24:27, 0x1 ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_CP_IG - 28:31, 0x0 ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_HTM_OPS - 32:35, 0x0 ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_HA_ASSIST - 36 , 0b1 ; # MCMODE0Q_MCFGRP_19_IS_HO_BIT - 37 , 0b1 ; # MCMODE0Q_CL_CHANNEL_TIMEOUT_FORCES_CHANNEL_FAIL - 38 , 0b0 ; # MCMODE0Q_ENABLE_FAULT_LINE_FOR_GLOBAL_CHECKSTOP - 39:43, 0b00000 ; # MCMODE0Q_RESERVED_39_43 Reserved - 44:52, 0b001100010 ; # MCMODE0Q_ADDRESS_COLLISION_MODES - 53 , 0b0 ; # MCMODE0Q_INCLUDE_CP_IG_IN_CP_WRITE_FULLNESS_GROUP - 54 , 0b1 ; # MCMODE0Q_ENABLE_DMAWR_CMD_BIT - 55 , 0b0 ; # MCMODE0Q_ENABLE_READ_LFSR_DATA - 56 , 0b0 ; # MCMODE0Q_FORCE_CHANNEL_FAIL - 57 , 0b0 ; # MCMODE0Q_DISABLE_READ_CRC_ECC_BYPASS_TAKEN - 58 , 0b0 ; # MCMODE0Q_DISABLE_CL_AO_QUEUES - 59:60, 0b00 ; # MCMODE0Q_ADDRESS_SELECT_LFSR_VALUE (4k) - 61 , 0b0 ; # MCMODE0Q_ENABLE_CENTAUR_SYNC - 62 , 0b0 ; # MCMODE0Q_WRITE_DATA_BUFFER_ECC_CHECK_DISABLE - 63 , 0b0 ; # MCMODE0Q_WRITE_DATA_BUFFER_ECC_CORRECT_DISABLE + bits , scom_data , expr ; + 0 , 0b1 , any ; # MCMODE0Q_ENABLE_CMD_BYP_STUTTER + 1 , 0b0 , any ; # MCMODE0Q_RESERVED Reserved + 2 , 0b1 , any ; # MCMODE0Q_ENABLE_NS_RD_AO_SFU_FOR_DCBZ + 3 , 0b1 , any ; # MCMODE0Q_ENABLE_CENTAUR_LOCAL_CHECKSTOP_COMMAND + 4:7 , 0xF , any ; # MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD + 8:11 , 0x0 , any ; # MCMODE0Q_Number_of_CL_Entries_Reserved_for_Read + 12:15, 0x1 , any ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_MIRRORED_OPS + 16:19, 0x0 , any ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_WRITES + 20:23, 0x1 , any ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_CP_WRITES + 24:27, 0x1 , any ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_CP_IG + 28:31, 0x0 , any ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_HTM_OPS + 32:35, 0x0 , any ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_HA_ASSIST + 36 , 0b1 , any ; # MCMODE0Q_MCFGRP_19_IS_HO_BIT + 37 , 0b0 , any ; # MCMODE0Q_CL_CHANNEL_TIMEOUT_FORCES_CHANNEL_FAIL + # 37 , 0b1 , (TGT1.ATTR_CHIP_EC_FEATURE_MCS_ECC_BYPASS_DISABLE == 0x0) ; # MCMODE0Q_CL_CHANNEL_TIMEOUT_FORCES_CHANNEL_FAIL + # 37 , 0b0 , (TGT1.ATTR_CHIP_EC_FEATURE_MCS_ECC_BYPASS_DISABLE != 0x0) ; # MCMODE0Q_CL_CHANNEL_TIMEOUT_FORCES_CHANNEL_FAIL + 38 , 0b0 , any ; # MCMODE0Q_ENABLE_FAULT_LINE_FOR_GLOBAL_CHECKSTOP + 39:43, 0b00000 , any ; # MCMODE0Q_RESERVED_39_43 Reserved + 44:52, 0b001100010 , any ; # MCMODE0Q_ADDRESS_COLLISION_MODES + 53 , 0b0 , any ; # MCMODE0Q_INCLUDE_CP_IG_IN_CP_WRITE_FULLNESS_GROUP + 54 , 0b1 , any ; # MCMODE0Q_ENABLE_DMAWR_CMD_BIT + 55 , 0b0 , any ; # MCMODE0Q_ENABLE_READ_LFSR_DATA + 56 , 0b0 , any ; # MCMODE0Q_FORCE_CHANNEL_FAIL + 57 , 0b0 , any ; # MCMODE0Q_DISABLE_READ_CRC_ECC_BYPASS_TAKEN + 58 , 0b0 , any ; # MCMODE0Q_DISABLE_CL_AO_QUEUES + 59:60, 0b00 , any ; # MCMODE0Q_ADDRESS_SELECT_LFSR_VALUE (4k) + 61 , 0b0 , any ; # MCMODE0Q_ENABLE_CENTAUR_SYNC + 62 , 0b0 , any ; # MCMODE0Q_WRITE_DATA_BUFFER_ECC_CHECK_DISABLE + 63 , 0b0 , any ; # MCMODE0Q_WRITE_DATA_BUFFER_ECC_CORRECT_DISABLE } @@ -86,7 +90,8 @@ SyntaxVersion = 1 60 , 0b0 , any ; # MCMODE1Q_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_GROUP_PUMP_LOCAL_READ 61 , 0b0 , any ; # MCMODE1Q_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_SYSTEM_PUMP_LOCAL_READ 62 , 0b0 , any ; # MCMODE1Q_DISABLE_FASTPATH_MCS_COMMAND_BYPASS - 63 , 0b0 , any ; # MCMODE1Q_DISABLE_FASTPATH_CRC_ECC_BYPASS + 63 , 0b0 , (TGT1.ATTR_CHIP_EC_FEATURE_MCS_ECC_BYPASS_DISABLE == 0x0) ; # MCMODE1Q_DISABLE_FASTPATH_CRC_ECC_BYPASS + 63 , 0b1 , (TGT1.ATTR_CHIP_EC_FEATURE_MCS_ECC_BYPASS_DISABLE != 0x0) ; # MCMODE1Q_DISABLE_FASTPATH_CRC_ECC_BYPASS } diff --git a/src/usr/hwpf/hwp/initfiles/p8.psi.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.psi.scom.initfile index 8f788af29..3c30405b8 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.psi.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.psi.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: p8.psi.scom.initfile,v 1.3 2013/03/29 15:39:19 jmcgill Exp $ +#-- $Id: p8.psi.scom.initfile,v 1.4 2013/05/03 20:28:05 jmcgill Exp $ #------------------------------------------------------------------------------- #-- #-- (C) Copyright International Business Machines Corp. 2011 @@ -23,8 +23,21 @@ SyntaxVersion = 1 #-- SCOM initializations #-------------------------------------------------------------------------------- + +# PSI Host Bridge FIR Action0 Register +scom 0x02010906 { + bits, scom_data; + 0:63, 0x0000000000000000; +} + +# PSI Host Bridge FIR Action1 Register +scom 0x02010907 { + bits, scom_data; + 0:63, 0xC62B000000000000; +} + # PSI Host Bridge FIR Mask Register scom 0x02010903 { bits, scom_data; - 0:63, 0x9D03FDF800000000; + 0:63, 0x3900FFF800000000; } diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.C index a524b71a4..e187704e7 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_oha_init.C,v 1.8 2013/03/26 12:13:04 pchatnah Exp $ +// $Id: p8_oha_init.C,v 1.9 2013/04/30 18:17:25 mjjones Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_oha_init.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -45,6 +45,8 @@ /// /// \version /// \version -------------------------------------------------------------------------- +/// \version 1.9 mjjones 04/30/13 Removed unused variable +/// \version -------------------------------------------------------------------------- /// \version 1.3 rmaier 10/04/12 Replacing genHex*Str function /// \version -------------------------------------------------------------------------- /// \version 1.1 rmaier 08/23/12 Renaming proc_ to p8_ @@ -218,17 +220,6 @@ p8_oha_init(const fapi::Target &i_target, uint32_t i_mode) FAPI_INF("<p8_oha_init> : MODE: RESET Calling p8_oha_init_reset"); - //Declare parms struct - //TODO RTC: 71328 - hack to indicate unused - struct_i_oha_val_init_type __attribute__((unused)) i_oha_val_init; - - //Assign values to parms in struct - // should come from MRWB - i_oha_val_init.AISS_HANG_DETECT_TIMER_SEL = 9; // oha_mode_reg (11:14) - 0=1ms, 1=2ms, 3=4ms, ...9=512ms. others illegal - i_oha_val_init.PPT_TIMER_SELECT = 3; // activity_sample_mode_reg (36:37) 0=0.25us, 1=0.5us, 2=1us, and 3=2us - i_oha_val_init.LAD_ENTRY = 16; - i_oha_val_init.LAD_EXIT = 17; - // ****************************************************************** /// \todo should this values be attributes?? The get those attributes here // FAPI_ATTR_GET("IVRMS_ENABLED", i_target,(unit8_t) ivrms_enabled); |
