diff options
7 files changed, 99 insertions, 29 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C index f5c078782..d8eca636d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C @@ -413,7 +413,6 @@ fapi2::ReturnCode eff_config::refresh_interval_time(const fapi2::Target<TARGET_T "%s Incorrect Fine Refresh Mode received: %d ", mss::c_str(i_target), l_refresh_mode); - break; } @@ -557,7 +556,7 @@ fapi_try_exit: } /// -/// @brief Determines & sets effective config for refresh cycle time (logical ranks) (tRFC_DLR) +/// @brief Determines & sets effective config for refresh cycle time (different logical ranks - tRFC_DLR) /// @param[in] i_target FAPI2 target /// @return fapi2::FAPI2_RC_SUCCESS if okay /// @@ -566,22 +565,43 @@ fapi2::ReturnCode eff_config::refresh_cycle_time_dlr(const fapi2::Target<TARGET_ const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) ); + uint8_t l_refresh_mode = 0; + uint8_t l_density = 0; + uint64_t l_tCK_in_ps = 0; + uint64_t l_trfc_dlr_in_ps = 0; + uint8_t l_trfc_dlr_in_nck = 0; std::vector<uint8_t> l_mcs_attrs_trfc_dlr(PORTS_PER_MCS, 0); - // Retrieve MCS attribute data - FAPI_TRY( eff_dram_trfc_dlr(l_mcs, l_mcs_attrs_trfc_dlr.data()), - "Failed to retrieve tRFC_DLR attribute" ); + // Retrieve map params + FAPI_TRY( iv_pDecoder->sdram_density(i_target, l_density), "Failed to get sdram density"); + FAPI_TRY ( mss::mrw_fine_refresh_mode(l_refresh_mode), "Failed to get MRW attribute for fine refresh mode" ); + + FAPI_INF("Retrieved SDRAM density: %d, fine refresh mode: %d", + l_density, l_refresh_mode); - // TK - RIT skeleton. Need to finish - BRS - l_mcs_attrs_trfc_dlr[l_port_num] = 0x90; - FAPI_INF("Hardwired tRFC_DLR: %d", l_mcs_attrs_trfc_dlr[l_port_num]); + // Calculate refresh cycle time in ps + FAPI_TRY( calc_trfc_dlr(l_refresh_mode, l_density, l_trfc_dlr_in_ps), "Failed calc_trfc_dlr()" ); + + // Calculate clock period (tCK) from selected freq from mss_freq + FAPI_TRY( clock_period(i_target, l_tCK_in_ps), "Failed to calculate clock period (tCK)"); + + // Calculate refresh cycle time in nck + l_trfc_dlr_in_nck = calc_nck(l_trfc_dlr_in_ps, l_tCK_in_ps, uint64_t(INVERSE_DDR4_CORRECTION_FACTOR)); + + FAPI_INF("Calculated clock period (tCK): %d, tRFC_DLR (ps): %d, tRFC_DLR (nck): %d", + l_tCK_in_ps, l_trfc_dlr_in_ps, l_trfc_dlr_in_nck); + + // Retrieve MCS attribute data + FAPI_TRY( eff_dram_trfc_dlr(l_mcs, l_mcs_attrs_trfc_dlr.data()), "Failed to retrieve tRFC_DLR attribute" ); // Update MCS attribute - // casts vector into the type FAPI_ATTR_SET is expecting by deduction + l_mcs_attrs_trfc_dlr[l_port_num] = l_trfc_dlr_in_nck; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TRFC_DLR, l_mcs, UINT8_VECTOR_TO_1D_ARRAY(l_mcs_attrs_trfc_dlr, PORTS_PER_MCS) ), "Failed to set tRFC_DLR attribute" ); + fapi_try_exit: return fapi2::current_err; @@ -594,9 +614,6 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::rcd_mirror_mode(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM - uint8_t l_attrs_mirror_mode[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; - // Targets const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); const auto l_mca = find_target<TARGET_TYPE_MCA>(i_target); @@ -605,13 +622,19 @@ fapi2::ReturnCode eff_config::rcd_mirror_mode(const fapi2::Target<TARGET_TYPE_DI const auto l_port_num = index(l_mca); const auto l_dimm_num = index(i_target); + // Retrieve MCS attribute data + uint8_t l_mirror_mode = 0; + uint8_t l_attrs_mirror_mode[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; + FAPI_TRY( eff_dimm_rcd_mirror_mode(l_mcs, &l_attrs_mirror_mode[0][0]) ); - l_attrs_mirror_mode[l_port_num][l_dimm_num] = 0x01; + FAPI_TRY( iv_pDecoder->iv_module_decoder->register_to_dram_addr_mapping(l_mirror_mode) ); + + // Update MCS attribute + l_attrs_mirror_mode[l_port_num][l_dimm_num] = l_mirror_mode; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_RCD_MIRROR_MODE, l_mcs, l_attrs_mirror_mode) ); fapi_try_exit: return fapi2::current_err; - } /// @@ -636,8 +659,6 @@ fapi2::ReturnCode eff_config::dram_bank_bits(const fapi2::Target<TARGET_TYPE_DIM fapi_try_exit: return fapi2::current_err; - - } /// @@ -662,8 +683,6 @@ fapi2::ReturnCode eff_config::dram_row_bits(const fapi2::Target<TARGET_TYPE_DIMM fapi_try_exit: return fapi2::current_err; - - } /// diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.C index db75d5b14..b755dfbd8 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.C @@ -72,7 +72,6 @@ static const std::vector<std::pair<uint8_t, uint64_t> > TRFC_DLR4 = // 16Gb - TBD }; - /// @brief Calculates refresh interval time /// @param[in] i_mode fine refresh rate mode /// @param[in] i_temp_refresh_range temperature refresh range @@ -114,4 +113,51 @@ fapi2::ReturnCode calc_trefi( const refresh_rate i_mode, return fapi2::FAPI2_RC_SUCCESS; } +/// @brief Calculates Minimum Refresh Recovery Delay Time (different logical rank) +/// @param[in] i_mode fine refresh rate mode +/// @param[in] i_density SDRAM density +/// @param[out] o_trfc_in_ps timing val in ps +/// @return fapi2::FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode calc_trfc_dlr(const uint8_t i_refresh_mode, + const uint8_t i_density, + uint64_t& o_trfc_in_ps) +{ + bool l_is_val_found = 0; + + // Selects appropriate tRFC based on fine refresh mode + switch(i_refresh_mode) + { + case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_NORMAL: + l_is_val_found = find_value_from_key(TRFC_DLR1, i_density, o_trfc_in_ps); + break; + + case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FIXED_2X: + case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FLY_2X: + l_is_val_found = find_value_from_key(TRFC_DLR2, i_density, o_trfc_in_ps); + break; + + case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FIXED_4X: + case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FLY_4X: + l_is_val_found = find_value_from_key(TRFC_DLR4, i_density, o_trfc_in_ps); + break; + + default: + // Fine Refresh Mode will be a platform attribute set by the MRW, + // which they "shouldn't" mess up as long as use "attribute" enums. + // if openpower messes this up we can at least catch it + FAPI_ERR( "Incorrect Fine Refresh Mode received: %d ", i_refresh_mode); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + break; + }// switch + + if(l_is_val_found) + { + return fapi2::FAPI2_RC_SUCCESS; + } + + FAPI_ERR("Unable to find tRFC (ps) from map with SDRAM density key %d", i_density); + return fapi2::FAPI2_RC_FALSE; +} + }// mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H index 87fd0a02e..9a207865b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H @@ -139,6 +139,17 @@ fapi_try_exit: fapi2::ReturnCode calc_trefi( const refresh_rate i_mode, const uint8_t i_temp_refresh_range, uint64_t& o_timing ); + +/// @brief Calculates Minimum Refresh Recovery Delay Time (different logical rank) +/// @param[in] i_mode fine refresh rate mode +/// @param[in] i_density SDRAM density +/// @param[out] o_trfc_in_ps timing val in ps +/// @return fapi2::FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode calc_trfc_dlr( const uint8_t i_refresh_mode, + const uint8_t i_density, + uint64_t& o_trfc_in_ps ); + } // mss #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.H b/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.H index 0a8bfbd19..0e7980781 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.H @@ -380,9 +380,7 @@ class decoder std::shared_ptr<dimm_module_decoder> iv_module_decoder; std::vector<uint8_t> iv_spd_data; - /// - /// @brief Default constructor - /// + // Default constructor deleted decoder() = delete; /// diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C index 9c054b63b..751b05b4b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C @@ -477,14 +477,10 @@ fapi2::ReturnCode populate_decoder_caches( const fapi2::Target<TARGET_TYPE_DIMM> return fapi2::FAPI2_RC_INVALID_PARAMETER; } - // This shouldn't be null so there is a specific decoder we are wanting to populate - std::shared_ptr<decoder> l_pDecoder(i_pDecoder); - // Custom decoder provided (usually done for testing) // Populate custom spd caches maps one dimm at a time - o_factory_caches.emplace( std::make_pair( pos(i_target), l_pDecoder ) ); + o_factory_caches.emplace( std::make_pair( pos(i_target), i_pDecoder ) ); - // TK - else what do we want here return fapi2::FAPI2_RC_SUCCESS; } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.C b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.C index 36846e54e..97159c5cd 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_spd.C @@ -95,7 +95,7 @@ static constexpr uint8_t vbu_spd[] = //112 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9C, 0xB5, 0x00, 0xC9, 0xC9, 0xC9, 0xE7, 0xD6, 0xCA, 0x91, //128 - 0x11, 0x11, 0x23, 0x05, 0x00, 0x80, 0xB3, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x11, 0x23, 0x05, 0x00, 0x80, 0xB3, 0x30, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, diff --git a/src/import/chips/p9/procedures/hwp/memory/tests/mss_rdimm_decoder_ut.C b/src/import/chips/p9/procedures/hwp/memory/tests/mss_rdimm_decoder_ut.C index 8643a2c6c..21a201c22 100644 --- a/src/import/chips/p9/procedures/hwp/memory/tests/mss_rdimm_decoder_ut.C +++ b/src/import/chips/p9/procedures/hwp/memory/tests/mss_rdimm_decoder_ut.C @@ -300,7 +300,7 @@ SCENARIO_METHOD(mcbist_target_test_fixture, "Verify RDIMM SPD Decoding", "[rdimm /// SPD Byte 136 (Bit 0) ///////////////////////////// uint8_t l_decoder_output = 0; - uint8_t l_expected = 0x0; // from VBU fake SPD + uint8_t l_expected = 0x1; // from VBU fake SPD REQUIRE_FALSE( l_decoder.register_to_dram_addr_mapping( l_decoder_output) ); REQUIRE( l_expected == l_decoder_output); } |