diff options
| -rw-r--r-- | src/include/usr/i2c/i2cif.H | 3 | ||||
| -rw-r--r-- | src/include/usr/vpd/vpdreasoncodes.H | 4 | ||||
| -rw-r--r-- | src/usr/targeting/common/xmltohb/simics_AXONE.system.xml | 370 | ||||
| -rw-r--r-- | src/usr/targeting/common/xmltohb/target_types_hb.xml | 5 | ||||
| -rw-r--r-- | src/usr/vpd/ddimm.C | 264 |
5 files changed, 546 insertions, 100 deletions
diff --git a/src/include/usr/i2c/i2cif.H b/src/include/usr/i2c/i2cif.H index a902fbcbf..c33c83e32 100644 --- a/src/include/usr/i2c/i2cif.H +++ b/src/include/usr/i2c/i2cif.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -24,6 +24,7 @@ /* IBM_PROLOG_END_TAG */ #ifndef __I2CIF_H #define __I2CIF_H +#include <list> namespace I2C { diff --git a/src/include/usr/vpd/vpdreasoncodes.H b/src/include/usr/vpd/vpdreasoncodes.H index 92aea3196..f0897e708 100644 --- a/src/include/usr/vpd/vpdreasoncodes.H +++ b/src/include/usr/vpd/vpdreasoncodes.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -155,6 +155,8 @@ enum vpdReasonCode VPD_CANNOT_WRITE_OVERRIDDEN_VPD = VPD_COMP_ID | 0x3c, VPD_FAILED_TO_RESOLVE_NODE_TARGET = VPD_COMP_ID | 0x3d, VPD_BAD_REC_NUM = VPD_COMP_ID | 0x3e, + VPD_INVALID_MASTER_I2C_PATH = VPD_COMP_ID | 0x3f, + VPD_NULL_I2C_MASTER = VPD_COMP_ID | 0x40, }; diff --git a/src/usr/targeting/common/xmltohb/simics_AXONE.system.xml b/src/usr/targeting/common/xmltohb/simics_AXONE.system.xml index d95b5b680..d6920ad53 100644 --- a/src/usr/targeting/common/xmltohb/simics_AXONE.system.xml +++ b/src/usr/targeting/common/xmltohb/simics_AXONE.system.xml @@ -8478,10 +8478,42 @@ <id>POSITION</id> <default>0</default> </attribute> - <attribute> + <attribute> <id>VPD_REC_NUM</id> <default>0</default> </attribute> + <attribute> + <id>FAPI_POS</id> + <default>0</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0xD0</value></field> + <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0</value></field> + </default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>engine</id><value>3</value></field> + <!-- Engine 3 Port 1 is directly attached to DDIMM0 in the simics axone model --> + <field><id>port</id><value>1</value></field> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>20</value></field> + <field><id>writePageSize</id><value>32</value></field> + <field><id>i2cMuxBusSelector</id><value>0xFF</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0</value></field> + </default> + </attribute> </targetInstance> <targetInstance> @@ -8511,10 +8543,43 @@ <id>POSITION</id> <default>1</default> </attribute> - <attribute> + <attribute> <id>VPD_REC_NUM</id> <default>1</default> </attribute> + <attribute> + <id>FAPI_POS</id> + <default>1</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>0</value></field> + <field><id>devAddr</id><value>0xD0</value></field> + <field><id>i2cMuxBusSelector</id><value>0x08</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/proc-0/i2c_mux-0</value></field> + </default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> + <field><id>port</id><value>0</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <!-- Valid Mux Bus Selections are 0x08-0x0F --> + <field><id>i2cMuxBusSelector</id><value>0x08</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> + </default> + </attribute> </targetInstance> <targetInstance> @@ -8544,10 +8609,43 @@ <id>POSITION</id> <default>2</default> </attribute> - <attribute> + <attribute> <id>VPD_REC_NUM</id> <default>2</default> </attribute> + <attribute> + <id>FAPI_POS</id> + <default>2</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0xD0</value></field> + <field><id>i2cMuxBusSelector</id><value>0x09</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/proc-0/i2c_mux-0</value></field> + </default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> + <field><id>port</id><value>0</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <!-- Valid Mux Bus Selections are 0x08-0x0F --> + <field><id>i2cMuxBusSelector</id><value>0x09</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> + </default> + </attribute> </targetInstance> <targetInstance> @@ -8577,10 +8675,43 @@ <id>POSITION</id> <default>3</default> </attribute> - <attribute> + <attribute> <id>VPD_REC_NUM</id> <default>3</default> </attribute> + <attribute> + <id>FAPI_POS</id> + <default>3</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0xD0</value></field> + <field><id>i2cMuxBusSelector</id><value>0x0A</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/proc-0/i2c_mux-0</value></field> + </default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> + <field><id>port</id><value>0</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <!-- Valid Mux Bus Selections are 0x08-0x0F --> + <field><id>i2cMuxBusSelector</id><value>0x0A</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> + </default> + </attribute> </targetInstance> <targetInstance> @@ -8610,10 +8741,43 @@ <id>POSITION</id> <default>4</default> </attribute> - <attribute> + <attribute> <id>VPD_REC_NUM</id> <default>4</default> </attribute> + <attribute> + <id>FAPI_POS</id> + <default>4</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0xD0</value></field> + <field><id>i2cMuxBusSelector</id><value>0x0B</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/proc-0/i2c_mux-0</value></field> + </default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> + <field><id>port</id><value>0</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <!-- Valid Mux Bus Selections are 0x08-0x0F --> + <field><id>i2cMuxBusSelector</id><value>0x0B</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> + </default> + </attribute> </targetInstance> <targetInstance> @@ -8643,10 +8807,43 @@ <id>POSITION</id> <default>5</default> </attribute> - <attribute> + <attribute> <id>VPD_REC_NUM</id> <default>5</default> </attribute> + <attribute> + <id>FAPI_POS</id> + <default>5</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0xD0</value></field> + <field><id>i2cMuxBusSelector</id><value>0x0C</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/proc-0/i2c_mux-0</value></field> + </default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> + <field><id>port</id><value>0</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <!-- Valid Mux Bus Selections are 0x08-0x0F --> + <field><id>i2cMuxBusSelector</id><value>0x0C</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> + </default> + </attribute> </targetInstance> <targetInstance> @@ -8676,10 +8873,43 @@ <id>POSITION</id> <default>6</default> </attribute> - <attribute> + <attribute> <id>VPD_REC_NUM</id> <default>6</default> </attribute> + <attribute> + <id>FAPI_POS</id> + <default>6</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0xD0</value></field> + <field><id>i2cMuxBusSelector</id><value>0x0D</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/proc-0/i2c_mux-0</value></field> + </default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> + <field><id>port</id><value>0</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <!-- Valid Mux Bus Selections are 0x08-0x0F --> + <field><id>i2cMuxBusSelector</id><value>0x0D</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> + </default> + </attribute> </targetInstance> <targetInstance> @@ -8709,10 +8939,43 @@ <id>POSITION</id> <default>7</default> </attribute> - <attribute> + <attribute> <id>VPD_REC_NUM</id> <default>7</default> </attribute> + <attribute> + <id>FAPI_POS</id> + <default>7</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0xD0</value></field> + <field><id>i2cMuxBusSelector</id><value>0x0E</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/proc-0/i2c_mux-0</value></field> + </default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> + <field><id>port</id><value>0</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <!-- Valid Mux Bus Selections are 0x08-0x0F --> + <field><id>i2cMuxBusSelector</id><value>0x0E</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> + </default> + </attribute> </targetInstance> <targetInstance> @@ -8742,10 +9005,43 @@ <id>POSITION</id> <default>8</default> </attribute> - <attribute> + <attribute> <id>VPD_REC_NUM</id> <default>8</default> </attribute> + <attribute> + <id>FAPI_POS</id> + <default>8</default> + </attribute> + <attribute> + <id>FAPI_I2C_CONTROL_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>port</id><value>1</value></field> + <field><id>devAddr</id><value>0xD0</value></field> + <field><id>i2cMuxBusSelector</id><value>0x0F</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/proc-0/i2c_mux-0</value></field> + </default> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + <default> + <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field> + <field><id>engine</id><value>3</value></field> + <field><id>byteAddrOffset</id><value>0x02</value></field> + <field><id>devAddr</id><value>0xA0</value></field> + <field><id>chipCount</id><value>0x01</value></field> + <!-- Engine 3 Port 0 connects to a 3 to 8 MUX attached to DDIMM1-8 in the simics axone model --> + <field><id>port</id><value>0</value></field> + <field><id>maxMemorySizeKB</id><value>0x4</value></field> + <field><id>writeCycleTime</id><value>05</value></field> + <field><id>writePageSize</id><value>0x20</value></field> + <!-- Valid Mux Bus Selections are 0x08-0x0F --> + <field><id>i2cMuxBusSelector</id><value>0x0F</value></field> + <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field> + </default> + </attribute> </targetInstance> <targetInstance> @@ -8775,10 +9071,16 @@ <id>POSITION</id> <default>9</default> </attribute> - <attribute> + <attribute> <id>VPD_REC_NUM</id> <default>9</default> </attribute> + <attribute> + <id>FAPI_POS</id> + <default>9</default> + </attribute> + <!-- No valid I2C connections to OCMB 9-15 in the Axone simics model + Skip setting EEPROM_VPD_PRIMARY_INFO and FAPI_I2C_CONTROL_INFO--> </targetInstance> <targetInstance> @@ -8808,10 +9110,16 @@ <id>POSITION</id> <default>10</default> </attribute> - <attribute> + <attribute> <id>VPD_REC_NUM</id> <default>10</default> </attribute> + <attribute> + <id>FAPI_POS</id> + <default>10</default> + </attribute> + <!-- No valid I2C connections to OCMB 9-15 in the Axone simics model + Skip setting EEPROM_VPD_PRIMARY_INFO and FAPI_I2C_CONTROL_INFO--> </targetInstance> <targetInstance> @@ -8841,10 +9149,16 @@ <id>POSITION</id> <default>11</default> </attribute> - <attribute> + <attribute> <id>VPD_REC_NUM</id> <default>11</default> </attribute> + <attribute> + <id>FAPI_POS</id> + <default>11</default> + </attribute> + <!-- No valid I2C connections to OCMB 9-15 in the Axone simics model + Skip setting EEPROM_VPD_PRIMARY_INFO and FAPI_I2C_CONTROL_INFO--> </targetInstance> <targetInstance> @@ -8874,10 +9188,16 @@ <id>POSITION</id> <default>12</default> </attribute> - <attribute> + <attribute> <id>VPD_REC_NUM</id> <default>12</default> </attribute> + <attribute> + <id>FAPI_POS</id> + <default>12</default> + </attribute> + <!-- No valid I2C connections to OCMB 9-15 in the Axone simics model + Skip setting EEPROM_VPD_PRIMARY_INFO and FAPI_I2C_CONTROL_INFO--> </targetInstance> <targetInstance> @@ -8907,10 +9227,16 @@ <id>POSITION</id> <default>13</default> </attribute> - <attribute> + <attribute> <id>VPD_REC_NUM</id> <default>13</default> </attribute> + <attribute> + <id>FAPI_POS</id> + <default>13</default> + </attribute> + <!-- No valid I2C connections to OCMB 9-15 in the Axone simics model + Skip setting EEPROM_VPD_PRIMARY_INFO and FAPI_I2C_CONTROL_INFO--> </targetInstance> <targetInstance> @@ -8940,10 +9266,16 @@ <id>POSITION</id> <default>14</default> </attribute> - <attribute> + <attribute> <id>VPD_REC_NUM</id> <default>14</default> </attribute> + <attribute> + <id>FAPI_POS</id> + <default>14</default> + </attribute> + <!-- No valid I2C connections to OCMB 9-15 in the Axone simics model + Skip setting EEPROM_VPD_PRIMARY_INFO and FAPI_I2C_CONTROL_INFO--> </targetInstance> <targetInstance> @@ -8973,10 +9305,16 @@ <id>POSITION</id> <default>15</default> </attribute> - <attribute> + <attribute> <id>VPD_REC_NUM</id> <default>15</default> </attribute> + <attribute> + <id>FAPI_POS</id> + <default>15</default> + </attribute> + <!-- No valid I2C connections to OCMB 9-15 in the Axone simics model + Skip setting EEPROM_VPD_PRIMARY_INFO and FAPI_I2C_CONTROL_INFO--> </targetInstance> <!-- ===================================================================== --> diff --git a/src/usr/targeting/common/xmltohb/target_types_hb.xml b/src/usr/targeting/common/xmltohb/target_types_hb.xml index c1217328d..61d744c4d 100644 --- a/src/usr/targeting/common/xmltohb/target_types_hb.xml +++ b/src/usr/targeting/common/xmltohb/target_types_hb.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2012,2018 --> +<!-- Contributors Listed Below - COPYRIGHT 2012,2019 --> <!-- [+] Google Inc. --> <!-- [+] International Business Machines Corp. --> <!-- --> @@ -90,6 +90,9 @@ <default>0</default> <id>MMIO_VM_ADDR</id> </attribute> + <attribute> + <id>VPD_SWITCHES</id> + </attribute> </targetTypeExtension> <targetTypeExtension> diff --git a/src/usr/vpd/ddimm.C b/src/usr/vpd/ddimm.C index 9c7cdc728..343a49b1e 100644 --- a/src/usr/vpd/ddimm.C +++ b/src/usr/vpd/ddimm.C @@ -26,20 +26,25 @@ * Provides functionality related to the DDIMM package */ -#include <devicefw/driverif.H> + #include <targeting/common/attributes.H> +#include <targeting/common/predicates/predicatectm.H> +#include <devicefw/driverif.H> +#include <fsi/fsiif.H> +#include <i2c/i2cif.H> +#include <initservice/initserviceif.H> #include <vpd/vpd_if.H> +#include <vpd/vpdreasoncodes.H> #include <errl/errlmanager.H> #include <hwas/common/hwasCallout.H> -#include <targeting/common/predicates/predicatectm.H> #include <config.h> -#include <initservice/initserviceif.H> -#include <vpd/vpdreasoncodes.H> #include "spd.H" #include <chipids.H> extern trace_desc_t* g_trac_vpd; +//#define TRACSSCOMP(args...) TRACFCOMP(args) +#define TRACSSCOMP(args...) namespace VPD { @@ -72,98 +77,195 @@ errlHndl_t ocmbPresenceDetect(DeviceFW::OperationType i_opType, va_list i_args) { errlHndl_t l_errl = nullptr; + bool l_ocmb_present = false; + bool l_i2cMaster_exists = false; + TARGETING::Target * l_i2cMasterTarget = nullptr; + TARGETING::Target* l_masterProcTarget = nullptr; + TARGETING::ATTR_FAPI_I2C_CONTROL_INFO_type l_i2cInfo; + uint32_t l_commonPlid = 0; - if (unlikely(io_buflen < sizeof(bool))) - { - TRACFCOMP(g_trac_vpd, - ERR_MRK "VPD::ocmbPresenceDetect> Invalid data length: %d", - io_buflen); - /*@ - * @errortype - * @moduleid VPD::MOD_OCMBPRESENCEDETECT - * @reasoncode VPD::VPD_INVALID_LENGTH - * @userdata1 Data Length - * @userdata2 HUID of target being detected - * @devdesc ocmbPresenceDetect> Invalid data length (!= 1 bytes) - * @custdesc Firmware error during boot - */ - l_errl = - new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, - VPD::MOD_OCMBPRESENCEDETECT, - VPD::VPD_INVALID_LENGTH, - TO_UINT64(io_buflen), - TARGETING::get_huid(i_target), - ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); - io_buflen = 0; - return l_errl; - } + TRACSSCOMP( g_trac_vpd, ENTER_MRK"ocmbPresenceDetect() " + "OCMB HUID 0x%.08X ENTER", TARGETING::get_huid(i_target)); -//@TODO-RTC:196805-Add real implementation -bool l_ocmbvpd_present = true; //default to everything present for now -//------------------------------------------------------------------- -#if 0 - - // First, make sure that the i2c master exists or we can't read - // our vpd -#ifdef CONFIG_MEMVPD_READ_FROM_HW - // look up i2cMasterPath from EEPROM_VPD_PRIMARY_INFO - // check if that target exists directly via FSI - bool l_check_for_vpd = isSlavePresent(i2cMasterTarget); - -#else - // just default to yes for PNOR-based VPD - bool l_check_for_vpd = true; -#endif + do{ - // Next, probe the VPD contents to see if we have anything - bool l_ocmbvpd_present = ...; -#endif + if (unlikely(io_buflen != sizeof(bool))) + { + TRACFCOMP(g_trac_vpd, + ERR_MRK "VPD::ocmbPresenceDetect> Invalid data length: %d", + io_buflen); + /*@ + * @errortype + * @moduleid VPD::MOD_OCMBPRESENCEDETECT + * @reasoncode VPD::VPD_INVALID_LENGTH + * @userdata1 Data Length + * @userdata2 HUID of target being detected + * @devdesc ocmbPresenceDetect> Invalid data length (!= 1 bytes) + * @custdesc Firmware error during boot + */ + l_errl = + new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, + VPD::MOD_OCMBPRESENCEDETECT, + VPD::VPD_INVALID_LENGTH, + TO_UINT64(io_buflen), + TARGETING::get_huid(i_target), + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + break; + } + // Get a ptr to the target service which we will use later on + TARGETING::TargetService& l_targetService = TARGETING::targetService(); -#if defined(CONFIG_MEMVPD_READ_FROM_HW) && defined(CONFIG_MEMVPD_READ_FROM_PNOR) - if( l_ocmbvpd_present ) - { - // Check if the VPD data in the PNOR matches the SEEPROM - l_errl = VPD::ensureCacheIsInSync( i_target ); - if( l_errl ) + // Read Attributes needed to complete the operation + l_i2cInfo = i_target->getAttr<TARGETING::ATTR_FAPI_I2C_CONTROL_INFO>(); + + // Check if the target set as the i2cMasterPath actually exists + l_targetService.exists(l_i2cInfo.i2cMasterPath, l_i2cMaster_exists); + + // if the i2c master listed doesn't exist then bail out -- this OCMB is not present + if(!l_i2cMaster_exists) { - // Save this plid to use later - //l_saved_plid = l_errl->plid(); - l_ocmbvpd_present = false; + TRACFCOMP(g_trac_vpd, + ERR_MRK"VPD::ocmbPresenceDetect> I2C Master in FAPI_I2C_CONTROL_INFO for OCMB 0x.08%X does not exist, target not present", + TARGETING::get_huid(i_target)); - TRACFCOMP(g_trac_vpd,ERR_MRK "VPD::ocmbPresenceDetect> Error during ensureCacheIsInSync (DDIMM)" ); - errlCommit( l_errl, VPD_COMP_ID ); + /*@ + * @errortype + * @moduleid VPD::MOD_OCMBPRESENCEDETECT + * @reasoncode VPD::VPD_INVALID_MASTER_I2C_PATH + * @userdata1 HUID of target being detected + * @userdata2 Unused + * @devdesc ocmbPresenceDetect> Invalid master i2c path + * @custdesc Firmware error during boot + */ + l_errl = + new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, + VPD::MOD_OCMBPRESENCEDETECT, + VPD::VPD_INVALID_MASTER_I2C_PATH, + TARGETING::get_huid(i_target), + 0, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + + break; } - } - else - { - // Defer invalidating DDIMM VPD in the PNOR in case another target - // might be sharing this VPD_REC_NUM. Check all targets sharing this - // VPD_REC_NUM after target discovery in VPD::validateSharedPnorCache. - // Ensure the VPD_SWITCHES cache valid bit is invalid at this point. - TARGETING::ATTR_VPD_SWITCHES_type vpdSwitches = - i_target->getAttr<TARGETING::ATTR_VPD_SWITCHES>(); - vpdSwitches.pnorCacheValid = 0; - i_target->setAttr<TARGETING::ATTR_VPD_SWITCHES>( vpdSwitches ); - } -#endif -//------------------------------------------------------------------- + // if we think it exists then lookup the master path with the target service + l_i2cMasterTarget = l_targetService.toTarget(l_i2cInfo.i2cMasterPath); - if( l_ocmbvpd_present ) - { - //Fsp sets PN/SN so if there is none, do it here - if(!INITSERVICE::spBaseServicesEnabled()) + // if target service returns a null ptr for the path something is wrong and we should + // mark the OCMB not present + if(l_i2cMasterTarget == nullptr) { - // set part and serial number attributes for current target - SPD::setPartAndSerialNumberAttributes( i_target ); + TRACFCOMP(g_trac_vpd, + ERR_MRK"VPD::ocmbPresenceDetect> I2C Master in FAPI_I2C_CONTROL_INFO for OCMB 0x.08%X returned a nullptr, target not present", + TARGETING::get_huid(i_target)); + + /*@ + * @errortype + * @moduleid VPD::MOD_OCMBPRESENCEDETECT + * @reasoncode VPD::VPD_NULL_I2C_MASTER + * @userdata1 HUID of target being detected + * @userdata2 Unused + * @devdesc ocmbPresenceDetect> Master i2c path returned nullptr + * @custdesc Firmware error during boot + */ + l_errl = + new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, + VPD::MOD_OCMBPRESENCEDETECT, + VPD::VPD_NULL_I2C_MASTER, + TARGETING::get_huid(i_target), + 0, + ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); + + break; + } + + TRACSSCOMP( g_trac_vpd, "VPD::ocmbPresenceDetect> i2c master for OCMB 0x%.08X is HUID 0x%.08X", + TARGETING::get_huid(i_target), TARGETING::get_huid(l_i2cMasterTarget)); + + // Master proc is taken as always present. Validate other targets. + TARGETING::targetService().masterProcChipTargetHandle(l_masterProcTarget ); + + if (l_i2cMasterTarget != l_masterProcTarget) + { + // Use the FSI slave presence detection to see if master i2c can be found + if( ! FSI::isSlavePresent(l_i2cMasterTarget) ) + { + TRACFCOMP( g_trac_vpd, + ERR_MRK"ocmbPresenceDetect> isSlavePresent returned false for I2C Master Target 0x%.08X. " + "This implies 0x%.08X is also NOT present", + TARGETING::get_huid(l_i2cMasterTarget), TARGETING::get_huid(i_target)); + break; + } + } + + //*********************************************************************************** + //* If we make it through all of the checks then we have verified master is present * + //*********************************************************************************** + + //Check for the target at the I2C level + l_ocmb_present = I2C::i2cPresence(l_i2cMasterTarget, + l_i2cInfo.port, + l_i2cInfo.engine, + l_i2cInfo.devAddr ); + + if(l_ocmb_present ) + { +#if defined(CONFIG_MEMVPD_READ_FROM_HW) && defined(CONFIG_MEMVPD_READ_FROM_PNOR) + // Check if the VPD data in the PNOR matches the SEEPROM + l_errl = VPD::ensureCacheIsInSync( i_target ); + if( l_errl ) + { + // Save this plid to use later + l_commonPlid = l_errl->plid(); + l_ocmb_present = false; + + TRACFCOMP(g_trac_vpd,ERR_MRK "VPD::ocmbPresenceDetect> Error during ensureCacheIsInSync (DDIMM)" ); + errlCommit( l_errl, VPD_COMP_ID ); + l_errl = nullptr; + } +#endif + //Fsp sets PN/SN so if there is none, do it here + if(!INITSERVICE::spBaseServicesEnabled()) + { + // set part and serial number attributes for current target + SPD::setPartAndSerialNumberAttributes( i_target ); + } } + else + { + TRACFCOMP(g_trac_vpd, + ERR_MRK"VPD::ocmbPresenceDetect> i2cPresence returned false! OCMB chip 0x%.08X is NOT Present!", + TARGETING::get_huid(i_target)); + } + }while(0); + + if(!l_ocmb_present) + { + // Invalidate the SPD in PNOR + l_errl = VPD::invalidatePnorCache(i_target); + if (l_errl) + { + // Link the logs if there was an existing log + if(l_commonPlid) + { + l_errl->plid(l_commonPlid); + } + TRACFCOMP( g_trac_vpd, ERR_MRK"dimmPresenceDetect() " + "Error invalidating SPD in PNOR for target 0x%.08X", + TARGETING::get_huid(i_target)); + } } - memcpy(io_buffer, &l_ocmbvpd_present, sizeof(l_ocmbvpd_present)); - io_buflen = sizeof(l_ocmbvpd_present); - return nullptr; + // Copy variable describing if ocmb is present or not to i/o buffer param + memcpy(io_buffer, &l_ocmb_present, sizeof(l_ocmb_present)); + io_buflen = sizeof(l_ocmb_present); + + TRACSSCOMP( g_trac_vpd, EXIT_MRK"ocmbPresenceDetect() " + "OCMB HUID 0x%.08X EXIT", TARGETING::get_huid(i_target)); + + return l_errl; } // Register the presence detect function with the device framework |
