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-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_gpe_init.C2
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C8
-rw-r--r--src/import/chips/p9/procedures/xml/error_info/p9_pm_occ_gpe_init_errors.xml6
-rw-r--r--src/import/chips/p9/procedures/xml/error_info/p9_pm_registers.xml40
-rw-r--r--src/import/chips/p9/procedures/xml/error_info/p9_pm_stop_gpe_init_errors.xml16
5 files changed, 60 insertions, 12 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_gpe_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_gpe_init.C
index c71d32ee4..41e072919 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_gpe_init.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_gpe_init.C
@@ -182,7 +182,7 @@ fapi2::ReturnCode pm_occ_gpe_reset(
FAPI_ASSERT((l_pollCount != 0),
fapi2::PM_OCC_GPE_RESET_TIMEOUT()
- .set_OCCGPESTATUS(l_data64),
+ .set_CHIP(i_target),
"OCC GPE could not be halted during reset operation.");
//Clear status (Instruction Address) register
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C
index a6d8ca549..cd96c993e 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C
@@ -245,7 +245,6 @@ fapi2::ReturnCode stop_gpe_init(
l_ir,
l_timeout_in_MS);
fapi2::delay(SGPE_POLLTIME_MS * 1000, SGPE_POLLTIME_MCYCLES * 1000 * 1000);
-
}
while((!((l_occ_flag.getBit<p9hcd::SGPE_ACTIVE>() == 1) &&
(l_xsr.getBit<p9hcd::HALTED_STATE>() == 0))) &&
@@ -260,8 +259,7 @@ fapi2::ReturnCode stop_gpe_init(
FAPI_ASSERT((l_timeout_in_MS != 0),
fapi2::STOP_GPE_INIT_TIMEOUT()
- .set_OCCFLGSTAT(l_occ_flag)
- .set_XSR(l_xsr),
+ .set_CHIP(i_target),
"STOP GPE Init timeout");
fapi_try_exit:
@@ -287,7 +285,6 @@ fapi2::ReturnCode stop_gpe_reset(
fapi2::buffer<uint64_t> l_data64;
uint32_t l_timeout_in_MS = 100;
-
FAPI_IMP(">> stop_gpe_reset...");
// Program XCR to HALT SGPE
@@ -306,12 +303,13 @@ fapi2::ReturnCode stop_gpe_reset(
do
{
FAPI_TRY(getScom(i_target, PU_GPE3_GPEXIXSR_SCOM, l_data64));
+ fapi2::delay(SGPE_POLLTIME_MS * 1000, SGPE_POLLTIME_MCYCLES * 1000 * 1000);
}
while((l_data64.getBit<p9hcd::HALTED_STATE>() == 0) && (--l_timeout_in_MS != 0));
FAPI_ASSERT((l_timeout_in_MS != 0),
fapi2::STOP_GPE_RESET_TIMEOUT()
- .set_SGPEXSRNOTHALT(l_data64),
+ .set_CHIP(i_target),
"STOP GPE Init timeout");
FAPI_INF(" Clear SGPE_ACTIVE in OCC Flag Register...");
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_occ_gpe_init_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_occ_gpe_init_errors.xml
index 5423d02df..e8b948db7 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_occ_gpe_init_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_occ_gpe_init_errors.xml
@@ -33,7 +33,11 @@
<hwpError>
<rc>RC_PM_OCC_GPE_RESET_TIMEOUT</rc>
<description>Failed to halt OCC GPE during RESET operation.</description>
- <ffdc>OCCGPESTATUS</ffdc>
+ <collectRegisterFfdc>
+ <id>OCCGPE_FFDC_REGISTERS</id>
+ <target>CHIP</target>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ </collectRegisterFfdc>
</hwpError>
<!-- ********************************************************************* -->
</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_registers.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_registers.xml
index e94b37273..ba0611cd6 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_registers.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_registers.xml
@@ -27,6 +27,7 @@
<hwpErrors>
<!-- *********************************************************************** -->
<registerFfdc>
+ <!--TODO: RTC 163970: Add the register GPE[n] XISIB to FFDC -->
<id>CME_FFDC_REGISTERS</id>
<scomRegister>EX_PPE_XIRAMDBG</scomRegister>
<scomRegister>EX_CME_LCL_EISR_SCOM</scomRegister>
@@ -60,4 +61,43 @@
<scomRegister>EX_CME_SCOM_SRTCH1_SCOM</scomRegister>
</registerFfdc>
<!-- *********************************************************************** -->
+ <registerFfdc>
+ <id>SGPE_FFDC_REGISTERS</id>
+ <scomRegister>PU_OCB_OCI_OCCFLG_SCOM</scomRegister>
+ <scomRegister>PU_GPE3_GPEXIXSR_SCOM</scomRegister>
+ <scomRegister>PU_GPE3_GPEXIIAR_SCOM</scomRegister>
+ <scomRegister>PU_GPE3_GPEXIIR_SCOM</scomRegister>
+ <scomRegister>PU_GPE3_GPETSEL_SCOM</scomRegister>
+ <scomRegister>PU_GPE3_GPEIVPR_SCOM</scomRegister>
+ <scomRegister>PU_GPE3_GPESTR_SCOM</scomRegister>
+ <scomRegister>PU_GPE3_GPEMACR_SCOM</scomRegister>
+ <scomRegister>PU_GPE3_MIB_XISGB</scomRegister>
+ <scomRegister>PU_GPE3_MIB_XIICAC</scomRegister>
+ <scomRegister>PU_GPE3_MIB_XIDCAC_SCOM</scomRegister>
+ </registerFfdc>
+ <!-- ******************************************************************** -->
+ <registerFfdc>
+ <id>OCCGPE_FFDC_REGISTERS</id>
+ <scomRegister>PU_GPE0_GPEXIXSR_SCOM</scomRegister>
+ <scomRegister>PU_GPE0_GPEXIIAR_SCOM</scomRegister>
+ <scomRegister>PU_GPE0_GPEXIIR_SCOM</scomRegister>
+ <scomRegister>PU_GPE1_GPEXIXSR_SCOM</scomRegister>
+ <scomRegister>PU_GPE1_GPEXIIAR_SCOM</scomRegister>
+ <scomRegister>PU_GPE1_GPEXIIR_SCOM</scomRegister>
+ <scomRegister>PU_GPE0_GPETSEL_SCOM</scomRegister>
+ <scomRegister>PU_GPE0_GPEIVPR_SCOM</scomRegister>
+ <scomRegister>PU_GPE0_GPESTR_SCOM</scomRegister>
+ <scomRegister>PU_GPE0_GPEMACR_SCOM</scomRegister>
+ <scomRegister>PU_GPE0_MIB_XISGB</scomRegister>
+ <scomRegister>PU_GPE0_MIB_XIICAC</scomRegister>
+ <scomRegister>PU_GPE0_MIB_XIDCAC_SCOM</scomRegister>
+ <scomRegister>PU_GPE1_GPETSEL_SCOM</scomRegister>
+ <scomRegister>PU_GPE1_GPEIVPR_SCOM</scomRegister>
+ <scomRegister>PU_GPE1_GPESTR_SCOM</scomRegister>
+ <scomRegister>PU_GPE1_GPEMACR_SCOM</scomRegister>
+ <scomRegister>PU_GPE1_MIB_XISGB</scomRegister>
+ <scomRegister>PU_GPE1_MIB_XIICAC</scomRegister>
+ <scomRegister>PU_GPE1_MIB_XIDCAC_SCOM</scomRegister>
+ </registerFfdc>
+ <!-- ******************************************************************** -->
</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_stop_gpe_init_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_stop_gpe_init_errors.xml
index 87d4c711a..a59eb093d 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_stop_gpe_init_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_stop_gpe_init_errors.xml
@@ -22,7 +22,6 @@
<!-- permissions and limitations under the License. -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
-<!-- Error definitions for p9_pm_ocb_init procedure -->
<hwpErrors>
<!-- ******************************************************************** -->
<hwpError>
@@ -34,17 +33,24 @@
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_STOP_GPE_INIT_TIMEOUT</rc>
- <description> Stop GPE init timedout while waiting for SGPE ACtive in OCCFLG register.
+ <description> Stop GPE init timed out while waiting for SGPE Active in OCCFLG register.
</description>
- <ffdc>OCCFLGSTAT</ffdc>
- <ffdc>XSR</ffdc>
+ <collectRegisterFfdc>
+ <id>SGPE_FFDC_REGISTERS</id>
+ <target>CHIP</target>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ </collectRegisterFfdc>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_STOP_GPE_RESET_TIMEOUT</rc>
<description> Stop GPE init timedout while waiting for HALT status in XSR register.
</description>
- <ffdc>SGPEXSRNOTHALT</ffdc>
+ <collectRegisterFfdc>
+ <id>SGPE_FFDC_REGISTERS</id>
+ <target>CHIP</target>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ </collectRegisterFfdc>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
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