diff options
| -rw-r--r-- | src/import/chips/p9/security/Centaur_Register_List.csv | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/import/chips/p9/security/Centaur_Register_List.csv b/src/import/chips/p9/security/Centaur_Register_List.csv index 630913628..44780455a 100644 --- a/src/import/chips/p9/security/Centaur_Register_List.csv +++ b/src/import/chips/p9/security/Centaur_Register_List.csv @@ -1,9 +1,8 @@ #Register Address,WAND,WOR,Init/Expected Value,Mask Value, 1000000,1000004,1000005,7001900000000003,, +2000000,2000004,2000005,7001900000000003,, # @TODO: RTC 187288 # Some bits (see mask) are not tracking as expected -2000000,2000004,2000005,7001900000000003,FFFE7FFFFFFFFFFD, -2010800,2010801,2010802,0000400000000000,, 2010803,2010804,2010805,FFFFFFE000000000,, 2010C42,,,,, 201140A,,,,, @@ -42,6 +41,8 @@ # modeling the auto reset behavior 2030006,,,0FE00E0000000000,3FFFFFFFFFFFFFFF, 2030007,,,,, +20F0012,20F0013,20F0014,8016200000000000,, +3000000,3000004,3000005,7001900000000003,, # @TODO: RTC 187288 # Enabling causes 2011882 to report wrongly for some reason #20F0012,20F0013,20F0014,4016620000000000,3FFFBDFFFFFFFFFF, @@ -133,10 +134,10 @@ 30106C5,,,,, 30106C6,,,,, 30106C7,,,,, -30106DB,,,,, 3012300,,,0000A00000000000,, 301230B,,,,, 3030000,,,,, +30F0012,30F0013,30F0014,8016200000000000,, # @TODO: RTC 187288 # Enabling this register causes failing # behavior for 303000 |
