diff options
| -rw-r--r-- | src/usr/intr/intrrp.C | 40 | ||||
| -rw-r--r-- | src/usr/intr/intrrp.H | 2 |
2 files changed, 28 insertions, 14 deletions
diff --git a/src/usr/intr/intrrp.C b/src/usr/intr/intrrp.C index 2ec9d9a72..79e8ee052 100644 --- a/src/usr/intr/intrrp.C +++ b/src/usr/intr/intrrp.C @@ -125,6 +125,22 @@ errlHndl_t IntrRp::_init() break; } + //Disable Incoming PSI Interrupts + TRACDCOMP(g_trac_intr, "IntrRp::_init() Disabling PSI Interrupts"); + uint64_t l_disablePsiIntr = PSI_BRIDGE_INTP_STATUS_CTL_DISABLE_PSI; + uint64_t size = sizeof(l_disablePsiIntr); + l_err = deviceWrite(procTarget, + &l_disablePsiIntr, + size, + DEVICE_SCOM_ADDRESS(PSI_BRIDGE_INTP_STATUS_CTL_CLR_SCOM_ADDR)); + + if (l_err) + { + TRACFCOMP(g_trac_intr, + "IntrRp::_init() Error disabling PSI Interrupts."); + break; + } + //TODO RTC 134431 #ifdef CONFIG_MPIPL_ENABLED uint8_t is_mpipl = 0; @@ -879,15 +895,13 @@ errlHndl_t IntrRp::maskInterruptSource(uint8_t l_intr_source) l_psiHbEsbptr += (((l_intr_source*PAGE_SIZE)+PSI_BRIDGE_ESB_OFF_OFFSET)/sizeof(uint64_t)); - uint64_t l_maskRead = *l_psiHbEsbptr; - TRACDCOMP(g_trac_intr, "Mask read result: %lx", l_maskRead); - -/* - TODO RTC 150260 + //MMIO Read to this address transitions the ESB to the off state + volatile uint64_t l_maskRead = *l_psiHbEsbptr; + eieio(); - //Perform 2nd read to verify in OFF state + //Perform 2nd read to verify in OFF state - the read returns the previous + // esb state, so a 2nd read is required to know it is in the off state l_maskRead = *l_psiHbEsbptr; - TRACDCOMP(g_trac_intr, "Mask read result: %lx", l_maskRead); if (l_maskRead != ESB_STATE_OFF) { @@ -905,7 +919,6 @@ errlHndl_t IntrRp::maskInterruptSource(uint8_t l_intr_source) ); } -**/ return l_err; } @@ -917,12 +930,12 @@ errlHndl_t IntrRp::unmaskInterruptSource(uint8_t l_intr_source) l_psiHbEsbptr += (((l_intr_source*PAGE_SIZE)+PSI_BRIDGE_ESB_RESET_OFFSET)/sizeof(uint64_t)); - uint64_t l_unmaskRead = *l_psiHbEsbptr; - TRACDCOMP(g_trac_intr, "Unmask read result: %lx", l_unmaskRead); - -/* TODO RTC 150260 + //MMIO Read to this address transitions the ESB to the RESET state + volatile uint64_t l_unmaskRead = *l_psiHbEsbptr; + eieio(); - //Read 2nd time to verify proper ESB state + //Perform 2nd read to verify in RESET state - the read returns the previous + // esb state, so a 2nd read is required to know it is in the off state l_unmaskRead = *l_psiHbEsbptr; if (l_unmaskRead != ESB_STATE_RESET) @@ -941,7 +954,6 @@ errlHndl_t IntrRp::unmaskInterruptSource(uint8_t l_intr_source) ); } -**/ return l_err; } diff --git a/src/usr/intr/intrrp.H b/src/usr/intr/intrrp.H index 869bb1cd4..7b424fa02 100644 --- a/src/usr/intr/intrrp.H +++ b/src/usr/intr/intrrp.H @@ -207,8 +207,10 @@ namespace INTR XIVE_IVPE_QW3_LSI_ENABLE = 0x81, PSI_BRIDGE_INTP_STATUS_CTL_SCOM_ADDR = 0x0501290E, + PSI_BRIDGE_INTP_STATUS_CTL_CLR_SCOM_ADDR = 0x05012913, PSI_BRIDGE_INTP_STATUS_CTL_ENABLE = 0x8000000000000000ULL, PSI_BRIDGE_INTP_STATUS_CTL_RESET = 0x4000000000000000ULL, + PSI_BRIDGE_INTP_STATUS_CTL_DISABLE_PSI = 0x1000000000000000ULL, XIVE_RESET_INT_CQ_RST_CTL_SCOM_ADDR = 0x05013023, XIVE_RESET_POWERBUS_QUIESCE_ENABLE = 0x4000000000000000, |
