diff options
9 files changed, 430 insertions, 2657 deletions
diff --git a/src/usr/hwpf/hwp/dimm_spd_attributes.xml b/src/usr/hwpf/hwp/dimm_spd_attributes.xml index 3c5bb2353..30e6fa316 100644 --- a/src/usr/hwpf/hwp/dimm_spd_attributes.xml +++ b/src/usr/hwpf/hwp/dimm_spd_attributes.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2014 --> <!-- --> <!-- p1 --> <!-- --> @@ -20,7 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: dimm_spd_attributes.xml,v 1.33 2013/11/11 17:14:23 bellows Exp $ --> +<!-- $Id: dimm_spd_attributes.xml,v 1.34 2014/01/10 22:52:22 bellows Exp $ --> <!-- XML file specifying DIMM SPD attributes used by HW Procedures. --> <attributes> @@ -1412,30 +1412,6 @@ file <array> 2 2</array> </attribute> -<!-- TODO: RTC 82331 - Add this attribute to the Accessor HWP -<attribute> - <id>ATTR_VPD_DRAM_2N_MODE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description> - The 2N/2T characteristic of the DIMM from the VPD MR keyword. If the memory controller needs to run on 2N mode, the address is presented for two cycles. By default, 2N should be set to INVALID until the platform initializes it. - </description> - <valueType>uint8</valueType> - <enum>FALSE = 0, TRUE = 1</enum> - <platInit/> -</attribute> - -<attribute> - <id>ATTR_EFF_DIMM_SPARE_TEMP</id> - <targetType>TARGET_TYPE_DIMM</targetType> - <description>Spare DRAM availability. temporary version, will be replaced by the VPD version</description> - <valueType>uint8</valueType> - <enum>NO_SPARE = 0, LOW_NIBBLE = 1, HIGH_NIBBLE = 2, FULL_BYTE = 3</enum> - <odmVisable/> - <writeable/> - <odmChangeable/> -</attribute> ---> - <!-- Attributes added to support the VPD which was formally using the EFF settings --> <attribute> @@ -2312,6 +2288,7 @@ This Attribute is to be interpreted as an Integer</description> <!-- <description>Spare DRAM availability. It comes from the VPD or SPD in ISDIMM systems</description> --> <!-- <valueType>uint8</valueType> --> <!-- <enum>NO_SPARE = 0, LOW_NIBBLE = 1, HIGH_NIBBLE = 2, FULL_BYTE = 3</enum> --> +<!-- <platInit/> --> <!-- <odmVisable/> --> <!-- <odmChangeable/> --> <!-- <array> 2 2 4</array> --> @@ -2424,9 +2401,19 @@ Comes from the VPD MW Keyword</description> <odmVisable/> </attribute> -<!-- TODO: RTC 82331 - Add this attribute to the Accessor HWP <attribute> - <id>ATTR_VPD_CDIMM_MASTER_POWER_SLOPE</id> + <id>ATTR_VPD_DRAM_2N_MODE_ENABLED</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Describes if this MBA is in 2N address mode. The DIMM attributes associated with this MBA describes if this mode is needed for SI. Come from the VPD and consumed in the mba_def.initfile.</description> + <valueType>uint8</valueType> + <enum>FALSE = 0, TRUE = 1</enum> + <platInit/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_CDIMM_VPD_MASTER_POWER_SLOPE</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> <description>Master Power Slope that comes from the VPD MW Keyword</description> <valueType>uint32</valueType> @@ -2436,7 +2423,7 @@ Comes from the VPD MW Keyword</description> </attribute> <attribute> - <id>ATTR_VPD_CDIMM_MASTER_POWER_INTERCEPT</id> + <id>ATTR_CDIMM_VPD_MASTER_POWER_INTERCEPT</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> <description>Master Power Intercept that comes from the VPD MW Keyword</description> <valueType>uint32</valueType> @@ -2446,7 +2433,7 @@ Comes from the VPD MW Keyword</description> </attribute> <attribute> - <id>ATTR_VPD_CDIMM_SUPPLIER_POWER_SLOPE</id> + <id>ATTR_CDIMM_VPD_SUPPLIER_POWER_SLOPE</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> <description>Supplier Power Slope that comes from the VPD the MV Keyword</description> <valueType>uint32</valueType> @@ -2456,7 +2443,7 @@ Comes from the VPD MW Keyword</description> </attribute> <attribute> - <id>ATTR_VPD_CDIMM_SUPPLIER_POWER_INTERCEPT</id> + <id>ATTR_CDIMM_VPD_SUPPLIER_POWER_INTERCEPT</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> <description>Supplier Power Intercept that comes from MV Keyword</description> <valueType>uint32</valueType> @@ -2464,18 +2451,18 @@ Comes from the VPD MW Keyword</description> <odmVisable/> <persistRuntime/> </attribute> ---> <attribute> - <id>ATTR_VPD_DRAM_2N_MODE_ENABLED</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Describes if this MBA is in 2N address mode. The DIMM attributes associated with this MBA describes if this mode is needed for SI. Come from the VPD and consumed in the mba_def.initfile.</description> - <valueType>uint8</valueType> - <enum>FALSE = 0, TRUE = 1</enum> - <odmVisable/> - <odmChangeable/> + <id>ATTR_L4_BANK_DELETE_VPD</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>L4 Bank Delete settings in VPD. +Denotes what banks have been deleted from the L4. +Data will be pulled from CDIMM VPD if CDIMM present. +Data will be pulled from backplane VPD if IS DIMMs present.</description> + <valueType>uint32</valueType> + <writeable/> + <persistent/> </attribute> - </attributes> diff --git a/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.C b/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.C index db118d734..9ca589880 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.C +++ b/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013 */ +/* COPYRIGHT International Business Machines Corp. 2013,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_lrdimm_funcs.C,v 1.5 2013/12/03 22:51:13 kcook Exp $ +// $Id: mss_lrdimm_funcs.C,v 1.6 2014/01/07 21:50:11 bellows Exp $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2013 // *! All Rights Reserved -- Property of IBM @@ -40,11 +40,12 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- -// 1.5 | 12/03/13 | kcook | Updated VPD attributes. -// 1.4 | 09/16/13 | bellows | Hostboot compile update -// 1.3 | 09/16/13 | bellows | Added ID tag. -// 1.2 | 09/13/13 | kcook | Updated define FAPI_LRDIMM token. -// 1.1 | 08/27/13 | kcook | First drop of Centaur +// 1.6 | bellows |02-JAN-14| VPD attribute removal +// 1.5 | kcook |12/03/13 | Updated VPD attributes. +// 1.4 | bellows |09/16/13 | Hostboot compile update +// 1.3 | bellows |09/16/13 | Added ID tag. +// 1.2 | kcook |09/13/13 | Updated define FAPI_LRDIMM token. +// 1.1 | kcook |08/27/13 | First drop of Centaur //---------------------------------------------------------------------- // Includes @@ -1503,7 +1504,7 @@ fapi::ReturnCode mss_lrdimm_rewrite_odt( const Target& i_target_mba, uint32_t * { ReturnCode rc; uint8_t l_num_ranks_per_dimm_u8array[PORT_SIZE][DIMM_SIZE]; - uint8_t l_arr_offset; +// uint8_t l_arr_offset; uint32_t l_mss_freq = 0; uint8_t l_dram_width_u8; @@ -1517,7 +1518,7 @@ fapi::ReturnCode mss_lrdimm_rewrite_odt( const Target& i_target_mba, uint32_t * rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm_u8array); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width_u8); if(rc) return rc; - uint8_t l_start=44, l_end=60; +// uint8_t l_start=44, l_end=60; if ( (l_num_ranks_per_dimm_u8array[0][1] == 4) || (l_num_ranks_per_dimm_u8array[1][1] == 4) ) { odt_array = var_array_p_array[0]; FAPI_INF("Setting LRDIMM ODT_RD as 4 rank dimm"); @@ -1538,9 +1539,10 @@ fapi::ReturnCode mss_lrdimm_rewrite_odt( const Target& i_target_mba, uint32_t * FAPI_INF("Setting LRDIMM ODT_RD as 2 logical rank dimm"); } - for ( l_arr_offset = l_start; l_arr_offset < l_end; l_arr_offset++ ) { - *(p_b_var_array + l_arr_offset) = *(odt_array + l_arr_offset); - } +// mdb - we do not have eff config attributes, so we can't set this array. This function probably goes away +// for ( l_arr_offset = l_start; l_arr_offset < l_end; l_arr_offset++ ) { +// *(p_b_var_array + l_arr_offset) = *(odt_array + l_arr_offset); +// } return rc; } diff --git a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile index 8dd1d6bc8..e3507a0b9 100755 --- a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile +++ b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile @@ -1,4 +1,4 @@ -#-- $Id: cen_ddrphy.initfile,v 1.28 2013/12/02 21:15:01 asaetow Exp $ +#-- $Id: cen_ddrphy.initfile,v 1.29 2014/01/14 02:24:08 mwuu Exp $ #-- $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/ #-- centaur/working/procedures/ec_ind/scoms/cen_ddrphy.initfile,v $ # @@ -6,6 +6,8 @@ #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +# 1.29|mwuu |01/14/14|Added VPD attributes for TSYS_ADR, TSYS_DP18, +# | | |changed DIMM_TYPE for obsolete CDIMM enum # 1.28|mwuu |11/22/13|Update for VPD attributes # 1.27|mwuu |11/01/13|Had a typo for ATTR_VPD_CEN_PHASE_ROT_M_CMD_A8, # |port A was getting the value of A9 phase rotator. @@ -173,7 +175,7 @@ define def_not_ddr4 = (ATTR_EFF_DRAM_GEN != ENUM_ATTR_EFF_DRAM_GEN_DDR4) ; # not # shorter test for DIMM type define def_is_rdimm = (ATTR_EFF_DIMM_TYPE == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) ; # RDIMM = 1 -#define def_is_udimm = (ATTR_EFF_DIMM_TYPE == ENUM_ATTR_EFF_DIMM_TYPE_UDIMM) ; # UDIMM = 2 +define def_is_udimm = (ATTR_EFF_DIMM_TYPE == ENUM_ATTR_EFF_DIMM_TYPE_UDIMM) ; # UDIMM = 2 define def_is_lrdimm = (ATTR_EFF_DIMM_TYPE == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ; # LRDIMM = 3 # shorter test for DRAM width @@ -289,10 +291,10 @@ define def_cdi_spcke_ohm30_p1 = (ATTR_VPD_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_VPD_ define def_cdi_spcke_ohm40_p1 = (ATTR_VPD_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40) ; # OHM40 = 0x28 (40) # define for glacier1(1), glacier2=normal(0) remove dimm_type != cdimm later -define def_is_type1 = ((ATTR_MSS_DQS_SWIZZLE_TYPE == 1) && ((ATTR_EFF_CUSTOM_DIMM != ENUM_ATTR_EFF_CUSTOM_DIMM_YES) || (ATTR_EFF_DIMM_TYPE != ENUM_ATTR_EFF_DIMM_TYPE_CDIMM))); +define def_is_type1 = ((ATTR_MSS_DQS_SWIZZLE_TYPE == 1) && (ATTR_EFF_CUSTOM_DIMM != ENUM_ATTR_EFF_CUSTOM_DIMM_YES)); # remove dimm_type == cdimm later -define def_is_custom = ((ATTR_EFF_CUSTOM_DIMM == ENUM_ATTR_EFF_CUSTOM_DIMM_YES) || (ATTR_EFF_DIMM_TYPE == ENUM_ATTR_EFF_DIMM_TYPE_CDIMM)); +define def_is_custom = ((ATTR_EFF_CUSTOM_DIMM == ENUM_ATTR_EFF_CUSTOM_DIMM_YES) && (def_is_udimm)); # define for 2 cycle addressing mode (2N) define def_2N_mode = (ATTR_VPD_DRAM_2N_MODE_ENABLED == ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_TRUE) ; @@ -4201,8 +4203,8 @@ scom 0x800(0,1)CC050301143F { # _P[0:1] scom 0x800(0,1)3C030301143f { # DIR1_P[0:1]_[0:4] via broadcast bits , scom_data , expr ; # 0:47 , 0x000000000000, any ; # reserved -# 48:52 , 0b000000 , any ; # reserved... used to be DATA_BIT_DIR_16_23 - 53 , 0b0 , any ; # DD2_FIX_DIS +# 48:52 , 0b00000 , any ; # reserved... used to be DATA_BIT_DIR_16_23 + 53 , 0b0 , any ; # DD2_FIX_DIS, disable fixes for DP18 write logic 54 , 0b1 , any ; # TOXDRV_HIBERNATE # Thin oxide driver hibernation disable. 55 , 0b0 , any ; # ATEST_MUX_CTL_EN 56 , 0b0 , any ; # WL_ADVANCE_DISABLE @@ -4973,6 +4975,8 @@ scom 0x800(0,1)BC330301143F { # _P[0:1]_ADR32S[0:1] via broadcast # !! NOTE different depending on EC level, system voltage too? # value in the scom_data field is right aligned 48:55 , 0x60 , (def_is_sim) ; # ADR32_TSYS_WRCLK sim set to 0x60 + 48:55 , 0x70 , (ATTR_MSS_EFF_VPD_VERSION < 0x10); # if lower than v6.0 / VZ 0x10, use hardcode + 48:55 , (ATTR_VPD_TSYS_ADR[0]), any ; # below is for fast process parts # 48:55 , 0x15 , (CEN.ATTR_MSS_FREQ < 1458) ; # 1333 Mbps, and 1066 (21) # 48:55 , 0x19 , (CEN.ATTR_MSS_FREQ < 1724) ; # 1600 Mbps (25) @@ -4987,7 +4991,7 @@ scom 0x800(0,1)BC330301143F { # _P[0:1]_ADR32S[0:1] via broadcast # 48:55 , 0x35 , (CEN.ATTR_MSS_FREQ < 1724) ; # 1600 Mbps (53) # 48:55 , 0x3E , any ; # 1866 Mbps (62) #-------- debug ----------------------------- - 48:55 , 0x70 , any ; +# 48:55 , 0x70 , any ; # 56:63 , 0x00 , any ; # reserved } @@ -5012,6 +5016,8 @@ scom 0x800(0,1)3C740301143F { #_P[0:1]_[0:4] via broadcast # !! NOTE different depending on EC level # value in the scom_data field is right aligned 48:55 , 0x60 , (def_is_sim) ; # DP18_TSYS_WRCLK sim set to 0x60 + 48:55 , 0x6B , (ATTR_MSS_EFF_VPD_VERSION < 0x10); # if lower than v6.0 / VZ 0x10, use hardcode + 48:55 , (ATTR_VPD_TSYS_DP18[0]), any ; # below is for fast process parts # 48:55 , 0x14 , (CEN.ATTR_MSS_FREQ < 1458) ; # 1333 Mbps, and 1066 (20) # 48:55 , 0x18 , (CEN.ATTR_MSS_FREQ < 1724) ; # 1600 Mbps (24) @@ -5026,7 +5032,7 @@ scom 0x800(0,1)3C740301143F { #_P[0:1]_[0:4] via broadcast # 48:55 , 0x35 , (CEN.ATTR_MSS_FREQ < 1724) ; # 1600 Mbps (53) # 48:55 , 0x3E , any ; # 1866 Mbps (62) #-------- debug ----------------------------- - 48:55 , 0x6B , any ; +# 48:55 , 0x6B , any ; # 56:63 , 0x00 , any ; # reserved } diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C index 5c346d576..3b1af2e43 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_config.C,v 1.33 2013/09/16 13:56:33 bellows Exp $ +// $Id: mss_eff_config.C,v 1.36 2014/01/13 19:57:59 bellows Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/ // centaur/working/procedures/ipl/fapi/mss_eff_config.C,v $ //------------------------------------------------------------------------------ @@ -44,6 +44,10 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.35 | bellows |13-JAN-14| Make VPD version available at mba level +// 1.35 | asaetow |13-JAN-14| Fixed ATTR_EFF_DRAM_DLL_PPD from SLOWEXIT to FASTEXIT. +// | | | Added comments and converted some attr to use enums. +// 1.34 | bellows |02-JAN-14| VPD attribute removal // 1.33 | bellows |16-SEP-13| Hostboot compile update // 1.32 | kcook |13-SEP-13| Added using namespace fapi. // 1.31 | kcook |13-SEP-13| Updated define FAPI_LRDIMM token. @@ -278,6 +282,7 @@ struct mss_eff_config_spd_data // [DIMM_SIZE]; // HERE uint8_t bad_dq_data[PORT_SIZE][DIMM_SIZE] // [SPD_ATTR_SIZE_80]; + uint32_t vpd_version[PORT_SIZE][DIMM_SIZE]; }; //------------------------------------------------------------------------------ @@ -291,10 +296,9 @@ struct mss_eff_config_atts // AST HERE: Needs SPD byte68:76 uint64_t eff_dimm_rcd_cntl_word_0_15[PORT_SIZE][DIMM_SIZE]; uint8_t eff_dimm_size[PORT_SIZE][DIMM_SIZE]; - uint8_t eff_dimm_spare[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; uint8_t eff_dimm_type; uint8_t eff_custom_dimm; - uint8_t eff_dram_al; // initialized to 1 + uint8_t eff_dram_al; // Always use AL = CL - 1. uint8_t eff_dram_asr; uint8_t eff_dram_bl; uint8_t eff_dram_banks; @@ -304,14 +308,14 @@ struct mss_eff_config_atts uint8_t eff_dram_cwl; uint8_t eff_dram_density; uint8_t eff_dram_dll_enable; - uint8_t eff_dram_dll_ppd; - uint8_t eff_dram_dll_reset; // initialized to 1 + uint8_t eff_dram_dll_ppd; // Always use fast exit. + uint8_t eff_dram_dll_reset; // Always reset DLL at start of IPL. uint8_t eff_dram_gen; uint8_t eff_dram_output_buffer; uint8_t eff_dram_pasr; uint8_t eff_dram_rbt; uint8_t eff_dram_rows; - uint8_t eff_dram_srt; // initialized to 1 + uint8_t eff_dram_srt; // Always use extended operating temp range. uint8_t eff_dram_tdqs; uint8_t eff_dram_tfaw; uint32_t eff_dram_tfaw_u32; @@ -367,6 +371,7 @@ struct mss_eff_config_atts uint8_t eff_stack_type[PORT_SIZE][DIMM_SIZE]; uint32_t eff_zqcal_interval; uint8_t dimm_functional_vector; + uint32_t eff_vpd_version; }; @@ -623,6 +628,11 @@ fapi::ReturnCode mss_eff_config_read_spd_data(fapi::Target i_target_dimm, // HERE rc = FAPI_ATTR_GET(ATTR_SPD_BAD_DQ_DATA, &i_target_dimm, //p_o_spd_data->bad_dq_data[i_port][i_dimm]); //if(rc) break; + + rc = FAPI_ATTR_GET(ATTR_VPD_VERSION, &i_target_dimm, + p_o_spd_data->vpd_version[i_port][i_dimm]); + if(rc) break; + } while(0); return rc; @@ -1092,9 +1102,10 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( fapi::ReturnCode rc; // set select atts members to non-zero - p_o_atts->eff_dram_al = 1; - p_o_atts->eff_dram_dll_reset = 1; - p_o_atts->eff_dram_srt = 1; + p_o_atts->eff_dram_al = fapi::ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_1; // Always use AL = CL - 1. + p_o_atts->eff_dram_dll_ppd = fapi::ENUM_ATTR_EFF_DRAM_DLL_PPD_FASTEXIT; // Always use fast exit. + p_o_atts->eff_dram_dll_reset = fapi::ENUM_ATTR_EFF_DRAM_DLL_RESET_YES; // Always reset DLL at start of IPL. + p_o_atts->eff_dram_srt = fapi::ENUM_ATTR_EFF_DRAM_SRT_EXTEND; // Always use extended operating temp range. // array init for(int i = 0; i < PORT_SIZE; i++) { @@ -1590,6 +1601,9 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( // Added 10% margin to TRFI per defect HW248225 p_o_atts->eff_dram_trfi = (p_o_atts->eff_dram_trfi * 9) / 10; + p_o_atts->eff_vpd_version = 0xFFFFFF; // set VPD version to a large number, searching for smallest + // the VPD version is 2 ASCI characters, so this is always later than that + // Assigning dependent values to attributes for (int l_cur_mba_port = 0; l_cur_mba_port < PORT_SIZE; l_cur_mba_port += 1) @@ -1639,25 +1653,6 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( p_o_atts->eff_dimm_ranks_configed[l_cur_mba_port] [l_cur_mba_dimm] = 0x00; } - for (int l_cur_mba_rank = 0; l_cur_mba_rank < - RANK_SIZE; l_cur_mba_rank += 1) - { - if (( p_o_atts->eff_dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM) - && ( l_cur_mba_rank < p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] )) - { - // Added for CDIMM RC_B which uses x4 parts - if ( p_o_atts->eff_dram_width == fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4 ) { - p_o_atts->eff_dimm_spare[l_cur_mba_port][l_cur_mba_dimm][l_cur_mba_rank] - = fapi::ENUM_ATTR_EFF_DIMM_SPARE_LOW_NIBBLE; - } else { - p_o_atts->eff_dimm_spare[l_cur_mba_port][l_cur_mba_dimm][l_cur_mba_rank] - = fapi::ENUM_ATTR_EFF_DIMM_SPARE_FULL_BYTE; - } - } else { - p_o_atts->eff_dimm_spare[l_cur_mba_port][l_cur_mba_dimm][l_cur_mba_rank] - = fapi::ENUM_ATTR_EFF_DIMM_SPARE_NO_SPARE; - } - } if ( p_i_data->sdram_device_type[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_SDRAM_DEVICE_TYPE_NON_STANDARD) { @@ -1702,13 +1697,6 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( [l_cur_mba_dimm] = 0; p_o_atts->eff_dimm_ranks_configed[l_cur_mba_port] [l_cur_mba_dimm] = 0x00; - for (int l_cur_mba_rank = 0; l_cur_mba_rank < - RANK_SIZE; l_cur_mba_rank += 1) - { - p_o_atts-> - eff_dimm_spare[l_cur_mba_port][l_cur_mba_dimm][l_cur_mba_rank] - = fapi::ENUM_ATTR_EFF_DIMM_SPARE_NO_SPARE; - } p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE; p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_UNDEFINED; } @@ -1785,6 +1773,13 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( // p_o_atts->eff_dram_density, p_o_atts-> // attr_eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm], // p_o_atts->eff_dram_width, i_target_mba.toEcmdString()); +//------------------------------------------------------------------------------ + if(p_o_atts->eff_vpd_version == 0xFFFFFF || + p_i_data->vpd_version[l_cur_mba_port][l_cur_mba_dimm] < p_o_atts->eff_vpd_version ) { // find the smallest VPD + p_o_atts->eff_vpd_version = p_i_data->vpd_version[l_cur_mba_port][l_cur_mba_dimm]; + } +//------------------------------------------------------------------------------ + } // inner for loop } // outer for loop return rc; @@ -1824,9 +1819,6 @@ fapi::ReturnCode mss_eff_config_write_eff_atts( rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_SIZE, &i_target_mba, p_i_atts->eff_dimm_size); if(rc) break; - rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_SPARE, &i_target_mba, - p_i_atts->eff_dimm_spare); - if(rc) break; rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_TYPE, &i_target_mba, p_i_atts->eff_dimm_type); if(rc) break; @@ -2033,6 +2025,13 @@ fapi::ReturnCode mss_eff_config_write_eff_atts( rc = FAPI_ATTR_SET(ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR, &i_target_mba, p_i_atts->dimm_functional_vector); if(rc) break; + // Make the final VPD version be a number and not ascii + p_i_atts->eff_vpd_version=((p_i_atts->eff_vpd_version & 0x0f00)>> 4)| + ((p_i_atts->eff_vpd_version & 0x000f)>> 0); + rc = FAPI_ATTR_SET(ATTR_MSS_EFF_VPD_VERSION, &i_target_mba, + p_i_atts->eff_vpd_version); + if(rc) break; + } while(0); return rc; diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C index 508ce4109..d78577c38 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_config_cke_map.C,v 1.4 2013/08/16 13:45:30 kcook Exp $ +// $Id: mss_eff_config_cke_map.C,v 1.5 2014/01/07 21:50:06 bellows Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_cke_map.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -42,6 +42,7 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.5 | bellows |02-JAN-14| VPD attribute removal // 1.4 | kcook |16-AUG-12| Added LRDIMM support. // 1.3 | asaetow |14-NOV-12| Added ATTR_EFF_SPCKE_MAP. // 1.2 | asaetow |13-NOV-12| Added FAPI_ERR for else "Undefined IBM_TYPE". @@ -65,81 +66,10 @@ extern "C" { - - //---------------------------------------------------------------------- // ENUMs and CONSTs //---------------------------------------------------------------------- -// Define attribute array size -const uint8_t PORT_SIZE = 2; -const uint8_t DIMM_SIZE = 2; -const uint8_t RANK_SIZE = 4; -const uint8_t IBM_TYPE_SIZE = 27; - -const uint8_t l_cke_map_u8array[IBM_TYPE_SIZE][DIMM_SIZE][RANK_SIZE] = { - // UNDEFINED = 0, TYPE_1A = 1, TYPE_1B = 2, TYPE_1C = 3, TYPE_1D = 4, TYPE_2A = 5, TYPE_2B = 6, TYPE_2C = 7, TYPE_3A = 8, TYPE_3B = 9, TYPE_3C = 10, TYPE_4A = 11, TYPE_4B = 12, TYPE_4C = 13, TYPE_5A = 14, TYPE_5B = 15, TYPE_5C = 16, TYPE_5D = 17, TYPE_6A = 18, TYPE_6B = 19, TYPE_6C = 20, TYPE_7A = 21, TYPE_7B = 22, TYPE_7C = 23, TYPE_8A = 24, TYPE_8B = 25, TYPE_8C = 26 - // DIMM0 , DIMM1 - // 0 1 2 3 , 0 1 2 3 - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // UNDEFINED - {{0x80, 0x00, 0x00, 0x00}, {0x08, 0x00, 0x00, 0x00}}, // TYPE_1A - {{0x80, 0x40, 0x00, 0x00}, {0x08, 0x04, 0x00, 0x00}}, // TYPE_1B - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_1C <-- UNDEFINED - {{0x80, 0x40, 0x80, 0x40}, {0x08, 0x04, 0x08, 0x04}}, // TYPE_1D - {{0x80, 0x00, 0x00, 0x00}, {0x08, 0x00, 0x00, 0x00}}, // TYPE_2A - {{0x80, 0x00, 0x00, 0x00}, {0x08, 0x00, 0x00, 0x00}}, // TYPE_2B - {{0x80, 0x00, 0x00, 0x00}, {0x08, 0x00, 0x00, 0x00}}, // TYPE_2C - {{0x80, 0x40, 0x00, 0x00}, {0x08, 0x04, 0x00, 0x00}}, // TYPE_3A - {{0x80, 0x40, 0x00, 0x00}, {0x08, 0x04, 0x00, 0x00}}, // TYPE_3B - {{0x80, 0x40, 0x00, 0x00}, {0x08, 0x04, 0x00, 0x00}}, // TYPE_3C - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_4A <-- UNDEFINED - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_4B <-- UNDEFINED - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_4C <-- UNDEFINED - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_5A <-- UNDEFINED - {{0x80, 0x40, 0x00, 0x00}, {0x08, 0x04, 0x00, 0x00}}, // TYPE_5B - {{0x80, 0x40, 0x80, 0x40}, {0x08, 0x04, 0x08, 0x04}}, // TYPE_5C - {{0x80, 0x40, 0x00, 0x00}, {0x08, 0x04, 0x00, 0x00}}, // TYPE_5D - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_6A <-- UNDEFINED - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_6B <-- UNDEFINED - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_6C <-- UNDEFINED - {{0x80, 0x40, 0x00, 0x00}, {0x08, 0x04, 0x00, 0x00}}, // TYPE_7A - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_7B <-- NOT YET SUPPORTED for LRDIMM DDR3 - {{0x80, 0x40, 0x00, 0x00}, {0x08, 0x04, 0x00, 0x00}}, // TYPE_7C - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_8A <-- UNDEFINED - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_8B <-- UNDEFINED - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}}; // TYPE_8C <-- UNDEFINED - -const uint8_t l_spcke_map_u8array[IBM_TYPE_SIZE][DIMM_SIZE][RANK_SIZE] = { - // DIMM0 , DIMM1 - // 0 1 2 3 , 0 1 2 3 - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // UNDEFINED - {{0x20, 0x00, 0x00, 0x00}, {0x02, 0x00, 0x00, 0x00}}, // TYPE_1A - {{0x20, 0x10, 0x00, 0x00}, {0x02, 0x01, 0x00, 0x00}}, // TYPE_1B - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_1C <-- UNDEFINED - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_1D <-- NOT SUPPORTED for CDIMM - {{0x20, 0x00, 0x00, 0x00}, {0x02, 0x00, 0x00, 0x00}}, // TYPE_2A - {{0x20, 0x00, 0x00, 0x00}, {0x02, 0x00, 0x00, 0x00}}, // TYPE_2B - {{0x20, 0x00, 0x00, 0x00}, {0x02, 0x00, 0x00, 0x00}}, // TYPE_2C - {{0x20, 0x10, 0x00, 0x00}, {0x02, 0x01, 0x00, 0x00}}, // TYPE_3A - {{0x20, 0x10, 0x00, 0x00}, {0x02, 0x01, 0x00, 0x00}}, // TYPE_3B - {{0x20, 0x10, 0x00, 0x00}, {0x02, 0x01, 0x00, 0x00}}, // TYPE_3C - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_4A <-- UNDEFINED - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_4B <-- UNDEFINED - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_4C <-- UNDEFINED - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_5A <-- UNDEFINED - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_5B <-- NOT SUPPORTED for CDIMM - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_5C <-- NOT SUPPORTED for CDIMM - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_5D <-- NOT SUPPORTED for CDIMM, NOT YET SUPPORTED for LRDIMM DDR3 - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_6A <-- UNDEFINED - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_6B <-- UNDEFINED - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_6C <-- UNDEFINED - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_7A <-- NOT SUPPORTED for CDIMM - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_7B <-- NOT SUPPORTED for CDIMM, NOT YET SUPPORTED for LRDIMM DDR3 - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_7C <-- NOT SUPPORTED for CDIMM - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_8A <-- UNDEFINED - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}, // TYPE_8B <-- UNDEFINED - {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}}; // TYPE_8C <-- UNDEFINED - //****************************************************************************** @@ -153,179 +83,7 @@ fapi::ReturnCode mss_eff_config_cke_map(const fapi::Target i_target_mba) { // Define attribute array size - - // Fetch dependent attributes - uint8_t l_num_ranks_per_dimm_u8array[PORT_SIZE][DIMM_SIZE]; - // ATTR_EFF_DRAM_GEN: EMPTY = 0, DDR3 = 1, DDR4 = 2, - uint8_t l_dram_gen_u8; - // ATTR_EFF_DIMM_TYPE: CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3, - uint8_t l_dimm_type_u8; - uint8_t l_num_drops_per_port_u8; - uint8_t l_ibm_type_u8array[PORT_SIZE][DIMM_SIZE]; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm_u8array); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target_mba, l_dram_gen_u8); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, l_dimm_type_u8); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, l_num_drops_per_port_u8); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_IBM_TYPE, &i_target_mba, l_ibm_type_u8array); if(rc) return rc; - - - // Define local attribute variables - uint8_t l_attr_eff_cke_map[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; - uint8_t l_attr_eff_spcke_map[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; - - - for (uint8_t l_cur_port = 0; l_cur_port < PORT_SIZE; l_cur_port += 1) { - for (uint8_t l_cur_dimm = 0; l_cur_dimm < DIMM_SIZE; l_cur_dimm += 1) { - uint8_t l_ibm_type_index = 0; - // UNDEFINED = 0, TYPE_1A = 1, TYPE_1B = 2, TYPE_1C = 3, TYPE_1D = 4, TYPE_2A = 5, TYPE_2B = 6, TYPE_2C = 7, TYPE_3A = 8, TYPE_3B = 9, TYPE_3C = 10, TYPE_4A = 11, TYPE_4B = 12, TYPE_4C = 13, TYPE_5A = 14, TYPE_5B = 15, TYPE_5C = 16, TYPE_5D = 17, TYPE_6A = 18, TYPE_6B = 19, TYPE_6C = 20, TYPE_7A = 21, TYPE_7B = 22, TYPE_7C = 23, TYPE_8A = 24, TYPE_8B = 25, TYPE_8C = 26 - if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_UNDEFINED ) { - l_ibm_type_index = 0; - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_1A ) { - l_ibm_type_index = 1; - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_1B ) { - l_ibm_type_index = 2; - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_1C ) { - l_ibm_type_index = 3; - FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_1D ) { - l_ibm_type_index = 4; - if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) { - FAPI_ERR("Invalid IBM_TYPE for CDIMM on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_2A ) { - l_ibm_type_index = 5; - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_2B ) { - l_ibm_type_index = 6; - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_2C ) { - l_ibm_type_index = 7; - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_3A ) { - l_ibm_type_index = 8; - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_3B ) { - l_ibm_type_index = 9; - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_3C ) { - l_ibm_type_index = 10; - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_4A ) { - l_ibm_type_index = 11; - FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_4B ) { - l_ibm_type_index = 12; - FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_4C ) { - l_ibm_type_index = 13; - FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_5A ) { - l_ibm_type_index = 14; - FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_5B ) { - l_ibm_type_index = 15; - if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) { - FAPI_ERR("Invalid IBM_TYPE for CDIMM on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_5C ) { - l_ibm_type_index = 16; - if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) { - FAPI_ERR("Invalid IBM_TYPE for CDIMM on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_5D ) { - l_ibm_type_index = 17; - if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) { - FAPI_ERR("Invalid IBM_TYPE for CDIMM on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - FAPI_INF("WIP 8Rank LRDIMM IBM_TYPE on %s!", i_target_mba.toEcmdString()); -// FAPI_ERR("Currently unsupported IBM_TYPE on %s!", i_target_mba.toEcmdString()); -// FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_6A ) { - l_ibm_type_index = 18; - FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_6B ) { - l_ibm_type_index = 19; - FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_6C ) { - l_ibm_type_index = 20; - FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_7A ) { - l_ibm_type_index = 21; - if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) { - FAPI_ERR("Invalid IBM_TYPE for CDIMM on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_7B ) { - l_ibm_type_index = 22; - if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) { - FAPI_ERR("Invalid IBM_TYPE for CDIMM on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - FAPI_ERR("Currently unsupported IBM_TYPE on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_7C ) { - l_ibm_type_index = 23; - if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) { - FAPI_ERR("Invalid IBM_TYPE for CDIMM on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_8A ) { - l_ibm_type_index = 24; - FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_8B ) { - l_ibm_type_index = 25; - FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_8C ) { - l_ibm_type_index = 26; - FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } else { - l_ibm_type_index = 0; - FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - - for (uint8_t l_cur_rank = 0; l_cur_rank < RANK_SIZE; l_cur_rank += 1) { - if ( l_num_drops_per_port_u8 == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE ) { - if ( l_cur_dimm == 0 ) { - l_attr_eff_cke_map[l_cur_port][l_cur_dimm][l_cur_rank] = l_cke_map_u8array[l_ibm_type_index][l_cur_dimm][l_cur_rank]; - if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) { - l_attr_eff_spcke_map[l_cur_port][l_cur_dimm][l_cur_rank] = l_spcke_map_u8array[l_ibm_type_index][l_cur_dimm][l_cur_rank]; - FAPI_INF("WARNING: NUM_DROPS_PER_PORT = SINGLE for a CDIMM on %s!", i_target_mba.toEcmdString()); - } else { - l_attr_eff_spcke_map[l_cur_port][l_cur_dimm][l_cur_rank] = 0; - } - } else { - l_attr_eff_cke_map[l_cur_port][l_cur_dimm][l_cur_rank] = 0; - l_attr_eff_spcke_map[l_cur_port][l_cur_dimm][l_cur_rank] = 0; - } - } else if ( l_num_drops_per_port_u8 == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL ) { - l_attr_eff_cke_map[l_cur_port][l_cur_dimm][l_cur_rank] = l_cke_map_u8array[l_ibm_type_index][l_cur_dimm][l_cur_rank]; - if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) { - l_attr_eff_spcke_map[l_cur_port][l_cur_dimm][l_cur_rank] = l_spcke_map_u8array[l_ibm_type_index][l_cur_dimm][l_cur_rank]; - } else { - l_attr_eff_spcke_map[l_cur_port][l_cur_dimm][l_cur_rank] = 0; - } - } else { - l_attr_eff_cke_map[l_cur_port][l_cur_dimm][l_cur_rank] = 0; - l_attr_eff_spcke_map[l_cur_port][l_cur_dimm][l_cur_rank] = 0; - } - } - } - } - - // Set attributes - rc = FAPI_ATTR_SET(ATTR_EFF_CKE_MAP, &i_target_mba, l_attr_eff_cke_map); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_SPCKE_MAP, &i_target_mba, l_attr_eff_spcke_map); if(rc) return rc; FAPI_INF("%s on %s COMPLETE", PROCEDURE_NAME, i_target_mba.toEcmdString()); return rc; diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C index 62b76a038..3cde74679 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_config_termination.C,v 1.32 2013/08/27 22:25:29 kcook Exp $ +// $Id: mss_eff_config_termination.C,v 1.41 2014/01/14 19:06:27 dcadiga Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_termination.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -42,6 +42,15 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.41 | dcadiga |13-JAN-14| Removed checking of dimm type attribute for CDIMM, replaced with custom dimm type attribute +// 1.40 | bellows |02-JAN-14| VPD attribute removal +// 1.39 | bellows |25-NOV-13| removed dimm spare temp, added using namespace fapi +// 1.38 | dcadiga |22-NOV-13| DDR4 ATTR_VREF_DQ_TRAIN_VALUE change for Menlo (0 to 16) +// 1.37 | dcadiga |22-NOV-13| New Settings for RC/A and RC/C from Nov5/2013 Spreadsheet, DDR4 Enum Update +// 1.36 | bellows |19-SEP-13| Patched the AM keyword workaround.for >1 ranks +// 1.35 | bellows |16-SEP-13| Hostboot compile update. +// 1.34 | kcook |13-SEP-13| Updated define FAPI_LRDIMM token. +// 1.33 | bellows |12-SEP-13| set_vpd_dimm_spare function added before AM keyword shows up // 1.32 | kcook |27-AUG-13| Removed LRDIMM support to mss_lrdimm_funcs.C. // 1.31 | kcook |16-AUG-13| Added LRDIMM support. // 1.30 | dcadiga |07-AUG-13| Fixed hostboot compile issue @@ -93,13 +102,13 @@ #include <fapi.H> #include <mss_lrdimm_funcs.H> +using namespace fapi; - -#ifndef LRDIMM +#ifndef FAPI_LRDIMM using namespace fapi; -ReturnCode mss_lrdimm_rewrite_odt( const Target& i_target_mba, +fapi::ReturnCode mss_lrdimm_rewrite_odt( const Target& i_target_mba, uint32_t *p_b_var_array, uint32_t *var_array_p_array[5]) { @@ -130,573 +139,200 @@ const uint8_t PORT_SIZE = 2; const uint8_t DIMM_SIZE = 2; const uint8_t RANK_SIZE = 4; +// Define the size of the array that holds the values to set +const uint8_t STORE_ARRAY_SIZE = 10; + //Declare all Static Arrays uint32_t attr_eff_dimm_rcd_ibt[PORT_SIZE][DIMM_SIZE]; uint8_t attr_eff_dimm_rcd_mirror_mode[PORT_SIZE][DIMM_SIZE]; -uint8_t attr_eff_dram_ron[PORT_SIZE][DIMM_SIZE]; -uint8_t attr_eff_dram_rtt_nom[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; -uint8_t attr_eff_dram_rtt_wr[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; -uint8_t attr_eff_odt_rd[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; -uint8_t attr_eff_odt_wr[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; uint32_t attr_eff_cen_rd_vref[PORT_SIZE]; uint32_t attr_eff_dram_wr_vref[PORT_SIZE]; uint8_t attr_eff_dram_wrddr4_vref[PORT_SIZE]; uint8_t attr_eff_cen_rcv_imp_dq_dqs[PORT_SIZE]; uint8_t attr_eff_cen_drv_imp_dq_dqs[PORT_SIZE]; -uint8_t attr_eff_cen_drv_imp_cntl[PORT_SIZE]; -uint8_t attr_eff_cen_drv_imp_addr[PORT_SIZE]; -uint8_t attr_eff_cen_drv_imp_clk[PORT_SIZE]; -uint8_t attr_eff_cen_drv_imp_spcke[PORT_SIZE]; uint8_t attr_eff_cen_slew_rate_dq_dqs[PORT_SIZE]; -uint8_t attr_eff_cen_slew_rate_cntl[PORT_SIZE]; -uint8_t attr_eff_cen_slew_rate_addr[PORT_SIZE]; -uint8_t attr_eff_cen_slew_rate_clk[PORT_SIZE]; -uint8_t attr_eff_cen_slew_rate_spcke[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m0_clk_p0[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m0_clk_p1[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m1_clk_p0[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m1_clk_p1[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_cmd_a0[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_cmd_a1[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_cmd_a2[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_cmd_a3[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_cmd_a4[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_cmd_a5[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_cmd_a6[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_cmd_a7[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_cmd_a8[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_cmd_a9[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_cmd_a10[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_cmd_a11[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_cmd_a12[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_cmd_a13[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_cmd_a14[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_cmd_a15[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_cmd_bA0[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_cmd_bA1[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_cmd_bA2[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_cmd_casn[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_cmd_rasn[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_cmd_wen[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_par[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m_actn[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m0_cntl_cke0[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m0_cntl_cke1[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m0_cntl_cke2[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m0_cntl_cke3[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m0_cntl_csn0[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m0_cntl_csn1[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m0_cntl_csn2[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m0_cntl_csn3[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m0_cntl_odt0[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m0_cntl_odt1[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m1_cntl_cke0[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m1_cntl_cke1[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m1_cntl_cke2[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m1_cntl_cke3[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m1_cntl_csn0[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m1_cntl_csn1[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m1_cntl_csn2[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m1_cntl_csn3[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m1_cntl_odt0[PORT_SIZE]; -uint8_t attr_eff_cen_phase_rot_m1_cntl_odt1[PORT_SIZE]; -uint8_t attr_eff_dram_2n_mode_enabled; +uint8_t l_attr_vpd_2n_mode_enabled; uint8_t attr_eff_dram_al; uint8_t attr_eff_rlo[PORT_SIZE]; uint8_t attr_eff_wlo[PORT_SIZE]; uint8_t attr_eff_gpo[PORT_SIZE]; -/* -const uint8_t valid_attrs[210] = { -attr_eff_dimm_rcd_ibt[0][0], -attr_eff_dimm_rcd_ibt[0][1], -attr_eff_dimm_rcd_ibt[1][0], -attr_eff_dimm_rcd_ibt[1][1], -attr_eff_dimm_rcd_mirror_mode[0][0], -attr_eff_dimm_rcd_mirror_mode[0][1], -attr_eff_dimm_rcd_mirror_mode[1][0], -attr_eff_dimm_rcd_mirror_mode[1][1], -attr_eff_dram_ron[0][0], -attr_eff_dram_ron[0][1], -attr_eff_dram_ron[1][0], -attr_eff_dram_ron[1][1], -attr_eff_dram_rtt_nom[0][0][0], -attr_eff_dram_rtt_nom[0][0][1], -attr_eff_dram_rtt_nom[0][0][2], -attr_eff_dram_rtt_nom[0][0][3], -attr_eff_dram_rtt_nom[0][1][0], -attr_eff_dram_rtt_nom[0][1][1], -attr_eff_dram_rtt_nom[0][1][2], -attr_eff_dram_rtt_nom[0][1][3], -attr_eff_dram_rtt_nom[1][0][0], -attr_eff_dram_rtt_nom[1][0][1], -attr_eff_dram_rtt_nom[1][0][2], -attr_eff_dram_rtt_nom[1][0][3], -attr_eff_dram_rtt_nom[1][1][0], -attr_eff_dram_rtt_nom[1][1][1], -attr_eff_dram_rtt_nom[1][1][2], -attr_eff_dram_rtt_nom[1][1][3], -attr_eff_dram_rtt_wr[0][0][0], -attr_eff_dram_rtt_wr[0][0][1], -attr_eff_dram_rtt_wr[0][0][2], -attr_eff_dram_rtt_wr[0][0][3], -attr_eff_dram_rtt_wr[0][1][0], -attr_eff_dram_rtt_wr[0][1][1], -attr_eff_dram_rtt_wr[0][1][2], -attr_eff_dram_rtt_wr[0][1][3], -attr_eff_dram_rtt_wr[1][0][0], -attr_eff_dram_rtt_wr[1][0][1], -attr_eff_dram_rtt_wr[1][0][2], -attr_eff_dram_rtt_wr[1][0][3], -attr_eff_dram_rtt_wr[1][1][0], -attr_eff_dram_rtt_wr[1][1][1], -attr_eff_dram_rtt_wr[1][1][2], -attr_eff_dram_rtt_wr[1][1][3], -attr_eff_odt_rd[0][0][0], -attr_eff_odt_rd[0][0][1], -attr_eff_odt_rd[0][0][2], -attr_eff_odt_rd[0][0][3], -attr_eff_odt_rd[0][1][0], -attr_eff_odt_rd[0][1][1], -attr_eff_odt_rd[0][1][2], -attr_eff_odt_rd[0][1][3], -attr_eff_odt_rd[1][0][0], -attr_eff_odt_rd[1][0][1], -attr_eff_odt_rd[1][0][2], -attr_eff_odt_rd[1][0][3], -attr_eff_odt_rd[1][1][0], -attr_eff_odt_rd[1][1][1], -attr_eff_odt_rd[1][1][2], -attr_eff_odt_rd[1][1][3], -attr_eff_odt_wr[0][0][0], -attr_eff_odt_wr[0][0][1], -attr_eff_odt_wr[0][0][2], -attr_eff_odt_wr[0][0][3], -attr_eff_odt_wr[0][1][0], -attr_eff_odt_wr[0][1][1], -attr_eff_odt_wr[0][1][2], -attr_eff_odt_wr[0][1][3], -attr_eff_odt_wr[1][0][0], -attr_eff_odt_wr[1][0][1], -attr_eff_odt_wr[1][0][2], -attr_eff_odt_wr[1][0][3], -attr_eff_odt_wr[1][1][0], -attr_eff_odt_wr[1][1][1], -attr_eff_odt_wr[1][1][2], -attr_eff_odt_wr[1][1][3], -attr_eff_cen_rd_vref[0], -attr_eff_cen_rd_vref[1], -attr_eff_dram_wr_vref[0], -attr_eff_dram_wr_vref[1], -//attr_eff_dram_wrddr4_vref[0], -//attr_eff_dram_wrddr4_vref[1], -attr_eff_cen_rcv_imp_dq_dqs[0], -attr_eff_cen_rcv_imp_dq_dqs[1], -attr_eff_cen_drv_imp_dq_dqs[0], -attr_eff_cen_drv_imp_dq_dqs[1], -attr_eff_cen_drv_imp_cntl[0], -attr_eff_cen_drv_imp_cntl[1], -attr_eff_cen_drv_imp_addr[0], -attr_eff_cen_drv_imp_addr[1], -attr_eff_cen_drv_imp_clk[0], -attr_eff_cen_drv_imp_clk[1], -attr_eff_cen_drv_imp_spcke[0], -attr_eff_cen_drv_imp_spcke[1], -attr_eff_cen_slew_rate_dq_dqs[0], -attr_eff_cen_slew_rate_dq_dqs[1], -attr_eff_cen_slew_rate_cntl[0], -attr_eff_cen_slew_rate_cntl[1], -attr_eff_cen_slew_rate_addr[0], -attr_eff_cen_slew_rate_addr[1], -attr_eff_cen_slew_rate_clk[0], -attr_eff_cen_slew_rate_clk[1], -attr_eff_cen_slew_rate_spcke[0], -attr_eff_cen_slew_rate_spcke[1], -attr_eff_cen_phase_rot_m0_clk_p0[0], -attr_eff_cen_phase_rot_m0_clk_p1[0], -attr_eff_cen_phase_rot_m1_clk_p0[0], -attr_eff_cen_phase_rot_m1_clk_p1[0], -attr_eff_cen_phase_rot_m_cmd_a0[0], -attr_eff_cen_phase_rot_m_cmd_a1[0], -attr_eff_cen_phase_rot_m_cmd_a2[0], -attr_eff_cen_phase_rot_m_cmd_a3[0], -attr_eff_cen_phase_rot_m_cmd_a4[0], -attr_eff_cen_phase_rot_m_cmd_a5[0], -attr_eff_cen_phase_rot_m_cmd_a6[0], -attr_eff_cen_phase_rot_m_cmd_a7[0], -attr_eff_cen_phase_rot_m_cmd_a8[0], -attr_eff_cen_phase_rot_m_cmd_a9[0], -attr_eff_cen_phase_rot_m_cmd_a10[0], -attr_eff_cen_phase_rot_m_cmd_a11[0], -attr_eff_cen_phase_rot_m_cmd_a12[0], -attr_eff_cen_phase_rot_m_cmd_a13[0], -attr_eff_cen_phase_rot_m_cmd_a14[0], -attr_eff_cen_phase_rot_m_cmd_a15[0], -attr_eff_cen_phase_rot_m_cmd_bA0[0], -attr_eff_cen_phase_rot_m_cmd_bA1[0], -attr_eff_cen_phase_rot_m_cmd_bA2[0], -attr_eff_cen_phase_rot_m_cmd_casn[0], -attr_eff_cen_phase_rot_m_cmd_rasn[0], -attr_eff_cen_phase_rot_m_cmd_wen[0], -attr_eff_cen_phase_rot_m_par[0], -attr_eff_cen_phase_rot_m_actn[0], -attr_eff_cen_phase_rot_m0_cntl_cke0[0], -attr_eff_cen_phase_rot_m0_cntl_cke1[0], -attr_eff_cen_phase_rot_m0_cntl_cke2[0], -attr_eff_cen_phase_rot_m0_cntl_cke3[0], -attr_eff_cen_phase_rot_m0_cntl_csn0[0], -attr_eff_cen_phase_rot_m0_cntl_csn1[0], -attr_eff_cen_phase_rot_m0_cntl_csn2[0], -attr_eff_cen_phase_rot_m0_cntl_csn3[0], -attr_eff_cen_phase_rot_m0_cntl_odt0[0], -attr_eff_cen_phase_rot_m0_cntl_odt1[0], -attr_eff_cen_phase_rot_m1_cntl_cke0[0], -attr_eff_cen_phase_rot_m1_cntl_cke1[0], -attr_eff_cen_phase_rot_m1_cntl_cke2[0], -attr_eff_cen_phase_rot_m1_cntl_cke3[0], -attr_eff_cen_phase_rot_m1_cntl_csn0[0], -attr_eff_cen_phase_rot_m1_cntl_csn1[0], -attr_eff_cen_phase_rot_m1_cntl_csn2[0], -attr_eff_cen_phase_rot_m1_cntl_csn3[0], -attr_eff_cen_phase_rot_m1_cntl_odt0[0], -attr_eff_cen_phase_rot_m1_cntl_odt1[0], -attr_eff_cen_phase_rot_m0_clk_p0[1], -attr_eff_cen_phase_rot_m0_clk_p1[1], -attr_eff_cen_phase_rot_m1_clk_p0[1], -attr_eff_cen_phase_rot_m1_clk_p1[1], -attr_eff_cen_phase_rot_m_cmd_a0[1], -attr_eff_cen_phase_rot_m_cmd_a1[1], -attr_eff_cen_phase_rot_m_cmd_a2[1], -attr_eff_cen_phase_rot_m_cmd_a3[1], -attr_eff_cen_phase_rot_m_cmd_a4[1], -attr_eff_cen_phase_rot_m_cmd_a5[1], -attr_eff_cen_phase_rot_m_cmd_a6[1], -attr_eff_cen_phase_rot_m_cmd_a7[1], -attr_eff_cen_phase_rot_m_cmd_a8[1], -attr_eff_cen_phase_rot_m_cmd_a9[1], -attr_eff_cen_phase_rot_m_cmd_a10[1], -attr_eff_cen_phase_rot_m_cmd_a11[1], -attr_eff_cen_phase_rot_m_cmd_a12[1], -attr_eff_cen_phase_rot_m_cmd_a13[1], -attr_eff_cen_phase_rot_m_cmd_a14[1], -attr_eff_cen_phase_rot_m_cmd_a15[1], -attr_eff_cen_phase_rot_m_cmd_bA0[1], -attr_eff_cen_phase_rot_m_cmd_bA1[1], -attr_eff_cen_phase_rot_m_cmd_bA2[1], -attr_eff_cen_phase_rot_m_cmd_casn[1], -attr_eff_cen_phase_rot_m_cmd_rasn[1], -attr_eff_cen_phase_rot_m_cmd_wen[1], -attr_eff_cen_phase_rot_m_par[1], -attr_eff_cen_phase_rot_m_actn[1], -attr_eff_cen_phase_rot_m0_cntl_cke0[1], -attr_eff_cen_phase_rot_m0_cntl_cke1[1], -attr_eff_cen_phase_rot_m0_cntl_cke2[1], -attr_eff_cen_phase_rot_m0_cntl_cke3[1], -attr_eff_cen_phase_rot_m0_cntl_csn0[1], -attr_eff_cen_phase_rot_m0_cntl_csn1[1], -attr_eff_cen_phase_rot_m0_cntl_csn2[1], -attr_eff_cen_phase_rot_m0_cntl_csn3[1], -attr_eff_cen_phase_rot_m0_cntl_odt0[1], -attr_eff_cen_phase_rot_m0_cntl_odt1[1], -attr_eff_cen_phase_rot_m1_cntl_cke0[1], -attr_eff_cen_phase_rot_m1_cntl_cke1[1], -attr_eff_cen_phase_rot_m1_cntl_cke2[1], -attr_eff_cen_phase_rot_m1_cntl_cke3[1], -attr_eff_cen_phase_rot_m1_cntl_csn0[1], -attr_eff_cen_phase_rot_m1_cntl_csn1[1], -attr_eff_cen_phase_rot_m1_cntl_csn2[1], -attr_eff_cen_phase_rot_m1_cntl_csn3[1], -attr_eff_cen_phase_rot_m1_cntl_odt0[1], -attr_eff_cen_phase_rot_m1_cntl_odt1[1] -}; -*/ //Declare the different dimms here: //Cdimm rc_A -uint32_t cdimm_rca_1r_1333_mba0[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,89,0,91,0,13,13,13,8,5,6,8,7,9,13,17,14,14,14,13,17,12,11,17,18,17,18,0,0,19,0,21,0,0,0,0,0,2,0,19,0,0,0,7,0,0,0,3,0,86,0,92,0,17,15,18,8,6,5,7,6,12,12,18,12,16,15,13,16,10,9,17,18,21,19,0,0,19,0,24,0,2,0,0,0,2,0,20,0,0,0,3,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE -}; - -uint32_t cdimm_rca_1r_1333_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,87,0,92,0,18,18,18,11,11,11,13,13,15,18,16,18,17,20,18,15,9,11,14,15,18,14,0,0,26,0,32,0,11,0,0,0,3,0,29,0,0,0,2,0,0,0,10,0,86,0,91,0,12,13,15,6,7,9,9,8,9,15,11,15,12,14,15,12,6,7,12,12,11,11,0,0,17,0,31,0,1,0,0,0,0,0,17,0,0,0,6,0,0,0,1,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE -}; - -uint32_t cdimm_rca_1r_1600_mba0[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,93,0,96,0,15,16,15,10,7,7,10,9,11,15,20,16,17,16,16,20,14,13,21,22,21,21,0,0,24,0,27,0,0,0,0,0,2,0,24,0,0,0,9,0,0,0,4,0,90,0,98,0,20,18,21,10,7,7,9,7,15,14,22,15,20,18,16,20,12,11,21,22,25,23,0,0,24,0,30,0,3,0,0,0,2,0,25,0,0,0,4,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE -}; - -uint32_t cdimm_rca_1r_1600_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,91,0,97,0,22,22,21,14,13,14,16,15,19,21,19,22,21,24,22,18,11,13,17,18,22,17,0,0,32,0,39,0,13,0,0,0,3,0,35,0,0,0,3,0,0,0,12,0,90,0,96,0,15,16,18,8,9,10,11,10,11,18,13,18,15,17,18,15,8,8,14,15,13,13,0,0,22,0,38,0,1,0,0,0,0,0,22,0,0,0,7,0,0,0,1,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE -}; - -uint32_t cdimm_rca_2r_1333_mba0[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,95,0,103,0,6,7,7,3,0,0,3,2,4,6,11,8,8,7,7,11,6,6,11,12,11,12,0,0,31,0,24,0,12,0,0,0,14,0,31,0,34,0,19,0,0,0,15,0,90,0,99,0,11,9,12,2,0,0,1,0,7,5,12,6,10,9,7,10,4,4,11,12,15,13,0,0,32,0,27,0,14,0,0,0,14,0,33,0,33,0,15,0,0,0,12,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t cdimm_default[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF }; -uint32_t cdimm_rca_2r_1333_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,90,0,98,0,11,11,10,5,4,5,6,6,9,10,8,11,10,13,11,8,3,4,7,7,11,7,0,0,38,0,34,0,21,0,0,0,14,0,41,0,34,0,13,0,0,0,21,0,91,0,99,0,7,8,10,2,2,4,4,3,5,10,5,10,7,9,10,7,1,2,6,7,5,5,0,0,31,0,36,0,14,0,0,0,13,0,31,0,32,0,19,0,0,0,13,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t cdimm_rca_1r_1333_mba1[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF }; -uint32_t cdimm_rca_2r_1600_mba0[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,100,0,109,0,9,9,9,3,0,0,3,2,4,8,14,10,10,10,9,14,7,6,14,15,14,15,0,0,37,0,29,0,14,0,0,0,16,0,37,0,40,0,23,0,0,0,17,0,95,0,105,0,13,11,14,3,0,0,2,0,8,7,15,8,13,11,9,13,5,4,14,15,18,16,0,0,38,0,32,0,16,0,0,0,16,0,39,0,40,0,18,0,0,0,14,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE -}; - -uint32_t cdimm_rca_2r_1600_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,95,0,104,0,14,14,13,6,5,6,8,8,11,13,11,14,12,16,14,10,3,5,9,9,13,9,0,0,44,0,40,0,25,0,0,0,16,0,47,0,41,0,15,0,0,0,24,0,96,0,104,0,9,10,12,2,3,4,5,4,5,12,7,12,8,11,12,9,1,2,8,9,7,7,0,0,37,0,42,0,15,0,0,0,15,0,36,0,38,0,21,0,0,0,15,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t cdimm_rca_1r_1600_mba0[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF }; //Cdimm rc_A DD1.0 -uint32_t cdimm_rca_1r_1333_mba0_DD10[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,57,0,59,0,64,0,0,0,0,0,0,0,0,0,0,0,64,64,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,54,0,60,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,64,0,64,0,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE -}; - -uint32_t cdimm_rca_1r_1333_mba1_DD10[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,55,0,60,0,0,64,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,54,0,59,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,64,0,0,0,0,0,0,0,64,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE -}; - -uint32_t cdimm_rca_1r_1600_mba0_DD10[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,61,0,64,0,64,0,0,0,0,0,0,0,0,0,0,0,64,64,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,58,0,66,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,64,0,64,0,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE -}; - -uint32_t cdimm_rca_1r_1600_mba1_DD10[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,59,0,65,0,0,64,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,7,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,0,64,58,0,64,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,6,0,64,0,0,0,64,0,0,0,0,0,0,0,64,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE -}; - -uint32_t cdimm_rca_2r_1333_mba0_DD10[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,71,0,64,0,0,0,0,0,0,0,0,0,0,0,64,64,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,58,0,67,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,64,0,64,0,1,0,1,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE -}; -uint32_t cdimm_rca_2r_1333_mba1_DD10[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,58,0,66,0,0,64,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,6,0,2,0,0,0,0,0,0,0,9,0,2,0,0,0,0,0,0,64,59,0,67,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4,0,64,0,0,0,64,0,0,0,0,0,0,0,64,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE -}; - -uint32_t cdimm_rca_2r_1600_mba0_DD10[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,68,0,77,0,64,0,0,0,0,0,0,0,0,0,0,0,64,64,0,0,64,0,0,0,0,0,0,0,5,0,0,0,0,0,0,0,0,0,5,0,8,0,0,0,0,0,0,0,63,0,73,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,64,0,64,0,7,0,8,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE -}; - -uint32_t cdimm_rca_2r_1600_mba1_DD10[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,72,0,0,64,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,12,0,8,0,0,0,0,0,0,0,15,0,9,0,0,0,0,0,0,64,64,0,72,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,5,0,10,0,64,0,0,0,64,0,4,0,6,0,0,0,64,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE -}; //RCB -uint32_t cdimm_rcb_2r_1333_mba0[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,102,100,100,101,1,2,2,3,0,0,4,2,4,1,7,3,3,2,2,7,8,7,7,8,7,8,0,0,22,0,29,0,19,0,0,0,21,0,22,0,31,0,29,0,0,0,23,0,96,110,98,109,6,4,7,4,1,1,3,1,9,0,7,1,5,4,2,6,6,5,6,8,11,9,0,0,22,0,26,0,23,0,0,0,22,0,24,0,26,0,25,0,0,0,20,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE - -}; - -uint32_t cdimm_rcb_2r_1333_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,98,99,98,100,9,9,9,4,3,4,6,6,10,9,5,9,8,12,10,5,0,3,3,4,9,3,0,0,16,0,44,0,20,0,0,0,1,0,18,0,45,0,1,0,0,0,18,0,100,99,100,99,5,6,9,1,2,3,4,3,4,9,3,9,5,8,9,5,0,1,4,5,3,3,0,0,6,0,40,0,4,0,0,0,4,0,6,0,39,0,14,0,0,0,4,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE - -}; - -uint32_t cdimm_rcb_2r_1600_mba0[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,108,106,106,108,2,2,2,3,0,0,4,2,5,1,7,3,4,3,2,7,8,7,8,9,8,8,0,0,29,0,37,0,24,0,0,0,27,0,29,0,39,0,36,0,0,0,29,0,99,119,101,119,7,5,8,4,1,1,3,1,10,0,8,1,6,5,2,6,7,6,7,9,13,10,0,0,28,0,29,0,27,0,0,0,27,0,29,0,30,0,29,0,0,0,23,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE - -}; - -uint32_t cdimm_rcb_2r_1600_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,105,112,105,112,10,10,9,4,3,4,6,6,10,9,6,10,8,13,10,5,0,3,3,4,9,3,0,0,22,0,53,0,26,0,0,0,10,0,25,0,54,0,10,0,0,0,25,0,108,106,109,106,6,7,10,1,2,4,5,4,5,11,4,10,5,9,10,6,0,1,4,6,3,3,0,0,8,0,49,0,7,0,0,0,6,0,8,0,48,0,18,0,0,0,7,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE - -}; - //RCB4 - -uint32_t cdimm_rcb4_2r_1600_mba0[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD68625,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD68625,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,93,91,90,92,4,5,5,4,0,0,4,2,5,4,10,3,6,3,5,10,9,8,11,12,11,11,11,12,10,0,27,0,2,0,0,0,6,0,10,0,29,0,16,0,0,0,8,0,91,98,93,98,11,8,12,4,1,0,3,0,10,4,12,5,10,8,6,10,7,6,11,13,16,13,7,5,10,0,30,0,8,0,0,0,7,0,12,0,31,0,10,0,0,0,4,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE -}; -//{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,108,106,106,108,2,2,2,3,0,0,4,2,5,1,7,3,4,3,2,7,8,7,8,9,8,8,0,9,29,0,37,0,24,0,0,0,27,0,29,0,39,0,36,0,0,0,29,0,99,119,101,119,7,5,8,4,1,1,3,1,10,0,8,1,6,5,2,6,7,6,7,9,13,10,0,3,28,0,29,0,27,0,0,0,27,0,29,0,30,0,29,0,0,0,23,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE - -//}; - -uint32_t cdimm_rcb4_2r_1600_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD68625,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD68625,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,108,117,108,117,18,18,17,22,21,22,24,24,28,17,15,18,17,20,18,15,19,21,14,14,18,14,15,14,10,0,55,0,15,0,0,0,0,0,13,0,56,0,0,0,0,0,13,0,117,114,117,113,21,22,26,22,23,24,25,24,25,27,18,26,20,24,26,20,21,22,19,20,17,18,24,29,0,0,53,0,1,0,0,0,0,0,0,0,52,0,11,0,0,0,1,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE -}; -//{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,105,112,105,112,10,10,9,4,3,4,6,6,10,9,6,10,8,13,10,5,0,3,3,4,9,3,0,4,22,0,53,0,26,0,0,0,10,0,25,0,54,0,10,0,0,0,25,0,108,106,109,106,6,7,10,1,2,4,5,4,5,11,4,10,5,9,10,6,0,1,4,6,3,3,0,3,8,0,49,0,7,0,0,0,6,0,8,0,48,0,18,0,0,0,7,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE - -//}; - - //RCC -uint32_t cdimm_rcc_2r_1333_mba0[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,94,0,95,0,19,19,19,19,17,16,18,14,19,19,22,20,20,19,19,23,20,18,22,25,24,24,0,0,0,0,64,0,5,0,0,0,8,0,0,0,66,0,16,0,0,0,10,0,91,0,95,0,22,20,23,18,16,15,17,13,22,17,22,17,21,21,18,22,18,16,21,24,27,25,0,0,0,0,63,0,7,0,0,0,6,0,1,0,64,0,9,0,0,0,3,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE - -}; - -uint32_t cdimm_rcc_2r_1333_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,84,0,86,0,12,12,11,13,13,12,13,10,18,11,9,12,11,14,12,9,8,8,7,9,12,8,0,0,1,0,62,0,12,0,0,0,0,0,4,0,62,0,0,0,0,0,11,0,94,0,96,0,20,21,23,20,21,22,22,18,19,24,17,23,18,20,23,20,16,15,18,20,18,18,0,0,0,0,67,0,2,0,0,0,2,0,0,0,66,0,11,0,0,0,2,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE - -}; - -uint32_t cdimm_rcc_2r_1600_mba0[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,101,0,100,0,21,22,22,22,20,18,21,13,22,21,25,23,23,22,22,26,22,20,25,28,27,27,0,0,0,0,79,0,4,0,0,0,8,0,0,0,82,0,19,0,0,0,10,0,98,0,102,0,27,25,28,23,21,18,20,13,28,21,26,22,26,25,23,26,21,19,26,29,31,29,0,0,0,0,81,0,11,0,0,0,11,0,1,0,82,0,14,0,0,0,7,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE - -}; - -uint32_t cdimm_rcc_2r_1600_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,90,0,91,0,15,15,15,16,16,15,17,11,21,15,12,15,14,18,15,12,8,10,10,12,15,11,0,0,3,0,79,0,17,0,0,0,1,0,6,0,80,0,0,0,0,0,16,0,101,0,102,0,23,24,27,23,25,25,25,18,22,28,21,28,22,24,27,23,18,18,21,23,21,21,0,0,0,0,84,0,4,0,0,0,3,0,0,0,83,0,14,0,0,0,4,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE - -}; - - - - - //RDIMM A/B Ports MBA0 Glacier -uint32_t rdimm_glacier_1600_r10_mba0[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,70,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,7,9,11,10,4,0,3,5,0,0,4,10,3,12,3,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_glacier_1600_r10_mba0[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r20e_mba0[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,67,0,0,0,1,2,2,4,0,1,3,2,5,2,6,3,3,3,2,7,7,7,6,8,6,7,7,0,2,10,0,0,0,10,2,10,2,9,0,0,0,0,0,0,0,0,0,0,71,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,1,3,0,0,3,7,2,9,1,10,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_glacier_1333_r20e_mba0[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r20e_mba0[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,66,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,75,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,8,9,11,11,4,0,3,5,0,0,4,10,3,12,3,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_glacier_1600_r20e_mba0[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r20b_mba0[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,2,2,4,0,1,3,2,5,2,6,3,3,3,2,6,7,7,6,8,6,7,7,0,2,10,0,0,0,10,2,10,2,9,0,0,0,0,0,0,0,0,0,0,68,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,2,4,0,0,4,8,3,10,2,10,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_glacier_1333_r20b_mba0[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r20b_mba0[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,70,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,8,9,11,11,4,0,3,5,0,0,5,10,3,12,3,13,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_glacier_1600_r20b_mba0[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r40_mba0[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,4,1,1,4,3,5,2,7,3,4,3,3,7,7,7,7,8,7,8,7,0,3,11,0,0,1,11,3,11,3,10,0,0,0,0,0,0,0,0,0,0,71,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,2,4,0,0,4,8,3,10,3,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_glacier_1333_r40_mba0[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; //RDIMM C/D Ports MBA1 Glacier -uint32_t rdimm_glacier_1333_r10_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,12,11,12,11,8,12,13,13,16,12,9,12,11,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,10,10,13,10,11,13,13,12,13,13,9,13,10,12,13,10,10,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_glacier_1333_r10_mba1[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r10_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,15,13,15,14,10,15,16,17,21,15,11,15,13,18,15,9,11,13,8,10,14,7,11,0,10,2,0,0,13,2,12,5,4,2,0,0,0,0,0,0,0,0,0,0,71,0,0,0,12,13,16,13,13,16,16,15,16,17,11,16,12,15,17,12,12,13,11,12,9,10,15,0,4,14,0,0,4,15,4,13,4,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_glacier_1600_r10_mba1[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r20e_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,0,0,12,11,12,11,8,12,13,13,16,12,9,12,11,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,73,0,0,0,10,10,13,11,11,13,13,12,13,13,9,13,10,12,13,10,10,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_glacier_1333_r20e_mba1[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r20e_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,77,0,0,0,15,13,15,14,10,15,16,17,21,15,11,15,13,18,15,9,11,13,8,10,14,7,11,0,9,1,0,0,13,2,12,5,4,1,0,0,0,0,0,0,0,0,0,0,77,0,0,0,12,13,16,13,13,16,16,15,16,17,11,16,13,15,17,12,12,13,11,12,9,10,15,0,4,14,0,0,4,15,4,13,3,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_glacier_1600_r20e_mba1[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r20b_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,12,10,12,11,8,11,13,13,16,12,9,12,10,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,10,10,13,10,10,13,13,12,13,13,8,13,10,12,13,10,9,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_glacier_1333_r20b_mba1[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r20b_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,14,13,15,14,10,14,16,17,21,15,11,15,13,17,15,9,11,13,8,10,14,7,11,0,10,1,0,0,13,2,12,5,4,1,0,0,0,0,0,0,0,0,0,0,71,0,0,0,12,13,16,13,13,16,16,15,16,16,10,16,12,15,17,12,12,12,11,12,9,9,15,0,4,14,0,0,4,15,4,13,4,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_glacier_1600_r20b_mba1[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1066_r40_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,10,9,10,9,7,10,11,11,14,10,7,10,9,12,10,6,7,8,5,7,9,5,7,0,7,1,0,0,9,1,8,3,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,8,8,11,8,9,10,11,10,11,11,7,11,8,10,11,8,8,8,7,8,6,6,10,0,3,10,0,0,3,10,3,9,2,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_glacier_1066_r40_mba1[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r11_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,69,0,18,17,18,17,14,18,19,19,22,18,15,18,17,20,18,13,15,16,13,14,17,12,15,0,11,5,0,0,14,5,13,7,7,5,11,2,0,0,3,3,5,3,8,2,73,0,69,0,16,16,19,16,17,19,19,18,19,19,15,19,16,18,19,16,16,16,15,16,14,14,18,0,7,15,0,0,7,15,7,14,6,13,4,12,0,0,9,14,9,11,4,11,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_glacier_1333_r11_mba1[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r11_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,76,0,71,0,21,20,22,20,17,21,23,23,27,22,18,22,20,24,21,15,18,20,15,17,20,14,18,0,14,6,0,0,17,6,17,10,9,6,13,2,0,0,4,3,5,3,10,3,76,0,71,0,19,20,23,20,20,23,23,22,23,23,17,23,19,22,23,19,19,19,18,19,16,16,22,0,9,19,0,0,9,20,9,18,8,16,4,15,0,0,11,17,10,13,5,13,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_glacier_1600_r11_mba1[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r22e_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,77,0,72,0,17,16,18,17,14,17,18,19,22,18,15,18,16,19,17,13,14,16,12,14,17,11,14,0,12,5,0,0,14,5,14,8,7,5,11,2,0,0,3,3,5,3,8,2,77,0,72,0,16,16,19,16,16,18,19,18,19,19,14,18,16,18,19,16,15,16,15,16,13,13,18,0,8,15,0,0,8,16,8,15,7,13,4,12,0,0,9,14,9,11,4,11,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_glacier_1333_r22e_mba1[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r22e_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,81,0,77,0,21,19,21,20,16,21,22,23,27,22,17,21,19,23,21,15,17,19,14,16,20,13,17,0,13,5,0,0,16,5,15,8,7,5,13,2,0,0,4,3,5,3,10,2,81,0,77,0,19,19,23,19,19,22,23,21,23,23,17,22,19,21,23,19,18,19,18,19,16,16,22,0,7,17,0,0,8,18,8,16,7,15,4,15,0,0,11,17,10,13,5,13,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_glacier_1600_r22e_mba1[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r22b_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,69,0,16,14,16,15,12,16,17,17,21,16,12,16,14,18,16,10,12,14,10,12,15,9,12,0,12,6,0,0,15,6,14,8,8,6,11,2,0,0,3,3,5,3,8,2,73,0,69,0,14,14,17,14,14,17,17,16,17,17,12,17,14,16,17,13,13,14,13,14,11,11,16,0,8,16,0,0,8,17,8,15,7,14,4,12,0,0,9,14,9,11,4,10,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_glacier_1333_r22b_mba1[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r22b_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,78,0,71,0,20,18,20,19,15,20,21,22,26,21,16,21,18,23,20,14,16,18,13,15,19,12,16,0,16,8,0,0,20,8,19,12,11,8,14,2,0,0,4,3,6,3,10,3,78,0,71,0,17,18,22,18,18,21,22,20,22,22,15,21,17,20,22,17,17,17,16,17,14,14,21,0,11,21,0,0,11,22,11,20,10,18,4,15,0,0,11,17,11,13,5,13,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_glacier_1600_r22b_mba1[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1066_r44_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,0x20,0x20,0x20,0x20,0x80,0x80,0x80,0x80,0x20,0x20,0x20,0x20,0x80,0x80,0x80,0x80,0xA0,0x20,0x60,0x20,0xA0,0x80,0x90,0x80,0xA0,0x20,0x60,0x20,0xA0,0x80,0x90,0x80,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,74,0,68,0,15,14,15,14,12,15,16,16,19,15,12,15,14,17,15,11,12,14,10,12,14,9,12,0,12,7,0,0,15,7,14,9,9,7,9,1,0,0,3,2,4,3,7,2,74,0,68,0,13,14,16,14,14,16,16,15,16,16,12,16,13,15,16,13,13,13,12,13,11,11,15,0,9,15,0,0,9,16,9,15,8,14,3,10,0,0,8,12,7,9,3,9,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_glacier_1066_r44_mba1[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF }; //UDIMM TEMP FOR JAKE ICICLE -uint32_t udimm_glacier_1600_r10_mba0[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,70,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,7,9,11,10,4,0,3,5,0,0,4,10,3,12,3,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t udimm_glacier_1600_r10_mba0[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF }; -uint32_t udimm_glacier_1600_r10_mba1[210] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,15,13,15,14,10,15,16,17,21,15,11,15,13,18,15,9,11,13,8,10,14,7,11,0,10,2,0,0,13,2,12,5,4,2,0,0,0,0,0,0,0,0,0,0,71,0,0,0,12,13,16,13,13,16,16,15,16,17,11,16,12,15,17,12,12,13,11,12,9,10,15,0,4,14,0,0,4,15,4,13,4,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t udimm_glacier_1600_r10_mba1[STORE_ARRAY_SIZE] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF }; //KG3 -uint32_t rdimm_kg3_1333_r1_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_kg3_1333_r1_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_kg3_1333_r1_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_kg3_1333_r1_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_kg3_1600_r1_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_kg3_1600_r1_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_kg3_1600_r1_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_kg3_1600_r1_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_kg3_1333_r2b_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_kg3_1333_r2b_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_kg3_1333_r2b_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_kg3_1333_r2b_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_kg3_1600_r2b_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_kg3_1600_r2b_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_kg3_1600_r2b_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_kg3_1600_r2b_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_kg3_1333_r2e_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_kg3_1333_r2e_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_kg3_1333_r2e_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_kg3_1333_r2e_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_kg3_1600_r2e_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_kg3_1600_r2e_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_kg3_1600_r2e_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_kg3_1600_r2e_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_kg3_1333_r4_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_kg3_1333_r4_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_kg3_1333_r4_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_kg3_1333_r4_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_kg3_1600_r4_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_kg3_1600_r4_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_kg3_1600_r4_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +uint32_t rdimm_kg3_1600_r4_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; //Base Array Which Is Used For Looper To Setup Data -uint32_t base_var_array[210]; +uint32_t base_var_array[STORE_ARRAY_SIZE]; extern "C" { - //****************************************************************************** //* name=mss_eff_config_termination, param=i_target_mba, return=ReturnCode //****************************************************************************** @@ -776,27 +412,27 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { // find out if we are in simulation mode uint8_t l_attr_is_simulation; - rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, l_attr_is_simulation); + rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, l_attr_is_simulation); if(rc) return rc; // Define local attribute variables uint8_t l_attr_mss_cal_step_enable = 0xFF; //DEBUG MESSAGE! - FAPI_INF("DRAM GEN %d WIDTH %d 00R %d 10R %d 01R %d 11R %d DPP %d stack %d\n",l_dram_gen_u8,l_dram_width_u8,l_num_ranks_per_dimm_u8array[0][0],l_num_ranks_per_dimm_u8array[1][0],l_num_ranks_per_dimm_u8array[0][1],l_num_ranks_per_dimm_u8array[1][1],l_num_drops_per_port,l_stack_type_u8array[0][0]); + FAPI_INF("DRAM GEN %d WIDTH %d 00R %d 10R %d 01R %d 11R %d DPP %d stack %d type %d\n",l_dram_gen_u8,l_dram_width_u8,l_num_ranks_per_dimm_u8array[0][0],l_num_ranks_per_dimm_u8array[1][0],l_num_ranks_per_dimm_u8array[0][1],l_num_ranks_per_dimm_u8array[1][1],l_num_drops_per_port,l_stack_type_u8array[0][0],l_dimm_custom_u8); + //Now, Determine The Type Of Dimm We Are Using //l_target_mba_pos == 0,1 - MBA POS //l_num_drops_per_port == drops / port //if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM ) - //if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) if(l_attr_is_simulation != 0) { FAPI_INF("In Sim Detected %s on %s value is %d", PROCEDURE_NAME, i_target_mba.toEcmdString(), l_attr_is_simulation); - if((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM) || (l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) ){ - memcpy(base_var_array,cdimm_rca_1r_1600_mba1,210*sizeof(uint32_t)); + if((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM) || (l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) ){ + memcpy(base_var_array,cdimm_default,STORE_ARRAY_SIZE*sizeof(uint32_t)); } else if(l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM){ - memcpy(base_var_array,rdimm_glacier_1600_r22e_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1600_r22e_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); } else{ @@ -817,24 +453,24 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { if ( l_mss_freq <= 1466 ) { // 1333Mbps if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { //Removed Width Check, use settings for either x8 or x4, use 1600 settings for 1333! - memcpy(base_var_array,rdimm_kg3_1333_r1_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_kg3_1333_r1_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("LRDIMM: Base - KG3 RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 4)){ - memcpy(base_var_array,rdimm_kg3_1333_r2e_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_kg3_1333_r2e_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("KG3 r2e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){ //Removed Width Check, use settings for either x8 or x4, use 1600 settings for 1333! - memcpy(base_var_array,rdimm_kg3_1333_r1_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_kg3_1333_r1_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("KG3 r1 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 8)){ - memcpy(base_var_array,rdimm_kg3_1333_r2b_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_kg3_1333_r2b_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("KG3 r2b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){ - memcpy(base_var_array,rdimm_kg3_1333_r4_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_kg3_1333_r4_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("KG3 r4 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else{ @@ -846,26 +482,26 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { } else if ( l_mss_freq <= 1733 ) { // 1600Mbps if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { //Removed Width Check, use settings for either x8 or x4 - memcpy(base_var_array,rdimm_kg3_1600_r1_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_kg3_1600_r1_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("LRDIMM: Base - KG3 LRDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){ //Removed Width Check, use settings for either x8 or x4 - memcpy(base_var_array,rdimm_kg3_1600_r1_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_kg3_1600_r1_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("KG3 r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 4)){ - memcpy(base_var_array,rdimm_kg3_1600_r2e_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_kg3_1600_r2e_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("KG3 r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 8)){ - memcpy(base_var_array,rdimm_kg3_1600_r2b_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_kg3_1600_r2b_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("KG3 r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){ - memcpy(base_var_array,rdimm_kg3_1600_r4_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_kg3_1600_r4_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("KG3 r40 %d MBA%s Using 1333 Settings\n",l_mss_freq,i_target_mba.toEcmdString()); } @@ -879,24 +515,24 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { if ( l_mss_freq <= 1466 ) { // 1333Mbps if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { //Removed Width Check, use settings for either x8 or x4, - memcpy(base_var_array,rdimm_kg3_1333_r1_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_kg3_1333_r1_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("LRDIMM: Base - KG3 RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 4)){ - memcpy(base_var_array,rdimm_kg3_1333_r2e_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_kg3_1333_r2e_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("KG3 r2e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){ //Removed Width Check, use settings for either x8 or x4, use 1600 settings for 1333! - memcpy(base_var_array,rdimm_kg3_1333_r1_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_kg3_1333_r1_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("KG3 r1 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 8)){ - memcpy(base_var_array,rdimm_kg3_1333_r2b_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_kg3_1333_r2b_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("KG3 r2b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){ - memcpy(base_var_array,rdimm_kg3_1333_r4_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_kg3_1333_r4_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("KG3 r4 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else{ @@ -908,26 +544,26 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { } else if ( l_mss_freq <= 1733 ) { // 1600Mbps if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { //Removed Width Check, use settings for either x8 or x4 - memcpy(base_var_array,rdimm_kg3_1600_r1_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_kg3_1600_r1_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("LRDIMM: Base - KG3 RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){ //Removed Width Check, use settings for either x8 or x4 - memcpy(base_var_array,rdimm_kg3_1600_r1_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_kg3_1600_r1_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("KG3 r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 4)){ - memcpy(base_var_array,rdimm_kg3_1600_r2e_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_kg3_1600_r2e_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("KG3 r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 8)){ - memcpy(base_var_array,rdimm_kg3_1600_r2b_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_kg3_1600_r2b_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("KG3 r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){ - memcpy(base_var_array,rdimm_kg3_1600_r4_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_kg3_1600_r4_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("KG3 r40 %d MBA%s Using 1333 Settings\n",l_mss_freq,i_target_mba.toEcmdString()); } @@ -941,233 +577,11 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { #endif - else if( (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM) ){ - if((l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM) ){ - //This is a CDIMM! - if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 8) && (l_stack_type_u8array[0][0] == 0) && (l_dram_gen_u8 == 1)){ - //1R Cdimm RCA - l_dimm_rc_u8 = 0; - if ( l_mss_freq <= 1466 ) { // 1333Mbps - if((l_target_mba_pos == 0) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_FALSE)){ - memcpy(base_var_array,cdimm_rca_1r_1333_mba0,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rca_1r_1333 MBA0\n"); - } - else if ((l_target_mba_pos == 0) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_TRUE)){ - //memcpy(base_var_array,cdimm_rca_1r_1333_mba0_DD10,210*sizeof(uint32_t)); //PAULS SETTINGS - memcpy(base_var_array,cdimm_rca_1r_1333_mba0,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rca_1r_1333 MBA0 DD10\n"); - - } - else if ((l_target_mba_pos == 1) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_FALSE)){ - memcpy(base_var_array,cdimm_rca_1r_1333_mba1,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rca_1r_1333 MBA1\n"); - - } - else if ((l_target_mba_pos == 1) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_TRUE)){ - //memcpy(base_var_array,cdimm_rca_1r_1333_mba1_DD10,210*sizeof(uint32_t)); //PAULS SETTINGS - memcpy(base_var_array,cdimm_rca_1r_1333_mba1,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rca_1r_1333 MBA1 DD10\n"); - - } - else{ - FAPI_ERR("Invalid Dimm Type CDIMM FREQ %d\n",l_mss_freq); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - } else if ( l_mss_freq <= 1733 ) { // 1600Mbps - if((l_target_mba_pos == 0) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_FALSE)){ - memcpy(base_var_array,cdimm_rca_1r_1600_mba0,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rca_1r_1600 MBA0\n"); - } - else if ((l_target_mba_pos == 0) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_TRUE)){ - //memcpy(base_var_array,cdimm_rca_1r_1600_mba0_DD10,210*sizeof(uint32_t)); //PAULS SETTINGS - memcpy(base_var_array,cdimm_rca_1r_1600_mba0,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rca_1r_1600 MBA0 DD10\n"); - - } - else if ((l_target_mba_pos == 1) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_FALSE)){ - memcpy(base_var_array,cdimm_rca_1r_1600_mba1,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rca_1r_1600 MBA1\n"); - - } - else if ((l_target_mba_pos == 1) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_TRUE)){ - //memcpy(base_var_array,cdimm_rca_1r_1600_mba1_DD10,210*sizeof(uint32_t)); //PAULS SETTINGS - memcpy(base_var_array,cdimm_rca_1r_1600_mba1,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rca_1r_1600 MBA1 DD10\n"); - - } - else{ - FAPI_ERR("Invalid Dimm Type CDIMM FREQ %d\n",l_mss_freq); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - - }//1600 1R - - }//1R CDIMM - else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 8) && (l_stack_type_u8array[0][0] == 0) && (l_dram_gen_u8 == 1)){ - //2R Cdimm RCA - l_dimm_rc_u8 = 0; - if ( l_mss_freq <= 1466 ) { // 1333Mbps - if((l_target_mba_pos == 0) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_FALSE)){ - memcpy(base_var_array,cdimm_rca_2r_1333_mba0,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rca_2r_1333 MBA0\n"); - } - else if ((l_target_mba_pos == 0) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_TRUE)){ - //memcpy(base_var_array,cdimm_rca_2r_1333_mba0_DD10,210*sizeof(uint32_t)); //PAULS SETTINGS - memcpy(base_var_array,cdimm_rca_2r_1333_mba0,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rca_2r_1333 MBA0 DD10\n"); - - } - else if ((l_target_mba_pos == 1) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_FALSE)){ - memcpy(base_var_array,cdimm_rca_2r_1333_mba1,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rca_2r_1333 MBA1\n"); - - } - else if ((l_target_mba_pos == 1) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_TRUE)){ - //memcpy(base_var_array,cdimm_rca_2r_1333_mba1_DD10,210*sizeof(uint32_t)); //PAULS SETTINGS - memcpy(base_var_array,cdimm_rca_2r_1333_mba1,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rca_2r_1333 MBA1 DD10\n"); - - } - else{ - FAPI_ERR("Invalid Dimm Type CDIMM RCA FREQ %d\n",l_mss_freq); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - } else if ( l_mss_freq <= 1733 ) { // 1600Mbps - if((l_target_mba_pos == 0) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_FALSE)){ - memcpy(base_var_array,cdimm_rca_2r_1600_mba0,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rca_2r_1600 MBA0\n"); - } - else if ((l_target_mba_pos == 0) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_TRUE)){ - //memcpy(base_var_array,cdimm_rca_2r_1600_mba0_DD10,210*sizeof(uint32_t)); //PAULS SETTINGS - memcpy(base_var_array,cdimm_rca_2r_1600_mba0,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rca_2r_1600 MBA0 DD10\n"); - - } - else if ((l_target_mba_pos == 1) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_FALSE)){ - memcpy(base_var_array,cdimm_rca_2r_1600_mba1,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rca_2r_1600 MBA1\n"); - - } - else if ((l_target_mba_pos == 1) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_TRUE)){ - //memcpy(base_var_array,cdimm_rca_1r_1600_mba1_DD10,210*sizeof(uint32_t)); //PAULS SETTINGS - memcpy(base_var_array,cdimm_rca_2r_1600_mba1,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rca_2r_1600 MBA1 DD10\n"); - - } - else{ - FAPI_ERR("Invalid Dimm Type CDIMM RCA FREQ %d\n",l_mss_freq); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - - }//1600 2R - }//2R CDIMM RCA - else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 4) && (l_stack_type_u8array[0][0] == 0) && (l_dram_gen_u8 == 1)){ - //2R Cdimm RCB - l_dimm_rc_u8 = 1; - if ( l_mss_freq <= 1466 ) { // 1333Mbps - if(l_target_mba_pos == 0){ - memcpy(base_var_array,cdimm_rcb_2r_1333_mba0,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rcb_2r_1333 MBA0 \n"); - - - } - else if(l_target_mba_pos == 1){ - memcpy(base_var_array,cdimm_rcb_2r_1333_mba1,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rcb_2r_1333 MBA1 \n"); - - } - else{ - FAPI_ERR("Invalid Dimm Type CDIMM RCB FREQ %d\n",l_mss_freq); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - - } else if ( l_mss_freq <= 1733 ) { // 1600Mbps - if(l_target_mba_pos == 0){ - memcpy(base_var_array,cdimm_rcb_2r_1600_mba0,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rcb_2r_1600 MBA0 \n"); - - - } - else if(l_target_mba_pos == 1){ - memcpy(base_var_array,cdimm_rcb_2r_1600_mba1,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rcb_2r_1600 MBA1 \n"); - - } - else{ - FAPI_ERR("Invalid Dimm Type CDIMM RCB FREQ %d\n",l_mss_freq); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - } - }//CDIMM RCB - //else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[1][0] == 1) && ((l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) || (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)) && (l_dram_width_u8 == 4) && (l_stack_type_u8array[0][0] == 0) && (l_dram_gen_u8 == 2)){ - else if(l_dram_gen_u8 == 2){ - //2R Cdimm RCB4 - l_dimm_rc_u8 = 2; - if ( l_mss_freq <= 1733 ) { // 1600Mbps - if(l_target_mba_pos == 0){ - memcpy(base_var_array,cdimm_rcb4_2r_1600_mba0,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rcb4_2r_1600 MBA0 \n"); - //memcpy(base_var_array,cdimm_rcb_2r_1600_mba0,210*sizeof(uint32_t)); - //FAPI_INF("CDIMM rcb4 Running with RCB DDR3 Settings MBA0\n"); - - } - else if(l_target_mba_pos == 1){ - memcpy(base_var_array,cdimm_rcb4_2r_1600_mba1,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rcb4_2r_1600 MBA1 \n"); - //memcpy(base_var_array,cdimm_rcb_2r_1600_mba1,210*sizeof(uint32_t)); - //FAPI_INF("CDIMM rcb4 Running with RCB DDR3 Settings MBA1\n"); - - - } - else{ - FAPI_ERR("Invalid Dimm Type CDIMM RCB4 FREQ %d\n",l_mss_freq); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - } - }//CDIMM RCB4 - else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 4) && (l_stack_type_u8array[0][0] == 1) && (l_dram_gen_u8 == 1)){ - //2R Cdimm RCC - l_dimm_rc_u8 = 3; - if ( l_mss_freq <= 1466 ) { // 1333Mbps - if(l_target_mba_pos == 0){ - memcpy(base_var_array,cdimm_rcc_2r_1333_mba0,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rcc_2r_1333 MBA0 \n"); - - - } - else if(l_target_mba_pos == 1){ - memcpy(base_var_array,cdimm_rcc_2r_1333_mba1,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rcc_2r_1333 MBA1 \n"); - - } - else{ - FAPI_ERR("Invalid Dimm Type CDIMM RCC FREQ %d\n",l_mss_freq); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - - } else if ( l_mss_freq <= 1733 ) { // 1600Mbps - if(l_target_mba_pos == 0){ - memcpy(base_var_array,cdimm_rcc_2r_1600_mba0,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rcc_2r_1600 MBA0 \n"); - - - } - else if(l_target_mba_pos == 1){ - memcpy(base_var_array,cdimm_rcc_2r_1600_mba1,210*sizeof(uint32_t)); - FAPI_INF("CDIMM rcc_2r_1600 MBA1 \n"); - - } - else{ - FAPI_ERR("Invalid Dimm Type CDIMM RCC FREQ %d\n",l_mss_freq); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - } - }//CDIMM RCC - else{ - FAPI_ERR("Invalid Dimm Type"); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + else if((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM) || (l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)){ + if(l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) { - } + //This is a CDIMM! + memcpy(base_var_array,cdimm_default,STORE_ARRAY_SIZE*sizeof(uint32_t)); }//End CDIMM else{ //This is a UDIMM! @@ -1175,7 +589,7 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { if( l_target_mba_pos == 0 ){ if ( l_mss_freq <= 1733 ) { // 1600Mbps if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 8)){ - memcpy(base_var_array,udimm_glacier_1600_r10_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,udimm_glacier_1600_r10_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("UDIMM ICICLE r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else{ @@ -1192,7 +606,7 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { else{ if ( l_mss_freq <= 1733 ) { // 1600Mbps if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 8)){ - memcpy(base_var_array,udimm_glacier_1600_r10_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,udimm_glacier_1600_r10_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("UDIMM ICICLE r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else{ @@ -1218,20 +632,20 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { if ( l_mss_freq <= 1466 ) { // 1333Mbps if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 4)){ - memcpy(base_var_array,rdimm_glacier_1333_r20e_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1333_r20e_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){ //Removed Width Check, use settings for either x8 or x4, use 1600 settings for 1333! - memcpy(base_var_array,rdimm_glacier_1600_r10_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1600_r10_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 8)){ - memcpy(base_var_array,rdimm_glacier_1333_r20b_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1333_r20b_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){ - memcpy(base_var_array,rdimm_glacier_1333_r40_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1333_r40_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r40 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else{ @@ -1242,22 +656,22 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { } else if ( l_mss_freq <= 1733 ) { // 1600Mbps if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){ //Removed Width Check, use settings for either x8 or x4 - memcpy(base_var_array,rdimm_glacier_1600_r10_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1600_r10_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 4)){ - memcpy(base_var_array,rdimm_glacier_1600_r20e_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1600_r20e_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 8)){ - memcpy(base_var_array,rdimm_glacier_1600_r20b_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1600_r20b_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){ //USE 1333 settings at 1600 - memcpy(base_var_array,rdimm_glacier_1333_r40_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1333_r40_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r40 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } @@ -1270,11 +684,11 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { else{ if ( l_mss_freq <= 1200 ) { // 1066Mbps if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 4)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 4)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){ - memcpy(base_var_array,rdimm_glacier_1066_r44_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1066_r44_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r44 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ - memcpy(base_var_array,rdimm_glacier_1066_r40_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1066_r40_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r44 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else{ @@ -1284,32 +698,32 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { } else if ( l_mss_freq <= 1466 ) { // 1333Mbps if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ - memcpy(base_var_array,rdimm_glacier_1333_r10_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1333_r10_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){ - memcpy(base_var_array,rdimm_glacier_1333_r11_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1333_r11_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r11 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 4)){ - memcpy(base_var_array,rdimm_glacier_1333_r20e_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1333_r20e_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 8)){ - memcpy(base_var_array,rdimm_glacier_1333_r20b_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1333_r20b_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 4)){ - memcpy(base_var_array,rdimm_glacier_1333_r22e_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1333_r22e_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r22e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 8)){ - memcpy(base_var_array,rdimm_glacier_1333_r22b_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1333_r22b_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r22b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 0))) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ //Use 4R MBA0 settings for CD only! - memcpy(base_var_array,rdimm_glacier_1333_r40_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1333_r40_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r40 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } @@ -1321,33 +735,33 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { } else if ( l_mss_freq <= 1733 ) { // 1600Mbps if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ - memcpy(base_var_array,rdimm_glacier_1600_r10_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1600_r10_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){ - memcpy(base_var_array,rdimm_glacier_1600_r11_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1600_r11_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r11 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 4)){ - memcpy(base_var_array,rdimm_glacier_1600_r20e_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1600_r20e_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 8)){ - memcpy(base_var_array,rdimm_glacier_1600_r20b_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1600_r20b_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 4)){ - memcpy(base_var_array,rdimm_glacier_1600_r22e_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1600_r22e_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r22e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 8)){ - memcpy(base_var_array,rdimm_glacier_1600_r22b_mba1,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1600_r22b_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r22b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 0))) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ //Use 4R MBA0 1333 settings for CD only! - memcpy(base_var_array,rdimm_glacier_1333_r40_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1333_r40_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("RDIMM r40 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else{ @@ -1363,23 +777,23 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { if( l_target_mba_pos == 0){ if ( l_mss_freq <= 1466 ) { // 1333Mbps //Removed Width Check, use settings for either x8 or x4, use 1600 settings for 1333! - memcpy(base_var_array,rdimm_glacier_1600_r10_mba0,200*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1600_r10_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("LRDIMM: Base - RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if ( l_mss_freq <= 1733 ) { // 1600Mbps //Removed Width Check, use settings for either x8 or x4 - memcpy(base_var_array,rdimm_glacier_1600_r10_mba0,200*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1600_r10_mba0,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("LRDIMM: Base - LRDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } }//MBA0 else{ if ( l_mss_freq <= 1466 ) { // 1333Mbps if( (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ - memcpy(base_var_array,rdimm_glacier_1333_r10_mba1,200*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1333_r10_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("LRDIMM: Base - RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if( (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){ - memcpy(base_var_array,rdimm_glacier_1333_r11_mba1,200*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1333_r11_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("LRDIMM: Base - RDIMM r11 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else{ @@ -1389,11 +803,11 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { } else if ( l_mss_freq <= 1733 ) { // 1600Mbps if( (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ - memcpy(base_var_array,rdimm_glacier_1600_r10_mba1,200*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1600_r10_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("LRDIMM: Base - RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if( (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){ - memcpy(base_var_array,rdimm_glacier_1600_r11_mba1,200*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1600_r11_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); FAPI_INF("LRDIMM: Base - RDIMM r11 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else{ @@ -1432,293 +846,25 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; } - //SIM Mode - if(l_attr_is_simulation != 0) { - FAPI_INF("In Sim Detected %s on %s value is %d", PROCEDURE_NAME, i_target_mba.toEcmdString(), l_attr_is_simulation); - for( int l_array_offset = 102; l_array_offset < 198;l_array_offset++){ - if( (l_array_offset == 102) || - (l_array_offset == 103) || - (l_array_offset == 104) || - (l_array_offset == 105) || - (l_array_offset == 150) || - (l_array_offset == 151) || - (l_array_offset == 152) || - (l_array_offset == 153) ) - { - base_var_array[l_array_offset] = 0x40; - }//end if - else{ - base_var_array[l_array_offset] = 0x00; - }//end else - - - }//end for - - }//end if - - //DD1.0 N_WELL WORKAROUND - // Check for Centaur EC10 ADR Centerlane NWELL LVS issue PR=0x7F workaround. - if ( l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_TRUE && (l_attr_is_simulation == 0) ) { - for( int l_array_offset = 102; l_array_offset < 198;l_array_offset++){ - if ((((l_target_mba_pos == 0) && (l_array_offset == 118)) || // MA_CMD_A<12> - ((l_target_mba_pos == 0) && (l_array_offset == 106)) || // MA_CMS_A<0> - ((l_target_mba_pos == 0) && (l_array_offset == 119)) || // MA_CMD_A<13> - ((l_target_mba_pos == 0) && (l_array_offset == 122)) || // MA_CMD_BA<0> - ((l_target_mba_pos == 0) && (l_array_offset == 184)) || // MB0_CNTL_CSN<2> - ((l_target_mba_pos == 0) && (l_array_offset == 186)) || // MB0_CNTL_ODT<0> - ((l_target_mba_pos == 0) && (l_array_offset == 165)) || // MB_CMD_A<11> - ((l_target_mba_pos == 0) && (l_array_offset == 178)) || // MB0_CNTL_CKE<0> - ((l_target_mba_pos == 1) && (l_array_offset == 107)) || // MC_CMD_A<1> - ((l_target_mba_pos == 1) && (l_array_offset == 112)) || // MC_CMD_A<6> - ((l_target_mba_pos == 1) && (l_array_offset == 128)) || // MC_CMD_PAR - ((l_target_mba_pos == 1) && (l_array_offset == 149)) || // MC1_CNTL_ODT<1> - ((l_target_mba_pos == 1) && (l_array_offset == 182)) || // MD0_CNTL_CSN<0> - ((l_target_mba_pos == 1) && (l_array_offset == 164)) || // MD_CMD_A<10> - ((l_target_mba_pos == 1) && (l_array_offset == 194)) || // MD1_CNTL_CSN<2> - ((l_target_mba_pos == 1) && (l_array_offset == 186))) && // MD0_CNTL_ODT<0> - (l_attr_is_simulation == 0)) { - FAPI_INF("WARNING: Centaur EC10 ADR Centerlane PR=0x7F workaround for NWELL LVS issue on CmdLaneIndex %d MBA %s!", l_array_offset, i_target_mba.toEcmdString()); - base_var_array[l_array_offset] = 0x7F; - } else { - if (((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM) && (l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM)) { - if ((base_var_array[l_array_offset] - 32) > base_var_array[l_array_offset] ) { - base_var_array[l_array_offset] = 0; - } else { - FAPI_INF("OFFSET %d Value %d Value-32 %d\n",l_array_offset,base_var_array[l_array_offset],base_var_array[l_array_offset]-32); - base_var_array[l_array_offset] = base_var_array[l_array_offset] - 32; - - } - }//End IS CDIMM - }//END ELSE - - }//END FOR - }//END IF DD1.0 - - //RC-C DD1.01 Hack For Port A - if((l_bluewaterfall_broken == 1) && (l_nwell_misplacement == 0) && (l_dimm_rc_u8 == 3)){ - FAPI_INF("DD1.01 RC/C, Applying Port A Workaround For Phase Rotators!\n"); - if(l_target_mba_pos == 0){ - for( int l_array_offset = 102; l_array_offset < 150;l_array_offset++){ - base_var_array[l_array_offset] = base_var_array[l_array_offset] + 16; - - } - } - } - - - - - // Now Set All The Attributes uint8_t i = 0; - attr_eff_dimm_rcd_ibt[0][0] = base_var_array[i++]; - attr_eff_dimm_rcd_ibt[0][1] = base_var_array[i++]; - attr_eff_dimm_rcd_ibt[1][0] = base_var_array[i++]; - attr_eff_dimm_rcd_ibt[1][1] = base_var_array[i++]; - attr_eff_dimm_rcd_mirror_mode[0][0] = base_var_array[i++]; - attr_eff_dimm_rcd_mirror_mode[0][1] = base_var_array[i++]; - attr_eff_dimm_rcd_mirror_mode[1][0] = base_var_array[i++]; - attr_eff_dimm_rcd_mirror_mode[1][1] = base_var_array[i++]; - attr_eff_dram_ron[0][0] = base_var_array[i++]; - attr_eff_dram_ron[0][1] = base_var_array[i++]; - attr_eff_dram_ron[1][0] = base_var_array[i++]; - attr_eff_dram_ron[1][1] = base_var_array[i++]; - attr_eff_dram_rtt_nom[0][0][0] = base_var_array[i++]; - attr_eff_dram_rtt_nom[0][0][1] = base_var_array[i++]; - attr_eff_dram_rtt_nom[0][0][2] = base_var_array[i++]; - attr_eff_dram_rtt_nom[0][0][3] = base_var_array[i++]; - attr_eff_dram_rtt_nom[0][1][0] = base_var_array[i++]; - attr_eff_dram_rtt_nom[0][1][1] = base_var_array[i++]; - attr_eff_dram_rtt_nom[0][1][2] = base_var_array[i++]; - attr_eff_dram_rtt_nom[0][1][3] = base_var_array[i++]; - attr_eff_dram_rtt_nom[1][0][0] = base_var_array[i++]; - attr_eff_dram_rtt_nom[1][0][1] = base_var_array[i++]; - attr_eff_dram_rtt_nom[1][0][2] = base_var_array[i++]; - attr_eff_dram_rtt_nom[1][0][3] = base_var_array[i++]; - attr_eff_dram_rtt_nom[1][1][0] = base_var_array[i++]; - attr_eff_dram_rtt_nom[1][1][1] = base_var_array[i++]; - attr_eff_dram_rtt_nom[1][1][2] = base_var_array[i++]; - attr_eff_dram_rtt_nom[1][1][3] = base_var_array[i++]; - attr_eff_dram_rtt_wr[0][0][0] = base_var_array[i++]; - attr_eff_dram_rtt_wr[0][0][1] = base_var_array[i++]; - attr_eff_dram_rtt_wr[0][0][2] = base_var_array[i++]; - attr_eff_dram_rtt_wr[0][0][3] = base_var_array[i++]; - attr_eff_dram_rtt_wr[0][1][0] = base_var_array[i++]; - attr_eff_dram_rtt_wr[0][1][1] = base_var_array[i++]; - attr_eff_dram_rtt_wr[0][1][2] = base_var_array[i++]; - attr_eff_dram_rtt_wr[0][1][3] = base_var_array[i++]; - attr_eff_dram_rtt_wr[1][0][0] = base_var_array[i++]; - attr_eff_dram_rtt_wr[1][0][1] = base_var_array[i++]; - attr_eff_dram_rtt_wr[1][0][2] = base_var_array[i++]; - attr_eff_dram_rtt_wr[1][0][3] = base_var_array[i++]; - attr_eff_dram_rtt_wr[1][1][0] = base_var_array[i++]; - attr_eff_dram_rtt_wr[1][1][1] = base_var_array[i++]; - attr_eff_dram_rtt_wr[1][1][2] = base_var_array[i++]; - attr_eff_dram_rtt_wr[1][1][3] = base_var_array[i++]; - attr_eff_odt_rd[0][0][0] = base_var_array[i++]; - attr_eff_odt_rd[0][0][1] = base_var_array[i++]; - attr_eff_odt_rd[0][0][2] = base_var_array[i++]; - attr_eff_odt_rd[0][0][3] = base_var_array[i++]; - attr_eff_odt_rd[0][1][0] = base_var_array[i++]; - attr_eff_odt_rd[0][1][1] = base_var_array[i++]; - attr_eff_odt_rd[0][1][2] = base_var_array[i++]; - attr_eff_odt_rd[0][1][3] = base_var_array[i++]; - attr_eff_odt_rd[1][0][0] = base_var_array[i++]; - attr_eff_odt_rd[1][0][1] = base_var_array[i++]; - attr_eff_odt_rd[1][0][2] = base_var_array[i++]; - attr_eff_odt_rd[1][0][3] = base_var_array[i++]; - attr_eff_odt_rd[1][1][0] = base_var_array[i++]; - attr_eff_odt_rd[1][1][1] = base_var_array[i++]; - attr_eff_odt_rd[1][1][2] = base_var_array[i++]; - attr_eff_odt_rd[1][1][3] = base_var_array[i++]; - attr_eff_odt_wr[0][0][0] = base_var_array[i++]; - attr_eff_odt_wr[0][0][1] = base_var_array[i++]; - attr_eff_odt_wr[0][0][2] = base_var_array[i++]; - attr_eff_odt_wr[0][0][3] = base_var_array[i++]; - attr_eff_odt_wr[0][1][0] = base_var_array[i++]; - attr_eff_odt_wr[0][1][1] = base_var_array[i++]; - attr_eff_odt_wr[0][1][2] = base_var_array[i++]; - attr_eff_odt_wr[0][1][3] = base_var_array[i++]; - attr_eff_odt_wr[1][0][0] = base_var_array[i++]; - attr_eff_odt_wr[1][0][1] = base_var_array[i++]; - attr_eff_odt_wr[1][0][2] = base_var_array[i++]; - attr_eff_odt_wr[1][0][3] = base_var_array[i++]; - attr_eff_odt_wr[1][1][0] = base_var_array[i++]; - attr_eff_odt_wr[1][1][1] = base_var_array[i++]; - attr_eff_odt_wr[1][1][2] = base_var_array[i++]; - attr_eff_odt_wr[1][1][3] = base_var_array[i++]; - attr_eff_cen_rd_vref[0] = base_var_array[i++]; - attr_eff_cen_rd_vref[1] = base_var_array[i++]; - if(l_dram_gen_u8 == 1){ - attr_eff_dram_wr_vref[0] = base_var_array[i++]; - attr_eff_dram_wr_vref[1] = base_var_array[i++]; - } - else if(l_dram_gen_u8 == 2){ - attr_eff_dram_wrddr4_vref[0] = base_var_array[i++]; - attr_eff_dram_wrddr4_vref[1] = base_var_array[i++]; - attr_eff_dram_wrddr4_vref[0] = base_var_array[i++]; - attr_eff_dram_wrddr4_vref[1] = base_var_array[i++]; - } - attr_eff_cen_rcv_imp_dq_dqs[0] = base_var_array[i++]; - attr_eff_cen_rcv_imp_dq_dqs[1] = base_var_array[i++]; - attr_eff_cen_drv_imp_dq_dqs[0] = base_var_array[i++]; - attr_eff_cen_drv_imp_dq_dqs[1] = base_var_array[i++]; - attr_eff_cen_drv_imp_cntl[0] = base_var_array[i++]; - attr_eff_cen_drv_imp_cntl[1] = base_var_array[i++]; - attr_eff_cen_drv_imp_addr[0] = base_var_array[i++]; - attr_eff_cen_drv_imp_addr[1] = base_var_array[i++]; - attr_eff_cen_drv_imp_clk[0] = base_var_array[i++]; - attr_eff_cen_drv_imp_clk[1] = base_var_array[i++]; - attr_eff_cen_drv_imp_spcke[0] = base_var_array[i++]; - attr_eff_cen_drv_imp_spcke[1] = base_var_array[i++]; - attr_eff_cen_slew_rate_dq_dqs[0] = base_var_array[i++]; - attr_eff_cen_slew_rate_dq_dqs[1] = base_var_array[i++]; - attr_eff_cen_slew_rate_cntl[0] = base_var_array[i++]; - attr_eff_cen_slew_rate_cntl[1] = base_var_array[i++]; - attr_eff_cen_slew_rate_addr[0] = base_var_array[i++]; - attr_eff_cen_slew_rate_addr[1] = base_var_array[i++]; - attr_eff_cen_slew_rate_clk[0] = base_var_array[i++]; - attr_eff_cen_slew_rate_clk[1] = base_var_array[i++]; - attr_eff_cen_slew_rate_spcke[0] = base_var_array[i++]; - attr_eff_cen_slew_rate_spcke[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_clk_p0[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_clk_p1[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_clk_p0[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_clk_p1[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a0[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a1[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a2[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a3[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a4[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a5[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a6[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a7[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a8[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a9[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a10[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a11[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a12[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a13[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a14[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a15[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_bA0[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_bA1[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_bA2[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_casn[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_rasn[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_wen[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_par[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_actn[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_cntl_cke0[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_cntl_cke1[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_cntl_cke2[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_cntl_cke3[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_cntl_csn0[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_cntl_csn1[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_cntl_csn2[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_cntl_csn3[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_cntl_odt0[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_cntl_odt1[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_cntl_cke0[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_cntl_cke1[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_cntl_cke2[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_cntl_cke3[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_cntl_csn0[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_cntl_csn1[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_cntl_csn2[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_cntl_csn3[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_cntl_odt0[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_cntl_odt1[0] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_clk_p0[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_clk_p1[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_clk_p0[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_clk_p1[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a0[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a1[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a2[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a3[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a4[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a5[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a6[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a7[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a8[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a9[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a10[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a11[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a12[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a13[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a14[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_a15[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_bA0[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_bA1[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_bA2[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_casn[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_rasn[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_cmd_wen[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_par[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m_actn[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_cntl_cke0[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_cntl_cke1[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_cntl_cke2[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_cntl_cke3[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_cntl_csn0[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_cntl_csn1[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_cntl_csn2[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_cntl_csn3[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_cntl_odt0[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m0_cntl_odt1[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_cntl_cke0[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_cntl_cke1[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_cntl_cke2[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_cntl_cke3[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_cntl_csn0[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_cntl_csn1[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_cntl_csn2[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_cntl_csn3[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_cntl_odt0[1] = base_var_array[i++]; - attr_eff_cen_phase_rot_m1_cntl_odt1[1] = base_var_array[i++]; - attr_eff_dram_2n_mode_enabled = base_var_array[i++]; - + attr_eff_dimm_rcd_ibt[0][0] = base_var_array[i++]; // keep 0 + attr_eff_dimm_rcd_ibt[0][1] = base_var_array[i++]; // keep 1 + attr_eff_dimm_rcd_ibt[1][0] = base_var_array[i++]; // keep 2 + attr_eff_dimm_rcd_ibt[1][1] = base_var_array[i++]; // keep 3 + attr_eff_dimm_rcd_mirror_mode[0][0] = base_var_array[i++]; // keep 4 + attr_eff_dimm_rcd_mirror_mode[0][1] = base_var_array[i++]; // keep 5 + attr_eff_dimm_rcd_mirror_mode[1][0] = base_var_array[i++]; // keep 6 + attr_eff_dimm_rcd_mirror_mode[1][1] = base_var_array[i++]; // keep 7 + + // set these attributes from the VPD but allow the code to override later + rc = FAPI_ATTR_GET(ATTR_VPD_CEN_RD_VREF, &i_target_mba, attr_eff_cen_rd_vref); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_WR_VREF, &i_target_mba, attr_eff_dram_wr_vref); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_WRDDR4_VREF, &i_target_mba, attr_eff_dram_wrddr4_vref); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_VPD_CEN_RCV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_rcv_imp_dq_dqs); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_VPD_CEN_DRV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_drv_imp_dq_dqs); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_VPD_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, attr_eff_cen_slew_rate_dq_dqs); if(rc) return rc; + //Now Setup the RCD - Done Here to Steal Code From Anuwats Version Of Eff Config Termination if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM ) { @@ -1797,25 +943,39 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { } } - // Address mirroring - uint8_t attr_eff_dram_address_mirroring[PORT_SIZE][DIMM_SIZE]; - for( int l_port = 0; l_port < PORT_SIZE; l_port += 1 ) { - for( int l_dimm = 0; l_dimm < DIMM_SIZE; l_dimm += 1 ) { - if ((l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dimm == 1) && (l_dimm_rc_u8 !=3) && (l_stack_type_u8array[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE)) { - // For DUAL DROP CDIMM - attr_eff_dram_address_mirroring[l_port][l_dimm] = 0x0F; - } else if ( (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) && (l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & 0x0000000000000010LL) ) { - // For LRDIMM SPD file , == 1 Odd ranks are mirrored - attr_eff_dram_address_mirroring[l_port][l_dimm] = 0x05; - - } else { - attr_eff_dram_address_mirroring[l_port][l_dimm] = 0x00; - } - } - } - // For DDR4 + uint8_t l_attr_eff_dram_lpasr = ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_NORMAL; // 0 + uint8_t l_attr_eff_write_crc = ENUM_ATTR_EFF_WRITE_CRC_ENABLE; // 0; change ENUMS: DISABLE=0, ENABLE=1 + uint8_t l_attr_eff_mpr_page = 0; // 0; maybe add ENUMS: PG0=0, PG1=1, PG2=2, PG3=3 for more readability? + uint8_t l_attr_eff_geardown_mode = ENUM_ATTR_EFF_GEARDOWN_MODE_HALF; // 0 + uint8_t l_attr_eff_per_dram_access = ENUM_ATTR_EFF_PER_DRAM_ACCESS_DISABLE; // 1; change ENUMS: DISABLE=0; ENABLE=1 + uint8_t l_attr_eff_temp_readout = ENUM_ATTR_EFF_TEMP_READOUT_DISABLE; // 1; change ENUMS: DISABLE=0; ENABLE=1 + uint8_t l_attr_eff_fine_refresh_mode = ENUM_ATTR_EFF_FINE_REFRESH_MODE_NORMAL; // 4; maybe change ENUMS: NORMAL=0; FIXED_2X=1, FIXED_4X=2, FLY_2X=5, FLY_4X=6 to align with spec better + uint8_t l_attr_eff_crc_wr_latency = ENUM_ATTR_EFF_CRC_WR_LATENCY_4NCK; // 0; change ENUMS: 4NCK=4, 5NCK=5, 6NCK=6 following convention + uint8_t l_attr_eff_mpr_rd_format = ENUM_ATTR_EFF_MPR_RD_FORMAT_SERIAL; // 0 + uint8_t l_attr_eff_max_powerdown_mode = ENUM_ATTR_EFF_MAX_POWERDOWN_MODE_DISABLE; // 1; change ENUMS: DISABLE=0, ENABLE=1 + uint8_t l_attr_eff_temp_ref_range = ENUM_ATTR_EFF_TEMP_REF_RANGE_NORMAL; // 0 + uint8_t l_attr_eff_temp_ref_mode = ENUM_ATTR_EFF_TEMP_REF_MODE_ENABLE; // 0; change ENUMS: DISABLE=0, ENABLE=1 + uint8_t l_attr_eff_int_vref_mon = ENUM_ATTR_EFF_INT_VREF_MON_DISABLE; // change to disable; change ENUMS: DISABLE=0, ENABLE=1 + uint8_t l_attr_eff_cs_cmd_latency = 0; // 0; maybe add ENUMS: DISABLE=0, 3CYC=3, 4CYC=4, 5CYC=5, 6CYC=6, 8CYC=8 for better readability + uint8_t l_attr_eff_self_ref_abort = ENUM_ATTR_EFF_SELF_REF_ABORT_DISABLE; // 1; change ENUMS: DISABLE=0, ENABLE=1 + uint8_t l_attr_eff_rd_preamble_train = ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_DISABLE; // 1; change ENUMS: DISABLE=0, ENABLE=1 + uint8_t l_attr_eff_rd_preamble = ENUM_ATTR_EFF_RD_PREAMBLE_1NCLK; // 0; change ENUMS: 1NCK=1, 2NCK=2 following convention + uint8_t l_attr_eff_wr_preamble = ENUM_ATTR_EFF_WR_PREAMBLE_1NCLK; // 0; change ENUMS: 1NCK=1, 2NCK=2 following convention + uint8_t l_attr_eff_ca_parity_latency = ENUM_ATTR_EFF_CA_PARITY_LATENCY_DISABLE; // 0; add ENUMS: PL4=4, PL5=5, PL6=6, PL8=8, for better readability + uint8_t l_attr_eff_crc_error_clear = ENUM_ATTR_EFF_CRC_ERROR_CLEAR_ERROR; // 0; change ENUMS: CLEAR=0, ERROR=1 to match spec. + uint8_t l_attr_eff_ca_parity_error_status = ENUM_ATTR_EFF_CA_PARITY_ERROR_STATUS_ERROR; // 0; change ENUMS: CLEAR=0, ERROR=1 to match spec + uint8_t l_attr_eff_odt_input_buff = ENUM_ATTR_EFF_ODT_INPUT_BUFF_ACTIVATED; // 0; change ENUMS: DEACTIVATED=0, ACTIVATED=1 + uint8_t l_attr_eff_ca_parity = ENUM_ATTR_EFF_CA_PARITY_DISABLE; // change to disable; change ENUMS: DISABLE=0, ENABLE=1 to match spec + uint8_t l_attr_eff_data_mask = ENUM_ATTR_EFF_DATA_MASK_DISABLE; // 0 + uint8_t l_attr_eff_write_dbi = ENUM_ATTR_EFF_WRITE_DBI_DISABLE; // 0 + uint8_t l_attr_eff_read_dbi = ENUM_ATTR_EFF_READ_DBI_DISABLE; // 0 +// uint8_t l_attr_tccd_l = ENUM_ATTR_TCCD_L_5NCK; // 5; maybe add ENUMS: 4NCK=4, 5NCK=5, 6NCK=6; 7NCK=7, 8NCK=8 for better readability + uint8_t l_attr_tccd_l = 5; // 5; maybe add ENUMS: 4NCK=4, 5NCK=5, 6NCK=6; 7NCK=7, 8NCK=8 for better readability + +/* + * Remove Before COMMIT uint8_t l_attr_eff_dram_lpasr = 0; uint8_t l_attr_eff_write_crc = 0; uint8_t l_attr_eff_mpr_page = 0; @@ -1843,6 +1003,7 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { uint8_t l_attr_eff_write_dbi = 0; uint8_t l_attr_eff_read_dbi = 0; uint8_t l_attr_tccd_l = 5; +*/ uint8_t l_attr_eff_rtt_park[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; uint8_t l_attr_vref_dq_train_value[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; uint8_t l_attr_vref_dq_train_range[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; @@ -1852,9 +1013,9 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { for( int l_dimm = 0; l_dimm < DIMM_SIZE; l_dimm += 1 ) { for( int l_rank = 0; l_rank < RANK_SIZE; l_rank += 1 ) { l_attr_eff_rtt_park[l_port][l_dimm][l_rank] = 0; - l_attr_vref_dq_train_value[l_port][l_dimm][l_rank] = 0; + l_attr_vref_dq_train_value[l_port][l_dimm][l_rank] = 16; l_attr_vref_dq_train_range[l_port][l_dimm][l_rank] = 0; - l_attr_vref_dq_train_enable[l_port][l_dimm][l_rank] = 1; + l_attr_vref_dq_train_enable[l_port][l_dimm][l_rank] = ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_DISABLE; } } } @@ -1862,9 +1023,11 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { //RLO Settings FAPI_INF("Card Type is %d BW %d NW %d POS %d\n",l_dimm_rc_u8,l_bluewaterfall_broken,l_nwell_misplacement,l_target_mba_pos); - if((l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM)){ + if(l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES){ //if((l_lab_raw_card_u8 == 0) || (l_lab_raw_card_u8 == 1) || (l_lab_raw_card_u8 == 2) || (l_lab_raw_card_u8 == 3)){ //These are cdimms, RLO on all ports is 1! + //WLO,RLO,GPO all come from VPD NOW +/* if((l_bluewaterfall_broken == 1) && (l_nwell_misplacement == 0) && (l_dimm_rc_u8 == 3) && (l_target_mba_pos == 0)){ FAPI_INF("DD1.01 RC/C, Applying Port A Workaround For RLO!\n"); attr_eff_rlo[0] = (uint8_t)2; @@ -1890,7 +1053,7 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { attr_eff_wlo[1] = (uint8_t)0; attr_eff_gpo[0] = (uint8_t)5; attr_eff_gpo[1] = (uint8_t)5; - +*/ } else if(l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM){ @@ -1969,78 +1132,12 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, attr_eff_dram_wr_vref); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_rcv_imp_dq_dqs); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_drv_imp_dq_dqs); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_CNTL, &i_target_mba, attr_eff_cen_drv_imp_cntl); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_ADDR, &i_target_mba, attr_eff_cen_drv_imp_addr); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_CLK, &i_target_mba, attr_eff_cen_drv_imp_clk); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_SPCKE, &i_target_mba, attr_eff_cen_drv_imp_spcke); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, attr_eff_cen_slew_rate_dq_dqs); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CNTL, &i_target_mba, attr_eff_cen_slew_rate_cntl); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_ADDR, &i_target_mba, attr_eff_cen_slew_rate_addr); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CLK, &i_target_mba, attr_eff_cen_slew_rate_clk); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_SPCKE, &i_target_mba, attr_eff_cen_slew_rate_spcke); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RON, &i_target_mba, attr_eff_dram_ron); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RTT_NOM, &i_target_mba, attr_eff_dram_rtt_nom); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RTT_WR, &i_target_mba, attr_eff_dram_rtt_wr); if(rc) return rc; - if(l_dram_gen_u8 == 2){ - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WRDDR4_VREF, &i_target_mba, attr_eff_dram_wrddr4_vref); if(rc) return rc; - } - rc = FAPI_ATTR_SET(ATTR_EFF_ODT_RD, &i_target_mba, attr_eff_odt_rd); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_ODT_WR, &i_target_mba, attr_eff_odt_wr); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0, &i_target_mba, attr_eff_cen_phase_rot_m0_clk_p0); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1, &i_target_mba, attr_eff_cen_phase_rot_m0_clk_p1); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0, &i_target_mba, attr_eff_cen_phase_rot_m1_clk_p0); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1, &i_target_mba, attr_eff_cen_phase_rot_m1_clk_p1); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a0); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a1); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a2); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a3); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a4); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a5); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a6); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a7); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a8); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a9); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a10); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a11); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a12); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a13); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a14); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a15); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_bA0); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_bA1); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_bA2); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_casn); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_rasn); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_wen); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_PAR, &i_target_mba, attr_eff_cen_phase_rot_m_par); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_ACTN, &i_target_mba, attr_eff_cen_phase_rot_m_actn); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0, &i_target_mba, attr_eff_cen_phase_rot_m0_cntl_cke0); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1, &i_target_mba, attr_eff_cen_phase_rot_m0_cntl_cke1); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2, &i_target_mba, attr_eff_cen_phase_rot_m0_cntl_cke2); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3, &i_target_mba, attr_eff_cen_phase_rot_m0_cntl_cke3); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0, &i_target_mba, attr_eff_cen_phase_rot_m0_cntl_csn0); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1, &i_target_mba, attr_eff_cen_phase_rot_m0_cntl_csn1); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2, &i_target_mba, attr_eff_cen_phase_rot_m0_cntl_csn2); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3, &i_target_mba, attr_eff_cen_phase_rot_m0_cntl_csn3); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0, &i_target_mba, attr_eff_cen_phase_rot_m0_cntl_odt0); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1, &i_target_mba, attr_eff_cen_phase_rot_m0_cntl_odt1); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_cke0); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_cke1); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_cke2); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_cke3); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_csn0); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_csn1); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_csn2); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_csn3); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_odt0); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_odt1); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_2N_MODE_ENABLED, &i_target_mba, attr_eff_dram_2n_mode_enabled); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_RLO, &i_target_mba, attr_eff_rlo); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_WLO, &i_target_mba, attr_eff_wlo); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_GPO, &i_target_mba, attr_eff_gpo); if(rc) return rc; //Set AL to be 1 less IF 2N Mode Is Enabled - if(attr_eff_dram_2n_mode_enabled){ + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_2N_MODE_ENABLED, &i_target_mba, l_attr_vpd_2n_mode_enabled); if(rc) return rc; + + if(l_attr_vpd_2n_mode_enabled == fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_TRUE ) { FAPI_INF("Changing Additive Latency For 2N Mode\nCurrent AL IS %d\n",attr_eff_dram_al); if(attr_eff_dram_al == 1){ attr_eff_dram_al = 2; @@ -2048,8 +1145,12 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_AL, &i_target_mba, attr_eff_dram_al); if(rc) return rc; } - - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_ADDRESS_MIRRORING, &i_target_mba, attr_eff_dram_address_mirroring); if(rc) return rc; + + uint8_t l_attr_vpd_dimm_spare[2][2][4]; + + rc = FAPI_ATTR_GET(ATTR_VPD_DIMM_SPARE, &i_target_mba, l_attr_vpd_dimm_spare); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_SPARE, &i_target_mba, l_attr_vpd_dimm_spare); if(rc) return rc; + if(l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) { @@ -2061,6 +1162,7 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { } } + FAPI_INF("%s on %s COMPLETE", PROCEDURE_NAME, i_target_mba.toEcmdString()); return rc; diff --git a/src/usr/hwpf/hwp/memory_attributes.xml b/src/usr/hwpf/hwp/memory_attributes.xml index 28b1d0c9f..371538e7e 100644 --- a/src/usr/hwpf/hwp/memory_attributes.xml +++ b/src/usr/hwpf/hwp/memory_attributes.xml @@ -21,7 +21,7 @@ <!-- --> <!-- IBM_PROLOG_END_TAG --> <attributes> -<!-- $Id: memory_attributes.xml,v 1.98 2013/11/16 09:42:47 bellows Exp $ --> +<!-- $Id: memory_attributes.xml,v 1.103 2014/01/10 22:52:18 bellows Exp $ --> <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB --> <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP --> <!-- *********************************************************************** --> @@ -423,63 +423,11 @@ firmware notes: none</description> </attribute> <attribute> - <id>ATTR_EFF_ODT_RD</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Read ODT. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: VPD(MT),mss_eff_cnfg_termination -consumer: various.C files and initfiles -firmware notes: none -OBSOLETE: will use VPD attribute</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2 2 4</array> -</attribute> - -<attribute> - <id>ATTR_EFF_ODT_WR</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Write ODT. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -Creator: VPD(MT)/ mss_eff_cnfg_termination -consumer: various.C and initfile -firmware notes: none -Obsolete: will use VPD attribute</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2 2 4</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CKE_MAP</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Rank to CKE map. Used in various locations and is computed in mss_eff_cnfg_cke_map. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_cke_map consumer: various firmware notes: none - NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description> - <valueType>uint8</valueType> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2 2 4</array> -</attribute> - -<attribute> - <id>ATTR_EFF_SPCKE_MAP</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Rank to Spare CKE map. Used in various locations and is computed in mss_eff_cnfg_cke_map. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_cke_map consumer: various firmware notes: none NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description> - <valueType>uint8</valueType> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2 2 4</array> -</attribute> - -<attribute> <id>ATTR_EFF_DIMM_SPARE</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Spare DRAM availability. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg consumer: various firmware notes: load from spd</description> + <description>Spare DRAM availability. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg consumer: various firmware notes: load from spd +OBSOLETE: Use ATTR_VPD_DIMM_SPARE +</description> <valueType>uint8</valueType> <enum>NO_SPARE = 0, LOW_NIBBLE = 1, HIGH_NIBBLE = 2, FULL_BYTE = 3</enum> <writeable/> @@ -489,58 +437,6 @@ Obsolete: will use VPD attribute</description> </attribute> <attribute> - <id>ATTR_EFF_DRAM_RON</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>DRAM Ron. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -OHM48 is for DDR4. -creator: VPD(MT)/mss_eff_cnfg_termination -consumer: various.C files (no initfile) -firmware notes: none -OBSOLETE: Use VPD attribute</description> - <valueType>uint8</valueType> - <enum>OHM34 = 34, OHM40 = 40, OHM48 = 48</enum> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_DRAM_RTT_NOM</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>DRAM Rtt_Nom. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: VPD(MT),mss_eff_cnfg_termination -consumer: various.C files (no initfiles) -firmware notes: none -OBSOLETE: use VPD attribute</description> - <valueType>uint8</valueType> - <enum>DISABLE = 0, OHM20 = 20, OHM30 = 30, OHM34 = 34, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM240 = 240</enum> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2 2 4</array> -</attribute> - -<attribute> - <id>ATTR_EFF_DRAM_RTT_WR</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>DRAM Rtt_WR. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -Creator: VPD(MT), mss_eff_cnfg_termination -consumer: various.C files (no initfiles) -firmware notes: none -OBSOLETE: use VPD attribute</description> - <valueType>uint8</valueType> - <enum>DISABLE = 0, OHM60 = 60, OHM120 = 120, OHM240 = 240, HIGHZ = 1</enum> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2 2 4</array> -</attribute> - -<attribute> <id>ATTR_EFF_DRAM_WR_VREF</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> <description>DRAM Write Vref. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. @@ -559,24 +455,6 @@ This is for DDR3</description> </attribute> <attribute> - <id>ATTR_EFF_DRAM_WRDDR4_VREF</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>DRAM Write Vref. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: VPD(MT) or mss_eff_cnfg_termination -consumer: various -firmware notes: none -This is the nominal value -This is for DDR4 -The value is from 0 to 50</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> <id>ATTR_EFF_DRAM_WR_VREF_SCHMOO</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> <description>Enables for which VREF to use on the WR Schmoo. The LSB corresponds to the highest WR Vref</description> @@ -617,74 +495,6 @@ OHM30_FFE480 = 0x48, OHM30_FFE240 = 0x38, OHM30_FFE160 = 0x28, OHM30_FFE120 = 0x </attribute> <attribute> - <id>ATTR_EFF_CEN_DRV_IMP_ADDR</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Centaur Address Drive Impedance Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: mss_eff_cnfg_termination -consumer: initfile and various.C -firmware notes: none -This is the nominal value</description> - <valueType>uint8</valueType> - <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40</enum> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_DRV_IMP_CNTL</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Centaur Control Drive Impedance Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: VPD(MT)/mss_eff_cnfg_termination -consumer: initfile,various .C -firmware notes: none -This is the nominal value</description> - <valueType>uint8</valueType> - <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40</enum> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_DRV_IMP_CLK</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Centaur Clock Drive Impedance Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: VPD(MT),mss_eff_cnfg_termination -consumer: initfiles,various -firmware notes: none -This is the nominal value</description> - <valueType>uint8</valueType> - <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40</enum> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_DRV_IMP_SPCKE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Centaur Spare Clock Drive Impedance Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: VPD(MT) , mss_eff_cnfg_termination -consumer: initfiles, various.C -firmware notes: none -This is the nominal value</description> - <valueType>uint8</valueType> - <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40</enum> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> <id>ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> <description>Enables for which impedance values can be used and tested in a timing test. The bits have a one to one correspondence to the possible driver strengths and start with the first value down to the last (largest) impedance as the LSB of the 8 bit field.</description> @@ -780,92 +590,6 @@ SLEW_MAXV_NS = 7</enum> </attribute> <attribute> - <id>ATTR_EFF_CEN_SLEW_RATE_ADDR</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Centaur Address Slew Rate Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: VPD(MT),mss_eff_cnfg_termination -consumer: initfile,various .C files -firmware notes: none -This is the nominal value</description> - <valueType>uint8</valueType> - <enum>SLEW_3V_NS = 3, -SLEW_4V_NS = 4, -SLEW_5V_NS = 5, -SLEW_6V_NS = 6, -SLEW_MAXV_NS = 7</enum> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_SLEW_RATE_CLK</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Centaur Clock Slew Rate Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: VPD(MT)mss_eff_cnfg_termination -consumer: initfile,various.C files -firmware notes: none -This is the nominal value</description> - <valueType>uint8</valueType> - <enum>SLEW_3V_NS = 3, -SLEW_4V_NS = 4, -SLEW_5V_NS = 5, -SLEW_6V_NS = 6, -SLEW_MAXV_NS = 7</enum> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_SLEW_RATE_SPCKE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Centaur Spare Clock Slew Rate Used in various locations and comes from the MT keyword or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: VPD(MT) or mss_eff_cnfg_termination -consumer: initfile,various.C -firmware notes: none -This is the nominal value</description> - <valueType>uint8</valueType> - <enum>SLEW_3V_NS = 3, -SLEW_4V_NS = 4, -SLEW_5V_NS = 5, -SLEW_6V_NS = 6, -SLEW_MAXV_NS = 7 -</enum> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_SLEW_RATE_CNTL</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Centaur Control Slew Rate Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: VPD(MT),mss_eff_cnfg_termination -consumer:initfile, various .C files -firmware notes: none -This is the nominal value</description> - <valueType>uint8</valueType> - <enum>SLEW_3V_NS = 3, -SLEW_4V_NS = 4, -SLEW_5V_NS = 5, -SLEW_6V_NS = 6, -SLEW_MAXV_NS = 7 -</enum> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> <id>ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> <description>Slew Rates that can be selected during timing adjustments. The fastest rate is the LSB</description> @@ -1749,18 +1473,6 @@ firmware notes: none</description> </attribute> <attribute> - <id>ATTR_MSS_CHANNEL_MAXBANDWIDTH_GBS</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Channel Max Bandwidth in GBs output from thermal procedures</description> - <valueType>uint32</valueType> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> - <persistRuntime/> -</attribute> - -<attribute> <id>ATTR_MSS_CHANNEL_PAIR_MAXBANDWIDTH_GBS</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> <description>Channel Pair Max Bandwidth in GBs output from thermal procedures</description> @@ -1772,18 +1484,6 @@ firmware notes: none</description> </attribute> <attribute> - <id>ATTR_MSS_CHANNEL_MAXBANDWIDTH_MRS</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Channel Max Bandwidth MRs output from thermal procedures</description> - <valueType>uint32</valueType> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> - <persistRuntime/> -</attribute> - -<attribute> <id>ATTR_MSS_CHANNEL_PAIR_MAXBANDWIDTH_MRS</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> <description>Channel Pair Max Bandwidth MRs output from thermal procedures</description> @@ -1807,18 +1507,6 @@ firmware notes: none</description> </attribute> <attribute> - <id>ATTR_MSS_CHANNEL_MAXPOWER</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Channel Max Power output from thermal procedures</description> - <valueType>uint32</valueType> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> - <persistRuntime/> -</attribute> - -<attribute> <id>ATTR_MSS_CHANNEL_PAIR_MAXPOWER</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> <description>Channel Pair Max Power output from thermal procedures</description> @@ -1914,23 +1602,58 @@ firmware notes: none</description> <attribute> <id>ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT</id> <targetType>TARGET_TYPE_SYSTEM</targetType> - <description>This dial sets the Centaur address bits used to interleave addresses between MBA01 and MBA23. Valid values are 23 through 32. See Centaur Spec Chapter 5 for details. Used in the intifile </description> + <description>This dial sets the Centaur address bits used to interleave addresses between MBA01 and MBA23. Valid values are 23 through 32. See Centaur Spec Chapter 5 for details. Used in the intifile. Will be obsolete when the MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT is set</description> <valueType>uint8</valueType> <platInit/> <odmVisable/> <odmChangeable/> </attribute> +<!-- TODO: RTC 82331 - Add this attribute to the Accessor HWP +<attribute> + <id>ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>This dial sets the Centaur address bits used to interleave addresses between MBA01 and MBA23. Valid values are 23 through 32. See Centaur Spec Chapter 5 for details. Used in the intifile </description> + <valueType>uint8</valueType> + <odmVisable/> + <odmChangeable/> + <writeable/> +</attribute> +--> <attribute> <id>ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE</id> <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Value of on or off. On is 256 bit interleave. Off, the translation is on 128 bit interleave mode. See centaur workbook chapter 5. Will be obsolete when MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE is set</description> + <valueType>uint8</valueType> + <enum>OFF = 0, ON = 1</enum> + <platInit/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<!-- TODO: RTC 82331 - Add this attribute to the Accessor HWP +<attribute> + <id>ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> <description>Value of on or off. On is 256 bit interleave. Off, the translation is on 128 bit interleave mode. See centaur workbook chapter 5.</description> <valueType>uint8</valueType> <enum>OFF = 0, ON = 1</enum> + <odmVisable/> + <odmChangeable/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>At a system level, this attribute controls if interleaving is required, requested or never. The MRW.</description> + <valueType>uint8</valueType> + <enum>NEVER = 0, REQUIRED = 1, REQUESTED = 2</enum> <platInit/> <odmVisable/> <odmChangeable/> </attribute> +--> <attribute> <id>ATTR_MSS_CACHE_ENABLE</id> @@ -2531,582 +2254,6 @@ Firmware shares some code with the processor, so the attribute is named so they </attribute> <attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CLK_P0</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CLK_P1</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CLK_P0</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CLK_P1</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A0</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A1</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A2</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A3</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A4</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A5</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A6</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A7</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A8</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A9</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A10</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A11</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A12</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A13</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A14</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A15</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_BA0</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_BA1</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_BA2</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_CASN</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_RASN</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_WEN</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_PAR</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_PAR</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M_ACTN</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_ACTN</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CKE0</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CKE1</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CKE2</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CKE3</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CSN0</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CSN1</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CSN2</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CSN3</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_ODT0</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_ODT1</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CKE0</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CKE1</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CKE2</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CKE3</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CSN0</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CSN1</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CSN2</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CSN3</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_ODT0</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_ODT1</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> <id>ATTR_MSS_DQS_SWIZZLE_TYPE</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> <description>DQS Swizzle type is set by the platform to describe what kind of DQS connection is being used for register acceses. Type 0 is normal, type 1 is for systems with wiring like glacier 1. Additional types maybe defined if new boards have even different DQS swizzle features</description> @@ -3118,16 +2265,6 @@ Firmware shares some code with the processor, so the attribute is named so they </attribute> <attribute> - <id>ATTR_MSS_ZSERIES</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description>Determines if the code is Zseries type or P Series. The platform determines this and this attribute is mostly used in the initfiles so that we can share the same initialization code with the zSeries team</description> - <valueType>uint8</valueType> - <enum>FALSE = 0, TRUE = 1</enum> - <platInit/> - <odmVisable/> -</attribute> - -<attribute> <id>ATTR_MSS_PSRO</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> <description>Set by the centaur mss_get_cen_ecid function used diagnostic and chip characterization reporting</description> @@ -3147,118 +2284,6 @@ Firmware shares some code with the processor, so the attribute is named so they </attribute> <attribute> - <id>ATTR_EFF_DRAM_2N_MODE_ENABLED</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Describes if this MBA is in 2N address mode. The DIMM attributes associated with this MBA describes if this mode is needed for SI. The MR Keyword of the VPD gives and indication of the value needed. Set by eff_config and consumed in the mba_def.initfile.</description> - <valueType>uint8</valueType> - <enum>FALSE = 0, TRUE = 1</enum> - <writeable/> - <odmVisable/> - <odmChangeable/> -</attribute> - -<attribute> - <id>ATTR_MSS_DIMM_POWER_TEST_REV</id> - <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> - <description>The power test revision number that is saved when data is saved on an ISDIMM. If the power test changes, then a difference indicates that the power test needs to be rerun. This attribute needs to stick around between IPLs</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <persistent/> -</attribute> - -<attribute> - <id>ATTR_CDIMM_SENSOR_MAP_PRIMARY</id> - <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> - <description>Custom DIMM Sensor Map for Primary I2C Port (1 byte of data): -0x00 No sensors attached -0x01 DIMM sensor 0 attached -0x02 DIMM sensor 1 attached -0x04 DIMM sensor 2 attached -0x08 DIMM sensor 3 attached -0x10 DIMM sensor 4 attached -0x20 DIMM sensor 5 attached -0x40 DIMM sensor 6 attached -0x80 DIMM sensor 7 attached -Comes from the VPD MW Keyword</description> - <valueType>uint8</valueType> - <platInit/> - <odmVisable/> -</attribute> - -<attribute> - <id>ATTR_CDIMM_SENSOR_MAP_SECONDARY</id> - <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> - <description>Custom DIMM Sensor Map for Secondary I2C Port (1 byte of data): -0x00 No sensors attached -0x01 DIMM sensor 0 attached -0x02 DIMM sensor 1 attached -0x04 DIMM sensor 2 attached -0x08 DIMM sensor 3 attached -0x10 DIMM sensor 4 attached -0x20 DIMM sensor 5 attached -0x40 DIMM sensor 6 attached -0x80 DIMM sensor 7 attached -Comes from the VPD MW Keyword</description> - <valueType>uint8</valueType> - <platInit/> - <odmVisable/> -</attribute> - -<attribute> - <id>ATTR_CDIMM_VPD_MASTER_POWER_SLOPE</id> - <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> - <description>Master Power Slope that comes from the VPD MW Keyword</description> - <valueType>uint32</valueType> - <platInit/> - <odmVisable/> - <persistRuntime/> -</attribute> - -<attribute> - <id>ATTR_CDIMM_VPD_MASTER_POWER_INTERCEPT</id> - <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> - <description>Master Power Intercept that comes from the VPD MW Keyword</description> - <valueType>uint32</valueType> - <platInit/> - <odmVisable/> - <persistRuntime/> -</attribute> - -<attribute> - <id>ATTR_CDIMM_VPD_SUPPLIER_POWER_SLOPE</id> - <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> - <description>Supplier Power Slope that comes from the VPD the MV Keyword</description> - <valueType>uint32</valueType> - <platInit/> - <odmVisable/> - <persistRuntime/> -</attribute> - -<attribute> - <id>ATTR_CDIMM_VPD_SUPPLIER_POWER_INTERCEPT</id> - <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> - <description>Supplier Power Intercept that comes from MV Keyword</description> - <valueType>uint32</valueType> - <platInit/> - <odmVisable/> - <persistRuntime/> -</attribute> - -<attribute> - <id>ATTR_EFF_DRAM_ADDRESS_MIRRORING</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Address mirroring on the DIMM by rank, up to 4 ranks. The bits meanings is 0x08 is rank 0 is mirrored, 0x04 rank 1 is mirrored, 0x02 rank 2 and 0x01 rank 3 is mirrored. Comes from EFF config reading the VPD_DRAM_ADDRESS_MIRRORING from the AM keyword of the VPD.</description> - <valueType>uint8</valueType> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2 2</array> -</attribute> - -<attribute> <id>ATTR_MSS_BLUEWATERFALL_BROKEN</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> <description>Set by the platform depending on DD1.0X vs DD1.03 or newer. If true, then draminit_train will modify dqs_clk_ps and gate to work around the issue. Set in get ecid which determines if we are at 1.03</description> @@ -3340,52 +2365,6 @@ Comes from the VPD MW Keyword</description> </attribute> <attribute> - <id>ATTR_EFF_RLO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>This value comes from looking at the ATTR_VPD_RLO attribute associated with the DIMMs off the port. Computed in eff_config. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_CKE_PRI_MAP</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Contains the CKE MAP for the DIMM being plugged in. The source of the data comes from the the ATTR_CKE_PRI_MAP attributes where 16 bits associated with port A data and 16 bits with B. This value goes directly into the MBA01 Rank-to-primary-CKE mapping table register bits 0:31 (MBA01_MBAREF1Q) register. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description> - <valueType>uint32</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> -</attribute> - -<attribute> - <id>ATTR_EFF_CKE_PWR_MAP</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Contains the CKE Power Domain mapping tables for the DIMM being plugged in. The source of the data are the ATTR_VPD_CKE_PWR_MAP with 32 bits coming from the attribute associated with port A data and 32 bits with B. This value goes directly into the MBA01 Rank-to-CKE power domain mapping table bits 0:33 (MBA01_MBARPC1Q) register. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description> - <valueType>uint64</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> -</attribute> - -<attribute> - <id>ATTR_EFF_GPO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Global Phy Offset value that is used in setting up the phy. This value is dervived from the VPD_GPO attribute. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> <id>ATTR_EFF_RDTAG</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> <description>Read Tag value that is used in setting up the phy. It is expected that this value will come from the VPD. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description> @@ -3397,40 +2376,6 @@ Comes from the VPD MW Keyword</description> </attribute> <attribute> - <id>ATTR_EFF_WLO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>This value comes from looking at the ATTR_VPD_WLO attribute associated with the DIMMs off the port. Computed in eff_config. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> - <id>ATTR_EFF_TSYS_ADR</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>TSYS for all address blocks in the MBA pair. This value comes from ATTR_VPD_TSYS_ADR of the assoicated DIMMs. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> -</attribute> - -<attribute> - <id>ATTR_EFF_TSYS_DP18</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>TSYS for all DP18 blocks in the MBA pair. This value comes from ATTR_VPD_TSYS_DP18 from the associated DIMMs. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description> - <valueType>uint8</valueType> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> -</attribute> - -<attribute> <id>ATTR_EFF_DQ_WR_OFFSET</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> <description>DQ write offset value that is used in setting up the phy's phase rotators before WR_LVL, 0x40 is HW Default. It is expected that this value will come from the VPD</description> @@ -3492,18 +2437,6 @@ Will be set at an MBA level with one policy to be used</description> </attribute> <attribute> - <id>ATTR_L4_BANK_DELETE_VPD</id> - <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> - <description>L4 Bank Delete settings in VPD. -Denotes what banks have been deleted from the L4. -Data will be pulled from CDIMM VPD if CDIMM present. -Data will be pulled from backplane VPD if IS DIMMs present.</description> - <valueType>uint32</valueType> - <writeable/> - <persistent/> -</attribute> - -<attribute> <id>ATTR_MSS_DIMM_POWER_TEST_MEM_THROTTLE_NUMERATOR_PER_MBA</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> <description>runtime memory throttle values adjusted by the dimm power test @@ -3539,19 +2472,6 @@ DIMM power test memory throttles for cfg_nm_m</description> <persistent/> </attribute> -<!-- TODO: RTC 82331 - Add this attribute to the Accessor HWP -<attribute> - <id>ATTR_MSS_DRAM_ACTIVATE_POWER_PERCENT</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>DRAM Activation power percentage to determine the ras and cas weights for throttle controls -will originates from VPD for custom DIMMs in the MW keyword byte 5 (MSB is on the left(big endian)) -</description> - <valueType>uint8</valueType> - <platInit/> - <odmVisable/> -</attribute> ---> - <attribute> <id>ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> @@ -3572,148 +2492,128 @@ will originates from VPD for custom DIMMs in the MW keyword byte 5 (MSB is on th <odmChangeable/> </attribute> -<!-- TODO: Mark Bellows is to remove these obsoleted attributes <attribute> - <id>ATTR_VPD_MT_CKE_PRI_MAP</id> + <id>ATTR_MCBIST_RANDOM_SEED_VALUE</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>OBSOLETE - See ATTR_VPD_CKE_PRI_MAP</description> + <description>Controls the MCBIST engine in the centaur chip. The value will be set in mss_eff_config_shmoo.</description> <valueType>uint32</valueType> - <platInit/> + <writeable/> <odmVisable/> - <array>2</array> + <odmChangeable/> </attribute> <attribute> - <id>ATTR_VPD_MT_CKE_PWR_MAP</id> + <id>ATTR_MCBIST_RANDOM_SEED_TYPE</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>OBSOLETE - See ATTR_VPD_CKE_PWR_MAP</description> - <valueType>uint32</valueType> - <platInit/> + <description>Controls the MCBIST engine in the centaur chip. The value will be set in mss_eff_config_shmoo.</description> + <valueType>uint8</valueType> + <writeable/> <odmVisable/> - <array>2</array> + <odmChangeable/> </attribute> <attribute> - <id>ATTR_VPD_MR_GPO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>OBSOLETE - see ATTR_VPD_GPO</description> + <id>ATTR_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Machine Readable Workbook DIMM power curve percent uplift for this system</description> <valueType>uint8</valueType> <platInit/> <odmVisable/> - <array>2</array> + <persistRuntime/> </attribute> <attribute> - <id>ATTR_VPD_MR_RLO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>OBSOLETE - see ATTR_VPD_RLO</description> - <valueType>uint8</valueType> + <id>ATTR_MRW_MEM_THROTTLE_DENOMINATOR</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Machine Readable Workbook throttle value for denominator cfg_nm_m</description> + <valueType>uint32</valueType> <platInit/> <odmVisable/> - <array>2</array> + <persistRuntime/> </attribute> <attribute> - <id>ATTR_VPD_MR_WLO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>OBSOLETE - see ATTR_VPD_WLO</description> + <id>ATTR_MSS_INIT_STATE</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>How far into the ipl istep the centaur has been brought up</description> + <enum>COLD = 0, CLOCKS_ON = 1, DMI_ACTIVE = 2</enum> <valueType>uint8</valueType> - <platInit/> + <writeable/> <odmVisable/> - <array>2</array> + <odmChangeable/> </attribute> <attribute> - <id>ATTR_VPD_MR_TSYS_ADR</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>OBSOLETE see ATTR_VPD_TSYS_ADR</description> - <valueType>uint8</valueType> + <id>ATTR_MRW_MAX_DRAM_DATABUS_UTIL</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Machine Readable Workbook value for maximum dram data bus utilization in centi percent (c%). Used to determine memory throttle values.</description> + <valueType>uint32</valueType> <platInit/> <odmVisable/> - <array>2</array> + <persistRuntime/> </attribute> +<!-- TODO: RTC 82331 - Add this attribute to the Accessor HWP <attribute> - <id>ATTR_VPD_MR_TSYS_DP18</id> + <id>ATTR_MSS_DRAM_ACTIVATE_POWER_PERCENT</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>OBSOLETE see ATTR_VPD_TSYS_DP18</description> + <description>DRAM Activation power percentage to determine the ras and cas weights for throttle controls +</description> <valueType>uint8</valueType> - <platInit/> + <writeable/> <odmVisable/> - <array>2</array> + <odmChangeable/> </attribute> --> <attribute> - <id>ATTR_LAB_USE_JTAG_MODE</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description>This attribute controls how the procedures operate in JTAG mode under an environment called cronus flex. For normal operation, this attribute should be set to FALSE. Platforms should initialize this attribute to FALSE.</description> - <valueType>uint8</valueType> - <enum>FALSE =0, TRUE = 1</enum> - <platInit/> - <odmVisable/> -</attribute> - -<attribute> - <id>ATTR_MCBIST_RANDOM_SEED_VALUE</id> + <id>ATTR_MSS_EFF_VPD_VERSION</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Controls the MCBIST engine in the centaur chip. The value will be set in mss_eff_config_shmoo.</description> + <description> + The lowest VPD Version of the DIMMs attached to the MBA. Comes directly (in ASCII) of the VINI VZ keyword + </description> <valueType>uint32</valueType> <writeable/> <odmVisable/> <odmChangeable/> </attribute> +<!-- TODO: RTC 82331 - Add this attribute to the Accessor HWP <attribute> - <id>ATTR_MCBIST_RANDOM_SEED_TYPE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Controls the MCBIST engine in the centaur chip. The value will be set in mss_eff_config_shmoo.</description> + <id>ATTR_MSS_NEST_CAPABLE_FREQUENCIES</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description> + The NEST frequencies the memory chip can run at computed by the mss_freq. The possibilities are ORed together. The platform uses these value and the MRW to determine what frequency to boot the fabric (nest) if it can. There are two values: 8G and 9.6G + </description> <valueType>uint8</valueType> <writeable/> <odmVisable/> <odmChangeable/> -</attribute> + <enum>8_0G = 1, 9_6G = 2</enum> +</attribute> <attribute> - <id>ATTR_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description>Machine Readable Workbook DIMM power curve percent uplift for this system</description> + <id>ATTR_MRW_NEST_FREQUENCIES</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description> + The allowable NEST frequencies the memory chip can run at for this system. The value comes from MRW. + </description> <valueType>uint8</valueType> <platInit/> - <odmVisable/> - <persistRuntime/> -</attribute> + <enum>8_0G = 1, 9_6G = 2</enum> +</attribute> <attribute> - <id>ATTR_MRW_MEM_THROTTLE_DENOMINATOR</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description>Machine Readable Workbook throttle value for denominator cfg_nm_m</description> - <valueType>uint32</valueType> - <platInit/> - <odmVisable/> - <persistRuntime/> -</attribute> - -<attribute> - <id>ATTR_MRW_MAX_DRAM_DATABUS_UTIL</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description>Machine Readable Workbook value for maximum dram data bus utilization in centi percent (c%). Used to determine memory throttle values.</description> - <valueType>uint32</valueType> - <platInit/> - <odmVisable/> - <persistRuntime/> -</attribute> - -<attribute> - <id>ATTR_MSS_INIT_STATE</id> + <id>ATTR_MRW_STRICT_MBA_PLUG_RULE_CHECKING</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> - <description>How far into the ipl istep the centaur has been brought up</description> - <enum>COLD = 0, CLOCKS_ON = 1, DMI_ACTIVE = 2</enum> + <description> + The MRW for a system should set this to TRUE for systems that must obey plug rules. Lab environments should default this to off and allow the user to override using normal methods to test. + </description> <valueType>uint8</valueType> - <writeable/> - <odmVisable/> - <odmChangeable/> -</attribute> + <platInit/> + <enum>FALSE = 0, TRUE = 1</enum> +</attribute> +--> <!-- This attribute was added for defect SW244656, while the eKB version is waiting to be merged --> <attribute> @@ -3724,7 +2624,7 @@ will originates from VPD for custom DIMMs in the MW keyword byte 5 (MSB is on th <enum>OFF = 0, ON = 1</enum> <platInit/> <odmVisable/> - </attribute> +</attribute> <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB --> <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP --> diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index 811f228df..c0bbe00db 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -13088,4 +13088,21 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </hwpfToHbAttrMap> </attribute> +<attribute> + <id>MSS_EFF_VPD_VERSION</id> + <description> + The lowest VPD Version of the DIMMs attached to the MBA. Comes directly (in ASCII) of the VINI VZ keyword + </description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_EFF_VPD_VERSION</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + </attributes> diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index f5f373433..63a6d6a15 100644 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -27,6 +27,7 @@ HOST BOOT TARGETS Contains the definition of the different types of targets ================================================================= --> + <targetType> <id>base</id> <attribute><id>CLASS</id></attribute> @@ -1076,6 +1077,7 @@ <attribute><id>MCBIST_RANDOM_SEED_TYPE</id></attribute> <attribute><id>MSS_DATABUS_UTIL_PER_MBA</id></attribute> <attribute><id>MSS_UTIL_N_PER_MBA</id></attribute> + <attribute><id>MSS_EFF_VPD_VERSION</id></attribute> </targetType> <targetType> |
