diff options
13 files changed, 449 insertions, 76 deletions
diff --git a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C index 0364da1ef..d69048b71 100644 --- a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C +++ b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C @@ -222,11 +222,14 @@ fapi_try_exit: // void* i_ringSection: Ptr to ring section. // uint32_t& io_ringSectionSize: Running ring section size // uint32_t i_maxRingSectionSize: Max ring section size +// void* i_overlaysSection: Overlays ring section // uint8_t i_sysPhase: ={HB_SBE, RT_CME, RT_SGPE} // void* i_vpdRing: VPD ring buffer. // uint32_t i_vpdRingSize: Size of VPD ring buffer. // void* i_ringBuf2: Ring work buffer. // uint32_t i_ringBufSize2: Size of ring work buffer. +// void* i_ringBuf3: Ring work buffer. +// uint32_t i_ringBufSize3: Size of ring work buffer. // uint8_t i_chipletId: Chiplet Id // uint8_t i_evenOdd: Even/Odd for EX instances // const RingIdList i_ring: The ring ID list (#G or #R list) @@ -244,11 +247,14 @@ fapi2::ReturnCode _fetch_and_insert_vpd_rings( void* i_ringSection, uint32_t& io_ringSectionSize, uint32_t i_maxRingSectionSize, + void* i_overlaysSection, uint8_t i_sysPhase, void* i_vpdRing, uint32_t i_vpdRingSize, void* i_ringBuf2, uint32_t i_ringBufSize2, + void* i_ringBuf3, + uint32_t i_ringBufSize3, uint8_t i_chipletId, uint8_t i_evenOdd, const RingIdList i_ring, @@ -299,8 +305,51 @@ fapi2::ReturnCode _fetch_and_insert_vpd_rings( (uint8_t*)i_vpdRing, l_vpdRingSize ); +#if 0 //@TODO RTC174306 stage 2 + + /////////////////////////////////////////////////////////////////////// + // Fetch overlay ring /////////////////////////////////////////////////////////////////////// - //Append VPD ring to the ring section + if ring is CLASS_GPTR then + l_fapiRc = get_overlays_ring( // Create this FAPI function like resolve_gptr_overlays() + i_overlaysSection, // and which will do the following + i_ring.ringId, // 1. look for ringId in i_overlaysSection using + i_ringBuf2, // tor_get_single_ring(), + i_ringBuf3 ); // 2. copy compressed ring into io_ringBuf2, + + // 3. uncompress ring into io_ringBuf3, + // 4. return io_ringBuf2 into i_ringBuf2, and + // 5. return io_ringBuf3 into i_ringBuf3. + // NB! Above io_ringBufs are local to get_overlays_ring. + // So now you got both the compressed and the uncompressed versions of the + // overlay ring ready in i_ringBuf2 and i_ringBuf3. + // Whether you find a #G GPTR ring or not in the Mvpd, you must apply the overlays + // ring in i_ringBuf2 or in i_ringBuf3 to i_vpdRing as follows. There are three + // cases: + // a. You found a ring in Mvpd. In this case you'll need i_ringBuf3 only. Here + // you'll uncompress i_vpdRing into i_ringBuf2 and do an overlays (OO) operation + // between i_ringBuf2 and i_ringBuf3 as shown further below and then compress + // the result into i_vpdRing. + // b. You found a redundant ring in Mvpd. In this case you'll need i_ringBuf2 + // only. Here you'll simply copy i_ringBuf2 into i_vpdRing. No need to + // uncompress i_vpdRing. Also, you don't need the care part of the overlays + // ring. + // c. You didn't find a ring in Mvpd, but you did find one in overlays. This + // scenario, I believe, is illegal. Please verify with Mike Sgro. But if it + // is a possibility, treat like case b. +if case a above then + l_fapiRc = apply_overlays_ring( // Create a FAPI function to do this and which + i_ringVpd, // 1. uncompresses i_ringVpd into i_ringBuf2, + i_ringBuf2, // 2. does the overlays operation (OO), + i_ringBuf3 ); // 3. compresses the result into io_ringVpd, and + // 4. returns io_ringVpd into i_ringVpd. + // You'll have to pu this latter call strategically later after some of the below + // error checks, I think. + // NB! The overlays operation AND how to handle the data and care parts have been + // sent in an email. +#endif + /////////////////////////////////////////////////////////////////////// + // Append VPD ring to the ring section /////////////////////////////////////////////////////////////////////// if (l_fapiRc == fapi2::FAPI2_RC_SUCCESS) @@ -578,6 +627,109 @@ fapi_try_exit: +// Function: resolve_gptr_overlays() +// +// Parameter list: +// const fapi::Target &i_target: Processor chip target. +// void* i_hwImage: Ptr to ring section. +// void** o_overlaysSection: Ptr to extracted DD section in hwImage. +// bool& o_bGptrMvpdSupport: Boolean art indicating whether Gptr support or not. +#ifdef WIN32 +int resolve_gptr_overlays( + int i_procTarget, +#else +fapi2::ReturnCode resolve_gptr_overlays( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_procTarget, +#endif + void* i_hwImage, + void** o_overlaysSection, + bool& o_bGptrMvpdSupport ) +{ + + fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; + int l_rc = 0; + uint8_t l_nimbusDd1 = 1; + bool l_bDdSupport = false; + + FAPI_DBG("Entering resolve_gptr_overlays"); + + //------------------------------ + // Stage 1 & 2 (shared section) + //------------------------------ + // Determine if there is GPTR support through MVPD which there will NOT be if + // - Nimbus DD1, and + // - XIP DD section does not support overlays + + // First determine if we're on Nimbus < DD20. If we are, continue, else err out. + FAPI_TRY( FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_NO_GPTR_SUPPORT_VIA_MVPD, + i_procTarget, + l_nimbusDd1), + "FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_HAS_GPTR_SUPPORT_VIA_MVPD) failed w/rc=0x%08x", + (uint64_t)current_err ); + + // Second determine if there's no overlays support. If no, continue, else err out. + l_rc = p9_xip_dd_section_support(i_hwImage, P9_XIP_SECTION_HW_OVERLAYS, l_bDdSupport); + + FAPI_ASSERT( l_rc == 0, + fapi2::XIPC_XIP_API_MISC_ERROR(). + set_CHIP_TARGET(i_procTarget). + set_XIP_RC(l_rc). + set_OCCURRENCE(10), + "xip_dd_section_support() failed w/rc=0x%08x.\n", + (uint32_t)l_rc ); + + // Now do the checks of the above return vars, l_nimbusDd1, l_bDdSupport and l_rc. + if ( l_nimbusDd1 ) + { + o_bGptrMvpdSupport = false; + FAPI_DBG("There's no Mvpd-GPTR support in Nimbus DD1."); + } + else if ( !l_bDdSupport ) + { + o_bGptrMvpdSupport = false; + FAPI_DBG("The image has no DD support in overlays, thus there's no Mvpd-GPTR support either. (This is probably an old image w/Gptr but with new Mvpd-GPTR code and Nimbus DD2.)"); + } + else + { +#if 0 + + //-------------------------------- + // Stage 2 (suggested pseudo steps) + // @TODO RTC174306 + // Assumes commit 40046 + //-------------------------------- + if (bDdSupport) + { + <extract_ddLlevel_via_attr_svc>(<attr>, <target>, l_ddLevel) // see how elsewhere in this file + p9_xip_get_section((i_hwImage, P9_XIP_SECTION_OVERLAYS, l_xipSection, l_ddLevel); + } + else + { + // Get the whole overlays section since there's no DD specific levels yet. + // (Temporary only to test early overlays support before Jamie has + // the DD packaging all down right. At least you can still test how + // to apply the overlays rings onto the Gptr rings. After Jamie's got + // the DD assembly going, error out here instead.) + p9_xip_get_section((i_hwImage, P9_XIP_SECTION_OVERLAYS, l_xipSection); + } + + *o_overlaysSection = (void*)((uint8_t*)i_hwImage + l_xipSection.iv_offset); +#endif + + o_bGptrMvpdSupport = true; + } + + P9XipSection l_xipSection; + *o_overlaysSection = (void*)((uint8_t*)i_hwImage + l_xipSection.iv_offset); + +fapi_try_exit: + FAPI_DBG("Exiting resolve_gptr_overlays"); + return fapi2::current_err; + +} + + + // Function: fetch_and_insert_vpd_rings() // // Parameter list: @@ -585,11 +737,14 @@ fapi_try_exit: // void* i_ringSection: Ptr to ring section. // uint32_t& io_ringSectionSize: Running size // uint32_t i_maxRingSectionSize: Max size +// void* i_hwImage: HW image // uint8_t i_sysPhase: ={IPL, RT_CME, RT_SGPE} // void* i_vpdRing: VPD ring buffer. // uint32_t i_vpdRingSize: Size of VPD ring buffer. // void* i_ringBuf2: Ring work buffer. // uint32_t i_ringBufSize2: Size of ring work buffer. +// void* i_ringBuf3: Ring work buffer. +// uint32_t i_ringBufSize3: Size of ring work buffer. // uint32_t& io_bootCoreMask: Desired (in) and actual (out) boot cores. // #ifdef WIN32 @@ -602,11 +757,14 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings( void* i_ringSection, uint32_t& io_ringSectionSize, // Running size uint32_t i_maxRingSectionSize, // Max size + void* i_hwImage, uint8_t i_sysPhase, void* i_vpdRing, uint32_t i_vpdRingSize, void* i_ringBuf2, uint32_t i_ringBufSize2, + void* i_ringBuf3, + uint32_t i_ringBufSize3, uint32_t& io_bootCoreMask ) { @@ -618,14 +776,25 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings( uint8_t l_ringStatusInMvpd = RING_SCAN; bool l_bImgOutOfSpace = false; uint8_t l_eqNumWhenOutOfSpace = 0xF; // Assign invalid value to check for correctness of value when used - uint8_t l_ringType; + uint8_t l_ringType = RING_TYPES::COMMON_RING; // Initialize activeCoreMask to be filled up with EC column filling as it progresses uint32_t l_activeCoreMask = 0x0; uint32_t l_bootCoreMaskMin = 0x0; + void* l_overlaysSection; + bool bGptrMvpdSupport = false; + FAPI_DBG("Entering fetch_and_insert_vpd_rings"); + FAPI_TRY( resolve_gptr_overlays( i_procTarget, + i_hwImage, + &l_overlaysSection, + bGptrMvpdSupport ), + "resolve_gptr_overlays() failed w/rc=0x%08x", + (uint32_t)current_err ); + + // Walk through all Vpd rings and add any that's there to the image. // Do this in two steps: // 1- Add all NEST rings @@ -645,11 +814,14 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings( for (size_t iRing = 0; iRing < l_ringIdListSize; iRing++) { - // Filter out GPTR requests. Not supported in DD1. Coming in through initfiles instead. - if (l_ringIdList[iRing].vpdRingClass != VPD_RING_CLASS_EQ_INS && - l_ringIdList[iRing].vpdRingClass != VPD_RING_CLASS_EX_INS && - l_ringIdList[iRing].vpdRingClass != VPD_RING_CLASS_EC_INS && - l_ringIdList[iRing].vpdRingClass != VPD_RING_CLASS_GPTR) + if ( l_ringIdList[iRing].vpdRingClass != VPD_RING_CLASS_EQ_INS && + l_ringIdList[iRing].vpdRingClass != VPD_RING_CLASS_EX_INS && + l_ringIdList[iRing].vpdRingClass != VPD_RING_CLASS_EC_INS && + //@FIXME Remove the next three checks in a cleanup commit after + // stage 2 (RTC174306) has merged and stabilized. + ( l_ringIdList[iRing].vpdRingClass != VPD_RING_CLASS_GPTR || + ( l_ringIdList[iRing].vpdRingClass == VPD_RING_CLASS_GPTR && + bGptrMvpdSupport ) ) ) { // We use ring.instanceIdMax column to govern max value of instanceIdMax (i.e., the // max chipletId). But unlike in P8, in P9 we will not search for chipletId=0xff in P9 @@ -679,21 +851,25 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings( (l_ringIdList[iRing].vpdRingClass == VPD_RING_CLASS_EX || l_ringIdList[iRing].vpdRingClass == VPD_RING_CLASS_EQ)) ) { - l_fapiRc = _fetch_and_insert_vpd_rings ( i_procTarget, - i_ringSection, - io_ringSectionSize, - i_maxRingSectionSize, - i_sysPhase, - i_vpdRing, - i_vpdRingSize, - i_ringBuf2, - i_ringBufSize2, - l_chipletId, - l_evenOdd, - l_ringIdList[iRing], - l_ringStatusInMvpd, - l_bImgOutOfSpace, - io_bootCoreMask ); + l_fapiRc = _fetch_and_insert_vpd_rings ( + i_procTarget, + i_ringSection, + io_ringSectionSize, + i_maxRingSectionSize, + l_overlaysSection, + i_sysPhase, + i_vpdRing, + i_vpdRingSize, + i_ringBuf2, + i_ringBufSize2, + i_ringBuf3, + i_ringBufSize3, + l_chipletId, + l_evenOdd, + l_ringIdList[iRing], + l_ringStatusInMvpd, + l_bImgOutOfSpace, + io_bootCoreMask ); if ( (uint32_t)l_fapiRc == RC_XIPC_IMAGE_WOULD_OVERFLOW || ( (uint32_t)l_fapiRc != RC_MVPD_RING_REDUNDANT_DATA && @@ -786,11 +962,14 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings( i_ringSection, io_ringSectionSize, i_maxRingSectionSize, + l_overlaysSection, i_sysPhase, i_vpdRing, i_vpdRingSize, i_ringBuf2, i_ringBufSize2, + i_ringBuf3, + i_ringBufSize3, l_chipletId, l_evenOdd, l_ringEQ, @@ -891,11 +1070,14 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings( i_ringSection, io_ringSectionSize, i_maxRingSectionSize, + l_overlaysSection, i_sysPhase, i_vpdRing, i_vpdRingSize, i_ringBuf2, i_ringBufSize2, + i_ringBuf3, + i_ringBufSize3, l_chipletId, l_evenOdd, l_ringEX[inst], @@ -972,11 +1154,14 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings( i_ringSection, io_ringSectionSize, i_maxRingSectionSize, + l_overlaysSection, i_sysPhase, i_vpdRing, i_vpdRingSize, i_ringBuf2, i_ringBufSize2, + i_ringBuf3, + i_ringBufSize3, l_chipletId, l_evenOdd, l_ringEC, @@ -1286,16 +1471,19 @@ fapi2::ReturnCode p9_xip_customize ( ReturnCode p9_xip_customize ( int& i_procTarget, #endif + void* i_hwImage, void* io_image, uint32_t& io_imageSize, // In: Max, Out: Actual void* io_ringSectionBuf, uint32_t& io_ringSectionBufSize, // In: Max, Out: Actual uint8_t i_sysPhase, uint8_t i_modeBuild, - void* io_ringBuf1, + void* i_ringBuf1, uint32_t i_ringBufSize1, - void* io_ringBuf2, + void* i_ringBuf2, uint32_t i_ringBufSize2, + void* i_ringBuf3, + uint32_t i_ringBufSize3, uint32_t& io_bootCoreMask ) // Bits(8:31) = EC00:EC23 { #ifndef WIN32 @@ -1306,7 +1494,7 @@ ReturnCode p9_xip_customize ( ReturnCode l_fapiRc = fapi2::FAPI2_RC_SUCCESS; ReturnCode l_fapiRc2 = fapi2::FAPI2_RC_SUCCESS; #endif - int l_rc = 0; // Non-fapi RC + int l_rc = 0; // Non-fapi RC P9XipSection l_xipRingsSection; uint32_t l_inputImageSize; @@ -1335,25 +1523,33 @@ ReturnCode p9_xip_customize ( // - more buffer size checks in big switch() //------------------------------------------- - FAPI_ASSERT( io_image != NULL && + FAPI_ASSERT( i_hwImage != NULL && + io_image != NULL && io_ringSectionBuf != NULL && - io_ringBuf1 != NULL && - io_ringBuf2 != NULL, + i_ringBuf1 != NULL && + i_ringBuf2 != NULL && + i_ringBuf3 != NULL, fapi2::XIPC_INVALID_INPUT_BUFFER_PARM(). set_CHIP_TARGET(i_procTarget). + set_HW_IMAGE(i_hwImage). set_IMAGE_BUF(io_image). set_RING_SECTION_BUF(io_ringSectionBuf). - set_RING_BUF1(io_ringBuf1). - set_RING_BUF2(io_ringBuf2), + set_RING_BUF1(i_ringBuf1). + set_RING_BUF2(i_ringBuf2). + set_RING_BUF3(i_ringBuf3), "One or more invalid input buffer pointers:\n" + " i_hwImage=0x%016llx\n" " io_image=0x%016llx\n" " io_ringSectionBuf=0x%016llx\n" - " io_ringBuf1=0x%016llx\n" - " io_ringBuf2=0x%016llx\n", + " i_ringBuf1=0x%016llx\n" + " i_ringBuf2=0x%016llx\n" + " i_ringBuf3=0x%016llx\n", + (uintptr_t)i_hwImage, (uintptr_t)io_image, (uintptr_t)io_ringSectionBuf, - (uintptr_t)io_ringBuf1, - (uintptr_t)io_ringBuf2 ); + (uintptr_t)i_ringBuf1, + (uintptr_t)i_ringBuf2, + (uintptr_t)i_ringBuf3 ); l_rc = p9_xip_image_size(io_image, &l_inputImageSize); @@ -1371,7 +1567,8 @@ ReturnCode p9_xip_customize ( FAPI_ASSERT( (io_imageSize >= l_inputImageSize || io_imageSize >= MAX_SEEPROM_IMAGE_SIZE) && io_ringSectionBufSize >= MAX_SEEPROM_IMAGE_SIZE && i_ringBufSize1 == MAX_RING_BUF_SIZE && - i_ringBufSize2 == MAX_RING_BUF_SIZE, + i_ringBufSize2 == MAX_RING_BUF_SIZE && + i_ringBufSize3 == MAX_RING_BUF_SIZE, fapi2::XIPC_INVALID_INPUT_BUFFER_SIZE_PARM(). set_CHIP_TARGET(i_procTarget). set_INPUT_IMAGE_SIZE(l_inputImageSize). @@ -1379,18 +1576,21 @@ ReturnCode p9_xip_customize ( set_RING_SECTION_BUF_SIZE(io_ringSectionBufSize). set_RING_BUF_SIZE1(i_ringBufSize1). set_RING_BUF_SIZE2(i_ringBufSize2). + set_RING_BUF_SIZE3(i_ringBufSize3). set_OCCURRENCE(1), "One or more invalid input buffer sizes:\n" " l_inputImageSize=0x%016llx\n" " io_imageSize=0x%016llx\n" " io_ringSectionBufSize=0x%016llx\n" " i_ringBufSize1=0x%016llx\n" - " i_ringBufSize2=0x%016llx\n", + " i_ringBufSize2=0x%016llx\n" + " i_ringBufSize3=0x%016llx\n", (uintptr_t)l_inputImageSize, (uintptr_t)io_imageSize, (uintptr_t)io_ringSectionBufSize, (uintptr_t)i_ringBufSize1, - (uintptr_t)i_ringBufSize2 ); + (uintptr_t)i_ringBufSize2, + (uintptr_t)i_ringBufSize3 ); FAPI_DBG("Input image size: %d", l_inputImageSize); @@ -1425,7 +1625,7 @@ ReturnCode p9_xip_customize ( uint64_t l_pibmemRepData[4] = {0}; uint32_t l_sizeMvpdFieldExpected = sizeof(l_pibmemRepVersion) + sizeof(l_pibmemRepData); uint32_t l_sizeMvpdField = 0; - uint8_t* l_bufMvpdField = (uint8_t*)io_ringBuf1; + uint8_t* l_bufMvpdField = (uint8_t*)i_ringBuf1; FAPI_TRY( getMvpdField(MVPD_RECORD_CP00, MVPD_KEYWORD_PB, @@ -1574,6 +1774,7 @@ ReturnCode p9_xip_customize ( // - Copy image's sysPhase specific [sub-]section into separate ring // section buffer // - Delete (IPL sysPhase only) .rings, since we need to append later + // - Determine if there GPTR support, and overlays support, through Mvpd ////////////////////////////////////////////////////////////////////////// switch (i_sysPhase) @@ -1710,11 +1911,14 @@ ReturnCode p9_xip_customize ( io_ringSectionBuf, io_ringSectionBufSize, // Running section size l_maxRingSectionSize, // Max section size + i_hwImage, i_sysPhase, - io_ringBuf1, + i_ringBuf1, i_ringBufSize1, - io_ringBuf2, + i_ringBuf2, i_ringBufSize2, + i_ringBuf3, + i_ringBufSize3, io_bootCoreMask ); FAPI_DBG("-----------------------------------------------------------------------"); @@ -1941,11 +2145,14 @@ ReturnCode p9_xip_customize ( io_ringSectionBuf, io_ringSectionBufSize, // Running section size l_maxRingSectionSize, // Max section size + i_hwImage, i_sysPhase, - io_ringBuf1, + i_ringBuf1, i_ringBufSize1, - io_ringBuf2, + i_ringBuf2, i_ringBufSize2, + i_ringBuf3, + i_ringBufSize3, io_bootCoreMask ); FAPI_DBG("Size of .rings section after VPD update: %d", io_ringSectionBufSize ); diff --git a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.H b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.H index 0b6de8a23..06490cb17 100644 --- a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.H +++ b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.H @@ -30,16 +30,19 @@ typedef fapi2::ReturnCode (*p9_xip_customize_FP_t) ( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_proc_target, + void* i_hwImage, void* io_image, uint32_t& io_imageSize, void* io_ringSectionBuf, uint32_t& io_ringSectionBufSize, uint8_t i_sysPhase, uint8_t i_modeBuild, - void* io_ringBuf1, + void* i_ringBuf1, uint32_t i_ringBufSize1, - void* io_ringBuf2, + void* i_ringBuf2, uint32_t i_ringBufSize2, + void* i_ringBuf3, + uint32_t i_ringBufSize3, uint32_t& io_bootCoreMask); extern "C" @@ -48,6 +51,7 @@ extern "C" /// mailbox attributes, VPD rings and other stuff. /// /// @param[in] i_proc_target => P9 proc chip target +/// @param[in] i_hwImage => HW image /// @param[in/out] io_image => Pointer to an in-memory image /// HB_SBE: /// In: SBE image @@ -80,14 +84,18 @@ extern "C" /// Out: Final size /// @param[in] i_sysPhase => ={HB_SBE, RT_CME, RT_SGPE} /// @param[in] i_modeBuild => ={IPL, REBUILD} -/// @param[in/out] io_ringBuf1 => Caller supplied in-memory buffer -/// for uncompressed VPD rings in +/// @param[in] i_ringBuf1 => Caller supplied in-memory buffer +/// for VPD rings /// @param[in] i_ringBufSize1 => Max size of VPD ring buffer /// (Should equal MAX_RING_BUF_SIZE) -/// @param[in/out] io_ringBuf2 => Caller supplied in-memory buffer -/// for uncompressed overlay rings +/// @param[in] i_ringBuf2 => Caller supplied in-memory buffer +/// for overlay rings /// @param[in] i_ringBufSize2 => Max size of overlay ring buffer /// (Should equal MAX_RING_BUF_SIZE) +/// @param[in] i_ringBuf3 => Caller supplied in-memory buffer +/// to hold scratchpad rings +/// @param[in] i_ringBufSize3 => Max size of overlay ring buffer +/// (Should equal MAX_RING_BUF_SIZE) /// @param[in/out] io_bootCoreMask => In: Mask of the desired boot cores /// Out: Actual boot cores /// (Only used in HB_SBE sysPhase) @@ -97,26 +105,29 @@ extern "C" /// fapi2::ReturnCode p9_xip_customize ( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_proc_target, + void* i_hwImage, void* io_image, uint32_t& io_imageSize, void* io_ringSectionBuf, uint32_t& io_ringSectionBufSize, uint8_t i_sysPhase, uint8_t i_modeBuild, - void* io_ringBuf1, + void* i_ringBuf1, uint32_t i_ringBufSize1, - void* io_ringBuf2, + void* i_ringBuf2, uint32_t i_ringBufSize2, + void* i_ringBuf3, + uint32_t i_ringBufSize3, uint32_t& io_bootCoreMask); - } #else extern "C" { int p9_xip_customize ( int& i_proc_target, - void* i_image, + void* i_hwImage, + void* io_image, uint32_t& io_imageSize, - void* i_ringSectionBuf, + void* io_ringSectionBuf, uint32_t& io_ringSectionBufSize, uint8_t i_sysPhase, uint8_t i_modeBuild, @@ -124,6 +135,8 @@ extern "C" { uint32_t i_ringBufSize1, void* i_ringBuf2, uint32_t i_ringBufSize2, + void* i_ringBuf3, + uint32_t i_ringBufSize3, uint32_t& io_bootCoreMask); } #endif diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C index c6cbe0fde..3380235c3 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C @@ -149,16 +149,21 @@ struct RingBufData uint32_t iv_sizeWorkBuf1; void* iv_pWorkBuf2; uint32_t iv_sizeWorkBuf2; + void* iv_pWorkBuf3; + uint32_t iv_sizeWorkBuf3; RingBufData( void* i_pRingBuf1, const uint32_t i_ringSize, void* i_pWorkBuf1, const uint32_t i_sizeWorkBuf1, - void* i_pWorkBuf2, const uint32_t i_sizeWorkBuf2 ) : + void* i_pWorkBuf2, const uint32_t i_sizeWorkBuf2, + void* i_pWorkBuf3, const uint32_t i_sizeWorkBuf3 ) : iv_pRingBuffer( i_pRingBuf1), iv_ringBufSize(i_ringSize), iv_pWorkBuf1( i_pWorkBuf1 ), iv_sizeWorkBuf1( i_sizeWorkBuf1 ), iv_pWorkBuf2( i_pWorkBuf2 ), - iv_sizeWorkBuf2( i_sizeWorkBuf2 ) + iv_sizeWorkBuf2( i_sizeWorkBuf2 ), + iv_pWorkBuf3( i_pWorkBuf3 ), + iv_sizeWorkBuf3( i_sizeWorkBuf3 ) {} @@ -168,7 +173,9 @@ struct RingBufData iv_pWorkBuf1( NULL ), iv_sizeWorkBuf1( 0 ), iv_pWorkBuf2( NULL ), - iv_sizeWorkBuf2( 0 ) + iv_sizeWorkBuf2( 0 ), + iv_pWorkBuf3( NULL ), + iv_sizeWorkBuf3( 0 ) { } }; @@ -549,7 +556,8 @@ fapi_try_exit: fapi2::ReturnCode validateInputArguments( void* const i_pImageIn, void* i_pImageOut, SysPhase_t i_phase, ImageType_t i_imgType, void* i_pBuf1, uint32_t i_bufSize1, void* i_pBuf2, - uint32_t i_bufSize2, void* i_pBuf3, uint32_t i_bufSize3 ) + uint32_t i_bufSize2, void* i_pBuf3, uint32_t i_bufSize3, + void* i_pBuf4, uint32_t i_bufSize4 ) { uint32_t l_rc = IMG_BUILD_SUCCESS; uint32_t hwImagSize = 0; @@ -600,6 +608,11 @@ fapi2::ReturnCode validateInputArguments( void* const i_pImageIn, void* i_pImage .set_TEMP3_BUF_SIZE( i_bufSize3 ), "Invalid temp buffer3 passed for hcode image build" ); + FAPI_ASSERT( ( i_pBuf4 != NULL ), + fapi2::HCODE_INVALID_TEMP4_BUF() + .set_TEMP4_BUF_SIZE( i_bufSize4 ), + "Invalid temp buffer4 passed for hcode image build" ); + FAPI_ASSERT( ( i_bufSize1 != 0 ) , fapi2::HCODE_INVALID_TEMP1_BUF_SIZE() .set_TEMP1_BUF_SIZE( i_bufSize1 ), @@ -615,6 +628,11 @@ fapi2::ReturnCode validateInputArguments( void* const i_pImageIn, void* i_pImage .set_TEMP3_BUF_SIZE( i_bufSize3 ), "Invalid size for temp buf3 passed for hcode image build" ); + FAPI_ASSERT( ( i_bufSize4 != 0 ), + fapi2::HCODE_INVALID_TEMP4_BUF_SIZE() + .set_TEMP4_BUF_SIZE( i_bufSize4 ), + "Invalid size for temp buf4 passed for hcode image build" ); + FAPI_ASSERT( ( i_imgType.isBuildValid() ), fapi2::HCODE_INVALID_IMG_TYPE(), "Invalid image type passed for hcode image build" ); @@ -1679,6 +1697,8 @@ uint32_t getPpeScanRings( void* const i_pHwImage, (uintptr_t)(i_ringData.iv_pWorkBuf1), i_ringData.iv_sizeWorkBuf1); FAPI_DBG("Work buf2 (buf,size)=(0x%016llX,0x%08X)", (uintptr_t)(i_ringData.iv_pWorkBuf2), i_ringData.iv_sizeWorkBuf2); + FAPI_DBG("Work buf2 (buf,size)=(0x%016llX,0x%08X)", + (uintptr_t)(i_ringData.iv_pWorkBuf3), i_ringData.iv_sizeWorkBuf3); FAPI_DBG("---------------=== Buffer Specs Ends --------------------"); FAPI_DBG("--------------- Buffer Initializaiton to 0 --------------------"); @@ -1686,6 +1706,7 @@ uint32_t getPpeScanRings( void* const i_pHwImage, memset( (uint8_t*) i_ringData.iv_pRingBuffer, 0x00, i_ringData.iv_ringBufSize ); memset( (uint8_t*) i_ringData.iv_pWorkBuf1, 0x00, i_ringData.iv_sizeWorkBuf1 ); memset( (uint8_t*) i_ringData.iv_pWorkBuf2, 0x00, i_ringData.iv_sizeWorkBuf2 ); + memset( (uint8_t*) i_ringData.iv_pWorkBuf3, 0x00, i_ringData.iv_sizeWorkBuf3 ); uint32_t l_bootMask = ENABLE_ALL_CORE; fapi2::ReturnCode l_fapiRc = fapi2::FAPI2_RC_SUCCESS; @@ -1694,6 +1715,7 @@ uint32_t getPpeScanRings( void* const i_pHwImage, p9_xip_customize, i_procTgt, i_pHwImage, + i_pHwImage, hwImageSize, i_ringData.iv_pRingBuffer, i_ringData.iv_ringBufSize, @@ -1703,6 +1725,8 @@ uint32_t getPpeScanRings( void* const i_pHwImage, i_ringData.iv_sizeWorkBuf1, i_ringData.iv_pWorkBuf2, i_ringData.iv_sizeWorkBuf2, + i_ringData.iv_pWorkBuf3, + i_ringData.iv_sizeWorkBuf3, l_bootMask ); if( l_fapiRc ) @@ -3923,7 +3947,9 @@ fapi2::ReturnCode p9_hcode_image_build( CONST_FAPI2_PROC& i_procTgt, void* const i_pBuf2, const uint32_t i_sizeBuf2, void* const i_pBuf3, - const uint32_t i_sizeBuf3 ) + const uint32_t i_sizeBuf3, + void* const i_pBuf4, + const uint32_t i_sizeBuf4 ) { @@ -3946,7 +3972,9 @@ fapi2::ReturnCode p9_hcode_image_build( CONST_FAPI2_PROC& i_procTgt, i_pBuf2, i_sizeBuf2, i_pBuf3, - i_sizeBuf3 ); + i_sizeBuf3, + i_pBuf4, + i_sizeBuf4 ); FAPI_TRY( validateInputArguments( i_pImageIn, i_pHomerImage, @@ -3957,7 +3985,9 @@ fapi2::ReturnCode p9_hcode_image_build( CONST_FAPI2_PROC& i_procTgt, i_pBuf2, i_sizeBuf2, i_pBuf3, - i_sizeBuf3 ), + i_sizeBuf3, + i_pBuf4, + i_sizeBuf4 ), "Invalid arguments, escaping hcode image build" ); // HW Image is a nested XIP Image. Let us read global TOC of hardware image diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.H b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.H index 8aa661c0b..1ec980981 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.H @@ -138,7 +138,9 @@ extern "C" void* const i_pBuf2, const uint32_t i_sizeBuf2, void* const i_pBuf3, - const uint32_t i_sizeBuf3 ); + const uint32_t i_sizeBuf3, + void* const i_pBuf4, + const uint32_t i_sizeBuf4 ); /** * @brief builds a STOP image using a refrence image as input. @@ -152,8 +154,10 @@ extern "C" * @param i_sizeBuf1 size of work buffer1. Minimum size expected HW_IMG_RING_SIZE. * @param i_pBuf2 pointer to a work buffer2. Minimum size expected WORK_BUF_SIZE. * @param i_sizeBuf2 size of work buffer2 - * @param i_pBuf3 pointer to a work buffer2. Minimum size expected WORK_BUF_SIZE. - * @param i_sizeBuf3 size of work buffer2 + * @param i_pBuf3 pointer to a work buffer3. Minimum size expected WORK_BUF_SIZE. + * @param i_sizeBuf3 size of work buffer3 + * @param i_pBuf4 pointer to a work buffer4. Minimum size expected WORK_BUF_SIZE. + * @param i_sizeBuf4 size of work buffer4 * @note needs attribute ATTR_EC */ fapi2::ReturnCode p9_hcode_image_build( CONST_FAPI2_PROC& i_procTgt, @@ -167,6 +171,8 @@ extern "C" void* const i_pBuf2, const uint32_t i_sizeBuf2, void* const i_pBuf3, - const uint32_t i_sizeBuf3 ); + const uint32_t i_sizeBuf3, + void* const i_pBuf4, + const uint32_t i_sizeBuf4 ); } // extern C #endif //__HCODE_IMG_BUILD_H_ diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index daa54c47c..cce652faa 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -4178,4 +4178,23 @@ </chipEcFeature> </attribute> <!-- ********************************************************************* --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_NO_GPTR_SUPPORT_VIA_MVPD</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + indicaes if there is GPTR support through MVPD which there will NOT be if + Nimbus DD1 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ********************************************************************* --> + </attributes> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml index 9c9b4a6a5..c092902da 100755 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml @@ -129,6 +129,26 @@ </hwpError> <!-- *********************************************************************** --> <hwpError> + <rc>RC_HCODE_INVALID_TEMP4_BUF</rc> + <description>Temporary buffer4 is invalid.</description> + <ffdc>TEMP4_BUF_SIZE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_HCODE_INVALID_TEMP4_BUF_SIZE</rc> + <description>Invalid size for temp buf4</description> + <ffdc>TEMP4_BUF_SIZE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> <rc>RC_HCODE_INVALID_IMG_TYPE</rc> <description>Invalid image type passed for hcode image build.</description> <callout> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_xip_customize_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_xip_customize_errors.xml index 3b7d22622..8f3f5323f 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_xip_customize_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_xip_customize_errors.xml @@ -44,10 +44,12 @@ <priority>HIGH</priority> </callout> <ffdc>CHIP_TARGET</ffdc> + <ffdc>HW_IMAGE</ffdc> <ffdc>IMAGE_BUF</ffdc> <ffdc>RING_SECTION_BUF</ffdc> <ffdc>RING_BUF1</ffdc> <ffdc>RING_BUF2</ffdc> + <ffdc>RING_BUF3</ffdc> </hwpError> <!-- ********************************************************************* --> <hwpError> @@ -63,6 +65,7 @@ <ffdc>RING_SECTION_BUF_SIZE</ffdc> <ffdc>RING_BUF_SIZE1</ffdc> <ffdc>RING_BUF_SIZE2</ffdc> + <ffdc>RING_BUF_SIZE3</ffdc> <ffdc>OCCURRENCE</ffdc> </hwpError> <!-- ********************************************************************* --> diff --git a/src/import/chips/p9/xip/p9_xip_image.C b/src/import/chips/p9/xip/p9_xip_image.C index 0dbf5cf6d..97d7ed86d 100644 --- a/src/import/chips/p9/xip/p9_xip_image.C +++ b/src/import/chips/p9/xip/p9_xip_image.C @@ -3264,11 +3264,6 @@ int p9_xip_dd_section_support(const void* i_image, int rc; P9XipSection section; - if (i_sectionId == P9_XIP_SECTION_HW_OVERLAYS) - { - return P9_XIP_OVERLAYS_NOT_SUPPORTED; - } - rc = p9_xip_get_section(i_image, i_sectionId, §ion); if (!rc) diff --git a/src/include/usr/sbe/sbe_update.H b/src/include/usr/sbe/sbe_update.H index 9280ab55b..1d5a6a784 100644 --- a/src/include/usr/sbe/sbe_update.H +++ b/src/include/usr/sbe/sbe_update.H @@ -139,15 +139,17 @@ namespace SBE // // 256K - 316K = Ring buf1 // 316K - 376K = Ring buf2 - // 376K - 632K = Ring Section buf + // 376k - 436k = Ring buf3 + // 436K - 692K = Ring Section buf // ---- ALT use 256K-632K for SBE ECC image - // 632K - 888K = SBE + HBBL image + // 692K - 948K = SBE + HBBL image enum { FIXED_SEEPROM_WORK_SPACE = 256 * 1024, SBE_IMG_VADDR = VMM_VADDR_SBE_UPDATE, RING_BUF1_VADDR = FIXED_SEEPROM_WORK_SPACE + SBE_IMG_VADDR, RING_BUF2_VADDR = RING_BUF1_VADDR + MAX_RING_BUF_SIZE, - RING_SEC_VADDR = RING_BUF2_VADDR + MAX_RING_BUF_SIZE, + RING_BUF3_VADDR = RING_BUF2_VADDR + MAX_RING_BUF_SIZE, + RING_SEC_VADDR = RING_BUF3_VADDR + MAX_RING_BUF_SIZE, //NOTE: recycling the same memory space for different //steps in the process. SBE_ECC_IMG_VADDR = RING_BUF1_VADDR, @@ -431,6 +433,7 @@ namespace SBE * @return errlHndl_t Error log handle on failure. */ errlHndl_t procCustomizeSbeImg(TARGETING::Target* i_target, + void* i_hwImgPtr, void* i_sbeImgPtr, size_t i_maxImgSize, void* io_imgPtr, diff --git a/src/include/usr/vmmconst.h b/src/include/usr/vmmconst.h index 233d5fe19..b19980941 100644 --- a/src/include/usr/vmmconst.h +++ b/src/include/usr/vmmconst.h @@ -100,7 +100,7 @@ /** SBE Update process is at 3GB, uses 512KB */ #define VMM_VADDR_SBE_UPDATE (3 * GIGABYTE) -#define VMM_SBE_UPDATE_SIZE (900 * KILOBYTE) +#define VMM_SBE_UPDATE_SIZE (1024 * KILOBYTE) #define VMM_VADDR_SBE_UPDATE_END (VMM_VADDR_SBE_UPDATE + VMM_SBE_UPDATE_SIZE) /** Debug Comm Channel is at 3.5GB, uses 32KB */ #define VMM_VADDR_DEBUG_COMM ((3 * GIGABYTE) + (500 * MEGABYTE)) diff --git a/src/usr/isteps/istep15/host_build_stop_image.C b/src/usr/isteps/istep15/host_build_stop_image.C index 9109df54d..b63fc4390 100644 --- a/src/usr/isteps/istep15/host_build_stop_image.C +++ b/src/usr/isteps/istep15/host_build_stop_image.C @@ -366,10 +366,11 @@ void* host_build_stop_image (void *io_pArgs) TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "host_build_stop_image entry" ); - // allocate three temporary work buffers + // allocate four temporary work buffers void* l_temp_buffer0 = malloc(HW_IMG_RING_SIZE); void* l_temp_buffer1 = malloc(MAX_RING_BUF_SIZE); void* l_temp_buffer2 = malloc(MAX_RING_BUF_SIZE); + void* l_temp_buffer3 = malloc(MAX_RING_BUF_SIZE); do { //Determine top-level system target @@ -528,7 +529,9 @@ void* host_build_stop_image (void *io_pArgs) l_temp_buffer1, MAX_RING_BUF_SIZE, l_temp_buffer2, - MAX_RING_BUF_SIZE ); + MAX_RING_BUF_SIZE, + l_temp_buffer3, + MAX_RING_BUF_SIZE); if ( l_errl ) { @@ -592,6 +595,7 @@ void* host_build_stop_image (void *io_pArgs) if( l_temp_buffer0 ) { free(l_temp_buffer0); } if( l_temp_buffer1 ) { free(l_temp_buffer1); } if( l_temp_buffer2 ) { free(l_temp_buffer2); } + if( l_temp_buffer3 ) { free(l_temp_buffer3); } #ifdef CONFIG_SECUREBOOT // securely unload HCODE PNOR section, if necessary diff --git a/src/usr/isteps/pm/pm_common.C b/src/usr/isteps/pm/pm_common.C index 995686747..15a91c5a1 100644 --- a/src/usr/isteps/pm/pm_common.C +++ b/src/usr/isteps/pm/pm_common.C @@ -238,6 +238,7 @@ namespace HBPM void *l_buffer0 = (void*)malloc(HW_IMG_RING_SIZE); void *l_buffer1 = (void*)malloc(MAX_RING_BUF_SIZE); void *l_buffer2 = (void*)malloc(MAX_RING_BUF_SIZE); + void *l_buffer3 = (void*)malloc(MAX_RING_BUF_SIZE); do { @@ -323,7 +324,9 @@ namespace HBPM l_buffer1, MAX_RING_BUF_SIZE, l_buffer2, - MAX_RING_BUF_SIZE ); + MAX_RING_BUF_SIZE, + l_buffer3, + MAX_RING_BUF_SIZE); if (l_errl) { @@ -413,6 +416,7 @@ namespace HBPM free(l_buffer0); free(l_buffer1); free(l_buffer2); + free(l_buffer3); TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, EXIT_MRK"loadHcode: RC=0x%X, PLID=0x%lX", diff --git a/src/usr/sbe/sbe_update.C b/src/usr/sbe/sbe_update.C index 5c4068631..b3366adf0 100644 --- a/src/usr/sbe/sbe_update.C +++ b/src/usr/sbe/sbe_update.C @@ -962,6 +962,7 @@ namespace SBE ///////////////////////////////////////////////////////////////////// errlHndl_t procCustomizeSbeImg(TARGETING::Target* i_target, + void* i_hwImgPtr, void* i_sbeImgPtr, size_t i_maxImgSize, void* io_imgPtr, @@ -1035,6 +1036,7 @@ namespace SBE FAPI_INVOKE_HWP( err, p9_xip_customize, l_fapiTarg, + i_hwImgPtr, io_imgPtr, //image in/out tmpImgSize, (void*)RING_SEC_VADDR, @@ -1045,6 +1047,8 @@ namespace SBE (uint32_t)MAX_RING_BUF_SIZE, (void*)RING_BUF2_VADDR, (uint32_t)MAX_RING_BUF_SIZE, + (void*)RING_BUF3_VADDR, + (uint32_t)MAX_RING_BUF_SIZE, procIOMask ); // Bits(8:31) = EC00:EC23 // Check for no error and use of input cores @@ -1705,6 +1709,36 @@ namespace SBE } ///////////////////////////////////////////////////////////////////// + errlHndl_t sbeLoadHcode(char*& o_hcodeAddr) + { + errlHndl_t l_errl = NULL; + PNOR::SectionInfo_t l_info; + + do + { + + // Get HCODE PNOR section info from PNOR RP + l_errl = PNOR::getSectionInfo( PNOR::HCODE, l_info ); + if( l_errl ) + { + //No need to commit error here, it gets handled later + //just break out to escape this function + break; + } + + o_hcodeAddr = reinterpret_cast<char*>(l_info.vaddr); + + TRACUCOMP( g_trac_sbe, + ERR_MRK"sbeLoadHcode() - Error from " + "HCODE addr = 0x%p ", + o_hcodeAddr); + + } while ( 0 ); + + return l_errl; + } + + ///////////////////////////////////////////////////////////////////// errlHndl_t getSbeInfoState(sbeTargetState_t& io_sbeState) { @@ -1965,7 +1999,25 @@ namespace SBE /* Calculate CRC of the image */ /*******************************************/ size_t sbeImgSize = 0; + + + // get a pointer to the hcode for the .overlays + char* l_hCodeAddr = NULL; + + err = sbeLoadHcode(l_hCodeAddr); + + if(err) + { + TRACFCOMP( g_trac_sbe, ERR_MRK"ge() - " + "Error from sbeLoadHcode(), " + "RC=0x%X, PLID=0x%lX", + ERRL_GETRC_SAFE(err), + ERRL_GETPLID_SAFE(err)); + break; + } + err = procCustomizeSbeImg(io_sbeState.target, + l_hCodeAddr, // HCODE in memory sbeHbblImgPtr, //SBE, HBBL in memory sbeHbblImgSize, reinterpret_cast<void*> @@ -1982,6 +2034,8 @@ namespace SBE break; } + + // Verify that HW Key Hash is included in customized image SHA512_t hash = {0}; err = getHwKeyHashFromSbeImage(io_sbeState.target, // ignored @@ -3800,6 +3854,14 @@ namespace SBE TRACFCOMP( g_trac_sbe, ERR_MRK,"createSbeImageVmmSpace() - Error from loadSecureSection(PNOR::HB_BOOTLOADER)"); break; } + + err = loadSecureSection(PNOR::HCODE); + + if (err) + { + TRACFCOMP( g_trac_sbe, ERR_MRK,"createSbeImageVmmSpace() - Error from loadSecureSection(PNOR::HCODE)"); + break; + } #endif }while(0); @@ -3911,6 +3973,13 @@ namespace SBE TRACFCOMP( g_trac_sbe, ERR_MRK,"cleanupSbeImageVmmSpace() - Error from unloadSecureSection(PNOR::HB_BOOTLOADER)"); break; } + err = unloadSecureSection(PNOR::HCODE); + if (err) + { + TRACFCOMP( g_trac_sbe, ERR_MRK,"cleanupSbeImageVmmSpace() - Error from unloadSecureSection(PNOR::HCODE)"); + break; + } + #endif }while(0); |
