diff options
11 files changed, 646 insertions, 609 deletions
diff --git a/src/usr/hwpf/hwp/dimm_spd_attributes.xml b/src/usr/hwpf/hwp/dimm_spd_attributes.xml index 704d9c959..3c5bb2353 100644 --- a/src/usr/hwpf/hwp/dimm_spd_attributes.xml +++ b/src/usr/hwpf/hwp/dimm_spd_attributes.xml @@ -20,7 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: dimm_spd_attributes.xml,v 1.28 2013/10/11 19:58:00 mjjones Exp $ --> +<!-- $Id: dimm_spd_attributes.xml,v 1.33 2013/11/11 17:14:23 bellows Exp $ --> <!-- XML file specifying DIMM SPD attributes used by HW Procedures. --> <attributes> @@ -1409,19 +1409,18 @@ file RANK3_MIRRORED = 0x01 </enum> <platInit/> - <array> 2 2 </array> + <array> 2 2</array> </attribute> -<!-- Not yet supported by firmware +<!-- TODO: RTC 82331 - Add this attribute to the Accessor HWP <attribute> <id>ATTR_VPD_DRAM_2N_MODE</id> - <targetType>TARGET_TYPE_DIMM</targetType> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> <description> The 2N/2T characteristic of the DIMM from the VPD MR keyword. If the memory controller needs to run on 2N mode, the address is presented for two cycles. By default, 2N should be set to INVALID until the platform initializes it. </description> <valueType>uint8</valueType> - <enum>INVALID = 0x00, 1N = 0x01, 2N = 0x02</enum> - <array>2</array> + <enum>FALSE = 0, TRUE = 1</enum> <platInit/> </attribute> @@ -1477,7 +1476,7 @@ consumer: various.C files (no initfile) firmware notes: none This Attribute is to be interpreted as an Integer </description> <valueType>uint8</valueType> - <enum>INVALID =0, OHM34 = 34, OHM40 = 40, OHM48 = 48</enum> + <enum>INVALID = 0, OHM34 = 34, OHM40 = 40, OHM48 = 48</enum> <platInit/> <odmVisable/> <odmChangeable/> @@ -2306,6 +2305,87 @@ This Attribute is to be interpreted as an Integer</description> <array> 2</array> </attribute> +<!-- Spare attribute found in eclipz/hwpf/hwp/xml/attribute_info/dimm_attributes.xml --> +<!-- <attribute> --> +<!-- <id>ATTR_VPD_DIMM_SPARE</id> --> +<!-- <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> --> +<!-- <description>Spare DRAM availability. It comes from the VPD or SPD in ISDIMM systems</description> --> +<!-- <valueType>uint8</valueType> --> +<!-- <enum>NO_SPARE = 0, LOW_NIBBLE = 1, HIGH_NIBBLE = 2, FULL_BYTE = 3</enum> --> +<!-- <odmVisable/> --> +<!-- <odmChangeable/> --> +<!-- <array> 2 2 4</array> --> +<!-- </attribute> --> + +<attribute> + <id>ATTR_VPD_CKE_PRI_MAP</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>This value comes from the VPD keyword MT bytes 54 and 55 MT(54:55) for the Logical DIMM associated with port A. Bytes 118:119 for port B, 182:183 for port C and 246:247 for port D. In the end, the AB and CD portions form a 32 bit word for each mba to write into the corresponding ddrphy register</description> + <valueType>uint32</valueType> + <platInit/> + <odmVisable/> + <array>2</array> +</attribute> + +<attribute> + <id>ATTR_VPD_CKE_PWR_MAP</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>This value comes from the VPD keyword MT bytes 56 to 59 MT(56:59) for the Logical DIMM associated with port A. Bytes 120:123 for port B, 184:187 for port C and 248:251 for port D. The values for Port A concatenated with port B forms the value for one MBA. C concat D forms the value for the other MBA</description> + <valueType>uint64</valueType> + <platInit/> + <odmVisable/> +</attribute> + +<attribute> + <id>ATTR_VPD_GPO</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>This value comes from the VPD keyword MT bytes 61 MT(61) for the Logical DIMM associated with port A. Bytes 125 for port B, 189 for port C and 253 for port D</description> + <valueType>uint8</valueType> + <platInit/> + <odmVisable/> + <array>2</array> +</attribute> + +<attribute> + <id>ATTR_VPD_RLO</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>This value comes from the VPD keyword MT byte 60 bits 4:7 for the Logical DIMM associated with port A. Byte 124 bits 4:7 for port B, 188 bits 4:7 for port C and 252 bits 4:7 for port D</description> + <valueType>uint8</valueType> + <platInit/> + <odmVisable/> + <array>2</array> +</attribute> + +<attribute> + <id>ATTR_VPD_WLO</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>This value comes from the VPD keyword MT byte 60 bits 0:3 for the Logical DIMM associated with port A. Byte 124 bits 0:3 for port B, 188 bits 0:3 for port C and 252 bits 0:3 for port D</description> + <valueType>uint8</valueType> + <platInit/> + <odmVisable/> + <array>2</array> +</attribute> + +<attribute> + <id>ATTR_VPD_TSYS_ADR</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>This value comes from the VPD MR keyword byte 49 for ports A and B and byte 177 for port C and D. This means that all ADR blocks use this value on an mba level</description> + <valueType>uint8</valueType> + <platInit/> + <odmVisable/> + <array>2</array> +</attribute> + +<attribute> + <id>ATTR_VPD_TSYS_DP18</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>This value comes from the VPD MR keyword byte 113 for ports A and B and byte 241 for port C and D. This means all DP18 blocks use this value on a mba level</description> + <valueType>uint8</valueType> + <platInit/> + <odmVisable/> + <array>2</array> +</attribute> + <attribute> <id>ATTR_VPD_CDIMM_SENSOR_MAP_PRIMARY</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -2344,6 +2424,48 @@ Comes from the VPD MW Keyword</description> <odmVisable/> </attribute> +<!-- TODO: RTC 82331 - Add this attribute to the Accessor HWP +<attribute> + <id>ATTR_VPD_CDIMM_MASTER_POWER_SLOPE</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>Master Power Slope that comes from the VPD MW Keyword</description> + <valueType>uint32</valueType> + <platInit/> + <odmVisable/> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_VPD_CDIMM_MASTER_POWER_INTERCEPT</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>Master Power Intercept that comes from the VPD MW Keyword</description> + <valueType>uint32</valueType> + <platInit/> + <odmVisable/> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_VPD_CDIMM_SUPPLIER_POWER_SLOPE</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>Supplier Power Slope that comes from the VPD the MV Keyword</description> + <valueType>uint32</valueType> + <platInit/> + <odmVisable/> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_VPD_CDIMM_SUPPLIER_POWER_INTERCEPT</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>Supplier Power Intercept that comes from MV Keyword</description> + <valueType>uint32</valueType> + <platInit/> + <odmVisable/> + <persistRuntime/> +</attribute> +--> + <attribute> <id>ATTR_VPD_DRAM_2N_MODE_ENABLED</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> @@ -2355,4 +2477,5 @@ Comes from the VPD MW Keyword</description> </attribute> + </attributes> diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C index 4dd219b8d..3d3ae22d1 100755 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit.C,v 1.58 2013/10/15 14:16:33 jdsloat Exp $ +// $Id: mss_draminit.C,v 1.59 2013/11/11 20:50:06 jdsloat Exp $ //------------------------------------------------------------------------------ // Don't forget to create CVS comments when you check in your changes! //------------------------------------------------------------------------------ @@ -28,6 +28,7 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.59 | jdsloat | 11/11/13| Changed EFF attributes to VPD named attributes // 1.58 | jdsloat | 10/15/13| Added rc checks in ddr4 shadow regs check per review request // 1.57 | jdsloat | 10/09/13| Added mrs_load_ddr4 with defines for ddr4 usage, added shadow regs, removed complicated flow // 1.56 | bellows | 09/16/13| Hostboot compile fix @@ -293,7 +294,7 @@ ReturnCode mss_draminit_cloned(Target& i_target) rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim); if(rc) return rc; uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm] - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map); + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map); if(rc) return rc; @@ -1387,11 +1388,11 @@ ReturnCode mss_mrs_load( if(rc) return rc; uint8_t dram_2n_mode = 0; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_2N_MODE_ENABLED, &i_target, dram_2n_mode); + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_2N_MODE_ENABLED, &i_target, dram_2n_mode); if(rc) return rc; uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm] - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map); + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map); if(rc) return rc; @@ -1517,10 +1518,10 @@ ReturnCode mss_mrs_load( rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_ENABLE, &i_target, dll_enable); if(rc) return rc; uint8_t out_drv_imp_cntl[2][2]; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RON, &i_target, out_drv_imp_cntl); + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RON, &i_target, out_drv_imp_cntl); if(rc) return rc; uint8_t dram_rtt_nom[2][2][4]; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RTT_NOM, &i_target, dram_rtt_nom); + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_NOM, &i_target, dram_rtt_nom); if(rc) return rc; uint8_t dram_al; rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_AL, &i_target, dram_al); @@ -1598,7 +1599,7 @@ ReturnCode mss_mrs_load( rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_SRT, &i_target, sr_temp); if(rc) return rc; uint8_t dram_rtt_wr[2][2][4]; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RTT_WR, &i_target, dram_rtt_wr); + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_WR, &i_target, dram_rtt_wr); if(rc) return rc; if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_FULL) @@ -1750,42 +1751,42 @@ ReturnCode mss_mrs_load( { dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x00; } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE) + else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE) { dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x00; } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20) + else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20) { dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x20; } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30) + else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30) { dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xA0; } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40) + else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40) { dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xC0; } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM60) + else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60) { dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x80; } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120) + else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM120) { dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x40; } else { - FAPI_ERR( "mss_mrs_load: Error determining ATTR_EFF_DRAM_RTT_NOM value: %d from attribute", dram_rtt_nom[i_port_number][dimm_number][rank_number]); + FAPI_ERR( "mss_mrs_load: Error determining ATTR_VPD_DRAM_RTT_NOM value: %d from attribute", dram_rtt_nom[i_port_number][dimm_number][rank_number]); FAPI_SET_HWP_ERROR(rc, RC_MSS_IMP_INPUT_ERROR); return rc; } - if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_EFF_DRAM_RON_OHM40) + if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_VPD_DRAM_RON_OHM40) { out_drv_imp_cntl[i_port_number][dimm_number] = 0x00; } - else if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_EFF_DRAM_RON_OHM34) + else if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_VPD_DRAM_RON_OHM34) { out_drv_imp_cntl[i_port_number][dimm_number] = 0x80; } @@ -1811,21 +1812,21 @@ ReturnCode mss_mrs_load( { dram_rtt_wr[i_port_number][dimm_number][rank_number] = dram_rtt_wr[i_port_number][dimm_number][0]; } - else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) + else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE) { dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x00; } - else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60) + else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60) { dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x80; } - else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120) + else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120) { dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x40; } else { - FAPI_ERR( "mss_mrs_load: Error determining ATTR_EFF_DRAM_RTT_WR value: %d from attribute", dram_rtt_wr[i_port_number][dimm_number][rank_number]); + FAPI_ERR( "mss_mrs_load: Error determining ATTR_VPD_DRAM_RTT_WR value: %d from attribute", dram_rtt_wr[i_port_number][dimm_number][rank_number]); FAPI_SET_HWP_ERROR(rc, RC_MSS_IMP_INPUT_ERROR); return rc; } @@ -1910,7 +1911,7 @@ ReturnCode mss_mrs_load( } - if (dram_2n_mode == ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_TRUE) + if (dram_2n_mode == ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_TRUE) { // Send out to the CCS array a "setup" cycle diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C index 1b2980f3b..ac4f671a3 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit_training.C,v 1.69 2013/11/06 16:22:45 jdsloat Exp $ +// $Id: mss_draminit_training.C,v 1.70 2013/11/11 20:51:15 jdsloat Exp $ //------------------------------------------------------------------------------ // Don't forget to create CVS comments when you check in your changes! //------------------------------------------------------------------------------ @@ -28,6 +28,7 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|------------------------------------------------ +// 1.70 | jdsloat | 11/11/13| Changed EFF attributes to VPD named attributes // 1.69 | jdsloat |06-OCT-13| Removed Control Switch Attribute // 1.68 | bellows |16-SEP-13| Hostboot compile update // 1.67 | kcook |13-SEP-13| Updated define FAPI_LRDIMM token. @@ -2590,7 +2591,7 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( if(rc) return rc; uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm] - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map); + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map); if(rc) return rc; diff --git a/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.C b/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.C index 57bdab249..db118d734 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.C +++ b/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_lrdimm_funcs.C,v 1.4 2013/09/16 13:56:38 bellows Exp $ +// $Id: mss_lrdimm_funcs.C,v 1.5 2013/12/03 22:51:13 kcook Exp $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2013 // *! All Rights Reserved -- Property of IBM @@ -40,6 +40,7 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.5 | 12/03/13 | kcook | Updated VPD attributes. // 1.4 | 09/16/13 | bellows | Hostboot compile update // 1.3 | 09/16/13 | bellows | Added ID tag. // 1.2 | 09/13/13 | kcook | Updated define FAPI_LRDIMM token. @@ -585,11 +586,11 @@ fapi::ReturnCode mss_lrdimm_mrs_load( Target& i_target , uint32_t i_port_number, if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target, rcd_array); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map); + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_2N_MODE_ENABLED, &i_target, dram_2n_mode); + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_2N_MODE_ENABLED, &i_target, dram_2n_mode); if(rc) return rc; //MRS1 @@ -597,10 +598,10 @@ fapi::ReturnCode mss_lrdimm_mrs_load( Target& i_target , uint32_t i_port_number, rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_ENABLE, &i_target, dll_enable); if(rc) return rc; uint8_t out_drv_imp_cntl[2][2]; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RON, &i_target, out_drv_imp_cntl); + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RON, &i_target, out_drv_imp_cntl); if(rc) return rc; uint8_t dram_rtt_nom[2][2][4]; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RTT_NOM, &i_target, dram_rtt_nom); + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_NOM, &i_target, dram_rtt_nom); if(rc) return rc; uint8_t dram_al; rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_AL, &i_target, dram_al); @@ -799,36 +800,36 @@ fapi::ReturnCode mss_lrdimm_mrs_load( Target& i_target , uint32_t i_port_number, rc_num = rc_num | csn_8.setBit(0,8); rc_num = rc_num | address_16.clearBit(0, 16); - if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE) + if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE) { dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x00; } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20) + else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20) { dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x20; } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30) + else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30) { dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xA0; } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40) + else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40) { dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xC0; } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM60) + else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60) { dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x80; } - else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120) + else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM120) { dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x40; } - if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_EFF_DRAM_RON_OHM40) + if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_VPD_DRAM_RON_OHM40) { out_drv_imp_cntl[i_port_number][dimm_number] = 0x00; } - else if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_EFF_DRAM_RON_OHM34) + else if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_VPD_DRAM_RON_OHM34) { out_drv_imp_cntl[i_port_number][dimm_number] = 0x80; } @@ -885,7 +886,7 @@ fapi::ReturnCode mss_lrdimm_mrs_load( Target& i_target , uint32_t i_port_number, } - if (dram_2n_mode == ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_TRUE) + if (dram_2n_mode == ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_TRUE) { // Send out to the CCS array @@ -1584,10 +1585,10 @@ fapi::ReturnCode mss_lrdimm_term_atts(const Target& i_target_mba) // Fetch impacted attributes uint64_t l_attr_eff_dimm_rcd_cntl_word_0_15[PORT_SIZE][DIMM_SIZE]; rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RON, &i_target_mba, attr_eff_dram_ron); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RTT_NOM, &i_target_mba, attr_eff_dram_rtt_nom); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RTT_WR, &i_target_mba, attr_eff_dram_rtt_wr); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_ODT_WR, &i_target_mba, attr_eff_odt_wr); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RON, &i_target_mba, attr_eff_dram_ron); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_NOM, &i_target_mba, attr_eff_dram_rtt_nom); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_WR, &i_target_mba, attr_eff_dram_rtt_wr); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_VPD_ODT_WR, &i_target_mba, attr_eff_odt_wr); if(rc) return rc; // Fetch impacted attributes rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, l_num_drops_per_port); if(rc) return rc; @@ -1734,9 +1735,9 @@ fapi::ReturnCode mss_lrdimm_term_atts(const Target& i_target_mba) l_dram_rtt_wr[l_port][l_dimm] = (l_lrdimm_mr12_u8array[l_port][l_dimm] & 0xC0) >> 6; // Pulled from SPD LR MR1,2 DRAM RTT_WR [7:6] if ( l_dram_ron[l_port][l_dimm] == 0 ) { - l_dram_ron[l_port][l_dimm] = fapi::ENUM_ATTR_EFF_DRAM_RON_OHM40; + l_dram_ron[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RON_OHM40; } else if ( l_dram_ron[l_port][l_dimm] == 1 ) { - l_dram_ron[l_port][l_dimm] = fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34; + l_dram_ron[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34; } else { FAPI_ERR("Invalid SPD LR MR1,2 DRAM drv imp on %s!", i_target_mba.toEcmdString()); FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; @@ -1746,17 +1747,17 @@ fapi::ReturnCode mss_lrdimm_term_atts(const Target& i_target_mba) FAPI_INF("Set LRDIMM DRAM_RON to SPD LR MR1,2 DRAM drv imp"); switch (l_dram_rtt_nom[l_port][l_dimm]) { - case 0 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE; + case 0 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE; break; - case 1 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM60; + case 1 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60; break; - case 2 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120; + case 2 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM120; break; - case 3 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40; + case 3 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40; break; - case 4 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20; + case 4 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20; break; - case 5 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30; + case 5 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30; break; default: FAPI_ERR("Invalid SPD LR MR1,2 DRAM RTT_NOM on %s!", i_target_mba.toEcmdString()); FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; @@ -1764,11 +1765,11 @@ fapi::ReturnCode mss_lrdimm_term_atts(const Target& i_target_mba) } switch (l_dram_rtt_wr[l_port][l_dimm]) { - case 0 : l_dram_rtt_wr[l_port][l_dimm] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE; + case 0 : l_dram_rtt_wr[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE; break; - case 1 : l_dram_rtt_wr[l_port][l_dimm] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60; + case 1 : l_dram_rtt_wr[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60; break; - case 2 : l_dram_rtt_wr[l_port][l_dimm] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; + case 2 : l_dram_rtt_wr[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120; break; default: FAPI_ERR("Invalid SPD LR MR1,2 DRAM RTT_WR on %s!", i_target_mba.toEcmdString()); FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; @@ -1777,8 +1778,8 @@ fapi::ReturnCode mss_lrdimm_term_atts(const Target& i_target_mba) uint8_t l_rank; for ( l_rank = 0; l_rank < RANK_SIZE; l_rank++ ) { // clear RTT_NOM & RTT_WR - attr_eff_dram_rtt_nom[l_port][l_dimm][l_rank] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE; - attr_eff_dram_rtt_wr[l_port][l_dimm][l_rank] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE; + attr_eff_dram_rtt_nom[l_port][l_dimm][l_rank] = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE; + attr_eff_dram_rtt_wr[l_port][l_dimm][l_rank] = fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE; } if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] > 0 ) { // Set RTT_NOM Rank 0 for multi rank LRDIMM @@ -1812,10 +1813,10 @@ fapi::ReturnCode mss_lrdimm_term_atts(const Target& i_target_mba) } // end port loop // Set adjusted attributes - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RON, &i_target_mba, attr_eff_dram_ron); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RTT_NOM, &i_target_mba, attr_eff_dram_rtt_nom); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RTT_WR, &i_target_mba, attr_eff_dram_rtt_wr); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_ODT_WR, &i_target_mba, attr_eff_odt_wr); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_RON, &i_target_mba, attr_eff_dram_ron); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_RTT_NOM, &i_target_mba, attr_eff_dram_rtt_nom); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_RTT_WR, &i_target_mba, attr_eff_dram_rtt_wr); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_VPD_ODT_WR, &i_target_mba, attr_eff_odt_wr); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc; diff --git a/src/usr/hwpf/hwp/dram_training/mss_termination_control.C b/src/usr/hwpf/hwp/dram_training/mss_termination_control.C index b2f6ce6cf..d9b179250 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_termination_control.C +++ b/src/usr/hwpf/hwp/dram_training/mss_termination_control.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_termination_control.C,v 1.22 2013/09/24 22:14:02 mwuu Exp $ +// $Id: mss_termination_control.C,v 1.23 2013/12/02 18:55:39 bellows Exp $ /* File is created by SARAVANAN SETHURAMAN on Thur 29 Sept 2011. */ //------------------------------------------------------------------------------ @@ -43,6 +43,7 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.23 | bellows |02-Dec-13| VPD attribute update // 1.22 | mwuu |20-Sep-13| Updated ADR DDR3 slew calibration table for 1 setting, // 1066 20ohms, 4V/ns, changed from 11 to 10. // 1.21 | sasethur |16-Apr-13| Added DDR4 settings for rd_vref @@ -1466,63 +1467,63 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba) // slew_imp_val[SLEW_TYPE_DATA][IMP][j]); } // Get desired ADR control slew rate & impedance from attribute - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_CNTL, &i_target_mba, + rc = FAPI_ATTR_GET(ATTR_VPD_CEN_SLEW_RATE_CNTL, &i_target_mba, slew_imp_val[SLEW_TYPE_ADR_CNTL][SLEW]); if (rc) { - FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_SLEW_RATE_CNTL"); + FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_SLEW_RATE_CNTL"); return rc; } - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_CNTL, &i_target_mba, + rc = FAPI_ATTR_GET(ATTR_VPD_CEN_DRV_IMP_CNTL, &i_target_mba, slew_imp_val[SLEW_TYPE_ADR_CNTL][IMP]); if (rc) { - FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_DRV_IMP_CNTL"); + FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_DRV_IMP_CNTL"); return rc; } // Get desired ADR command slew rate & impedance from attribute - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_ADDR, &i_target_mba, + rc = FAPI_ATTR_GET(ATTR_VPD_CEN_SLEW_RATE_ADDR, &i_target_mba, slew_imp_val[SLEW_TYPE_ADR_ADDR][SLEW]); if (rc) { - FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_SLEW_RATE_ADDR"); + FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_SLEW_RATE_ADDR"); return rc; } - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_ADDR, &i_target_mba, + rc = FAPI_ATTR_GET(ATTR_VPD_CEN_DRV_IMP_ADDR, &i_target_mba, slew_imp_val[SLEW_TYPE_ADR_ADDR][IMP]); if (rc) { - FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_DRV_IMP_ADDR"); + FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_DRV_IMP_ADDR"); return rc; } // Get desired ADR clock slew rate & impedance from attribute - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_CLK, &i_target_mba, + rc = FAPI_ATTR_GET(ATTR_VPD_CEN_SLEW_RATE_CLK, &i_target_mba, slew_imp_val[SLEW_TYPE_ADR_CLK][SLEW]); if (rc) { - FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_SLEW_RATE_CLK"); + FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_SLEW_RATE_CLK"); return rc; } - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_CLK, &i_target_mba, + rc = FAPI_ATTR_GET(ATTR_VPD_CEN_DRV_IMP_CLK, &i_target_mba, slew_imp_val[SLEW_TYPE_ADR_CLK][IMP]); if (rc) { - FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_DRV_IMP_CLK"); + FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_DRV_IMP_CLK"); return rc; } // Get desired ADR Spare clock slew rate & impedance from attribute - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_SPCKE, &i_target_mba, + rc = FAPI_ATTR_GET(ATTR_VPD_CEN_SLEW_RATE_SPCKE, &i_target_mba, slew_imp_val[SLEW_TYPE_ADR_SPCKE][SLEW]); if (rc) { - FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_SLEW_RATE_SPCKE"); + FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_SLEW_RATE_SPCKE"); return rc; } - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_SPCKE, &i_target_mba, + rc = FAPI_ATTR_GET(ATTR_VPD_CEN_DRV_IMP_SPCKE, &i_target_mba, slew_imp_val[SLEW_TYPE_ADR_SPCKE][IMP]); if (rc) { - FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_DRV_IMP_SPCKE"); + FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_DRV_IMP_SPCKE"); return rc; } diff --git a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile index 95e3424fb..8dd1d6bc8 100755 --- a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile +++ b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile @@ -1,4 +1,4 @@ -#-- $Id: cen_ddrphy.initfile,v 1.27 2013/11/01 19:40:50 mwuu Exp $ +#-- $Id: cen_ddrphy.initfile,v 1.28 2013/12/02 21:15:01 asaetow Exp $ #-- $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/ #-- centaur/working/procedures/ec_ind/scoms/cen_ddrphy.initfile,v $ # @@ -6,7 +6,8 @@ #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- -# 1.28|mwuu |11/01/13|Had a typo for ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8, +# 1.28|mwuu |11/22/13|Update for VPD attributes +# 1.27|mwuu |11/01/13|Had a typo for ATTR_VPD_CEN_PHASE_ROT_M_CMD_A8, # |port A was getting the value of A9 phase rotator. # |Using attribute settings for GPO,RLO,WLO for LRDIMM # 1.27|mwuu |08/22/13|Changed RLO/GPO settings for LRDIMM to be picked up @@ -15,7 +16,7 @@ # | | |type1 define to use CUSTOM attribute as well. # | | |Changed READ_CLOCK section to enable clocks for x4. #-- 1.25|mwuu |05/08/13|Fixed change in DDR4/DDR3 DIMM type -#-- 1.24|mwuu |04/19/13|Changed to use ATTR_EFF_DIMM_SPARE instead of CDIMM +#-- 1.24|mwuu |04/19/13|Changed to use ATTR_VPD_DIMM_SPARE instead of CDIMM #-- 1.23|mwuu |04/09/13|Fixed typo ENUM for 2N mode. #-- 1.22|mwuu |04/04/13|Updated tODTL definition when AL=0, added 2N support # |changed for LRDIMM: RLO=6, WLO=-1; DDR4 UDIMM mem type @@ -101,16 +102,16 @@ define def_is_sim = (SYS.ATTR_IS_SIMULATION == 1) ; # FAST_SIM_PER_CNTR for periodic calibrations define def_FAST_SIM_PC = (SYS.ATTR_IS_SIMULATION == 1) ; -# for real HW uncomment, !!FIX once ATTR_EFF_DIMM_SPARE available [2][4][4] port, dimm, rank -define def_p0_has_spare_full = (ATTR_EFF_DIMM_SPARE[0][0][0] == ENUM_ATTR_EFF_DIMM_SPARE_FULL_BYTE) ; # spare byte -define def_p0_has_spare_upper = (ATTR_EFF_DIMM_SPARE[0][0][0] == ENUM_ATTR_EFF_DIMM_SPARE_HIGH_NIBBLE) ; # upper nibble -define def_p0_has_spare_lower = (ATTR_EFF_DIMM_SPARE[0][0][0] == ENUM_ATTR_EFF_DIMM_SPARE_LOW_NIBBLE) ; # lower nibble -define def_p0_no_spare = (ATTR_EFF_DIMM_SPARE[0][0][0] == ENUM_ATTR_EFF_DIMM_SPARE_NO_SPARE) ; # no spare +# for real HW uncomment, !!FIX once ATTR_VPD_DIMM_SPARE available [2][4][4] port, dimm, rank +define def_p0_has_spare_full = (ATTR_VPD_DIMM_SPARE[0][0][0] == ENUM_ATTR_VPD_DIMM_SPARE_FULL_BYTE) ; # spare byte +define def_p0_has_spare_upper = (ATTR_VPD_DIMM_SPARE[0][0][0] == ENUM_ATTR_VPD_DIMM_SPARE_HIGH_NIBBLE) ; # upper nibble +define def_p0_has_spare_lower = (ATTR_VPD_DIMM_SPARE[0][0][0] == ENUM_ATTR_VPD_DIMM_SPARE_LOW_NIBBLE) ; # lower nibble +define def_p0_no_spare = (ATTR_VPD_DIMM_SPARE[0][0][0] == ENUM_ATTR_VPD_DIMM_SPARE_NO_SPARE) ; # no spare -define def_p1_has_spare_full = (ATTR_EFF_DIMM_SPARE[1][0][0] == ENUM_ATTR_EFF_DIMM_SPARE_FULL_BYTE) ; # spare byte -define def_p1_has_spare_upper = (ATTR_EFF_DIMM_SPARE[1][0][0] == ENUM_ATTR_EFF_DIMM_SPARE_HIGH_NIBBLE) ; # upper nibble -define def_p1_has_spare_lower = (ATTR_EFF_DIMM_SPARE[1][0][0] == ENUM_ATTR_EFF_DIMM_SPARE_LOW_NIBBLE) ; # lower nibble -define def_p1_no_spare = (ATTR_EFF_DIMM_SPARE[1][0][0] == ENUM_ATTR_EFF_DIMM_SPARE_NO_SPARE) ; # no spare +define def_p1_has_spare_full = (ATTR_VPD_DIMM_SPARE[1][0][0] == ENUM_ATTR_VPD_DIMM_SPARE_FULL_BYTE) ; # spare byte +define def_p1_has_spare_upper = (ATTR_VPD_DIMM_SPARE[1][0][0] == ENUM_ATTR_VPD_DIMM_SPARE_HIGH_NIBBLE) ; # upper nibble +define def_p1_has_spare_lower = (ATTR_VPD_DIMM_SPARE[1][0][0] == ENUM_ATTR_VPD_DIMM_SPARE_LOW_NIBBLE) ; # lower nibble +define def_p1_no_spare = (ATTR_VPD_DIMM_SPARE[1][0][0] == ENUM_ATTR_VPD_DIMM_SPARE_NO_SPARE) ; # no spare # ports 0,1 must have functional dimms to be valid define def_valid_p0 = (ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR >> 4); # ((def_is_mba01) || (def_is_mba23)) && @@ -244,48 +245,48 @@ define def_ffe3_p1 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_I define def_ffe4_p1 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE120) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE120) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE120)) ; # shorter test for Centaur driver impedance command/address (A0:15, BA0:3, ACT, PAR, CAS, RAS, WE) -define def_cdi_addr_ohm15_p0= (ATTR_EFF_CEN_DRV_IMP_ADDR[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM15) ; # OHM15 = 0x0F (15) -define def_cdi_addr_ohm20_p0= (ATTR_EFF_CEN_DRV_IMP_ADDR[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20) ; # OHM20 = 0x14 (20) -define def_cdi_addr_ohm30_p0= (ATTR_EFF_CEN_DRV_IMP_ADDR[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30) ; # OHM30 = 0x1E (30) -define def_cdi_addr_ohm40_p0= (ATTR_EFF_CEN_DRV_IMP_ADDR[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40) ; # OHM40 = 0x28 (40) +define def_cdi_addr_ohm15_p0= (ATTR_VPD_CEN_DRV_IMP_ADDR[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM15) ; # OHM15 = 0x0F (15) +define def_cdi_addr_ohm20_p0= (ATTR_VPD_CEN_DRV_IMP_ADDR[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM20) ; # OHM20 = 0x14 (20) +define def_cdi_addr_ohm30_p0= (ATTR_VPD_CEN_DRV_IMP_ADDR[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM30) ; # OHM30 = 0x1E (30) +define def_cdi_addr_ohm40_p0= (ATTR_VPD_CEN_DRV_IMP_ADDR[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40) ; # OHM40 = 0x28 (40) -define def_cdi_addr_ohm15_p1= (ATTR_EFF_CEN_DRV_IMP_ADDR[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM15) ; # OHM15 = 0x0F (15) -define def_cdi_addr_ohm20_p1= (ATTR_EFF_CEN_DRV_IMP_ADDR[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20) ; # OHM20 = 0x14 (20) -define def_cdi_addr_ohm30_p1= (ATTR_EFF_CEN_DRV_IMP_ADDR[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30) ; # OHM30 = 0x1E (30) -define def_cdi_addr_ohm40_p1= (ATTR_EFF_CEN_DRV_IMP_ADDR[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40) ; # OHM40 = 0x28 (40) +define def_cdi_addr_ohm15_p1= (ATTR_VPD_CEN_DRV_IMP_ADDR[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM15) ; # OHM15 = 0x0F (15) +define def_cdi_addr_ohm20_p1= (ATTR_VPD_CEN_DRV_IMP_ADDR[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM20) ; # OHM20 = 0x14 (20) +define def_cdi_addr_ohm30_p1= (ATTR_VPD_CEN_DRV_IMP_ADDR[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM30) ; # OHM30 = 0x1E (30) +define def_cdi_addr_ohm40_p1= (ATTR_VPD_CEN_DRV_IMP_ADDR[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40) ; # OHM40 = 0x28 (40) # shorter test for Centaur driver impedance control (CKE0:1, CKE4:5, ODT0:3, CSN0:7) -define def_cdi_ctl_ohm15_p0 = (ATTR_EFF_CEN_DRV_IMP_CNTL[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15) ; # OHM15 = 0x0F (15) -define def_cdi_ctl_ohm20_p0 = (ATTR_EFF_CEN_DRV_IMP_CNTL[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20) ; # OHM20 = 0x14 (20) -define def_cdi_ctl_ohm30_p0 = (ATTR_EFF_CEN_DRV_IMP_CNTL[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30) ; # OHM30 = 0x1E (30) -define def_cdi_ctl_ohm40_p0 = (ATTR_EFF_CEN_DRV_IMP_CNTL[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40) ; # OHM40 = 0x28 (40) +define def_cdi_ctl_ohm15_p0 = (ATTR_VPD_CEN_DRV_IMP_CNTL[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM15) ; # OHM15 = 0x0F (15) +define def_cdi_ctl_ohm20_p0 = (ATTR_VPD_CEN_DRV_IMP_CNTL[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM20) ; # OHM20 = 0x14 (20) +define def_cdi_ctl_ohm30_p0 = (ATTR_VPD_CEN_DRV_IMP_CNTL[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM30) ; # OHM30 = 0x1E (30) +define def_cdi_ctl_ohm40_p0 = (ATTR_VPD_CEN_DRV_IMP_CNTL[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40) ; # OHM40 = 0x28 (40) -define def_cdi_ctl_ohm15_p1 = (ATTR_EFF_CEN_DRV_IMP_CNTL[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15) ; # OHM15 = 0x0F (15) -define def_cdi_ctl_ohm20_p1 = (ATTR_EFF_CEN_DRV_IMP_CNTL[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20) ; # OHM20 = 0x14 (20) -define def_cdi_ctl_ohm30_p1 = (ATTR_EFF_CEN_DRV_IMP_CNTL[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30) ; # OHM30 = 0x1E (30) -define def_cdi_ctl_ohm40_p1 = (ATTR_EFF_CEN_DRV_IMP_CNTL[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40) ; # OHM40 = 0x28 (40) +define def_cdi_ctl_ohm15_p1 = (ATTR_VPD_CEN_DRV_IMP_CNTL[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM15) ; # OHM15 = 0x0F (15) +define def_cdi_ctl_ohm20_p1 = (ATTR_VPD_CEN_DRV_IMP_CNTL[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM20) ; # OHM20 = 0x14 (20) +define def_cdi_ctl_ohm30_p1 = (ATTR_VPD_CEN_DRV_IMP_CNTL[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM30) ; # OHM30 = 0x1E (30) +define def_cdi_ctl_ohm40_p1 = (ATTR_VPD_CEN_DRV_IMP_CNTL[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40) ; # OHM40 = 0x28 (40) # shorter test for Centaur driver impedance clocks (CLK0:3) -define def_cdi_clk_ohm15_p0 = (ATTR_EFF_CEN_DRV_IMP_CLK[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM15) ; # OHM15 = 0x0F (15) -define def_cdi_clk_ohm20_p0 = (ATTR_EFF_CEN_DRV_IMP_CLK[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20) ; # OHM20 = 0x14 (20) -define def_cdi_clk_ohm30_p0 = (ATTR_EFF_CEN_DRV_IMP_CLK[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30) ; # OHM30 = 0x1E (30) -define def_cdi_clk_ohm40_p0 = (ATTR_EFF_CEN_DRV_IMP_CLK[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40) ; # OHM40 = 0x28 (40) +define def_cdi_clk_ohm15_p0 = (ATTR_VPD_CEN_DRV_IMP_CLK[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM15) ; # OHM15 = 0x0F (15) +define def_cdi_clk_ohm20_p0 = (ATTR_VPD_CEN_DRV_IMP_CLK[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM20) ; # OHM20 = 0x14 (20) +define def_cdi_clk_ohm30_p0 = (ATTR_VPD_CEN_DRV_IMP_CLK[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM30) ; # OHM30 = 0x1E (30) +define def_cdi_clk_ohm40_p0 = (ATTR_VPD_CEN_DRV_IMP_CLK[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40) ; # OHM40 = 0x28 (40) -define def_cdi_clk_ohm15_p1 = (ATTR_EFF_CEN_DRV_IMP_CLK[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM15) ; # OHM15 = 0x0F (15) -define def_cdi_clk_ohm20_p1 = (ATTR_EFF_CEN_DRV_IMP_CLK[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20) ; # OHM20 = 0x14 (20) -define def_cdi_clk_ohm30_p1 = (ATTR_EFF_CEN_DRV_IMP_CLK[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30) ; # OHM30 = 0x1E (30) -define def_cdi_clk_ohm40_p1 = (ATTR_EFF_CEN_DRV_IMP_CLK[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40) ; # OHM40 = 0x28 (40) +define def_cdi_clk_ohm15_p1 = (ATTR_VPD_CEN_DRV_IMP_CLK[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM15) ; # OHM15 = 0x0F (15) +define def_cdi_clk_ohm20_p1 = (ATTR_VPD_CEN_DRV_IMP_CLK[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM20) ; # OHM20 = 0x14 (20) +define def_cdi_clk_ohm30_p1 = (ATTR_VPD_CEN_DRV_IMP_CLK[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM30) ; # OHM30 = 0x1E (30) +define def_cdi_clk_ohm40_p1 = (ATTR_VPD_CEN_DRV_IMP_CLK[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40) ; # OHM40 = 0x28 (40) # shorter test for Centaur driver impedance spare clocks (CKE2:3, CKE6:7) -define def_cdi_spcke_ohm15_p0 = (ATTR_EFF_CEN_DRV_IMP_SPCKE[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM15) ; # OHM15 = 0x0F (15) -define def_cdi_spcke_ohm20_p0 = (ATTR_EFF_CEN_DRV_IMP_SPCKE[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM20) ; # OHM20 = 0x14 (20) -define def_cdi_spcke_ohm30_p0 = (ATTR_EFF_CEN_DRV_IMP_SPCKE[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM30) ; # OHM30 = 0x1E (30) -define def_cdi_spcke_ohm40_p0 = (ATTR_EFF_CEN_DRV_IMP_SPCKE[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40) ; # OHM40 = 0x28 (40) +define def_cdi_spcke_ohm15_p0 = (ATTR_VPD_CEN_DRV_IMP_SPCKE[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM15) ; # OHM15 = 0x0F (15) +define def_cdi_spcke_ohm20_p0 = (ATTR_VPD_CEN_DRV_IMP_SPCKE[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM20) ; # OHM20 = 0x14 (20) +define def_cdi_spcke_ohm30_p0 = (ATTR_VPD_CEN_DRV_IMP_SPCKE[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM30) ; # OHM30 = 0x1E (30) +define def_cdi_spcke_ohm40_p0 = (ATTR_VPD_CEN_DRV_IMP_SPCKE[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40) ; # OHM40 = 0x28 (40) -define def_cdi_spcke_ohm15_p1 = (ATTR_EFF_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM15) ; # OHM15 = 0x0F (15) -define def_cdi_spcke_ohm20_p1 = (ATTR_EFF_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM20) ; # OHM20 = 0x14 (20) -define def_cdi_spcke_ohm30_p1 = (ATTR_EFF_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM30) ; # OHM30 = 0x1E (30) -define def_cdi_spcke_ohm40_p1 = (ATTR_EFF_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40) ; # OHM40 = 0x28 (40) +define def_cdi_spcke_ohm15_p1 = (ATTR_VPD_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM15) ; # OHM15 = 0x0F (15) +define def_cdi_spcke_ohm20_p1 = (ATTR_VPD_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM20) ; # OHM20 = 0x14 (20) +define def_cdi_spcke_ohm30_p1 = (ATTR_VPD_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM30) ; # OHM30 = 0x1E (30) +define def_cdi_spcke_ohm40_p1 = (ATTR_VPD_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40) ; # OHM40 = 0x28 (40) # define for glacier1(1), glacier2=normal(0) remove dimm_type != cdimm later define def_is_type1 = ((ATTR_MSS_DQS_SWIZZLE_TYPE == 1) && ((ATTR_EFF_CUSTOM_DIMM != ENUM_ATTR_EFF_CUSTOM_DIMM_YES) || (ATTR_EFF_DIMM_TYPE != ENUM_ATTR_EFF_DIMM_TYPE_CDIMM))); @@ -294,11 +295,11 @@ define def_is_type1 = ((ATTR_MSS_DQS_SWIZZLE_TYPE == 1) && ((ATTR_EFF_CUSTOM_DIM define def_is_custom = ((ATTR_EFF_CUSTOM_DIMM == ENUM_ATTR_EFF_CUSTOM_DIMM_YES) || (ATTR_EFF_DIMM_TYPE == ENUM_ATTR_EFF_DIMM_TYPE_CDIMM)); # define for 2 cycle addressing mode (2N) -define def_2N_mode = (ATTR_EFF_DRAM_2N_MODE_ENABLED == ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_TRUE) ; +define def_2N_mode = (ATTR_VPD_DRAM_2N_MODE_ENABLED == ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_TRUE) ; # fix phase rotators due to NWELL issue #define def_CL_adj = (CEN.ATTR_MSS_NWELL_MISPLACEMENT * 0x7F); -# 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0[0] | (def_CL_adj)) , (def_is_mba01) ; # P0 L1 , A_A0 centerlane +# 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A0[0] | (def_CL_adj)) , (def_is_mba01) ; # P0 L1 , A_A0 centerlane #define def_PR_adj = (CEN.ATTR_MSS_NWELL_MISPLACEMENT * 32); # SIMPLIFY @@ -429,14 +430,14 @@ scom 0x8000C00D0301143F { # # WLO is normally 0 except for RDIMM (RCD) configurations in which case it's set to 1 # DD0 = PORT_BUFFER_LATENCY 48:51 , 0xF , (def_is_lrdimm) ; # LRDIMM set WLO=-1 - 48:51 , (ATTR_EFF_WLO[0]), any ; # based on attribute now.. + 48:51 , (ATTR_VPD_WLO[0]), any ; # based on attribute now.. # 48:51 , 0x1 , (def_is_rdimm) ; # RDIMM # 48:51 , 0x0 , any ; # WLO=WRITE_LATENCY_OFFSET (2's complement -8 to 7) # # 9.4.12.2 RLO = READ_LATENCY_OFFSET (2's complement -8 to 7) {0=CDIMM, 1=RDIMM, 2=LRDIMM} # 52:55 , 0x1 , (def_is_rdimm) ; # RDIMM # 52:55 , 0x0 , any ; # CDIMM/UDIMM # 52:55 , 0x6 , (def_is_lrdimm) ; # LRDIMM # !! need to review LR settings !! - 52:55 , (ATTR_EFF_RLO[0]), any ; # based on attribute now.. + 52:55 , (ATTR_VPD_RLO[0]), any ; # based on attribute now.. 56 , 0b0 , any ; # MEMCTL_CIC_FAST 57 , 0b0 , any ; # MEMCTL_CTRN_IGNORE 58 , 0b0 , any ; # DISABLE_MEMCTL_CAL @@ -467,12 +468,12 @@ scom 0x8001C00D0301143F { # # WLO is normally 0 except for RDIMM (RCD) configurations in which case it's set to 1 # DD0 = PORT_BUFFER_LATENCY 48:51 , 0xF , (def_is_lrdimm) ; # LRDIMM set WLO=-1 - 48:51 , (ATTR_EFF_WLO[1]), any ; # based on attribute now.. + 48:51 , (ATTR_VPD_WLO[1]), any ; # based on attribute now.. # 48:51 , 0x1 , (def_is_rdimm) ; # RDIMM # 48:51 , 0x0 , any ; # WLO=WRITE_LATENCY_OFFSET (2's complement -8 to 7) # # 9.4.12.2 RLO = READ_LATENCY_OFFSET (2's complement -8 to 7) {0=CDIMM, 1=RDIMM, 2=LRDIMM} 52:55 , 0x6 , (def_is_lrdimm) ; # LRDIMM - 52:55 , (ATTR_EFF_RLO[1]), any ; # based on attribute now.. + 52:55 , (ATTR_VPD_RLO[1]), any ; # based on attribute now.. # 52:55 , 0x1 , (def_is_rdimm) ; # RDIMM # 52:55 , 0x0 , any ; # CDIMM/UDIMM 56 , 0b0 , any ; # MEMCTL_CIC_FAST @@ -976,7 +977,7 @@ scom 0x80013C7(8,9)0301143F { # [N:P]FET_SLICE_P1_[0:4] broadcast # CNTL = cke, clk, cs, odt # # ATTR_EFF_CEN_DRV_IMP_CMD 15,20,30,40 -# ATTR_EFF_CEN_DRV_IMP_CNTL 15,20,30,40 +# ATTR_VPD_CEN_DRV_IMP_CNTL 15,20,30,40 # # SEL# impedance # 00b = 15 ohm, @@ -1970,13 +1971,13 @@ scom 0x80014c210301143f { # bits , scom_data , expr ; ## 0:47 , 0x000000000000, any ; # reserved # SLEW_CTL0, used for command (A0:15, BA0:3, ACT, PAR, CAS, RAS, WE) -# 48:51 , 0b0000 , (ATTR_EFF_CEN_SLEW_RATE_ADDR[0]) ; +# 48:51 , 0b0000 , (ATTR_VPD_CEN_SLEW_RATE_ADDR[0]) ; # SLEW_CTL1, used for control (CKE0:1, CKE4:5, ODT, CSN0:7) -# 52:55 , 0b0000 , (ATTR_EFF_CEN_SLEW_RATE_CNTL[0]) ; +# 52:55 , 0b0000 , (ATTR_VPD_CEN_SLEW_RATE_CNTL[0]) ; # SLEW_CTL2, used for clocks (CLK0:3) -# 56:59 , 0b0000 , (ATTR_EFF_CEN_SLEW_RATE_CLK[0]) ; +# 56:59 , 0b0000 , (ATTR_VPD_CEN_SLEW_RATE_CLK[0]) ; # SLEW_CTL3, used for spare drams (CKE2:3, CKE6:7) -# 60:63 , 0b0000 , (ATTR_EFF_CEN_SLEW_RATE_SPCKE[0) ; +# 60:63 , 0b0000 , (ATTR_VPD_CEN_SLEW_RATE_SPCKE[0) ; #} #********************************************************************************** @@ -2775,7 +2776,7 @@ scom 0x8001c4010301143f { # 56:63 are ODT pins 0-7 (bit8-15) during read of rank {0-3}*2+1 # # bit#=odt# 0..1 0..1 0..3 ODT0:1 ODT2:3 ODT4:5 ODT6:7 -# ATTR_EFF_ODT_RD[port][dimm][rank] = dimm0 dimm1 dimm2 unused; +# ATTR_VPD_ODT_RD[port][dimm][rank] = dimm0 dimm1 dimm2 unused; # bits 0:1 2:3 4:5 6:7 # # DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG0_P0 0x00E 0x8000c40e0301143f @@ -2784,122 +2785,122 @@ scom 0x8000C40E0301143F { # ODT 01234567 bits , scom_data ; # DIMM0, Port0 # 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_EFF_ODT_RD[0][0][0] ; # when Read of Rank0 - 56:63 , ATTR_EFF_ODT_RD[0][0][1] ; # when Read of Rank1 + 48:55 , ATTR_VPD_ODT_RD[0][0][0] ; # when Read of Rank0 + 56:63 , ATTR_VPD_ODT_RD[0][0][1] ; # when Read of Rank1 } # DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG1_P0 scom 0x8000C40F0301143F { bits , scom_data ; # DIMM0, Port0 # 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_EFF_ODT_RD[0][0][2] ; # when Read of Rank2 - 56:63 , ATTR_EFF_ODT_RD[0][0][3] ; # when Read of Rank3 + 48:55 , ATTR_VPD_ODT_RD[0][0][2] ; # when Read of Rank2 + 56:63 , ATTR_VPD_ODT_RD[0][0][3] ; # when Read of Rank3 } # DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG2_P0 scom 0x8000C4100301143F { bits , scom_data ; # DIMM1, Port0 # 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_EFF_ODT_RD[0][1][0] ; # when Read of Rank4 - 56:63 , ATTR_EFF_ODT_RD[0][1][1] ; # when Read of Rank5 + 48:55 , ATTR_VPD_ODT_RD[0][1][0] ; # when Read of Rank4 + 56:63 , ATTR_VPD_ODT_RD[0][1][1] ; # when Read of Rank5 } # DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG3_P0 scom 0x8000C4110301143F { bits , scom_data ; # DIMM1, Port0 # 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_EFF_ODT_RD[0][1][2] ; # when Read of Rank6 - 56:63 , ATTR_EFF_ODT_RD[0][1][3] ; # when Read of Rank7 + 48:55 , ATTR_VPD_ODT_RD[0][1][2] ; # when Read of Rank6 + 56:63 , ATTR_VPD_ODT_RD[0][1][3] ; # when Read of Rank7 } # ------- Read ODT Port 1 (DIMM2 & DIMM3) ---------------------------------- # DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG0_P1 scom 0x8001C40E0301143F { bits , scom_data ; # DIMM2, Port1 # 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_EFF_ODT_RD[1][0][0] ; # when Read of Rank0 - 56:63 , ATTR_EFF_ODT_RD[1][0][1] ; # when Read of Rank1 + 48:55 , ATTR_VPD_ODT_RD[1][0][0] ; # when Read of Rank0 + 56:63 , ATTR_VPD_ODT_RD[1][0][1] ; # when Read of Rank1 } # DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG1_P1 scom 0x8001C40F0301143F { bits , scom_data ; # DIMM2, Port1 # 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_EFF_ODT_RD[1][0][2] ; # when Read of Rank2 - 56:63 , ATTR_EFF_ODT_RD[1][0][3] ; # when Read of Rank3 + 48:55 , ATTR_VPD_ODT_RD[1][0][2] ; # when Read of Rank2 + 56:63 , ATTR_VPD_ODT_RD[1][0][3] ; # when Read of Rank3 } # DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG2_P1 scom 0x8001C4100301143F { bits , scom_data ; # DIMM3, Port1 # 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_EFF_ODT_RD[1][1][0] ; # when Read of Rank4 - 56:63 , ATTR_EFF_ODT_RD[1][1][1] ; # when Read of Rank5 + 48:55 , ATTR_VPD_ODT_RD[1][1][0] ; # when Read of Rank4 + 56:63 , ATTR_VPD_ODT_RD[1][1][1] ; # when Read of Rank5 } # DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG3_P1 scom 0x8001C4110301143F { bits , scom_data ; # DIMM3, Port1 # 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_EFF_ODT_RD[1][1][2] ; # when Read of Rank6 - 56:63 , ATTR_EFF_ODT_RD[1][1][3] ; # when Read of Rank7 + 48:55 , ATTR_VPD_ODT_RD[1][1][2] ; # when Read of Rank6 + 56:63 , ATTR_VPD_ODT_RD[1][1][3] ; # when Read of Rank7 } #================================================================================ # ODT write registers default=0 # # bit#=odt# 0..1 0..1 0..3 ODT0:1 ODT2:3 ODT4:5 ODT6:7 -# ATTR_EFF_ODT_WR[port][dimm][rank] = dimm0 dimm1 dimm2 unused ; +# ATTR_VPD_ODT_WR[port][dimm][rank] = dimm0 dimm1 dimm2 unused ; # # DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG0_P0 0x000A 0x8000c40a0301143f # PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.ODT_WR_CONFIG0_L2 scom 0x8000C40A0301143F { bits , scom_data ; # DIMM0, Port0 # 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_EFF_ODT_WR[0][0][0] ; # when write of Rank0 - 56:63 , ATTR_EFF_ODT_WR[0][0][1] ; # when write of Rank1 + 48:55 , ATTR_VPD_ODT_WR[0][0][0] ; # when write of Rank0 + 56:63 , ATTR_VPD_ODT_WR[0][0][1] ; # when write of Rank1 } # DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG1_P0 scom 0x8000C40B0301143F { bits , scom_data ; # DIMM0, Port0 # 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_EFF_ODT_WR[0][0][2] ; # when write of Rank2 - 56:63 , ATTR_EFF_ODT_WR[0][0][3] ; # when write of Rank3 + 48:55 , ATTR_VPD_ODT_WR[0][0][2] ; # when write of Rank2 + 56:63 , ATTR_VPD_ODT_WR[0][0][3] ; # when write of Rank3 } # DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG2_P0 scom 0x8000C40C0301143F { bits , scom_data ; # DIMM1, Port0 # 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_EFF_ODT_WR[0][1][0] ; # when write of Rank4 - 56:63 , ATTR_EFF_ODT_WR[0][1][1] ; # when write of Rank5 + 48:55 , ATTR_VPD_ODT_WR[0][1][0] ; # when write of Rank4 + 56:63 , ATTR_VPD_ODT_WR[0][1][1] ; # when write of Rank5 } # DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG3_P0 scom 0x8000C40D0301143F { bits , scom_data ; # DIMM1, Port0 # 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_EFF_ODT_WR[0][1][2] ; # when write of Rank6 - 56:63 , ATTR_EFF_ODT_WR[0][1][3] ; # when write of Rank7 + 48:55 , ATTR_VPD_ODT_WR[0][1][2] ; # when write of Rank6 + 56:63 , ATTR_VPD_ODT_WR[0][1][3] ; # when write of Rank7 } # ------- Write ODT Port 1 (DIMM2 & DIMM3) ---------------------------------- # DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG0_P1 scom 0x8001C40A0301143F { bits , scom_data ; # DIMM2, Port1 # 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_EFF_ODT_WR[1][0][0] ; # when write of Rank0 - 56:63 , ATTR_EFF_ODT_WR[1][0][1] ; # when write of Rank1 + 48:55 , ATTR_VPD_ODT_WR[1][0][0] ; # when write of Rank0 + 56:63 , ATTR_VPD_ODT_WR[1][0][1] ; # when write of Rank1 } # DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG1_P1 scom 0x8001C40B0301143F { bits , scom_data ; # DIMM2, Port1 # 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_EFF_ODT_WR[1][0][2] ; # when write of Rank2 - 56:63 , ATTR_EFF_ODT_WR[1][0][3] ; # when write of Rank3 + 48:55 , ATTR_VPD_ODT_WR[1][0][2] ; # when write of Rank2 + 56:63 , ATTR_VPD_ODT_WR[1][0][3] ; # when write of Rank3 } # DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG2_P1 scom 0x8001C40C0301143F { bits , scom_data ; # DIMM3, Port1 # 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_EFF_ODT_WR[1][1][0] ; # when write of Rank4 - 56:63 , ATTR_EFF_ODT_WR[1][1][1] ; # when write of Rank5 + 48:55 , ATTR_VPD_ODT_WR[1][1][0] ; # when write of Rank4 + 56:63 , ATTR_VPD_ODT_WR[1][1][1] ; # when write of Rank5 } # DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG3_P1 scom 0x8001C40D0301143F { bits , scom_data ; # DIMM3, Port1 # 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_EFF_ODT_WR[1][1][2] ; # when write of Rank6 - 56:63 , ATTR_EFF_ODT_WR[1][1][3] ; # when write of Rank7 + 48:55 , ATTR_VPD_ODT_WR[1][1][2] ; # when write of Rank6 + 56:63 , ATTR_VPD_ODT_WR[1][1][3] ; # when write of Rank7 } # --------------------------------------------------------------------------------------- @@ -3763,7 +3764,7 @@ scom 0x8000C8000301143F { # _P0 # min GPO = 5 + max(rndUp(System_delay)) - RLO + ADVANCE_RD_VALID + SPAM_EN # max GPO = 11 if in 2:1, 13 if in 4:1 # 48:51 , 0b0111 , (def_is_lrdimm) ; # GLOBAL_PHY_OFFSET LRDIMM set to 7 # need to review LR settings - 48:51 , (ATTR_EFF_GPO[0]), any ; # GLOBAL_PHY_OFFSET (GPO), based on attribute now + 48:51 , (ATTR_VPD_GPO[0]), any ; # GLOBAL_PHY_OFFSET (GPO), based on attribute now # 48:51 , 0b0101 , any ; # GLOBAL_PHY_OFFSET (GPO), ideally 2:1 max=11, 4:1 max=13 52 , 0b0 , any ; # ADVANCE_RD_VALID ask Yuen 53 , 0b0 , any ; # PER_DUTY_CYCLE_SW, 0=rd cmds 50% duty cycle during per.cal, 1=continuously @@ -3792,7 +3793,7 @@ scom 0x8001C8000301143F { # _P1 # min GPO = 5 + max(rndUp(System_delay)) - RLO + ADVANCE_RD_VALID + SPAM_EN # max GPO = 11 if in 2:1, 13 if in 4:1 48:51 , 0b0111 , (def_is_lrdimm) ; # GLOBAL_PHY_OFFSET LRDIMM set to 7 - 48:51 , (ATTR_EFF_GPO[1]), any ; # GLOBAL_PHY_OFFSET (GPO), based on attribute now + 48:51 , (ATTR_VPD_GPO[1]), any ; # GLOBAL_PHY_OFFSET (GPO), based on attribute now # 48:51 , 0b0101 , any ; # GLOBAL_PHY_OFFSET (GPO), ideally 2:1 max=11, 4:1 max=13 52 , 0b0 , any ; # ADVANCE_RD_VALID ask Yuen 53 , 0b0 , any ; # PER_DUTY_CYCLE_SW, 0=rd cmds 50% duty cycle during per.cal, 1=continuously @@ -4422,213 +4423,213 @@ scom 0x800(048,04C,148,14C)000301143F { # _P[0:1]_ADR[2:3] scom 0x800040040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P0_ADR0 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1[0]) , (def_is_mba01) ; # P0 L0 , A1_CKE1 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3[0]) , (def_is_mba01) ; # P0 L1 , A0_CS3n - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0[0]) , (def_is_mba23) ; # P2 L0 , C0_CS0n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3[0]) , (def_is_mba23) ; # P2 L1 , C_A3 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE1[0]) , (def_is_mba01) ; # P0 L0 , A1_CKE1 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN3[0]) , (def_is_mba01) ; # P0 L1 , A0_CS3n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN0[0]) , (def_is_mba23) ; # P2 L0 , C0_CS0n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A3[0]) , (def_is_mba23) ; # P2 L1 , C_A3 } scom 0x800040050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P0_ADR0 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0[0]) , (def_is_mba01) ; # P0 L2 , A1_CKE0 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0[0]) , (def_is_mba01) ; # P0 L3 , A0_ODT0 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3[0]) , (def_is_mba23) ; # P2 L2 , C1_CS3n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN[0]) , (def_is_mba23) ; # P2 L3 , C_RASn + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE0[0]) , (def_is_mba01) ; # P0 L2 , A1_CKE0 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT0[0]) , (def_is_mba01) ; # P0 L3 , A0_ODT0 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN3[0]) , (def_is_mba23) ; # P2 L2 , C1_CS3n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_RASN[0]) , (def_is_mba23) ; # P2 L3 , C_RASn } scom 0x800040060301143F { # DPHY01_DDRPHY_ADR_DELAY2_P0_ADR0 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15[0]) , (def_is_mba01) ; # P0 L4 , A_A15 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_PAR[0]) , (def_is_mba01) ; # P0 L5 , A_PAR - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12[0]) , (def_is_mba23) ; # P2 L4 , C_A12 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7[0]) , (def_is_mba23) ; # P2 L5 , C_A7 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A15[0]) , (def_is_mba01) ; # P0 L4 , A_A15 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_PAR[0]) , (def_is_mba01) ; # P0 L5 , A_PAR + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A12[0]) , (def_is_mba23) ; # P2 L4 , C_A12 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A7[0]) , (def_is_mba23) ; # P2 L5 , C_A7 } scom 0x800040070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P0_ADR0 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1[0]) , (def_is_mba01) ; # P0 L6 , A0_CKE1 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1[0]) , (def_is_mba01) ; # P0 L7 , A0_CS1n - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[0]) , (def_is_mba23) ; # P2 L6 , C0_CLK1_p - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[0]) , (def_is_mba23) ; # P2 L7 , C0_CLK1_n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE1[0]) , (def_is_mba01) ; # P0 L6 , A0_CKE1 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN1[0]) , (def_is_mba01) ; # P0 L7 , A0_CS1n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1[0]) , (def_is_mba23) ; # P2 L6 , C0_CLK1_p + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1[0]) , (def_is_mba23) ; # P2 L7 , C0_CLK1_n } scom 0x800040080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P0_ADR0 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0[0]) , (def_is_mba01) ; # P0 L8 , A0_CKE0 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0[0]) , (def_is_mba01) ; # P0 L9 , A1_ODT0 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[0]) , (def_is_mba23) ; # P2 L8 , C1_CLK1_p - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[0]) , (def_is_mba23) ; # P2 L9 , C1_CLK1_n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE0[0]) , (def_is_mba01) ; # P0 L8 , A0_CKE0 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT0[0]) , (def_is_mba01) ; # P0 L9 , A1_ODT0 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1[0]) , (def_is_mba23) ; # P2 L8 , C1_CLK1_p + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1[0]) , (def_is_mba23) ; # P2 L9 , C1_CLK1_n } scom 0x800040090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P0_ADR0 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[0]) , (def_is_mba01) ; # P0 L10, A0_CLK0_p - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[0]) , (def_is_mba01) ; # P0 L11, A0_CLK0_n - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2[0]) , (def_is_mba23) ; # P2 L10, C1_CKE2 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2[0]) , (def_is_mba23) ; # P2 L11, C0_CKE2 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0[0]) , (def_is_mba01) ; # P0 L10, A0_CLK0_p + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0[0]) , (def_is_mba01) ; # P0 L11, A0_CLK0_n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE2[0]) , (def_is_mba23) ; # P2 L10, C1_CKE2 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE2[0]) , (def_is_mba23) ; # P2 L11, C0_CKE2 } #-- Port 0/2 ADR 1 ------------------------------------------------------------ scom 0x800044040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P0_ADR1 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0[0]) , (def_is_mba01) ; # P0 L0 , A0_CS0n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3[0]) , (def_is_mba01) ; # P0 L1 , A1_CKE3 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2[0]) , (def_is_mba23) ; # P2 L0 , C_BA2 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1[0]) , (def_is_mba23) ; # P2 L1 , C1_CKE1 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN0[0]) , (def_is_mba01) ; # P0 L0 , A0_CS0n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE3[0]) , (def_is_mba01) ; # P0 L1 , A1_CKE3 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA2[0]) , (def_is_mba23) ; # P2 L0 , C_BA2 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE1[0]) , (def_is_mba23) ; # P2 L1 , C1_CKE1 } scom 0x800044050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P0_ADR1 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1[0]) , (def_is_mba01) ; # P0 L2 , A1_ODT1 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2[0]) , (def_is_mba01) ; # P0 L3 , A_A2 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1[0]) , (def_is_mba23) ; # P2 L2 , C0_ODT1 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN[0]) , (def_is_mba23) ; # P2 L3 , C_WEn + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT1[0]) , (def_is_mba01) ; # P0 L2 , A1_ODT1 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A2[0]) , (def_is_mba01) ; # P0 L3 , A_A2 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT1[0]) , (def_is_mba23) ; # P2 L2 , C0_ODT1 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_WEN[0]) , (def_is_mba23) ; # P2 L3 , C_WEn } scom 0x800044060301143F { # DPHY01_DDRPHY_ADR_DELAY2_P0_ADR1 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6[0]) , (def_is_mba01) ; # P0 L4 , A_A6 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1[0]) , (def_is_mba01) ; # P0 L5 , A_A1 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1[0]) , (def_is_mba23) ; # P2 L4 , C0_CS1n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11[0]) , (def_is_mba23) ; # P2 L5 , C_A11 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A6[0]) , (def_is_mba01) ; # P0 L4 , A_A6 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A1[0]) , (def_is_mba01) ; # P0 L5 , A_A1 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN1[0]) , (def_is_mba23) ; # P2 L4 , C0_CS1n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A11[0]) , (def_is_mba23) ; # P2 L5 , C_A11 } scom 0x800044070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P0_ADR1 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14[0]) , (def_is_mba01) ; # P0 L6 , A_A14 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2[0]) , (def_is_mba01) ; # P0 L7 , A0_CKE2 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3[0]) , (def_is_mba23) ; # P2 L6 , C0_CKE3 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2[0]) , (def_is_mba23) ; # P2 L7 , C0_CS2n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A14[0]) , (def_is_mba01) ; # P0 L6 , A_A14 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE2[0]) , (def_is_mba01) ; # P0 L7 , A0_CKE2 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE3[0]) , (def_is_mba23) ; # P2 L6 , C0_CKE3 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN2[0]) , (def_is_mba23) ; # P2 L7 , C0_CS2n } scom 0x800044080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P0_ADR1 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2[0]) , (def_is_mba01) ; # P0 L8 , A1_CS2n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2[0]) , (def_is_mba01) ; # P0 L9 , A1_CKE2 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0[0]) , (def_is_mba23) ; # P2 L8 , C0_ODT0 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8[0]) , (def_is_mba23) ; # P2 L9 , C_A8 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN2[0]) , (def_is_mba01) ; # P0 L8 , A1_CS2n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE2[0]) , (def_is_mba01) ; # P0 L9 , A1_CKE2 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT0[0]) , (def_is_mba23) ; # P2 L8 , C0_ODT0 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A8[0]) , (def_is_mba23) ; # P2 L9 , C_A8 } scom 0x800044090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P0_ADR1 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4[0]) , (def_is_mba01) ; # P0 L10, A_A4 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN[0]) , (def_is_mba01) ; # P0 L11, A_RASn - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5[0]) , (def_is_mba23) ; # P2 L10, C_A5 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0[0]) , (def_is_mba23) ; # P2 L11, C1_CS0n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A4[0]) , (def_is_mba01) ; # P0 L10, A_A4 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_RASN[0]) , (def_is_mba01) ; # P0 L11, A_RASn + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A5[0]) , (def_is_mba23) ; # P2 L10, C_A5 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN0[0]) , (def_is_mba23) ; # P2 L11, C1_CS0n } #-- Port 0/2 ADR 2 ------------------------------------------------------------ scom 0x800048040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P0_ADR2 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12[0]) , (def_is_mba01) ; # P0 L0 , A_A12 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0[0]) , (def_is_mba01) ; # P0 L1 , A_A0 centerlane - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1[0]) , (def_is_mba23) ; # P2 L0 , C_A1 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6[0]) , (def_is_mba23) ; # P2 L1 , C_A6 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A12[0]) , (def_is_mba01) ; # P0 L0 , A_A12 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A0[0]) , (def_is_mba01) ; # P0 L1 , A_A0 centerlane + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A1[0]) , (def_is_mba23) ; # P2 L0 , C_A1 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A6[0]) , (def_is_mba23) ; # P2 L1 , C_A6 } scom 0x800048050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P0_ADR2 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3[0]) , (def_is_mba01) ; # P0 L2 , A0_CKE3 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3[0]) , (def_is_mba01) ; # P0 L3 , A1_CS3n - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13[0]) , (def_is_mba23) ; # P2 L2 , C_A13 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0[0]) , (def_is_mba23) ; # P2 L3 , C0_CKE0 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE3[0]) , (def_is_mba01) ; # P0 L2 , A0_CKE3 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN3[0]) , (def_is_mba01) ; # P0 L3 , A1_CS3n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A13[0]) , (def_is_mba23) ; # P2 L2 , C_A13 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE0[0]) , (def_is_mba23) ; # P2 L3 , C0_CKE0 } scom 0x800048060301143F { # DPHY01.DDRPHY_ADR_DELAY2_P0_ADR2 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[0]) , (def_is_mba01) ; # P0 L4 , A1_CLK0_p - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[0]) , (def_is_mba01) ; # P0 L5 , A1_CLK0_n - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0[0]) , (def_is_mba23) ; # P2 L4 , C1_ODT0 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1[0]) , (def_is_mba23) ; # P2 L5 , C1_CS1n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0[0]) , (def_is_mba01) ; # P0 L4 , A1_CLK0_p + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0[0]) , (def_is_mba01) ; # P0 L5 , A1_CLK0_n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT0[0]) , (def_is_mba23) ; # P2 L4 , C1_ODT0 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN1[0]) , (def_is_mba23) ; # P2 L5 , C1_CS1n } scom 0x800048070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P0_ADR2 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1[0]) , (def_is_mba01) ; # P0 L6 , A0_ODT1 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0[0]) , (def_is_mba01) ; # P0 L7 , A1_CS0n - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1[0]) , (def_is_mba23) ; # P2 L6 , C0_CKE1 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0[0]) , (def_is_mba23) ; # P2 L7 , C1_CKE0 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT1[0]) , (def_is_mba01) ; # P0 L6 , A0_ODT1 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN0[0]) , (def_is_mba01) ; # P0 L7 , A1_CS0n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE1[0]) , (def_is_mba23) ; # P2 L6 , C0_CKE1 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE0[0]) , (def_is_mba23) ; # P2 L7 , C1_CKE0 } scom 0x800048080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P0_ADR2 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1[0]) , (def_is_mba01) ; # P0 L8 , A1_CS1n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10[0]) , (def_is_mba01) ; # P0 L9 , A_A10 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0[0]) , (def_is_mba23) ; # P2 L8 , C_A0 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1[0]) , (def_is_mba23) ; # P2 L9 , C_BA1 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN1[0]) , (def_is_mba01) ; # P0 L8 , A1_CS1n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A10[0]) , (def_is_mba01) ; # P0 L9 , A_A10 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A0[0]) , (def_is_mba23) ; # P2 L8 , C_A0 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA1[0]) , (def_is_mba23) ; # P2 L9 , C_BA1 } scom 0x800048090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P0_ADR2 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[0]) , (def_is_mba01) ; # P0 L10, A0_CLK1_n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[0]) , (def_is_mba01) ; # P0 L11, A0_CLK1_p - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[0]) , (def_is_mba23) ; # P2 L10, C0_CLK0_n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[0]) , (def_is_mba23) ; # P2 L11, C0_CLK0_p + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1[0]) , (def_is_mba01) ; # P0 L10, A0_CLK1_n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1[0]) , (def_is_mba01) ; # P0 L11, A0_CLK1_p + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0[0]) , (def_is_mba23) ; # P2 L10, C0_CLK0_n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0[0]) , (def_is_mba23) ; # P2 L11, C0_CLK0_p } scom 0x8000480A0301143F { # DPHY01.DDRPHY_ADR_DELAY6_P0_ADR2 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[0]) , (def_is_mba01) ; # P0 L12, A1_CLK1_n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[0]) , (def_is_mba01) ; # P0 L13, A1_CLK1_p - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2[0]) , (def_is_mba23) ; # P2 L12, C1_CS2n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10[0]) , (def_is_mba23) ; # P2 L13, C_A10 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1[0]) , (def_is_mba01) ; # P0 L12, A1_CLK1_n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1[0]) , (def_is_mba01) ; # P0 L13, A1_CLK1_p + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN2[0]) , (def_is_mba23) ; # P2 L12, C1_CS2n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A10[0]) , (def_is_mba23) ; # P2 L13, C_A10 } #-- Port 0/2 ADR 3 ------------------------------------------------------------ scom 0x80004C040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P0_ADR3 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13[0]) , (def_is_mba01) ; # P0 L0 , A_A13 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0[0]) , (def_is_mba01) ; # P0 L1 , A_BA0 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_PAR[0]) , (def_is_mba23) ; # P2 L0 , C_PAR - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1[0]) , (def_is_mba23) ; # P2 L1 , C1_ODT1 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A13[0]) , (def_is_mba01) ; # P0 L0 , A_A13 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA0[0]) , (def_is_mba01) ; # P0 L1 , A_BA0 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_PAR[0]) , (def_is_mba23) ; # P2 L0 , C_PAR + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT1[0]) , (def_is_mba23) ; # P2 L1 , C1_ODT1 } scom 0x80004C050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P0_ADR3 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN[0]) , (def_is_mba01) ; # P0 L2 , A_WEn - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2[0]) , (def_is_mba01) ; # P0 L3 , A0_CS2n - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[0]) , (def_is_mba23) ; # P2 L2 , C1_CLK0_p - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[0]) , (def_is_mba23) ; # P2 L3 , C1_CLK0_n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_WEN[0]) , (def_is_mba01) ; # P0 L2 , A_WEn + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN2[0]) , (def_is_mba01) ; # P0 L3 , A0_CS2n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0[0]) , (def_is_mba23) ; # P2 L2 , C1_CLK0_p + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0[0]) , (def_is_mba23) ; # P2 L3 , C1_CLK0_n } scom 0x80004C060301143F { # DPHY01.DDRPHY_ADR_DELAY2_P0_ADR3 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1[0]) , (def_is_mba01) ; # P0 L4 , A_BA1 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN[0]) , (def_is_mba01) ; # P0 L5 , A_CASn - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14[0]) , (def_is_mba23) ; # P2 L4 , C_A14 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9[0]) , (def_is_mba23) ; # P2 L5 , C_A9 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA1[0]) , (def_is_mba01) ; # P0 L4 , A_BA1 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_CASN[0]) , (def_is_mba01) ; # P0 L5 , A_CASn + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A14[0]) , (def_is_mba23) ; # P2 L4 , C_A14 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A9[0]) , (def_is_mba23) ; # P2 L5 , C_A9 } scom 0x80004C070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P0_ADR3 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5[0]) , (def_is_mba01) ; # P0 L6 , A_A5 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3[0]) , (def_is_mba01) ; # P0 L7 , A_A3 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_ACTN[0]) , (def_is_mba23) ; # P2 L6 , C_ACTn - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2[0]) , (def_is_mba23) ; # P2 L7 , C_A2 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A5[0]) , (def_is_mba01) ; # P0 L6 , A_A5 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A3[0]) , (def_is_mba01) ; # P0 L7 , A_A3 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_ACTN[0]) , (def_is_mba23) ; # P2 L6 , C_ACTn + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A2[0]) , (def_is_mba23) ; # P2 L7 , C_A2 } scom 0x80004C080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P0_ADR3 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2[0]) , (def_is_mba01) ; # P0 L8 , A_BA2 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11[0]) , (def_is_mba01) ; # P0 L9 , A_A11 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3[0]) , (def_is_mba23) ; # P2 L8 , C1_CKE3 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15[0]) , (def_is_mba23) ; # P2 L9 , C_A15 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA2[0]) , (def_is_mba01) ; # P0 L8 , A_BA2 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A11[0]) , (def_is_mba01) ; # P0 L9 , A_A11 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE3[0]) , (def_is_mba23) ; # P2 L8 , C1_CKE3 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A15[0]) , (def_is_mba23) ; # P2 L9 , C_A15 } scom 0x80004C090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P0_ADR3 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7[0]) , (def_is_mba01) ; # P0 L10, A_A7 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_ACTN[0]) , (def_is_mba01) ; # P0 L11, A_ACTn - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0[0]) , (def_is_mba23) ; # P2 L10, C_BA0 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN[0]) , (def_is_mba23) ; # P2 L11, C_CASn + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A7[0]) , (def_is_mba01) ; # P0 L10, A_A7 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_ACTN[0]) , (def_is_mba01) ; # P0 L11, A_ACTn + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA0[0]) , (def_is_mba23) ; # P2 L10, C_BA0 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_CASN[0]) , (def_is_mba23) ; # P2 L11, C_CASn } scom 0x80004C0A0301143F { # DPHY01.DDRPHY_ADR_DELAY6_P0_ADR3 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9[0]) , (def_is_mba01) ; # P0 L12, A_A9 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8[0]) , (def_is_mba01) ; # P0 L13, A_A8 # fixed typo - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4[0]) , (def_is_mba23) ; # P2 L12, C_A4 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3[0]) , (def_is_mba23) ; # P2 L13, C0_CS3n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A9[0]) , (def_is_mba01) ; # P0 L12, A_A9 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A8[0]) , (def_is_mba01) ; # P0 L13, A_A8 # fixed typo + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A4[0]) , (def_is_mba23) ; # P2 L12, C_A4 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN3[0]) , (def_is_mba23) ; # P2 L13, C0_CS3n } #==================================================================================== # PORT 1 / 3 @@ -4637,213 +4638,213 @@ scom 0x80004C0A0301143F { # DPHY01.DDRPHY_ADR_DELAY6_P0_ADR3 scom 0x800140040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P1_ADR0 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[1]) , (def_is_mba01) ; # P1 L0 , B1_CLK0_n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[1]) , (def_is_mba01) ; # P1 L1 , B1_CLK0_p - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1[1]) , (def_is_mba23) ; # P3 L0 , D1_CKE1 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2[1]) , (def_is_mba23) ; # P3 L1 , D_BA2 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0[1]) , (def_is_mba01) ; # P1 L0 , B1_CLK0_n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0[1]) , (def_is_mba01) ; # P1 L1 , B1_CLK0_p + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE1[1]) , (def_is_mba23) ; # P3 L0 , D1_CKE1 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA2[1]) , (def_is_mba23) ; # P3 L1 , D_BA2 } scom 0x800140050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P1_ADR0 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[1]) , (def_is_mba01) ; # P1 L2 , B1_CLK1_n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[1]) , (def_is_mba01) ; # P1 L3 , B1_CLK1_p - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1[1]) , (def_is_mba23) ; # P3 L2 , D_A1 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5[1]) , (def_is_mba23) ; # P3 L3 , D_A5 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1[1]) , (def_is_mba01) ; # P1 L2 , B1_CLK1_n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1[1]) , (def_is_mba01) ; # P1 L3 , B1_CLK1_p + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A1[1]) , (def_is_mba23) ; # P3 L2 , D_A1 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A5[1]) , (def_is_mba23) ; # P3 L3 , D_A5 } scom 0x800140060301143F { # DPHY01_DDRPHY_ADR_DELAY2_P1_ADR0 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3[1]) , (def_is_mba01) ; # P1 L4 , B0_CKE3 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3[1]) , (def_is_mba01) ; # P1 L5 , B0_CS3n - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12[1]) , (def_is_mba23) ; # P3 L4 , D_A12 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0[1]) , (def_is_mba23) ; # P3 L5 , D_BA0 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE3[1]) , (def_is_mba01) ; # P1 L4 , B0_CKE3 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN3[1]) , (def_is_mba01) ; # P1 L5 , B0_CS3n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A12[1]) , (def_is_mba23) ; # P3 L4 , D_A12 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA0[1]) , (def_is_mba23) ; # P3 L5 , D_BA0 } scom 0x800140070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P1_ADR0 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0[1]) , (def_is_mba01) ; # P1 L6 , B_BA0 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1[1]) , (def_is_mba01) ; # P1 L7 , B1_ODT1 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2[1]) , (def_is_mba23) ; # P3 L6 , D1_CKE2 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1[1]) , (def_is_mba23) ; # P3 L7 , D1_CS1n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA0[1]) , (def_is_mba01) ; # P1 L6 , B_BA0 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT1[1]) , (def_is_mba01) ; # P1 L7 , B1_ODT1 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE2[1]) , (def_is_mba23) ; # P3 L6 , D1_CKE2 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN1[1]) , (def_is_mba23) ; # P3 L7 , D1_CS1n } scom 0x800140080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P1_ADR0 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3[1]) , (def_is_mba01) ; # P1 L8 , B1_CKE3 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15[1]) , (def_is_mba01) ; # P1 L9 , B_A15 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0[1]) , (def_is_mba23) ; # P3 L8 , D0_CKE0 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2[1]) , (def_is_mba23) ; # P3 L9 , D0_CS2n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE3[1]) , (def_is_mba01) ; # P1 L8 , B1_CKE3 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A15[1]) , (def_is_mba01) ; # P1 L9 , B_A15 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE0[1]) , (def_is_mba23) ; # P3 L8 , D0_CKE0 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN2[1]) , (def_is_mba23) ; # P3 L9 , D0_CS2n } scom 0x800140090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P1_ADR0 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2[1]) , (def_is_mba01) ; # P1 L10, B1_CS2n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1[1]) , (def_is_mba01) ; # P1 L11, B0_CKE1 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[1]) , (def_is_mba23) ; # P3 L10, D1_CLK0_p - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[1]) , (def_is_mba23) ; # P3 L11, D1_CLK0_n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN2[1]) , (def_is_mba01) ; # P1 L10, B1_CS2n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE1[1]) , (def_is_mba01) ; # P1 L11, B0_CKE1 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0[1]) , (def_is_mba23) ; # P3 L10, D1_CLK0_p + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0[1]) , (def_is_mba23) ; # P3 L11, D1_CLK0_n } #-- Port 1/3 ADR 1 ------------------------------------------------------------ scom 0x800144040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P1_ADR1 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2[1]) , (def_is_mba01) ; # P1 L0 , B0_CKE2 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7[1]) , (def_is_mba01) ; # P1 L1 , B_A7 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8[1]) , (def_is_mba23) ; # P3 L0 , D_A8 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13[1]) , (def_is_mba23) ; # P3 L1 , D_A13 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE2[1]) , (def_is_mba01) ; # P1 L0 , B0_CKE2 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A7[1]) , (def_is_mba01) ; # P1 L1 , B_A7 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A8[1]) , (def_is_mba23) ; # P3 L0 , D_A8 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A13[1]) , (def_is_mba23) ; # P3 L1 , D_A13 } scom 0x800144050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P1_ADR1 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10[1]) , (def_is_mba01) ; # P1 L2 , B_A10 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1[1]) , (def_is_mba01) ; # P1 L3 , B1_CKE1 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1[1]) , (def_is_mba23) ; # P3 L2 , D0_ODT1 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_PAR[1]) , (def_is_mba23) ; # P3 L3 , D_PAR + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A10[1]) , (def_is_mba01) ; # P1 L2 , B_A10 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE1[1]) , (def_is_mba01) ; # P1 L3 , B1_CKE1 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT1[1]) , (def_is_mba23) ; # P3 L2 , D0_ODT1 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_PAR[1]) , (def_is_mba23) ; # P3 L3 , D_PAR } scom 0x800144060301143F { # DPHY01_DDRPHY_ADR_DELAY2_P1_ADR1 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1[1]) , (def_is_mba01) ; # P1 L4 , B0_CS1n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8[1]) , (def_is_mba01) ; # P1 L5 , B_A8 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0[1]) , (def_is_mba23) ; # P3 L4 , D1_CS0n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11[1]) , (def_is_mba23) ; # P3 L5 , D_A11 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN1[1]) , (def_is_mba01) ; # P1 L4 , B0_CS1n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A8[1]) , (def_is_mba01) ; # P1 L5 , B_A8 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN0[1]) , (def_is_mba23) ; # P3 L4 , D1_CS0n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A11[1]) , (def_is_mba23) ; # P3 L5 , D_A11 } scom 0x800144070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P1_ADR1 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6[1]) , (def_is_mba01) ; # P1 L6 , B_A6 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3[1]) , (def_is_mba01) ; # P1 L7 , B1_CS3n - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1[1]) , (def_is_mba23) ; # P3 L6 , D0_CKE1 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN[1]) , (def_is_mba23) ; # P3 L7 , D_WEn + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A6[1]) , (def_is_mba01) ; # P1 L6 , B_A6 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN3[1]) , (def_is_mba01) ; # P1 L7 , B1_CS3n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE1[1]) , (def_is_mba23) ; # P3 L6 , D0_CKE1 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_WEN[1]) , (def_is_mba23) ; # P3 L7 , D_WEn } scom 0x800144080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P1_ADR1 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4[1]) , (def_is_mba01) ; # P1 L8 , B_A4 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1[1]) , (def_is_mba01) ; # P1 L9 , B1_CS1n - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3[1]) , (def_is_mba23) ; # P3 L8 , D0_CKE3 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0[1]) , (def_is_mba23) ; # P3 L9 , D1_ODT0 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A4[1]) , (def_is_mba01) ; # P1 L8 , B_A4 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN1[1]) , (def_is_mba01) ; # P1 L9 , B1_CS1n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE3[1]) , (def_is_mba23) ; # P3 L8 , D0_CKE3 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT0[1]) , (def_is_mba23) ; # P3 L9 , D1_ODT0 } scom 0x800144090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P1_ADR1 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1[1]) , (def_is_mba01) ; # P1 L10, B_A1 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1[1]) , (def_is_mba01) ; # P1 L11, B_BA1 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN[1]) , (def_is_mba23) ; # P3 L10, D_RASn - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1[1]) , (def_is_mba23) ; # P3 L11, D0_CS1n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A1[1]) , (def_is_mba01) ; # P1 L10, B_A1 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA1[1]) , (def_is_mba01) ; # P1 L11, B_BA1 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_RASN[1]) , (def_is_mba23) ; # P3 L10, D_RASn + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN1[1]) , (def_is_mba23) ; # P3 L11, D0_CS1n } #-- Port 1/3 ADR 2 ------------------------------------------------------------ scom 0x800148040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P1_ADR2 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2[1]) , (def_is_mba01) ; # P1 L0 , B0_CS2n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0[1]) , (def_is_mba01) ; # P1 L1 , B0_ODT0 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0[1]) , (def_is_mba23) ; # P3 L0 , D0_CS0n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10[1]) , (def_is_mba23) ; # P3 L1 , D_A10 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN2[1]) , (def_is_mba01) ; # P1 L0 , B0_CS2n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT0[1]) , (def_is_mba01) ; # P1 L1 , B0_ODT0 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN0[1]) , (def_is_mba23) ; # P3 L0 , D0_CS0n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A10[1]) , (def_is_mba23) ; # P3 L1 , D_A10 } scom 0x800148050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P1_ADR2 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN[1]) , (def_is_mba01) ; # P1 L2 , B_WEn - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2[1]) , (def_is_mba01) ; # P1 L3 , B_A2 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4[1]) , (def_is_mba23) ; # P3 L2 , D_A4 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3[1]) , (def_is_mba23) ; # P3 L3 , D1_CS3n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_WEN[1]) , (def_is_mba01) ; # P1 L2 , B_WEn + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A2[1]) , (def_is_mba01) ; # P1 L3 , B_A2 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A4[1]) , (def_is_mba23) ; # P3 L2 , D_A4 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN3[1]) , (def_is_mba23) ; # P3 L3 , D1_CS3n } scom 0x800148060301143F { # DPHY01.DDRPHY_ADR_DELAY2_P1_ADR2 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1[1]) , (def_is_mba01) ; # P1 L4 , B0_ODT1 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0[1]) , (def_is_mba01) ; # P1 L5 , B0_CS0n - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_ACTN[1]) , (def_is_mba23) ; # P3 L4 , D_ACTn - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9[1]) , (def_is_mba23) ; # P3 L5 , D_A9 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT1[1]) , (def_is_mba01) ; # P1 L4 , B0_ODT1 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN0[1]) , (def_is_mba01) ; # P1 L5 , B0_CS0n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_ACTN[1]) , (def_is_mba23) ; # P3 L4 , D_ACTn + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A9[1]) , (def_is_mba23) ; # P3 L5 , D_A9 } scom 0x800148070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P1_ADR2 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3[1]) , (def_is_mba01) ; # P1 L6 , B_A3 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0[1]) , (def_is_mba01) ; # P1 L7 , B_A0 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3[1]) , (def_is_mba23) ; # P3 L6 , D1_CKE3 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0[1]) , (def_is_mba23) ; # P3 L7 , D1_CKE0 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A3[1]) , (def_is_mba01) ; # P1 L6 , B_A3 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A0[1]) , (def_is_mba01) ; # P1 L7 , B_A0 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE3[1]) , (def_is_mba23) ; # P3 L6 , D1_CKE3 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE0[1]) , (def_is_mba23) ; # P3 L7 , D1_CKE0 } scom 0x800148080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P1_ADR2 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[1]) , (def_is_mba01) ; # P1 L8 , B0_CLK1_p - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[1]) , (def_is_mba01) ; # P1 L9 , B0_CLK1_n - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3[1]) , (def_is_mba23) ; # P3 L8 , D0_CS3n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2[1]) , (def_is_mba23) ; # P3 L9 , D_A2 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1[1]) , (def_is_mba01) ; # P1 L8 , B0_CLK1_p + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1[1]) , (def_is_mba01) ; # P1 L9 , B0_CLK1_n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN3[1]) , (def_is_mba23) ; # P3 L8 , D0_CS3n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A2[1]) , (def_is_mba23) ; # P3 L9 , D_A2 } scom 0x800148090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P1_ADR2 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN[1]) , (def_is_mba01) ; # P1 L10, B_CASn - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0[1]) , (def_is_mba01) ; # P1 L11, B1_CS0n - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[1]) , (def_is_mba23) ; # P3 L10, D1_CLK1_n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[1]) , (def_is_mba23) ; # P3 L11, D1_CLK1_p + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_CASN[1]) , (def_is_mba01) ; # P1 L10, B_CASn + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN0[1]) , (def_is_mba01) ; # P1 L11, B1_CS0n + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1[1]) , (def_is_mba23) ; # P3 L10, D1_CLK1_n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1[1]) , (def_is_mba23) ; # P3 L11, D1_CLK1_p } scom 0x8001480A0301143F { # DPHY01.DDRPHY_ADR_DELAY6_P1_ADR2 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0[1]) , (def_is_mba01) ; # P1 L12, B1_CKE0 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12[1]) , (def_is_mba01) ; # P1 L13, B_A12 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[1]) , (def_is_mba23) ; # P3 L12, D0_CLK1_n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[1]) , (def_is_mba23) ; # P3 L13, D0_CLK1_p + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE0[1]) , (def_is_mba01) ; # P1 L12, B1_CKE0 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A12[1]) , (def_is_mba01) ; # P1 L13, B_A12 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1[1]) , (def_is_mba23) ; # P3 L12, D0_CLK1_n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1[1]) , (def_is_mba23) ; # P3 L13, D0_CLK1_p } #-- Port 1/3 ADR 3 ------------------------------------------------------------ scom 0x80014C040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P1_ADR3 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11[1]) , (def_is_mba01) ; # P1 L0 , B_A11 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0[1]) , (def_is_mba01) ; # P1 L1 , B0_CKE0 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2[1]) , (def_is_mba23) ; # P3 L0 , D1_CS2n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0[1]) , (def_is_mba23) ; # P3 L1 , D0_ODT0 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A11[1]) , (def_is_mba01) ; # P1 L0 , B_A11 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE0[1]) , (def_is_mba01) ; # P1 L1 , B0_CKE0 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN2[1]) , (def_is_mba23) ; # P3 L0 , D1_CS2n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT0[1]) , (def_is_mba23) ; # P3 L1 , D0_ODT0 } scom 0x80014C050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P1_ADR3 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[1]) , (def_is_mba01) ; # P1 L2 , B0_CLK0_n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[1]) , (def_is_mba01) ; # P1 L3 , B0_CLK0_p - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[1]) , (def_is_mba23) ; # P3 L2 , D0_CLK0_n - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[1]) , (def_is_mba23) ; # P3 L3 , D0_CLK0_p + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0[1]) , (def_is_mba01) ; # P1 L2 , B0_CLK0_n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0[1]) , (def_is_mba01) ; # P1 L3 , B0_CLK0_p + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0[1]) , (def_is_mba23) ; # P3 L2 , D0_CLK0_n + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0[1]) , (def_is_mba23) ; # P3 L3 , D0_CLK0_p } scom 0x80014C060301143F { # DPHY01.DDRPHY_ADR_DELAY2_P1_ADR3 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13[1]) , (def_is_mba01) ; # P1 L4 , B_A13 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14[1]) , (def_is_mba01) ; # P1 L5 , B_A14 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6[1]) , (def_is_mba23) ; # P3 L4 , D_A6 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1[1]) , (def_is_mba23) ; # P3 L5 , D1_ODT1 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A13[1]) , (def_is_mba01) ; # P1 L4 , B_A13 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A14[1]) , (def_is_mba01) ; # P1 L5 , B_A14 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A6[1]) , (def_is_mba23) ; # P3 L4 , D_A6 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT1[1]) , (def_is_mba23) ; # P3 L5 , D1_ODT1 } scom 0x80014C070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P1_ADR3 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2[1]) , (def_is_mba01) ; # P1 L6 , B1_CKE2 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0[1]) , (def_is_mba01) ; # P1 L7 , B1_ODT0 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0[1]) , (def_is_mba23) ; # P3 L6 , D_A0 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN[1]) , (def_is_mba23) ; # P3 L7 , D_CASn + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE2[1]) , (def_is_mba01) ; # P1 L6 , B1_CKE2 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT0[1]) , (def_is_mba01) ; # P1 L7 , B1_ODT0 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A0[1]) , (def_is_mba23) ; # P3 L6 , D_A0 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_CASN[1]) , (def_is_mba23) ; # P3 L7 , D_CASn } scom 0x80014C080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P1_ADR3 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9[1]) , (def_is_mba01) ; # P1 L8 , B_A9 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2[1]) , (def_is_mba01) ; # P1 L9 , B_BA2 - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14[1]) , (def_is_mba23) ; # P3 L8 , D_A14 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3[1]) , (def_is_mba23) ; # P3 L9 , D_A3 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A9[1]) , (def_is_mba01) ; # P1 L8 , B_A9 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA2[1]) , (def_is_mba01) ; # P1 L9 , B_BA2 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A14[1]) , (def_is_mba23) ; # P3 L8 , D_A14 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A3[1]) , (def_is_mba23) ; # P3 L9 , D_A3 } scom 0x80014C090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P1_ADR3 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN[1]) , (def_is_mba01) ; # P1 L10, B_RASn - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_ACTN[1]) , (def_is_mba01) ; # P1 L11, B_ACTn - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7[1]) , (def_is_mba23) ; # P3 L10, D_A7 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15[1]) , (def_is_mba23) ; # P3 L11, D_A15 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_RASN[1]) , (def_is_mba01) ; # P1 L10, B_RASn + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_ACTN[1]) , (def_is_mba01) ; # P1 L11, B_ACTn + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A7[1]) , (def_is_mba23) ; # P3 L10, D_A7 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A15[1]) , (def_is_mba23) ; # P3 L11, D_A15 } scom 0x80014C0A0301143F { # DPHY01.DDRPHY_ADR_DELAY6_P1_ADR3 bits , scom_data , expr ; # 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5[1]) , (def_is_mba01) ; # P1 L12, B_A5 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_PAR[1]) , (def_is_mba01) ; # P1 L13, B_PAR - 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1[1]) , (def_is_mba23) ; # P3 L12, D_BA1 - 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2[1]) , (def_is_mba23) ; # P3 L13, D0_CKE2 + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A5[1]) , (def_is_mba01) ; # P1 L12, B_A5 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_PAR[1]) , (def_is_mba01) ; # P1 L13, B_PAR + 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA1[1]) , (def_is_mba23) ; # P3 L12, D_BA1 + 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE2[1]) , (def_is_mba23) ; # P3 L13, D0_CKE2 } #================================================================================ diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C index 674c66982..8ad67c94e 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_config_thermal.C,v 1.19 2013/09/23 22:05:04 pardeik Exp $ +// $Id: mss_eff_config_thermal.C,v 1.23 2013/12/02 22:46:01 pardeik Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/ // centaur/working/procedures/ipl/fapi/mss_eff_config_thermal.C,v $ //------------------------------------------------------------------------------ @@ -30,8 +30,8 @@ //------------------------------------------------------------------------------ // *! TITLE : mss_eff_config_thermal // *! DESCRIPTION : see additional comments below -// *! OWNER NAME : Joab Henderson Email: joabhend@us.ibm.com -// *! BACKUP NAME : Michael Pardeik Email: pardeik@us.ibm.com +// *! OWNER NAME : Michael Pardeik Email: pardeik@us.ibm.com +// *! BACKUP NAME : Jacob Sloat Email: jdsloat@us.ibm.com // *! ADDITIONAL COMMENTS : // // applicable CQ component memory_screen @@ -53,6 +53,11 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.23 | pardeik |02-DEC-13| enable supplier power curve attributes +// 1.22 | pardeik |18-NOV-13| rename attributes (eff to vpd) +// 1.21 | pardeik |14-NOV-13| hardcode supplier power curves until lab is +// | | | using read VPD +// 1.20 | pardeik |13-NOV-13| enable power curve attribute data from VPD // 1.19 | pardeik |23-SEP-13| initial support for the ras/cas increments // 1.18 | bellows |19-SEP-13| fixed possible buffer overrun found by stradale // 1.17 | pardeik |19-JUL-13| Use runtime throttles for IPL for scominit @@ -108,9 +113,8 @@ TODO ITEMS: Waiting for platinit attributes to enable sections in this procedure: -1. Power Curves to originate from CDIMM VPD (platinit) -2. Call out error for CDIMM and lab VPD power curves when it makes sense -3. Update ISDIMM power table after hardware measurements are done +1. Call out error for CDIMM and lab VPD power curves when it makes sense +2. Update ISDIMM power table after hardware measurements are done */ //------------------------------------------------------------------------------ @@ -141,6 +145,7 @@ const uint8_t ACTIVE_DIMM_UTILIZATION = 70; const uint8_t DATA_BUS_READ_PERCENT = 66; const uint8_t DATA_BUS_WRITE_PERCENT = 34; +//@thi - Change all FAPI_INF to FAPI_INF extern "C" { @@ -397,19 +402,19 @@ extern "C" { FAPI_ERR("Error getting attribute ATTR_EFF_DIMM_RANKS_CONFIGED"); return rc; } - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RON, &i_target_mba, dimm_dram_ron); + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RON, &i_target_mba, dimm_dram_ron); if (rc) { - FAPI_ERR("Error getting attribute ATTR_EFF_DRAM_RON"); + FAPI_ERR("Error getting attribute ATTR_VPD_DRAM_RON"); return rc; } - rc = FAPI_ATTR_GET(ATTR_EFF_ODT_RD, &i_target_mba, dimm_rank_odt_rd); + rc = FAPI_ATTR_GET(ATTR_VPD_ODT_RD, &i_target_mba, dimm_rank_odt_rd); if (rc) { - FAPI_ERR("Error getting attribute ATTR_EFF_ODT_RD"); + FAPI_ERR("Error getting attribute ATTR_VPD_ODT_RD"); return rc; } - rc = FAPI_ATTR_GET(ATTR_EFF_ODT_WR, &i_target_mba, dimm_rank_odt_wr); + rc = FAPI_ATTR_GET(ATTR_VPD_ODT_WR, &i_target_mba, dimm_rank_odt_wr); if (rc) { - FAPI_ERR("Error getting attribute ATTR_EFF_ODT_WR"); + FAPI_ERR("Error getting attribute ATTR_VPD_ODT_WR"); return rc; } rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, @@ -424,14 +429,14 @@ extern "C" { FAPI_ERR("Error getting attribute ATTR_EFF_CEN_DRV_IMP_DQ_DQS"); return rc; } - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RTT_NOM, &i_target_mba, dram_rtt_nom); + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_NOM, &i_target_mba, dram_rtt_nom); if (rc) { - FAPI_ERR("Error getting attribute ATTR_EFF_DRAM_RTT_NOM"); + FAPI_ERR("Error getting attribute ATTR_VPD_DRAM_RTT_NOM"); return rc; } - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RTT_WR, &i_target_mba, dram_rtt_wr); + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_WR, &i_target_mba, dram_rtt_wr); if (rc) { - FAPI_ERR("Error getting attribute ATTR_EFF_DRAM_RTT_WR"); + FAPI_ERR("Error getting attribute ATTR_VPD_DRAM_RTT_WR"); return rc; } rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, @@ -440,13 +445,6 @@ extern "C" { FAPI_ERR("Error getting attribute ATTR_EFF_NUM_DROPS_PER_PORT"); return rc; } -// TODO: use vpd values when power curve data is available from CDIMM VPD -// (platinit), remove hardcoding - cdimm_master_power_slope = CDIMM_POWER_SLOPE_DEFAULT; - cdimm_master_power_intercept = CDIMM_POWER_INT_DEFAULT; - cdimm_supplier_power_slope = CDIMM_POWER_SLOPE_DEFAULT; - cdimm_supplier_power_intercept = CDIMM_POWER_INT_DEFAULT; -/* rc = FAPI_ATTR_GET(ATTR_CDIMM_VPD_MASTER_POWER_SLOPE, &target_chip, cdimm_master_power_slope); if (rc) { @@ -459,6 +457,7 @@ extern "C" { FAPI_ERR("Error getting attribute ATTR_CDIMM_VPD_MASTER_POWER_INTERCEPT"); return rc; } + rc = FAPI_ATTR_GET(ATTR_CDIMM_VPD_SUPPLIER_POWER_SLOPE, &target_chip, cdimm_supplier_power_slope); if (rc) { @@ -471,7 +470,6 @@ extern "C" { FAPI_ERR("Error getting attribute ATTR_CDIMM_VPD_SUPPLIER_POWER_INTERCEPT"); return rc; } -*/ rc = FAPI_ATTR_GET(ATTR_MRW_THERMAL_MEMORY_POWER_LIMIT, NULL, dimm_thermal_power_limit); @@ -776,7 +774,7 @@ extern "C" { (rc, RC_MSS_DIMM_POWER_CURVE_DATA_INVALID); if (rc) fapiLogError(rc); } - FAPI_DBG("CDIMM Power [P%d:D%d][SLOPE=%d:INT=%d cW][SLOPE2=%d:INT2=%d cW]", port, dimm, power_slope_array[port][dimm], power_int_array[port][dimm], power_slope2_array[port][dimm], power_int2_array[port][dimm]); + FAPI_INF("CDIMM Power [P%d:D%d][SLOPE=%d:INT=%d cW][SLOPE2=%d:INT2=%d cW]", port, dimm, power_slope_array[port][dimm], power_int_array[port][dimm], power_slope2_array[port][dimm], power_int2_array[port][dimm]); } // ISDIMM power slope/intercept will come from equation else @@ -937,9 +935,9 @@ extern "C" { } found_entry_in_table = 1; - FAPI_DBG("FOUND ENTRY: GEN=%s WIDTH=X%d RANK=%d IDLE(%d%%)=%d ACTIVE(%d%%)=%d ADDER[TYPE=%d WCTERM=%4.2f] Multiplier[VOLT=%4.2f FREQ=%4.2f]", dram_gen_str, power_table[entry].dram_width, power_table[entry].dimm_ranks, IDLE_DIMM_UTILIZATION, power_table[entry].rank_power.idle, ACTIVE_DIMM_UTILIZATION, power_table[entry].rank_power.active, dimm_power_adder_type, dimm_power_adder_termination_wc, dimm_power_multiplier_volt, dimm_power_mulitiplier_freq); - FAPI_DBG("ISDIMM Power [P%d:D%d][%s:X%d:R%d/%d:%d:%d][IDLE(%d%%)=%4.2f:ACTIVE(%d%%)=%4.2f cW][SLOPE=%d:INT=%d cW]", port, dimm, dram_gen_str, power_table[entry].dram_width, dimm_master_ranks_array[port][dimm], (dimm_ranks_array[port][dimm] - dimm_master_ranks_array[port][dimm]), dimm_voltage, dimm_frequency, IDLE_DIMM_UTILIZATION, dimm_idle_power, ACTIVE_DIMM_UTILIZATION, dimm_active_power, power_slope_array[port][dimm], power_int_array[port][dimm]); - FAPI_DBG("ISDIMM Power [P%d:D%d][SLOPE=%d:INT=%d cW][SLOPE2=%d:INT2=%d cW]", port, dimm, power_slope_array[port][dimm], power_int_array[port][dimm], power_slope2_array[port][dimm], power_int2_array[port][dimm]); + FAPI_INF("FOUND ENTRY: GEN=%s WIDTH=X%d RANK=%d IDLE(%d%%)=%d ACTIVE(%d%%)=%d ADDER[TYPE=%d WCTERM=%4.2f] Multiplier[VOLT=%4.2f FREQ=%4.2f]", dram_gen_str, power_table[entry].dram_width, power_table[entry].dimm_ranks, IDLE_DIMM_UTILIZATION, power_table[entry].rank_power.idle, ACTIVE_DIMM_UTILIZATION, power_table[entry].rank_power.active, dimm_power_adder_type, dimm_power_adder_termination_wc, dimm_power_multiplier_volt, dimm_power_mulitiplier_freq); + FAPI_INF("ISDIMM Power [P%d:D%d][%s:X%d:R%d/%d:%d:%d][IDLE(%d%%)=%4.2f:ACTIVE(%d%%)=%4.2f cW][SLOPE=%d:INT=%d cW]", port, dimm, dram_gen_str, power_table[entry].dram_width, dimm_master_ranks_array[port][dimm], (dimm_ranks_array[port][dimm] - dimm_master_ranks_array[port][dimm]), dimm_voltage, dimm_frequency, IDLE_DIMM_UTILIZATION, dimm_idle_power, ACTIVE_DIMM_UTILIZATION, dimm_active_power, power_slope_array[port][dimm], power_int_array[port][dimm]); + FAPI_INF("ISDIMM Power [P%d:D%d][SLOPE=%d:INT=%d cW][SLOPE2=%d:INT2=%d cW]", port, dimm, power_slope_array[port][dimm], power_int_array[port][dimm], power_slope2_array[port][dimm], power_int2_array[port][dimm]); break; } @@ -1087,7 +1085,6 @@ extern "C" { } // Setup the RAS and CAS increments used in the throttling register -// TODO: base these values off of number of ranks and dram width ras_increment=0; cas_increment=1; @@ -1340,7 +1337,7 @@ extern "C" { ((i_dimm_rank_odt_rd[i_port][i_dimm][i_rank] & 0x80) != 0) && (i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE) + fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE) ) { if (eff_term_rd == 0) @@ -1357,7 +1354,7 @@ extern "C" { (eff_term_rd + i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank]); } - FAPI_DBG("[P%d:D%d:R%d] 0ODT0 RD TERMINATION = %4.2f (%d)", i_port, i_dimm, i_rank, eff_term_rd, i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank]); + FAPI_INF("[P%d:D%d:R%d] 0ODT0 RD TERMINATION = %4.2f (%d)", i_port, i_dimm, i_rank, eff_term_rd, i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank]); } //------------------------------------------------------------------------------ @@ -1366,7 +1363,7 @@ extern "C" { ((i_dimm_rank_odt_rd[i_port][i_dimm][i_rank] & 0x40) != 0) && (i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE) + fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE) ) { if (eff_term_rd == 0) @@ -1383,7 +1380,7 @@ extern "C" { (eff_term_rd + i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank]); } - FAPI_DBG("[P%d:D%d:R%d] 0ODT1 RD TERMINATION = %4.2f (%d)", i_port, i_dimm, i_rank, eff_term_rd, i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank]); + FAPI_INF("[P%d:D%d:R%d] 0ODT1 RD TERMINATION = %4.2f (%d)", i_port, i_dimm, i_rank, eff_term_rd, i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank]); } //------------------------------------------------------------------------------ // 1ODT0 @@ -1391,7 +1388,7 @@ extern "C" { ((i_dimm_rank_odt_rd[i_port][i_dimm][i_rank] & 0x20) != 0) && (i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE) + fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE) ) { if (eff_term_rd == 0) @@ -1408,7 +1405,7 @@ extern "C" { (eff_term_rd + i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank]); } - FAPI_DBG("[P%d:D%d:R%d] 1ODT0 RD TERMINATION = %4.2f (%d)", i_port, i_dimm, i_rank, eff_term_rd, i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank]); + FAPI_INF("[P%d:D%d:R%d] 1ODT0 RD TERMINATION = %4.2f (%d)", i_port, i_dimm, i_rank, eff_term_rd, i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank]); } //------------------------------------------------------------------------------ // 1ODT1 @@ -1416,7 +1413,7 @@ extern "C" { ((i_dimm_rank_odt_rd[i_port][i_dimm][i_rank] & 0x10) != 0) && (i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE) + fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE) ) { if (eff_term_rd == 0) @@ -1433,7 +1430,7 @@ extern "C" { (eff_term_rd + i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank]); } - FAPI_DBG("[P%d:D%d:R%d] 1ODT1 RD TERMINATION = %4.2f (%d)", i_port, i_dimm, i_rank, eff_term_rd, i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank]); + FAPI_INF("[P%d:D%d:R%d] 1ODT1 RD TERMINATION = %4.2f (%d)", i_port, i_dimm, i_rank, eff_term_rd, i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank]); } // calculate out effective read termination @@ -1488,15 +1485,15 @@ extern "C" { ) && ((i_dram_rtt_wr[i_port][i_dimm][i_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) || + fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE) || (i_dram_rtt_nom[i_port][i_dimm][i_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)) + fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE)) ) { // dynamic ODT enabled, so use rtt_wr (only if the rank being written to has // it enabled) if (i_dram_rtt_wr[i_port][i_dimm][i_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) + fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE) { if (eff_term_wr == 0) { @@ -1513,7 +1510,7 @@ extern "C" { // dynamic ODT disabled, so use rtt_nom else if (i_dram_rtt_nom[i_port][i_dimm][i_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE) + fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE) { if (eff_term_wr == 0) { @@ -1529,7 +1526,7 @@ extern "C" { } } - FAPI_DBG("[P%d:D%d:R%d] WR TERMINATION = %4.2f (%d/%d)", i_port, i_dimm, i_rank, eff_term_wr, i_dram_rtt_wr[i_port][i_dimm][i_rank], i_dram_rtt_nom[i_port][i_dimm][i_rank]); + FAPI_INF("[P%d:D%d:R%d] WR TERMINATION = %4.2f (%d/%d)", i_port, i_dimm, i_rank, eff_term_wr, i_dram_rtt_wr[i_port][i_dimm][i_rank], i_dram_rtt_nom[i_port][i_dimm][i_rank]); } //------------------------------------------------------------------------------ // 0ODT0 @@ -1537,16 +1534,16 @@ extern "C" { ((i_dimm_rank_odt_wr[i_port][i_dimm][i_rank] & 0x80) != 0) && ((i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt0_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) || + fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE) || (i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)) + fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE)) ) { // dynamic ODT enabled, so use rtt_wr (only if the rank being written to has // it enabled) if ( (i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt0_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) + fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE) && (i_dimm == 0) && (i_rank == ma0odt0_rank) ) @@ -1568,7 +1565,7 @@ extern "C" { } // dynamic ODT disabled, so use rtt_nom else if (i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE) + fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE) { if (eff_term_wr == 0) { @@ -1586,7 +1583,7 @@ extern "C" { } } - FAPI_DBG("[P%d:D%d:R%d] 0ODT0 WR TERMINATION = %4.2f (%d/%d)", i_port, i_dimm, i_rank, eff_term_wr, i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank], i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt0_rank]); + FAPI_INF("[P%d:D%d:R%d] 0ODT0 WR TERMINATION = %4.2f (%d/%d)", i_port, i_dimm, i_rank, eff_term_wr, i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank], i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt0_rank]); } //------------------------------------------------------------------------------ // 0ODT1 @@ -1594,16 +1591,16 @@ extern "C" { ((i_dimm_rank_odt_wr[i_port][i_dimm][i_rank] & 0x40) != 0) && ((i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt1_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) || + fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE) || (i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)) + fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE)) ) { // dynamic ODT enabled, so use rtt_wr (only if the rank being written to has // it enabled) if ( (i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt1_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) + fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE) && (i_dimm == 0) && (i_rank == ma0odt1_rank) ) @@ -1625,7 +1622,7 @@ extern "C" { } // dynamic ODT disabled, so use rtt_nom else if (i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE) + fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE) { if (eff_term_wr == 0) { @@ -1643,7 +1640,7 @@ extern "C" { } } - FAPI_DBG("[P%d:D%d:R%d] 0ODT1 WR TERMINATION = %4.2f (%d/%d)", i_port, i_dimm, i_rank, eff_term_wr, i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank], i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt1_rank]); + FAPI_INF("[P%d:D%d:R%d] 0ODT1 WR TERMINATION = %4.2f (%d/%d)", i_port, i_dimm, i_rank, eff_term_wr, i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank], i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt1_rank]); } //------------------------------------------------------------------------------ // 1ODT0 @@ -1651,16 +1648,16 @@ extern "C" { ((i_dimm_rank_odt_wr[i_port][i_dimm][i_rank] & 0x20) != 0) && ((i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt0_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) || + fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE) || (i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)) + fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE)) ) { // dynamic ODT enabled, so use rtt_wr (only if the rank being written to has // it enabled) if ( (i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt0_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) + fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE) && (i_dimm == 1) && (i_rank == ma1odt0_rank) ) @@ -1682,7 +1679,7 @@ extern "C" { } // dynamic ODT disabled, so use rtt_nom else if (i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE) + fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE) { if (eff_term_wr == 0) { @@ -1700,7 +1697,7 @@ extern "C" { } } - FAPI_DBG("[P%d:D%d:R%d] 1ODT0 WR TERMINATION = %4.2f (%d/%d)", i_port, i_dimm, i_rank, eff_term_wr, i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank], i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt0_rank]); + FAPI_INF("[P%d:D%d:R%d] 1ODT0 WR TERMINATION = %4.2f (%d/%d)", i_port, i_dimm, i_rank, eff_term_wr, i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank], i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt0_rank]); } //------------------------------------------------------------------------------ // 1ODT1 @@ -1708,16 +1705,16 @@ extern "C" { ((i_dimm_rank_odt_wr[i_port][i_dimm][i_rank] & 0x10) != 0) && ((i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt1_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) || + fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE) || (i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)) + fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE)) ) { // dynamic ODT enabled, so use rtt_wr (only if the rank being written to has // it enabled) if ( (i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt1_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) + fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE) && (i_dimm == 1) && (i_rank == ma1odt1_rank) ) @@ -1739,7 +1736,7 @@ extern "C" { } // dynamic ODT disabled, so use rtt_nom else if (i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank] != - fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE) + fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE) { if (eff_term_wr == 0) { @@ -1757,7 +1754,7 @@ extern "C" { } } - FAPI_DBG("[P%d:D%d:R%d] 1ODT1 WR TERMINATION = %4.2f (%d/%d)", i_port, i_dimm, i_rank, eff_term_wr, i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank], i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt1_rank]); + FAPI_INF("[P%d:D%d:R%d] 1ODT1 WR TERMINATION = %4.2f (%d/%d)", i_port, i_dimm, i_rank, eff_term_wr, i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank], i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt1_rank]); } @@ -1813,8 +1810,8 @@ extern "C" { (float(ACTIVE_DIMM_UTILIZATION) / 100) * (float(DATA_BUS_WRITE_PERCENT) / 100) * (term_odt_mult_wr)) ); - FAPI_DBG("%s TERM:[P%d:D%d:R%d] CEN[DRV=%d RCV=%d] DRAM[DRV=%d ODT_RD=%4.2f ODT_WR=%4.2f]", i_nom_or_wc_term, i_port, i_dimm, i_rank, cen_dq_dqs_drv_imp_value, i_cen_dq_dqs_rcv_imp[i_port], i_dimm_dram_ron[i_port][i_dimm], eff_term_rd, eff_term_wr); - FAPI_DBG("%s TERM POWER:[P%d:D%d:R%d] RD[Nets=%d EffTerm=%3.2f ODTMult=%1.2f] WR[Nets=%d EffTerm=%3.2f ODTMult=%1.2f] TermPower(%d%%)=%2.2f W", i_nom_or_wc_term, i_port, i_dimm, i_rank, number_nets_term_rd, eff_net_term_rd, term_odt_mult_rd, number_nets_term_wr, eff_net_term_wr, term_odt_mult_wr, ACTIVE_DIMM_UTILIZATION, o_dimm_power_adder_termination); + FAPI_INF("%s TERM:[P%d:D%d:R%d] CEN[DRV=%d RCV=%d] DRAM[DRV=%d ODT_RD=%4.2f ODT_WR=%4.2f]", i_nom_or_wc_term, i_port, i_dimm, i_rank, cen_dq_dqs_drv_imp_value, i_cen_dq_dqs_rcv_imp[i_port], i_dimm_dram_ron[i_port][i_dimm], eff_term_rd, eff_term_wr); + FAPI_INF("%s TERM POWER:[P%d:D%d:R%d] RD[Nets=%d EffTerm=%3.2f ODTMult=%1.2f] WR[Nets=%d EffTerm=%3.2f ODTMult=%1.2f] TermPower(%d%%)=%2.2f W", i_nom_or_wc_term, i_port, i_dimm, i_rank, number_nets_term_rd, eff_net_term_rd, term_odt_mult_rd, number_nets_term_wr, eff_net_term_wr, term_odt_mult_wr, ACTIVE_DIMM_UTILIZATION, o_dimm_power_adder_termination); } else { diff --git a/src/usr/hwpf/hwp/memory_attributes.xml b/src/usr/hwpf/hwp/memory_attributes.xml index ebf0d7f8c..1100f9e9f 100644 --- a/src/usr/hwpf/hwp/memory_attributes.xml +++ b/src/usr/hwpf/hwp/memory_attributes.xml @@ -21,7 +21,7 @@ <!-- --> <!-- IBM_PROLOG_END_TAG --> <attributes> -<!-- $Id: memory_attributes.xml,v 1.88 2013/09/04 18:03:12 bellows Exp $ --> +<!-- $Id: memory_attributes.xml,v 1.98 2013/11/16 09:42:47 bellows Exp $ --> <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB --> <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP --> <!-- *********************************************************************** --> @@ -2038,6 +2038,7 @@ creator: mss_eff_cnfg consumer: various firmware notes: none</description> <valueType>uint8</valueType> + <enum>PG0 = 0, PG1 = 1, PG2 = 2, PG3 = 3</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -2065,7 +2066,7 @@ creator: mss_eff_cnfg consumer: various firmware notes: none</description> <valueType>uint8</valueType> - <enum>ENABLE = 0, DISABLE = 1</enum> + <enum>DISABLE = 0, ENABLE = 1</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -2079,7 +2080,7 @@ creator: mss_eff_cnfg consumer: various firmware notes: none</description> <valueType>uint8</valueType> - <enum>ENABLE = 0, DISABLE = 1</enum> + <enum>DISABLE = 0, ENABLE = 1</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -2093,7 +2094,7 @@ creator: mss_eff_cnfg consumer: various firmware notes: none</description> <valueType>uint8</valueType> - <enum>FIXED_2X = 0, FIXED_4X = 1, FLY_2X = 2, FLY_4X = 3, NORMAL = 4</enum> + <enum>NORMAL = 0, FIXED_2X = 1, FIXED_4X = 2, FLY_2X = 5, FLY_4X = 6</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -2107,7 +2108,7 @@ creator: mss_eff_cnfg consumer: various firmware notes: none</description> <valueType>uint8</valueType> - <enum>4NCK = 0, 5NCK = 2, 6NCK = 3</enum> + <enum>4NCK = 4, 5NCK = 5, 6NCK = 6</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -2135,7 +2136,7 @@ creator: mss_eff_cnfg consumer: various firmware notes: none</description> <valueType>uint8</valueType> - <enum>ENABLE = 0, DISABLE = 1</enum> + <enum>DISABLE = 0, ENABLE = 1</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -2163,7 +2164,7 @@ creator: mss_eff_cnfg consumer: various firmware notes: none</description> <valueType>uint8</valueType> - <enum>ENABLE = 0, DISABLE = 1</enum> + <enum>DISABLE = 0, ENABLE = 1</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -2177,7 +2178,7 @@ creator: mss_eff_cnfg consumer: various firmware notes: none</description> <valueType>uint8</valueType> - <enum>ENABLE = 0, DISABLE = 1</enum> + <enum>DISABLE = 0, ENABLE = 1</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -2191,6 +2192,7 @@ creator: mss_eff_cnfg consumer: various firmware notes: none</description> <valueType>uint8</valueType> + <enum>DISABLE = 0, 3CYC = 3, 4CYC = 4, 5CYC = 5, 6CYC = 6, 8CYC = 8</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -2204,7 +2206,7 @@ creator: mss_eff_cnfg consumer: various firmware notes: none</description> <valueType>uint8</valueType> - <enum>ENABLE = 0, DISABLE = 1</enum> + <enum>DISABLE = 0, ENABLE = 1</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -2218,7 +2220,7 @@ creator: mss_eff_cnfg consumer: various firmware notes: none</description> <valueType>uint8</valueType> - <enum>ENABLE = 0, DISABLE = 1</enum> + <enum>DISABLE = 0, ENABLE = 1</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -2232,7 +2234,7 @@ creator: mss_eff_cnfg consumer: various firmware notes: none</description> <valueType>uint8</valueType> - <enum>1NCLK = 0, 2NCLK = 1</enum> + <enum>1NCLK = 1, 2NCLK = 2</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -2246,7 +2248,7 @@ creator: mss_eff_cnfg consumer: various firmware notes: none</description> <valueType>uint8</valueType> - <enum>1NCLK = 0, 2NCLK = 1</enum> + <enum>1NCLK = 1, 2NCLK = 2</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -2260,7 +2262,7 @@ creator: mss_eff_cnfg consumer: various firmware notes: none</description> <valueType>uint8</valueType> - <enum>DISABLE = 0</enum> + <enum>DISABLE = 0, PL4 = 4, PL5 = 5, PL6 = 6, PL8 = 8</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -2274,7 +2276,7 @@ creator: mss_eff_cnfg consumer: various firmware notes: none</description> <valueType>uint8</valueType> - <enum>ERROR = 0, CLEAR = 1</enum> + <enum>CLEAR = 0, ERROR = 1</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -2288,7 +2290,7 @@ creator: mss_eff_cnfg consumer: various firmware notes: none</description> <valueType>uint8</valueType> - <enum>ERROR = 0, CLEAR = 1</enum> + <enum>CLEAR = 0, ERROR = 1</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -2302,7 +2304,7 @@ creator: mss_eff_cnfg consumer: various firmware notes: none</description> <valueType>uint8</valueType> - <enum>ACTIVATED = 0, DEACTIVATED = 1</enum> + <enum>DEACTIVATED = 0, ACTIVATED = 1</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -2316,7 +2318,7 @@ creator: mss_eff_cnfg consumer: various firmware notes: none</description> <valueType>uint8</valueType> - <enum>DISABLE = 0, 60OHM = 1, 40OHM = 2, 120OHM = 3, 240OHM = 4, 48OHM = 5, 80OHM = 6, 34OHM = 7</enum> + <enum>DISABLE = 0, 60OHM = 60, 120OHM = 120, 40OHM = 40, 240OHM = 240, 48OHM = 48, 80OHM = 80, 34OHM = 34</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -2331,7 +2333,7 @@ creator: mss_eff_cnfg consumer: various firmware notes: none</description> <valueType>uint8</valueType> - <enum>ENABLE = 0, DISABLE = 1</enum> + <enum>DISABLE = 0, ENABLE = 1</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -2416,7 +2418,7 @@ Creator: mss_eff_cnfg Consumer:various Firmware notes: none</description> <valueType>uint8</valueType> - <enum>ENABLE = 0, DISABLE = 1</enum> + <enum>DISABLE = 0, ENABLE = 1</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -2431,6 +2433,7 @@ Creator: mss_eff_cnfg Consumer:various Firmware notes: none</description> <valueType>uint8</valueType> + <enum>4NCK = 4, 5NCK = 5, 6NCK = 6, 7NCK = 7, 8NCK = 8</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -2439,12 +2442,12 @@ Firmware notes: none</description> <attribute> <id>ATTR_EFF_WRITE_CRC</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Write CRC control for DDR4. Set in mss_eff_cnfg. Each memory channel will have a value. + <description>Write CRC control for DDR4 in MRS2. Set in mss_eff_cnfg. Each memory channel will have a value. Creator: mss_eff_cnfg Consumer:various Firmware notes: none</description> <valueType>uint8</valueType> - <enum>ENABLE = 0, DISABLE = 1</enum> + <enum>DISABLE = 0, ENABLE = 1</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -3569,77 +3572,7 @@ will originates from VPD for custom DIMMs in the MW keyword byte 5 (MSB is on th <odmChangeable/> </attribute> -<!-- TODO: RTC 82331 - Add this attribute to the Accessor HWP -<attribute> - <id>ATTR_VPD_CKE_PRI_MAP</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>This value comes from the VPD keyword MT bytes 54 and 55 MT(54:55) for the Logical DIMM associated with port A. Bytes 118:119 for port B, 182:183 for port C and 246:247 for port D. In the end, the AB and CD portions form a 32 bit word for each mba to write into the corresponding ddrphy register</description> - <valueType>uint32</valueType> - <platInit/> - <odmVisable/> - <array>2</array> -</attribute> - -<attribute> - <id>ATTR_VPD_CKE_PWR_MAP</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>This value comes from the VPD keyword MT bytes 56 to 59 MT(56:59) for the Logical DIMM associated with port A. Bytes 120:123 for port B, 184:187 for port C and 248:251 for port D</description> - <valueType>uint32</valueType> - <platInit/> - <odmVisable/> - <array>2</array> -</attribute> - -<attribute> - <id>ATTR_VPD_GPO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>This value comes from the VPD keyword MT bytes 61 MT(61) for the Logical DIMM associated with port A. Bytes 125 for port B, 189 for port C and 253 for port D</description> - <valueType>uint8</valueType> - <platInit/> - <odmVisable/> - <array>2</array> -</attribute> - -<attribute> - <id>ATTR_VPD_RLO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>This value comes from the VPD keyword MT byte 60 bits 4:7 for the Logical DIMM associated with port A. Byte 124 bits 4:7 for port B, 188 bits 4:7 for port C and 252 bits 4:7 for port D</description> - <valueType>uint8</valueType> - <platInit/> - <odmVisable/> - <array>2</array> -</attribute> - -<attribute> - <id>ATTR_VPD_WLO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>This value comes from the VPD keyword MT byte 60 bits 0:3 for the Logical DIMM associated with port A. Byte 124 bits 0:3 for port B, 188 bits 0:3 for port C and 252 bits 0:3 for port D</description> - <valueType>uint8</valueType> - <platInit/> - <odmVisable/> - <array>2</array> -</attribute> - -<attribute> - <id>ATTR_VPD_TSYS_ADR</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>This value comes from the VPD MR keyword byte 49 for ports A and B and byte 177 for port C and D. This means that all ADR blocks use this value on an mba level</description> - <valueType>uint8</valueType> - <platInit/> - <odmVisable/> - <array>2</array> -</attribute> - -<attribute> - <id>ATTR_VPD_TSYS_DP18</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>This value comes from the VPD MR keyword byte 113 for ports A and B and byte 241 for port C and D. This means all DP18 blocks use this value on a mba level</description> - <valueType>uint8</valueType> - <platInit/> - <odmVisable/> - <array>2</array> -</attribute> - +<!-- TODO: Mark Bellows is to remove these obsoleted attributes <attribute> <id>ATTR_VPD_MT_CKE_PRI_MAP</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> @@ -3712,117 +3645,79 @@ will originates from VPD for custom DIMMs in the MW keyword byte 5 (MSB is on th --> <attribute> - <id>ATTR_VPD_CKE_PRI_MAP</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>This value comes from the VPD keyword MT bytes 54 and 55 MT(54:55) for the Logical DIMM associated with port A. Bytes 118:119 for port B, 182:183 for port C and 246:247 for port D. In the end, the AB and CD portions form a 32 bit word for each mba to write into the corresponding ddrphy register</description> - <valueType>uint32</valueType> - <platInit/> - <odmVisable/> - <array>2</array> -</attribute> - -<attribute> - <id>ATTR_VPD_CKE_PWR_MAP</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>This value comes from the VPD keyword MT bytes 56 to 59 MT(56:59) for the Logical DIMM associated with port A. Bytes 120:123 for port B, 184:187 for port C and 248:251 for port D</description> - <valueType>uint32</valueType> - <platInit/> - <odmVisable/> - <array>2</array> -</attribute> - -<attribute> - <id>ATTR_VPD_GPO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>This value comes from the VPD keyword MT bytes 61 MT(61) for the Logical DIMM associated with port A. Bytes 125 for port B, 189 for port C and 253 for port D</description> - <valueType>uint8</valueType> - <platInit/> - <odmVisable/> - <array>2</array> -</attribute> - -<attribute> - <id>ATTR_VPD_RLO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>This value comes from the VPD keyword MT byte 60 bits 4:7 for the Logical DIMM associated with port A. Byte 124 bits 4:7 for port B, 188 bits 4:7 for port C and 252 bits 4:7 for port D</description> - <valueType>uint8</valueType> - <platInit/> - <odmVisable/> - <array>2</array> -</attribute> - -<attribute> - <id>ATTR_VPD_WLO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>This value comes from the VPD keyword MT byte 60 bits 0:3 for the Logical DIMM associated with port A. Byte 124 bits 0:3 for port B, 188 bits 0:3 for port C and 252 bits 0:3 for port D</description> + <id>ATTR_LAB_USE_JTAG_MODE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>This attribute controls how the procedures operate in JTAG mode under an environment called cronus flex. For normal operation, this attribute should be set to FALSE. Platforms should initialize this attribute to FALSE.</description> <valueType>uint8</valueType> + <enum>FALSE =0, TRUE = 1</enum> <platInit/> <odmVisable/> - <array>2</array> </attribute> <attribute> - <id>ATTR_VPD_TSYS_ADR</id> + <id>ATTR_MCBIST_RANDOM_SEED_VALUE</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>This value comes from the VPD MR keyword byte 49 for ports A and B and byte 177 for port C and D. This means that all ADR blocks use this value on an mba level</description> - <valueType>uint8</valueType> - <platInit/> + <description>Controls the MCBIST engine in the centaur chip. The value will be set in mss_eff_config_shmoo.</description> + <valueType>uint32</valueType> + <writeable/> <odmVisable/> - <array>2</array> + <odmChangeable/> </attribute> <attribute> - <id>ATTR_VPD_TSYS_DP18</id> + <id>ATTR_MCBIST_RANDOM_SEED_TYPE</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>This value comes from the VPD MR keyword byte 113 for ports A and B and byte 241 for port C and D. This means all DP18 blocks use this value on a mba level</description> + <description>Controls the MCBIST engine in the centaur chip. The value will be set in mss_eff_config_shmoo.</description> <valueType>uint8</valueType> - <platInit/> + <writeable/> <odmVisable/> - <array>2</array> + <odmChangeable/> </attribute> +<!-- NOT USED YET BY PROCEDURES <attribute> - <id>ATTR_LAB_USE_JTAG_MODE</id> + <id>ATTR_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT</id> <targetType>TARGET_TYPE_SYSTEM</targetType> - <description>This attribute controls how the procedures operate in JTAG mode under an environment called cronus flex. For normal operation, this attribute should be set to FALSE. Platforms should initialize this attribute to FALSE.</description> + <description>Machine Readable Workbook DIMM power curve percent uplift for this system</description> <valueType>uint8</valueType> - <enum>FALSE =0, TRUE = 1</enum> <platInit/> <odmVisable/> + <persistRuntime/> </attribute> <attribute> - <id>ATTR_MSS_CONTROL_SWITCH</id> + <id>ATTR_MRW_MEM_THROTTLE_DENOMINATOR</id> <targetType>TARGET_TYPE_SYSTEM</targetType> - <description>This attribute enables control switches in the memory code. This is a one hot vector: Bit 7 controls the Bad Bit Mask function in draminit_training. The platform should initialize this to BBM_ON except if ATTR_LAB_USE_JTAG_MODE == TRUE, then the platform should set this attribute to BBM_ OFF.</description> - <valueType>uint8</valueType> - <enum>BBM_ON = 0x01, BBM_OFF = 0x00 </enum> + <description>Machine Readable Workbook throttle value for denominator cfg_nm_m</description> + <valueType>uint32</valueType> <platInit/> - <writeable/> <odmVisable/> - <odmChangeable/> + <persistRuntime/> </attribute> <attribute> - <id>ATTR_MCBIST_RANDOM_SEED_VALUE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Controls the MCBIST engine in the centaur chip. The value will be set in mss_eff_config_shmoo.</description> + <id>ATTR_MRW_MAX_DRAM_DATABUS_UTIL</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Machine Readable Workbook value for maximum dram data bus utilization in centi percent (c%). Used to determine memory throttle values.</description> <valueType>uint32</valueType> - <writeable/> + <platInit/> <odmVisable/> - <odmChangeable/> + <persistRuntime/> </attribute> +--> <attribute> - <id>ATTR_MCBIST_RANDOM_SEED_TYPE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Controls the MCBIST engine in the centaur chip. The value will be set in mss_eff_config_shmoo.</description> + <id>ATTR_MSS_INIT_STATE</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>How far into the ipl istep the centaur has been brought up</description> + <enum>COLD = 0, CLOCKS_ON = 1, DMI_ACTIVE = 2</enum> <valueType>uint8</valueType> <writeable/> <odmVisable/> <odmChangeable/> </attribute> + <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB --> <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP --> </attributes> diff --git a/src/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.C b/src/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.C index c1d722930..7b2fef9b6 100644 --- a/src/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.C +++ b/src/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_maint_cmds.C,v 1.28 2013/10/31 20:42:54 gollub Exp $ +// $Id: mss_maint_cmds.C,v 1.29 2013/12/02 18:58:05 bellows Exp $ //------------------------------------------------------------------------------ // Don't forget to create CVS comments when you check in your changes! //------------------------------------------------------------------------------ @@ -82,6 +82,7 @@ // | | | ENABLE_CMD_COMPLETE_ATTENTION_ON_CLEAN_AND_ERROR // | | | DD2: enable (fixed) // | | | DD1: disable (broken) +// 1.29 | 11/19/13 | bellows | Swapped to use ATTR_VPD_DIMM_SPARE //------------------------------------------------------------------------------ @@ -4632,7 +4633,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, // l_spare_dram[port][dimm][rank] // NO_SPARE = 0, LOW_NIBBLE = 1, HIGH_NIBBLE = 2, FULL_BYTE = 3 // NOTE: Typically will same value for whole Centaur. - l_rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_SPARE, &i_target, l_spare_dram); + l_rc = FAPI_ATTR_GET(ATTR_VPD_DIMM_SPARE, &i_target, l_spare_dram); if(l_rc) { FAPI_ERR("Error reading attribute to see if spare exists on %s.",i_target.toEcmdString()); diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index 8ac65ba97..7fb5cbcc3 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -12759,4 +12759,19 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <readable/> </attribute> +<attribute> + <id>MSS_INIT_STATE</id> + <description>How far into the ipl istep the centaur has been brought up</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_INIT_STATE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + </attributes> diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index c5c2a3ba0..8d7595259 100644 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -1194,6 +1194,7 @@ <attribute><id>CDIMM_SENSOR_MAP_SECONDARY</id></attribute> <attribute><id>MSS_BLUEWATERFALL_BROKEN</id></attribute> <attribute><id>DMI_DFE_OVERRIDE</id></attribute> + <attribute><id>MSS_INIT_STATE</id></attribute> </targetType> <!-- Centaur L4 --> |
