diff options
| -rw-r--r-- | src/usr/isteps/istep12/call_cen_set_inband_addr.C | 310 | ||||
| -rw-r--r-- | src/usr/targeting/common/xmltohb/target_types_hb.xml | 3 |
2 files changed, 191 insertions, 122 deletions
diff --git a/src/usr/isteps/istep12/call_cen_set_inband_addr.C b/src/usr/isteps/istep12/call_cen_set_inband_addr.C index d26bcbd83..508729332 100644 --- a/src/usr/isteps/istep12/call_cen_set_inband_addr.C +++ b/src/usr/isteps/istep12/call_cen_set_inband_addr.C @@ -44,14 +44,14 @@ #include <util/utilmbox_scratch.H> #include <util/misc.H> -//HWP -#include <p9c_set_inband_addr.H> - -#include <expupd/expupd.H> - #ifdef CONFIG_AXONE +// Axone HWPs #include <exp_omi_init.H> #include <p9a_omi_init.H> +#include <expupd/expupd.H> +#else +// Cumulus HWP +#include <p9c_set_inband_addr.H> #endif //Inband SCOM @@ -62,167 +62,216 @@ using namespace ISTEP_ERROR; using namespace ERRORLOG; using namespace TARGETING; - namespace ISTEP_12 { +void cumulus_call_cen_set_inband_addr(IStepError & io_istepError); +void axone_call_cen_set_inband_addr(IStepError & io_istepError); +void enableInbandScomsOCMB( TARGETING::TargetHandleList i_ocmbTargetList ); + void* call_cen_set_inband_addr (void *io_pArgs) { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr entry" ); IStepError l_StepError; - errlHndl_t l_err = NULL; auto l_procModel = TARGETING::targetService().getProcessorModel(); - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr entry" ); - - if(l_procModel == TARGETING::MODEL_CUMULUS) + switch (l_procModel) { - TARGETING::TargetHandleList l_procTargetList; - getAllChips(l_procTargetList, TYPE_PROC); + case TARGETING::MODEL_CUMULUS: + cumulus_call_cen_set_inband_addr(l_StepError); + // @todo RTC 187913 inband centaur scom in P9 + // Re-enable when support available in simics + if ( Util::isSimicsRunning() == false ) + { + //Now enable Inband SCOM for all memory mapped chips. + IBSCOM::enableInbandScoms(); + } + break; + case TARGETING::MODEL_AXONE: + axone_call_cen_set_inband_addr(l_StepError); + break; + case TARGETING::MODEL_NIMBUS: + break; // do nothing step + default: + assert(0, "call_cen_set_inband_addr: Unsupported model type 0x%04X", + l_procModel); + break; + } - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr: %d proc chips found", - l_procTargetList.size()); + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr exit" ); - for (const auto & l_proc_target : l_procTargetList) - { + // end task, returning any errorlogs to IStepDisp + return l_StepError.getErrorHandle(); +} - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "p9c_set_inband_addr HWP target HUID %.8x", - TARGETING::get_huid(l_proc_target)); +#ifndef CONFIG_AXONE +void cumulus_call_cen_set_inband_addr(IStepError & io_istepError) +{ + errlHndl_t l_err = nullptr; + TARGETING::TargetHandleList l_procTargetList; + getAllChips(l_procTargetList, TYPE_PROC); - // call the HWP with each target - fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_proc_target - (l_proc_target); + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr: %d proc chips found", + l_procTargetList.size()); - FAPI_INVOKE_HWP(l_err, p9c_set_inband_addr, l_fapi_proc_target); + for (const auto & l_proc_target : l_procTargetList) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "p9c_set_inband_addr HWP target HUID %.8x", + TARGETING::get_huid(l_proc_target)); - // process return code. - if ( l_err ) - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9c_set_inband_addr HWP on target HUID %.8x", - l_err->reasonCode(), TARGETING::get_huid(l_proc_target) ); + // call the HWP with each target + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_proc_target + (l_proc_target); - // capture the target data in the elog - ErrlUserDetailsTarget(l_proc_target).addToLog( l_err ); + FAPI_INVOKE_HWP(l_err, p9c_set_inband_addr, l_fapi_proc_target); - // Create IStep error log and cross reference to error that occurred - l_StepError.addErrorDetails( l_err ); + // process return code. + if ( l_err ) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: p9c_set_inband_addr HWP on target HUID %.8x", + l_err->reasonCode(), TARGETING::get_huid(l_proc_target) ); - // Commit Error - errlCommit( l_err, ISTEP_COMP_ID ); + // capture the target data in the elog + ErrlUserDetailsTarget(l_proc_target).addToLog( l_err ); - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : p9c_set_inband_addr HWP"); - } + // Create IStep error log and cross reference to error that occurred + io_istepError.addErrorDetails( l_err ); + + // Commit Error + errlCommit( l_err, ISTEP_COMP_ID ); } - } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : p9c_set_inband_addr HWP"); + } + } // proc target loop +} - // @todo RTC 187913 inband centaur scom in P9 - // Re-enable when support available in simics - if ( Util::isSimicsRunning() == false ) - { - //Now enable Inband SCOM for all membuf chips. - IBSCOM::enableInbandScoms(); - } +void axone_call_cen_set_inband_addr(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'exp_omi_init/p9a_omi_init' but Axone code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} -#ifdef CONFIG_AXONE - if(l_procModel == TARGETING::MODEL_AXONE) - { +void enableInbandScomsOCMB( TARGETING::TargetHandleList l_ocmbTargetList ) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'enableInbandScomsOCMB' but Axone code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} - TARGETING::TargetHandleList l_ocmbTargetList; - getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP); +#else - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr: %d ocmb chips found", - l_ocmbTargetList.size()); +void cumulus_call_cen_set_inband_addr(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'p9c_set_inband_addr' but Cumulus code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} - for (const auto & l_ocmb_target : l_ocmbTargetList) - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "exp_omi_init HWP target HUID %.8x", - TARGETING::get_huid(l_ocmb_target)); +void axone_call_cen_set_inband_addr(IStepError & io_istepError) +{ + errlHndl_t l_err = nullptr; + TARGETING::TargetHandleList l_ocmbTargetList; + getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP); + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "axone_call_cen_set_inband_addr: %d ocmb chips found", + l_ocmbTargetList.size()); + + for (const auto & l_ocmb_target : l_ocmbTargetList) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "exp_omi_init HWP target HUID %.8x", + TARGETING::get_huid(l_ocmb_target) ); - // call the HWP with each target - fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi_ocmb_target - (l_ocmb_target); + // call the HWP with each target + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi_ocmb_target + (l_ocmb_target); - FAPI_INVOKE_HWP(l_err, exp_omi_init , l_fapi_ocmb_target); + FAPI_INVOKE_HWP(l_err, exp_omi_init , l_fapi_ocmb_target); - // process return code. - if ( l_err ) - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + // process return code. + if ( l_err ) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, ERR_MRK "ERROR 0x%.8X: exp_omi_init HWP on target HUID 0x%.8x", l_err->reasonCode(), TARGETING::get_huid(l_ocmb_target) ); - // capture the target data in the elog - ErrlUserDetailsTarget(l_ocmb_target).addToLog( l_err ); + // capture the target data in the elog + ErrlUserDetailsTarget(l_ocmb_target).addToLog( l_err ); - // Create IStep error log and cross reference to error that occurred - l_StepError.addErrorDetails( l_err ); - - // Commit Error - errlCommit( l_err, ISTEP_COMP_ID ); - - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : exp_omi_init HWP on target HUID 0x%.8x", - TARGETING::get_huid(l_ocmb_target)); - } + // Create IStep error log and cross reference to error that occurred + io_istepError.addErrorDetails( l_err ); + // Commit Error + errlCommit( l_err, ISTEP_COMP_ID ); } - - TARGETING::TargetHandleList l_mccTargetList; - getAllChiplets(l_mccTargetList, TYPE_MCC); - - for (const auto & l_mcc_target : l_mccTargetList) + else { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "p9a_omi_init HWP target HUID %.8x", - TARGETING::get_huid(l_mcc_target)); + "SUCCESS : exp_omi_init HWP on target HUID 0x%.8x", + TARGETING::get_huid(l_ocmb_target) ); + } + } // ocmb loop - // call the HWP with each target - fapi2::Target<fapi2::TARGET_TYPE_MCC> l_fapi_mcc_target - (l_mcc_target); + TargetHandleList l_mccTargetList; + getAllChiplets(l_mccTargetList, TYPE_MCC); - FAPI_INVOKE_HWP(l_err, p9a_omi_init, l_fapi_mcc_target); + for (const auto & l_mcc_target : l_mccTargetList) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "p9a_omi_init HWP target HUID %.8x", + TARGETING::get_huid(l_mcc_target) ); - // process return code. - if ( l_err ) - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9a_omi_init HWP on target HUID %.8x", - l_err->reasonCode(), TARGETING::get_huid(l_mcc_target) ); + // call the HWP with each target + fapi2::Target<fapi2::TARGET_TYPE_MCC> l_fapi_mcc_target + (l_mcc_target); - // capture the target data in the elog - ErrlUserDetailsTarget(l_mcc_target).addToLog( l_err ); + FAPI_INVOKE_HWP(l_err, p9a_omi_init, l_fapi_mcc_target); - // Create IStep error log and cross reference to error that occurred - l_StepError.addErrorDetails( l_err ); + // process return code. + if ( l_err ) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, ERR_MRK + "ERROR 0x%.8X: p9a_omi_init HWP on target HUID %.8x", + l_err->reasonCode(), TARGETING::get_huid(l_mcc_target) ); - // Commit Error - errlCommit( l_err, ISTEP_COMP_ID ); + // capture the target data in the elog + ErrlUserDetailsTarget(l_mcc_target).addToLog( l_err ); - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : p9a_omi_init HWP on target HUID 0x%.8x", - TARGETING::get_huid(l_mcc_target)); - } + // Create IStep error log and cross reference to error that occurred + io_istepError.addErrorDetails( l_err ); + // Commit Error + errlCommit( l_err, ISTEP_COMP_ID ); } - } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : p9a_omi_init HWP on target HUID 0x%.8x ," + "setting scom settings to use inband for all ocmb children", + TARGETING::get_huid(l_mcc_target)); + + TargetHandleList l_ocmbTargetList; + getChildAffinityTargets(l_ocmbTargetList , l_mcc_target, + CLASS_CHIP, TARGETING::TYPE_OCMB_CHIP); + enableInbandScomsOCMB(l_ocmbTargetList); + } + } // MCC loop // Check if any explorer chips require a firmware update and update them // (skipped on MPIPL) + // We should be checking for updates and perform the updates even if OMI + // initialization failed. It's possible that the OMI failure was due to + // the OCMB having an old image. The update code will automatically + // switch to using i2c if OMI is not enabled. Target* l_pTopLevel = nullptr; targetService().getTopLevelTarget( l_pTopLevel ); - assert(l_pTopLevel, "call_cen_set_inband_addr: no TopLevelTarget"); + assert(l_pTopLevel, "axone_call_cen_set_inband_addr: no TopLevelTarget"); if (l_pTopLevel->getAttr<TARGETING::ATTR_IS_MPIPL_HB>()) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, @@ -230,17 +279,34 @@ void* call_cen_set_inband_addr (void *io_pArgs) } else { - expupd::updateAll(l_StepError); + expupd::updateAll(io_istepError); } +} -#endif // CONFIG_AXONE - +/** + * @brief Enable Inband Scom for the OCMB targets + * @param i_ocmbTargetList - OCMB targets + */ +void enableInbandScomsOCMB( TARGETING::TargetHandleList i_ocmbTargetList ) +{ + mutex_t* l_mutex = NULL; - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr exit" ); + for ( const auto & l_ocmb : i_ocmbTargetList ) + { + //don't mess with attributes without the mutex (just to be safe) + l_mutex = l_ocmb->getHbMutexAttr<TARGETING::ATTR_IBSCOM_MUTEX>(); + mutex_lock(l_mutex); - // end task, returning any errorlogs to IStepDisp - return l_StepError.getErrorHandle(); + ScomSwitches l_switches = l_ocmb->getAttr<ATTR_SCOM_SWITCHES>(); + l_switches.useI2cScom = 0; + l_switches.useInbandScom = 1; + // Modify attribute + l_ocmb->setAttr<ATTR_SCOM_SWITCHES>(l_switches); + mutex_unlock(l_mutex); + } } +#endif // CONFIG_AXONE + }; diff --git a/src/usr/targeting/common/xmltohb/target_types_hb.xml b/src/usr/targeting/common/xmltohb/target_types_hb.xml index bd9c7d165..93e0bf912 100644 --- a/src/usr/targeting/common/xmltohb/target_types_hb.xml +++ b/src/usr/targeting/common/xmltohb/target_types_hb.xml @@ -87,6 +87,9 @@ <targetTypeExtension> <id>chip-ocmb</id> <attribute> + <id>IBSCOM_MUTEX</id> + </attribute> + <attribute> <default>0</default> <id>MMIO_VM_ADDR</id> </attribute> |
